2 * Ralink RT288x SoC specific setup
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Ralink's 2.6.21 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
20 #include <asm/mips_machine.h>
21 #include <asm/reboot.h>
24 #include <asm/mach-ralink/common.h>
25 #include <asm/mach-ralink/rt288x.h>
26 #include <asm/mach-ralink/rt288x_regs.h>
29 static void rt288x_restart(char *command)
31 rt288x_sysc_wr(RT2880_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
37 static void rt288x_halt(void)
43 unsigned int __cpuinit get_c0_compare_irq(void)
45 return CP0_LEGACY_COMPARE_IRQ;
48 void __init ramips_soc_setup(void)
52 rt288x_sysc_base = ioremap_nocache(RT2880_SYSC_BASE, RT2880_SYSC_SIZE);
53 rt288x_memc_base = ioremap_nocache(RT2880_MEMC_BASE, RT2880_MEMC_SIZE);
57 clk = clk_get(NULL, "cpu");
59 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
61 printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
62 clk_get_rate(clk) / 1000000,
63 (clk_get_rate(clk) % 1000000) * 100 / 1000000);
65 _machine_restart = rt288x_restart;
66 _machine_halt = rt288x_halt;
67 pm_power_off = rt288x_halt;
69 clk = clk_get(NULL, "uart");
71 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
73 ramips_early_serial_setup(0, RT2880_UART0_BASE, clk_get_rate(clk),
74 RT2880_INTC_IRQ_UART0);
75 ramips_early_serial_setup(1, RT2880_UART1_BASE, clk_get_rate(clk),
76 RT2880_INTC_IRQ_UART1);
79 void __init plat_time_init(void)
83 clk = clk_get(NULL, "cpu");
85 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
87 mips_hpt_frequency = clk_get_rate(clk) / 2;