4 /*******************************************************************************
6 * Copyright 2002 Integrated Device Technology, Inc.
9 * DDR register definition.
11 * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
13 * Author : ryan.holmQVist@idt.com
17 * Revision 1.2 2002/06/06 18:34:03 astichte
18 * Added XXX_PhysicalAddress and XXX_VirtualAddress
20 * Revision 1.1 2002/05/29 17:33:21 sysarch
21 * jba File moved from vcode/include/idt/acacia
24 ******************************************************************************/
28 DDR0_PhysicalAddress = 0x18018000,
29 DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
31 DDR0_VirtualAddress = 0xb8018000,
32 DDR_VirtualAddress = DDR0_VirtualAddress, // Default
52 DDR0BASE_baseaddr_b = 16,
53 DDR0BASE_baseaddr_m = 0xffff0000,
56 DDR0MASK_mask_m = 0xffff0000,
58 DDR1BASE_baseaddr_b = 16,
59 DDR1BASE_baseaddr_m = 0xffff0000,
62 DDR1MASK_mask_m = 0xffff0000,
65 DDRC_ata_m = 0x000000E0,
67 DDRC_dbw_m = 0x00000100,
69 DDRC_wr_m = 0x00000600,
71 DDRC_ps_m = 0x00001800,
73 DDRC_dtype_m = 0x0000e000,
75 DDRC_rfc_m = 0x000f0000,
77 DDRC_rp_m = 0x00300000,
79 DDRC_ap_m = 0x00400000,
81 DDRC_rcd_m = 0x01800000,
83 DDRC_cl_m = 0x06000000,
85 DDRC_dbm_m = 0x08000000,
87 DDRC_sds_m = 0x10000000,
89 DDRC_atp_m = 0x60000000,
91 DDRC_re_m = 0x80000000,
94 DDRRDC_ces_m = 0x00000001,
96 DDRRDC_ace_m = 0x00000002,
98 DDRABASE_baseaddr_b = 16,
99 DDRABASE_baseaddr_m = 0xffff0000,
101 DDRAMASK_mask_b = 16,
102 DDRAMASK_mask_m = 0xffff0000,
105 DDRAMAP_map_m = 0xffff0000,
108 DDRCUST_cs_m = 0x00000003,
110 DDRCUST_we_m = 0x00000004,
112 DDRCUST_ras_m = 0x00000008,
114 DDRCUST_cas_m = 0x00000010,
116 DDRCUST_cke_m = 0x00000020,
118 DDRCUST_ba_m = 0x000000c0,
121 RCOUNT_rcount_m = 0x0000ffff,
123 RCOMPARE_rcompare_b = 0,
124 RCOMPARE_rcompare_m = 0x0000ffff,
127 RTC_ce_m = 0x00000001,
129 RTC_to_m = 0x00000002,
131 RTC_rqe_m = 0x00000004,
134 DDRDQSC_dm_m = 0x00000003,
136 DDRDQSC_dqsbs_m = 0x000000fc,
138 DDRDQSC_db_m = 0x00000100,
140 DDRDQSC_dbsp_m = 0x01fffe00,
142 DDRDQSC_bdp_m = 0x7e000000,
145 DDRDLLC_eao_m = 0x00000001,
147 DDRDLLC_eo_m = 0x0000003e,
149 DDRDLLC_fs_m = 0x000000c0,
151 DDRDLLC_as_m = 0x00000700,
153 DDRDLLC_sp_m = 0x001ff800,
156 DDRDLLFC_men_m = 0x00000001,
158 DDRDLLFC_aen_m = 0x00000002,
160 DDRDLLFC_ff_m = 0x00000004,
163 DDRDLLTA_addr_m = 0xfffffffc,
166 DDRDLLED_dbe_m = 0x00000001,
168 DDRDLLED_dte_m = 0x00000002,
173 #endif // __IDT_DDR_H__