target/linux/s3c24xx/patches-2.6.28/001-merge-openmoko.patch

   1 Merge OpenMoko kernel patches
   2 git://git.openmoko.org/git/kernel.git#andy-tracking
   3
   4 mb@homer   Thu Jan  1 22:58:51 UTC 2009
   5
   6 ---
   7
   8 Index: linux-2.6.28/arch/arm/common/vic.c
   9 ===================================================================
  10 --- linux-2.6.28.orig/arch/arm/common/vic.c     2008-12-25 00:26:37.000000000 +0100
  11 +++ linux-2.6.28/arch/arm/common/vic.c  2009-01-02 00:01:56.000000000 +0100
  12 @@ -69,12 +69,12 @@ void __init vic_init(void __iomem *base,
  13         /*
  14          * Make sure we clear all existing interrupts
  15          */
  16 -       writel(0, base + VIC_VECT_ADDR);
  17 +       writel(0, base + VIC_PL190_VECT_ADDR);
  18         for (i = 0; i < 19; i++) {
  19                 unsigned int value;
  20
  21 -               value = readl(base + VIC_VECT_ADDR);
  22 -               writel(value, base + VIC_VECT_ADDR);
  23 +               value = readl(base + VIC_PL190_VECT_ADDR);
  24 +               writel(value, base + VIC_PL190_VECT_ADDR);
  25         }
  26
  27         for (i = 0; i < 16; i++) {
  28 @@ -82,7 +82,7 @@ void __init vic_init(void __iomem *base,
  29                 writel(VIC_VECT_CNTL_ENABLE | i, reg);
  30         }
  31
  32 -       writel(32, base + VIC_DEF_VECT_ADDR);
  33 +       writel(32, base + VIC_PL190_DEF_VECT_ADDR);
  34
  35         for (i = 0; i < 32; i++) {
  36                 unsigned int irq = irq_start + i;
  37 Index: linux-2.6.28/arch/arm/configs/gta02-moredrivers-defconfig
  38 ===================================================================
  39 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  40 +++ linux-2.6.28/arch/arm/configs/gta02-moredrivers-defconfig   2009-01-02 00:01:56.000000000 +0100
  41 @@ -0,0 +1,2107 @@
  42 +#
  43 +# Automatically generated make config: don't edit
  44 +# Linux kernel version: 2.6.28-rc4
  45 +# Mon Dec 29 12:13:48 2008
  46 +#
  47 +CONFIG_ARM=y
  48 +CONFIG_HAVE_PWM=y
  49 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
  50 +CONFIG_GENERIC_GPIO=y
  51 +# CONFIG_GENERIC_TIME is not set
  52 +# CONFIG_GENERIC_CLOCKEVENTS is not set
  53 +CONFIG_MMU=y
  54 +CONFIG_NO_IOPORT=y
  55 +CONFIG_GENERIC_HARDIRQS=y
  56 +CONFIG_STACKTRACE_SUPPORT=y
  57 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
  58 +CONFIG_LOCKDEP_SUPPORT=y
  59 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
  60 +CONFIG_HARDIRQS_SW_RESEND=y
  61 +CONFIG_GENERIC_IRQ_PROBE=y
  62 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
  63 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
  64 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
  65 +CONFIG_GENERIC_HWEIGHT=y
  66 +CONFIG_GENERIC_CALIBRATE_DELAY=y
  67 +CONFIG_FIQ=y
  68 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
  69 +CONFIG_VECTORS_BASE=0xffff0000
  70 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
  71 +
  72 +#
  73 +# General setup
  74 +#
  75 +CONFIG_EXPERIMENTAL=y
  76 +CONFIG_BROKEN_ON_SMP=y
  77 +CONFIG_LOCK_KERNEL=y
  78 +CONFIG_INIT_ENV_ARG_LIMIT=32
  79 +CONFIG_LOCALVERSION="-mokodev"
  80 +# CONFIG_LOCALVERSION_AUTO is not set
  81 +CONFIG_SWAP=y
  82 +CONFIG_SYSVIPC=y
  83 +CONFIG_SYSVIPC_SYSCTL=y
  84 +# CONFIG_POSIX_MQUEUE is not set
  85 +# CONFIG_BSD_PROCESS_ACCT is not set
  86 +# CONFIG_TASKSTATS is not set
  87 +# CONFIG_AUDIT is not set
  88 +CONFIG_IKCONFIG=y
  89 +CONFIG_IKCONFIG_PROC=y
  90 +CONFIG_LOG_BUF_SHIFT=18
  91 +# CONFIG_CGROUPS is not set
  92 +# CONFIG_GROUP_SCHED is not set
  93 +CONFIG_SYSFS_DEPRECATED=y
  94 +CONFIG_SYSFS_DEPRECATED_V2=y
  95 +# CONFIG_RELAY is not set
  96 +CONFIG_NAMESPACES=y
  97 +# CONFIG_UTS_NS is not set
  98 +# CONFIG_IPC_NS is not set
  99 +# CONFIG_USER_NS is not set
 100 +# CONFIG_PID_NS is not set
 101 +CONFIG_BLK_DEV_INITRD=y
 102 +CONFIG_INITRAMFS_SOURCE=""
 103 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 104 +CONFIG_SYSCTL=y
 105 +# CONFIG_EMBEDDED is not set
 106 +CONFIG_UID16=y
 107 +CONFIG_SYSCTL_SYSCALL=y
 108 +CONFIG_KALLSYMS=y
 109 +CONFIG_KALLSYMS_ALL=y
 110 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
 111 +CONFIG_HOTPLUG=y
 112 +CONFIG_PRINTK=y
 113 +CONFIG_BUG=y
 114 +CONFIG_ELF_CORE=y
 115 +CONFIG_COMPAT_BRK=y
 116 +CONFIG_BASE_FULL=y
 117 +CONFIG_FUTEX=y
 118 +CONFIG_ANON_INODES=y
 119 +CONFIG_EPOLL=y
 120 +CONFIG_SIGNALFD=y
 121 +CONFIG_TIMERFD=y
 122 +CONFIG_EVENTFD=y
 123 +CONFIG_SHMEM=y
 124 +CONFIG_AIO=y
 125 +CONFIG_ASHMEM=y
 126 +CONFIG_VM_EVENT_COUNTERS=y
 127 +CONFIG_SLAB=y
 128 +# CONFIG_SLUB is not set
 129 +# CONFIG_SLOB is not set
 130 +# CONFIG_PROFILING is not set
 131 +CONFIG_MARKERS=y
 132 +CONFIG_HAVE_OPROFILE=y
 133 +# CONFIG_KPROBES is not set
 134 +CONFIG_HAVE_KPROBES=y
 135 +CONFIG_HAVE_KRETPROBES=y
 136 +CONFIG_HAVE_CLK=y
 137 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 138 +CONFIG_SLABINFO=y
 139 +CONFIG_RT_MUTEXES=y
 140 +# CONFIG_TINY_SHMEM is not set
 141 +CONFIG_BASE_SMALL=0
 142 +CONFIG_MODULES=y
 143 +# CONFIG_MODULE_FORCE_LOAD is not set
 144 +CONFIG_MODULE_UNLOAD=y
 145 +CONFIG_MODULE_FORCE_UNLOAD=y
 146 +# CONFIG_MODVERSIONS is not set
 147 +# CONFIG_MODULE_SRCVERSION_ALL is not set
 148 +CONFIG_KMOD=y
 149 +CONFIG_BLOCK=y
 150 +# CONFIG_LBD is not set
 151 +# CONFIG_BLK_DEV_IO_TRACE is not set
 152 +# CONFIG_LSF is not set
 153 +# CONFIG_BLK_DEV_BSG is not set
 154 +# CONFIG_BLK_DEV_INTEGRITY is not set
 155 +
 156 +#
 157 +# IO Schedulers
 158 +#
 159 +CONFIG_IOSCHED_NOOP=y
 160 +CONFIG_IOSCHED_AS=m
 161 +CONFIG_IOSCHED_DEADLINE=y
 162 +CONFIG_IOSCHED_CFQ=m
 163 +# CONFIG_DEFAULT_AS is not set
 164 +CONFIG_DEFAULT_DEADLINE=y
 165 +# CONFIG_DEFAULT_CFQ is not set
 166 +# CONFIG_DEFAULT_NOOP is not set
 167 +CONFIG_DEFAULT_IOSCHED="deadline"
 168 +CONFIG_CLASSIC_RCU=y
 169 +CONFIG_FREEZER=y
 170 +
 171 +#
 172 +# System Type
 173 +#
 174 +# CONFIG_ARCH_AAEC2000 is not set
 175 +# CONFIG_ARCH_INTEGRATOR is not set
 176 +# CONFIG_ARCH_REALVIEW is not set
 177 +# CONFIG_ARCH_VERSATILE is not set
 178 +# CONFIG_ARCH_AT91 is not set
 179 +# CONFIG_ARCH_CLPS7500 is not set
 180 +# CONFIG_ARCH_CLPS711X is not set
 181 +# CONFIG_ARCH_EBSA110 is not set
 182 +# CONFIG_ARCH_EP93XX is not set
 183 +# CONFIG_ARCH_FOOTBRIDGE is not set
 184 +# CONFIG_ARCH_NETX is not set
 185 +# CONFIG_ARCH_H720X is not set
 186 +# CONFIG_ARCH_IMX is not set
 187 +# CONFIG_ARCH_IOP13XX is not set
 188 +# CONFIG_ARCH_IOP32X is not set
 189 +# CONFIG_ARCH_IOP33X is not set
 190 +# CONFIG_ARCH_IXP23XX is not set
 191 +# CONFIG_ARCH_IXP2000 is not set
 192 +# CONFIG_ARCH_IXP4XX is not set
 193 +# CONFIG_ARCH_L7200 is not set
 194 +# CONFIG_ARCH_KIRKWOOD is not set
 195 +# CONFIG_ARCH_KS8695 is not set
 196 +# CONFIG_ARCH_NS9XXX is not set
 197 +# CONFIG_ARCH_LOKI is not set
 198 +# CONFIG_ARCH_MV78XX0 is not set
 199 +# CONFIG_ARCH_MXC is not set
 200 +# CONFIG_ARCH_ORION5X is not set
 201 +# CONFIG_ARCH_PNX4008 is not set
 202 +# CONFIG_ARCH_PXA is not set
 203 +# CONFIG_ARCH_RPC is not set
 204 +# CONFIG_ARCH_SA1100 is not set
 205 +CONFIG_ARCH_S3C2410=y
 206 +# CONFIG_ARCH_S3C64XX is not set
 207 +# CONFIG_ARCH_SHARK is not set
 208 +# CONFIG_ARCH_LH7A40X is not set
 209 +# CONFIG_ARCH_DAVINCI is not set
 210 +# CONFIG_ARCH_OMAP is not set
 211 +# CONFIG_ARCH_MSM is not set
 212 +CONFIG_PLAT_S3C24XX=y
 213 +CONFIG_S3C2410_CLOCK=y
 214 +CONFIG_CPU_S3C244X=y
 215 +CONFIG_S3C24XX_PWM=y
 216 +CONFIG_S3C2410_DMA=y
 217 +# CONFIG_S3C2410_DMA_DEBUG is not set
 218 +CONFIG_MACH_SMDK=y
 219 +CONFIG_MACH_NEO1973=y
 220 +CONFIG_PLAT_S3C=y
 221 +CONFIG_CPU_LLSERIAL_S3C2410=y
 222 +CONFIG_CPU_LLSERIAL_S3C2440=y
 223 +
 224 +#
 225 +# Boot options
 226 +#
 227 +# CONFIG_S3C_BOOT_WATCHDOG is not set
 228 +# CONFIG_S3C_BOOT_ERROR_RESET is not set
 229 +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
 230 +
 231 +#
 232 +# Power management
 233 +#
 234 +# CONFIG_S3C2410_PM_DEBUG is not set
 235 +# CONFIG_S3C2410_PM_CHECK is not set
 236 +CONFIG_S3C_LOWLEVEL_UART_PORT=2
 237 +CONFIG_S3C_GPIO_SPACE=0
 238 +CONFIG_S3C_GPIO_TRACK=y
 239 +
 240 +#
 241 +# S3C2400 Machines
 242 +#
 243 +CONFIG_CPU_S3C2410=y
 244 +CONFIG_CPU_S3C2410_DMA=y
 245 +CONFIG_S3C2410_PM=y
 246 +CONFIG_S3C2410_GPIO=y
 247 +CONFIG_S3C2410_PWM=y
 248 +
 249 +#
 250 +# S3C2410 Machines
 251 +#
 252 +# CONFIG_ARCH_SMDK2410 is not set
 253 +# CONFIG_ARCH_H1940 is not set
 254 +# CONFIG_MACH_N30 is not set
 255 +# CONFIG_ARCH_BAST is not set
 256 +# CONFIG_MACH_OTOM is not set
 257 +# CONFIG_MACH_AML_M5900 is not set
 258 +# CONFIG_MACH_TCT_HAMMER is not set
 259 +# CONFIG_MACH_VR1000 is not set
 260 +CONFIG_MACH_QT2410=y
 261 +# CONFIG_MACH_NEO1973_GTA01 is not set
 262 +
 263 +#
 264 +# S3C2412 Machines
 265 +#
 266 +# CONFIG_MACH_JIVE is not set
 267 +# CONFIG_MACH_SMDK2413 is not set
 268 +# CONFIG_MACH_SMDK2412 is not set
 269 +# CONFIG_MACH_VSTMS is not set
 270 +CONFIG_CPU_S3C2440=y
 271 +CONFIG_S3C2440_DMA=y
 272 +CONFIG_S3C2440_C_FIQ=y
 273 +
 274 +#
 275 +# S3C2440 Machines
 276 +#
 277 +# CONFIG_MACH_ANUBIS is not set
 278 +# CONFIG_MACH_OSIRIS is not set
 279 +# CONFIG_MACH_RX3715 is not set
 280 +CONFIG_ARCH_S3C2440=y
 281 +# CONFIG_MACH_NEXCODER_2440 is not set
 282 +CONFIG_SMDK2440_CPU2440=y
 283 +# CONFIG_MACH_AT2440EVB is not set
 284 +CONFIG_MACH_NEO1973_GTA02=y
 285 +# CONFIG_NEO1973_GTA02_2440 is not set
 286 +CONFIG_CPU_S3C2442=y
 287 +
 288 +#
 289 +# S3C2442 Machines
 290 +#
 291 +CONFIG_SMDK2440_CPU2442=y
 292 +
 293 +#
 294 +# S3C2443 Machines
 295 +#
 296 +# CONFIG_MACH_SMDK2443 is not set
 297 +
 298 +#
 299 +# Processor Type
 300 +#
 301 +CONFIG_CPU_32=y
 302 +CONFIG_CPU_ARM920T=y
 303 +CONFIG_CPU_32v4T=y
 304 +CONFIG_CPU_ABRT_EV4T=y
 305 +CONFIG_CPU_PABRT_NOIFAR=y
 306 +CONFIG_CPU_CACHE_V4WT=y
 307 +CONFIG_CPU_CACHE_VIVT=y
 308 +CONFIG_CPU_COPY_V4WB=y
 309 +CONFIG_CPU_TLB_V4WBI=y
 310 +CONFIG_CPU_CP15=y
 311 +CONFIG_CPU_CP15_MMU=y
 312 +
 313 +#
 314 +# Processor Features
 315 +#
 316 +CONFIG_ARM_THUMB=y
 317 +# CONFIG_CPU_ICACHE_DISABLE is not set
 318 +# CONFIG_CPU_DCACHE_DISABLE is not set
 319 +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 320 +# CONFIG_OUTER_CACHE is not set
 321 +
 322 +#
 323 +# Bus support
 324 +#
 325 +# CONFIG_PCI_SYSCALL is not set
 326 +# CONFIG_ARCH_SUPPORTS_MSI is not set
 327 +# CONFIG_PCCARD is not set
 328 +
 329 +#
 330 +# Kernel Features
 331 +#
 332 +CONFIG_VMSPLIT_3G=y
 333 +# CONFIG_VMSPLIT_2G is not set
 334 +# CONFIG_VMSPLIT_1G is not set
 335 +CONFIG_PAGE_OFFSET=0xC0000000
 336 +CONFIG_PREEMPT=y
 337 +CONFIG_HZ=200
 338 +CONFIG_AEABI=y
 339 +CONFIG_OABI_COMPAT=y
 340 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
 341 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 342 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 343 +CONFIG_SELECT_MEMORY_MODEL=y
 344 +CONFIG_FLATMEM_MANUAL=y
 345 +# CONFIG_DISCONTIGMEM_MANUAL is not set
 346 +# CONFIG_SPARSEMEM_MANUAL is not set
 347 +CONFIG_FLATMEM=y
 348 +CONFIG_FLAT_NODE_MEM_MAP=y
 349 +CONFIG_PAGEFLAGS_EXTENDED=y
 350 +CONFIG_SPLIT_PTLOCK_CPUS=4096
 351 +# CONFIG_RESOURCES_64BIT is not set
 352 +# CONFIG_PHYS_ADDR_T_64BIT is not set
 353 +CONFIG_ZONE_DMA_FLAG=0
 354 +CONFIG_VIRT_TO_BUS=y
 355 +CONFIG_UNEVICTABLE_LRU=y
 356 +CONFIG_ALIGNMENT_TRAP=y
 357 +
 358 +#
 359 +# Boot options
 360 +#
 361 +CONFIG_ZBOOT_ROM_TEXT=0x0
 362 +CONFIG_ZBOOT_ROM_BSS=0x0
 363 +CONFIG_CMDLINE="unused -- bootloader passes ATAG list"
 364 +# CONFIG_XIP_KERNEL is not set
 365 +CONFIG_KEXEC=y
 366 +CONFIG_ATAGS_PROC=y
 367 +
 368 +#
 369 +# CPU Power Management
 370 +#
 371 +CONFIG_CPU_IDLE=y
 372 +CONFIG_CPU_IDLE_GOV_LADDER=y
 373 +
 374 +#
 375 +# Floating point emulation
 376 +#
 377 +
 378 +#
 379 +# At least one emulation must be selected
 380 +#
 381 +CONFIG_FPE_NWFPE=y
 382 +# CONFIG_FPE_NWFPE_XP is not set
 383 +# CONFIG_FPE_FASTFPE is not set
 384 +
 385 +#
 386 +# Userspace binary formats
 387 +#
 388 +CONFIG_BINFMT_ELF=y
 389 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 390 +CONFIG_HAVE_AOUT=y
 391 +# CONFIG_BINFMT_AOUT is not set
 392 +# CONFIG_BINFMT_MISC is not set
 393 +
 394 +#
 395 +# Power management options
 396 +#
 397 +CONFIG_PM=y
 398 +# CONFIG_PM_DEBUG is not set
 399 +CONFIG_PM_SLEEP=y
 400 +CONFIG_SUSPEND=y
 401 +CONFIG_SUSPEND_FREEZER=y
 402 +CONFIG_APM_EMULATION=y
 403 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
 404 +CONFIG_NET=y
 405 +
 406 +#
 407 +# Networking options
 408 +#
 409 +CONFIG_PACKET=y
 410 +CONFIG_PACKET_MMAP=y
 411 +CONFIG_UNIX=y
 412 +CONFIG_XFRM=y
 413 +# CONFIG_XFRM_USER is not set
 414 +# CONFIG_XFRM_SUB_POLICY is not set
 415 +CONFIG_XFRM_MIGRATE=y
 416 +# CONFIG_XFRM_STATISTICS is not set
 417 +CONFIG_XFRM_IPCOMP=m
 418 +CONFIG_NET_KEY=m
 419 +CONFIG_NET_KEY_MIGRATE=y
 420 +CONFIG_INET=y
 421 +CONFIG_IP_MULTICAST=y
 422 +CONFIG_IP_ADVANCED_ROUTER=y
 423 +CONFIG_ASK_IP_FIB_HASH=y
 424 +# CONFIG_IP_FIB_TRIE is not set
 425 +CONFIG_IP_FIB_HASH=y
 426 +CONFIG_IP_MULTIPLE_TABLES=y
 427 +# CONFIG_IP_ROUTE_MULTIPATH is not set
 428 +# CONFIG_IP_ROUTE_VERBOSE is not set
 429 +CONFIG_IP_PNP=y
 430 +# CONFIG_IP_PNP_DHCP is not set
 431 +# CONFIG_IP_PNP_BOOTP is not set
 432 +# CONFIG_IP_PNP_RARP is not set
 433 +CONFIG_NET_IPIP=m
 434 +CONFIG_NET_IPGRE=m
 435 +# CONFIG_NET_IPGRE_BROADCAST is not set
 436 +# CONFIG_IP_MROUTE is not set
 437 +# CONFIG_ARPD is not set
 438 +CONFIG_SYN_COOKIES=y
 439 +CONFIG_INET_AH=m
 440 +CONFIG_INET_ESP=m
 441 +CONFIG_INET_IPCOMP=m
 442 +CONFIG_INET_XFRM_TUNNEL=m
 443 +CONFIG_INET_TUNNEL=m
 444 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
 445 +CONFIG_INET_XFRM_MODE_TUNNEL=m
 446 +CONFIG_INET_XFRM_MODE_BEET=m
 447 +# CONFIG_INET_LRO is not set
 448 +CONFIG_INET_DIAG=y
 449 +CONFIG_INET_TCP_DIAG=y
 450 +# CONFIG_TCP_CONG_ADVANCED is not set
 451 +CONFIG_TCP_CONG_CUBIC=y
 452 +CONFIG_DEFAULT_TCP_CONG="cubic"
 453 +CONFIG_TCP_MD5SIG=y
 454 +CONFIG_IPV6=m
 455 +# CONFIG_IPV6_PRIVACY is not set
 456 +# CONFIG_IPV6_ROUTER_PREF is not set
 457 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
 458 +CONFIG_INET6_AH=m
 459 +CONFIG_INET6_ESP=m
 460 +CONFIG_INET6_IPCOMP=m
 461 +# CONFIG_IPV6_MIP6 is not set
 462 +CONFIG_INET6_XFRM_TUNNEL=m
 463 +CONFIG_INET6_TUNNEL=m
 464 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
 465 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
 466 +CONFIG_INET6_XFRM_MODE_BEET=m
 467 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 468 +CONFIG_IPV6_SIT=m
 469 +CONFIG_IPV6_NDISC_NODETYPE=y
 470 +CONFIG_IPV6_TUNNEL=m
 471 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
 472 +# CONFIG_IPV6_MROUTE is not set
 473 +# CONFIG_NETWORK_SECMARK is not set
 474 +CONFIG_NETFILTER=y
 475 +# CONFIG_NETFILTER_DEBUG is not set
 476 +CONFIG_NETFILTER_ADVANCED=y
 477 +CONFIG_BRIDGE_NETFILTER=y
 478 +
 479 +#
 480 +# Core Netfilter Configuration
 481 +#
 482 +CONFIG_NETFILTER_NETLINK=m
 483 +CONFIG_NETFILTER_NETLINK_QUEUE=m
 484 +CONFIG_NETFILTER_NETLINK_LOG=m
 485 +CONFIG_NF_CONNTRACK=y
 486 +# CONFIG_NF_CT_ACCT is not set
 487 +# CONFIG_NF_CONNTRACK_MARK is not set
 488 +# CONFIG_NF_CONNTRACK_EVENTS is not set
 489 +# CONFIG_NF_CT_PROTO_DCCP is not set
 490 +# CONFIG_NF_CT_PROTO_SCTP is not set
 491 +# CONFIG_NF_CT_PROTO_UDPLITE is not set
 492 +# CONFIG_NF_CONNTRACK_AMANDA is not set
 493 +# CONFIG_NF_CONNTRACK_FTP is not set
 494 +# CONFIG_NF_CONNTRACK_H323 is not set
 495 +# CONFIG_NF_CONNTRACK_IRC is not set
 496 +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
 497 +# CONFIG_NF_CONNTRACK_PPTP is not set
 498 +# CONFIG_NF_CONNTRACK_SANE is not set
 499 +# CONFIG_NF_CONNTRACK_SIP is not set
 500 +# CONFIG_NF_CONNTRACK_TFTP is not set
 501 +# CONFIG_NF_CT_NETLINK is not set
 502 +# CONFIG_NETFILTER_TPROXY is not set
 503 +CONFIG_NETFILTER_XTABLES=m
 504 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
 505 +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
 506 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
 507 +CONFIG_NETFILTER_XT_TARGET_MARK=m
 508 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
 509 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
 510 +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
 511 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
 512 +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
 513 +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
 514 +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
 515 +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
 516 +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
 517 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
 518 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
 519 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
 520 +CONFIG_NETFILTER_XT_MATCH_ESP=m
 521 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
 522 +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
 523 +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
 524 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
 525 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
 526 +CONFIG_NETFILTER_XT_MATCH_MAC=m
 527 +CONFIG_NETFILTER_XT_MATCH_MARK=m
 528 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
 529 +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
 530 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
 531 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
 532 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
 533 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
 534 +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
 535 +CONFIG_NETFILTER_XT_MATCH_REALM=m
 536 +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
 537 +CONFIG_NETFILTER_XT_MATCH_SCTP=m
 538 +# CONFIG_NETFILTER_XT_MATCH_STATE is not set
 539 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
 540 +CONFIG_NETFILTER_XT_MATCH_STRING=m
 541 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
 542 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
 543 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
 544 +# CONFIG_IP_VS is not set
 545 +
 546 +#
 547 +# IP: Netfilter Configuration
 548 +#
 549 +CONFIG_NF_DEFRAG_IPV4=y
 550 +CONFIG_NF_CONNTRACK_IPV4=y
 551 +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
 552 +# CONFIG_IP_NF_QUEUE is not set
 553 +CONFIG_IP_NF_IPTABLES=m
 554 +CONFIG_IP_NF_MATCH_ADDRTYPE=m
 555 +CONFIG_IP_NF_MATCH_AH=m
 556 +CONFIG_IP_NF_MATCH_ECN=m
 557 +CONFIG_IP_NF_MATCH_TTL=m
 558 +CONFIG_IP_NF_FILTER=m
 559 +CONFIG_IP_NF_TARGET_REJECT=m
 560 +CONFIG_IP_NF_TARGET_LOG=m
 561 +CONFIG_IP_NF_TARGET_ULOG=m
 562 +CONFIG_NF_NAT=m
 563 +CONFIG_NF_NAT_NEEDED=y
 564 +CONFIG_IP_NF_TARGET_MASQUERADE=m
 565 +# CONFIG_IP_NF_TARGET_NETMAP is not set
 566 +# CONFIG_IP_NF_TARGET_REDIRECT is not set
 567 +# CONFIG_NF_NAT_SNMP_BASIC is not set
 568 +# CONFIG_NF_NAT_FTP is not set
 569 +# CONFIG_NF_NAT_IRC is not set
 570 +# CONFIG_NF_NAT_TFTP is not set
 571 +# CONFIG_NF_NAT_AMANDA is not set
 572 +# CONFIG_NF_NAT_PPTP is not set
 573 +# CONFIG_NF_NAT_H323 is not set
 574 +# CONFIG_NF_NAT_SIP is not set
 575 +CONFIG_IP_NF_MANGLE=m
 576 +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
 577 +CONFIG_IP_NF_TARGET_ECN=m
 578 +CONFIG_IP_NF_TARGET_TTL=m
 579 +# CONFIG_IP_NF_RAW is not set
 580 +# CONFIG_IP_NF_ARPTABLES is not set
 581 +
 582 +#
 583 +# IPv6: Netfilter Configuration
 584 +#
 585 +CONFIG_NF_CONNTRACK_IPV6=m
 586 +# CONFIG_IP6_NF_QUEUE is not set
 587 +CONFIG_IP6_NF_IPTABLES=m
 588 +CONFIG_IP6_NF_MATCH_AH=m
 589 +CONFIG_IP6_NF_MATCH_EUI64=m
 590 +CONFIG_IP6_NF_MATCH_FRAG=m
 591 +CONFIG_IP6_NF_MATCH_OPTS=m
 592 +CONFIG_IP6_NF_MATCH_HL=m
 593 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
 594 +CONFIG_IP6_NF_MATCH_MH=m
 595 +CONFIG_IP6_NF_MATCH_RT=m
 596 +CONFIG_IP6_NF_TARGET_LOG=m
 597 +CONFIG_IP6_NF_FILTER=m
 598 +CONFIG_IP6_NF_TARGET_REJECT=m
 599 +CONFIG_IP6_NF_MANGLE=m
 600 +CONFIG_IP6_NF_TARGET_HL=m
 601 +# CONFIG_IP6_NF_RAW is not set
 602 +CONFIG_BRIDGE_NF_EBTABLES=m
 603 +CONFIG_BRIDGE_EBT_BROUTE=m
 604 +CONFIG_BRIDGE_EBT_T_FILTER=m
 605 +CONFIG_BRIDGE_EBT_T_NAT=m
 606 +CONFIG_BRIDGE_EBT_802_3=m
 607 +CONFIG_BRIDGE_EBT_AMONG=m
 608 +CONFIG_BRIDGE_EBT_ARP=m
 609 +CONFIG_BRIDGE_EBT_IP=m
 610 +# CONFIG_BRIDGE_EBT_IP6 is not set
 611 +CONFIG_BRIDGE_EBT_LIMIT=m
 612 +CONFIG_BRIDGE_EBT_MARK=m
 613 +CONFIG_BRIDGE_EBT_PKTTYPE=m
 614 +CONFIG_BRIDGE_EBT_STP=m
 615 +CONFIG_BRIDGE_EBT_VLAN=m
 616 +CONFIG_BRIDGE_EBT_ARPREPLY=m
 617 +CONFIG_BRIDGE_EBT_DNAT=m
 618 +CONFIG_BRIDGE_EBT_MARK_T=m
 619 +CONFIG_BRIDGE_EBT_REDIRECT=m
 620 +CONFIG_BRIDGE_EBT_SNAT=m
 621 +CONFIG_BRIDGE_EBT_LOG=m
 622 +CONFIG_BRIDGE_EBT_ULOG=m
 623 +# CONFIG_BRIDGE_EBT_NFLOG is not set
 624 +# CONFIG_IP_DCCP is not set
 625 +# CONFIG_IP_SCTP is not set
 626 +# CONFIG_TIPC is not set
 627 +# CONFIG_ATM is not set
 628 +CONFIG_STP=y
 629 +CONFIG_BRIDGE=y
 630 +# CONFIG_NET_DSA is not set
 631 +# CONFIG_VLAN_8021Q is not set
 632 +# CONFIG_DECNET is not set
 633 +CONFIG_LLC=y
 634 +# CONFIG_LLC2 is not set
 635 +# CONFIG_IPX is not set
 636 +# CONFIG_ATALK is not set
 637 +# CONFIG_X25 is not set
 638 +# CONFIG_LAPB is not set
 639 +# CONFIG_ECONET is not set
 640 +# CONFIG_WAN_ROUTER is not set
 641 +CONFIG_NET_SCHED=y
 642 +
 643 +#
 644 +# Queueing/Scheduling
 645 +#
 646 +CONFIG_NET_SCH_CBQ=m
 647 +CONFIG_NET_SCH_HTB=m
 648 +CONFIG_NET_SCH_HFSC=m
 649 +CONFIG_NET_SCH_PRIO=m
 650 +# CONFIG_NET_SCH_MULTIQ is not set
 651 +CONFIG_NET_SCH_RED=m
 652 +CONFIG_NET_SCH_SFQ=m
 653 +CONFIG_NET_SCH_TEQL=m
 654 +CONFIG_NET_SCH_TBF=m
 655 +CONFIG_NET_SCH_GRED=m
 656 +CONFIG_NET_SCH_DSMARK=m
 657 +CONFIG_NET_SCH_NETEM=m
 658 +
 659 +#
 660 +# Classification
 661 +#
 662 +CONFIG_NET_CLS=y
 663 +CONFIG_NET_CLS_BASIC=m
 664 +CONFIG_NET_CLS_TCINDEX=m
 665 +CONFIG_NET_CLS_ROUTE4=m
 666 +CONFIG_NET_CLS_ROUTE=y
 667 +CONFIG_NET_CLS_FW=m
 668 +CONFIG_NET_CLS_U32=m
 669 +CONFIG_CLS_U32_PERF=y
 670 +CONFIG_CLS_U32_MARK=y
 671 +CONFIG_NET_CLS_RSVP=m
 672 +CONFIG_NET_CLS_RSVP6=m
 673 +# CONFIG_NET_CLS_FLOW is not set
 674 +# CONFIG_NET_EMATCH is not set
 675 +# CONFIG_NET_CLS_ACT is not set
 676 +# CONFIG_NET_CLS_IND is not set
 677 +CONFIG_NET_SCH_FIFO=y
 678 +
 679 +#
 680 +# Network testing
 681 +#
 682 +# CONFIG_NET_PKTGEN is not set
 683 +# CONFIG_HAMRADIO is not set
 684 +# CONFIG_CAN is not set
 685 +# CONFIG_IRDA is not set
 686 +CONFIG_BT=y
 687 +CONFIG_BT_L2CAP=y
 688 +CONFIG_BT_SCO=y
 689 +CONFIG_BT_RFCOMM=y
 690 +CONFIG_BT_RFCOMM_TTY=y
 691 +CONFIG_BT_BNEP=y
 692 +CONFIG_BT_BNEP_MC_FILTER=y
 693 +CONFIG_BT_BNEP_PROTO_FILTER=y
 694 +CONFIG_BT_HIDP=y
 695 +
 696 +#
 697 +# Bluetooth device drivers
 698 +#
 699 +CONFIG_BT_HCIBTUSB=y
 700 +# CONFIG_BT_HCIBTSDIO is not set
 701 +# CONFIG_BT_HCIUART is not set
 702 +# CONFIG_BT_HCIBCM203X is not set
 703 +# CONFIG_BT_HCIBPA10X is not set
 704 +# CONFIG_BT_HCIBFUSB is not set
 705 +# CONFIG_BT_HCIVHCI is not set
 706 +# CONFIG_AF_RXRPC is not set
 707 +# CONFIG_PHONET is not set
 708 +CONFIG_FIB_RULES=y
 709 +CONFIG_WIRELESS=y
 710 +# CONFIG_CFG80211 is not set
 711 +# CONFIG_WIRELESS_OLD_REGULATORY is not set
 712 +CONFIG_WIRELESS_EXT=y
 713 +CONFIG_WIRELESS_EXT_SYSFS=y
 714 +# CONFIG_MAC80211 is not set
 715 +# CONFIG_IEEE80211 is not set
 716 +CONFIG_RFKILL=y
 717 +CONFIG_RFKILL_INPUT=y
 718 +CONFIG_RFKILL_LEDS=y
 719 +# CONFIG_NET_9P is not set
 720 +
 721 +#
 722 +# Device Drivers
 723 +#
 724 +
 725 +#
 726 +# Generic Driver Options
 727 +#
 728 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 729 +CONFIG_STANDALONE=y
 730 +CONFIG_PREVENT_FIRMWARE_BUILD=y
 731 +CONFIG_FW_LOADER=y
 732 +# CONFIG_FIRMWARE_IN_KERNEL is not set
 733 +CONFIG_EXTRA_FIRMWARE=""
 734 +# CONFIG_DEBUG_DRIVER is not set
 735 +# CONFIG_DEBUG_DEVRES is not set
 736 +# CONFIG_SYS_HYPERVISOR is not set
 737 +CONFIG_CONNECTOR=m
 738 +CONFIG_MTD=y
 739 +# CONFIG_MTD_DEBUG is not set
 740 +CONFIG_MTD_CONCAT=y
 741 +CONFIG_MTD_PARTITIONS=y
 742 +# CONFIG_MTD_REDBOOT_PARTS is not set
 743 +CONFIG_MTD_CMDLINE_PARTS=y
 744 +# CONFIG_MTD_AFS_PARTS is not set
 745 +# CONFIG_MTD_AR7_PARTS is not set
 746 +
 747 +#
 748 +# User Modules And Translation Layers
 749 +#
 750 +CONFIG_MTD_CHAR=y
 751 +CONFIG_MTD_BLKDEVS=y
 752 +CONFIG_MTD_BLOCK=y
 753 +# CONFIG_FTL is not set
 754 +# CONFIG_NFTL is not set
 755 +# CONFIG_INFTL is not set
 756 +# CONFIG_RFD_FTL is not set
 757 +# CONFIG_SSFDC is not set
 758 +# CONFIG_MTD_OOPS is not set
 759 +
 760 +#
 761 +# RAM/ROM/Flash chip drivers
 762 +#
 763 +CONFIG_MTD_CFI=y
 764 +# CONFIG_MTD_JEDECPROBE is not set
 765 +CONFIG_MTD_GEN_PROBE=y
 766 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 767 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
 768 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
 769 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
 770 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
 771 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
 772 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
 773 +CONFIG_MTD_CFI_I1=y
 774 +CONFIG_MTD_CFI_I2=y
 775 +# CONFIG_MTD_CFI_I4 is not set
 776 +# CONFIG_MTD_CFI_I8 is not set
 777 +CONFIG_MTD_CFI_INTELEXT=y
 778 +# CONFIG_MTD_CFI_AMDSTD is not set
 779 +# CONFIG_MTD_CFI_STAA is not set
 780 +CONFIG_MTD_CFI_UTIL=y
 781 +# CONFIG_MTD_RAM is not set
 782 +CONFIG_MTD_ROM=y
 783 +CONFIG_MTD_ABSENT=y
 784 +
 785 +#
 786 +# Mapping drivers for chip access
 787 +#
 788 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
 789 +CONFIG_MTD_PHYSMAP=y
 790 +CONFIG_MTD_PHYSMAP_START=0x0
 791 +CONFIG_MTD_PHYSMAP_LEN=0
 792 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 793 +# CONFIG_MTD_ARM_INTEGRATOR is not set
 794 +# CONFIG_MTD_PLATRAM is not set
 795 +
 796 +#
 797 +# Self-contained MTD device drivers
 798 +#
 799 +# CONFIG_MTD_DATAFLASH is not set
 800 +# CONFIG_MTD_M25P80 is not set
 801 +# CONFIG_MTD_SLRAM is not set
 802 +# CONFIG_MTD_PHRAM is not set
 803 +# CONFIG_MTD_MTDRAM is not set
 804 +# CONFIG_MTD_BLOCK2MTD is not set
 805 +
 806 +#
 807 +# Disk-On-Chip Device Drivers
 808 +#
 809 +# CONFIG_MTD_DOC2000 is not set
 810 +# CONFIG_MTD_DOC2001 is not set
 811 +# CONFIG_MTD_DOC2001PLUS is not set
 812 +CONFIG_MTD_NAND=y
 813 +CONFIG_MTD_NAND_VERIFY_WRITE=y
 814 +# CONFIG_MTD_NAND_ECC_SMC is not set
 815 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 816 +# CONFIG_MTD_NAND_GPIO is not set
 817 +CONFIG_MTD_NAND_IDS=y
 818 +CONFIG_MTD_NAND_S3C2410=y
 819 +CONFIG_MTD_NAND_S3C2410_DEBUG=y
 820 +CONFIG_MTD_NAND_S3C2410_HWECC=y
 821 +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
 822 +# CONFIG_MTD_NAND_DISKONCHIP is not set
 823 +# CONFIG_MTD_NAND_NANDSIM is not set
 824 +# CONFIG_MTD_NAND_PLATFORM is not set
 825 +# CONFIG_MTD_ALAUDA is not set
 826 +# CONFIG_MTD_ONENAND is not set
 827 +
 828 +#
 829 +# UBI - Unsorted block images
 830 +#
 831 +# CONFIG_MTD_UBI is not set
 832 +# CONFIG_PARPORT is not set
 833 +CONFIG_BLK_DEV=y
 834 +# CONFIG_BLK_DEV_COW_COMMON is not set
 835 +CONFIG_BLK_DEV_LOOP=m
 836 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
 837 +# CONFIG_BLK_DEV_NBD is not set
 838 +CONFIG_BLK_DEV_UB=m
 839 +CONFIG_BLK_DEV_RAM=y
 840 +CONFIG_BLK_DEV_RAM_COUNT=16
 841 +CONFIG_BLK_DEV_RAM_SIZE=4096
 842 +# CONFIG_BLK_DEV_XIP is not set
 843 +# CONFIG_CDROM_PKTCDVD is not set
 844 +# CONFIG_ATA_OVER_ETH is not set
 845 +CONFIG_MISC_DEVICES=y
 846 +# CONFIG_EEPROM_93CX6 is not set
 847 +CONFIG_LOW_MEMORY_KILLER=y
 848 +# CONFIG_ENCLOSURE_SERVICES is not set
 849 +CONFIG_HAVE_IDE=y
 850 +# CONFIG_IDE is not set
 851 +
 852 +#
 853 +# SCSI device support
 854 +#
 855 +# CONFIG_RAID_ATTRS is not set
 856 +CONFIG_SCSI=y
 857 +CONFIG_SCSI_DMA=y
 858 +# CONFIG_SCSI_TGT is not set
 859 +# CONFIG_SCSI_NETLINK is not set
 860 +CONFIG_SCSI_PROC_FS=y
 861 +
 862 +#
 863 +# SCSI support type (disk, tape, CD-ROM)
 864 +#
 865 +CONFIG_BLK_DEV_SD=y
 866 +# CONFIG_CHR_DEV_ST is not set
 867 +# CONFIG_CHR_DEV_OSST is not set
 868 +CONFIG_BLK_DEV_SR=y
 869 +# CONFIG_BLK_DEV_SR_VENDOR is not set
 870 +CONFIG_CHR_DEV_SG=y
 871 +# CONFIG_CHR_DEV_SCH is not set
 872 +
 873 +#
 874 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 875 +#
 876 +CONFIG_SCSI_MULTI_LUN=y
 877 +# CONFIG_SCSI_CONSTANTS is not set
 878 +# CONFIG_SCSI_LOGGING is not set
 879 +CONFIG_SCSI_SCAN_ASYNC=y
 880 +CONFIG_SCSI_WAIT_SCAN=m
 881 +
 882 +#
 883 +# SCSI Transports
 884 +#
 885 +# CONFIG_SCSI_SPI_ATTRS is not set
 886 +# CONFIG_SCSI_FC_ATTRS is not set
 887 +# CONFIG_SCSI_ISCSI_ATTRS is not set
 888 +# CONFIG_SCSI_SAS_LIBSAS is not set
 889 +# CONFIG_SCSI_SRP_ATTRS is not set
 890 +CONFIG_SCSI_LOWLEVEL=y
 891 +# CONFIG_ISCSI_TCP is not set
 892 +# CONFIG_SCSI_DEBUG is not set
 893 +# CONFIG_SCSI_DH is not set
 894 +# CONFIG_ATA is not set
 895 +CONFIG_MD=y
 896 +# CONFIG_BLK_DEV_MD is not set
 897 +CONFIG_BLK_DEV_DM=m
 898 +# CONFIG_DM_DEBUG is not set
 899 +CONFIG_DM_CRYPT=m
 900 +CONFIG_DM_SNAPSHOT=m
 901 +# CONFIG_DM_MIRROR is not set
 902 +# CONFIG_DM_ZERO is not set
 903 +# CONFIG_DM_MULTIPATH is not set
 904 +# CONFIG_DM_DELAY is not set
 905 +# CONFIG_DM_UEVENT is not set
 906 +CONFIG_NETDEVICES=y
 907 +# CONFIG_DUMMY is not set
 908 +# CONFIG_BONDING is not set
 909 +# CONFIG_MACVLAN is not set
 910 +# CONFIG_EQUALIZER is not set
 911 +CONFIG_TUN=y
 912 +# CONFIG_VETH is not set
 913 +# CONFIG_PHYLIB is not set
 914 +CONFIG_NET_ETHERNET=y
 915 +CONFIG_MII=y
 916 +# CONFIG_AX88796 is not set
 917 +# CONFIG_SMC91X is not set
 918 +# CONFIG_DM9000 is not set
 919 +# CONFIG_ENC28J60 is not set
 920 +# CONFIG_SMC911X is not set
 921 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
 922 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
 923 +# CONFIG_IBM_NEW_EMAC_TAH is not set
 924 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
 925 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
 926 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
 927 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 928 +# CONFIG_B44 is not set
 929 +# CONFIG_NETDEV_1000 is not set
 930 +# CONFIG_NETDEV_10000 is not set
 931 +
 932 +#
 933 +# Wireless LAN
 934 +#
 935 +# CONFIG_WLAN_PRE80211 is not set
 936 +# CONFIG_WLAN_80211 is not set
 937 +# CONFIG_IWLWIFI_LEDS is not set
 938 +
 939 +#
 940 +# USB Network Adapters
 941 +#
 942 +CONFIG_USB_CATC=m
 943 +CONFIG_USB_KAWETH=m
 944 +CONFIG_USB_PEGASUS=m
 945 +CONFIG_USB_RTL8150=m
 946 +CONFIG_USB_USBNET=y
 947 +CONFIG_USB_NET_AX8817X=m
 948 +CONFIG_USB_NET_CDCETHER=y
 949 +CONFIG_USB_NET_DM9601=m
 950 +# CONFIG_USB_NET_SMSC95XX is not set
 951 +CONFIG_USB_NET_GL620A=m
 952 +CONFIG_USB_NET_NET1080=m
 953 +CONFIG_USB_NET_PLUSB=m
 954 +CONFIG_USB_NET_MCS7830=m
 955 +CONFIG_USB_NET_RNDIS_HOST=y
 956 +CONFIG_USB_NET_CDC_SUBSET=m
 957 +CONFIG_USB_ALI_M5632=y
 958 +CONFIG_USB_AN2720=y
 959 +CONFIG_USB_BELKIN=y
 960 +CONFIG_USB_ARMLINUX=y
 961 +CONFIG_USB_EPSON2888=y
 962 +CONFIG_USB_KC2190=y
 963 +CONFIG_USB_NET_ZAURUS=m
 964 +# CONFIG_USB_HSO is not set
 965 +# CONFIG_WAN is not set
 966 +CONFIG_PPP=y
 967 +CONFIG_PPP_MULTILINK=y
 968 +CONFIG_PPP_FILTER=y
 969 +CONFIG_PPP_ASYNC=y
 970 +CONFIG_PPP_SYNC_TTY=y
 971 +CONFIG_PPP_DEFLATE=y
 972 +CONFIG_PPP_BSDCOMP=y
 973 +CONFIG_PPP_MPPE=y
 974 +# CONFIG_PPPOE is not set
 975 +# CONFIG_PPPOL2TP is not set
 976 +# CONFIG_SLIP is not set
 977 +CONFIG_SLHC=y
 978 +# CONFIG_NETCONSOLE is not set
 979 +# CONFIG_NETPOLL is not set
 980 +# CONFIG_NET_POLL_CONTROLLER is not set
 981 +# CONFIG_ISDN is not set
 982 +
 983 +#
 984 +# Input device support
 985 +#
 986 +CONFIG_INPUT=y
 987 +# CONFIG_INPUT_FF_MEMLESS is not set
 988 +# CONFIG_INPUT_POLLDEV is not set
 989 +
 990 +#
 991 +# Userland interfaces
 992 +#
 993 +CONFIG_INPUT_MOUSEDEV=y
 994 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 995 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
 996 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640
 997 +# CONFIG_INPUT_JOYDEV is not set
 998 +CONFIG_INPUT_EVDEV=y
 999 +# CONFIG_INPUT_EVBUG is not set
1000 +
1001 +#
1002 +# Input Device Drivers
1003 +#
1004 +CONFIG_INPUT_KEYBOARD=y
1005 +# CONFIG_KEYBOARD_ATKBD is not set
1006 +# CONFIG_KEYBOARD_SUNKBD is not set
1007 +# CONFIG_KEYBOARD_LKKBD is not set
1008 +# CONFIG_KEYBOARD_XTKBD is not set
1009 +# CONFIG_KEYBOARD_NEWTON is not set
1010 +CONFIG_KEYBOARD_STOWAWAY=m
1011 +CONFIG_KEYBOARD_GPIO=m
1012 +CONFIG_KEYBOARD_NEO1973=y
1013 +CONFIG_KEYBOARD_QT2410=y
1014 +CONFIG_INPUT_MOUSE=y
1015 +# CONFIG_MOUSE_PS2 is not set
1016 +# CONFIG_MOUSE_SERIAL is not set
1017 +# CONFIG_MOUSE_APPLETOUCH is not set
1018 +# CONFIG_MOUSE_BCM5974 is not set
1019 +# CONFIG_MOUSE_VSXXXAA is not set
1020 +# CONFIG_MOUSE_GPIO is not set
1021 +# CONFIG_INPUT_JOYSTICK is not set
1022 +# CONFIG_INPUT_TABLET is not set
1023 +CONFIG_INPUT_TOUCHSCREEN=y
1024 +CONFIG_TOUCHSCREEN_FILTER=y
1025 +CONFIG_TOUCHSCREEN_FILTER_GROUP=y
1026 +CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
1027 +CONFIG_TOUCHSCREEN_FILTER_MEAN=y
1028 +CONFIG_TOUCHSCREEN_FILTER_LINEAR=y
1029 +# CONFIG_TOUCHSCREEN_ADS7846 is not set
1030 +# CONFIG_TOUCHSCREEN_FUJITSU is not set
1031 +CONFIG_TOUCHSCREEN_S3C2410=y
1032 +# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set
1033 +# CONFIG_TOUCHSCREEN_GUNZE is not set
1034 +# CONFIG_TOUCHSCREEN_ELO is not set
1035 +# CONFIG_TOUCHSCREEN_MTOUCH is not set
1036 +# CONFIG_TOUCHSCREEN_INEXIO is not set
1037 +# CONFIG_TOUCHSCREEN_MK712 is not set
1038 +# CONFIG_TOUCHSCREEN_PENMOUNT is not set
1039 +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
1040 +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
1041 +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
1042 +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
1043 +# CONFIG_TOUCHSCREEN_PCAP7200 is not set
1044 +CONFIG_INPUT_MISC=y
1045 +# CONFIG_INPUT_ATI_REMOTE is not set
1046 +# CONFIG_INPUT_ATI_REMOTE2 is not set
1047 +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
1048 +# CONFIG_INPUT_POWERMATE is not set
1049 +# CONFIG_INPUT_YEALINK is not set
1050 +# CONFIG_INPUT_CM109 is not set
1051 +CONFIG_INPUT_UINPUT=m
1052 +CONFIG_INPUT_LIS302DL=y
1053 +CONFIG_INPUT_PCF50633_PMU=y
1054 +
1055 +#
1056 +# Hardware I/O ports
1057 +#
1058 +CONFIG_SERIO=y
1059 +# CONFIG_SERIO_SERPORT is not set
1060 +# CONFIG_SERIO_RAW is not set
1061 +# CONFIG_GAMEPORT is not set
1062 +
1063 +#
1064 +# Character devices
1065 +#
1066 +CONFIG_VT=y
1067 +CONFIG_CONSOLE_TRANSLATIONS=y
1068 +CONFIG_VT_CONSOLE=y
1069 +CONFIG_NR_TTY_DEVICES=6
1070 +CONFIG_HW_CONSOLE=y
1071 +CONFIG_VT_HW_CONSOLE_BINDING=y
1072 +# CONFIG_DEVKMEM is not set
1073 +# CONFIG_SERIAL_NONSTANDARD is not set
1074 +
1075 +#
1076 +# Serial drivers
1077 +#
1078 +# CONFIG_SERIAL_8250 is not set
1079 +
1080 +#
1081 +# Non-8250 serial port support
1082 +#
1083 +CONFIG_SERIAL_SAMSUNG=y
1084 +CONFIG_SERIAL_SAMSUNG_UARTS=3
1085 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
1086 +CONFIG_SERIAL_S3C2410=y
1087 +CONFIG_SERIAL_S3C2440=y
1088 +CONFIG_SERIAL_CORE=y
1089 +CONFIG_SERIAL_CORE_CONSOLE=y
1090 +CONFIG_UNIX98_PTYS=y
1091 +# CONFIG_LEGACY_PTYS is not set
1092 +# CONFIG_IPMI_HANDLER is not set
1093 +# CONFIG_HW_RANDOM is not set
1094 +# CONFIG_NVRAM is not set
1095 +# CONFIG_R3964 is not set
1096 +# CONFIG_RAW_DRIVER is not set
1097 +# CONFIG_TCG_TPM is not set
1098 +CONFIG_I2C=y
1099 +CONFIG_I2C_BOARDINFO=y
1100 +CONFIG_I2C_CHARDEV=y
1101 +CONFIG_I2C_HELPER_AUTO=y
1102 +
1103 +#
1104 +# I2C Hardware Bus support
1105 +#
1106 +
1107 +#
1108 +# I2C system bus drivers (mostly embedded / system-on-chip)
1109 +#
1110 +# CONFIG_I2C_GPIO is not set
1111 +# CONFIG_I2C_OCORES is not set
1112 +CONFIG_I2C_S3C2410=y
1113 +# CONFIG_I2C_SIMTEC is not set
1114 +
1115 +#
1116 +# External I2C/SMBus adapter drivers
1117 +#
1118 +# CONFIG_I2C_PARPORT_LIGHT is not set
1119 +# CONFIG_I2C_TAOS_EVM is not set
1120 +# CONFIG_I2C_TINY_USB is not set
1121 +
1122 +#
1123 +# Other I2C/SMBus bus drivers
1124 +#
1125 +# CONFIG_I2C_PCA_PLATFORM is not set
1126 +# CONFIG_I2C_STUB is not set
1127 +
1128 +#
1129 +# Miscellaneous I2C Chip support
1130 +#
1131 +# CONFIG_DS1682 is not set
1132 +# CONFIG_AT24 is not set
1133 +# CONFIG_SENSORS_EEPROM is not set
1134 +# CONFIG_SENSORS_PCF50606 is not set
1135 +# CONFIG_SENSORS_PCF50633 is not set
1136 +# CONFIG_SENSORS_PCF8574 is not set
1137 +# CONFIG_PCF8575 is not set
1138 +# CONFIG_SENSORS_PCA9539 is not set
1139 +# CONFIG_SENSORS_PCF8591 is not set
1140 +# CONFIG_TPS65010 is not set
1141 +# CONFIG_SENSORS_MAX6875 is not set
1142 +# CONFIG_SENSORS_TSL2550 is not set
1143 +# CONFIG_SENSORS_TSL256X is not set
1144 +CONFIG_PCA9632=y
1145 +# CONFIG_I2C_DEBUG_CORE is not set
1146 +# CONFIG_I2C_DEBUG_ALGO is not set
1147 +# CONFIG_I2C_DEBUG_BUS is not set
1148 +# CONFIG_I2C_DEBUG_CHIP is not set
1149 +CONFIG_SPI=y
1150 +# CONFIG_SPI_DEBUG is not set
1151 +CONFIG_SPI_MASTER=y
1152 +
1153 +#
1154 +# SPI Master Controller Drivers
1155 +#
1156 +CONFIG_SPI_BITBANG=y
1157 +# CONFIG_SPI_S3C24XX is not set
1158 +CONFIG_SPI_S3C24XX_GPIO=y
1159 +
1160 +#
1161 +# SPI Protocol Masters
1162 +#
1163 +# CONFIG_SPI_AT25 is not set
1164 +# CONFIG_SPI_SPIDEV is not set
1165 +# CONFIG_SPI_TLE62X0 is not set
1166 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
1167 +CONFIG_GPIOLIB=y
1168 +CONFIG_DEBUG_GPIO=y
1169 +CONFIG_GPIO_SYSFS=y
1170 +
1171 +#
1172 +# I2C GPIO expanders:
1173 +#
1174 +# CONFIG_GPIO_MAX732X is not set
1175 +# CONFIG_GPIO_PCA953X is not set
1176 +# CONFIG_GPIO_PCF857X is not set
1177 +
1178 +#
1179 +# PCI GPIO expanders:
1180 +#
1181 +
1182 +#
1183 +# SPI GPIO expanders:
1184 +#
1185 +# CONFIG_GPIO_MAX7301 is not set
1186 +# CONFIG_GPIO_MCP23S08 is not set
1187 +# CONFIG_W1 is not set
1188 +CONFIG_POWER_SUPPLY=y
1189 +CONFIG_POWER_SUPPLY_DEBUG=y
1190 +CONFIG_PDA_POWER=y
1191 +CONFIG_APM_POWER=y
1192 +# CONFIG_BATTERY_DS2760 is not set
1193 +# CONFIG_BATTERY_BQ27x00 is not set
1194 +CONFIG_BATTERY_BQ27000_HDQ=y
1195 +CONFIG_GTA02_HDQ=y
1196 +CONFIG_CHARGER_PCF50633=y
1197 +CONFIG_HWMON=y
1198 +# CONFIG_HWMON_VID is not set
1199 +# CONFIG_SENSORS_AD7414 is not set
1200 +# CONFIG_SENSORS_AD7418 is not set
1201 +# CONFIG_SENSORS_ADCXX is not set
1202 +# CONFIG_SENSORS_ADM1021 is not set
1203 +# CONFIG_SENSORS_ADM1025 is not set
1204 +# CONFIG_SENSORS_ADM1026 is not set
1205 +# CONFIG_SENSORS_ADM1029 is not set
1206 +# CONFIG_SENSORS_ADM1031 is not set
1207 +# CONFIG_SENSORS_ADM9240 is not set
1208 +# CONFIG_SENSORS_ADT7470 is not set
1209 +# CONFIG_SENSORS_ADT7473 is not set
1210 +# CONFIG_SENSORS_ATXP1 is not set
1211 +# CONFIG_SENSORS_DS1621 is not set
1212 +# CONFIG_SENSORS_F71805F is not set
1213 +# CONFIG_SENSORS_F71882FG is not set
1214 +# CONFIG_SENSORS_F75375S is not set
1215 +# CONFIG_SENSORS_GL518SM is not set
1216 +# CONFIG_SENSORS_GL520SM is not set
1217 +# CONFIG_SENSORS_IT87 is not set
1218 +# CONFIG_SENSORS_LM63 is not set
1219 +# CONFIG_SENSORS_LM70 is not set
1220 +# CONFIG_SENSORS_LM75 is not set
1221 +# CONFIG_SENSORS_LM77 is not set
1222 +# CONFIG_SENSORS_LM78 is not set
1223 +# CONFIG_SENSORS_LM80 is not set
1224 +# CONFIG_SENSORS_LM83 is not set
1225 +# CONFIG_SENSORS_LM85 is not set
1226 +# CONFIG_SENSORS_LM87 is not set
1227 +# CONFIG_SENSORS_LM90 is not set
1228 +# CONFIG_SENSORS_LM92 is not set
1229 +# CONFIG_SENSORS_LM93 is not set
1230 +# CONFIG_SENSORS_MAX1111 is not set
1231 +# CONFIG_SENSORS_MAX1619 is not set
1232 +# CONFIG_SENSORS_MAX6650 is not set
1233 +# CONFIG_SENSORS_PC87360 is not set
1234 +# CONFIG_SENSORS_PC87427 is not set
1235 +# CONFIG_SENSORS_DME1737 is not set
1236 +# CONFIG_SENSORS_SMSC47M1 is not set
1237 +# CONFIG_SENSORS_SMSC47M192 is not set
1238 +# CONFIG_SENSORS_SMSC47B397 is not set
1239 +# CONFIG_SENSORS_ADS7828 is not set
1240 +# CONFIG_SENSORS_THMC50 is not set
1241 +# CONFIG_SENSORS_VT1211 is not set
1242 +# CONFIG_SENSORS_W83781D is not set
1243 +# CONFIG_SENSORS_W83791D is not set
1244 +# CONFIG_SENSORS_W83792D is not set
1245 +# CONFIG_SENSORS_W83793 is not set
1246 +# CONFIG_SENSORS_W83L785TS is not set
1247 +# CONFIG_SENSORS_W83L786NG is not set
1248 +# CONFIG_SENSORS_W83627HF is not set
1249 +# CONFIG_SENSORS_W83627EHF is not set
1250 +# CONFIG_HWMON_DEBUG_CHIP is not set
1251 +# CONFIG_THERMAL is not set
1252 +# CONFIG_THERMAL_HWMON is not set
1253 +CONFIG_WATCHDOG=y
1254 +# CONFIG_WATCHDOG_NOWAYOUT is not set
1255 +
1256 +#
1257 +# Watchdog Device Drivers
1258 +#
1259 +# CONFIG_SOFT_WATCHDOG is not set
1260 +CONFIG_S3C2410_WATCHDOG=m
1261 +
1262 +#
1263 +# USB-based Watchdog Cards
1264 +#
1265 +# CONFIG_USBPCWATCHDOG is not set
1266 +
1267 +#
1268 +# Sonics Silicon Backplane
1269 +#
1270 +CONFIG_SSB_POSSIBLE=y
1271 +# CONFIG_SSB is not set
1272 +
1273 +#
1274 +# Multifunction device drivers
1275 +#
1276 +# CONFIG_MFD_CORE is not set
1277 +# CONFIG_MFD_SM501 is not set
1278 +# CONFIG_MFD_ASIC3 is not set
1279 +# CONFIG_HTC_EGPIO is not set
1280 +# CONFIG_HTC_PASIC3 is not set
1281 +# CONFIG_MFD_TMIO is not set
1282 +# CONFIG_MFD_T7L66XB is not set
1283 +# CONFIG_MFD_TC6387XB is not set
1284 +# CONFIG_MFD_TC6393XB is not set
1285 +# CONFIG_PMIC_DA903X is not set
1286 +# CONFIG_MFD_WM8400 is not set
1287 +# CONFIG_MFD_WM8350_I2C is not set
1288 +CONFIG_MFD_PCF50633=y
1289 +CONFIG_PCF50633_ADC=y
1290 +CONFIG_PCF50633_GPIO=y
1291 +# CONFIG_MFD_PCF50606 is not set
1292 +CONFIG_MFD_GLAMO=y
1293 +CONFIG_MFD_GLAMO_FB=y
1294 +CONFIG_MFD_GLAMO_SPI_GPIO=y
1295 +CONFIG_MFD_GLAMO_SPI_FB=y
1296 +CONFIG_MFD_GLAMO_MCI=y
1297 +
1298 +#
1299 +# Multimedia devices
1300 +#
1301 +
1302 +#
1303 +# Multimedia core support
1304 +#
1305 +# CONFIG_VIDEO_DEV is not set
1306 +# CONFIG_DVB_CORE is not set
1307 +# CONFIG_VIDEO_MEDIA is not set
1308 +
1309 +#
1310 +# Multimedia drivers
1311 +#
1312 +CONFIG_DAB=y
1313 +# CONFIG_USB_DABUSB is not set
1314 +
1315 +#
1316 +# Graphics support
1317 +#
1318 +# CONFIG_VGASTATE is not set
1319 +CONFIG_VIDEO_OUTPUT_CONTROL=y
1320 +CONFIG_FB=y
1321 +# CONFIG_FIRMWARE_EDID is not set
1322 +# CONFIG_FB_DDC is not set
1323 +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
1324 +CONFIG_FB_CFB_FILLRECT=y
1325 +CONFIG_FB_CFB_COPYAREA=y
1326 +CONFIG_FB_CFB_IMAGEBLIT=y
1327 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1328 +# CONFIG_FB_SYS_FILLRECT is not set
1329 +# CONFIG_FB_SYS_COPYAREA is not set
1330 +# CONFIG_FB_SYS_IMAGEBLIT is not set
1331 +# CONFIG_FB_FOREIGN_ENDIAN is not set
1332 +# CONFIG_FB_SYS_FOPS is not set
1333 +# CONFIG_FB_SVGALIB is not set
1334 +# CONFIG_FB_MACMODES is not set
1335 +# CONFIG_FB_BACKLIGHT is not set
1336 +# CONFIG_FB_MODE_HELPERS is not set
1337 +# CONFIG_FB_TILEBLITTING is not set
1338 +
1339 +#
1340 +# Frame buffer hardware drivers
1341 +#
1342 +# CONFIG_FB_UVESA is not set
1343 +# CONFIG_FB_S1D13XXX is not set
1344 +CONFIG_FB_S3C2410=y
1345 +# CONFIG_FB_S3C2410_DEBUG is not set
1346 +# CONFIG_FB_VIRTUAL is not set
1347 +# CONFIG_FB_METRONOME is not set
1348 +# CONFIG_FB_MB862XX is not set
1349 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
1350 +CONFIG_LCD_CLASS_DEVICE=y
1351 +CONFIG_LCD_LTV350QV=y
1352 +# CONFIG_LCD_ILI9320 is not set
1353 +# CONFIG_LCD_TDO24M is not set
1354 +# CONFIG_LCD_VGG2432A4 is not set
1355 +# CONFIG_LCD_PLATFORM is not set
1356 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
1357 +CONFIG_BACKLIGHT_CORGI=y
1358 +# CONFIG_BACKLIGHT_PWM is not set
1359 +
1360 +#
1361 +# Display device support
1362 +#
1363 +CONFIG_DISPLAY_SUPPORT=y
1364 +
1365 +#
1366 +# Display hardware drivers
1367 +#
1368 +CONFIG_DISPLAY_JBT6K74=y
1369 +
1370 +#
1371 +# Console display driver support
1372 +#
1373 +# CONFIG_VGA_CONSOLE is not set
1374 +CONFIG_DUMMY_CONSOLE=y
1375 +CONFIG_FRAMEBUFFER_CONSOLE=y
1376 +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1377 +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1378 +CONFIG_FONTS=y
1379 +# CONFIG_FONT_8x8 is not set
1380 +# CONFIG_FONT_8x16 is not set
1381 +CONFIG_FONT_6x11=y
1382 +# CONFIG_FONT_7x14 is not set
1383 +# CONFIG_FONT_PEARL_8x8 is not set
1384 +# CONFIG_FONT_ACORN_8x8 is not set
1385 +# CONFIG_FONT_MINI_4x6 is not set
1386 +# CONFIG_FONT_SUN8x16 is not set
1387 +# CONFIG_FONT_SUN12x22 is not set
1388 +# CONFIG_FONT_10x18 is not set
1389 +# CONFIG_LOGO is not set
1390 +CONFIG_SOUND=y
1391 +CONFIG_SOUND_OSS_CORE=y
1392 +CONFIG_SND=y
1393 +CONFIG_SND_TIMER=y
1394 +CONFIG_SND_PCM=y
1395 +CONFIG_SND_HWDEP=m
1396 +CONFIG_SND_RAWMIDI=m
1397 +# CONFIG_SND_SEQUENCER is not set
1398 +CONFIG_SND_OSSEMUL=y
1399 +CONFIG_SND_MIXER_OSS=y
1400 +CONFIG_SND_PCM_OSS=y
1401 +CONFIG_SND_PCM_OSS_PLUGINS=y
1402 +# CONFIG_SND_DYNAMIC_MINORS is not set
1403 +CONFIG_SND_SUPPORT_OLD_API=y
1404 +CONFIG_SND_VERBOSE_PROCFS=y
1405 +# CONFIG_SND_VERBOSE_PRINTK is not set
1406 +CONFIG_SND_DEBUG=y
1407 +# CONFIG_SND_DEBUG_VERBOSE is not set
1408 +CONFIG_SND_PCM_XRUN_DEBUG=y
1409 +CONFIG_SND_DRIVERS=y
1410 +# CONFIG_SND_DUMMY is not set
1411 +# CONFIG_SND_MTPAV is not set
1412 +# CONFIG_SND_SERIAL_U16550 is not set
1413 +# CONFIG_SND_MPU401 is not set
1414 +CONFIG_SND_ARM=y
1415 +# CONFIG_SND_SPI is not set
1416 +CONFIG_SND_USB=y
1417 +CONFIG_SND_USB_AUDIO=m
1418 +# CONFIG_SND_USB_CAIAQ is not set
1419 +CONFIG_SND_SOC=y
1420 +CONFIG_SND_S3C24XX_SOC=y
1421 +CONFIG_SND_S3C24XX_SOC_I2S=y
1422 +CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753=y
1423 +# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
1424 +# CONFIG_SND_SOC_ALL_CODECS is not set
1425 +CONFIG_SND_SOC_WM8753=y
1426 +# CONFIG_SOUND_PRIME is not set
1427 +CONFIG_HID_SUPPORT=y
1428 +CONFIG_HID=y
1429 +# CONFIG_HID_DEBUG is not set
1430 +# CONFIG_HIDRAW is not set
1431 +
1432 +#
1433 +# USB Input Devices
1434 +#
1435 +CONFIG_USB_HID=y
1436 +CONFIG_HID_PID=y
1437 +# CONFIG_USB_HIDDEV is not set
1438 +
1439 +#
1440 +# Special HID drivers
1441 +#
1442 +CONFIG_HID_COMPAT=y
1443 +CONFIG_HID_A4TECH=y
1444 +CONFIG_HID_APPLE=y
1445 +CONFIG_HID_BELKIN=y
1446 +CONFIG_HID_BRIGHT=y
1447 +CONFIG_HID_CHERRY=y
1448 +CONFIG_HID_CHICONY=y
1449 +CONFIG_HID_CYPRESS=y
1450 +CONFIG_HID_DELL=y
1451 +CONFIG_HID_EZKEY=y
1452 +CONFIG_HID_GYRATION=y
1453 +CONFIG_HID_LOGITECH=y
1454 +# CONFIG_LOGITECH_FF is not set
1455 +# CONFIG_LOGIRUMBLEPAD2_FF is not set
1456 +CONFIG_HID_MICROSOFT=y
1457 +CONFIG_HID_MONTEREY=y
1458 +CONFIG_HID_PANTHERLORD=y
1459 +# CONFIG_PANTHERLORD_FF is not set
1460 +CONFIG_HID_PETALYNX=y
1461 +CONFIG_HID_SAMSUNG=y
1462 +CONFIG_HID_SONY=y
1463 +CONFIG_HID_SUNPLUS=y
1464 +# CONFIG_THRUSTMASTER_FF is not set
1465 +# CONFIG_ZEROPLUS_FF is not set
1466 +CONFIG_USB_SUPPORT=y
1467 +CONFIG_USB_ARCH_HAS_HCD=y
1468 +CONFIG_USB_ARCH_HAS_OHCI=y
1469 +# CONFIG_USB_ARCH_HAS_EHCI is not set
1470 +CONFIG_USB=y
1471 +# CONFIG_USB_DEBUG is not set
1472 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1473 +
1474 +#
1475 +# Miscellaneous USB options
1476 +#
1477 +CONFIG_USB_DEVICEFS=y
1478 +CONFIG_USB_DEVICE_CLASS=y
1479 +# CONFIG_USB_DYNAMIC_MINORS is not set
1480 +CONFIG_USB_SUSPEND=y
1481 +# CONFIG_USB_OTG is not set
1482 +CONFIG_USB_MON=y
1483 +# CONFIG_USB_WUSB is not set
1484 +# CONFIG_USB_WUSB_CBAF is not set
1485 +
1486 +#
1487 +# USB Host Controller Drivers
1488 +#
1489 +# CONFIG_USB_C67X00_HCD is not set
1490 +# CONFIG_USB_ISP116X_HCD is not set
1491 +# CONFIG_USB_ISP1760_HCD is not set
1492 +CONFIG_USB_OHCI_HCD=y
1493 +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1494 +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1495 +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1496 +# CONFIG_USB_SL811_HCD is not set
1497 +# CONFIG_USB_R8A66597_HCD is not set
1498 +# CONFIG_USB_HWA_HCD is not set
1499 +# CONFIG_USB_MUSB_HDRC is not set
1500 +# CONFIG_USB_GADGET_MUSB_HDRC is not set
1501 +
1502 +#
1503 +# USB Device Class drivers
1504 +#
1505 +CONFIG_USB_ACM=y
1506 +CONFIG_USB_PRINTER=m
1507 +# CONFIG_USB_WDM is not set
1508 +CONFIG_USB_TMC=m
1509 +
1510 +#
1511 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1512 +#
1513 +
1514 +#
1515 +# may also be needed; see USB_STORAGE Help for more information
1516 +#
1517 +CONFIG_USB_STORAGE=y
1518 +# CONFIG_USB_STORAGE_DEBUG is not set
1519 +CONFIG_USB_STORAGE_DATAFAB=y
1520 +CONFIG_USB_STORAGE_FREECOM=y
1521 +# CONFIG_USB_STORAGE_ISD200 is not set
1522 +CONFIG_USB_STORAGE_DPCM=y
1523 +CONFIG_USB_STORAGE_USBAT=y
1524 +CONFIG_USB_STORAGE_SDDR09=y
1525 +CONFIG_USB_STORAGE_SDDR55=y
1526 +CONFIG_USB_STORAGE_JUMPSHOT=y
1527 +CONFIG_USB_STORAGE_ALAUDA=y
1528 +# CONFIG_USB_STORAGE_ONETOUCH is not set
1529 +CONFIG_USB_STORAGE_KARMA=y
1530 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1531 +CONFIG_USB_LIBUSUAL=y
1532 +
1533 +#
1534 +# USB Imaging devices
1535 +#
1536 +# CONFIG_USB_MDC800 is not set
1537 +# CONFIG_USB_MICROTEK is not set
1538 +
1539 +#
1540 +# USB port drivers
1541 +#
1542 +CONFIG_USB_SERIAL=y
1543 +CONFIG_USB_SERIAL_CONSOLE=y
1544 +CONFIG_USB_EZUSB=y
1545 +CONFIG_USB_SERIAL_GENERIC=y
1546 +CONFIG_USB_SERIAL_AIRCABLE=m
1547 +CONFIG_USB_SERIAL_ARK3116=m
1548 +CONFIG_USB_SERIAL_BELKIN=m
1549 +# CONFIG_USB_SERIAL_CH341 is not set
1550 +CONFIG_USB_SERIAL_WHITEHEAT=m
1551 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1552 +CONFIG_USB_SERIAL_CP2101=m
1553 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1554 +CONFIG_USB_SERIAL_EMPEG=m
1555 +CONFIG_USB_SERIAL_FTDI_SIO=m
1556 +CONFIG_USB_SERIAL_FUNSOFT=m
1557 +CONFIG_USB_SERIAL_VISOR=m
1558 +CONFIG_USB_SERIAL_IPAQ=m
1559 +CONFIG_USB_SERIAL_IR=m
1560 +CONFIG_USB_SERIAL_EDGEPORT=m
1561 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1562 +CONFIG_USB_SERIAL_GARMIN=m
1563 +CONFIG_USB_SERIAL_IPW=m
1564 +# CONFIG_USB_SERIAL_IUU is not set
1565 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1566 +CONFIG_USB_SERIAL_KEYSPAN=m
1567 +CONFIG_USB_SERIAL_KLSI=m
1568 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1569 +CONFIG_USB_SERIAL_MCT_U232=m
1570 +CONFIG_USB_SERIAL_MOS7720=m
1571 +CONFIG_USB_SERIAL_MOS7840=m
1572 +# CONFIG_USB_SERIAL_MOTOROLA is not set
1573 +CONFIG_USB_SERIAL_NAVMAN=m
1574 +CONFIG_USB_SERIAL_PL2303=m
1575 +# CONFIG_USB_SERIAL_OTI6858 is not set
1576 +# CONFIG_USB_SERIAL_SPCP8X5 is not set
1577 +CONFIG_USB_SERIAL_HP4X=m
1578 +CONFIG_USB_SERIAL_SAFE=m
1579 +CONFIG_USB_SERIAL_SAFE_PADDED=y
1580 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1581 +CONFIG_USB_SERIAL_TI=m
1582 +CONFIG_USB_SERIAL_CYBERJACK=m
1583 +CONFIG_USB_SERIAL_XIRCOM=m
1584 +CONFIG_USB_SERIAL_OPTION=y
1585 +CONFIG_USB_SERIAL_OMNINET=m
1586 +# CONFIG_USB_SERIAL_DEBUG is not set
1587 +
1588 +#
1589 +# USB Miscellaneous drivers
1590 +#
1591 +# CONFIG_USB_EMI62 is not set
1592 +# CONFIG_USB_EMI26 is not set
1593 +# CONFIG_USB_ADUTUX is not set
1594 +# CONFIG_USB_SEVSEG is not set
1595 +# CONFIG_USB_RIO500 is not set
1596 +# CONFIG_USB_LEGOTOWER is not set
1597 +# CONFIG_USB_LCD is not set
1598 +CONFIG_USB_BERRY_CHARGE=m
1599 +# CONFIG_USB_LED is not set
1600 +# CONFIG_USB_CYPRESS_CY7C63 is not set
1601 +# CONFIG_USB_CYTHERM is not set
1602 +# CONFIG_USB_PHIDGET is not set
1603 +# CONFIG_USB_IDMOUSE is not set
1604 +# CONFIG_USB_FTDI_ELAN is not set
1605 +# CONFIG_USB_APPLEDISPLAY is not set
1606 +# CONFIG_USB_LD is not set
1607 +CONFIG_USB_TRANCEVIBRATOR=m
1608 +CONFIG_USB_IOWARRIOR=m
1609 +# CONFIG_USB_TEST is not set
1610 +# CONFIG_USB_ISIGHTFW is not set
1611 +# CONFIG_USB_VST is not set
1612 +CONFIG_USB_GADGET=y
1613 +# CONFIG_USB_GADGET_DEBUG is not set
1614 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
1615 +# CONFIG_USB_GADGET_DEBUG_FS is not set
1616 +CONFIG_USB_GADGET_VBUS_DRAW=500
1617 +CONFIG_USB_GADGET_SELECTED=y
1618 +# CONFIG_USB_GADGET_AT91 is not set
1619 +# CONFIG_USB_GADGET_ATMEL_USBA is not set
1620 +# CONFIG_USB_GADGET_FSL_USB2 is not set
1621 +# CONFIG_USB_GADGET_LH7A40X is not set
1622 +# CONFIG_USB_GADGET_OMAP is not set
1623 +# CONFIG_USB_GADGET_PXA25X is not set
1624 +# CONFIG_USB_GADGET_PXA27X is not set
1625 +CONFIG_USB_GADGET_S3C2410=y
1626 +CONFIG_USB_S3C2410=y
1627 +CONFIG_USB_S3C2410_DEBUG=y
1628 +# CONFIG_USB_GADGET_M66592 is not set
1629 +# CONFIG_USB_GADGET_AMD5536UDC is not set
1630 +# CONFIG_USB_GADGET_FSL_QE is not set
1631 +# CONFIG_USB_GADGET_NET2280 is not set
1632 +# CONFIG_USB_GADGET_GOKU is not set
1633 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
1634 +# CONFIG_USB_GADGET_DUALSPEED is not set
1635 +# CONFIG_USB_ZERO is not set
1636 +CONFIG_USB_ETH=y
1637 +CONFIG_USB_ETH_RNDIS=y
1638 +# CONFIG_USB_GADGETFS is not set
1639 +# CONFIG_USB_FILE_STORAGE is not set
1640 +# CONFIG_USB_G_SERIAL is not set
1641 +# CONFIG_USB_MIDI_GADGET is not set
1642 +# CONFIG_USB_G_PRINTER is not set
1643 +# CONFIG_USB_CDC_COMPOSITE is not set
1644 +CONFIG_AR6000_WLAN=y
1645 +CONFIG_MMC=y
1646 +# CONFIG_MMC_DEBUG is not set
1647 +CONFIG_MMC_UNSAFE_RESUME=y
1648 +
1649 +#
1650 +# MMC/SD/SDIO Card Drivers
1651 +#
1652 +CONFIG_MMC_BLOCK=y
1653 +CONFIG_MMC_BLOCK_BOUNCE=y
1654 +# CONFIG_SDIO_UART is not set
1655 +# CONFIG_MMC_TEST is not set
1656 +
1657 +#
1658 +# MMC/SD/SDIO Host Controller Drivers
1659 +#
1660 +CONFIG_MMC_SDHCI=y
1661 +CONFIG_MMC_SDHCI_S3C=y
1662 +# CONFIG_MMC_SPI is not set
1663 +CONFIG_MMC_S3C=y
1664 +# CONFIG_MEMSTICK is not set
1665 +# CONFIG_ACCESSIBILITY is not set
1666 +CONFIG_NEW_LEDS=y
1667 +CONFIG_LEDS_CLASS=y
1668 +
1669 +#
1670 +# LED drivers
1671 +#
1672 +CONFIG_LEDS_S3C24XX=m
1673 +# CONFIG_LEDS_PCA9532 is not set
1674 +CONFIG_LEDS_GPIO=y
1675 +# CONFIG_LEDS_PCA955X is not set
1676 +CONFIG_LEDS_NEO1973_VIBRATOR=y
1677 +CONFIG_LEDS_NEO1973_GTA02=y
1678 +
1679 +#
1680 +# LED Triggers
1681 +#
1682 +CONFIG_LEDS_TRIGGERS=y
1683 +CONFIG_LEDS_TRIGGER_TIMER=y
1684 +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
1685 +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
1686 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1687 +CONFIG_RTC_LIB=y
1688 +CONFIG_RTC_CLASS=y
1689 +CONFIG_RTC_HCTOSYS=y
1690 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1691 +CONFIG_RTC_DEBUG=y
1692 +
1693 +#
1694 +# RTC interfaces
1695 +#
1696 +CONFIG_RTC_INTF_SYSFS=y
1697 +CONFIG_RTC_INTF_PROC=y
1698 +CONFIG_RTC_INTF_DEV=y
1699 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1700 +# CONFIG_RTC_DRV_TEST is not set
1701 +
1702 +#
1703 +# I2C RTC drivers
1704 +#
1705 +# CONFIG_RTC_DRV_DS1307 is not set
1706 +# CONFIG_RTC_DRV_DS1374 is not set
1707 +# CONFIG_RTC_DRV_DS1672 is not set
1708 +# CONFIG_RTC_DRV_MAX6900 is not set
1709 +# CONFIG_RTC_DRV_RS5C372 is not set
1710 +# CONFIG_RTC_DRV_ISL1208 is not set
1711 +# CONFIG_RTC_DRV_X1205 is not set
1712 +# CONFIG_RTC_DRV_PCF8563 is not set
1713 +# CONFIG_RTC_DRV_PCF8583 is not set
1714 +CONFIG_RTC_DRV_PCF50633=y
1715 +# CONFIG_RTC_DRV_PCF50606 is not set
1716 +# CONFIG_RTC_DRV_M41T80 is not set
1717 +# CONFIG_RTC_DRV_S35390A is not set
1718 +# CONFIG_RTC_DRV_FM3130 is not set
1719 +
1720 +#
1721 +# SPI RTC drivers
1722 +#
1723 +# CONFIG_RTC_DRV_M41T94 is not set
1724 +# CONFIG_RTC_DRV_DS1305 is not set
1725 +# CONFIG_RTC_DRV_MAX6902 is not set
1726 +# CONFIG_RTC_DRV_R9701 is not set
1727 +# CONFIG_RTC_DRV_RS5C348 is not set
1728 +# CONFIG_RTC_DRV_DS3234 is not set
1729 +
1730 +#
1731 +# Platform RTC drivers
1732 +#
1733 +# CONFIG_RTC_DRV_CMOS is not set
1734 +# CONFIG_RTC_DRV_DS1286 is not set
1735 +# CONFIG_RTC_DRV_DS1511 is not set
1736 +# CONFIG_RTC_DRV_DS1553 is not set
1737 +# CONFIG_RTC_DRV_DS1742 is not set
1738 +# CONFIG_RTC_DRV_STK17TA8 is not set
1739 +# CONFIG_RTC_DRV_M48T86 is not set
1740 +# CONFIG_RTC_DRV_M48T35 is not set
1741 +# CONFIG_RTC_DRV_M48T59 is not set
1742 +# CONFIG_RTC_DRV_BQ4802 is not set
1743 +# CONFIG_RTC_DRV_V3020 is not set
1744 +
1745 +#
1746 +# on-CPU RTC drivers
1747 +#
1748 +CONFIG_RTC_DRV_S3C=m
1749 +CONFIG_DMADEVICES=y
1750 +
1751 +#
1752 +# DMA Devices
1753 +#
1754 +
1755 +#
1756 +# Android
1757 +#
1758 +CONFIG_ANDROID_BINDER_IPC=y
1759 +CONFIG_ANDROID_POWER=y
1760 +CONFIG_ANDROID_POWER_STAT=y
1761 +CONFIG_ANDROID_POWER_ALARM=y
1762 +CONFIG_ANDROID_LOGGER=y
1763 +# CONFIG_ANDROID_RAM_CONSOLE is not set
1764 +# CONFIG_ANDROID_TIMED_GPIO is not set
1765 +# CONFIG_ANDROID_PARANOID_NETWORK is not set
1766 +CONFIG_REGULATOR=y
1767 +CONFIG_REGULATOR_DEBUG=y
1768 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
1769 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1770 +# CONFIG_REGULATOR_BQ24022 is not set
1771 +CONFIG_REGULATOR_PCF50633=y
1772 +CONFIG_UIO=y
1773 +CONFIG_UIO_PDRV=y
1774 +# CONFIG_UIO_PDRV_GENIRQ is not set
1775 +# CONFIG_UIO_SMX is not set
1776 +# CONFIG_UIO_SERCOS3 is not set
1777 +
1778 +#
1779 +# File systems
1780 +#
1781 +CONFIG_EXT2_FS=y
1782 +# CONFIG_EXT2_FS_XATTR is not set
1783 +# CONFIG_EXT2_FS_XIP is not set
1784 +CONFIG_EXT3_FS=y
1785 +# CONFIG_EXT3_FS_XATTR is not set
1786 +CONFIG_EXT4_FS=y
1787 +CONFIG_EXT4DEV_COMPAT=y
1788 +CONFIG_EXT4_FS_XATTR=y
1789 +# CONFIG_EXT4_FS_POSIX_ACL is not set
1790 +CONFIG_EXT4_FS_SECURITY=y
1791 +CONFIG_JBD=y
1792 +# CONFIG_JBD_DEBUG is not set
1793 +CONFIG_JBD2=y
1794 +# CONFIG_JBD2_DEBUG is not set
1795 +CONFIG_FS_MBCACHE=y
1796 +# CONFIG_REISERFS_FS is not set
1797 +# CONFIG_JFS_FS is not set
1798 +CONFIG_FS_POSIX_ACL=y
1799 +CONFIG_FILE_LOCKING=y
1800 +# CONFIG_XFS_FS is not set
1801 +# CONFIG_OCFS2_FS is not set
1802 +CONFIG_DNOTIFY=y
1803 +CONFIG_INOTIFY=y
1804 +CONFIG_INOTIFY_USER=y
1805 +# CONFIG_QUOTA is not set
1806 +# CONFIG_AUTOFS_FS is not set
1807 +# CONFIG_AUTOFS4_FS is not set
1808 +CONFIG_FUSE_FS=m
1809 +
1810 +#
1811 +# CD-ROM/DVD Filesystems
1812 +#
1813 +CONFIG_ISO9660_FS=m
1814 +CONFIG_JOLIET=y
1815 +# CONFIG_ZISOFS is not set
1816 +# CONFIG_UDF_FS is not set
1817 +
1818 +#
1819 +# DOS/FAT/NT Filesystems
1820 +#
1821 +CONFIG_FAT_FS=y
1822 +CONFIG_MSDOS_FS=y
1823 +CONFIG_VFAT_FS=y
1824 +CONFIG_FAT_DEFAULT_CODEPAGE=437
1825 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1826 +# CONFIG_NTFS_FS is not set
1827 +
1828 +#
1829 +# Pseudo filesystems
1830 +#
1831 +CONFIG_PROC_FS=y
1832 +CONFIG_PROC_SYSCTL=y
1833 +CONFIG_PROC_PAGE_MONITOR=y
1834 +CONFIG_SYSFS=y
1835 +CONFIG_TMPFS=y
1836 +# CONFIG_TMPFS_POSIX_ACL is not set
1837 +# CONFIG_HUGETLB_PAGE is not set
1838 +CONFIG_CONFIGFS_FS=m
1839 +
1840 +#
1841 +# Miscellaneous filesystems
1842 +#
1843 +# CONFIG_ADFS_FS is not set
1844 +# CONFIG_AFFS_FS is not set
1845 +# CONFIG_HFS_FS is not set
1846 +# CONFIG_HFSPLUS_FS is not set
1847 +# CONFIG_BEFS_FS is not set
1848 +# CONFIG_BFS_FS is not set
1849 +# CONFIG_EFS_FS is not set
1850 +CONFIG_JFFS2_FS=y
1851 +CONFIG_JFFS2_FS_DEBUG=0
1852 +CONFIG_JFFS2_FS_WRITEBUFFER=y
1853 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1854 +CONFIG_JFFS2_SUMMARY=y
1855 +# CONFIG_JFFS2_FS_XATTR is not set
1856 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1857 +CONFIG_JFFS2_ZLIB=y
1858 +# CONFIG_JFFS2_LZO is not set
1859 +CONFIG_JFFS2_RTIME=y
1860 +# CONFIG_JFFS2_RUBIN is not set
1861 +CONFIG_CRAMFS=y
1862 +# CONFIG_VXFS_FS is not set
1863 +# CONFIG_MINIX_FS is not set
1864 +# CONFIG_OMFS_FS is not set
1865 +# CONFIG_HPFS_FS is not set
1866 +# CONFIG_QNX4FS_FS is not set
1867 +CONFIG_ROMFS_FS=y
1868 +# CONFIG_SYSV_FS is not set
1869 +# CONFIG_UFS_FS is not set
1870 +CONFIG_NETWORK_FILESYSTEMS=y
1871 +# CONFIG_NFS_FS is not set
1872 +CONFIG_NFSD=y
1873 +CONFIG_NFSD_V2_ACL=y
1874 +CONFIG_NFSD_V3=y
1875 +CONFIG_NFSD_V3_ACL=y
1876 +# CONFIG_NFSD_V4 is not set
1877 +CONFIG_LOCKD=y
1878 +CONFIG_LOCKD_V4=y
1879 +CONFIG_EXPORTFS=y
1880 +CONFIG_NFS_ACL_SUPPORT=y
1881 +CONFIG_NFS_COMMON=y
1882 +CONFIG_SUNRPC=y
1883 +# CONFIG_SUNRPC_REGISTER_V4 is not set
1884 +# CONFIG_RPCSEC_GSS_KRB5 is not set
1885 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
1886 +# CONFIG_SMB_FS is not set
1887 +CONFIG_CIFS=m
1888 +# CONFIG_CIFS_STATS is not set
1889 +# CONFIG_CIFS_WEAK_PW_HASH is not set
1890 +# CONFIG_CIFS_XATTR is not set
1891 +# CONFIG_CIFS_DEBUG2 is not set
1892 +# CONFIG_CIFS_EXPERIMENTAL is not set
1893 +# CONFIG_NCP_FS is not set
1894 +# CONFIG_CODA_FS is not set
1895 +# CONFIG_AFS_FS is not set
1896 +
1897 +#
1898 +# Partition Types
1899 +#
1900 +CONFIG_PARTITION_ADVANCED=y
1901 +# CONFIG_ACORN_PARTITION is not set
1902 +# CONFIG_OSF_PARTITION is not set
1903 +# CONFIG_AMIGA_PARTITION is not set
1904 +# CONFIG_ATARI_PARTITION is not set
1905 +# CONFIG_MAC_PARTITION is not set
1906 +CONFIG_MSDOS_PARTITION=y
1907 +# CONFIG_BSD_DISKLABEL is not set
1908 +# CONFIG_MINIX_SUBPARTITION is not set
1909 +# CONFIG_SOLARIS_X86_PARTITION is not set
1910 +# CONFIG_UNIXWARE_DISKLABEL is not set
1911 +# CONFIG_LDM_PARTITION is not set
1912 +# CONFIG_SGI_PARTITION is not set
1913 +# CONFIG_ULTRIX_PARTITION is not set
1914 +# CONFIG_SUN_PARTITION is not set
1915 +# CONFIG_KARMA_PARTITION is not set
1916 +# CONFIG_EFI_PARTITION is not set
1917 +# CONFIG_SYSV68_PARTITION is not set
1918 +CONFIG_NLS=y
1919 +CONFIG_NLS_DEFAULT="iso8859-1"
1920 +CONFIG_NLS_CODEPAGE_437=y
1921 +# CONFIG_NLS_CODEPAGE_737 is not set
1922 +# CONFIG_NLS_CODEPAGE_775 is not set
1923 +CONFIG_NLS_CODEPAGE_850=m
1924 +# CONFIG_NLS_CODEPAGE_852 is not set
1925 +# CONFIG_NLS_CODEPAGE_855 is not set
1926 +# CONFIG_NLS_CODEPAGE_857 is not set
1927 +# CONFIG_NLS_CODEPAGE_860 is not set
1928 +# CONFIG_NLS_CODEPAGE_861 is not set
1929 +# CONFIG_NLS_CODEPAGE_862 is not set
1930 +# CONFIG_NLS_CODEPAGE_863 is not set
1931 +# CONFIG_NLS_CODEPAGE_864 is not set
1932 +# CONFIG_NLS_CODEPAGE_865 is not set
1933 +# CONFIG_NLS_CODEPAGE_866 is not set
1934 +# CONFIG_NLS_CODEPAGE_869 is not set
1935 +CONFIG_NLS_CODEPAGE_936=m
1936 +CONFIG_NLS_CODEPAGE_950=m
1937 +# CONFIG_NLS_CODEPAGE_932 is not set
1938 +# CONFIG_NLS_CODEPAGE_949 is not set
1939 +# CONFIG_NLS_CODEPAGE_874 is not set
1940 +# CONFIG_NLS_ISO8859_8 is not set
1941 +# CONFIG_NLS_CODEPAGE_1250 is not set
1942 +# CONFIG_NLS_CODEPAGE_1251 is not set
1943 +# CONFIG_NLS_ASCII is not set
1944 +CONFIG_NLS_ISO8859_1=y
1945 +# CONFIG_NLS_ISO8859_2 is not set
1946 +# CONFIG_NLS_ISO8859_3 is not set
1947 +# CONFIG_NLS_ISO8859_4 is not set
1948 +# CONFIG_NLS_ISO8859_5 is not set
1949 +# CONFIG_NLS_ISO8859_6 is not set
1950 +# CONFIG_NLS_ISO8859_7 is not set
1951 +# CONFIG_NLS_ISO8859_9 is not set
1952 +# CONFIG_NLS_ISO8859_13 is not set
1953 +# CONFIG_NLS_ISO8859_14 is not set
1954 +# CONFIG_NLS_ISO8859_15 is not set
1955 +# CONFIG_NLS_KOI8_R is not set
1956 +# CONFIG_NLS_KOI8_U is not set
1957 +CONFIG_NLS_UTF8=m
1958 +# CONFIG_DLM is not set
1959 +
1960 +#
1961 +# Kernel hacking
1962 +#
1963 +CONFIG_PRINTK_TIME=y
1964 +CONFIG_ENABLE_WARN_DEPRECATED=y
1965 +CONFIG_ENABLE_MUST_CHECK=y
1966 +CONFIG_FRAME_WARN=1024
1967 +CONFIG_MAGIC_SYSRQ=y
1968 +# CONFIG_UNUSED_SYMBOLS is not set
1969 +CONFIG_DEBUG_FS=y
1970 +# CONFIG_HEADERS_CHECK is not set
1971 +CONFIG_DEBUG_KERNEL=y
1972 +CONFIG_DEBUG_SHIRQ=y
1973 +CONFIG_DETECT_SOFTLOCKUP=y
1974 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
1975 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
1976 +CONFIG_SCHED_DEBUG=y
1977 +CONFIG_SCHEDSTATS=y
1978 +CONFIG_TIMER_STATS=y
1979 +# CONFIG_DEBUG_OBJECTS is not set
1980 +# CONFIG_DEBUG_SLAB is not set
1981 +CONFIG_DEBUG_PREEMPT=y
1982 +# CONFIG_DEBUG_RT_MUTEXES is not set
1983 +# CONFIG_RT_MUTEX_TESTER is not set
1984 +CONFIG_DEBUG_SPINLOCK=y
1985 +CONFIG_DEBUG_MUTEXES=y
1986 +CONFIG_DEBUG_LOCK_ALLOC=y
1987 +# CONFIG_PROVE_LOCKING is not set
1988 +CONFIG_LOCKDEP=y
1989 +CONFIG_LOCK_STAT=y
1990 +CONFIG_DEBUG_LOCKDEP=y
1991 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
1992 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1993 +CONFIG_STACKTRACE=y
1994 +# CONFIG_DEBUG_KOBJECT is not set
1995 +CONFIG_DEBUG_BUGVERBOSE=y
1996 +CONFIG_DEBUG_INFO=y
1997 +# CONFIG_DEBUG_VM is not set
1998 +# CONFIG_DEBUG_WRITECOUNT is not set
1999 +CONFIG_DEBUG_MEMORY_INIT=y
2000 +# CONFIG_DEBUG_LIST is not set
2001 +CONFIG_DEBUG_SG=y
2002 +CONFIG_FRAME_POINTER=y
2003 +# CONFIG_BOOT_PRINTK_DELAY is not set
2004 +# CONFIG_RCU_TORTURE_TEST is not set
2005 +CONFIG_RCU_CPU_STALL_DETECTOR=y
2006 +# CONFIG_BACKTRACE_SELF_TEST is not set
2007 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
2008 +# CONFIG_FAULT_INJECTION is not set
2009 +CONFIG_LATENCYTOP=y
2010 +CONFIG_SYSCTL_SYSCALL_CHECK=y
2011 +CONFIG_HAVE_FUNCTION_TRACER=y
2012 +
2013 +#
2014 +# Tracers
2015 +#
2016 +# CONFIG_FUNCTION_TRACER is not set
2017 +# CONFIG_SCHED_TRACER is not set
2018 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
2019 +# CONFIG_BOOT_TRACER is not set
2020 +# CONFIG_STACK_TRACER is not set
2021 +CONFIG_DYNAMIC_PRINTK_DEBUG=y
2022 +# CONFIG_SAMPLES is not set
2023 +CONFIG_HAVE_ARCH_KGDB=y
2024 +# CONFIG_KGDB is not set
2025 +# CONFIG_DEBUG_USER is not set
2026 +CONFIG_DEBUG_ERRORS=y
2027 +# CONFIG_DEBUG_STACK_USAGE is not set
2028 +# CONFIG_DEBUG_LL is not set
2029 +CONFIG_DEBUG_S3C_UART=2
2030 +
2031 +#
2032 +# Security options
2033 +#
2034 +# CONFIG_KEYS is not set
2035 +# CONFIG_SECURITY is not set
2036 +CONFIG_SECURITYFS=y
2037 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
2038 +CONFIG_CRYPTO=y
2039 +
2040 +#
2041 +# Crypto core or helper
2042 +#
2043 +CONFIG_CRYPTO_FIPS=y
2044 +CONFIG_CRYPTO_ALGAPI=y
2045 +CONFIG_CRYPTO_AEAD=y
2046 +CONFIG_CRYPTO_BLKCIPHER=y
2047 +CONFIG_CRYPTO_HASH=y
2048 +CONFIG_CRYPTO_RNG=y
2049 +CONFIG_CRYPTO_MANAGER=y
2050 +CONFIG_CRYPTO_GF128MUL=m
2051 +CONFIG_CRYPTO_NULL=m
2052 +# CONFIG_CRYPTO_CRYPTD is not set
2053 +CONFIG_CRYPTO_AUTHENC=m
2054 +CONFIG_CRYPTO_TEST=m
2055 +
2056 +#
2057 +# Authenticated Encryption with Associated Data
2058 +#
2059 +# CONFIG_CRYPTO_CCM is not set
2060 +# CONFIG_CRYPTO_GCM is not set
2061 +# CONFIG_CRYPTO_SEQIV is not set
2062 +
2063 +#
2064 +# Block modes
2065 +#
2066 +CONFIG_CRYPTO_CBC=y
2067 +# CONFIG_CRYPTO_CTR is not set
2068 +# CONFIG_CRYPTO_CTS is not set
2069 +CONFIG_CRYPTO_ECB=y
2070 +CONFIG_CRYPTO_LRW=m
2071 +CONFIG_CRYPTO_PCBC=m
2072 +# CONFIG_CRYPTO_XTS is not set
2073 +
2074 +#
2075 +# Hash modes
2076 +#
2077 +CONFIG_CRYPTO_HMAC=y
2078 +CONFIG_CRYPTO_XCBC=m
2079 +
2080 +#
2081 +# Digest
2082 +#
2083 +CONFIG_CRYPTO_CRC32C=m
2084 +CONFIG_CRYPTO_MD4=m
2085 +CONFIG_CRYPTO_MD5=y
2086 +CONFIG_CRYPTO_MICHAEL_MIC=m
2087 +# CONFIG_CRYPTO_RMD128 is not set
2088 +# CONFIG_CRYPTO_RMD160 is not set
2089 +# CONFIG_CRYPTO_RMD256 is not set
2090 +# CONFIG_CRYPTO_RMD320 is not set
2091 +CONFIG_CRYPTO_SHA1=y
2092 +CONFIG_CRYPTO_SHA256=m
2093 +CONFIG_CRYPTO_SHA512=m
2094 +CONFIG_CRYPTO_TGR192=m
2095 +CONFIG_CRYPTO_WP512=m
2096 +
2097 +#
2098 +# Ciphers
2099 +#
2100 +CONFIG_CRYPTO_AES=y
2101 +CONFIG_CRYPTO_ANUBIS=m
2102 +CONFIG_CRYPTO_ARC4=y
2103 +CONFIG_CRYPTO_BLOWFISH=m
2104 +CONFIG_CRYPTO_CAMELLIA=m
2105 +CONFIG_CRYPTO_CAST5=m
2106 +CONFIG_CRYPTO_CAST6=m
2107 +CONFIG_CRYPTO_DES=y
2108 +CONFIG_CRYPTO_FCRYPT=m
2109 +CONFIG_CRYPTO_KHAZAD=m
2110 +# CONFIG_CRYPTO_SALSA20 is not set
2111 +# CONFIG_CRYPTO_SEED is not set
2112 +CONFIG_CRYPTO_SERPENT=m
2113 +CONFIG_CRYPTO_TEA=m
2114 +CONFIG_CRYPTO_TWOFISH=m
2115 +CONFIG_CRYPTO_TWOFISH_COMMON=m
2116 +
2117 +#
2118 +# Compression
2119 +#
2120 +CONFIG_CRYPTO_DEFLATE=m
2121 +# CONFIG_CRYPTO_LZO is not set
2122 +
2123 +#
2124 +# Random Number Generation
2125 +#
2126 +CONFIG_CRYPTO_ANSI_CPRNG=y
2127 +CONFIG_CRYPTO_HW=y
2128 +
2129 +#
2130 +# Library routines
2131 +#
2132 +CONFIG_BITREVERSE=y
2133 +CONFIG_CRC_CCITT=y
2134 +CONFIG_CRC16=y
2135 +CONFIG_CRC_T10DIF=y
2136 +# CONFIG_CRC_ITU_T is not set
2137 +CONFIG_CRC32=y
2138 +# CONFIG_CRC7 is not set
2139 +CONFIG_LIBCRC32C=m
2140 +CONFIG_ZLIB_INFLATE=y
2141 +CONFIG_ZLIB_DEFLATE=y
2142 +CONFIG_TEXTSEARCH=y
2143 +CONFIG_TEXTSEARCH_KMP=m
2144 +CONFIG_TEXTSEARCH_BM=m
2145 +CONFIG_TEXTSEARCH_FSM=m
2146 +CONFIG_PLIST=y
2147 +CONFIG_HAS_IOMEM=y
2148 +CONFIG_HAS_DMA=y
2149 Index: linux-2.6.28/arch/arm/configs/gta02-packaging-defconfig
2150 ===================================================================
2151 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2152 +++ linux-2.6.28/arch/arm/configs/gta02-packaging-defconfig     2009-01-02 00:01:56.000000000 +0100
2153 @@ -0,0 +1,2111 @@
2154 +#
2155 +# Automatically generated make config: don't edit
2156 +# Linux kernel version: 2.6.28-rc4
2157 +# Wed Dec 10 11:09:39 2008
2158 +#
2159 +CONFIG_ARM=y
2160 +CONFIG_HAVE_PWM=y
2161 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
2162 +CONFIG_GENERIC_GPIO=y
2163 +# CONFIG_GENERIC_TIME is not set
2164 +# CONFIG_GENERIC_CLOCKEVENTS is not set
2165 +CONFIG_MMU=y
2166 +CONFIG_NO_IOPORT=y
2167 +CONFIG_GENERIC_HARDIRQS=y
2168 +CONFIG_STACKTRACE_SUPPORT=y
2169 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
2170 +CONFIG_LOCKDEP_SUPPORT=y
2171 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2172 +CONFIG_HARDIRQS_SW_RESEND=y
2173 +CONFIG_GENERIC_IRQ_PROBE=y
2174 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2175 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2176 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2177 +CONFIG_GENERIC_HWEIGHT=y
2178 +CONFIG_GENERIC_CALIBRATE_DELAY=y
2179 +CONFIG_FIQ=y
2180 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
2181 +CONFIG_VECTORS_BASE=0xffff0000
2182 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2183 +
2184 +#
2185 +# General setup
2186 +#
2187 +CONFIG_EXPERIMENTAL=y
2188 +CONFIG_BROKEN_ON_SMP=y
2189 +CONFIG_LOCK_KERNEL=y
2190 +CONFIG_INIT_ENV_ARG_LIMIT=32
2191 +CONFIG_LOCALVERSION="-mokodev"
2192 +# CONFIG_LOCALVERSION_AUTO is not set
2193 +CONFIG_SWAP=y
2194 +CONFIG_SYSVIPC=y
2195 +CONFIG_SYSVIPC_SYSCTL=y
2196 +# CONFIG_POSIX_MQUEUE is not set
2197 +# CONFIG_BSD_PROCESS_ACCT is not set
2198 +# CONFIG_TASKSTATS is not set
2199 +# CONFIG_AUDIT is not set
2200 +CONFIG_IKCONFIG=y
2201 +CONFIG_IKCONFIG_PROC=y
2202 +CONFIG_LOG_BUF_SHIFT=18
2203 +# CONFIG_CGROUPS is not set
2204 +# CONFIG_GROUP_SCHED is not set
2205 +CONFIG_SYSFS_DEPRECATED=y
2206 +CONFIG_SYSFS_DEPRECATED_V2=y
2207 +# CONFIG_RELAY is not set
2208 +CONFIG_NAMESPACES=y
2209 +# CONFIG_UTS_NS is not set
2210 +# CONFIG_IPC_NS is not set
2211 +# CONFIG_USER_NS is not set
2212 +# CONFIG_PID_NS is not set
2213 +CONFIG_BLK_DEV_INITRD=y
2214 +CONFIG_INITRAMFS_SOURCE=""
2215 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
2216 +CONFIG_SYSCTL=y
2217 +# CONFIG_EMBEDDED is not set
2218 +CONFIG_UID16=y
2219 +CONFIG_SYSCTL_SYSCALL=y
2220 +CONFIG_KALLSYMS=y
2221 +CONFIG_KALLSYMS_ALL=y
2222 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
2223 +CONFIG_HOTPLUG=y
2224 +CONFIG_PRINTK=y
2225 +CONFIG_BUG=y
2226 +CONFIG_ELF_CORE=y
2227 +CONFIG_COMPAT_BRK=y
2228 +CONFIG_BASE_FULL=y
2229 +CONFIG_FUTEX=y
2230 +CONFIG_ANON_INODES=y
2231 +CONFIG_EPOLL=y
2232 +CONFIG_SIGNALFD=y
2233 +CONFIG_TIMERFD=y
2234 +CONFIG_EVENTFD=y
2235 +CONFIG_SHMEM=y
2236 +CONFIG_AIO=y
2237 +CONFIG_ASHMEM=y
2238 +CONFIG_VM_EVENT_COUNTERS=y
2239 +CONFIG_SLAB=y
2240 +# CONFIG_SLUB is not set
2241 +# CONFIG_SLOB is not set
2242 +# CONFIG_PROFILING is not set
2243 +CONFIG_MARKERS=y
2244 +CONFIG_HAVE_OPROFILE=y
2245 +# CONFIG_KPROBES is not set
2246 +CONFIG_HAVE_KPROBES=y
2247 +CONFIG_HAVE_KRETPROBES=y
2248 +CONFIG_HAVE_CLK=y
2249 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
2250 +CONFIG_SLABINFO=y
2251 +CONFIG_RT_MUTEXES=y
2252 +# CONFIG_TINY_SHMEM is not set
2253 +CONFIG_BASE_SMALL=0
2254 +CONFIG_MODULES=y
2255 +# CONFIG_MODULE_FORCE_LOAD is not set
2256 +CONFIG_MODULE_UNLOAD=y
2257 +CONFIG_MODULE_FORCE_UNLOAD=y
2258 +# CONFIG_MODVERSIONS is not set
2259 +# CONFIG_MODULE_SRCVERSION_ALL is not set
2260 +CONFIG_KMOD=y
2261 +CONFIG_BLOCK=y
2262 +# CONFIG_LBD is not set
2263 +# CONFIG_BLK_DEV_IO_TRACE is not set
2264 +# CONFIG_LSF is not set
2265 +# CONFIG_BLK_DEV_BSG is not set
2266 +# CONFIG_BLK_DEV_INTEGRITY is not set
2267 +
2268 +#
2269 +# IO Schedulers
2270 +#
2271 +CONFIG_IOSCHED_NOOP=y
2272 +CONFIG_IOSCHED_AS=m
2273 +CONFIG_IOSCHED_DEADLINE=y
2274 +CONFIG_IOSCHED_CFQ=m
2275 +# CONFIG_DEFAULT_AS is not set
2276 +CONFIG_DEFAULT_DEADLINE=y
2277 +# CONFIG_DEFAULT_CFQ is not set
2278 +# CONFIG_DEFAULT_NOOP is not set
2279 +CONFIG_DEFAULT_IOSCHED="deadline"
2280 +CONFIG_CLASSIC_RCU=y
2281 +CONFIG_FREEZER=y
2282 +
2283 +#
2284 +# System Type
2285 +#
2286 +# CONFIG_ARCH_AAEC2000 is not set
2287 +# CONFIG_ARCH_INTEGRATOR is not set
2288 +# CONFIG_ARCH_REALVIEW is not set
2289 +# CONFIG_ARCH_VERSATILE is not set
2290 +# CONFIG_ARCH_AT91 is not set
2291 +# CONFIG_ARCH_CLPS7500 is not set
2292 +# CONFIG_ARCH_CLPS711X is not set
2293 +# CONFIG_ARCH_EBSA110 is not set
2294 +# CONFIG_ARCH_EP93XX is not set
2295 +# CONFIG_ARCH_FOOTBRIDGE is not set
2296 +# CONFIG_ARCH_NETX is not set
2297 +# CONFIG_ARCH_H720X is not set
2298 +# CONFIG_ARCH_IMX is not set
2299 +# CONFIG_ARCH_IOP13XX is not set
2300 +# CONFIG_ARCH_IOP32X is not set
2301 +# CONFIG_ARCH_IOP33X is not set
2302 +# CONFIG_ARCH_IXP23XX is not set
2303 +# CONFIG_ARCH_IXP2000 is not set
2304 +# CONFIG_ARCH_IXP4XX is not set
2305 +# CONFIG_ARCH_L7200 is not set
2306 +# CONFIG_ARCH_KIRKWOOD is not set
2307 +# CONFIG_ARCH_KS8695 is not set
2308 +# CONFIG_ARCH_NS9XXX is not set
2309 +# CONFIG_ARCH_LOKI is not set
2310 +# CONFIG_ARCH_MV78XX0 is not set
2311 +# CONFIG_ARCH_MXC is not set
2312 +# CONFIG_ARCH_ORION5X is not set
2313 +# CONFIG_ARCH_PNX4008 is not set
2314 +# CONFIG_ARCH_PXA is not set
2315 +# CONFIG_ARCH_RPC is not set
2316 +# CONFIG_ARCH_SA1100 is not set
2317 +CONFIG_ARCH_S3C2410=y
2318 +# CONFIG_ARCH_S3C64XX is not set
2319 +# CONFIG_ARCH_SHARK is not set
2320 +# CONFIG_ARCH_LH7A40X is not set
2321 +# CONFIG_ARCH_DAVINCI is not set
2322 +# CONFIG_ARCH_OMAP is not set
2323 +# CONFIG_ARCH_MSM is not set
2324 +CONFIG_PLAT_S3C24XX=y
2325 +CONFIG_S3C2410_CLOCK=y
2326 +CONFIG_CPU_S3C244X=y
2327 +CONFIG_S3C24XX_PWM=y
2328 +CONFIG_S3C2410_DMA=y
2329 +# CONFIG_S3C2410_DMA_DEBUG is not set
2330 +CONFIG_MACH_SMDK=y
2331 +CONFIG_MACH_NEO1973=y
2332 +CONFIG_PLAT_S3C=y
2333 +CONFIG_CPU_LLSERIAL_S3C2410=y
2334 +CONFIG_CPU_LLSERIAL_S3C2440=y
2335 +
2336 +#
2337 +# Boot options
2338 +#
2339 +# CONFIG_S3C_BOOT_WATCHDOG is not set
2340 +# CONFIG_S3C_BOOT_ERROR_RESET is not set
2341 +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
2342 +
2343 +#
2344 +# Power management
2345 +#
2346 +# CONFIG_S3C2410_PM_DEBUG is not set
2347 +# CONFIG_S3C2410_PM_CHECK is not set
2348 +CONFIG_S3C_LOWLEVEL_UART_PORT=2
2349 +CONFIG_S3C_GPIO_SPACE=0
2350 +CONFIG_S3C_GPIO_TRACK=y
2351 +
2352 +#
2353 +# S3C2400 Machines
2354 +#
2355 +CONFIG_CPU_S3C2410=y
2356 +CONFIG_CPU_S3C2410_DMA=y
2357 +CONFIG_S3C2410_PM=y
2358 +CONFIG_S3C2410_GPIO=y
2359 +CONFIG_S3C2410_PWM=y
2360 +
2361 +#
2362 +# S3C2410 Machines
2363 +#
2364 +# CONFIG_ARCH_SMDK2410 is not set
2365 +# CONFIG_ARCH_H1940 is not set
2366 +# CONFIG_MACH_N30 is not set
2367 +# CONFIG_ARCH_BAST is not set
2368 +# CONFIG_MACH_OTOM is not set
2369 +# CONFIG_MACH_AML_M5900 is not set
2370 +# CONFIG_MACH_TCT_HAMMER is not set
2371 +# CONFIG_MACH_VR1000 is not set
2372 +CONFIG_MACH_QT2410=y
2373 +# CONFIG_MACH_NEO1973_GTA01 is not set
2374 +
2375 +#
2376 +# S3C2412 Machines
2377 +#
2378 +# CONFIG_MACH_JIVE is not set
2379 +# CONFIG_MACH_SMDK2413 is not set
2380 +# CONFIG_MACH_SMDK2412 is not set
2381 +# CONFIG_MACH_VSTMS is not set
2382 +CONFIG_CPU_S3C2440=y
2383 +CONFIG_S3C2440_DMA=y
2384 +CONFIG_S3C2440_C_FIQ=y
2385 +
2386 +#
2387 +# S3C2440 Machines
2388 +#
2389 +# CONFIG_MACH_ANUBIS is not set
2390 +# CONFIG_MACH_OSIRIS is not set
2391 +# CONFIG_MACH_RX3715 is not set
2392 +CONFIG_ARCH_S3C2440=y
2393 +# CONFIG_MACH_NEXCODER_2440 is not set
2394 +CONFIG_SMDK2440_CPU2440=y
2395 +# CONFIG_MACH_AT2440EVB is not set
2396 +CONFIG_MACH_NEO1973_GTA02=y
2397 +# CONFIG_NEO1973_GTA02_2440 is not set
2398 +CONFIG_CPU_S3C2442=y
2399 +
2400 +#
2401 +# S3C2442 Machines
2402 +#
2403 +CONFIG_SMDK2440_CPU2442=y
2404 +
2405 +#
2406 +# S3C2443 Machines
2407 +#
2408 +# CONFIG_MACH_SMDK2443 is not set
2409 +
2410 +#
2411 +# Processor Type
2412 +#
2413 +CONFIG_CPU_32=y
2414 +CONFIG_CPU_ARM920T=y
2415 +CONFIG_CPU_32v4T=y
2416 +CONFIG_CPU_ABRT_EV4T=y
2417 +CONFIG_CPU_PABRT_NOIFAR=y
2418 +CONFIG_CPU_CACHE_V4WT=y
2419 +CONFIG_CPU_CACHE_VIVT=y
2420 +CONFIG_CPU_COPY_V4WB=y
2421 +CONFIG_CPU_TLB_V4WBI=y
2422 +CONFIG_CPU_CP15=y
2423 +CONFIG_CPU_CP15_MMU=y
2424 +
2425 +#
2426 +# Processor Features
2427 +#
2428 +CONFIG_ARM_THUMB=y
2429 +# CONFIG_CPU_ICACHE_DISABLE is not set
2430 +# CONFIG_CPU_DCACHE_DISABLE is not set
2431 +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
2432 +# CONFIG_OUTER_CACHE is not set
2433 +
2434 +#
2435 +# Bus support
2436 +#
2437 +# CONFIG_PCI_SYSCALL is not set
2438 +# CONFIG_ARCH_SUPPORTS_MSI is not set
2439 +# CONFIG_PCCARD is not set
2440 +
2441 +#
2442 +# Kernel Features
2443 +#
2444 +CONFIG_VMSPLIT_3G=y
2445 +# CONFIG_VMSPLIT_2G is not set
2446 +# CONFIG_VMSPLIT_1G is not set
2447 +CONFIG_PAGE_OFFSET=0xC0000000
2448 +CONFIG_PREEMPT=y
2449 +CONFIG_HZ=200
2450 +CONFIG_AEABI=y
2451 +CONFIG_OABI_COMPAT=y
2452 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
2453 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
2454 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
2455 +CONFIG_SELECT_MEMORY_MODEL=y
2456 +CONFIG_FLATMEM_MANUAL=y
2457 +# CONFIG_DISCONTIGMEM_MANUAL is not set
2458 +# CONFIG_SPARSEMEM_MANUAL is not set
2459 +CONFIG_FLATMEM=y
2460 +CONFIG_FLAT_NODE_MEM_MAP=y
2461 +CONFIG_PAGEFLAGS_EXTENDED=y
2462 +CONFIG_SPLIT_PTLOCK_CPUS=4096
2463 +# CONFIG_RESOURCES_64BIT is not set
2464 +# CONFIG_PHYS_ADDR_T_64BIT is not set
2465 +CONFIG_ZONE_DMA_FLAG=0
2466 +CONFIG_VIRT_TO_BUS=y
2467 +CONFIG_UNEVICTABLE_LRU=y
2468 +CONFIG_ALIGNMENT_TRAP=y
2469 +
2470 +#
2471 +# Boot options
2472 +#
2473 +CONFIG_ZBOOT_ROM_TEXT=0x0
2474 +CONFIG_ZBOOT_ROM_BSS=0x0
2475 +CONFIG_CMDLINE="unused -- bootloader passes ATAG list"
2476 +# CONFIG_XIP_KERNEL is not set
2477 +CONFIG_KEXEC=y
2478 +CONFIG_ATAGS_PROC=y
2479 +
2480 +#
2481 +# CPU Power Management
2482 +#
2483 +CONFIG_CPU_IDLE=y
2484 +CONFIG_CPU_IDLE_GOV_LADDER=y
2485 +
2486 +#
2487 +# Floating point emulation
2488 +#
2489 +
2490 +#
2491 +# At least one emulation must be selected
2492 +#
2493 +CONFIG_FPE_NWFPE=y
2494 +# CONFIG_FPE_NWFPE_XP is not set
2495 +# CONFIG_FPE_FASTFPE is not set
2496 +
2497 +#
2498 +# Userspace binary formats
2499 +#
2500 +CONFIG_BINFMT_ELF=y
2501 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
2502 +CONFIG_HAVE_AOUT=y
2503 +# CONFIG_BINFMT_AOUT is not set
2504 +# CONFIG_BINFMT_MISC is not set
2505 +
2506 +#
2507 +# Power management options
2508 +#
2509 +CONFIG_PM=y
2510 +# CONFIG_PM_DEBUG is not set
2511 +CONFIG_PM_SLEEP=y
2512 +CONFIG_SUSPEND=y
2513 +CONFIG_SUSPEND_FREEZER=y
2514 +CONFIG_APM_EMULATION=y
2515 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
2516 +CONFIG_NET=y
2517 +
2518 +#
2519 +# Networking options
2520 +#
2521 +CONFIG_PACKET=y
2522 +CONFIG_PACKET_MMAP=y
2523 +CONFIG_UNIX=y
2524 +CONFIG_XFRM=y
2525 +# CONFIG_XFRM_USER is not set
2526 +# CONFIG_XFRM_SUB_POLICY is not set
2527 +CONFIG_XFRM_MIGRATE=y
2528 +# CONFIG_XFRM_STATISTICS is not set
2529 +CONFIG_XFRM_IPCOMP=m
2530 +CONFIG_NET_KEY=m
2531 +CONFIG_NET_KEY_MIGRATE=y
2532 +CONFIG_INET=y
2533 +CONFIG_IP_MULTICAST=y
2534 +CONFIG_IP_ADVANCED_ROUTER=y
2535 +CONFIG_ASK_IP_FIB_HASH=y
2536 +# CONFIG_IP_FIB_TRIE is not set
2537 +CONFIG_IP_FIB_HASH=y
2538 +CONFIG_IP_MULTIPLE_TABLES=y
2539 +# CONFIG_IP_ROUTE_MULTIPATH is not set
2540 +# CONFIG_IP_ROUTE_VERBOSE is not set
2541 +CONFIG_IP_PNP=y
2542 +# CONFIG_IP_PNP_DHCP is not set
2543 +# CONFIG_IP_PNP_BOOTP is not set
2544 +# CONFIG_IP_PNP_RARP is not set
2545 +CONFIG_NET_IPIP=m
2546 +CONFIG_NET_IPGRE=m
2547 +# CONFIG_NET_IPGRE_BROADCAST is not set
2548 +# CONFIG_IP_MROUTE is not set
2549 +# CONFIG_ARPD is not set
2550 +CONFIG_SYN_COOKIES=y
2551 +CONFIG_INET_AH=m
2552 +CONFIG_INET_ESP=m
2553 +CONFIG_INET_IPCOMP=m
2554 +CONFIG_INET_XFRM_TUNNEL=m
2555 +CONFIG_INET_TUNNEL=m
2556 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
2557 +CONFIG_INET_XFRM_MODE_TUNNEL=m
2558 +CONFIG_INET_XFRM_MODE_BEET=m
2559 +# CONFIG_INET_LRO is not set
2560 +CONFIG_INET_DIAG=y
2561 +CONFIG_INET_TCP_DIAG=y
2562 +# CONFIG_TCP_CONG_ADVANCED is not set
2563 +CONFIG_TCP_CONG_CUBIC=y
2564 +CONFIG_DEFAULT_TCP_CONG="cubic"
2565 +CONFIG_TCP_MD5SIG=y
2566 +CONFIG_IPV6=m
2567 +# CONFIG_IPV6_PRIVACY is not set
2568 +# CONFIG_IPV6_ROUTER_PREF is not set
2569 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
2570 +CONFIG_INET6_AH=m
2571 +CONFIG_INET6_ESP=m
2572 +CONFIG_INET6_IPCOMP=m
2573 +# CONFIG_IPV6_MIP6 is not set
2574 +CONFIG_INET6_XFRM_TUNNEL=m
2575 +CONFIG_INET6_TUNNEL=m
2576 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
2577 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
2578 +CONFIG_INET6_XFRM_MODE_BEET=m
2579 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
2580 +CONFIG_IPV6_SIT=m
2581 +CONFIG_IPV6_NDISC_NODETYPE=y
2582 +CONFIG_IPV6_TUNNEL=m
2583 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
2584 +# CONFIG_IPV6_MROUTE is not set
2585 +# CONFIG_NETWORK_SECMARK is not set
2586 +CONFIG_NETFILTER=y
2587 +# CONFIG_NETFILTER_DEBUG is not set
2588 +CONFIG_NETFILTER_ADVANCED=y
2589 +CONFIG_BRIDGE_NETFILTER=y
2590 +
2591 +#
2592 +# Core Netfilter Configuration
2593 +#
2594 +CONFIG_NETFILTER_NETLINK=m
2595 +CONFIG_NETFILTER_NETLINK_QUEUE=m
2596 +CONFIG_NETFILTER_NETLINK_LOG=m
2597 +CONFIG_NF_CONNTRACK=m
2598 +CONFIG_NF_CT_ACCT=y
2599 +CONFIG_NF_CONNTRACK_MARK=y
2600 +# CONFIG_NF_CONNTRACK_EVENTS is not set
2601 +# CONFIG_NF_CT_PROTO_DCCP is not set
2602 +CONFIG_NF_CT_PROTO_GRE=m
2603 +CONFIG_NF_CT_PROTO_SCTP=m
2604 +# CONFIG_NF_CT_PROTO_UDPLITE is not set
2605 +# CONFIG_NF_CONNTRACK_AMANDA is not set
2606 +CONFIG_NF_CONNTRACK_FTP=m
2607 +CONFIG_NF_CONNTRACK_H323=m
2608 +CONFIG_NF_CONNTRACK_IRC=m
2609 +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
2610 +CONFIG_NF_CONNTRACK_PPTP=m
2611 +CONFIG_NF_CONNTRACK_SANE=m
2612 +CONFIG_NF_CONNTRACK_SIP=m
2613 +CONFIG_NF_CONNTRACK_TFTP=m
2614 +CONFIG_NF_CT_NETLINK=m
2615 +# CONFIG_NETFILTER_TPROXY is not set
2616 +CONFIG_NETFILTER_XTABLES=m
2617 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
2618 +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
2619 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
2620 +CONFIG_NETFILTER_XT_TARGET_MARK=m
2621 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
2622 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
2623 +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
2624 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
2625 +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
2626 +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
2627 +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
2628 +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
2629 +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
2630 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
2631 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
2632 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
2633 +CONFIG_NETFILTER_XT_MATCH_ESP=m
2634 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
2635 +CONFIG_NETFILTER_XT_MATCH_HELPER=m
2636 +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
2637 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
2638 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
2639 +CONFIG_NETFILTER_XT_MATCH_MAC=m
2640 +CONFIG_NETFILTER_XT_MATCH_MARK=m
2641 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
2642 +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
2643 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
2644 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
2645 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
2646 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
2647 +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
2648 +CONFIG_NETFILTER_XT_MATCH_REALM=m
2649 +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
2650 +CONFIG_NETFILTER_XT_MATCH_SCTP=m
2651 +CONFIG_NETFILTER_XT_MATCH_STATE=m
2652 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
2653 +CONFIG_NETFILTER_XT_MATCH_STRING=m
2654 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
2655 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
2656 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
2657 +# CONFIG_IP_VS is not set
2658 +
2659 +#
2660 +# IP: Netfilter Configuration
2661 +#
2662 +CONFIG_NF_DEFRAG_IPV4=m
2663 +CONFIG_NF_CONNTRACK_IPV4=m
2664 +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
2665 +# CONFIG_IP_NF_QUEUE is not set
2666 +CONFIG_IP_NF_IPTABLES=m
2667 +CONFIG_IP_NF_MATCH_ADDRTYPE=m
2668 +CONFIG_IP_NF_MATCH_AH=m
2669 +CONFIG_IP_NF_MATCH_ECN=m
2670 +CONFIG_IP_NF_MATCH_TTL=m
2671 +CONFIG_IP_NF_FILTER=m
2672 +CONFIG_IP_NF_TARGET_REJECT=m
2673 +CONFIG_IP_NF_TARGET_LOG=m
2674 +CONFIG_IP_NF_TARGET_ULOG=m
2675 +CONFIG_NF_NAT=m
2676 +CONFIG_NF_NAT_NEEDED=y
2677 +CONFIG_IP_NF_TARGET_MASQUERADE=m
2678 +CONFIG_IP_NF_TARGET_NETMAP=m
2679 +CONFIG_IP_NF_TARGET_REDIRECT=m
2680 +CONFIG_NF_NAT_SNMP_BASIC=m
2681 +CONFIG_NF_NAT_PROTO_GRE=m
2682 +CONFIG_NF_NAT_PROTO_SCTP=m
2683 +CONFIG_NF_NAT_FTP=m
2684 +CONFIG_NF_NAT_IRC=m
2685 +CONFIG_NF_NAT_TFTP=m
2686 +# CONFIG_NF_NAT_AMANDA is not set
2687 +CONFIG_NF_NAT_PPTP=m
2688 +CONFIG_NF_NAT_H323=m
2689 +CONFIG_NF_NAT_SIP=m
2690 +CONFIG_IP_NF_MANGLE=m
2691 +CONFIG_IP_NF_TARGET_CLUSTERIP=m
2692 +CONFIG_IP_NF_TARGET_ECN=m
2693 +CONFIG_IP_NF_TARGET_TTL=m
2694 +# CONFIG_IP_NF_RAW is not set
2695 +# CONFIG_IP_NF_ARPTABLES is not set
2696 +
2697 +#
2698 +# IPv6: Netfilter Configuration
2699 +#
2700 +CONFIG_NF_CONNTRACK_IPV6=m
2701 +# CONFIG_IP6_NF_QUEUE is not set
2702 +CONFIG_IP6_NF_IPTABLES=m
2703 +CONFIG_IP6_NF_MATCH_AH=m
2704 +CONFIG_IP6_NF_MATCH_EUI64=m
2705 +CONFIG_IP6_NF_MATCH_FRAG=m
2706 +CONFIG_IP6_NF_MATCH_OPTS=m
2707 +CONFIG_IP6_NF_MATCH_HL=m
2708 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
2709 +CONFIG_IP6_NF_MATCH_MH=m
2710 +CONFIG_IP6_NF_MATCH_RT=m
2711 +CONFIG_IP6_NF_TARGET_LOG=m
2712 +CONFIG_IP6_NF_FILTER=m
2713 +CONFIG_IP6_NF_TARGET_REJECT=m
2714 +CONFIG_IP6_NF_MANGLE=m
2715 +CONFIG_IP6_NF_TARGET_HL=m
2716 +# CONFIG_IP6_NF_RAW is not set
2717 +CONFIG_BRIDGE_NF_EBTABLES=m
2718 +CONFIG_BRIDGE_EBT_BROUTE=m
2719 +CONFIG_BRIDGE_EBT_T_FILTER=m
2720 +CONFIG_BRIDGE_EBT_T_NAT=m
2721 +CONFIG_BRIDGE_EBT_802_3=m
2722 +CONFIG_BRIDGE_EBT_AMONG=m
2723 +CONFIG_BRIDGE_EBT_ARP=m
2724 +CONFIG_BRIDGE_EBT_IP=m
2725 +# CONFIG_BRIDGE_EBT_IP6 is not set
2726 +CONFIG_BRIDGE_EBT_LIMIT=m
2727 +CONFIG_BRIDGE_EBT_MARK=m
2728 +CONFIG_BRIDGE_EBT_PKTTYPE=m
2729 +CONFIG_BRIDGE_EBT_STP=m
2730 +CONFIG_BRIDGE_EBT_VLAN=m
2731 +CONFIG_BRIDGE_EBT_ARPREPLY=m
2732 +CONFIG_BRIDGE_EBT_DNAT=m
2733 +CONFIG_BRIDGE_EBT_MARK_T=m
2734 +CONFIG_BRIDGE_EBT_REDIRECT=m
2735 +CONFIG_BRIDGE_EBT_SNAT=m
2736 +CONFIG_BRIDGE_EBT_LOG=m
2737 +CONFIG_BRIDGE_EBT_ULOG=m
2738 +# CONFIG_BRIDGE_EBT_NFLOG is not set
2739 +# CONFIG_IP_DCCP is not set
2740 +# CONFIG_IP_SCTP is not set
2741 +# CONFIG_TIPC is not set
2742 +# CONFIG_ATM is not set
2743 +CONFIG_STP=y
2744 +CONFIG_BRIDGE=y
2745 +# CONFIG_NET_DSA is not set
2746 +# CONFIG_VLAN_8021Q is not set
2747 +# CONFIG_DECNET is not set
2748 +CONFIG_LLC=y
2749 +# CONFIG_LLC2 is not set
2750 +# CONFIG_IPX is not set
2751 +# CONFIG_ATALK is not set
2752 +# CONFIG_X25 is not set
2753 +# CONFIG_LAPB is not set
2754 +# CONFIG_ECONET is not set
2755 +# CONFIG_WAN_ROUTER is not set
2756 +CONFIG_NET_SCHED=y
2757 +
2758 +#
2759 +# Queueing/Scheduling
2760 +#
2761 +CONFIG_NET_SCH_CBQ=m
2762 +CONFIG_NET_SCH_HTB=m
2763 +CONFIG_NET_SCH_HFSC=m
2764 +CONFIG_NET_SCH_PRIO=m
2765 +# CONFIG_NET_SCH_MULTIQ is not set
2766 +CONFIG_NET_SCH_RED=m
2767 +CONFIG_NET_SCH_SFQ=m
2768 +CONFIG_NET_SCH_TEQL=m
2769 +CONFIG_NET_SCH_TBF=m
2770 +CONFIG_NET_SCH_GRED=m
2771 +CONFIG_NET_SCH_DSMARK=m
2772 +CONFIG_NET_SCH_NETEM=m
2773 +
2774 +#
2775 +# Classification
2776 +#
2777 +CONFIG_NET_CLS=y
2778 +CONFIG_NET_CLS_BASIC=m
2779 +CONFIG_NET_CLS_TCINDEX=m
2780 +CONFIG_NET_CLS_ROUTE4=m
2781 +CONFIG_NET_CLS_ROUTE=y
2782 +CONFIG_NET_CLS_FW=m
2783 +CONFIG_NET_CLS_U32=m
2784 +CONFIG_CLS_U32_PERF=y
2785 +CONFIG_CLS_U32_MARK=y
2786 +CONFIG_NET_CLS_RSVP=m
2787 +CONFIG_NET_CLS_RSVP6=m
2788 +# CONFIG_NET_CLS_FLOW is not set
2789 +# CONFIG_NET_EMATCH is not set
2790 +# CONFIG_NET_CLS_ACT is not set
2791 +# CONFIG_NET_CLS_IND is not set
2792 +CONFIG_NET_SCH_FIFO=y
2793 +
2794 +#
2795 +# Network testing
2796 +#
2797 +# CONFIG_NET_PKTGEN is not set
2798 +# CONFIG_HAMRADIO is not set
2799 +# CONFIG_CAN is not set
2800 +# CONFIG_IRDA is not set
2801 +CONFIG_BT=m
2802 +CONFIG_BT_L2CAP=m
2803 +CONFIG_BT_SCO=m
2804 +CONFIG_BT_RFCOMM=m
2805 +CONFIG_BT_RFCOMM_TTY=y
2806 +CONFIG_BT_BNEP=m
2807 +CONFIG_BT_BNEP_MC_FILTER=y
2808 +CONFIG_BT_BNEP_PROTO_FILTER=y
2809 +CONFIG_BT_HIDP=m
2810 +
2811 +#
2812 +# Bluetooth device drivers
2813 +#
2814 +CONFIG_BT_HCIBTUSB=m
2815 +# CONFIG_BT_HCIBTSDIO is not set
2816 +# CONFIG_BT_HCIUART is not set
2817 +# CONFIG_BT_HCIBCM203X is not set
2818 +# CONFIG_BT_HCIBPA10X is not set
2819 +# CONFIG_BT_HCIBFUSB is not set
2820 +# CONFIG_BT_HCIVHCI is not set
2821 +# CONFIG_AF_RXRPC is not set
2822 +# CONFIG_PHONET is not set
2823 +CONFIG_FIB_RULES=y
2824 +CONFIG_WIRELESS=y
2825 +# CONFIG_CFG80211 is not set
2826 +# CONFIG_WIRELESS_OLD_REGULATORY is not set
2827 +CONFIG_WIRELESS_EXT=y
2828 +CONFIG_WIRELESS_EXT_SYSFS=y
2829 +# CONFIG_MAC80211 is not set
2830 +# CONFIG_IEEE80211 is not set
2831 +CONFIG_RFKILL=y
2832 +CONFIG_RFKILL_INPUT=y
2833 +CONFIG_RFKILL_LEDS=y
2834 +# CONFIG_NET_9P is not set
2835 +
2836 +#
2837 +# Device Drivers
2838 +#
2839 +
2840 +#
2841 +# Generic Driver Options
2842 +#
2843 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
2844 +CONFIG_STANDALONE=y
2845 +CONFIG_PREVENT_FIRMWARE_BUILD=y
2846 +CONFIG_FW_LOADER=y
2847 +# CONFIG_FIRMWARE_IN_KERNEL is not set
2848 +CONFIG_EXTRA_FIRMWARE=""
2849 +# CONFIG_DEBUG_DRIVER is not set
2850 +# CONFIG_DEBUG_DEVRES is not set
2851 +# CONFIG_SYS_HYPERVISOR is not set
2852 +CONFIG_CONNECTOR=m
2853 +CONFIG_MTD=y
2854 +# CONFIG_MTD_DEBUG is not set
2855 +CONFIG_MTD_CONCAT=y
2856 +CONFIG_MTD_PARTITIONS=y
2857 +# CONFIG_MTD_REDBOOT_PARTS is not set
2858 +CONFIG_MTD_CMDLINE_PARTS=y
2859 +# CONFIG_MTD_AFS_PARTS is not set
2860 +# CONFIG_MTD_AR7_PARTS is not set
2861 +
2862 +#
2863 +# User Modules And Translation Layers
2864 +#
2865 +CONFIG_MTD_CHAR=y
2866 +CONFIG_MTD_BLKDEVS=y
2867 +CONFIG_MTD_BLOCK=y
2868 +# CONFIG_FTL is not set
2869 +# CONFIG_NFTL is not set
2870 +# CONFIG_INFTL is not set
2871 +# CONFIG_RFD_FTL is not set
2872 +# CONFIG_SSFDC is not set
2873 +# CONFIG_MTD_OOPS is not set
2874 +
2875 +#
2876 +# RAM/ROM/Flash chip drivers
2877 +#
2878 +CONFIG_MTD_CFI=y
2879 +# CONFIG_MTD_JEDECPROBE is not set
2880 +CONFIG_MTD_GEN_PROBE=y
2881 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
2882 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
2883 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
2884 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
2885 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
2886 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
2887 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
2888 +CONFIG_MTD_CFI_I1=y
2889 +CONFIG_MTD_CFI_I2=y
2890 +# CONFIG_MTD_CFI_I4 is not set
2891 +# CONFIG_MTD_CFI_I8 is not set
2892 +CONFIG_MTD_CFI_INTELEXT=y
2893 +# CONFIG_MTD_CFI_AMDSTD is not set
2894 +# CONFIG_MTD_CFI_STAA is not set
2895 +CONFIG_MTD_CFI_UTIL=y
2896 +# CONFIG_MTD_RAM is not set
2897 +CONFIG_MTD_ROM=y
2898 +CONFIG_MTD_ABSENT=y
2899 +
2900 +#
2901 +# Mapping drivers for chip access
2902 +#
2903 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
2904 +CONFIG_MTD_PHYSMAP=y
2905 +CONFIG_MTD_PHYSMAP_START=0x0
2906 +CONFIG_MTD_PHYSMAP_LEN=0
2907 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
2908 +# CONFIG_MTD_ARM_INTEGRATOR is not set
2909 +# CONFIG_MTD_PLATRAM is not set
2910 +
2911 +#
2912 +# Self-contained MTD device drivers
2913 +#
2914 +# CONFIG_MTD_DATAFLASH is not set
2915 +# CONFIG_MTD_M25P80 is not set
2916 +# CONFIG_MTD_SLRAM is not set
2917 +# CONFIG_MTD_PHRAM is not set
2918 +# CONFIG_MTD_MTDRAM is not set
2919 +# CONFIG_MTD_BLOCK2MTD is not set
2920 +
2921 +#
2922 +# Disk-On-Chip Device Drivers
2923 +#
2924 +# CONFIG_MTD_DOC2000 is not set
2925 +# CONFIG_MTD_DOC2001 is not set
2926 +# CONFIG_MTD_DOC2001PLUS is not set
2927 +CONFIG_MTD_NAND=y
2928 +CONFIG_MTD_NAND_VERIFY_WRITE=y
2929 +# CONFIG_MTD_NAND_ECC_SMC is not set
2930 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
2931 +# CONFIG_MTD_NAND_GPIO is not set
2932 +CONFIG_MTD_NAND_IDS=y
2933 +CONFIG_MTD_NAND_S3C2410=y
2934 +CONFIG_MTD_NAND_S3C2410_DEBUG=y
2935 +CONFIG_MTD_NAND_S3C2410_HWECC=y
2936 +# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
2937 +# CONFIG_MTD_NAND_DISKONCHIP is not set
2938 +# CONFIG_MTD_NAND_NANDSIM is not set
2939 +# CONFIG_MTD_NAND_PLATFORM is not set
2940 +# CONFIG_MTD_ALAUDA is not set
2941 +# CONFIG_MTD_ONENAND is not set
2942 +
2943 +#
2944 +# UBI - Unsorted block images
2945 +#
2946 +# CONFIG_MTD_UBI is not set
2947 +# CONFIG_PARPORT is not set
2948 +CONFIG_BLK_DEV=y
2949 +# CONFIG_BLK_DEV_COW_COMMON is not set
2950 +CONFIG_BLK_DEV_LOOP=m
2951 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
2952 +# CONFIG_BLK_DEV_NBD is not set
2953 +CONFIG_BLK_DEV_UB=m
2954 +CONFIG_BLK_DEV_RAM=y
2955 +CONFIG_BLK_DEV_RAM_COUNT=16
2956 +CONFIG_BLK_DEV_RAM_SIZE=4096
2957 +# CONFIG_BLK_DEV_XIP is not set
2958 +# CONFIG_CDROM_PKTCDVD is not set
2959 +# CONFIG_ATA_OVER_ETH is not set
2960 +CONFIG_MISC_DEVICES=y
2961 +# CONFIG_EEPROM_93CX6 is not set
2962 +CONFIG_LOW_MEMORY_KILLER=y
2963 +# CONFIG_ENCLOSURE_SERVICES is not set
2964 +CONFIG_HAVE_IDE=y
2965 +# CONFIG_IDE is not set
2966 +
2967 +#
2968 +# SCSI device support
2969 +#
2970 +# CONFIG_RAID_ATTRS is not set
2971 +CONFIG_SCSI=m
2972 +CONFIG_SCSI_DMA=y
2973 +# CONFIG_SCSI_TGT is not set
2974 +# CONFIG_SCSI_NETLINK is not set
2975 +CONFIG_SCSI_PROC_FS=y
2976 +
2977 +#
2978 +# SCSI support type (disk, tape, CD-ROM)
2979 +#
2980 +CONFIG_BLK_DEV_SD=m
2981 +# CONFIG_CHR_DEV_ST is not set
2982 +# CONFIG_CHR_DEV_OSST is not set
2983 +CONFIG_BLK_DEV_SR=m
2984 +# CONFIG_BLK_DEV_SR_VENDOR is not set
2985 +CONFIG_CHR_DEV_SG=m
2986 +# CONFIG_CHR_DEV_SCH is not set
2987 +
2988 +#
2989 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
2990 +#
2991 +CONFIG_SCSI_MULTI_LUN=y
2992 +# CONFIG_SCSI_CONSTANTS is not set
2993 +# CONFIG_SCSI_LOGGING is not set
2994 +CONFIG_SCSI_SCAN_ASYNC=y
2995 +CONFIG_SCSI_WAIT_SCAN=m
2996 +
2997 +#
2998 +# SCSI Transports
2999 +#
3000 +# CONFIG_SCSI_SPI_ATTRS is not set
3001 +# CONFIG_SCSI_FC_ATTRS is not set
3002 +# CONFIG_SCSI_ISCSI_ATTRS is not set
3003 +# CONFIG_SCSI_SAS_LIBSAS is not set
3004 +# CONFIG_SCSI_SRP_ATTRS is not set
3005 +CONFIG_SCSI_LOWLEVEL=y
3006 +# CONFIG_ISCSI_TCP is not set
3007 +# CONFIG_SCSI_DEBUG is not set
3008 +# CONFIG_SCSI_DH is not set
3009 +# CONFIG_ATA is not set
3010 +CONFIG_MD=y
3011 +# CONFIG_BLK_DEV_MD is not set
3012 +CONFIG_BLK_DEV_DM=m
3013 +# CONFIG_DM_DEBUG is not set
3014 +CONFIG_DM_CRYPT=m
3015 +CONFIG_DM_SNAPSHOT=m
3016 +# CONFIG_DM_MIRROR is not set
3017 +# CONFIG_DM_ZERO is not set
3018 +# CONFIG_DM_MULTIPATH is not set
3019 +# CONFIG_DM_DELAY is not set
3020 +# CONFIG_DM_UEVENT is not set
3021 +CONFIG_NETDEVICES=y
3022 +# CONFIG_DUMMY is not set
3023 +# CONFIG_BONDING is not set
3024 +# CONFIG_MACVLAN is not set
3025 +# CONFIG_EQUALIZER is not set
3026 +CONFIG_TUN=m
3027 +# CONFIG_VETH is not set
3028 +# CONFIG_PHYLIB is not set
3029 +CONFIG_NET_ETHERNET=y
3030 +CONFIG_MII=y
3031 +# CONFIG_AX88796 is not set
3032 +# CONFIG_SMC91X is not set
3033 +# CONFIG_DM9000 is not set
3034 +# CONFIG_ENC28J60 is not set
3035 +# CONFIG_SMC911X is not set
3036 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
3037 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
3038 +# CONFIG_IBM_NEW_EMAC_TAH is not set
3039 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
3040 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
3041 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
3042 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
3043 +# CONFIG_B44 is not set
3044 +# CONFIG_NETDEV_1000 is not set
3045 +# CONFIG_NETDEV_10000 is not set
3046 +
3047 +#
3048 +# Wireless LAN
3049 +#
3050 +# CONFIG_WLAN_PRE80211 is not set
3051 +# CONFIG_WLAN_80211 is not set
3052 +# CONFIG_IWLWIFI_LEDS is not set
3053 +
3054 +#
3055 +# USB Network Adapters
3056 +#
3057 +CONFIG_USB_CATC=m
3058 +CONFIG_USB_KAWETH=m
3059 +CONFIG_USB_PEGASUS=m
3060 +CONFIG_USB_RTL8150=m
3061 +CONFIG_USB_USBNET=y
3062 +CONFIG_USB_NET_AX8817X=m
3063 +CONFIG_USB_NET_CDCETHER=m
3064 +CONFIG_USB_NET_DM9601=m
3065 +# CONFIG_USB_NET_SMSC95XX is not set
3066 +CONFIG_USB_NET_GL620A=m
3067 +CONFIG_USB_NET_NET1080=m
3068 +CONFIG_USB_NET_PLUSB=m
3069 +CONFIG_USB_NET_MCS7830=m
3070 +CONFIG_USB_NET_RNDIS_HOST=m
3071 +CONFIG_USB_NET_CDC_SUBSET=m
3072 +CONFIG_USB_ALI_M5632=y
3073 +CONFIG_USB_AN2720=y
3074 +CONFIG_USB_BELKIN=y
3075 +CONFIG_USB_ARMLINUX=y
3076 +CONFIG_USB_EPSON2888=y
3077 +CONFIG_USB_KC2190=y
3078 +CONFIG_USB_NET_ZAURUS=m
3079 +# CONFIG_USB_HSO is not set
3080 +# CONFIG_WAN is not set
3081 +CONFIG_PPP=m
3082 +CONFIG_PPP_MULTILINK=y
3083 +CONFIG_PPP_FILTER=y
3084 +CONFIG_PPP_ASYNC=m
3085 +CONFIG_PPP_SYNC_TTY=m
3086 +CONFIG_PPP_DEFLATE=m
3087 +CONFIG_PPP_BSDCOMP=m
3088 +CONFIG_PPP_MPPE=m
3089 +# CONFIG_PPPOE is not set
3090 +# CONFIG_PPPOL2TP is not set
3091 +# CONFIG_SLIP is not set
3092 +CONFIG_SLHC=m
3093 +# CONFIG_NETCONSOLE is not set
3094 +# CONFIG_NETPOLL is not set
3095 +# CONFIG_NET_POLL_CONTROLLER is not set
3096 +# CONFIG_ISDN is not set
3097 +
3098 +#
3099 +# Input device support
3100 +#
3101 +CONFIG_INPUT=y
3102 +# CONFIG_INPUT_FF_MEMLESS is not set
3103 +# CONFIG_INPUT_POLLDEV is not set
3104 +
3105 +#
3106 +# Userland interfaces
3107 +#
3108 +CONFIG_INPUT_MOUSEDEV=y
3109 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
3110 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
3111 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640
3112 +# CONFIG_INPUT_JOYDEV is not set
3113 +CONFIG_INPUT_EVDEV=y
3114 +# CONFIG_INPUT_EVBUG is not set
3115 +
3116 +#
3117 +# Input Device Drivers
3118 +#
3119 +CONFIG_INPUT_KEYBOARD=y
3120 +# CONFIG_KEYBOARD_ATKBD is not set
3121 +# CONFIG_KEYBOARD_SUNKBD is not set
3122 +# CONFIG_KEYBOARD_LKKBD is not set
3123 +# CONFIG_KEYBOARD_XTKBD is not set
3124 +# CONFIG_KEYBOARD_NEWTON is not set
3125 +CONFIG_KEYBOARD_STOWAWAY=m
3126 +CONFIG_KEYBOARD_GPIO=m
3127 +CONFIG_KEYBOARD_NEO1973=y
3128 +CONFIG_KEYBOARD_QT2410=y
3129 +CONFIG_INPUT_MOUSE=y
3130 +# CONFIG_MOUSE_PS2 is not set
3131 +# CONFIG_MOUSE_SERIAL is not set
3132 +# CONFIG_MOUSE_APPLETOUCH is not set
3133 +# CONFIG_MOUSE_BCM5974 is not set
3134 +# CONFIG_MOUSE_VSXXXAA is not set
3135 +# CONFIG_MOUSE_GPIO is not set
3136 +# CONFIG_INPUT_JOYSTICK is not set
3137 +# CONFIG_INPUT_TABLET is not set
3138 +CONFIG_INPUT_TOUCHSCREEN=y
3139 +CONFIG_TOUCHSCREEN_FILTER=y
3140 +CONFIG_TOUCHSCREEN_FILTER_GROUP=y
3141 +CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
3142 +CONFIG_TOUCHSCREEN_FILTER_MEAN=y
3143 +CONFIG_TOUCHSCREEN_FILTER_LINEAR=y
3144 +# CONFIG_TOUCHSCREEN_ADS7846 is not set
3145 +# CONFIG_TOUCHSCREEN_FUJITSU is not set
3146 +CONFIG_TOUCHSCREEN_S3C2410=y
3147 +# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set
3148 +# CONFIG_TOUCHSCREEN_GUNZE is not set
3149 +# CONFIG_TOUCHSCREEN_ELO is not set
3150 +# CONFIG_TOUCHSCREEN_MTOUCH is not set
3151 +# CONFIG_TOUCHSCREEN_INEXIO is not set
3152 +# CONFIG_TOUCHSCREEN_MK712 is not set
3153 +# CONFIG_TOUCHSCREEN_PENMOUNT is not set
3154 +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
3155 +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
3156 +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
3157 +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
3158 +# CONFIG_TOUCHSCREEN_PCAP7200 is not set
3159 +CONFIG_INPUT_MISC=y
3160 +# CONFIG_INPUT_ATI_REMOTE is not set
3161 +# CONFIG_INPUT_ATI_REMOTE2 is not set
3162 +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
3163 +# CONFIG_INPUT_POWERMATE is not set
3164 +# CONFIG_INPUT_YEALINK is not set
3165 +# CONFIG_INPUT_CM109 is not set
3166 +CONFIG_INPUT_UINPUT=m
3167 +CONFIG_INPUT_LIS302DL=y
3168 +CONFIG_INPUT_PCF50633_PMU=y
3169 +
3170 +#
3171 +# Hardware I/O ports
3172 +#
3173 +CONFIG_SERIO=y
3174 +# CONFIG_SERIO_SERPORT is not set
3175 +# CONFIG_SERIO_RAW is not set
3176 +# CONFIG_GAMEPORT is not set
3177 +
3178 +#
3179 +# Character devices
3180 +#
3181 +CONFIG_VT=y
3182 +CONFIG_CONSOLE_TRANSLATIONS=y
3183 +CONFIG_VT_CONSOLE=y
3184 +CONFIG_NR_TTY_DEVICES=6
3185 +CONFIG_HW_CONSOLE=y
3186 +CONFIG_VT_HW_CONSOLE_BINDING=y
3187 +# CONFIG_DEVKMEM is not set
3188 +# CONFIG_SERIAL_NONSTANDARD is not set
3189 +
3190 +#
3191 +# Serial drivers
3192 +#
3193 +# CONFIG_SERIAL_8250 is not set
3194 +
3195 +#
3196 +# Non-8250 serial port support
3197 +#
3198 +CONFIG_SERIAL_SAMSUNG=y
3199 +CONFIG_SERIAL_SAMSUNG_UARTS=3
3200 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
3201 +CONFIG_SERIAL_S3C2410=y
3202 +CONFIG_SERIAL_S3C2440=y
3203 +CONFIG_SERIAL_CORE=y
3204 +CONFIG_SERIAL_CORE_CONSOLE=y
3205 +CONFIG_UNIX98_PTYS=y
3206 +# CONFIG_LEGACY_PTYS is not set
3207 +# CONFIG_IPMI_HANDLER is not set
3208 +# CONFIG_HW_RANDOM is not set
3209 +# CONFIG_NVRAM is not set
3210 +# CONFIG_R3964 is not set
3211 +# CONFIG_RAW_DRIVER is not set
3212 +# CONFIG_TCG_TPM is not set
3213 +CONFIG_I2C=y
3214 +CONFIG_I2C_BOARDINFO=y
3215 +CONFIG_I2C_CHARDEV=y
3216 +CONFIG_I2C_HELPER_AUTO=y
3217 +
3218 +#
3219 +# I2C Hardware Bus support
3220 +#
3221 +
3222 +#
3223 +# I2C system bus drivers (mostly embedded / system-on-chip)
3224 +#
3225 +# CONFIG_I2C_GPIO is not set
3226 +# CONFIG_I2C_OCORES is not set
3227 +CONFIG_I2C_S3C2410=y
3228 +# CONFIG_I2C_SIMTEC is not set
3229 +
3230 +#
3231 +# External I2C/SMBus adapter drivers
3232 +#
3233 +# CONFIG_I2C_PARPORT_LIGHT is not set
3234 +# CONFIG_I2C_TAOS_EVM is not set
3235 +# CONFIG_I2C_TINY_USB is not set
3236 +
3237 +#
3238 +# Other I2C/SMBus bus drivers
3239 +#
3240 +# CONFIG_I2C_PCA_PLATFORM is not set
3241 +# CONFIG_I2C_STUB is not set
3242 +
3243 +#
3244 +# Miscellaneous I2C Chip support
3245 +#
3246 +# CONFIG_DS1682 is not set
3247 +# CONFIG_AT24 is not set
3248 +# CONFIG_SENSORS_EEPROM is not set
3249 +# CONFIG_SENSORS_PCF50606 is not set
3250 +# CONFIG_SENSORS_PCF50633 is not set
3251 +# CONFIG_SENSORS_PCF8574 is not set
3252 +# CONFIG_PCF8575 is not set
3253 +# CONFIG_SENSORS_PCA9539 is not set
3254 +# CONFIG_SENSORS_PCF8591 is not set
3255 +# CONFIG_TPS65010 is not set
3256 +# CONFIG_SENSORS_MAX6875 is not set
3257 +# CONFIG_SENSORS_TSL2550 is not set
3258 +# CONFIG_SENSORS_TSL256X is not set
3259 +CONFIG_PCA9632=y
3260 +# CONFIG_I2C_DEBUG_CORE is not set
3261 +# CONFIG_I2C_DEBUG_ALGO is not set
3262 +# CONFIG_I2C_DEBUG_BUS is not set
3263 +# CONFIG_I2C_DEBUG_CHIP is not set
3264 +CONFIG_SPI=y
3265 +# CONFIG_SPI_DEBUG is not set
3266 +CONFIG_SPI_MASTER=y
3267 +
3268 +#
3269 +# SPI Master Controller Drivers
3270 +#
3271 +CONFIG_SPI_BITBANG=y
3272 +# CONFIG_SPI_S3C24XX is not set
3273 +CONFIG_SPI_S3C24XX_GPIO=y
3274 +
3275 +#
3276 +# SPI Protocol Masters
3277 +#
3278 +# CONFIG_SPI_AT25 is not set
3279 +# CONFIG_SPI_SPIDEV is not set
3280 +# CONFIG_SPI_TLE62X0 is not set
3281 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
3282 +CONFIG_GPIOLIB=y
3283 +CONFIG_DEBUG_GPIO=y
3284 +CONFIG_GPIO_SYSFS=y
3285 +
3286 +#
3287 +# I2C GPIO expanders:
3288 +#
3289 +# CONFIG_GPIO_MAX732X is not set
3290 +# CONFIG_GPIO_PCA953X is not set
3291 +# CONFIG_GPIO_PCF857X is not set
3292 +
3293 +#
3294 +# PCI GPIO expanders:
3295 +#
3296 +
3297 +#
3298 +# SPI GPIO expanders:
3299 +#
3300 +# CONFIG_GPIO_MAX7301 is not set
3301 +# CONFIG_GPIO_MCP23S08 is not set
3302 +# CONFIG_W1 is not set
3303 +CONFIG_POWER_SUPPLY=y
3304 +CONFIG_POWER_SUPPLY_DEBUG=y
3305 +CONFIG_PDA_POWER=y
3306 +CONFIG_APM_POWER=y
3307 +# CONFIG_BATTERY_DS2760 is not set
3308 +# CONFIG_BATTERY_BQ27x00 is not set
3309 +CONFIG_BATTERY_BQ27000_HDQ=y
3310 +CONFIG_GTA02_HDQ=y
3311 +CONFIG_CHARGER_PCF50633=y
3312 +CONFIG_HWMON=y
3313 +# CONFIG_HWMON_VID is not set
3314 +# CONFIG_SENSORS_AD7414 is not set
3315 +# CONFIG_SENSORS_AD7418 is not set
3316 +# CONFIG_SENSORS_ADCXX is not set
3317 +# CONFIG_SENSORS_ADM1021 is not set
3318 +# CONFIG_SENSORS_ADM1025 is not set
3319 +# CONFIG_SENSORS_ADM1026 is not set
3320 +# CONFIG_SENSORS_ADM1029 is not set
3321 +# CONFIG_SENSORS_ADM1031 is not set
3322 +# CONFIG_SENSORS_ADM9240 is not set
3323 +# CONFIG_SENSORS_ADT7470 is not set
3324 +# CONFIG_SENSORS_ADT7473 is not set
3325 +# CONFIG_SENSORS_ATXP1 is not set
3326 +# CONFIG_SENSORS_DS1621 is not set
3327 +# CONFIG_SENSORS_F71805F is not set
3328 +# CONFIG_SENSORS_F71882FG is not set
3329 +# CONFIG_SENSORS_F75375S is not set
3330 +# CONFIG_SENSORS_GL518SM is not set
3331 +# CONFIG_SENSORS_GL520SM is not set
3332 +# CONFIG_SENSORS_IT87 is not set
3333 +# CONFIG_SENSORS_LM63 is not set
3334 +# CONFIG_SENSORS_LM70 is not set
3335 +# CONFIG_SENSORS_LM75 is not set
3336 +# CONFIG_SENSORS_LM77 is not set
3337 +# CONFIG_SENSORS_LM78 is not set
3338 +# CONFIG_SENSORS_LM80 is not set
3339 +# CONFIG_SENSORS_LM83 is not set
3340 +# CONFIG_SENSORS_LM85 is not set
3341 +# CONFIG_SENSORS_LM87 is not set
3342 +# CONFIG_SENSORS_LM90 is not set
3343 +# CONFIG_SENSORS_LM92 is not set
3344 +# CONFIG_SENSORS_LM93 is not set
3345 +# CONFIG_SENSORS_MAX1111 is not set
3346 +# CONFIG_SENSORS_MAX1619 is not set
3347 +# CONFIG_SENSORS_MAX6650 is not set
3348 +# CONFIG_SENSORS_PC87360 is not set
3349 +# CONFIG_SENSORS_PC87427 is not set
3350 +# CONFIG_SENSORS_DME1737 is not set
3351 +# CONFIG_SENSORS_SMSC47M1 is not set
3352 +# CONFIG_SENSORS_SMSC47M192 is not set
3353 +# CONFIG_SENSORS_SMSC47B397 is not set
3354 +# CONFIG_SENSORS_ADS7828 is not set
3355 +# CONFIG_SENSORS_THMC50 is not set
3356 +# CONFIG_SENSORS_VT1211 is not set
3357 +# CONFIG_SENSORS_W83781D is not set
3358 +# CONFIG_SENSORS_W83791D is not set
3359 +# CONFIG_SENSORS_W83792D is not set
3360 +# CONFIG_SENSORS_W83793 is not set
3361 +# CONFIG_SENSORS_W83L785TS is not set
3362 +# CONFIG_SENSORS_W83L786NG is not set
3363 +# CONFIG_SENSORS_W83627HF is not set
3364 +# CONFIG_SENSORS_W83627EHF is not set
3365 +# CONFIG_HWMON_DEBUG_CHIP is not set
3366 +# CONFIG_THERMAL is not set
3367 +# CONFIG_THERMAL_HWMON is not set
3368 +CONFIG_WATCHDOG=y
3369 +# CONFIG_WATCHDOG_NOWAYOUT is not set
3370 +
3371 +#
3372 +# Watchdog Device Drivers
3373 +#
3374 +# CONFIG_SOFT_WATCHDOG is not set
3375 +CONFIG_S3C2410_WATCHDOG=m
3376 +
3377 +#
3378 +# USB-based Watchdog Cards
3379 +#
3380 +# CONFIG_USBPCWATCHDOG is not set
3381 +
3382 +#
3383 +# Sonics Silicon Backplane
3384 +#
3385 +CONFIG_SSB_POSSIBLE=y
3386 +# CONFIG_SSB is not set
3387 +
3388 +#
3389 +# Multifunction device drivers
3390 +#
3391 +# CONFIG_MFD_CORE is not set
3392 +# CONFIG_MFD_SM501 is not set
3393 +# CONFIG_MFD_ASIC3 is not set
3394 +# CONFIG_HTC_EGPIO is not set
3395 +# CONFIG_HTC_PASIC3 is not set
3396 +# CONFIG_MFD_TMIO is not set
3397 +# CONFIG_MFD_T7L66XB is not set
3398 +# CONFIG_MFD_TC6387XB is not set
3399 +# CONFIG_MFD_TC6393XB is not set
3400 +# CONFIG_PMIC_DA903X is not set
3401 +# CONFIG_MFD_WM8400 is not set
3402 +# CONFIG_MFD_WM8350_I2C is not set
3403 +CONFIG_MFD_PCF50633=y
3404 +CONFIG_PCF50633_ADC=y
3405 +CONFIG_PCF50633_GPIO=y
3406 +# CONFIG_MFD_PCF50606 is not set
3407 +CONFIG_MFD_GLAMO=y
3408 +CONFIG_MFD_GLAMO_FB=y
3409 +CONFIG_MFD_GLAMO_SPI_GPIO=y
3410 +CONFIG_MFD_GLAMO_SPI_FB=y
3411 +CONFIG_MFD_GLAMO_MCI=y
3412 +
3413 +#
3414 +# Multimedia devices
3415 +#
3416 +
3417 +#
3418 +# Multimedia core support
3419 +#
3420 +# CONFIG_VIDEO_DEV is not set
3421 +# CONFIG_DVB_CORE is not set
3422 +# CONFIG_VIDEO_MEDIA is not set
3423 +
3424 +#
3425 +# Multimedia drivers
3426 +#
3427 +CONFIG_DAB=y
3428 +# CONFIG_USB_DABUSB is not set
3429 +
3430 +#
3431 +# Graphics support
3432 +#
3433 +# CONFIG_VGASTATE is not set
3434 +CONFIG_VIDEO_OUTPUT_CONTROL=y
3435 +CONFIG_FB=y
3436 +# CONFIG_FIRMWARE_EDID is not set
3437 +# CONFIG_FB_DDC is not set
3438 +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
3439 +CONFIG_FB_CFB_FILLRECT=y
3440 +CONFIG_FB_CFB_COPYAREA=y
3441 +CONFIG_FB_CFB_IMAGEBLIT=y
3442 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
3443 +# CONFIG_FB_SYS_FILLRECT is not set
3444 +# CONFIG_FB_SYS_COPYAREA is not set
3445 +# CONFIG_FB_SYS_IMAGEBLIT is not set
3446 +# CONFIG_FB_FOREIGN_ENDIAN is not set
3447 +# CONFIG_FB_SYS_FOPS is not set
3448 +# CONFIG_FB_SVGALIB is not set
3449 +# CONFIG_FB_MACMODES is not set
3450 +# CONFIG_FB_BACKLIGHT is not set
3451 +# CONFIG_FB_MODE_HELPERS is not set
3452 +# CONFIG_FB_TILEBLITTING is not set
3453 +
3454 +#
3455 +# Frame buffer hardware drivers
3456 +#
3457 +# CONFIG_FB_UVESA is not set
3458 +# CONFIG_FB_S1D13XXX is not set
3459 +CONFIG_FB_S3C2410=y
3460 +# CONFIG_FB_S3C2410_DEBUG is not set
3461 +# CONFIG_FB_VIRTUAL is not set
3462 +# CONFIG_FB_METRONOME is not set
3463 +# CONFIG_FB_MB862XX is not set
3464 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
3465 +CONFIG_LCD_CLASS_DEVICE=y
3466 +CONFIG_LCD_LTV350QV=y
3467 +# CONFIG_LCD_ILI9320 is not set
3468 +# CONFIG_LCD_TDO24M is not set
3469 +# CONFIG_LCD_VGG2432A4 is not set
3470 +# CONFIG_LCD_PLATFORM is not set
3471 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
3472 +CONFIG_BACKLIGHT_CORGI=y
3473 +# CONFIG_BACKLIGHT_PWM is not set
3474 +
3475 +#
3476 +# Display device support
3477 +#
3478 +CONFIG_DISPLAY_SUPPORT=y
3479 +
3480 +#
3481 +# Display hardware drivers
3482 +#
3483 +CONFIG_DISPLAY_JBT6K74=y
3484 +
3485 +#
3486 +# Console display driver support
3487 +#
3488 +# CONFIG_VGA_CONSOLE is not set
3489 +CONFIG_DUMMY_CONSOLE=y
3490 +CONFIG_FRAMEBUFFER_CONSOLE=y
3491 +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
3492 +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
3493 +CONFIG_FONTS=y
3494 +# CONFIG_FONT_8x8 is not set
3495 +# CONFIG_FONT_8x16 is not set
3496 +CONFIG_FONT_6x11=y
3497 +# CONFIG_FONT_7x14 is not set
3498 +# CONFIG_FONT_PEARL_8x8 is not set
3499 +# CONFIG_FONT_ACORN_8x8 is not set
3500 +# CONFIG_FONT_MINI_4x6 is not set
3501 +# CONFIG_FONT_SUN8x16 is not set
3502 +# CONFIG_FONT_SUN12x22 is not set
3503 +# CONFIG_FONT_10x18 is not set
3504 +# CONFIG_LOGO is not set
3505 +CONFIG_SOUND=y
3506 +CONFIG_SOUND_OSS_CORE=y
3507 +CONFIG_SND=m
3508 +CONFIG_SND_TIMER=m
3509 +CONFIG_SND_PCM=m
3510 +CONFIG_SND_HWDEP=m
3511 +CONFIG_SND_RAWMIDI=m
3512 +# CONFIG_SND_SEQUENCER is not set
3513 +CONFIG_SND_OSSEMUL=y
3514 +CONFIG_SND_MIXER_OSS=m
3515 +CONFIG_SND_PCM_OSS=m
3516 +CONFIG_SND_PCM_OSS_PLUGINS=y
3517 +# CONFIG_SND_DYNAMIC_MINORS is not set
3518 +CONFIG_SND_SUPPORT_OLD_API=y
3519 +CONFIG_SND_VERBOSE_PROCFS=y
3520 +# CONFIG_SND_VERBOSE_PRINTK is not set
3521 +CONFIG_SND_DEBUG=y
3522 +# CONFIG_SND_DEBUG_VERBOSE is not set
3523 +CONFIG_SND_PCM_XRUN_DEBUG=y
3524 +CONFIG_SND_DRIVERS=y
3525 +# CONFIG_SND_DUMMY is not set
3526 +# CONFIG_SND_MTPAV is not set
3527 +# CONFIG_SND_SERIAL_U16550 is not set
3528 +# CONFIG_SND_MPU401 is not set
3529 +CONFIG_SND_ARM=y
3530 +# CONFIG_SND_SPI is not set
3531 +CONFIG_SND_USB=y
3532 +CONFIG_SND_USB_AUDIO=m
3533 +# CONFIG_SND_USB_CAIAQ is not set
3534 +CONFIG_SND_SOC=m
3535 +CONFIG_SND_S3C24XX_SOC=m
3536 +CONFIG_SND_S3C24XX_SOC_I2S=m
3537 +CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753=m
3538 +# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
3539 +# CONFIG_SND_SOC_ALL_CODECS is not set
3540 +CONFIG_SND_SOC_WM8753=m
3541 +# CONFIG_SOUND_PRIME is not set
3542 +CONFIG_HID_SUPPORT=y
3543 +CONFIG_HID=y
3544 +# CONFIG_HID_DEBUG is not set
3545 +# CONFIG_HIDRAW is not set
3546 +
3547 +#
3548 +# USB Input Devices
3549 +#
3550 +CONFIG_USB_HID=y
3551 +CONFIG_HID_PID=y
3552 +# CONFIG_USB_HIDDEV is not set
3553 +
3554 +#
3555 +# Special HID drivers
3556 +#
3557 +CONFIG_HID_COMPAT=y
3558 +CONFIG_HID_A4TECH=y
3559 +CONFIG_HID_APPLE=y
3560 +CONFIG_HID_BELKIN=y
3561 +CONFIG_HID_BRIGHT=y
3562 +CONFIG_HID_CHERRY=y
3563 +CONFIG_HID_CHICONY=y
3564 +CONFIG_HID_CYPRESS=y
3565 +CONFIG_HID_DELL=y
3566 +CONFIG_HID_EZKEY=y
3567 +CONFIG_HID_GYRATION=y
3568 +CONFIG_HID_LOGITECH=y
3569 +# CONFIG_LOGITECH_FF is not set
3570 +# CONFIG_LOGIRUMBLEPAD2_FF is not set
3571 +CONFIG_HID_MICROSOFT=y
3572 +CONFIG_HID_MONTEREY=y
3573 +CONFIG_HID_PANTHERLORD=y
3574 +# CONFIG_PANTHERLORD_FF is not set
3575 +CONFIG_HID_PETALYNX=y
3576 +CONFIG_HID_SAMSUNG=y
3577 +CONFIG_HID_SONY=y
3578 +CONFIG_HID_SUNPLUS=y
3579 +# CONFIG_THRUSTMASTER_FF is not set
3580 +# CONFIG_ZEROPLUS_FF is not set
3581 +CONFIG_USB_SUPPORT=y
3582 +CONFIG_USB_ARCH_HAS_HCD=y
3583 +CONFIG_USB_ARCH_HAS_OHCI=y
3584 +# CONFIG_USB_ARCH_HAS_EHCI is not set
3585 +CONFIG_USB=y
3586 +# CONFIG_USB_DEBUG is not set
3587 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
3588 +
3589 +#
3590 +# Miscellaneous USB options
3591 +#
3592 +CONFIG_USB_DEVICEFS=y
3593 +CONFIG_USB_DEVICE_CLASS=y
3594 +# CONFIG_USB_DYNAMIC_MINORS is not set
3595 +CONFIG_USB_SUSPEND=y
3596 +# CONFIG_USB_OTG is not set
3597 +CONFIG_USB_MON=y
3598 +# CONFIG_USB_WUSB is not set
3599 +# CONFIG_USB_WUSB_CBAF is not set
3600 +
3601 +#
3602 +# USB Host Controller Drivers
3603 +#
3604 +# CONFIG_USB_C67X00_HCD is not set
3605 +# CONFIG_USB_ISP116X_HCD is not set
3606 +# CONFIG_USB_ISP1760_HCD is not set
3607 +CONFIG_USB_OHCI_HCD=m
3608 +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
3609 +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
3610 +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
3611 +# CONFIG_USB_SL811_HCD is not set
3612 +# CONFIG_USB_R8A66597_HCD is not set
3613 +# CONFIG_USB_HWA_HCD is not set
3614 +# CONFIG_USB_MUSB_HDRC is not set
3615 +# CONFIG_USB_GADGET_MUSB_HDRC is not set
3616 +
3617 +#
3618 +# USB Device Class drivers
3619 +#
3620 +CONFIG_USB_ACM=m
3621 +CONFIG_USB_PRINTER=m
3622 +# CONFIG_USB_WDM is not set
3623 +CONFIG_USB_TMC=m
3624 +
3625 +#
3626 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
3627 +#
3628 +
3629 +#
3630 +# may also be needed; see USB_STORAGE Help for more information
3631 +#
3632 +CONFIG_USB_STORAGE=m
3633 +# CONFIG_USB_STORAGE_DEBUG is not set
3634 +CONFIG_USB_STORAGE_DATAFAB=y
3635 +CONFIG_USB_STORAGE_FREECOM=y
3636 +# CONFIG_USB_STORAGE_ISD200 is not set
3637 +CONFIG_USB_STORAGE_DPCM=y
3638 +CONFIG_USB_STORAGE_USBAT=y
3639 +CONFIG_USB_STORAGE_SDDR09=y
3640 +CONFIG_USB_STORAGE_SDDR55=y
3641 +CONFIG_USB_STORAGE_JUMPSHOT=y
3642 +CONFIG_USB_STORAGE_ALAUDA=y
3643 +# CONFIG_USB_STORAGE_ONETOUCH is not set
3644 +CONFIG_USB_STORAGE_KARMA=y
3645 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
3646 +CONFIG_USB_LIBUSUAL=y
3647 +
3648 +#
3649 +# USB Imaging devices
3650 +#
3651 +# CONFIG_USB_MDC800 is not set
3652 +# CONFIG_USB_MICROTEK is not set
3653 +
3654 +#
3655 +# USB port drivers
3656 +#
3657 +CONFIG_USB_SERIAL=m
3658 +CONFIG_USB_EZUSB=y
3659 +CONFIG_USB_SERIAL_GENERIC=y
3660 +CONFIG_USB_SERIAL_AIRCABLE=m
3661 +CONFIG_USB_SERIAL_ARK3116=m
3662 +CONFIG_USB_SERIAL_BELKIN=m
3663 +# CONFIG_USB_SERIAL_CH341 is not set
3664 +CONFIG_USB_SERIAL_WHITEHEAT=m
3665 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
3666 +CONFIG_USB_SERIAL_CP2101=m
3667 +CONFIG_USB_SERIAL_CYPRESS_M8=m
3668 +CONFIG_USB_SERIAL_EMPEG=m
3669 +CONFIG_USB_SERIAL_FTDI_SIO=m
3670 +CONFIG_USB_SERIAL_FUNSOFT=m
3671 +CONFIG_USB_SERIAL_VISOR=m
3672 +CONFIG_USB_SERIAL_IPAQ=m
3673 +CONFIG_USB_SERIAL_IR=m
3674 +CONFIG_USB_SERIAL_EDGEPORT=m
3675 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
3676 +CONFIG_USB_SERIAL_GARMIN=m
3677 +CONFIG_USB_SERIAL_IPW=m
3678 +# CONFIG_USB_SERIAL_IUU is not set
3679 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
3680 +CONFIG_USB_SERIAL_KEYSPAN=m
3681 +CONFIG_USB_SERIAL_KLSI=m
3682 +CONFIG_USB_SERIAL_KOBIL_SCT=m
3683 +CONFIG_USB_SERIAL_MCT_U232=m
3684 +CONFIG_USB_SERIAL_MOS7720=m
3685 +CONFIG_USB_SERIAL_MOS7840=m
3686 +# CONFIG_USB_SERIAL_MOTOROLA is not set
3687 +CONFIG_USB_SERIAL_NAVMAN=m
3688 +CONFIG_USB_SERIAL_PL2303=m
3689 +# CONFIG_USB_SERIAL_OTI6858 is not set
3690 +# CONFIG_USB_SERIAL_SPCP8X5 is not set
3691 +CONFIG_USB_SERIAL_HP4X=m
3692 +CONFIG_USB_SERIAL_SAFE=m
3693 +CONFIG_USB_SERIAL_SAFE_PADDED=y
3694 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
3695 +CONFIG_USB_SERIAL_TI=m
3696 +CONFIG_USB_SERIAL_CYBERJACK=m
3697 +CONFIG_USB_SERIAL_XIRCOM=m
3698 +CONFIG_USB_SERIAL_OPTION=m
3699 +CONFIG_USB_SERIAL_OMNINET=m
3700 +# CONFIG_USB_SERIAL_DEBUG is not set
3701 +
3702 +#
3703 +# USB Miscellaneous drivers
3704 +#
3705 +# CONFIG_USB_EMI62 is not set
3706 +# CONFIG_USB_EMI26 is not set
3707 +# CONFIG_USB_ADUTUX is not set
3708 +# CONFIG_USB_SEVSEG is not set
3709 +# CONFIG_USB_RIO500 is not set
3710 +# CONFIG_USB_LEGOTOWER is not set
3711 +# CONFIG_USB_LCD is not set
3712 +CONFIG_USB_BERRY_CHARGE=m
3713 +# CONFIG_USB_LED is not set
3714 +# CONFIG_USB_CYPRESS_CY7C63 is not set
3715 +# CONFIG_USB_CYTHERM is not set
3716 +# CONFIG_USB_PHIDGET is not set
3717 +# CONFIG_USB_IDMOUSE is not set
3718 +# CONFIG_USB_FTDI_ELAN is not set
3719 +# CONFIG_USB_APPLEDISPLAY is not set
3720 +# CONFIG_USB_LD is not set
3721 +CONFIG_USB_TRANCEVIBRATOR=m
3722 +CONFIG_USB_IOWARRIOR=m
3723 +# CONFIG_USB_TEST is not set
3724 +# CONFIG_USB_ISIGHTFW is not set
3725 +# CONFIG_USB_VST is not set
3726 +CONFIG_USB_GADGET=y
3727 +# CONFIG_USB_GADGET_DEBUG is not set
3728 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
3729 +# CONFIG_USB_GADGET_DEBUG_FS is not set
3730 +CONFIG_USB_GADGET_VBUS_DRAW=500
3731 +CONFIG_USB_GADGET_SELECTED=y
3732 +# CONFIG_USB_GADGET_AT91 is not set
3733 +# CONFIG_USB_GADGET_ATMEL_USBA is not set
3734 +# CONFIG_USB_GADGET_FSL_USB2 is not set
3735 +# CONFIG_USB_GADGET_LH7A40X is not set
3736 +# CONFIG_USB_GADGET_OMAP is not set
3737 +# CONFIG_USB_GADGET_PXA25X is not set
3738 +# CONFIG_USB_GADGET_PXA27X is not set
3739 +CONFIG_USB_GADGET_S3C2410=y
3740 +CONFIG_USB_S3C2410=y
3741 +CONFIG_USB_S3C2410_DEBUG=y
3742 +# CONFIG_USB_GADGET_M66592 is not set
3743 +# CONFIG_USB_GADGET_AMD5536UDC is not set
3744 +# CONFIG_USB_GADGET_FSL_QE is not set
3745 +# CONFIG_USB_GADGET_NET2280 is not set
3746 +# CONFIG_USB_GADGET_GOKU is not set
3747 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
3748 +# CONFIG_USB_GADGET_DUALSPEED is not set
3749 +# CONFIG_USB_ZERO is not set
3750 +CONFIG_USB_ETH=m
3751 +CONFIG_USB_ETH_RNDIS=y
3752 +CONFIG_USB_GADGETFS=m
3753 +CONFIG_USB_FILE_STORAGE=m
3754 +# CONFIG_USB_FILE_STORAGE_TEST is not set
3755 +CONFIG_USB_G_SERIAL=m
3756 +CONFIG_USB_MIDI_GADGET=m
3757 +# CONFIG_USB_G_PRINTER is not set
3758 +# CONFIG_USB_CDC_COMPOSITE is not set
3759 +CONFIG_AR6000_WLAN=y
3760 +CONFIG_MMC=y
3761 +# CONFIG_MMC_DEBUG is not set
3762 +CONFIG_MMC_UNSAFE_RESUME=y
3763 +
3764 +#
3765 +# MMC/SD/SDIO Card Drivers
3766 +#
3767 +CONFIG_MMC_BLOCK=y
3768 +CONFIG_MMC_BLOCK_BOUNCE=y
3769 +# CONFIG_SDIO_UART is not set
3770 +# CONFIG_MMC_TEST is not set
3771 +
3772 +#
3773 +# MMC/SD/SDIO Host Controller Drivers
3774 +#
3775 +CONFIG_MMC_SDHCI=y
3776 +CONFIG_MMC_SDHCI_S3C=y
3777 +# CONFIG_MMC_SPI is not set
3778 +CONFIG_MMC_S3C=y
3779 +# CONFIG_MEMSTICK is not set
3780 +# CONFIG_ACCESSIBILITY is not set
3781 +CONFIG_NEW_LEDS=y
3782 +CONFIG_LEDS_CLASS=y
3783 +
3784 +#
3785 +# LED drivers
3786 +#
3787 +CONFIG_LEDS_S3C24XX=m
3788 +# CONFIG_LEDS_PCA9532 is not set
3789 +CONFIG_LEDS_GPIO=y
3790 +# CONFIG_LEDS_PCA955X is not set
3791 +CONFIG_LEDS_NEO1973_VIBRATOR=y
3792 +CONFIG_LEDS_NEO1973_GTA02=y
3793 +
3794 +#
3795 +# LED Triggers
3796 +#
3797 +CONFIG_LEDS_TRIGGERS=y
3798 +CONFIG_LEDS_TRIGGER_TIMER=y
3799 +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
3800 +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
3801 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
3802 +CONFIG_RTC_LIB=y
3803 +CONFIG_RTC_CLASS=y
3804 +CONFIG_RTC_HCTOSYS=y
3805 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
3806 +CONFIG_RTC_DEBUG=y
3807 +
3808 +#
3809 +# RTC interfaces
3810 +#
3811 +CONFIG_RTC_INTF_SYSFS=y
3812 +CONFIG_RTC_INTF_PROC=y
3813 +CONFIG_RTC_INTF_DEV=y
3814 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
3815 +# CONFIG_RTC_DRV_TEST is not set
3816 +
3817 +#
3818 +# I2C RTC drivers
3819 +#
3820 +# CONFIG_RTC_DRV_DS1307 is not set
3821 +# CONFIG_RTC_DRV_DS1374 is not set
3822 +# CONFIG_RTC_DRV_DS1672 is not set
3823 +# CONFIG_RTC_DRV_MAX6900 is not set
3824 +# CONFIG_RTC_DRV_RS5C372 is not set
3825 +# CONFIG_RTC_DRV_ISL1208 is not set
3826 +# CONFIG_RTC_DRV_X1205 is not set
3827 +# CONFIG_RTC_DRV_PCF8563 is not set
3828 +# CONFIG_RTC_DRV_PCF8583 is not set
3829 +CONFIG_RTC_DRV_PCF50633=y
3830 +# CONFIG_RTC_DRV_PCF50606 is not set
3831 +# CONFIG_RTC_DRV_M41T80 is not set
3832 +# CONFIG_RTC_DRV_S35390A is not set
3833 +# CONFIG_RTC_DRV_FM3130 is not set
3834 +
3835 +#
3836 +# SPI RTC drivers
3837 +#
3838 +# CONFIG_RTC_DRV_M41T94 is not set
3839 +# CONFIG_RTC_DRV_DS1305 is not set
3840 +# CONFIG_RTC_DRV_MAX6902 is not set
3841 +# CONFIG_RTC_DRV_R9701 is not set
3842 +# CONFIG_RTC_DRV_RS5C348 is not set
3843 +# CONFIG_RTC_DRV_DS3234 is not set
3844 +
3845 +#
3846 +# Platform RTC drivers
3847 +#
3848 +# CONFIG_RTC_DRV_CMOS is not set
3849 +# CONFIG_RTC_DRV_DS1286 is not set
3850 +# CONFIG_RTC_DRV_DS1511 is not set
3851 +# CONFIG_RTC_DRV_DS1553 is not set
3852 +# CONFIG_RTC_DRV_DS1742 is not set
3853 +# CONFIG_RTC_DRV_STK17TA8 is not set
3854 +# CONFIG_RTC_DRV_M48T86 is not set
3855 +# CONFIG_RTC_DRV_M48T35 is not set
3856 +# CONFIG_RTC_DRV_M48T59 is not set
3857 +# CONFIG_RTC_DRV_BQ4802 is not set
3858 +# CONFIG_RTC_DRV_V3020 is not set
3859 +
3860 +#
3861 +# on-CPU RTC drivers
3862 +#
3863 +CONFIG_RTC_DRV_S3C=m
3864 +CONFIG_DMADEVICES=y
3865 +
3866 +#
3867 +# DMA Devices
3868 +#
3869 +
3870 +#
3871 +# Android
3872 +#
3873 +CONFIG_ANDROID_BINDER_IPC=y
3874 +CONFIG_ANDROID_POWER=y
3875 +CONFIG_ANDROID_POWER_STAT=y
3876 +CONFIG_ANDROID_POWER_ALARM=y
3877 +CONFIG_ANDROID_LOGGER=y
3878 +# CONFIG_ANDROID_RAM_CONSOLE is not set
3879 +# CONFIG_ANDROID_TIMED_GPIO is not set
3880 +# CONFIG_ANDROID_PARANOID_NETWORK is not set
3881 +CONFIG_REGULATOR=y
3882 +CONFIG_REGULATOR_DEBUG=y
3883 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
3884 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
3885 +# CONFIG_REGULATOR_BQ24022 is not set
3886 +CONFIG_REGULATOR_PCF50633=y
3887 +CONFIG_UIO=y
3888 +CONFIG_UIO_PDRV=y
3889 +# CONFIG_UIO_PDRV_GENIRQ is not set
3890 +# CONFIG_UIO_SMX is not set
3891 +# CONFIG_UIO_SERCOS3 is not set
3892 +
3893 +#
3894 +# File systems
3895 +#
3896 +CONFIG_EXT2_FS=y
3897 +# CONFIG_EXT2_FS_XATTR is not set
3898 +# CONFIG_EXT2_FS_XIP is not set
3899 +CONFIG_EXT3_FS=y
3900 +# CONFIG_EXT3_FS_XATTR is not set
3901 +CONFIG_EXT4_FS=y
3902 +CONFIG_EXT4DEV_COMPAT=y
3903 +CONFIG_EXT4_FS_XATTR=y
3904 +# CONFIG_EXT4_FS_POSIX_ACL is not set
3905 +CONFIG_EXT4_FS_SECURITY=y
3906 +CONFIG_JBD=y
3907 +# CONFIG_JBD_DEBUG is not set
3908 +CONFIG_JBD2=y
3909 +# CONFIG_JBD2_DEBUG is not set
3910 +CONFIG_FS_MBCACHE=y
3911 +# CONFIG_REISERFS_FS is not set
3912 +# CONFIG_JFS_FS is not set
3913 +CONFIG_FS_POSIX_ACL=y
3914 +CONFIG_FILE_LOCKING=y
3915 +# CONFIG_XFS_FS is not set
3916 +# CONFIG_OCFS2_FS is not set
3917 +CONFIG_DNOTIFY=y
3918 +CONFIG_INOTIFY=y
3919 +CONFIG_INOTIFY_USER=y
3920 +# CONFIG_QUOTA is not set
3921 +# CONFIG_AUTOFS_FS is not set
3922 +CONFIG_AUTOFS4_FS=m
3923 +CONFIG_FUSE_FS=m
3924 +
3925 +#
3926 +# CD-ROM/DVD Filesystems
3927 +#
3928 +CONFIG_ISO9660_FS=m
3929 +CONFIG_JOLIET=y
3930 +# CONFIG_ZISOFS is not set
3931 +CONFIG_UDF_FS=m
3932 +CONFIG_UDF_NLS=y
3933 +
3934 +#
3935 +# DOS/FAT/NT Filesystems
3936 +#
3937 +CONFIG_FAT_FS=y
3938 +CONFIG_MSDOS_FS=y
3939 +CONFIG_VFAT_FS=y
3940 +CONFIG_FAT_DEFAULT_CODEPAGE=437
3941 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3942 +# CONFIG_NTFS_FS is not set
3943 +
3944 +#
3945 +# Pseudo filesystems
3946 +#
3947 +CONFIG_PROC_FS=y
3948 +CONFIG_PROC_SYSCTL=y
3949 +CONFIG_PROC_PAGE_MONITOR=y
3950 +CONFIG_SYSFS=y
3951 +CONFIG_TMPFS=y
3952 +# CONFIG_TMPFS_POSIX_ACL is not set
3953 +# CONFIG_HUGETLB_PAGE is not set
3954 +CONFIG_CONFIGFS_FS=m
3955 +
3956 +#
3957 +# Miscellaneous filesystems
3958 +#
3959 +# CONFIG_ADFS_FS is not set
3960 +# CONFIG_AFFS_FS is not set
3961 +# CONFIG_HFS_FS is not set
3962 +# CONFIG_HFSPLUS_FS is not set
3963 +# CONFIG_BEFS_FS is not set
3964 +# CONFIG_BFS_FS is not set
3965 +# CONFIG_EFS_FS is not set
3966 +CONFIG_JFFS2_FS=y
3967 +CONFIG_JFFS2_FS_DEBUG=0
3968 +CONFIG_JFFS2_FS_WRITEBUFFER=y
3969 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
3970 +CONFIG_JFFS2_SUMMARY=y
3971 +# CONFIG_JFFS2_FS_XATTR is not set
3972 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3973 +CONFIG_JFFS2_ZLIB=y
3974 +# CONFIG_JFFS2_LZO is not set
3975 +CONFIG_JFFS2_RTIME=y
3976 +# CONFIG_JFFS2_RUBIN is not set
3977 +CONFIG_CRAMFS=y
3978 +# CONFIG_VXFS_FS is not set
3979 +# CONFIG_MINIX_FS is not set
3980 +# CONFIG_OMFS_FS is not set
3981 +# CONFIG_HPFS_FS is not set
3982 +# CONFIG_QNX4FS_FS is not set
3983 +CONFIG_ROMFS_FS=y
3984 +# CONFIG_SYSV_FS is not set
3985 +# CONFIG_UFS_FS is not set
3986 +CONFIG_NETWORK_FILESYSTEMS=y
3987 +# CONFIG_NFS_FS is not set
3988 +CONFIG_NFSD=m
3989 +CONFIG_NFSD_V2_ACL=y
3990 +CONFIG_NFSD_V3=y
3991 +CONFIG_NFSD_V3_ACL=y
3992 +# CONFIG_NFSD_V4 is not set
3993 +CONFIG_LOCKD=m
3994 +CONFIG_LOCKD_V4=y
3995 +CONFIG_EXPORTFS=m
3996 +CONFIG_NFS_ACL_SUPPORT=m
3997 +CONFIG_NFS_COMMON=y
3998 +CONFIG_SUNRPC=m
3999 +# CONFIG_SUNRPC_REGISTER_V4 is not set
4000 +# CONFIG_RPCSEC_GSS_KRB5 is not set
4001 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
4002 +# CONFIG_SMB_FS is not set
4003 +CONFIG_CIFS=m
4004 +# CONFIG_CIFS_STATS is not set
4005 +# CONFIG_CIFS_WEAK_PW_HASH is not set
4006 +# CONFIG_CIFS_XATTR is not set
4007 +# CONFIG_CIFS_DEBUG2 is not set
4008 +# CONFIG_CIFS_EXPERIMENTAL is not set
4009 +# CONFIG_NCP_FS is not set
4010 +# CONFIG_CODA_FS is not set
4011 +# CONFIG_AFS_FS is not set
4012 +
4013 +#
4014 +# Partition Types
4015 +#
4016 +CONFIG_PARTITION_ADVANCED=y
4017 +# CONFIG_ACORN_PARTITION is not set
4018 +# CONFIG_OSF_PARTITION is not set
4019 +# CONFIG_AMIGA_PARTITION is not set
4020 +# CONFIG_ATARI_PARTITION is not set
4021 +# CONFIG_MAC_PARTITION is not set
4022 +CONFIG_MSDOS_PARTITION=y
4023 +# CONFIG_BSD_DISKLABEL is not set
4024 +# CONFIG_MINIX_SUBPARTITION is not set
4025 +# CONFIG_SOLARIS_X86_PARTITION is not set
4026 +# CONFIG_UNIXWARE_DISKLABEL is not set
4027 +# CONFIG_LDM_PARTITION is not set
4028 +# CONFIG_SGI_PARTITION is not set
4029 +# CONFIG_ULTRIX_PARTITION is not set
4030 +# CONFIG_SUN_PARTITION is not set
4031 +# CONFIG_KARMA_PARTITION is not set
4032 +# CONFIG_EFI_PARTITION is not set
4033 +# CONFIG_SYSV68_PARTITION is not set
4034 +CONFIG_NLS=y
4035 +CONFIG_NLS_DEFAULT="iso8859-1"
4036 +CONFIG_NLS_CODEPAGE_437=y
4037 +# CONFIG_NLS_CODEPAGE_737 is not set
4038 +# CONFIG_NLS_CODEPAGE_775 is not set
4039 +CONFIG_NLS_CODEPAGE_850=m
4040 +# CONFIG_NLS_CODEPAGE_852 is not set
4041 +# CONFIG_NLS_CODEPAGE_855 is not set
4042 +# CONFIG_NLS_CODEPAGE_857 is not set
4043 +# CONFIG_NLS_CODEPAGE_860 is not set
4044 +# CONFIG_NLS_CODEPAGE_861 is not set
4045 +# CONFIG_NLS_CODEPAGE_862 is not set
4046 +# CONFIG_NLS_CODEPAGE_863 is not set
4047 +# CONFIG_NLS_CODEPAGE_864 is not set
4048 +# CONFIG_NLS_CODEPAGE_865 is not set
4049 +# CONFIG_NLS_CODEPAGE_866 is not set
4050 +# CONFIG_NLS_CODEPAGE_869 is not set
4051 +CONFIG_NLS_CODEPAGE_936=m
4052 +CONFIG_NLS_CODEPAGE_950=m
4053 +# CONFIG_NLS_CODEPAGE_932 is not set
4054 +# CONFIG_NLS_CODEPAGE_949 is not set
4055 +# CONFIG_NLS_CODEPAGE_874 is not set
4056 +# CONFIG_NLS_ISO8859_8 is not set
4057 +# CONFIG_NLS_CODEPAGE_1250 is not set
4058 +# CONFIG_NLS_CODEPAGE_1251 is not set
4059 +# CONFIG_NLS_ASCII is not set
4060 +CONFIG_NLS_ISO8859_1=y
4061 +# CONFIG_NLS_ISO8859_2 is not set
4062 +# CONFIG_NLS_ISO8859_3 is not set
4063 +# CONFIG_NLS_ISO8859_4 is not set
4064 +# CONFIG_NLS_ISO8859_5 is not set
4065 +# CONFIG_NLS_ISO8859_6 is not set
4066 +# CONFIG_NLS_ISO8859_7 is not set
4067 +# CONFIG_NLS_ISO8859_9 is not set
4068 +# CONFIG_NLS_ISO8859_13 is not set
4069 +# CONFIG_NLS_ISO8859_14 is not set
4070 +# CONFIG_NLS_ISO8859_15 is not set
4071 +# CONFIG_NLS_KOI8_R is not set
4072 +# CONFIG_NLS_KOI8_U is not set
4073 +CONFIG_NLS_UTF8=m
4074 +# CONFIG_DLM is not set
4075 +
4076 +#
4077 +# Kernel hacking
4078 +#
4079 +CONFIG_PRINTK_TIME=y
4080 +CONFIG_ENABLE_WARN_DEPRECATED=y
4081 +CONFIG_ENABLE_MUST_CHECK=y
4082 +CONFIG_FRAME_WARN=1024
4083 +CONFIG_MAGIC_SYSRQ=y
4084 +# CONFIG_UNUSED_SYMBOLS is not set
4085 +CONFIG_DEBUG_FS=y
4086 +# CONFIG_HEADERS_CHECK is not set
4087 +CONFIG_DEBUG_KERNEL=y
4088 +CONFIG_DEBUG_SHIRQ=y
4089 +CONFIG_DETECT_SOFTLOCKUP=y
4090 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
4091 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
4092 +CONFIG_SCHED_DEBUG=y
4093 +CONFIG_SCHEDSTATS=y
4094 +CONFIG_TIMER_STATS=y
4095 +# CONFIG_DEBUG_OBJECTS is not set
4096 +# CONFIG_DEBUG_SLAB is not set
4097 +CONFIG_DEBUG_PREEMPT=y
4098 +# CONFIG_DEBUG_RT_MUTEXES is not set
4099 +# CONFIG_RT_MUTEX_TESTER is not set
4100 +CONFIG_DEBUG_SPINLOCK=y
4101 +CONFIG_DEBUG_MUTEXES=y
4102 +CONFIG_DEBUG_LOCK_ALLOC=y
4103 +# CONFIG_PROVE_LOCKING is not set
4104 +CONFIG_LOCKDEP=y
4105 +CONFIG_LOCK_STAT=y
4106 +CONFIG_DEBUG_LOCKDEP=y
4107 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
4108 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
4109 +CONFIG_STACKTRACE=y
4110 +# CONFIG_DEBUG_KOBJECT is not set
4111 +CONFIG_DEBUG_BUGVERBOSE=y
4112 +CONFIG_DEBUG_INFO=y
4113 +# CONFIG_DEBUG_VM is not set
4114 +# CONFIG_DEBUG_WRITECOUNT is not set
4115 +CONFIG_DEBUG_MEMORY_INIT=y
4116 +# CONFIG_DEBUG_LIST is not set
4117 +CONFIG_DEBUG_SG=y
4118 +CONFIG_FRAME_POINTER=y
4119 +# CONFIG_BOOT_PRINTK_DELAY is not set
4120 +# CONFIG_RCU_TORTURE_TEST is not set
4121 +CONFIG_RCU_CPU_STALL_DETECTOR=y
4122 +# CONFIG_BACKTRACE_SELF_TEST is not set
4123 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
4124 +# CONFIG_FAULT_INJECTION is not set
4125 +CONFIG_LATENCYTOP=y
4126 +CONFIG_SYSCTL_SYSCALL_CHECK=y
4127 +CONFIG_HAVE_FUNCTION_TRACER=y
4128 +
4129 +#
4130 +# Tracers
4131 +#
4132 +# CONFIG_FUNCTION_TRACER is not set
4133 +# CONFIG_SCHED_TRACER is not set
4134 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
4135 +# CONFIG_BOOT_TRACER is not set
4136 +# CONFIG_STACK_TRACER is not set
4137 +CONFIG_DYNAMIC_PRINTK_DEBUG=y
4138 +# CONFIG_SAMPLES is not set
4139 +CONFIG_HAVE_ARCH_KGDB=y
4140 +# CONFIG_KGDB is not set
4141 +# CONFIG_DEBUG_USER is not set
4142 +CONFIG_DEBUG_ERRORS=y
4143 +# CONFIG_DEBUG_STACK_USAGE is not set
4144 +# CONFIG_DEBUG_LL is not set
4145 +CONFIG_DEBUG_S3C_UART=2
4146 +
4147 +#
4148 +# Security options
4149 +#
4150 +# CONFIG_KEYS is not set
4151 +# CONFIG_SECURITY is not set
4152 +CONFIG_SECURITYFS=y
4153 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
4154 +CONFIG_CRYPTO=y
4155 +
4156 +#
4157 +# Crypto core or helper
4158 +#
4159 +CONFIG_CRYPTO_FIPS=y
4160 +CONFIG_CRYPTO_ALGAPI=y
4161 +CONFIG_CRYPTO_AEAD=y
4162 +CONFIG_CRYPTO_BLKCIPHER=y
4163 +CONFIG_CRYPTO_HASH=y
4164 +CONFIG_CRYPTO_RNG=y
4165 +CONFIG_CRYPTO_MANAGER=y
4166 +CONFIG_CRYPTO_GF128MUL=m
4167 +CONFIG_CRYPTO_NULL=m
4168 +# CONFIG_CRYPTO_CRYPTD is not set
4169 +CONFIG_CRYPTO_AUTHENC=m
4170 +CONFIG_CRYPTO_TEST=m
4171 +
4172 +#
4173 +# Authenticated Encryption with Associated Data
4174 +#
4175 +# CONFIG_CRYPTO_CCM is not set
4176 +# CONFIG_CRYPTO_GCM is not set
4177 +# CONFIG_CRYPTO_SEQIV is not set
4178 +
4179 +#
4180 +# Block modes
4181 +#
4182 +CONFIG_CRYPTO_CBC=y
4183 +# CONFIG_CRYPTO_CTR is not set
4184 +# CONFIG_CRYPTO_CTS is not set
4185 +CONFIG_CRYPTO_ECB=m
4186 +CONFIG_CRYPTO_LRW=m
4187 +CONFIG_CRYPTO_PCBC=m
4188 +# CONFIG_CRYPTO_XTS is not set
4189 +
4190 +#
4191 +# Hash modes
4192 +#
4193 +CONFIG_CRYPTO_HMAC=y
4194 +CONFIG_CRYPTO_XCBC=m
4195 +
4196 +#
4197 +# Digest
4198 +#
4199 +CONFIG_CRYPTO_CRC32C=m
4200 +CONFIG_CRYPTO_MD4=m
4201 +CONFIG_CRYPTO_MD5=y
4202 +CONFIG_CRYPTO_MICHAEL_MIC=m
4203 +# CONFIG_CRYPTO_RMD128 is not set
4204 +# CONFIG_CRYPTO_RMD160 is not set
4205 +# CONFIG_CRYPTO_RMD256 is not set
4206 +# CONFIG_CRYPTO_RMD320 is not set
4207 +CONFIG_CRYPTO_SHA1=m
4208 +CONFIG_CRYPTO_SHA256=m
4209 +CONFIG_CRYPTO_SHA512=m
4210 +CONFIG_CRYPTO_TGR192=m
4211 +CONFIG_CRYPTO_WP512=m
4212 +
4213 +#
4214 +# Ciphers
4215 +#
4216 +CONFIG_CRYPTO_AES=y
4217 +CONFIG_CRYPTO_ANUBIS=m
4218 +CONFIG_CRYPTO_ARC4=m
4219 +CONFIG_CRYPTO_BLOWFISH=m
4220 +CONFIG_CRYPTO_CAMELLIA=m
4221 +CONFIG_CRYPTO_CAST5=m
4222 +CONFIG_CRYPTO_CAST6=m
4223 +CONFIG_CRYPTO_DES=y
4224 +CONFIG_CRYPTO_FCRYPT=m
4225 +CONFIG_CRYPTO_KHAZAD=m
4226 +# CONFIG_CRYPTO_SALSA20 is not set
4227 +# CONFIG_CRYPTO_SEED is not set
4228 +CONFIG_CRYPTO_SERPENT=m
4229 +CONFIG_CRYPTO_TEA=m
4230 +CONFIG_CRYPTO_TWOFISH=m
4231 +CONFIG_CRYPTO_TWOFISH_COMMON=m
4232 +
4233 +#
4234 +# Compression
4235 +#
4236 +CONFIG_CRYPTO_DEFLATE=m
4237 +# CONFIG_CRYPTO_LZO is not set
4238 +
4239 +#
4240 +# Random Number Generation
4241 +#
4242 +CONFIG_CRYPTO_ANSI_CPRNG=y
4243 +CONFIG_CRYPTO_HW=y
4244 +
4245 +#
4246 +# Library routines
4247 +#
4248 +CONFIG_BITREVERSE=y
4249 +CONFIG_CRC_CCITT=m
4250 +CONFIG_CRC16=y
4251 +CONFIG_CRC_T10DIF=y
4252 +CONFIG_CRC_ITU_T=m
4253 +CONFIG_CRC32=y
4254 +# CONFIG_CRC7 is not set
4255 +CONFIG_LIBCRC32C=m
4256 +CONFIG_ZLIB_INFLATE=y
4257 +CONFIG_ZLIB_DEFLATE=y
4258 +CONFIG_TEXTSEARCH=y
4259 +CONFIG_TEXTSEARCH_KMP=m
4260 +CONFIG_TEXTSEARCH_BM=m
4261 +CONFIG_TEXTSEARCH_FSM=m
4262 +CONFIG_PLIST=y
4263 +CONFIG_HAS_IOMEM=y
4264 +CONFIG_HAS_DMA=y
4265 Index: linux-2.6.28/arch/arm/configs/gta03_defconfig
4266 ===================================================================
4267 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4268 +++ linux-2.6.28/arch/arm/configs/gta03_defconfig       2009-01-02 00:01:56.000000000 +0100
4269 @@ -0,0 +1,1548 @@
4270 +#
4271 +# Automatically generated make config: don't edit
4272 +# Linux kernel version: 2.6.28-rc4
4273 +# Fri Dec 12 12:07:49 2008
4274 +#
4275 +CONFIG_ARM=y
4276 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
4277 +CONFIG_GENERIC_GPIO=y
4278 +# CONFIG_GENERIC_TIME is not set
4279 +# CONFIG_GENERIC_CLOCKEVENTS is not set
4280 +CONFIG_MMU=y
4281 +CONFIG_NO_IOPORT=y
4282 +CONFIG_GENERIC_HARDIRQS=y
4283 +CONFIG_STACKTRACE_SUPPORT=y
4284 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
4285 +CONFIG_LOCKDEP_SUPPORT=y
4286 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
4287 +CONFIG_HARDIRQS_SW_RESEND=y
4288 +CONFIG_GENERIC_IRQ_PROBE=y
4289 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
4290 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
4291 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
4292 +CONFIG_GENERIC_HWEIGHT=y
4293 +CONFIG_GENERIC_CALIBRATE_DELAY=y
4294 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
4295 +CONFIG_VECTORS_BASE=0xffff0000
4296 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
4297 +
4298 +#
4299 +# General setup
4300 +#
4301 +CONFIG_EXPERIMENTAL=y
4302 +CONFIG_BROKEN_ON_SMP=y
4303 +CONFIG_INIT_ENV_ARG_LIMIT=32
4304 +CONFIG_LOCALVERSION=""
4305 +CONFIG_LOCALVERSION_AUTO=y
4306 +CONFIG_SWAP=y
4307 +# CONFIG_SYSVIPC is not set
4308 +# CONFIG_POSIX_MQUEUE is not set
4309 +# CONFIG_BSD_PROCESS_ACCT is not set
4310 +# CONFIG_TASKSTATS is not set
4311 +# CONFIG_AUDIT is not set
4312 +CONFIG_IKCONFIG=y
4313 +CONFIG_IKCONFIG_PROC=y
4314 +CONFIG_LOG_BUF_SHIFT=18
4315 +# CONFIG_CGROUPS is not set
4316 +# CONFIG_GROUP_SCHED is not set
4317 +CONFIG_SYSFS_DEPRECATED=y
4318 +CONFIG_SYSFS_DEPRECATED_V2=y
4319 +# CONFIG_RELAY is not set
4320 +CONFIG_NAMESPACES=y
4321 +# CONFIG_UTS_NS is not set
4322 +# CONFIG_USER_NS is not set
4323 +# CONFIG_PID_NS is not set
4324 +CONFIG_BLK_DEV_INITRD=y
4325 +CONFIG_INITRAMFS_SOURCE=""
4326 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
4327 +CONFIG_SYSCTL=y
4328 +# CONFIG_EMBEDDED is not set
4329 +CONFIG_UID16=y
4330 +CONFIG_SYSCTL_SYSCALL=y
4331 +CONFIG_KALLSYMS=y
4332 +CONFIG_KALLSYMS_ALL=y
4333 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
4334 +CONFIG_HOTPLUG=y
4335 +CONFIG_PRINTK=y
4336 +CONFIG_BUG=y
4337 +CONFIG_ELF_CORE=y
4338 +CONFIG_COMPAT_BRK=y
4339 +CONFIG_BASE_FULL=y
4340 +CONFIG_FUTEX=y
4341 +CONFIG_ANON_INODES=y
4342 +CONFIG_EPOLL=y
4343 +CONFIG_SIGNALFD=y
4344 +CONFIG_TIMERFD=y
4345 +CONFIG_EVENTFD=y
4346 +CONFIG_SHMEM=y
4347 +CONFIG_AIO=y
4348 +CONFIG_ASHMEM=y
4349 +CONFIG_VM_EVENT_COUNTERS=y
4350 +CONFIG_SLUB_DEBUG=y
4351 +# CONFIG_SLAB is not set
4352 +CONFIG_SLUB=y
4353 +# CONFIG_SLOB is not set
4354 +# CONFIG_PROFILING is not set
4355 +# CONFIG_MARKERS is not set
4356 +CONFIG_HAVE_OPROFILE=y
4357 +# CONFIG_KPROBES is not set
4358 +CONFIG_HAVE_KPROBES=y
4359 +CONFIG_HAVE_KRETPROBES=y
4360 +CONFIG_HAVE_CLK=y
4361 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
4362 +CONFIG_SLABINFO=y
4363 +CONFIG_RT_MUTEXES=y
4364 +# CONFIG_TINY_SHMEM is not set
4365 +CONFIG_BASE_SMALL=0
4366 +CONFIG_MODULES=y
4367 +# CONFIG_MODULE_FORCE_LOAD is not set
4368 +CONFIG_MODULE_UNLOAD=y
4369 +# CONFIG_MODULE_FORCE_UNLOAD is not set
4370 +# CONFIG_MODVERSIONS is not set
4371 +# CONFIG_MODULE_SRCVERSION_ALL is not set
4372 +CONFIG_KMOD=y
4373 +CONFIG_BLOCK=y
4374 +CONFIG_LBD=y
4375 +# CONFIG_BLK_DEV_IO_TRACE is not set
4376 +CONFIG_LSF=y
4377 +# CONFIG_BLK_DEV_BSG is not set
4378 +# CONFIG_BLK_DEV_INTEGRITY is not set
4379 +
4380 +#
4381 +# IO Schedulers
4382 +#
4383 +CONFIG_IOSCHED_NOOP=y
4384 +CONFIG_IOSCHED_AS=y
4385 +CONFIG_IOSCHED_DEADLINE=y
4386 +CONFIG_IOSCHED_CFQ=y
4387 +# CONFIG_DEFAULT_AS is not set
4388 +# CONFIG_DEFAULT_DEADLINE is not set
4389 +CONFIG_DEFAULT_CFQ=y
4390 +# CONFIG_DEFAULT_NOOP is not set
4391 +CONFIG_DEFAULT_IOSCHED="cfq"
4392 +CONFIG_CLASSIC_RCU=y
4393 +CONFIG_FREEZER=y
4394 +
4395 +#
4396 +# System Type
4397 +#
4398 +# CONFIG_ARCH_AAEC2000 is not set
4399 +# CONFIG_ARCH_INTEGRATOR is not set
4400 +# CONFIG_ARCH_REALVIEW is not set
4401 +# CONFIG_ARCH_VERSATILE is not set
4402 +# CONFIG_ARCH_AT91 is not set
4403 +# CONFIG_ARCH_CLPS7500 is not set
4404 +# CONFIG_ARCH_CLPS711X is not set
4405 +# CONFIG_ARCH_EBSA110 is not set
4406 +# CONFIG_ARCH_EP93XX is not set
4407 +# CONFIG_ARCH_FOOTBRIDGE is not set
4408 +# CONFIG_ARCH_NETX is not set
4409 +# CONFIG_ARCH_H720X is not set
4410 +# CONFIG_ARCH_IMX is not set
4411 +# CONFIG_ARCH_IOP13XX is not set
4412 +# CONFIG_ARCH_IOP32X is not set
4413 +# CONFIG_ARCH_IOP33X is not set
4414 +# CONFIG_ARCH_IXP23XX is not set
4415 +# CONFIG_ARCH_IXP2000 is not set
4416 +# CONFIG_ARCH_IXP4XX is not set
4417 +# CONFIG_ARCH_L7200 is not set
4418 +# CONFIG_ARCH_KIRKWOOD is not set
4419 +# CONFIG_ARCH_KS8695 is not set
4420 +# CONFIG_ARCH_NS9XXX is not set
4421 +# CONFIG_ARCH_LOKI is not set
4422 +# CONFIG_ARCH_MV78XX0 is not set
4423 +# CONFIG_ARCH_MXC is not set
4424 +# CONFIG_ARCH_ORION5X is not set
4425 +# CONFIG_ARCH_PNX4008 is not set
4426 +# CONFIG_ARCH_PXA is not set
4427 +# CONFIG_ARCH_RPC is not set
4428 +# CONFIG_ARCH_SA1100 is not set
4429 +# CONFIG_ARCH_S3C2410 is not set
4430 +CONFIG_ARCH_S3C64XX=y
4431 +# CONFIG_ARCH_SHARK is not set
4432 +# CONFIG_ARCH_LH7A40X is not set
4433 +# CONFIG_ARCH_DAVINCI is not set
4434 +# CONFIG_ARCH_OMAP is not set
4435 +# CONFIG_ARCH_MSM is not set
4436 +CONFIG_MACH_NEO1973=y
4437 +CONFIG_PLAT_S3C64XX=y
4438 +CONFIG_CPU_S3C6400_INIT=y
4439 +CONFIG_CPU_S3C6400_CLOCK=y
4440 +CONFIG_S3C64XX_SETUP_I2C0=y
4441 +CONFIG_S3C64XX_SETUP_I2C1=y
4442 +CONFIG_S3C64XX_SETUP_FB_24BPP=y
4443 +CONFIG_PLAT_S3C=y
4444 +
4445 +#
4446 +# Boot options
4447 +#
4448 +CONFIG_S3C_BOOT_ERROR_RESET=y
4449 +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
4450 +
4451 +#
4452 +# Power management
4453 +#
4454 +# CONFIG_S3C2410_PM_DEBUG is not set
4455 +# CONFIG_S3C2410_PM_CHECK is not set
4456 +CONFIG_S3C_LOWLEVEL_UART_PORT=3
4457 +CONFIG_S3C_GPIO_SPACE=0
4458 +CONFIG_S3C_GPIO_TRACK=y
4459 +CONFIG_S3C_GPIO_PULL_UPDOWN=y
4460 +CONFIG_S3C_GPIO_CFG_S3C24XX=y
4461 +CONFIG_S3C_GPIO_CFG_S3C64XX=y
4462 +CONFIG_S3C_DEV_HSMMC=y
4463 +CONFIG_S3C_DEV_HSMMC1=y
4464 +CONFIG_S3C_DEV_I2C1=y
4465 +CONFIG_S3C_DEV_FB=y
4466 +CONFIG_CPU_S3C6410=y
4467 +CONFIG_S3C6410_SETUP_SDHCI=y
4468 +# CONFIG_MACH_SMDK6410 is not set
4469 +CONFIG_MACH_OPENMOKO_GTA03=y
4470 +
4471 +#
4472 +# Processor Type
4473 +#
4474 +CONFIG_CPU_32=y
4475 +CONFIG_CPU_V6=y
4476 +CONFIG_CPU_32v6K=y
4477 +CONFIG_CPU_32v6=y
4478 +CONFIG_CPU_ABRT_EV6=y
4479 +CONFIG_CPU_PABRT_NOIFAR=y
4480 +CONFIG_CPU_CACHE_V6=y
4481 +CONFIG_CPU_CACHE_VIPT=y
4482 +CONFIG_CPU_COPY_V6=y
4483 +CONFIG_CPU_TLB_V6=y
4484 +CONFIG_CPU_HAS_ASID=y
4485 +CONFIG_CPU_CP15=y
4486 +CONFIG_CPU_CP15_MMU=y
4487 +
4488 +#
4489 +# Processor Features
4490 +#
4491 +CONFIG_ARM_THUMB=y
4492 +# CONFIG_CPU_ICACHE_DISABLE is not set
4493 +# CONFIG_CPU_DCACHE_DISABLE is not set
4494 +# CONFIG_CPU_BPREDICT_DISABLE is not set
4495 +# CONFIG_OUTER_CACHE is not set
4496 +CONFIG_ARM_VIC=y
4497 +
4498 +#
4499 +# Bus support
4500 +#
4501 +# CONFIG_PCI_SYSCALL is not set
4502 +# CONFIG_ARCH_SUPPORTS_MSI is not set
4503 +# CONFIG_PCCARD is not set
4504 +
4505 +#
4506 +# Kernel Features
4507 +#
4508 +CONFIG_VMSPLIT_3G=y
4509 +# CONFIG_VMSPLIT_2G is not set
4510 +# CONFIG_VMSPLIT_1G is not set
4511 +CONFIG_PAGE_OFFSET=0xC0000000
4512 +# CONFIG_PREEMPT is not set
4513 +CONFIG_HZ=100
4514 +CONFIG_AEABI=y
4515 +CONFIG_OABI_COMPAT=y
4516 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
4517 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
4518 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
4519 +CONFIG_SELECT_MEMORY_MODEL=y
4520 +CONFIG_FLATMEM_MANUAL=y
4521 +# CONFIG_DISCONTIGMEM_MANUAL is not set
4522 +# CONFIG_SPARSEMEM_MANUAL is not set
4523 +CONFIG_FLATMEM=y
4524 +CONFIG_FLAT_NODE_MEM_MAP=y
4525 +CONFIG_PAGEFLAGS_EXTENDED=y
4526 +CONFIG_SPLIT_PTLOCK_CPUS=4
4527 +# CONFIG_RESOURCES_64BIT is not set
4528 +# CONFIG_PHYS_ADDR_T_64BIT is not set
4529 +CONFIG_ZONE_DMA_FLAG=0
4530 +CONFIG_VIRT_TO_BUS=y
4531 +CONFIG_UNEVICTABLE_LRU=y
4532 +CONFIG_ALIGNMENT_TRAP=y
4533 +
4534 +#
4535 +# Boot options
4536 +#
4537 +CONFIG_ZBOOT_ROM_TEXT=0
4538 +CONFIG_ZBOOT_ROM_BSS=0
4539 +CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
4540 +# CONFIG_XIP_KERNEL is not set
4541 +# CONFIG_KEXEC is not set
4542 +
4543 +#
4544 +# CPU Power Management
4545 +#
4546 +CONFIG_CPU_IDLE=y
4547 +CONFIG_CPU_IDLE_GOV_LADDER=y
4548 +
4549 +#
4550 +# Floating point emulation
4551 +#
4552 +
4553 +#
4554 +# At least one emulation must be selected
4555 +#
4556 +# CONFIG_FPE_NWFPE is not set
4557 +# CONFIG_FPE_FASTFPE is not set
4558 +CONFIG_VFP=y
4559 +
4560 +#
4561 +# Userspace binary formats
4562 +#
4563 +CONFIG_BINFMT_ELF=y
4564 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
4565 +CONFIG_HAVE_AOUT=y
4566 +# CONFIG_BINFMT_AOUT is not set
4567 +# CONFIG_BINFMT_MISC is not set
4568 +
4569 +#
4570 +# Power management options
4571 +#
4572 +CONFIG_PM=y
4573 +# CONFIG_PM_DEBUG is not set
4574 +CONFIG_PM_SLEEP=y
4575 +CONFIG_SUSPEND=y
4576 +CONFIG_SUSPEND_FREEZER=y
4577 +CONFIG_APM_EMULATION=y
4578 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
4579 +CONFIG_NET=y
4580 +
4581 +#
4582 +# Networking options
4583 +#
4584 +CONFIG_PACKET=y
4585 +CONFIG_PACKET_MMAP=y
4586 +CONFIG_UNIX=y
4587 +CONFIG_XFRM=y
4588 +# CONFIG_XFRM_USER is not set
4589 +# CONFIG_XFRM_SUB_POLICY is not set
4590 +CONFIG_XFRM_MIGRATE=y
4591 +# CONFIG_XFRM_STATISTICS is not set
4592 +# CONFIG_NET_KEY is not set
4593 +CONFIG_INET=y
4594 +CONFIG_IP_MULTICAST=y
4595 +CONFIG_IP_ADVANCED_ROUTER=y
4596 +CONFIG_ASK_IP_FIB_HASH=y
4597 +# CONFIG_IP_FIB_TRIE is not set
4598 +CONFIG_IP_FIB_HASH=y
4599 +CONFIG_IP_MULTIPLE_TABLES=y
4600 +# CONFIG_IP_ROUTE_MULTIPATH is not set
4601 +# CONFIG_IP_ROUTE_VERBOSE is not set
4602 +CONFIG_IP_PNP=y
4603 +# CONFIG_IP_PNP_DHCP is not set
4604 +# CONFIG_IP_PNP_BOOTP is not set
4605 +# CONFIG_IP_PNP_RARP is not set
4606 +# CONFIG_NET_IPIP is not set
4607 +# CONFIG_NET_IPGRE is not set
4608 +# CONFIG_IP_MROUTE is not set
4609 +# CONFIG_ARPD is not set
4610 +CONFIG_SYN_COOKIES=y
4611 +# CONFIG_INET_AH is not set
4612 +# CONFIG_INET_ESP is not set
4613 +# CONFIG_INET_IPCOMP is not set
4614 +# CONFIG_INET_XFRM_TUNNEL is not set
4615 +CONFIG_INET_TUNNEL=m
4616 +CONFIG_INET_XFRM_MODE_TRANSPORT=y
4617 +CONFIG_INET_XFRM_MODE_TUNNEL=y
4618 +CONFIG_INET_XFRM_MODE_BEET=y
4619 +# CONFIG_INET_LRO is not set
4620 +CONFIG_INET_DIAG=y
4621 +CONFIG_INET_TCP_DIAG=y
4622 +# CONFIG_TCP_CONG_ADVANCED is not set
4623 +CONFIG_TCP_CONG_CUBIC=y
4624 +CONFIG_DEFAULT_TCP_CONG="cubic"
4625 +CONFIG_TCP_MD5SIG=y
4626 +CONFIG_IPV6=m
4627 +# CONFIG_IPV6_PRIVACY is not set
4628 +# CONFIG_IPV6_ROUTER_PREF is not set
4629 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
4630 +# CONFIG_INET6_AH is not set
4631 +# CONFIG_INET6_ESP is not set
4632 +# CONFIG_INET6_IPCOMP is not set
4633 +# CONFIG_IPV6_MIP6 is not set
4634 +# CONFIG_INET6_XFRM_TUNNEL is not set
4635 +# CONFIG_INET6_TUNNEL is not set
4636 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
4637 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
4638 +CONFIG_INET6_XFRM_MODE_BEET=m
4639 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
4640 +CONFIG_IPV6_SIT=m
4641 +CONFIG_IPV6_NDISC_NODETYPE=y
4642 +# CONFIG_IPV6_TUNNEL is not set
4643 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
4644 +# CONFIG_IPV6_MROUTE is not set
4645 +# CONFIG_NETWORK_SECMARK is not set
4646 +CONFIG_NETFILTER=y
4647 +# CONFIG_NETFILTER_DEBUG is not set
4648 +CONFIG_NETFILTER_ADVANCED=y
4649 +
4650 +#
4651 +# Core Netfilter Configuration
4652 +#
4653 +# CONFIG_NETFILTER_NETLINK_QUEUE is not set
4654 +# CONFIG_NETFILTER_NETLINK_LOG is not set
4655 +# CONFIG_NF_CONNTRACK is not set
4656 +CONFIG_NETFILTER_XTABLES=m
4657 +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
4658 +# CONFIG_NETFILTER_XT_TARGET_MARK is not set
4659 +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
4660 +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
4661 +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
4662 +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
4663 +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
4664 +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
4665 +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
4666 +# CONFIG_NETFILTER_XT_MATCH_ESP is not set
4667 +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
4668 +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
4669 +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
4670 +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
4671 +# CONFIG_NETFILTER_XT_MATCH_MAC is not set
4672 +# CONFIG_NETFILTER_XT_MATCH_MARK is not set
4673 +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
4674 +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
4675 +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
4676 +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
4677 +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
4678 +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
4679 +# CONFIG_NETFILTER_XT_MATCH_REALM is not set
4680 +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
4681 +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
4682 +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
4683 +# CONFIG_NETFILTER_XT_MATCH_STRING is not set
4684 +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
4685 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
4686 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
4687 +# CONFIG_IP_VS is not set
4688 +
4689 +#
4690 +# IP: Netfilter Configuration
4691 +#
4692 +# CONFIG_NF_DEFRAG_IPV4 is not set
4693 +# CONFIG_IP_NF_QUEUE is not set
4694 +# CONFIG_IP_NF_IPTABLES is not set
4695 +# CONFIG_IP_NF_ARPTABLES is not set
4696 +
4697 +#
4698 +# IPv6: Netfilter Configuration
4699 +#
4700 +# CONFIG_IP6_NF_QUEUE is not set
4701 +CONFIG_IP6_NF_IPTABLES=m
4702 +# CONFIG_IP6_NF_MATCH_AH is not set
4703 +# CONFIG_IP6_NF_MATCH_EUI64 is not set
4704 +# CONFIG_IP6_NF_MATCH_FRAG is not set
4705 +# CONFIG_IP6_NF_MATCH_OPTS is not set
4706 +# CONFIG_IP6_NF_MATCH_HL is not set
4707 +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
4708 +# CONFIG_IP6_NF_MATCH_MH is not set
4709 +# CONFIG_IP6_NF_MATCH_RT is not set
4710 +# CONFIG_IP6_NF_TARGET_LOG is not set
4711 +# CONFIG_IP6_NF_FILTER is not set
4712 +# CONFIG_IP6_NF_MANGLE is not set
4713 +# CONFIG_IP6_NF_RAW is not set
4714 +# CONFIG_IP_DCCP is not set
4715 +# CONFIG_IP_SCTP is not set
4716 +# CONFIG_TIPC is not set
4717 +# CONFIG_ATM is not set
4718 +# CONFIG_BRIDGE is not set
4719 +# CONFIG_NET_DSA is not set
4720 +# CONFIG_VLAN_8021Q is not set
4721 +# CONFIG_DECNET is not set
4722 +# CONFIG_LLC2 is not set
4723 +# CONFIG_IPX is not set
4724 +# CONFIG_ATALK is not set
4725 +# CONFIG_X25 is not set
4726 +# CONFIG_LAPB is not set
4727 +# CONFIG_ECONET is not set
4728 +# CONFIG_WAN_ROUTER is not set
4729 +# CONFIG_NET_SCHED is not set
4730 +
4731 +#
4732 +# Network testing
4733 +#
4734 +# CONFIG_NET_PKTGEN is not set
4735 +# CONFIG_HAMRADIO is not set
4736 +# CONFIG_CAN is not set
4737 +# CONFIG_IRDA is not set
4738 +# CONFIG_BT is not set
4739 +# CONFIG_AF_RXRPC is not set
4740 +# CONFIG_PHONET is not set
4741 +CONFIG_FIB_RULES=y
4742 +CONFIG_WIRELESS=y
4743 +CONFIG_CFG80211=y
4744 +CONFIG_NL80211=y
4745 +CONFIG_WIRELESS_OLD_REGULATORY=y
4746 +CONFIG_WIRELESS_EXT=y
4747 +CONFIG_WIRELESS_EXT_SYSFS=y
4748 +CONFIG_MAC80211=y
4749 +
4750 +#
4751 +# Rate control algorithm selection
4752 +#
4753 +CONFIG_MAC80211_RC_PID=y
4754 +# CONFIG_MAC80211_RC_MINSTREL is not set
4755 +CONFIG_MAC80211_RC_DEFAULT_PID=y
4756 +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
4757 +CONFIG_MAC80211_RC_DEFAULT="pid"
4758 +# CONFIG_MAC80211_MESH is not set
4759 +CONFIG_MAC80211_LEDS=y
4760 +# CONFIG_MAC80211_DEBUG_MENU is not set
4761 +# CONFIG_IEEE80211 is not set
4762 +# CONFIG_RFKILL is not set
4763 +# CONFIG_NET_9P is not set
4764 +
4765 +#
4766 +# Device Drivers
4767 +#
4768 +
4769 +#
4770 +# Generic Driver Options
4771 +#
4772 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
4773 +CONFIG_STANDALONE=y
4774 +CONFIG_PREVENT_FIRMWARE_BUILD=y
4775 +CONFIG_FW_LOADER=y
4776 +CONFIG_FIRMWARE_IN_KERNEL=y
4777 +CONFIG_EXTRA_FIRMWARE=""
4778 +# CONFIG_DEBUG_DRIVER is not set
4779 +# CONFIG_DEBUG_DEVRES is not set
4780 +# CONFIG_SYS_HYPERVISOR is not set
4781 +# CONFIG_CONNECTOR is not set
4782 +CONFIG_MTD=y
4783 +# CONFIG_MTD_DEBUG is not set
4784 +# CONFIG_MTD_CONCAT is not set
4785 +CONFIG_MTD_PARTITIONS=y
4786 +# CONFIG_MTD_REDBOOT_PARTS is not set
4787 +CONFIG_MTD_CMDLINE_PARTS=y
4788 +# CONFIG_MTD_AFS_PARTS is not set
4789 +# CONFIG_MTD_AR7_PARTS is not set
4790 +
4791 +#
4792 +# User Modules And Translation Layers
4793 +#
4794 +CONFIG_MTD_CHAR=y
4795 +CONFIG_MTD_BLKDEVS=y
4796 +CONFIG_MTD_BLOCK=y
4797 +# CONFIG_FTL is not set
4798 +# CONFIG_NFTL is not set
4799 +# CONFIG_INFTL is not set
4800 +# CONFIG_RFD_FTL is not set
4801 +# CONFIG_SSFDC is not set
4802 +# CONFIG_MTD_OOPS is not set
4803 +
4804 +#
4805 +# RAM/ROM/Flash chip drivers
4806 +#
4807 +# CONFIG_MTD_CFI is not set
4808 +# CONFIG_MTD_JEDECPROBE is not set
4809 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
4810 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
4811 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
4812 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
4813 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
4814 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
4815 +CONFIG_MTD_CFI_I1=y
4816 +CONFIG_MTD_CFI_I2=y
4817 +# CONFIG_MTD_CFI_I4 is not set
4818 +# CONFIG_MTD_CFI_I8 is not set
4819 +# CONFIG_MTD_RAM is not set
4820 +# CONFIG_MTD_ROM is not set
4821 +# CONFIG_MTD_ABSENT is not set
4822 +
4823 +#
4824 +# Mapping drivers for chip access
4825 +#
4826 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
4827 +# CONFIG_MTD_PLATRAM is not set
4828 +
4829 +#
4830 +# Self-contained MTD device drivers
4831 +#
4832 +# CONFIG_MTD_DATAFLASH is not set
4833 +# CONFIG_MTD_M25P80 is not set
4834 +# CONFIG_MTD_SLRAM is not set
4835 +# CONFIG_MTD_PHRAM is not set
4836 +# CONFIG_MTD_MTDRAM is not set
4837 +# CONFIG_MTD_BLOCK2MTD is not set
4838 +
4839 +#
4840 +# Disk-On-Chip Device Drivers
4841 +#
4842 +# CONFIG_MTD_DOC2000 is not set
4843 +# CONFIG_MTD_DOC2001 is not set
4844 +# CONFIG_MTD_DOC2001PLUS is not set
4845 +# CONFIG_MTD_NAND is not set
4846 +CONFIG_MTD_ONENAND=y
4847 +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
4848 +CONFIG_MTD_ONENAND_GENERIC=y
4849 +# CONFIG_MTD_ONENAND_OTP is not set
4850 +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
4851 +# CONFIG_MTD_ONENAND_SIM is not set
4852 +
4853 +#
4854 +# UBI - Unsorted block images
4855 +#
4856 +# CONFIG_MTD_UBI is not set
4857 +# CONFIG_PARPORT is not set
4858 +CONFIG_BLK_DEV=y
4859 +# CONFIG_BLK_DEV_COW_COMMON is not set
4860 +CONFIG_BLK_DEV_LOOP=y
4861 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
4862 +# CONFIG_BLK_DEV_NBD is not set
4863 +CONFIG_BLK_DEV_RAM=y
4864 +CONFIG_BLK_DEV_RAM_COUNT=16
4865 +CONFIG_BLK_DEV_RAM_SIZE=8192
4866 +# CONFIG_BLK_DEV_XIP is not set
4867 +# CONFIG_CDROM_PKTCDVD is not set
4868 +# CONFIG_ATA_OVER_ETH is not set
4869 +CONFIG_MISC_DEVICES=y
4870 +# CONFIG_EEPROM_93CX6 is not set
4871 +CONFIG_LOW_MEMORY_KILLER=y
4872 +# CONFIG_ENCLOSURE_SERVICES is not set
4873 +CONFIG_HAVE_IDE=y
4874 +# CONFIG_IDE is not set
4875 +
4876 +#
4877 +# SCSI device support
4878 +#
4879 +# CONFIG_RAID_ATTRS is not set
4880 +# CONFIG_SCSI is not set
4881 +# CONFIG_SCSI_DMA is not set
4882 +# CONFIG_SCSI_NETLINK is not set
4883 +# CONFIG_ATA is not set
4884 +# CONFIG_MD is not set
4885 +CONFIG_NETDEVICES=y
4886 +# CONFIG_DUMMY is not set
4887 +# CONFIG_BONDING is not set
4888 +# CONFIG_MACVLAN is not set
4889 +# CONFIG_EQUALIZER is not set
4890 +CONFIG_TUN=y
4891 +# CONFIG_VETH is not set
4892 +# CONFIG_NET_ETHERNET is not set
4893 +# CONFIG_NETDEV_1000 is not set
4894 +# CONFIG_NETDEV_10000 is not set
4895 +
4896 +#
4897 +# Wireless LAN
4898 +#
4899 +# CONFIG_WLAN_PRE80211 is not set
4900 +# CONFIG_WLAN_80211 is not set
4901 +# CONFIG_IWLWIFI_LEDS is not set
4902 +# CONFIG_WAN is not set
4903 +CONFIG_PPP=y
4904 +# CONFIG_PPP_MULTILINK is not set
4905 +# CONFIG_PPP_FILTER is not set
4906 +CONFIG_PPP_ASYNC=y
4907 +CONFIG_PPP_SYNC_TTY=y
4908 +CONFIG_PPP_DEFLATE=y
4909 +CONFIG_PPP_BSDCOMP=y
4910 +CONFIG_PPP_MPPE=y
4911 +# CONFIG_PPPOE is not set
4912 +# CONFIG_PPPOL2TP is not set
4913 +# CONFIG_SLIP is not set
4914 +CONFIG_SLHC=y
4915 +# CONFIG_NETCONSOLE is not set
4916 +# CONFIG_NETPOLL is not set
4917 +# CONFIG_NET_POLL_CONTROLLER is not set
4918 +# CONFIG_ISDN is not set
4919 +
4920 +#
4921 +# Input device support
4922 +#
4923 +CONFIG_INPUT=y
4924 +# CONFIG_INPUT_FF_MEMLESS is not set
4925 +# CONFIG_INPUT_POLLDEV is not set
4926 +
4927 +#
4928 +# Userland interfaces
4929 +#
4930 +CONFIG_INPUT_MOUSEDEV=y
4931 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
4932 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
4933 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
4934 +# CONFIG_INPUT_JOYDEV is not set
4935 +CONFIG_INPUT_EVDEV=y
4936 +# CONFIG_INPUT_EVBUG is not set
4937 +
4938 +#
4939 +# Input Device Drivers
4940 +#
4941 +CONFIG_INPUT_KEYBOARD=y
4942 +CONFIG_KEYBOARD_ATKBD=y
4943 +# CONFIG_KEYBOARD_SUNKBD is not set
4944 +# CONFIG_KEYBOARD_LKKBD is not set
4945 +# CONFIG_KEYBOARD_XTKBD is not set
4946 +# CONFIG_KEYBOARD_NEWTON is not set
4947 +# CONFIG_KEYBOARD_STOWAWAY is not set
4948 +# CONFIG_KEYBOARD_GPIO is not set
4949 +CONFIG_KEYBOARD_NEO1973=y
4950 +CONFIG_INPUT_MOUSE=y
4951 +CONFIG_MOUSE_PS2=y
4952 +CONFIG_MOUSE_PS2_ALPS=y
4953 +CONFIG_MOUSE_PS2_LOGIPS2PP=y
4954 +CONFIG_MOUSE_PS2_SYNAPTICS=y
4955 +CONFIG_MOUSE_PS2_LIFEBOOK=y
4956 +CONFIG_MOUSE_PS2_TRACKPOINT=y
4957 +# CONFIG_MOUSE_PS2_ELANTECH is not set
4958 +# CONFIG_MOUSE_PS2_TOUCHKIT is not set
4959 +# CONFIG_MOUSE_SERIAL is not set
4960 +# CONFIG_MOUSE_APPLETOUCH is not set
4961 +# CONFIG_MOUSE_BCM5974 is not set
4962 +# CONFIG_MOUSE_VSXXXAA is not set
4963 +# CONFIG_MOUSE_GPIO is not set
4964 +# CONFIG_INPUT_JOYSTICK is not set
4965 +# CONFIG_INPUT_TABLET is not set
4966 +CONFIG_INPUT_TOUCHSCREEN=y
4967 +CONFIG_TOUCHSCREEN_FILTER=y
4968 +CONFIG_TOUCHSCREEN_FILTER_GROUP=y
4969 +CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
4970 +CONFIG_TOUCHSCREEN_FILTER_MEAN=y
4971 +# CONFIG_TOUCHSCREEN_ADS7846 is not set
4972 +# CONFIG_TOUCHSCREEN_FUJITSU is not set
4973 +# CONFIG_TOUCHSCREEN_GUNZE is not set
4974 +# CONFIG_TOUCHSCREEN_ELO is not set
4975 +# CONFIG_TOUCHSCREEN_MTOUCH is not set
4976 +# CONFIG_TOUCHSCREEN_INEXIO is not set
4977 +# CONFIG_TOUCHSCREEN_MK712 is not set
4978 +# CONFIG_TOUCHSCREEN_PENMOUNT is not set
4979 +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
4980 +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
4981 +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
4982 +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
4983 +CONFIG_INPUT_MISC=y
4984 +CONFIG_TOUCHSCREEN_PCAP7200=y
4985 +# CONFIG_INPUT_ATI_REMOTE is not set
4986 +# CONFIG_INPUT_ATI_REMOTE2 is not set
4987 +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
4988 +# CONFIG_INPUT_POWERMATE is not set
4989 +# CONFIG_INPUT_YEALINK is not set
4990 +# CONFIG_INPUT_CM109 is not set
4991 +# CONFIG_INPUT_UINPUT is not set
4992 +CONFIG_INPUT_LIS302DL=y
4993 +CONFIG_INPUT_PCF50633_PMU=y
4994 +
4995 +#
4996 +# Hardware I/O ports
4997 +#
4998 +CONFIG_SERIO=y
4999 +CONFIG_SERIO_SERPORT=y
5000 +CONFIG_SERIO_LIBPS2=y
5001 +# CONFIG_SERIO_RAW is not set
5002 +# CONFIG_GAMEPORT is not set
5003 +
5004 +#
5005 +# Character devices
5006 +#
5007 +CONFIG_VT=y
5008 +CONFIG_CONSOLE_TRANSLATIONS=y
5009 +CONFIG_VT_CONSOLE=y
5010 +CONFIG_NR_TTY_DEVICES=6
5011 +CONFIG_HW_CONSOLE=y
5012 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
5013 +CONFIG_DEVKMEM=y
5014 +# CONFIG_SERIAL_NONSTANDARD is not set
5015 +
5016 +#
5017 +# Serial drivers
5018 +#
5019 +CONFIG_SERIAL_8250=y
5020 +# CONFIG_SERIAL_8250_CONSOLE is not set
5021 +CONFIG_SERIAL_8250_NR_UARTS=4
5022 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4
5023 +# CONFIG_SERIAL_8250_EXTENDED is not set
5024 +
5025 +#
5026 +# Non-8250 serial port support
5027 +#
5028 +CONFIG_SERIAL_SAMSUNG=y
5029 +CONFIG_SERIAL_SAMSUNG_UARTS=4
5030 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
5031 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
5032 +CONFIG_SERIAL_S3C6400=y
5033 +CONFIG_SERIAL_CORE=y
5034 +CONFIG_SERIAL_CORE_CONSOLE=y
5035 +CONFIG_UNIX98_PTYS=y
5036 +CONFIG_LEGACY_PTYS=y
5037 +CONFIG_LEGACY_PTY_COUNT=256
5038 +# CONFIG_IPMI_HANDLER is not set
5039 +CONFIG_HW_RANDOM=y
5040 +# CONFIG_NVRAM is not set
5041 +# CONFIG_R3964 is not set
5042 +# CONFIG_RAW_DRIVER is not set
5043 +# CONFIG_TCG_TPM is not set
5044 +CONFIG_I2C=y
5045 +CONFIG_I2C_BOARDINFO=y
5046 +CONFIG_I2C_CHARDEV=y
5047 +CONFIG_I2C_HELPER_AUTO=y
5048 +
5049 +#
5050 +# I2C Hardware Bus support
5051 +#
5052 +
5053 +#
5054 +# I2C system bus drivers (mostly embedded / system-on-chip)
5055 +#
5056 +# CONFIG_I2C_GPIO is not set
5057 +# CONFIG_I2C_OCORES is not set
5058 +CONFIG_I2C_S3C2410=y
5059 +# CONFIG_I2C_SIMTEC is not set
5060 +
5061 +#
5062 +# External I2C/SMBus adapter drivers
5063 +#
5064 +# CONFIG_I2C_PARPORT_LIGHT is not set
5065 +# CONFIG_I2C_TAOS_EVM is not set
5066 +
5067 +#
5068 +# Other I2C/SMBus bus drivers
5069 +#
5070 +# CONFIG_I2C_PCA_PLATFORM is not set
5071 +# CONFIG_I2C_STUB is not set
5072 +
5073 +#
5074 +# Miscellaneous I2C Chip support
5075 +#
5076 +# CONFIG_DS1682 is not set
5077 +# CONFIG_AT24 is not set
5078 +# CONFIG_SENSORS_EEPROM is not set
5079 +# CONFIG_SENSORS_PCF50606 is not set
5080 +# CONFIG_SENSORS_PCF50633 is not set
5081 +# CONFIG_SENSORS_PCF8574 is not set
5082 +# CONFIG_PCF8575 is not set
5083 +# CONFIG_SENSORS_PCA9539 is not set
5084 +# CONFIG_SENSORS_PCF8591 is not set
5085 +# CONFIG_TPS65010 is not set
5086 +# CONFIG_SENSORS_MAX6875 is not set
5087 +# CONFIG_SENSORS_TSL2550 is not set
5088 +# CONFIG_SENSORS_TSL256X is not set
5089 +CONFIG_PCA9632=y
5090 +# CONFIG_I2C_DEBUG_CORE is not set
5091 +# CONFIG_I2C_DEBUG_ALGO is not set
5092 +# CONFIG_I2C_DEBUG_BUS is not set
5093 +# CONFIG_I2C_DEBUG_CHIP is not set
5094 +CONFIG_SPI=y
5095 +# CONFIG_SPI_DEBUG is not set
5096 +CONFIG_SPI_MASTER=y
5097 +
5098 +#
5099 +# SPI Master Controller Drivers
5100 +#
5101 +CONFIG_SPI_BITBANG=y
5102 +
5103 +#
5104 +# SPI Protocol Masters
5105 +#
5106 +# CONFIG_SPI_AT25 is not set
5107 +# CONFIG_SPI_SPIDEV is not set
5108 +# CONFIG_SPI_TLE62X0 is not set
5109 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
5110 +CONFIG_GPIOLIB=y
5111 +# CONFIG_DEBUG_GPIO is not set
5112 +CONFIG_GPIO_SYSFS=y
5113 +
5114 +#
5115 +# I2C GPIO expanders:
5116 +#
5117 +# CONFIG_GPIO_MAX732X is not set
5118 +# CONFIG_GPIO_PCA953X is not set
5119 +# CONFIG_GPIO_PCF857X is not set
5120 +
5121 +#
5122 +# PCI GPIO expanders:
5123 +#
5124 +
5125 +#
5126 +# SPI GPIO expanders:
5127 +#
5128 +# CONFIG_GPIO_MAX7301 is not set
5129 +# CONFIG_GPIO_MCP23S08 is not set
5130 +# CONFIG_W1 is not set
5131 +CONFIG_POWER_SUPPLY=y
5132 +# CONFIG_POWER_SUPPLY_DEBUG is not set
5133 +# CONFIG_PDA_POWER is not set
5134 +# CONFIG_APM_POWER is not set
5135 +# CONFIG_BATTERY_DS2760 is not set
5136 +# CONFIG_BATTERY_BQ27x00 is not set
5137 +# CONFIG_BATTERY_BQ27000_HDQ is not set
5138 +CONFIG_CHARGER_PCF50633=y
5139 +CONFIG_HWMON=y
5140 +# CONFIG_HWMON_VID is not set
5141 +# CONFIG_SENSORS_AD7414 is not set
5142 +# CONFIG_SENSORS_AD7418 is not set
5143 +# CONFIG_SENSORS_ADCXX is not set
5144 +# CONFIG_SENSORS_ADM1021 is not set
5145 +# CONFIG_SENSORS_ADM1025 is not set
5146 +# CONFIG_SENSORS_ADM1026 is not set
5147 +# CONFIG_SENSORS_ADM1029 is not set
5148 +# CONFIG_SENSORS_ADM1031 is not set
5149 +# CONFIG_SENSORS_ADM9240 is not set
5150 +# CONFIG_SENSORS_ADT7470 is not set
5151 +# CONFIG_SENSORS_ADT7473 is not set
5152 +# CONFIG_SENSORS_ATXP1 is not set
5153 +# CONFIG_SENSORS_DS1621 is not set
5154 +# CONFIG_SENSORS_F71805F is not set
5155 +# CONFIG_SENSORS_F71882FG is not set
5156 +# CONFIG_SENSORS_F75375S is not set
5157 +# CONFIG_SENSORS_GL518SM is not set
5158 +# CONFIG_SENSORS_GL520SM is not set
5159 +# CONFIG_SENSORS_IT87 is not set
5160 +# CONFIG_SENSORS_LM63 is not set
5161 +# CONFIG_SENSORS_LM70 is not set
5162 +# CONFIG_SENSORS_LM75 is not set
5163 +# CONFIG_SENSORS_LM77 is not set
5164 +# CONFIG_SENSORS_LM78 is not set
5165 +# CONFIG_SENSORS_LM80 is not set
5166 +# CONFIG_SENSORS_LM83 is not set
5167 +# CONFIG_SENSORS_LM85 is not set
5168 +# CONFIG_SENSORS_LM87 is not set
5169 +# CONFIG_SENSORS_LM90 is not set
5170 +# CONFIG_SENSORS_LM92 is not set
5171 +# CONFIG_SENSORS_LM93 is not set
5172 +# CONFIG_SENSORS_MAX1111 is not set
5173 +# CONFIG_SENSORS_MAX1619 is not set
5174 +# CONFIG_SENSORS_MAX6650 is not set
5175 +# CONFIG_SENSORS_PC87360 is not set
5176 +# CONFIG_SENSORS_PC87427 is not set
5177 +# CONFIG_SENSORS_DME1737 is not set
5178 +# CONFIG_SENSORS_SMSC47M1 is not set
5179 +# CONFIG_SENSORS_SMSC47M192 is not set
5180 +# CONFIG_SENSORS_SMSC47B397 is not set
5181 +# CONFIG_SENSORS_ADS7828 is not set
5182 +# CONFIG_SENSORS_THMC50 is not set
5183 +# CONFIG_SENSORS_VT1211 is not set
5184 +# CONFIG_SENSORS_W83781D is not set
5185 +# CONFIG_SENSORS_W83791D is not set
5186 +# CONFIG_SENSORS_W83792D is not set
5187 +# CONFIG_SENSORS_W83793 is not set
5188 +# CONFIG_SENSORS_W83L785TS is not set
5189 +# CONFIG_SENSORS_W83L786NG is not set
5190 +# CONFIG_SENSORS_W83627HF is not set
5191 +# CONFIG_SENSORS_W83627EHF is not set
5192 +# CONFIG_HWMON_DEBUG_CHIP is not set
5193 +# CONFIG_THERMAL is not set
5194 +# CONFIG_THERMAL_HWMON is not set
5195 +# CONFIG_WATCHDOG is not set
5196 +
5197 +#
5198 +# Sonics Silicon Backplane
5199 +#
5200 +CONFIG_SSB_POSSIBLE=y
5201 +# CONFIG_SSB is not set
5202 +
5203 +#
5204 +# Multifunction device drivers
5205 +#
5206 +# CONFIG_MFD_CORE is not set
5207 +# CONFIG_MFD_SM501 is not set
5208 +# CONFIG_MFD_ASIC3 is not set
5209 +# CONFIG_HTC_EGPIO is not set
5210 +# CONFIG_HTC_PASIC3 is not set
5211 +# CONFIG_MFD_TMIO is not set
5212 +# CONFIG_MFD_T7L66XB is not set
5213 +# CONFIG_MFD_TC6387XB is not set
5214 +# CONFIG_MFD_TC6393XB is not set
5215 +# CONFIG_PMIC_DA903X is not set
5216 +# CONFIG_MFD_WM8400 is not set
5217 +# CONFIG_MFD_WM8350_I2C is not set
5218 +CONFIG_MFD_PCF50633=y
5219 +CONFIG_PCF50633_ADC=y
5220 +CONFIG_PCF50633_GPIO=y
5221 +# CONFIG_MFD_PCF50606 is not set
5222 +# CONFIG_MFD_GLAMO is not set
5223 +
5224 +#
5225 +# Multimedia devices
5226 +#
5227 +
5228 +#
5229 +# Multimedia core support
5230 +#
5231 +# CONFIG_VIDEO_DEV is not set
5232 +# CONFIG_DVB_CORE is not set
5233 +# CONFIG_VIDEO_MEDIA is not set
5234 +
5235 +#
5236 +# Multimedia drivers
5237 +#
5238 +# CONFIG_DAB is not set
5239 +
5240 +#
5241 +# Graphics support
5242 +#
5243 +# CONFIG_VGASTATE is not set
5244 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
5245 +CONFIG_FB=y
5246 +# CONFIG_FIRMWARE_EDID is not set
5247 +# CONFIG_FB_DDC is not set
5248 +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
5249 +CONFIG_FB_CFB_FILLRECT=y
5250 +CONFIG_FB_CFB_COPYAREA=y
5251 +CONFIG_FB_CFB_IMAGEBLIT=y
5252 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
5253 +# CONFIG_FB_SYS_FILLRECT is not set
5254 +# CONFIG_FB_SYS_COPYAREA is not set
5255 +# CONFIG_FB_SYS_IMAGEBLIT is not set
5256 +# CONFIG_FB_FOREIGN_ENDIAN is not set
5257 +# CONFIG_FB_SYS_FOPS is not set
5258 +# CONFIG_FB_SVGALIB is not set
5259 +# CONFIG_FB_MACMODES is not set
5260 +# CONFIG_FB_BACKLIGHT is not set
5261 +CONFIG_FB_MODE_HELPERS=y
5262 +CONFIG_FB_TILEBLITTING=y
5263 +
5264 +#
5265 +# Frame buffer hardware drivers
5266 +#
5267 +# CONFIG_FB_S1D13XXX is not set
5268 +CONFIG_FB_S3C=y
5269 +# CONFIG_FB_S3C_DEBUG_REGWRITE is not set
5270 +# CONFIG_FB_VIRTUAL is not set
5271 +# CONFIG_FB_METRONOME is not set
5272 +# CONFIG_FB_MB862XX is not set
5273 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
5274 +CONFIG_LCD_CLASS_DEVICE=y
5275 +# CONFIG_LCD_LTV350QV is not set
5276 +# CONFIG_LCD_ILI9320 is not set
5277 +# CONFIG_LCD_TDO24M is not set
5278 +# CONFIG_LCD_VGG2432A4 is not set
5279 +CONFIG_LCD_PLATFORM=y
5280 +CONFIG_BACKLIGHT_CLASS_DEVICE=y
5281 +CONFIG_BACKLIGHT_CORGI=y
5282 +
5283 +#
5284 +# Display device support
5285 +#
5286 +# CONFIG_DISPLAY_SUPPORT is not set
5287 +# CONFIG_DISPLAY_JBT6K74 is not set
5288 +
5289 +#
5290 +# Console display driver support
5291 +#
5292 +# CONFIG_VGA_CONSOLE is not set
5293 +CONFIG_DUMMY_CONSOLE=y
5294 +CONFIG_FRAMEBUFFER_CONSOLE=y
5295 +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
5296 +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
5297 +CONFIG_FONTS=y
5298 +CONFIG_FONT_8x8=y
5299 +CONFIG_FONT_8x16=y
5300 +# CONFIG_FONT_6x11 is not set
5301 +# CONFIG_FONT_7x14 is not set
5302 +# CONFIG_FONT_PEARL_8x8 is not set
5303 +# CONFIG_FONT_ACORN_8x8 is not set
5304 +# CONFIG_FONT_MINI_4x6 is not set
5305 +# CONFIG_FONT_SUN8x16 is not set
5306 +# CONFIG_FONT_SUN12x22 is not set
5307 +# CONFIG_FONT_10x18 is not set
5308 +CONFIG_LOGO=y
5309 +CONFIG_LOGO_LINUX_MONO=y
5310 +CONFIG_LOGO_LINUX_VGA16=y
5311 +# CONFIG_LOGO_LINUX_CLUT224 is not set
5312 +CONFIG_SOUND=y
5313 +# CONFIG_SOUND_OSS_CORE is not set
5314 +CONFIG_SND=y
5315 +CONFIG_SND_TIMER=y
5316 +CONFIG_SND_PCM=y
5317 +# CONFIG_SND_SEQUENCER is not set
5318 +# CONFIG_SND_MIXER_OSS is not set
5319 +# CONFIG_SND_PCM_OSS is not set
5320 +# CONFIG_SND_DYNAMIC_MINORS is not set
5321 +CONFIG_SND_SUPPORT_OLD_API=y
5322 +CONFIG_SND_VERBOSE_PROCFS=y
5323 +# CONFIG_SND_VERBOSE_PRINTK is not set
5324 +# CONFIG_SND_DEBUG is not set
5325 +CONFIG_SND_DRIVERS=y
5326 +# CONFIG_SND_DUMMY is not set
5327 +# CONFIG_SND_MTPAV is not set
5328 +# CONFIG_SND_SERIAL_U16550 is not set
5329 +# CONFIG_SND_MPU401 is not set
5330 +CONFIG_SND_ARM=y
5331 +CONFIG_SND_SPI=y
5332 +CONFIG_SND_SOC=y
5333 +# CONFIG_SND_SOC_ALL_CODECS is not set
5334 +# CONFIG_SOUND_PRIME is not set
5335 +CONFIG_HID_SUPPORT=y
5336 +CONFIG_HID=y
5337 +CONFIG_HID_DEBUG=y
5338 +# CONFIG_HIDRAW is not set
5339 +# CONFIG_HID_PID is not set
5340 +
5341 +#
5342 +# Special HID drivers
5343 +#
5344 +# CONFIG_HID_COMPAT is not set
5345 +CONFIG_USB_SUPPORT=y
5346 +CONFIG_USB_ARCH_HAS_HCD=y
5347 +# CONFIG_USB_ARCH_HAS_OHCI is not set
5348 +# CONFIG_USB_ARCH_HAS_EHCI is not set
5349 +# CONFIG_USB is not set
5350 +
5351 +#
5352 +# Enable Host or Gadget support to see Inventra options
5353 +#
5354 +
5355 +#
5356 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
5357 +#
5358 +# CONFIG_USB_GADGET is not set
5359 +# CONFIG_AR6000_WLAN is not set
5360 +CONFIG_MMC=y
5361 +CONFIG_MMC_DEBUG=y
5362 +CONFIG_MMC_UNSAFE_RESUME=y
5363 +
5364 +#
5365 +# MMC/SD/SDIO Card Drivers
5366 +#
5367 +CONFIG_MMC_BLOCK=y
5368 +CONFIG_MMC_BLOCK_BOUNCE=y
5369 +CONFIG_SDIO_UART=y
5370 +# CONFIG_MMC_TEST is not set
5371 +
5372 +#
5373 +# MMC/SD/SDIO Host Controller Drivers
5374 +#
5375 +CONFIG_MMC_SDHCI=y
5376 +CONFIG_MMC_SDHCI_S3C=y
5377 +# CONFIG_MMC_SPI is not set
5378 +# CONFIG_MEMSTICK is not set
5379 +# CONFIG_ACCESSIBILITY is not set
5380 +CONFIG_NEW_LEDS=y
5381 +# CONFIG_LEDS_CLASS is not set
5382 +
5383 +#
5384 +# LED drivers
5385 +#
5386 +
5387 +#
5388 +# LED Triggers
5389 +#
5390 +CONFIG_LEDS_TRIGGERS=y
5391 +# CONFIG_LEDS_TRIGGER_TIMER is not set
5392 +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
5393 +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
5394 +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
5395 +CONFIG_RTC_LIB=y
5396 +CONFIG_RTC_CLASS=y
5397 +CONFIG_RTC_HCTOSYS=y
5398 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
5399 +# CONFIG_RTC_DEBUG is not set
5400 +
5401 +#
5402 +# RTC interfaces
5403 +#
5404 +CONFIG_RTC_INTF_SYSFS=y
5405 +CONFIG_RTC_INTF_PROC=y
5406 +CONFIG_RTC_INTF_DEV=y
5407 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
5408 +# CONFIG_RTC_DRV_TEST is not set
5409 +
5410 +#
5411 +# I2C RTC drivers
5412 +#
5413 +# CONFIG_RTC_DRV_DS1307 is not set
5414 +# CONFIG_RTC_DRV_DS1374 is not set
5415 +# CONFIG_RTC_DRV_DS1672 is not set
5416 +# CONFIG_RTC_DRV_MAX6900 is not set
5417 +# CONFIG_RTC_DRV_RS5C372 is not set
5418 +# CONFIG_RTC_DRV_ISL1208 is not set
5419 +# CONFIG_RTC_DRV_X1205 is not set
5420 +# CONFIG_RTC_DRV_PCF8563 is not set
5421 +# CONFIG_RTC_DRV_PCF8583 is not set
5422 +CONFIG_RTC_DRV_PCF50633=y
5423 +# CONFIG_RTC_DRV_PCF50606 is not set
5424 +# CONFIG_RTC_DRV_M41T80 is not set
5425 +# CONFIG_RTC_DRV_S35390A is not set
5426 +# CONFIG_RTC_DRV_FM3130 is not set
5427 +
5428 +#
5429 +# SPI RTC drivers
5430 +#
5431 +# CONFIG_RTC_DRV_M41T94 is not set
5432 +# CONFIG_RTC_DRV_DS1305 is not set
5433 +# CONFIG_RTC_DRV_MAX6902 is not set
5434 +# CONFIG_RTC_DRV_R9701 is not set
5435 +# CONFIG_RTC_DRV_RS5C348 is not set
5436 +# CONFIG_RTC_DRV_DS3234 is not set
5437 +
5438 +#
5439 +# Platform RTC drivers
5440 +#
5441 +# CONFIG_RTC_DRV_CMOS is not set
5442 +# CONFIG_RTC_DRV_DS1286 is not set
5443 +# CONFIG_RTC_DRV_DS1511 is not set
5444 +# CONFIG_RTC_DRV_DS1553 is not set
5445 +# CONFIG_RTC_DRV_DS1742 is not set
5446 +# CONFIG_RTC_DRV_STK17TA8 is not set
5447 +# CONFIG_RTC_DRV_M48T86 is not set
5448 +# CONFIG_RTC_DRV_M48T35 is not set
5449 +# CONFIG_RTC_DRV_M48T59 is not set
5450 +# CONFIG_RTC_DRV_BQ4802 is not set
5451 +# CONFIG_RTC_DRV_V3020 is not set
5452 +
5453 +#
5454 +# on-CPU RTC drivers
5455 +#
5456 +# CONFIG_DMADEVICES is not set
5457 +
5458 +#
5459 +# Android
5460 +#
5461 +CONFIG_ANDROID_BINDER_IPC=y
5462 +# CONFIG_ANDROID_POWER is not set
5463 +CONFIG_ANDROID_LOGGER=y
5464 +# CONFIG_ANDROID_RAM_CONSOLE is not set
5465 +# CONFIG_ANDROID_TIMED_GPIO is not set
5466 +# CONFIG_ANDROID_PARANOID_NETWORK is not set
5467 +CONFIG_REGULATOR=y
5468 +# CONFIG_REGULATOR_DEBUG is not set
5469 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
5470 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
5471 +# CONFIG_REGULATOR_BQ24022 is not set
5472 +CONFIG_REGULATOR_PCF50633=y
5473 +# CONFIG_UIO is not set
5474 +
5475 +#
5476 +# File systems
5477 +#
5478 +CONFIG_EXT2_FS=y
5479 +# CONFIG_EXT2_FS_XATTR is not set
5480 +# CONFIG_EXT2_FS_XIP is not set
5481 +CONFIG_EXT3_FS=y
5482 +CONFIG_EXT3_FS_XATTR=y
5483 +CONFIG_EXT3_FS_POSIX_ACL=y
5484 +CONFIG_EXT3_FS_SECURITY=y
5485 +# CONFIG_EXT4_FS is not set
5486 +CONFIG_JBD=y
5487 +CONFIG_FS_MBCACHE=y
5488 +# CONFIG_REISERFS_FS is not set
5489 +# CONFIG_JFS_FS is not set
5490 +CONFIG_FS_POSIX_ACL=y
5491 +CONFIG_FILE_LOCKING=y
5492 +# CONFIG_XFS_FS is not set
5493 +# CONFIG_GFS2_FS is not set
5494 +# CONFIG_OCFS2_FS is not set
5495 +CONFIG_DNOTIFY=y
5496 +CONFIG_INOTIFY=y
5497 +CONFIG_INOTIFY_USER=y
5498 +# CONFIG_QUOTA is not set
5499 +# CONFIG_AUTOFS_FS is not set
5500 +# CONFIG_AUTOFS4_FS is not set
5501 +# CONFIG_FUSE_FS is not set
5502 +CONFIG_GENERIC_ACL=y
5503 +
5504 +#
5505 +# CD-ROM/DVD Filesystems
5506 +#
5507 +# CONFIG_ISO9660_FS is not set
5508 +# CONFIG_UDF_FS is not set
5509 +
5510 +#
5511 +# DOS/FAT/NT Filesystems
5512 +#
5513 +CONFIG_FAT_FS=y
5514 +# CONFIG_MSDOS_FS is not set
5515 +CONFIG_VFAT_FS=y
5516 +CONFIG_FAT_DEFAULT_CODEPAGE=437
5517 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
5518 +# CONFIG_NTFS_FS is not set
5519 +
5520 +#
5521 +# Pseudo filesystems
5522 +#
5523 +CONFIG_PROC_FS=y
5524 +CONFIG_PROC_SYSCTL=y
5525 +CONFIG_PROC_PAGE_MONITOR=y
5526 +CONFIG_SYSFS=y
5527 +CONFIG_TMPFS=y
5528 +CONFIG_TMPFS_POSIX_ACL=y
5529 +# CONFIG_HUGETLB_PAGE is not set
5530 +# CONFIG_CONFIGFS_FS is not set
5531 +
5532 +#
5533 +# Miscellaneous filesystems
5534 +#
5535 +# CONFIG_ADFS_FS is not set
5536 +# CONFIG_AFFS_FS is not set
5537 +# CONFIG_HFS_FS is not set
5538 +# CONFIG_HFSPLUS_FS is not set
5539 +# CONFIG_BEFS_FS is not set
5540 +# CONFIG_BFS_FS is not set
5541 +# CONFIG_EFS_FS is not set
5542 +CONFIG_JFFS2_FS=y
5543 +CONFIG_JFFS2_FS_DEBUG=0
5544 +CONFIG_JFFS2_FS_WRITEBUFFER=y
5545 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
5546 +CONFIG_JFFS2_SUMMARY=y
5547 +# CONFIG_JFFS2_FS_XATTR is not set
5548 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
5549 +CONFIG_JFFS2_ZLIB=y
5550 +# CONFIG_JFFS2_LZO is not set
5551 +CONFIG_JFFS2_RTIME=y
5552 +# CONFIG_JFFS2_RUBIN is not set
5553 +CONFIG_CRAMFS=y
5554 +# CONFIG_VXFS_FS is not set
5555 +# CONFIG_MINIX_FS is not set
5556 +# CONFIG_OMFS_FS is not set
5557 +# CONFIG_HPFS_FS is not set
5558 +# CONFIG_QNX4FS_FS is not set
5559 +CONFIG_ROMFS_FS=y
5560 +# CONFIG_SYSV_FS is not set
5561 +# CONFIG_UFS_FS is not set
5562 +CONFIG_NETWORK_FILESYSTEMS=y
5563 +# CONFIG_NFS_FS is not set
5564 +# CONFIG_NFSD is not set
5565 +# CONFIG_SMB_FS is not set
5566 +# CONFIG_CIFS is not set
5567 +# CONFIG_NCP_FS is not set
5568 +# CONFIG_CODA_FS is not set
5569 +# CONFIG_AFS_FS is not set
5570 +
5571 +#
5572 +# Partition Types
5573 +#
5574 +CONFIG_PARTITION_ADVANCED=y
5575 +# CONFIG_ACORN_PARTITION is not set
5576 +# CONFIG_OSF_PARTITION is not set
5577 +# CONFIG_AMIGA_PARTITION is not set
5578 +# CONFIG_ATARI_PARTITION is not set
5579 +# CONFIG_MAC_PARTITION is not set
5580 +CONFIG_MSDOS_PARTITION=y
5581 +# CONFIG_BSD_DISKLABEL is not set
5582 +# CONFIG_MINIX_SUBPARTITION is not set
5583 +# CONFIG_SOLARIS_X86_PARTITION is not set
5584 +# CONFIG_UNIXWARE_DISKLABEL is not set
5585 +# CONFIG_LDM_PARTITION is not set
5586 +# CONFIG_SGI_PARTITION is not set
5587 +# CONFIG_ULTRIX_PARTITION is not set
5588 +# CONFIG_SUN_PARTITION is not set
5589 +# CONFIG_KARMA_PARTITION is not set
5590 +# CONFIG_EFI_PARTITION is not set
5591 +# CONFIG_SYSV68_PARTITION is not set
5592 +CONFIG_NLS=y
5593 +CONFIG_NLS_DEFAULT="iso8859-1"
5594 +CONFIG_NLS_CODEPAGE_437=y
5595 +# CONFIG_NLS_CODEPAGE_737 is not set
5596 +# CONFIG_NLS_CODEPAGE_775 is not set
5597 +# CONFIG_NLS_CODEPAGE_850 is not set
5598 +# CONFIG_NLS_CODEPAGE_852 is not set
5599 +# CONFIG_NLS_CODEPAGE_855 is not set
5600 +# CONFIG_NLS_CODEPAGE_857 is not set
5601 +# CONFIG_NLS_CODEPAGE_860 is not set
5602 +# CONFIG_NLS_CODEPAGE_861 is not set
5603 +# CONFIG_NLS_CODEPAGE_862 is not set
5604 +# CONFIG_NLS_CODEPAGE_863 is not set
5605 +# CONFIG_NLS_CODEPAGE_864 is not set
5606 +# CONFIG_NLS_CODEPAGE_865 is not set
5607 +# CONFIG_NLS_CODEPAGE_866 is not set
5608 +# CONFIG_NLS_CODEPAGE_869 is not set
5609 +# CONFIG_NLS_CODEPAGE_936 is not set
5610 +# CONFIG_NLS_CODEPAGE_950 is not set
5611 +# CONFIG_NLS_CODEPAGE_932 is not set
5612 +# CONFIG_NLS_CODEPAGE_949 is not set
5613 +# CONFIG_NLS_CODEPAGE_874 is not set
5614 +# CONFIG_NLS_ISO8859_8 is not set
5615 +# CONFIG_NLS_CODEPAGE_1250 is not set
5616 +# CONFIG_NLS_CODEPAGE_1251 is not set
5617 +# CONFIG_NLS_ASCII is not set
5618 +CONFIG_NLS_ISO8859_1=y
5619 +# CONFIG_NLS_ISO8859_2 is not set
5620 +# CONFIG_NLS_ISO8859_3 is not set
5621 +# CONFIG_NLS_ISO8859_4 is not set
5622 +# CONFIG_NLS_ISO8859_5 is not set
5623 +# CONFIG_NLS_ISO8859_6 is not set
5624 +# CONFIG_NLS_ISO8859_7 is not set
5625 +# CONFIG_NLS_ISO8859_9 is not set
5626 +# CONFIG_NLS_ISO8859_13 is not set
5627 +# CONFIG_NLS_ISO8859_14 is not set
5628 +# CONFIG_NLS_ISO8859_15 is not set
5629 +# CONFIG_NLS_KOI8_R is not set
5630 +# CONFIG_NLS_KOI8_U is not set
5631 +CONFIG_NLS_UTF8=y
5632 +# CONFIG_DLM is not set
5633 +
5634 +#
5635 +# Kernel hacking
5636 +#
5637 +CONFIG_PRINTK_TIME=y
5638 +CONFIG_ENABLE_WARN_DEPRECATED=y
5639 +CONFIG_ENABLE_MUST_CHECK=y
5640 +CONFIG_FRAME_WARN=1024
5641 +CONFIG_MAGIC_SYSRQ=y
5642 +# CONFIG_UNUSED_SYMBOLS is not set
5643 +# CONFIG_DEBUG_FS is not set
5644 +# CONFIG_HEADERS_CHECK is not set
5645 +CONFIG_DEBUG_KERNEL=y
5646 +# CONFIG_DEBUG_SHIRQ is not set
5647 +CONFIG_DETECT_SOFTLOCKUP=y
5648 +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
5649 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
5650 +CONFIG_SCHED_DEBUG=y
5651 +# CONFIG_SCHEDSTATS is not set
5652 +# CONFIG_TIMER_STATS is not set
5653 +# CONFIG_DEBUG_OBJECTS is not set
5654 +# CONFIG_SLUB_DEBUG_ON is not set
5655 +# CONFIG_SLUB_STATS is not set
5656 +CONFIG_DEBUG_RT_MUTEXES=y
5657 +CONFIG_DEBUG_PI_LIST=y
5658 +# CONFIG_RT_MUTEX_TESTER is not set
5659 +CONFIG_DEBUG_SPINLOCK=y
5660 +CONFIG_DEBUG_MUTEXES=y
5661 +# CONFIG_DEBUG_LOCK_ALLOC is not set
5662 +# CONFIG_PROVE_LOCKING is not set
5663 +# CONFIG_LOCK_STAT is not set
5664 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
5665 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
5666 +# CONFIG_DEBUG_KOBJECT is not set
5667 +CONFIG_DEBUG_BUGVERBOSE=y
5668 +CONFIG_DEBUG_INFO=y
5669 +# CONFIG_DEBUG_VM is not set
5670 +# CONFIG_DEBUG_WRITECOUNT is not set
5671 +CONFIG_DEBUG_MEMORY_INIT=y
5672 +# CONFIG_DEBUG_LIST is not set
5673 +# CONFIG_DEBUG_SG is not set
5674 +CONFIG_FRAME_POINTER=y
5675 +# CONFIG_BOOT_PRINTK_DELAY is not set
5676 +# CONFIG_RCU_TORTURE_TEST is not set
5677 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
5678 +# CONFIG_BACKTRACE_SELF_TEST is not set
5679 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
5680 +# CONFIG_FAULT_INJECTION is not set
5681 +# CONFIG_LATENCYTOP is not set
5682 +CONFIG_SYSCTL_SYSCALL_CHECK=y
5683 +CONFIG_HAVE_FUNCTION_TRACER=y
5684 +
5685 +#
5686 +# Tracers
5687 +#
5688 +# CONFIG_FUNCTION_TRACER is not set
5689 +# CONFIG_SCHED_TRACER is not set
5690 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
5691 +# CONFIG_BOOT_TRACER is not set
5692 +# CONFIG_STACK_TRACER is not set
5693 +CONFIG_DYNAMIC_PRINTK_DEBUG=y
5694 +# CONFIG_SAMPLES is not set
5695 +CONFIG_HAVE_ARCH_KGDB=y
5696 +# CONFIG_KGDB is not set
5697 +CONFIG_DEBUG_USER=y
5698 +CONFIG_DEBUG_ERRORS=y
5699 +# CONFIG_DEBUG_STACK_USAGE is not set
5700 +CONFIG_DEBUG_LL=y
5701 +# CONFIG_DEBUG_ICEDCC is not set
5702 +CONFIG_DEBUG_S3C_PORT=y
5703 +CONFIG_DEBUG_S3C_UART=3
5704 +
5705 +#
5706 +# Security options
5707 +#
5708 +# CONFIG_KEYS is not set
5709 +# CONFIG_SECURITY is not set
5710 +# CONFIG_SECURITYFS is not set
5711 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
5712 +CONFIG_CRYPTO=y
5713 +
5714 +#
5715 +# Crypto core or helper
5716 +#
5717 +# CONFIG_CRYPTO_FIPS is not set
5718 +CONFIG_CRYPTO_ALGAPI=y
5719 +CONFIG_CRYPTO_AEAD=y
5720 +CONFIG_CRYPTO_BLKCIPHER=y
5721 +CONFIG_CRYPTO_HASH=y
5722 +CONFIG_CRYPTO_RNG=y
5723 +CONFIG_CRYPTO_MANAGER=y
5724 +# CONFIG_CRYPTO_GF128MUL is not set
5725 +# CONFIG_CRYPTO_NULL is not set
5726 +# CONFIG_CRYPTO_CRYPTD is not set
5727 +# CONFIG_CRYPTO_AUTHENC is not set
5728 +# CONFIG_CRYPTO_TEST is not set
5729 +
5730 +#
5731 +# Authenticated Encryption with Associated Data
5732 +#
5733 +# CONFIG_CRYPTO_CCM is not set
5734 +# CONFIG_CRYPTO_GCM is not set
5735 +# CONFIG_CRYPTO_SEQIV is not set
5736 +
5737 +#
5738 +# Block modes
5739 +#
5740 +# CONFIG_CRYPTO_CBC is not set
5741 +# CONFIG_CRYPTO_CTR is not set
5742 +# CONFIG_CRYPTO_CTS is not set
5743 +CONFIG_CRYPTO_ECB=y
5744 +# CONFIG_CRYPTO_LRW is not set
5745 +# CONFIG_CRYPTO_PCBC is not set
5746 +# CONFIG_CRYPTO_XTS is not set
5747 +
5748 +#
5749 +# Hash modes
5750 +#
5751 +# CONFIG_CRYPTO_HMAC is not set
5752 +# CONFIG_CRYPTO_XCBC is not set
5753 +
5754 +#
5755 +# Digest
5756 +#
5757 +# CONFIG_CRYPTO_CRC32C is not set
5758 +# CONFIG_CRYPTO_MD4 is not set
5759 +CONFIG_CRYPTO_MD5=y
5760 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
5761 +# CONFIG_CRYPTO_RMD128 is not set
5762 +# CONFIG_CRYPTO_RMD160 is not set
5763 +# CONFIG_CRYPTO_RMD256 is not set
5764 +# CONFIG_CRYPTO_RMD320 is not set
5765 +CONFIG_CRYPTO_SHA1=y
5766 +# CONFIG_CRYPTO_SHA256 is not set
5767 +# CONFIG_CRYPTO_SHA512 is not set
5768 +# CONFIG_CRYPTO_TGR192 is not set
5769 +# CONFIG_CRYPTO_WP512 is not set
5770 +
5771 +#
5772 +# Ciphers
5773 +#
5774 +CONFIG_CRYPTO_AES=y
5775 +# CONFIG_CRYPTO_ANUBIS is not set
5776 +CONFIG_CRYPTO_ARC4=y
5777 +# CONFIG_CRYPTO_BLOWFISH is not set
5778 +# CONFIG_CRYPTO_CAMELLIA is not set
5779 +# CONFIG_CRYPTO_CAST5 is not set
5780 +# CONFIG_CRYPTO_CAST6 is not set
5781 +# CONFIG_CRYPTO_DES is not set
5782 +# CONFIG_CRYPTO_FCRYPT is not set
5783 +# CONFIG_CRYPTO_KHAZAD is not set
5784 +# CONFIG_CRYPTO_SALSA20 is not set
5785 +# CONFIG_CRYPTO_SEED is not set
5786 +# CONFIG_CRYPTO_SERPENT is not set
5787 +# CONFIG_CRYPTO_TEA is not set
5788 +# CONFIG_CRYPTO_TWOFISH is not set
5789 +
5790 +#
5791 +# Compression
5792 +#
5793 +# CONFIG_CRYPTO_DEFLATE is not set
5794 +# CONFIG_CRYPTO_LZO is not set
5795 +
5796 +#
5797 +# Random Number Generation
5798 +#
5799 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
5800 +CONFIG_CRYPTO_HW=y
5801 +
5802 +#
5803 +# Library routines
5804 +#
5805 +CONFIG_BITREVERSE=y
5806 +CONFIG_CRC_CCITT=y
5807 +# CONFIG_CRC16 is not set
5808 +# CONFIG_CRC_T10DIF is not set
5809 +# CONFIG_CRC_ITU_T is not set
5810 +CONFIG_CRC32=y
5811 +# CONFIG_CRC7 is not set
5812 +# CONFIG_LIBCRC32C is not set
5813 +CONFIG_ZLIB_INFLATE=y
5814 +CONFIG_ZLIB_DEFLATE=y
5815 +CONFIG_PLIST=y
5816 +CONFIG_HAS_IOMEM=y
5817 +CONFIG_HAS_DMA=y
5818 Index: linux-2.6.28/arch/arm/configs/s3c6400_defconfig
5819 ===================================================================
5820 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5821 +++ linux-2.6.28/arch/arm/configs/s3c6400_defconfig     2009-01-02 00:01:56.000000000 +0100
5822 @@ -0,0 +1,845 @@
5823 +#
5824 +# Automatically generated make config: don't edit
5825 +# Linux kernel version: 2.6.28-rc3
5826 +# Mon Nov  3 10:10:30 2008
5827 +#
5828 +CONFIG_ARM=y
5829 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
5830 +CONFIG_GENERIC_GPIO=y
5831 +# CONFIG_GENERIC_TIME is not set
5832 +# CONFIG_GENERIC_CLOCKEVENTS is not set
5833 +CONFIG_MMU=y
5834 +CONFIG_NO_IOPORT=y
5835 +CONFIG_GENERIC_HARDIRQS=y
5836 +CONFIG_STACKTRACE_SUPPORT=y
5837 +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
5838 +CONFIG_LOCKDEP_SUPPORT=y
5839 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
5840 +CONFIG_HARDIRQS_SW_RESEND=y
5841 +CONFIG_GENERIC_IRQ_PROBE=y
5842 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
5843 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
5844 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
5845 +CONFIG_GENERIC_HWEIGHT=y
5846 +CONFIG_GENERIC_CALIBRATE_DELAY=y
5847 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
5848 +CONFIG_VECTORS_BASE=0xffff0000
5849 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
5850 +
5851 +#
5852 +# General setup
5853 +#
5854 +CONFIG_EXPERIMENTAL=y
5855 +CONFIG_BROKEN_ON_SMP=y
5856 +CONFIG_INIT_ENV_ARG_LIMIT=32
5857 +CONFIG_LOCALVERSION=""
5858 +CONFIG_LOCALVERSION_AUTO=y
5859 +CONFIG_SWAP=y
5860 +# CONFIG_SYSVIPC is not set
5861 +# CONFIG_BSD_PROCESS_ACCT is not set
5862 +# CONFIG_IKCONFIG is not set
5863 +CONFIG_LOG_BUF_SHIFT=17
5864 +# CONFIG_CGROUPS is not set
5865 +# CONFIG_GROUP_SCHED is not set
5866 +CONFIG_SYSFS_DEPRECATED=y
5867 +CONFIG_SYSFS_DEPRECATED_V2=y
5868 +# CONFIG_RELAY is not set
5869 +CONFIG_NAMESPACES=y
5870 +# CONFIG_UTS_NS is not set
5871 +# CONFIG_USER_NS is not set
5872 +# CONFIG_PID_NS is not set
5873 +CONFIG_BLK_DEV_INITRD=y
5874 +CONFIG_INITRAMFS_SOURCE=""
5875 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
5876 +CONFIG_SYSCTL=y
5877 +# CONFIG_EMBEDDED is not set
5878 +CONFIG_UID16=y
5879 +CONFIG_SYSCTL_SYSCALL=y
5880 +CONFIG_KALLSYMS=y
5881 +CONFIG_KALLSYMS_ALL=y
5882 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
5883 +CONFIG_HOTPLUG=y
5884 +CONFIG_PRINTK=y
5885 +CONFIG_BUG=y
5886 +CONFIG_ELF_CORE=y
5887 +CONFIG_COMPAT_BRK=y
5888 +CONFIG_BASE_FULL=y
5889 +CONFIG_FUTEX=y
5890 +CONFIG_ANON_INODES=y
5891 +CONFIG_EPOLL=y
5892 +CONFIG_SIGNALFD=y
5893 +CONFIG_TIMERFD=y
5894 +CONFIG_EVENTFD=y
5895 +CONFIG_SHMEM=y
5896 +CONFIG_AIO=y
5897 +CONFIG_VM_EVENT_COUNTERS=y
5898 +CONFIG_SLUB_DEBUG=y
5899 +# CONFIG_SLAB is not set
5900 +CONFIG_SLUB=y
5901 +# CONFIG_SLOB is not set
5902 +# CONFIG_PROFILING is not set
5903 +# CONFIG_MARKERS is not set
5904 +CONFIG_HAVE_OPROFILE=y
5905 +# CONFIG_KPROBES is not set
5906 +CONFIG_HAVE_KPROBES=y
5907 +CONFIG_HAVE_KRETPROBES=y
5908 +CONFIG_HAVE_CLK=y
5909 +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
5910 +CONFIG_SLABINFO=y
5911 +CONFIG_RT_MUTEXES=y
5912 +# CONFIG_TINY_SHMEM is not set
5913 +CONFIG_BASE_SMALL=0
5914 +CONFIG_MODULES=y
5915 +# CONFIG_MODULE_FORCE_LOAD is not set
5916 +CONFIG_MODULE_UNLOAD=y
5917 +# CONFIG_MODULE_FORCE_UNLOAD is not set
5918 +# CONFIG_MODVERSIONS is not set
5919 +# CONFIG_MODULE_SRCVERSION_ALL is not set
5920 +CONFIG_KMOD=y
5921 +CONFIG_BLOCK=y
5922 +CONFIG_LBD=y
5923 +# CONFIG_BLK_DEV_IO_TRACE is not set
5924 +CONFIG_LSF=y
5925 +# CONFIG_BLK_DEV_BSG is not set
5926 +# CONFIG_BLK_DEV_INTEGRITY is not set
5927 +
5928 +#
5929 +# IO Schedulers
5930 +#
5931 +CONFIG_IOSCHED_NOOP=y
5932 +CONFIG_IOSCHED_AS=y
5933 +CONFIG_IOSCHED_DEADLINE=y
5934 +CONFIG_IOSCHED_CFQ=y
5935 +# CONFIG_DEFAULT_AS is not set
5936 +# CONFIG_DEFAULT_DEADLINE is not set
5937 +CONFIG_DEFAULT_CFQ=y
5938 +# CONFIG_DEFAULT_NOOP is not set
5939 +CONFIG_DEFAULT_IOSCHED="cfq"
5940 +CONFIG_CLASSIC_RCU=y
5941 +# CONFIG_FREEZER is not set
5942 +
5943 +#
5944 +# System Type
5945 +#
5946 +# CONFIG_ARCH_AAEC2000 is not set
5947 +# CONFIG_ARCH_INTEGRATOR is not set
5948 +# CONFIG_ARCH_REALVIEW is not set
5949 +# CONFIG_ARCH_VERSATILE is not set
5950 +# CONFIG_ARCH_AT91 is not set
5951 +# CONFIG_ARCH_CLPS7500 is not set
5952 +# CONFIG_ARCH_CLPS711X is not set
5953 +# CONFIG_ARCH_EBSA110 is not set
5954 +# CONFIG_ARCH_EP93XX is not set
5955 +# CONFIG_ARCH_FOOTBRIDGE is not set
5956 +# CONFIG_ARCH_NETX is not set
5957 +# CONFIG_ARCH_H720X is not set
5958 +# CONFIG_ARCH_IMX is not set
5959 +# CONFIG_ARCH_IOP13XX is not set
5960 +# CONFIG_ARCH_IOP32X is not set
5961 +# CONFIG_ARCH_IOP33X is not set
5962 +# CONFIG_ARCH_IXP23XX is not set
5963 +# CONFIG_ARCH_IXP2000 is not set
5964 +# CONFIG_ARCH_IXP4XX is not set
5965 +# CONFIG_ARCH_L7200 is not set
5966 +# CONFIG_ARCH_KIRKWOOD is not set
5967 +# CONFIG_ARCH_KS8695 is not set
5968 +# CONFIG_ARCH_NS9XXX is not set
5969 +# CONFIG_ARCH_LOKI is not set
5970 +# CONFIG_ARCH_MV78XX0 is not set
5971 +# CONFIG_ARCH_MXC is not set
5972 +# CONFIG_ARCH_ORION5X is not set
5973 +# CONFIG_ARCH_PNX4008 is not set
5974 +# CONFIG_ARCH_PXA is not set
5975 +# CONFIG_ARCH_RPC is not set
5976 +# CONFIG_ARCH_SA1100 is not set
5977 +# CONFIG_ARCH_S3C2410 is not set
5978 +CONFIG_ARCH_S3C64XX=y
5979 +# CONFIG_ARCH_SHARK is not set
5980 +# CONFIG_ARCH_LH7A40X is not set
5981 +# CONFIG_ARCH_DAVINCI is not set
5982 +# CONFIG_ARCH_OMAP is not set
5983 +# CONFIG_ARCH_MSM is not set
5984 +CONFIG_PLAT_S3C64XX=y
5985 +CONFIG_CPU_S3C6400_INIT=y
5986 +CONFIG_CPU_S3C6400_CLOCK=y
5987 +CONFIG_S3C64XX_SETUP_I2C0=y
5988 +CONFIG_S3C64XX_SETUP_I2C1=y
5989 +CONFIG_PLAT_S3C=y
5990 +
5991 +#
5992 +# Boot options
5993 +#
5994 +CONFIG_S3C_BOOT_ERROR_RESET=y
5995 +
5996 +#
5997 +# Power management
5998 +#
5999 +CONFIG_S3C_LOWLEVEL_UART_PORT=0
6000 +CONFIG_S3C_GPIO_SPACE=0
6001 +CONFIG_S3C_GPIO_TRACK=y
6002 +CONFIG_S3C_GPIO_PULL_UPDOWN=y
6003 +CONFIG_S3C_GPIO_CFG_S3C24XX=y
6004 +CONFIG_S3C_GPIO_CFG_S3C64XX=y
6005 +CONFIG_S3C_DEV_HSMMC=y
6006 +CONFIG_S3C_DEV_HSMMC1=y
6007 +CONFIG_S3C_DEV_I2C1=y
6008 +CONFIG_CPU_S3C6410=y
6009 +CONFIG_S3C6410_SETUP_SDHCI=y
6010 +CONFIG_MACH_SMDK6410=y
6011 +CONFIG_SMDK6410_SD_CH0=y
6012 +# CONFIG_SMDK6410_SD_CH1 is not set
6013 +
6014 +#
6015 +# Processor Type
6016 +#
6017 +CONFIG_CPU_32=y
6018 +CONFIG_CPU_V6=y
6019 +CONFIG_CPU_32v6K=y
6020 +CONFIG_CPU_32v6=y
6021 +CONFIG_CPU_ABRT_EV6=y
6022 +CONFIG_CPU_PABRT_NOIFAR=y
6023 +CONFIG_CPU_CACHE_V6=y
6024 +CONFIG_CPU_CACHE_VIPT=y
6025 +CONFIG_CPU_COPY_V6=y
6026 +CONFIG_CPU_TLB_V6=y
6027 +CONFIG_CPU_HAS_ASID=y
6028 +CONFIG_CPU_CP15=y
6029 +CONFIG_CPU_CP15_MMU=y
6030 +
6031 +#
6032 +# Processor Features
6033 +#
6034 +CONFIG_ARM_THUMB=y
6035 +# CONFIG_CPU_ICACHE_DISABLE is not set
6036 +# CONFIG_CPU_DCACHE_DISABLE is not set
6037 +# CONFIG_CPU_BPREDICT_DISABLE is not set
6038 +# CONFIG_OUTER_CACHE is not set
6039 +CONFIG_ARM_VIC=y
6040 +
6041 +#
6042 +# Bus support
6043 +#
6044 +# CONFIG_PCI_SYSCALL is not set
6045 +# CONFIG_ARCH_SUPPORTS_MSI is not set
6046 +# CONFIG_PCCARD is not set
6047 +
6048 +#
6049 +# Kernel Features
6050 +#
6051 +CONFIG_VMSPLIT_3G=y
6052 +# CONFIG_VMSPLIT_2G is not set
6053 +# CONFIG_VMSPLIT_1G is not set
6054 +CONFIG_PAGE_OFFSET=0xC0000000
6055 +# CONFIG_PREEMPT is not set
6056 +CONFIG_HZ=100
6057 +CONFIG_AEABI=y
6058 +CONFIG_OABI_COMPAT=y
6059 +CONFIG_ARCH_FLATMEM_HAS_HOLES=y
6060 +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
6061 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
6062 +CONFIG_SELECT_MEMORY_MODEL=y
6063 +CONFIG_FLATMEM_MANUAL=y
6064 +# CONFIG_DISCONTIGMEM_MANUAL is not set
6065 +# CONFIG_SPARSEMEM_MANUAL is not set
6066 +CONFIG_FLATMEM=y
6067 +CONFIG_FLAT_NODE_MEM_MAP=y
6068 +CONFIG_PAGEFLAGS_EXTENDED=y
6069 +CONFIG_SPLIT_PTLOCK_CPUS=4
6070 +# CONFIG_RESOURCES_64BIT is not set
6071 +# CONFIG_PHYS_ADDR_T_64BIT is not set
6072 +CONFIG_ZONE_DMA_FLAG=0
6073 +CONFIG_VIRT_TO_BUS=y
6074 +CONFIG_UNEVICTABLE_LRU=y
6075 +CONFIG_ALIGNMENT_TRAP=y
6076 +
6077 +#
6078 +# Boot options
6079 +#
6080 +CONFIG_ZBOOT_ROM_TEXT=0
6081 +CONFIG_ZBOOT_ROM_BSS=0
6082 +CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
6083 +# CONFIG_XIP_KERNEL is not set
6084 +# CONFIG_KEXEC is not set
6085 +
6086 +#
6087 +# CPU Power Management
6088 +#
6089 +# CONFIG_CPU_IDLE is not set
6090 +
6091 +#
6092 +# Floating point emulation
6093 +#
6094 +
6095 +#
6096 +# At least one emulation must be selected
6097 +#
6098 +# CONFIG_FPE_NWFPE is not set
6099 +# CONFIG_FPE_FASTFPE is not set
6100 +CONFIG_VFP=y
6101 +
6102 +#
6103 +# Userspace binary formats
6104 +#
6105 +CONFIG_BINFMT_ELF=y
6106 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
6107 +CONFIG_HAVE_AOUT=y
6108 +# CONFIG_BINFMT_AOUT is not set
6109 +# CONFIG_BINFMT_MISC is not set
6110 +
6111 +#
6112 +# Power management options
6113 +#
6114 +# CONFIG_PM is not set
6115 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
6116 +# CONFIG_NET is not set
6117 +
6118 +#
6119 +# Device Drivers
6120 +#
6121 +
6122 +#
6123 +# Generic Driver Options
6124 +#
6125 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
6126 +CONFIG_STANDALONE=y
6127 +CONFIG_PREVENT_FIRMWARE_BUILD=y
6128 +CONFIG_FW_LOADER=y
6129 +CONFIG_FIRMWARE_IN_KERNEL=y
6130 +CONFIG_EXTRA_FIRMWARE=""
6131 +# CONFIG_DEBUG_DRIVER is not set
6132 +# CONFIG_DEBUG_DEVRES is not set
6133 +# CONFIG_SYS_HYPERVISOR is not set
6134 +# CONFIG_MTD is not set
6135 +# CONFIG_PARPORT is not set
6136 +CONFIG_BLK_DEV=y
6137 +# CONFIG_BLK_DEV_COW_COMMON is not set
6138 +CONFIG_BLK_DEV_LOOP=y
6139 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
6140 +CONFIG_BLK_DEV_RAM=y
6141 +CONFIG_BLK_DEV_RAM_COUNT=16
6142 +CONFIG_BLK_DEV_RAM_SIZE=4096
6143 +# CONFIG_BLK_DEV_XIP is not set
6144 +# CONFIG_CDROM_PKTCDVD is not set
6145 +CONFIG_MISC_DEVICES=y
6146 +# CONFIG_EEPROM_93CX6 is not set
6147 +# CONFIG_ENCLOSURE_SERVICES is not set
6148 +CONFIG_HAVE_IDE=y
6149 +# CONFIG_IDE is not set
6150 +
6151 +#
6152 +# SCSI device support
6153 +#
6154 +# CONFIG_RAID_ATTRS is not set
6155 +# CONFIG_SCSI is not set
6156 +# CONFIG_SCSI_DMA is not set
6157 +# CONFIG_SCSI_NETLINK is not set
6158 +# CONFIG_ATA is not set
6159 +# CONFIG_MD is not set
6160 +
6161 +#
6162 +# Input device support
6163 +#
6164 +CONFIG_INPUT=y
6165 +# CONFIG_INPUT_FF_MEMLESS is not set
6166 +# CONFIG_INPUT_POLLDEV is not set
6167 +
6168 +#
6169 +# Userland interfaces
6170 +#
6171 +CONFIG_INPUT_MOUSEDEV=y
6172 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
6173 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
6174 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
6175 +# CONFIG_INPUT_JOYDEV is not set
6176 +# CONFIG_INPUT_EVDEV is not set
6177 +# CONFIG_INPUT_EVBUG is not set
6178 +
6179 +#
6180 +# Input Device Drivers
6181 +#
6182 +CONFIG_INPUT_KEYBOARD=y
6183 +CONFIG_KEYBOARD_ATKBD=y
6184 +# CONFIG_KEYBOARD_SUNKBD is not set
6185 +# CONFIG_KEYBOARD_LKKBD is not set
6186 +# CONFIG_KEYBOARD_XTKBD is not set
6187 +# CONFIG_KEYBOARD_NEWTON is not set
6188 +# CONFIG_KEYBOARD_STOWAWAY is not set
6189 +# CONFIG_KEYBOARD_GPIO is not set
6190 +CONFIG_INPUT_MOUSE=y
6191 +CONFIG_MOUSE_PS2=y
6192 +CONFIG_MOUSE_PS2_ALPS=y
6193 +CONFIG_MOUSE_PS2_LOGIPS2PP=y
6194 +CONFIG_MOUSE_PS2_SYNAPTICS=y
6195 +CONFIG_MOUSE_PS2_LIFEBOOK=y
6196 +CONFIG_MOUSE_PS2_TRACKPOINT=y
6197 +# CONFIG_MOUSE_PS2_ELANTECH is not set
6198 +# CONFIG_MOUSE_PS2_TOUCHKIT is not set
6199 +# CONFIG_MOUSE_SERIAL is not set
6200 +# CONFIG_MOUSE_APPLETOUCH is not set
6201 +# CONFIG_MOUSE_BCM5974 is not set
6202 +# CONFIG_MOUSE_VSXXXAA is not set
6203 +# CONFIG_MOUSE_GPIO is not set
6204 +# CONFIG_INPUT_JOYSTICK is not set
6205 +# CONFIG_INPUT_TABLET is not set
6206 +# CONFIG_INPUT_TOUCHSCREEN is not set
6207 +# CONFIG_INPUT_MISC is not set
6208 +
6209 +#
6210 +# Hardware I/O ports
6211 +#
6212 +CONFIG_SERIO=y
6213 +CONFIG_SERIO_SERPORT=y
6214 +CONFIG_SERIO_LIBPS2=y
6215 +# CONFIG_SERIO_RAW is not set
6216 +# CONFIG_GAMEPORT is not set
6217 +
6218 +#
6219 +# Character devices
6220 +#
6221 +CONFIG_VT=y
6222 +CONFIG_CONSOLE_TRANSLATIONS=y
6223 +CONFIG_VT_CONSOLE=y
6224 +CONFIG_HW_CONSOLE=y
6225 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
6226 +CONFIG_DEVKMEM=y
6227 +# CONFIG_SERIAL_NONSTANDARD is not set
6228 +
6229 +#
6230 +# Serial drivers
6231 +#
6232 +CONFIG_SERIAL_8250=y
6233 +# CONFIG_SERIAL_8250_CONSOLE is not set
6234 +CONFIG_SERIAL_8250_NR_UARTS=4
6235 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4
6236 +# CONFIG_SERIAL_8250_EXTENDED is not set
6237 +
6238 +#
6239 +# Non-8250 serial port support
6240 +#
6241 +CONFIG_SERIAL_SAMSUNG=y
6242 +CONFIG_SERIAL_SAMSUNG_UARTS=4
6243 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
6244 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y
6245 +CONFIG_SERIAL_S3C6400=y
6246 +CONFIG_SERIAL_CORE=y
6247 +CONFIG_SERIAL_CORE_CONSOLE=y
6248 +CONFIG_UNIX98_PTYS=y
6249 +CONFIG_LEGACY_PTYS=y
6250 +CONFIG_LEGACY_PTY_COUNT=256
6251 +# CONFIG_IPMI_HANDLER is not set
6252 +CONFIG_HW_RANDOM=y
6253 +# CONFIG_NVRAM is not set
6254 +# CONFIG_R3964 is not set
6255 +# CONFIG_RAW_DRIVER is not set
6256 +# CONFIG_TCG_TPM is not set
6257 +CONFIG_I2C=y
6258 +CONFIG_I2C_BOARDINFO=y
6259 +CONFIG_I2C_CHARDEV=y
6260 +CONFIG_I2C_HELPER_AUTO=y
6261 +
6262 +#
6263 +# I2C Hardware Bus support
6264 +#
6265 +
6266 +#
6267 +# I2C system bus drivers (mostly embedded / system-on-chip)
6268 +#
6269 +# CONFIG_I2C_GPIO is not set
6270 +# CONFIG_I2C_OCORES is not set
6271 +CONFIG_I2C_S3C2410=y
6272 +# CONFIG_I2C_SIMTEC is not set
6273 +
6274 +#
6275 +# External I2C/SMBus adapter drivers
6276 +#
6277 +# CONFIG_I2C_PARPORT_LIGHT is not set
6278 +# CONFIG_I2C_TAOS_EVM is not set
6279 +
6280 +#
6281 +# Other I2C/SMBus bus drivers
6282 +#
6283 +# CONFIG_I2C_PCA_PLATFORM is not set
6284 +# CONFIG_I2C_STUB is not set
6285 +
6286 +#
6287 +# Miscellaneous I2C Chip support
6288 +#
6289 +# CONFIG_DS1682 is not set
6290 +CONFIG_AT24=y
6291 +# CONFIG_SENSORS_EEPROM is not set
6292 +# CONFIG_SENSORS_PCF8574 is not set
6293 +# CONFIG_PCF8575 is not set
6294 +# CONFIG_SENSORS_PCA9539 is not set
6295 +# CONFIG_SENSORS_PCF8591 is not set
6296 +# CONFIG_TPS65010 is not set
6297 +# CONFIG_SENSORS_MAX6875 is not set
6298 +# CONFIG_SENSORS_TSL2550 is not set
6299 +# CONFIG_I2C_DEBUG_CORE is not set
6300 +# CONFIG_I2C_DEBUG_ALGO is not set
6301 +# CONFIG_I2C_DEBUG_BUS is not set
6302 +# CONFIG_I2C_DEBUG_CHIP is not set
6303 +# CONFIG_SPI is not set
6304 +CONFIG_ARCH_REQUIRE_GPIOLIB=y
6305 +CONFIG_GPIOLIB=y
6306 +# CONFIG_DEBUG_GPIO is not set
6307 +# CONFIG_GPIO_SYSFS is not set
6308 +
6309 +#
6310 +# I2C GPIO expanders:
6311 +#
6312 +# CONFIG_GPIO_MAX732X is not set
6313 +# CONFIG_GPIO_PCA953X is not set
6314 +# CONFIG_GPIO_PCF857X is not set
6315 +
6316 +#
6317 +# PCI GPIO expanders:
6318 +#
6319 +
6320 +#
6321 +# SPI GPIO expanders:
6322 +#
6323 +# CONFIG_W1 is not set
6324 +# CONFIG_POWER_SUPPLY is not set
6325 +CONFIG_HWMON=y
6326 +# CONFIG_HWMON_VID is not set
6327 +# CONFIG_SENSORS_AD7414 is not set
6328 +# CONFIG_SENSORS_AD7418 is not set
6329 +# CONFIG_SENSORS_ADM1021 is not set
6330 +# CONFIG_SENSORS_ADM1025 is not set
6331 +# CONFIG_SENSORS_ADM1026 is not set
6332 +# CONFIG_SENSORS_ADM1029 is not set
6333 +# CONFIG_SENSORS_ADM1031 is not set
6334 +# CONFIG_SENSORS_ADM9240 is not set
6335 +# CONFIG_SENSORS_ADT7470 is not set
6336 +# CONFIG_SENSORS_ADT7473 is not set
6337 +# CONFIG_SENSORS_ATXP1 is not set
6338 +# CONFIG_SENSORS_DS1621 is not set
6339 +# CONFIG_SENSORS_F71805F is not set
6340 +# CONFIG_SENSORS_F71882FG is not set
6341 +# CONFIG_SENSORS_F75375S is not set
6342 +# CONFIG_SENSORS_GL518SM is not set
6343 +# CONFIG_SENSORS_GL520SM is not set
6344 +# CONFIG_SENSORS_IT87 is not set
6345 +# CONFIG_SENSORS_LM63 is not set
6346 +# CONFIG_SENSORS_LM75 is not set
6347 +# CONFIG_SENSORS_LM77 is not set
6348 +# CONFIG_SENSORS_LM78 is not set
6349 +# CONFIG_SENSORS_LM80 is not set
6350 +# CONFIG_SENSORS_LM83 is not set
6351 +# CONFIG_SENSORS_LM85 is not set
6352 +# CONFIG_SENSORS_LM87 is not set
6353 +# CONFIG_SENSORS_LM90 is not set
6354 +# CONFIG_SENSORS_LM92 is not set
6355 +# CONFIG_SENSORS_LM93 is not set
6356 +# CONFIG_SENSORS_MAX1619 is not set
6357 +# CONFIG_SENSORS_MAX6650 is not set
6358 +# CONFIG_SENSORS_PC87360 is not set
6359 +# CONFIG_SENSORS_PC87427 is not set
6360 +# CONFIG_SENSORS_DME1737 is not set
6361 +# CONFIG_SENSORS_SMSC47M1 is not set
6362 +# CONFIG_SENSORS_SMSC47M192 is not set
6363 +# CONFIG_SENSORS_SMSC47B397 is not set
6364 +# CONFIG_SENSORS_ADS7828 is not set
6365 +# CONFIG_SENSORS_THMC50 is not set
6366 +# CONFIG_SENSORS_VT1211 is not set
6367 +# CONFIG_SENSORS_W83781D is not set
6368 +# CONFIG_SENSORS_W83791D is not set
6369 +# CONFIG_SENSORS_W83792D is not set
6370 +# CONFIG_SENSORS_W83793 is not set
6371 +# CONFIG_SENSORS_W83L785TS is not set
6372 +# CONFIG_SENSORS_W83L786NG is not set
6373 +# CONFIG_SENSORS_W83627HF is not set
6374 +# CONFIG_SENSORS_W83627EHF is not set
6375 +# CONFIG_HWMON_DEBUG_CHIP is not set
6376 +# CONFIG_THERMAL is not set
6377 +# CONFIG_THERMAL_HWMON is not set
6378 +# CONFIG_WATCHDOG is not set
6379 +
6380 +#
6381 +# Sonics Silicon Backplane
6382 +#
6383 +CONFIG_SSB_POSSIBLE=y
6384 +# CONFIG_SSB is not set
6385 +
6386 +#
6387 +# Multifunction device drivers
6388 +#
6389 +# CONFIG_MFD_CORE is not set
6390 +# CONFIG_MFD_SM501 is not set
6391 +# CONFIG_MFD_ASIC3 is not set
6392 +# CONFIG_HTC_EGPIO is not set
6393 +# CONFIG_HTC_PASIC3 is not set
6394 +# CONFIG_MFD_TMIO is not set
6395 +# CONFIG_MFD_T7L66XB is not set
6396 +# CONFIG_MFD_TC6387XB is not set
6397 +# CONFIG_MFD_TC6393XB is not set
6398 +# CONFIG_PMIC_DA903X is not set
6399 +# CONFIG_MFD_WM8400 is not set
6400 +# CONFIG_MFD_WM8350_I2C is not set
6401 +
6402 +#
6403 +# Multimedia devices
6404 +#
6405 +
6406 +#
6407 +# Multimedia core support
6408 +#
6409 +# CONFIG_VIDEO_DEV is not set
6410 +# CONFIG_VIDEO_MEDIA is not set
6411 +
6412 +#
6413 +# Multimedia drivers
6414 +#
6415 +# CONFIG_DAB is not set
6416 +
6417 +#
6418 +# Graphics support
6419 +#
6420 +# CONFIG_VGASTATE is not set
6421 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
6422 +# CONFIG_FB is not set
6423 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
6424 +
6425 +#
6426 +# Display device support
6427 +#
6428 +# CONFIG_DISPLAY_SUPPORT is not set
6429 +
6430 +#
6431 +# Console display driver support
6432 +#
6433 +# CONFIG_VGA_CONSOLE is not set
6434 +CONFIG_DUMMY_CONSOLE=y
6435 +# CONFIG_SOUND is not set
6436 +CONFIG_HID_SUPPORT=y
6437 +CONFIG_HID=y
6438 +CONFIG_HID_DEBUG=y
6439 +# CONFIG_HIDRAW is not set
6440 +# CONFIG_HID_PID is not set
6441 +
6442 +#
6443 +# Special HID drivers
6444 +#
6445 +# CONFIG_HID_COMPAT is not set
6446 +CONFIG_USB_SUPPORT=y
6447 +CONFIG_USB_ARCH_HAS_HCD=y
6448 +# CONFIG_USB_ARCH_HAS_OHCI is not set
6449 +# CONFIG_USB_ARCH_HAS_EHCI is not set
6450 +# CONFIG_USB is not set
6451 +
6452 +#
6453 +# Enable Host or Gadget support to see Inventra options
6454 +#
6455 +
6456 +#
6457 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
6458 +#
6459 +# CONFIG_USB_GADGET is not set
6460 +CONFIG_MMC=y
6461 +CONFIG_MMC_DEBUG=y
6462 +CONFIG_MMC_UNSAFE_RESUME=y
6463 +
6464 +#
6465 +# MMC/SD/SDIO Card Drivers
6466 +#
6467 +CONFIG_MMC_BLOCK=y
6468 +CONFIG_MMC_BLOCK_BOUNCE=y
6469 +CONFIG_SDIO_UART=y
6470 +# CONFIG_MMC_TEST is not set
6471 +
6472 +#
6473 +# MMC/SD/SDIO Host Controller Drivers
6474 +#
6475 +CONFIG_MMC_SDHCI=y
6476 +CONFIG_MMC_SDHCI_S3C=y
6477 +# CONFIG_MEMSTICK is not set
6478 +# CONFIG_ACCESSIBILITY is not set
6479 +# CONFIG_NEW_LEDS is not set
6480 +CONFIG_RTC_LIB=y
6481 +# CONFIG_RTC_CLASS is not set
6482 +# CONFIG_DMADEVICES is not set
6483 +
6484 +#
6485 +# Voltage and Current regulators
6486 +#
6487 +# CONFIG_REGULATOR is not set
6488 +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
6489 +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
6490 +# CONFIG_REGULATOR_BQ24022 is not set
6491 +# CONFIG_UIO is not set
6492 +
6493 +#
6494 +# File systems
6495 +#
6496 +CONFIG_EXT2_FS=y
6497 +# CONFIG_EXT2_FS_XATTR is not set
6498 +# CONFIG_EXT2_FS_XIP is not set
6499 +CONFIG_EXT3_FS=y
6500 +CONFIG_EXT3_FS_XATTR=y
6501 +CONFIG_EXT3_FS_POSIX_ACL=y
6502 +CONFIG_EXT3_FS_SECURITY=y
6503 +# CONFIG_EXT4_FS is not set
6504 +CONFIG_JBD=y
6505 +CONFIG_FS_MBCACHE=y
6506 +# CONFIG_REISERFS_FS is not set
6507 +# CONFIG_JFS_FS is not set
6508 +CONFIG_FS_POSIX_ACL=y
6509 +CONFIG_FILE_LOCKING=y
6510 +# CONFIG_XFS_FS is not set
6511 +# CONFIG_GFS2_FS is not set
6512 +CONFIG_DNOTIFY=y
6513 +CONFIG_INOTIFY=y
6514 +CONFIG_INOTIFY_USER=y
6515 +# CONFIG_QUOTA is not set
6516 +# CONFIG_AUTOFS_FS is not set
6517 +# CONFIG_AUTOFS4_FS is not set
6518 +# CONFIG_FUSE_FS is not set
6519 +CONFIG_GENERIC_ACL=y
6520 +
6521 +#
6522 +# CD-ROM/DVD Filesystems
6523 +#
6524 +# CONFIG_ISO9660_FS is not set
6525 +# CONFIG_UDF_FS is not set
6526 +
6527 +#
6528 +# DOS/FAT/NT Filesystems
6529 +#
6530 +# CONFIG_MSDOS_FS is not set
6531 +# CONFIG_VFAT_FS is not set
6532 +# CONFIG_NTFS_FS is not set
6533 +
6534 +#
6535 +# Pseudo filesystems
6536 +#
6537 +CONFIG_PROC_FS=y
6538 +CONFIG_PROC_SYSCTL=y
6539 +CONFIG_PROC_PAGE_MONITOR=y
6540 +CONFIG_SYSFS=y
6541 +CONFIG_TMPFS=y
6542 +CONFIG_TMPFS_POSIX_ACL=y
6543 +# CONFIG_HUGETLB_PAGE is not set
6544 +# CONFIG_CONFIGFS_FS is not set
6545 +
6546 +#
6547 +# Miscellaneous filesystems
6548 +#
6549 +# CONFIG_ADFS_FS is not set
6550 +# CONFIG_AFFS_FS is not set
6551 +# CONFIG_HFS_FS is not set
6552 +# CONFIG_HFSPLUS_FS is not set
6553 +# CONFIG_BEFS_FS is not set
6554 +# CONFIG_BFS_FS is not set
6555 +# CONFIG_EFS_FS is not set
6556 +CONFIG_CRAMFS=y
6557 +# CONFIG_VXFS_FS is not set
6558 +# CONFIG_MINIX_FS is not set
6559 +# CONFIG_OMFS_FS is not set
6560 +# CONFIG_HPFS_FS is not set
6561 +# CONFIG_QNX4FS_FS is not set
6562 +CONFIG_ROMFS_FS=y
6563 +# CONFIG_SYSV_FS is not set
6564 +# CONFIG_UFS_FS is not set
6565 +
6566 +#
6567 +# Partition Types
6568 +#
6569 +# CONFIG_PARTITION_ADVANCED is not set
6570 +CONFIG_MSDOS_PARTITION=y
6571 +# CONFIG_NLS is not set
6572 +
6573 +#
6574 +# Kernel hacking
6575 +#
6576 +# CONFIG_PRINTK_TIME is not set
6577 +CONFIG_ENABLE_WARN_DEPRECATED=y
6578 +CONFIG_ENABLE_MUST_CHECK=y
6579 +CONFIG_FRAME_WARN=1024
6580 +CONFIG_MAGIC_SYSRQ=y
6581 +# CONFIG_UNUSED_SYMBOLS is not set
6582 +# CONFIG_DEBUG_FS is not set
6583 +# CONFIG_HEADERS_CHECK is not set
6584 +CONFIG_DEBUG_KERNEL=y
6585 +# CONFIG_DEBUG_SHIRQ is not set
6586 +CONFIG_DETECT_SOFTLOCKUP=y
6587 +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
6588 +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
6589 +CONFIG_SCHED_DEBUG=y
6590 +# CONFIG_SCHEDSTATS is not set
6591 +# CONFIG_TIMER_STATS is not set
6592 +# CONFIG_DEBUG_OBJECTS is not set
6593 +# CONFIG_SLUB_DEBUG_ON is not set
6594 +# CONFIG_SLUB_STATS is not set
6595 +CONFIG_DEBUG_RT_MUTEXES=y
6596 +CONFIG_DEBUG_PI_LIST=y
6597 +# CONFIG_RT_MUTEX_TESTER is not set
6598 +CONFIG_DEBUG_SPINLOCK=y
6599 +CONFIG_DEBUG_MUTEXES=y
6600 +# CONFIG_DEBUG_LOCK_ALLOC is not set
6601 +# CONFIG_PROVE_LOCKING is not set
6602 +# CONFIG_LOCK_STAT is not set
6603 +CONFIG_DEBUG_SPINLOCK_SLEEP=y
6604 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
6605 +# CONFIG_DEBUG_KOBJECT is not set
6606 +CONFIG_DEBUG_BUGVERBOSE=y
6607 +CONFIG_DEBUG_INFO=y
6608 +# CONFIG_DEBUG_VM is not set
6609 +# CONFIG_DEBUG_WRITECOUNT is not set
6610 +CONFIG_DEBUG_MEMORY_INIT=y
6611 +# CONFIG_DEBUG_LIST is not set
6612 +# CONFIG_DEBUG_SG is not set
6613 +CONFIG_FRAME_POINTER=y
6614 +# CONFIG_BOOT_PRINTK_DELAY is not set
6615 +# CONFIG_RCU_TORTURE_TEST is not set
6616 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
6617 +# CONFIG_BACKTRACE_SELF_TEST is not set
6618 +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
6619 +# CONFIG_FAULT_INJECTION is not set
6620 +# CONFIG_LATENCYTOP is not set
6621 +CONFIG_SYSCTL_SYSCALL_CHECK=y
6622 +CONFIG_HAVE_FUNCTION_TRACER=y
6623 +
6624 +#
6625 +# Tracers
6626 +#
6627 +# CONFIG_FUNCTION_TRACER is not set
6628 +# CONFIG_SCHED_TRACER is not set
6629 +# CONFIG_CONTEXT_SWITCH_TRACER is not set
6630 +# CONFIG_BOOT_TRACER is not set
6631 +# CONFIG_STACK_TRACER is not set
6632 +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
6633 +# CONFIG_SAMPLES is not set
6634 +CONFIG_HAVE_ARCH_KGDB=y
6635 +# CONFIG_KGDB is not set
6636 +CONFIG_DEBUG_USER=y
6637 +CONFIG_DEBUG_ERRORS=y
6638 +# CONFIG_DEBUG_STACK_USAGE is not set
6639 +CONFIG_DEBUG_LL=y
6640 +# CONFIG_DEBUG_ICEDCC is not set
6641 +CONFIG_DEBUG_S3C_PORT=y
6642 +CONFIG_DEBUG_S3C_UART=0
6643 +
6644 +#
6645 +# Security options
6646 +#
6647 +# CONFIG_KEYS is not set
6648 +# CONFIG_SECURITY is not set
6649 +# CONFIG_SECURITYFS is not set
6650 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
6651 +# CONFIG_CRYPTO is not set
6652 +
6653 +#
6654 +# Library routines
6655 +#
6656 +CONFIG_BITREVERSE=y
6657 +# CONFIG_CRC_CCITT is not set
6658 +# CONFIG_CRC16 is not set
6659 +# CONFIG_CRC_T10DIF is not set
6660 +# CONFIG_CRC_ITU_T is not set
6661 +CONFIG_CRC32=y
6662 +# CONFIG_CRC7 is not set
6663 +# CONFIG_LIBCRC32C is not set
6664 +CONFIG_ZLIB_INFLATE=y
6665 +CONFIG_PLIST=y
6666 +CONFIG_HAS_IOMEM=y
6667 +CONFIG_HAS_DMA=y
6668 Index: linux-2.6.28/arch/arm/Kconfig
6669 ===================================================================
6670 --- linux-2.6.28.orig/arch/arm/Kconfig  2008-12-25 00:26:37.000000000 +0100
6671 +++ linux-2.6.28/arch/arm/Kconfig       2009-01-02 00:01:56.000000000 +0100
6672 @@ -498,6 +498,13 @@ config ARCH_S3C2410
6673           BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
6674           the Samsung SMDK2410 development board (and derivatives).
6675
6676 +config ARCH_S3C64XX
6677 +       bool "Samsung S3C64XX"
6678 +       select GENERIC_GPIO
6679 +       select HAVE_CLK
6680 +       help
6681 +         Samsung S3C64XX series based systems
6682 +
6683  config ARCH_SHARK
6684         bool "Shark"
6685         select ISA
6686 @@ -590,6 +597,7 @@ source "arch/arm/mach-orion5x/Kconfig"
6687  source "arch/arm/mach-kirkwood/Kconfig"
6688
6689  source "arch/arm/plat-s3c24xx/Kconfig"
6690 +source "arch/arm/plat-s3c64xx/Kconfig"
6691  source "arch/arm/plat-s3c/Kconfig"
6692
6693  if ARCH_S3C2410
6694 @@ -601,6 +609,11 @@ source "arch/arm/mach-s3c2442/Kconfig"
6695  source "arch/arm/mach-s3c2443/Kconfig"
6696  endif
6697
6698 +if ARCH_S3C64XX
6699 +source "arch/arm/mach-s3c6400/Kconfig"
6700 +source "arch/arm/mach-s3c6410/Kconfig"
6701 +endif
6702 +
6703  source "arch/arm/mach-lh7a40x/Kconfig"
6704
6705  source "arch/arm/mach-imx/Kconfig"
6706 @@ -1256,6 +1269,8 @@ source "drivers/usb/Kconfig"
6707
6708  source "drivers/uwb/Kconfig"
6709
6710 +source "drivers/ar6000/Kconfig"
6711 +
6712  source "drivers/mmc/Kconfig"
6713
6714  source "drivers/memstick/Kconfig"
6715 @@ -1268,6 +1283,8 @@ source "drivers/rtc/Kconfig"
6716
6717  source "drivers/dma/Kconfig"
6718
6719 +source "drivers/android/Kconfig"
6720 +
6721  source "drivers/dca/Kconfig"
6722
6723  source "drivers/auxdisplay/Kconfig"
6724 Index: linux-2.6.28/arch/arm/kernel/vmlinux.lds.S
6725 ===================================================================
6726 --- linux-2.6.28.orig/arch/arm/kernel/vmlinux.lds.S     2008-12-25 00:26:37.000000000 +0100
6727 +++ linux-2.6.28/arch/arm/kernel/vmlinux.lds.S  2009-01-02 00:01:56.000000000 +0100
6728 @@ -106,6 +106,8 @@ SECTIONS
6729                 *(.got)                 /* Global offset table          */
6730         }
6731
6732 +       NOTES
6733 +
6734         RODATA
6735
6736         _etext = .;                     /* End of text and rodata section */
6737 Index: linux-2.6.28/arch/arm/mach-s3c2410/clock.c
6738 ===================================================================
6739 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/clock.c     2008-12-25 00:26:37.000000000 +0100
6740 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
6741 @@ -1,276 +0,0 @@
6742 -/* linux/arch/arm/mach-s3c2410/clock.c
6743 - *
6744 - * Copyright (c) 2006 Simtec Electronics
6745 - *     Ben Dooks <ben@simtec.co.uk>
6746 - *
6747 - * S3C2410,S3C2440,S3C2442 Clock control support
6748 - *
6749 - * This program is free software; you can redistribute it and/or modify
6750 - * it under the terms of the GNU General Public License as published by
6751 - * the Free Software Foundation; either version 2 of the License, or
6752 - * (at your option) any later version.
6753 - *
6754 - * This program is distributed in the hope that it will be useful,
6755 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
6756 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6757 - * GNU General Public License for more details.
6758 - *
6759 - * You should have received a copy of the GNU General Public License
6760 - * along with this program; if not, write to the Free Software
6761 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6762 -*/
6763 -
6764 -#include <linux/init.h>
6765 -#include <linux/module.h>
6766 -#include <linux/kernel.h>
6767 -#include <linux/list.h>
6768 -#include <linux/errno.h>
6769 -#include <linux/err.h>
6770 -#include <linux/sysdev.h>
6771 -#include <linux/clk.h>
6772 -#include <linux/mutex.h>
6773 -#include <linux/delay.h>
6774 -#include <linux/serial_core.h>
6775 -#include <linux/io.h>
6776 -
6777 -#include <asm/mach/map.h>
6778 -
6779 -#include <mach/hardware.h>
6780 -
6781 -#include <plat/regs-serial.h>
6782 -#include <mach/regs-clock.h>
6783 -#include <mach/regs-gpio.h>
6784 -
6785 -#include <plat/s3c2410.h>
6786 -#include <plat/clock.h>
6787 -#include <plat/cpu.h>
6788 -
6789 -int s3c2410_clkcon_enable(struct clk *clk, int enable)
6790 -{
6791 -       unsigned int clocks = clk->ctrlbit;
6792 -       unsigned long clkcon;
6793 -
6794 -       clkcon = __raw_readl(S3C2410_CLKCON);
6795 -
6796 -       if (enable)
6797 -               clkcon |= clocks;
6798 -       else
6799 -               clkcon &= ~clocks;
6800 -
6801 -       /* ensure none of the special function bits set */
6802 -       clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
6803 -
6804 -       __raw_writel(clkcon, S3C2410_CLKCON);
6805 -
6806 -       return 0;
6807 -}
6808 -
6809 -static int s3c2410_upll_enable(struct clk *clk, int enable)
6810 -{
6811 -       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
6812 -       unsigned long orig = clkslow;
6813 -
6814 -       if (enable)
6815 -               clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
6816 -       else
6817 -               clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
6818 -
6819 -       __raw_writel(clkslow, S3C2410_CLKSLOW);
6820 -
6821 -       /* if we started the UPLL, then allow to settle */
6822 -
6823 -       if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
6824 -               udelay(200);
6825 -
6826 -       return 0;
6827 -}
6828 -
6829 -/* standard clock definitions */
6830 -
6831 -static struct clk init_clocks_disable[] = {
6832 -       {
6833 -               .name           = "nand",
6834 -               .id             = -1,
6835 -               .parent         = &clk_h,
6836 -               .enable         = s3c2410_clkcon_enable,
6837 -               .ctrlbit        = S3C2410_CLKCON_NAND,
6838 -       }, {
6839 -               .name           = "sdi",
6840 -               .id             = -1,
6841 -               .parent         = &clk_p,
6842 -               .enable         = s3c2410_clkcon_enable,
6843 -               .ctrlbit        = S3C2410_CLKCON_SDI,
6844 -       }, {
6845 -               .name           = "adc",
6846 -               .id             = -1,
6847 -               .parent         = &clk_p,
6848 -               .enable         = s3c2410_clkcon_enable,
6849 -               .ctrlbit        = S3C2410_CLKCON_ADC,
6850 -       }, {
6851 -               .name           = "i2c",
6852 -               .id             = -1,
6853 -               .parent         = &clk_p,
6854 -               .enable         = s3c2410_clkcon_enable,
6855 -               .ctrlbit        = S3C2410_CLKCON_IIC,
6856 -       }, {
6857 -               .name           = "iis",
6858 -               .id             = -1,
6859 -               .parent         = &clk_p,
6860 -               .enable         = s3c2410_clkcon_enable,
6861 -               .ctrlbit        = S3C2410_CLKCON_IIS,
6862 -       }, {
6863 -               .name           = "spi",
6864 -               .id             = -1,
6865 -               .parent         = &clk_p,
6866 -               .enable         = s3c2410_clkcon_enable,
6867 -               .ctrlbit        = S3C2410_CLKCON_SPI,
6868 -       }
6869 -};
6870 -
6871 -static struct clk init_clocks[] = {
6872 -       {
6873 -               .name           = "lcd",
6874 -               .id             = -1,
6875 -               .parent         = &clk_h,
6876 -               .enable         = s3c2410_clkcon_enable,
6877 -               .ctrlbit        = S3C2410_CLKCON_LCDC,
6878 -       }, {
6879 -               .name           = "gpio",
6880 -               .id             = -1,
6881 -               .parent         = &clk_p,
6882 -               .enable         = s3c2410_clkcon_enable,
6883 -               .ctrlbit        = S3C2410_CLKCON_GPIO,
6884 -       }, {
6885 -               .name           = "usb-host",
6886 -               .id             = -1,
6887 -               .parent         = &clk_h,
6888 -               .enable         = s3c2410_clkcon_enable,
6889 -               .ctrlbit        = S3C2410_CLKCON_USBH,
6890 -       }, {
6891 -               .name           = "usb-device",
6892 -               .id             = -1,
6893 -               .parent         = &clk_h,
6894 -               .enable         = s3c2410_clkcon_enable,
6895 -               .ctrlbit        = S3C2410_CLKCON_USBD,
6896 -       }, {
6897 -               .name           = "timers",
6898 -               .id             = -1,
6899 -               .parent         = &clk_p,
6900 -               .enable         = s3c2410_clkcon_enable,
6901 -               .ctrlbit        = S3C2410_CLKCON_PWMT,
6902 -       }, {
6903 -               .name           = "uart",
6904 -               .id             = 0,
6905 -               .parent         = &clk_p,
6906 -               .enable         = s3c2410_clkcon_enable,
6907 -               .ctrlbit        = S3C2410_CLKCON_UART0,
6908 -       }, {
6909 -               .name           = "uart",
6910 -               .id             = 1,
6911 -               .parent         = &clk_p,
6912 -               .enable         = s3c2410_clkcon_enable,
6913 -               .ctrlbit        = S3C2410_CLKCON_UART1,
6914 -       }, {
6915 -               .name           = "uart",
6916 -               .id             = 2,
6917 -               .parent         = &clk_p,
6918 -               .enable         = s3c2410_clkcon_enable,
6919 -               .ctrlbit        = S3C2410_CLKCON_UART2,
6920 -       }, {
6921 -               .name           = "rtc",
6922 -               .id             = -1,
6923 -               .parent         = &clk_p,
6924 -               .enable         = s3c2410_clkcon_enable,
6925 -               .ctrlbit        = S3C2410_CLKCON_RTC,
6926 -       }, {
6927 -               .name           = "watchdog",
6928 -               .id             = -1,
6929 -               .parent         = &clk_p,
6930 -               .ctrlbit        = 0,
6931 -       }, {
6932 -               .name           = "usb-bus-host",
6933 -               .id             = -1,
6934 -               .parent         = &clk_usb_bus,
6935 -       }, {
6936 -               .name           = "usb-bus-gadget",
6937 -               .id             = -1,
6938 -               .parent         = &clk_usb_bus,
6939 -       },
6940 -};
6941 -
6942 -/* s3c2410_baseclk_add()
6943 - *
6944 - * Add all the clocks used by the s3c2410 or compatible CPUs
6945 - * such as the S3C2440 and S3C2442.
6946 - *
6947 - * We cannot use a system device as we are needed before any
6948 - * of the init-calls that initialise the devices are actually
6949 - * done.
6950 -*/
6951 -
6952 -int __init s3c2410_baseclk_add(void)
6953 -{
6954 -       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
6955 -       unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
6956 -       struct clk *clkp;
6957 -       struct clk *xtal;
6958 -       int ret;
6959 -       int ptr;
6960 -
6961 -       clk_upll.enable = s3c2410_upll_enable;
6962 -
6963 -       if (s3c24xx_register_clock(&clk_usb_bus) < 0)
6964 -               printk(KERN_ERR "failed to register usb bus clock\n");
6965 -
6966 -       /* register clocks from clock array */
6967 -
6968 -       clkp = init_clocks;
6969 -       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
6970 -               /* ensure that we note the clock state */
6971 -
6972 -               clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
6973 -
6974 -               ret = s3c24xx_register_clock(clkp);
6975 -               if (ret < 0) {
6976 -                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
6977 -                              clkp->name, ret);
6978 -               }
6979 -       }
6980 -
6981 -       /* We must be careful disabling the clocks we are not intending to
6982 -        * be using at boot time, as subsystems such as the LCD which do
6983 -        * their own DMA requests to the bus can cause the system to lockup
6984 -        * if they where in the middle of requesting bus access.
6985 -        *
6986 -        * Disabling the LCD clock if the LCD is active is very dangerous,
6987 -        * and therefore the bootloader should be careful to not enable
6988 -        * the LCD clock if it is not needed.
6989 -       */
6990 -
6991 -       /* install (and disable) the clocks we do not need immediately */
6992 -
6993 -       clkp = init_clocks_disable;
6994 -       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
6995 -
6996 -               ret = s3c24xx_register_clock(clkp);
6997 -               if (ret < 0) {
6998 -                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
6999 -                              clkp->name, ret);
7000 -               }
7001 -
7002 -               s3c2410_clkcon_enable(clkp, 0);
7003 -       }
7004 -
7005 -       /* show the clock-slow value */
7006 -
7007 -       xtal = clk_get(NULL, "xtal");
7008 -
7009 -       printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
7010 -              print_mhz(clk_get_rate(xtal) /
7011 -                        ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
7012 -              (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
7013 -              (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
7014 -              (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
7015 -
7016 -       return 0;
7017 -}
7018 Index: linux-2.6.28/arch/arm/mach-s3c2410/dma.c
7019 ===================================================================
7020 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/dma.c       2008-12-25 00:26:37.000000000 +0100
7021 +++ linux-2.6.28/arch/arm/mach-s3c2410/dma.c    2009-01-02 00:01:56.000000000 +0100
7022 @@ -25,12 +25,12 @@
7023
7024  #include <plat/regs-serial.h>
7025  #include <mach/regs-gpio.h>
7026 -#include <asm/plat-s3c/regs-ac97.h>
7027 +#include <plat/regs-ac97.h>
7028  #include <mach/regs-mem.h>
7029  #include <mach/regs-lcd.h>
7030  #include <mach/regs-sdi.h>
7031  #include <asm/plat-s3c24xx/regs-iis.h>
7032 -#include <asm/plat-s3c24xx/regs-spi.h>
7033 +#include <plat/regs-spi.h>
7034
7035  static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
7036         [DMACH_XD0] = {
7037 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/fiq_ipc_gta02.h
7038 ===================================================================
7039 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7040 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/fiq_ipc_gta02.h     2009-01-02 00:01:56.000000000 +0100
7041 @@ -0,0 +1,60 @@
7042 +#ifndef _LINUX_FIQ_IPC_H
7043 +#define _LINUX_FIQ_IPC_H
7044 +
7045 +/*
7046 + * this defines the struct which is used to communicate between the FIQ
7047 + * world and the normal linux kernel world.  One of these structs is
7048 + * statically defined for you in the monolithic kernel so the FIQ ISR code
7049 + * can safely touch it any any time.
7050 + *
7051 + * You also want to include this file in your kernel module that wants to
7052 + * communicate with your FIQ code.  Add any kinds of vars that are used by
7053 + * the FIQ ISR and the module in here.
7054 + *
7055 + * To get you started there is just an int that is incremented every FIQ
7056 + * you can remove this when you are ready to customize, but it is useful
7057 + * for testing
7058 + */
7059 +
7060 +#include <mach/pwm.h>
7061 +#include <plat/regs-timer.h>
7062 +
7063 +extern u8 fiq_ready;
7064 +
7065 +enum hdq_bitbang_states {
7066 +       HDQB_IDLE = 0,
7067 +       HDQB_TX_BREAK,
7068 +       HDQB_TX_BREAK_RECOVERY,
7069 +       HDQB_ADS_CALC,
7070 +       HDQB_ADS_LOW,
7071 +       HDQB_ADS_HIGH,
7072 +       HDQB_WAIT_RX,
7073 +       HDQB_DATA_RX_LOW,
7074 +       HDQB_DATA_RX_HIGH,
7075 +       HDQB_WAIT_TX,
7076 +};
7077 +
7078 +struct fiq_ipc {
7079 +       /* vibrator */
7080 +       unsigned long vib_gpio_pin; /* which pin to meddle with */
7081 +       u8 vib_pwm; /* 0 = OFF -- will ensure GPIO deasserted and stop FIQ */
7082 +       u8 vib_pwm_latched;
7083 +
7084 +       /* hdq */
7085 +       u8 hdq_probed; /* nonzero after HDQ driver probed */
7086 +       struct mutex hdq_lock; /* if you want to use hdq, you have to take lock */
7087 +       unsigned long hdq_gpio_pin; /* GTA02 = GPD14 which pin to meddle with */
7088 +       u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */
7089 +       u8 hdq_tx_data; /* data to tx for write action */
7090 +       u8 hdq_rx_data; /* data received in read action */
7091 +       u8 hdq_request_ctr; /* incremented by "user" to request a transfer */
7092 +       u8 hdq_transaction_ctr; /* incremented after each transfer */
7093 +       u8 hdq_error; /* 0 = no error */
7094 +};
7095 +
7096 +/* actual definition lives in arch/arm/mach-s3c2440/fiq_c_isr.c */
7097 +extern struct fiq_ipc fiq_ipc;
7098 +extern unsigned long _fiq_count_fiqs;
7099 +extern void fiq_kick(void);  /* provoke a FIQ "immediately" */
7100 +
7101 +#endif /* _LINUX_FIQ_IPC_H */
7102 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio-core.h
7103 ===================================================================
7104 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7105 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio-core.h 2009-01-02 00:01:56.000000000 +0100
7106 @@ -0,0 +1,21 @@
7107 +/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
7108 + *
7109 + * Copyright 2008 Openmoko, Inc.
7110 + * Copyright 2008 Simtec Electronics
7111 + *      Ben Dooks <ben@simtec.co.uk>
7112 + *      http://armlinux.simtec.co.uk/
7113 + *
7114 + * S3C2410 - GPIO core support
7115 + *
7116 + * This program is free software; you can redistribute it and/or modify
7117 + * it under the terms of the GNU General Public License version 2 as
7118 + * published by the Free Software Foundation.
7119 +*/
7120 +
7121 +#ifndef __ASM_ARCH_GPIO_CORE_H
7122 +#define __ASM_ARCH_GPIO_CORE_H __FILE__
7123 +
7124 +/* currently we just include the platform support */
7125 +#include <plat/gpio-core.h>
7126 +
7127 +#endif /* __ASM_ARCH_GPIO_CORE_H */
7128 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio.h
7129 ===================================================================
7130 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/gpio.h 2008-12-25 00:26:37.000000000 +0100
7131 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio.h      2009-01-02 00:01:56.000000000 +0100
7132 @@ -15,4 +15,14 @@
7133  #define gpio_set_value __gpio_set_value
7134  #define gpio_cansleep  __gpio_cansleep
7135
7136 +/* These two defines should be removed as soon as the
7137 + * generic irq handling makes it upstream */
7138 +#include <mach/hardware.h>
7139 +#define gpio_to_irq(gpio)               s3c2410_gpio_getirq(gpio)
7140 +#define irq_to_gpio(irq)                s3c2410_gpio_irq2pin(irq)
7141 +/* -- cut to here when generic irq makes it */
7142 +
7143  #include <asm-generic/gpio.h>
7144 +#include <mach/gpio-nrs.h>
7145 +
7146 +#define S3C_GPIO_END   (S3C2410_GPIO_BANKH + 32)
7147 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
7148 ===================================================================
7149 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7150 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h  2009-01-02 00:01:56.000000000 +0100
7151 @@ -0,0 +1,23 @@
7152 +/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
7153 + *
7154 + * Copyright (c) 2008 Simtec Electronics
7155 + *     http://armlinux.simtec.co.uk/
7156 + *     Ben Dooks <ben@simtec.co.uk>
7157 + *
7158 + * S3C2410 - GPIO bank numbering
7159 + *
7160 + * This program is free software; you can redistribute it and/or modify
7161 + * it under the terms of the GNU General Public License version 2 as
7162 + * published by the Free Software Foundation.
7163 +*/
7164 +
7165 +#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
7166 +
7167 +#define S3C2410_GPIO_BANKA   (32*0)
7168 +#define S3C2410_GPIO_BANKB   (32*1)
7169 +#define S3C2410_GPIO_BANKC   (32*2)
7170 +#define S3C2410_GPIO_BANKD   (32*3)
7171 +#define S3C2410_GPIO_BANKE   (32*4)
7172 +#define S3C2410_GPIO_BANKF   (32*5)
7173 +#define S3C2410_GPIO_BANKG   (32*6)
7174 +#define S3C2410_GPIO_BANKH   (32*7)
7175 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gta01.h
7176 ===================================================================
7177 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7178 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gta01.h     2009-01-02 00:01:56.000000000 +0100
7179 @@ -0,0 +1,74 @@
7180 +#ifndef _GTA01_H
7181 +#define _GTA01_H
7182 +
7183 +#include <mach/regs-gpio.h>
7184 +#include <mach/irqs.h>
7185 +
7186 +/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
7187 +#define GTA01v3_SYSTEM_REV     0x00000130
7188 +#define GTA01v4_SYSTEM_REV     0x00000140
7189 +#define GTA01Bv2_SYSTEM_REV    0x00000220
7190 +#define GTA01Bv3_SYSTEM_REV    0x00000230
7191 +#define GTA01Bv4_SYSTEM_REV    0x00000240
7192 +
7193 +/* Backlight */
7194 +
7195 +extern void gta01bl_deferred_resume(void);
7196 +
7197 +struct gta01bl_machinfo {
7198 +       unsigned int default_intensity;
7199 +       unsigned int max_intensity;
7200 +       unsigned int limit_mask;
7201 +       unsigned int defer_resume_backlight;
7202 +};
7203 +
7204 +/* Definitions common to all revisions */
7205 +#define GTA01_GPIO_BACKLIGHT   S3C2410_GPB0
7206 +#define GTA01_GPIO_GPS_PWRON   S3C2410_GPB1
7207 +#define GTA01_GPIO_MODEM_RST   S3C2410_GPB6
7208 +#define GTA01_GPIO_MODEM_ON    S3C2410_GPB7
7209 +#define GTA01_GPIO_LCD_RESET   S3C2410_GPC6
7210 +#define GTA01_GPIO_PMU_IRQ     S3C2410_GPG8
7211 +#define GTA01_GPIO_JACK_INSERT S3C2410_GPF4
7212 +#define GTA01_GPIO_nSD_DETECT  S3C2410_GPF5
7213 +#define GTA01_GPIO_AUX_KEY     S3C2410_GPF6
7214 +#define GTA01_GPIO_HOLD_KEY    S3C2410_GPF7
7215 +#define GTA01_GPIO_VIBRATOR_ON S3C2410_GPG11
7216 +
7217 +#define GTA01_IRQ_MODEM                IRQ_EINT1
7218 +#define GTA01_IRQ_JACK_INSERT  IRQ_EINT4
7219 +#define GTA01_IRQ_nSD_DETECT   IRQ_EINT5
7220 +#define GTA01_IRQ_AUX_KEY      IRQ_EINT6
7221 +#define GTA01_IRQ_PCF50606      IRQ_EINT16
7222 +
7223 +/* GTA01v3 */
7224 +#define GTA01v3_GPIO_nGSM_EN   S3C2410_GPG9
7225 +
7226 +/* GTA01v4 */
7227 +#define GTA01_GPIO_MODEM_DNLOAD        S3C2410_GPG0
7228 +
7229 +/* GTA01Bv2 */
7230 +#define GTA01Bv2_GPIO_nGSM_EN  S3C2410_GPF2
7231 +#define GTA01Bv2_GPIO_VIBRATOR_ON S3C2410_GPB10
7232 +
7233 +/* GTA01Bv3 */
7234 +#define GTA01_GPIO_GPS_EN_3V3  S3C2410_GPG9
7235 +
7236 +#define GTA01_GPIO_SDMMC_ON    S3C2410_GPB2
7237 +#define GTA01_GPIO_BT_EN       S3C2410_GPB5
7238 +#define GTA01_GPIO_AB_DETECT   S3C2410_GPB8
7239 +#define GTA01_GPIO_USB_PULLUP  S3C2410_GPB9
7240 +#define GTA01_GPIO_USB_ATTACH  S3C2410_GPB10
7241 +
7242 +#define GTA01_GPIO_GPS_EN_2V8  S3C2410_GPG9
7243 +#define GTA01_GPIO_GPS_EN_3V   S3C2410_GPG10
7244 +#define GTA01_GPIO_GPS_RESET   S3C2410_GPC0
7245 +
7246 +/* GTA01Bv4 */
7247 +#define GTA01Bv4_GPIO_nNAND_WP S3C2410_GPA16
7248 +#define GTA01Bv4_GPIO_VIBRATOR_ON S3C2410_GPB3
7249 +#define GTA01Bv4_GPIO_PMU_IRQ  S3C2410_GPG1
7250 +
7251 +#define GTA01Bv4_IRQ_PCF50606  IRQ_EINT9
7252 +
7253 +#endif /* _GTA01_H */
7254 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gta02.h
7255 ===================================================================
7256 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7257 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gta02.h     2009-01-02 00:01:56.000000000 +0100
7258 @@ -0,0 +1,113 @@
7259 +#ifndef _GTA02_H
7260 +#define _GTA02_H
7261 +
7262 +#include <mach/regs-gpio.h>
7263 +#include <mach/irqs.h>
7264 +
7265 +#include <linux/mfd/pcf50633/core.h>
7266 +
7267 +/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
7268 +#define GTA02v1_SYSTEM_REV     0x00000310
7269 +#define GTA02v2_SYSTEM_REV     0x00000320
7270 +#define GTA02v3_SYSTEM_REV     0x00000330
7271 +#define GTA02v4_SYSTEM_REV     0x00000340
7272 +#define GTA02v5_SYSTEM_REV     0x00000350
7273 +#define GTA02v6_SYSTEM_REV     0x00000360
7274 +
7275 +#define GTA02_GPIO_n3DL_GSM    S3C2410_GPA13   /* v1 + v2 + v3 only */
7276 +
7277 +#define GTA02_GPIO_PWR_LED1    S3C2410_GPB0
7278 +#define GTA02_GPIO_PWR_LED2    S3C2410_GPB1
7279 +#define GTA02_GPIO_AUX_LED     S3C2410_GPB2
7280 +#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB3
7281 +#define GTA02v1_GPIO_GPS_PWRON S3C2410_GPB4    /* v1 only */
7282 +#define GTA02_GPIO_MODEM_RST   S3C2410_GPB5
7283 +#define GTA02_GPIO_BT_EN       S3C2410_GPB6
7284 +#define GTA02_GPIO_MODEM_ON    S3C2410_GPB7
7285 +#define GTA02v1_GPIO_EN_AGPS3V S3C2410_GPB8    /* v1 only */
7286 +#define GTA02_GPIO_EXTINT8     S3C2410_GPB8
7287 +#define GTA02_GPIO_USB_PULLUP  S3C2410_GPB9
7288 +
7289 +#define GTA02v1_GPIO_nGPS_RST  S3C2410_GPC0    /* v1 only */
7290 +#define GTA02v12_GPIO_PIO3     S3C2410_GPC5    /* v1 + v2 only */
7291 +#define GTA02_GPIO_PIO5                S3C2410_GPC5    /* v3 + v4 only */
7292 +#define GTA02_GPIO_LCD_RESET   S3C2410_GPC6    /* v1 + v2 only */
7293 +#define GTA02v12_GPIO_PIO2     S3C2410_GPC7    /* v1 + v2 only */
7294 +#define GTA02v2_nUSB_FLT       S3C2410_GPC9    /* v2 only */
7295 +#define GTA02v2_nUSB_OC                S3C2410_GPC10   /* v2 only */
7296 +#define GTA02v2_nGSM_OC                S3C2410_GPC12   /* v2 only */
7297 +
7298 +#define GTA02v3_GPIO_nG1_CS    S3C2410_GPD12   /* v3 + v4 only */
7299 +#define GTA02v3_GPIO_nG2_CS    S3C2410_GPD13   /* v3 + v4 only */
7300 +#define GTA02v5_GPIO_HDQ       S3C2410_GPD14   /* v5 + */
7301 +
7302 +#define GTA02_GPIO_nG1_INT     S3C2410_GPF0
7303 +#define GTA02_GPIO_IO1         S3C2410_GPF1
7304 +#define GTA02v1_GPIO_nG2_INT   S3C2410_GPF2    /* v1 only */
7305 +#define GTA02_GPIO_PIO_2       S3C2410_GPF2    /* v2 + v3 + v4 only */
7306 +#define GTA02_GPIO_JACK_INSERT S3C2410_GPF4
7307 +#define GTA02v1_GPIO_nSD_DETECT        S3C2410_GPF5    /* v1 only */
7308 +#define GTA02_GPIO_WLAN_GPIO1  S3C2410_GPF5    /* v2 + v3 + v4 only */
7309 +#define GTA02_GPIO_AUX_KEY     S3C2410_GPF6
7310 +#define GTA02_GPIO_HOLD_KEY    S3C2410_GPF7
7311 +
7312 +#define GTA02_GPIO_3D_IRQ      S3C2410_GPG4
7313 +#define GTA02v1_GPIO_nG1_CS    S3C2410_GPG8    /* v1 only */
7314 +#define GTA02v2_GPIO_nG2_INT   S3C2410_GPG8    /* v2 + v3 + v4 only */
7315 +#define GTA02v3_GPIO_nUSB_OC   S3C2410_GPG9    /* v3 + v4 only */
7316 +#define GTA02v3_GPIO_nUSB_FLT  S3C2410_GPG10   /* v3 + v4 only */
7317 +#define GTA02v1_GPIO_nG2_CS    S3C2410_GPG11   /* v1 only */
7318 +#define GTA02v3_GPIO_nGSM_OC   S3C2410_GPG11   /* v3 + v4 only */
7319 +
7320 +#define GTA02v1_GPIO_3D_RESET  S3C2440_GPJ0    /* v1 only */
7321 +#define GTA02v2_GPIO_BAT_ID    S3C2440_GPJ0    /* v2 only */
7322 +#define GTA02v1_GPIO_WLAN_GPIO8        S3C2440_GPJ1    /* v1 only */
7323 +#define GTA02_GPIO_AMP_SHUT    S3C2440_GPJ1    /* v2 + v3 + v4 only */
7324 +#define GTA02v1_GPIO_WLAN_GPIO10       S3C2440_GPJ2
7325 +#define GTA02_GPIO_HP_IN       S3C2440_GPJ2    /* v2 + v3 + v4 only */
7326 +#define GTA02v1_GPIO_KEEPACT   S3C2440_GPJ3    /* v1 only */
7327 +#define GTA02_GPIO_INT0                S3C2440_GPJ3    /* v2 + v3 + v4 only */
7328 +#define GTA02_GPIO_nGSM_EN     S3C2440_GPJ4
7329 +#define GTA02_GPIO_3D_RESET    S3C2440_GPJ5
7330 +#define GTA02_GPIO_nDL_GSM     S3C2440_GPJ6    /* v4 + v5 only */
7331 +#define GTA02_GPIO_WLAN_GPIO0  S3C2440_GPJ7
7332 +#define GTA02v1_GPIO_BAT_ID    S3C2440_GPJ8
7333 +#define GTA02_GPIO_KEEPACT     S3C2440_GPJ8
7334 +#define GTA02v1_GPIO_AMP_SHUT  S3C2440_GPJ9    /* v1 only */
7335 +#define GTA02v2_nG1_CS         S3C2440_GPJ9    /* v2 only */
7336 +#define GTA02v1_GPIO_HP_IN     S3C2440_GPJ10
7337 +#define GTA02v2_nG2_CS         S3C2440_GPJ10   /* v2 only */
7338 +#define GTA02v1_GPIO_INT0      S3C2440_GPJ11   /* v1 only */
7339 +#define GTA02_CHIP_PWD         S3C2440_GPJ11   /* v2 + v3 + v4 only */
7340 +#define GTA02v1_GPIO_nGSM_EN   S3C2440_GPJ12   /* v1 only */
7341 +#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12   /* v2 + v3 + v4 only */
7342 +
7343 +#define GTA02_IRQ_GSENSOR_1    IRQ_EINT0
7344 +#define GTA02_IRQ_MODEM                IRQ_EINT1
7345 +#define GTA02v1_IRQ_GSENSOR_2  IRQ_EINT2       /* v1 only */
7346 +#define GTA02_IRQ_PIO_2                IRQ_EINT2       /* v2 + v3 + v4 only */
7347 +#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4
7348 +#define GTA02v1_IRQ_nSD_CD     IRQ_EINT5       /* v1 only */
7349 +#define GTA02_IRQ_WLAN_GPIO1   IRQ_EINT5
7350 +#define GTA02_IRQ_AUX          IRQ_EINT6
7351 +#define GTA02_IRQ_nHOLD                IRQ_EINT7
7352 +#define GTA02v1_IRQ_nSIM_CD    IRQ_EINT8       /* v1 only */
7353 +#define GTA02_IRQ_PCF50633     IRQ_EINT9
7354 +#define GTA02_IRQ_3D           IRQ_EINT12
7355 +#define GTA02_IRQ_GSENSOR_2    IRQ_EINT16      /* v2 + v3 + v4 only */
7356 +#define GTA02v3_IRQ_nUSB_OC    IRQ_EINT17      /* v3 + v4 only */
7357 +#define GTA02v3_IRQ_nUSB_FLT   IRQ_EINT18      /* v3 + v4 only */
7358 +#define GTA02v3_IRQ_nGSM_OC    IRQ_EINT19      /* v3 + v4 only */
7359 +
7360 +/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
7361 +#define GTA02_PCB_ID1_0                S3C2410_GPC13
7362 +#define GTA02_PCB_ID1_1                S3C2410_GPC15
7363 +#define GTA02_PCB_ID1_2                S3C2410_GPD0
7364 +#define GTA02_PCB_ID2_0                S3C2410_GPD3
7365 +#define GTA02_PCB_ID2_1                S3C2410_GPD4
7366 +
7367 +int gta02_get_pcb_revision(void);
7368 +
7369 +extern struct pcf50633_platform_data gta02_pcf_pdata;
7370 +
7371 +#endif /* _GTA02_H */
7372 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gta02-pm-wlan.h
7373 ===================================================================
7374 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7375 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gta02-pm-wlan.h     2009-01-02 00:01:56.000000000 +0100
7376 @@ -0,0 +1 @@
7377 +void gta02_wlan_power(int on);
7378 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/irqs.h
7379 ===================================================================
7380 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/irqs.h 2008-12-25 00:26:37.000000000 +0100
7381 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/irqs.h      2009-01-02 00:01:56.000000000 +0100
7382 @@ -12,9 +12,9 @@
7383  #ifndef __ASM_ARCH_IRQS_H
7384  #define __ASM_ARCH_IRQS_H __FILE__
7385
7386 -#ifndef __ASM_ARM_IRQ_H
7387 -#error "Do not include this directly, instead #include <asm/irq.h>"
7388 -#endif
7389 +//#ifndef __ASM_ARM_IRQ_H
7390 +//#error "Do not include this directly, instead #include <asm/irq.h>"
7391 +//#endif
7392
7393  /* we keep the first set of CPU IRQs out of the range of
7394   * the ISA space, so that the PC104 has them to itself
7395 @@ -84,7 +84,7 @@
7396  #define IRQ_EINT22     S3C2410_IRQ(50)
7397  #define IRQ_EINT23     S3C2410_IRQ(51)
7398
7399 -
7400 +#define IRQ_EINT_BIT(x)        ((x) - IRQ_EINT4 + 4)
7401  #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
7402
7403  #define IRQ_LCD_FIFO   S3C2410_IRQ(52)
7404 @@ -134,6 +134,8 @@
7405  #define IRQ_S3C2443_HSMMC      S3C2410_IRQ(20)         /* IRQ_SDI */
7406  #define IRQ_S3C2443_NAND       S3C2410_IRQ(24)         /* reserved */
7407
7408 +#define IRQ_HSMMC0             IRQ_S3C2443_HSMMC
7409 +
7410  #define IRQ_S3C2443_LCD1       S3C2410_IRQSUB(14)
7411  #define IRQ_S3C2443_LCD2       S3C2410_IRQSUB(15)
7412  #define IRQ_S3C2443_LCD3       S3C2410_IRQSUB(16)
7413 @@ -155,12 +157,47 @@
7414  #define IRQ_S3C2443_AC97       S3C2410_IRQSUB(28)
7415
7416  #ifdef CONFIG_CPU_S3C2443
7417 -#define NR_IRQS (IRQ_S3C2443_AC97+1)
7418 +#define _NR_IRQS (IRQ_S3C2443_AC97+1)
7419  #else
7420 -#define NR_IRQS (IRQ_S3C2440_AC97+1)
7421 +#define _NR_IRQS (IRQ_S3C2440_AC97+1)
7422  #endif
7423
7424 +/* compatibility define. */
7425 +#define IRQ_UART3              IRQ_S3C2443_UART3
7426 +#define IRQ_S3CUART_RX3                IRQ_S3C2443_RX3
7427 +#define IRQ_S3CUART_TX3                IRQ_S3C2443_TX3
7428 +#define IRQ_S3CUART_ERR3       IRQ_S3C2443_ERR3
7429 +
7430  /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
7431  #define FIQ_START              IRQ_EINT0
7432
7433 +
7434 +/*
7435 + * The next 16 interrupts are for board specific purposes.  Since
7436 + * the kernel can only run on one machine at a time, we can re-use
7437 + * these.  If you need more, increase IRQ_BOARD_END, but keep it
7438 + * within sensible limits.
7439 + */
7440 +#define IRQ_BOARD_START         _NR_IRQS
7441 +#define IRQ_BOARD_END           (_NR_IRQS + 10)
7442 +
7443 +#if defined(CONFIG_MACH_NEO1973_GTA02)
7444 +#define NR_IRQS                 (IRQ_BOARD_END)
7445 +#else
7446 +#define NR_IRQS                 (IRQ_BOARD_START)
7447 +#endif
7448 +
7449 +/* Neo1973 GTA02 interrupts */
7450 +#define NEO1973_GTA02_IRQ(x)    (IRQ_BOARD_START + (x))
7451 +#define IRQ_GLAMO(x)            NEO1973_GTA02_IRQ(x)
7452 +#define IRQ_GLAMO_HOSTBUS       IRQ_GLAMO(0)
7453 +#define IRQ_GLAMO_JPEG          IRQ_GLAMO(1)
7454 +#define IRQ_GLAMO_MPEG          IRQ_GLAMO(2)
7455 +#define IRQ_GLAMO_MPROC1        IRQ_GLAMO(3)
7456 +#define IRQ_GLAMO_MPROC0        IRQ_GLAMO(4)
7457 +#define IRQ_GLAMO_CMDQUEUE      IRQ_GLAMO(5)
7458 +#define IRQ_GLAMO_2D            IRQ_GLAMO(6)
7459 +#define IRQ_GLAMO_MMC           IRQ_GLAMO(7)
7460 +#define IRQ_GLAMO_RISC          IRQ_GLAMO(8)
7461 +
7462  #endif /* __ASM_ARCH_IRQ_H */
7463 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/map.h
7464 ===================================================================
7465 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/map.h  2008-12-25 00:26:37.000000000 +0100
7466 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/map.h       2009-01-02 00:01:56.000000000 +0100
7467 @@ -13,34 +13,20 @@
7468  #ifndef __ASM_ARCH_MAP_H
7469  #define __ASM_ARCH_MAP_H
7470
7471 +#include <plat/map-base.h>
7472  #include <plat/map.h>
7473
7474  #define S3C2410_ADDR(x)                S3C_ADDR(x)
7475
7476 -/* interrupt controller is the first thing we put in, to make
7477 - * the assembly code for the irq detection easier
7478 - */
7479 -#define S3C24XX_VA_IRQ    S3C_VA_IRQ
7480 -#define S3C2410_PA_IRQ    (0x4A000000)
7481 -#define S3C24XX_SZ_IRQ    SZ_1M
7482 -
7483 -/* memory controller registers */
7484 -#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
7485 -#define S3C2410_PA_MEMCTRL (0x48000000)
7486 -#define S3C24XX_SZ_MEMCTRL SZ_1M
7487 -
7488  /* USB host controller */
7489  #define S3C2410_PA_USBHOST (0x49000000)
7490 -#define S3C24XX_SZ_USBHOST SZ_1M
7491
7492  /* DMA controller */
7493  #define S3C2410_PA_DMA    (0x4B000000)
7494  #define S3C24XX_SZ_DMA    SZ_1M
7495
7496  /* Clock and Power management */
7497 -#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
7498  #define S3C2410_PA_CLKPWR  (0x4C000000)
7499 -#define S3C24XX_SZ_CLKPWR  SZ_1M
7500
7501  /* LCD controller */
7502  #define S3C2410_PA_LCD    (0x4D000000)
7503 @@ -48,48 +34,12 @@
7504
7505  /* NAND flash controller */
7506  #define S3C2410_PA_NAND           (0x4E000000)
7507 -#define S3C24XX_SZ_NAND           SZ_1M
7508 -
7509 -/* UARTs */
7510 -#define S3C24XX_VA_UART           S3C_VA_UART
7511 -#define S3C2410_PA_UART           (0x50000000)
7512 -#define S3C24XX_SZ_UART           SZ_1M
7513 -
7514 -/* Timers */
7515 -#define S3C24XX_VA_TIMER   S3C_VA_TIMER
7516 -#define S3C2410_PA_TIMER   (0x51000000)
7517 -#define S3C24XX_SZ_TIMER   SZ_1M
7518 -
7519 -/* USB Device port */
7520 -#define S3C2410_PA_USBDEV  (0x52000000)
7521 -#define S3C24XX_SZ_USBDEV  SZ_1M
7522 -
7523 -/* Watchdog */
7524 -#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
7525 -#define S3C2410_PA_WATCHDOG (0x53000000)
7526 -#define S3C24XX_SZ_WATCHDOG SZ_1M
7527
7528  /* IIC hardware controller */
7529  #define S3C2410_PA_IIC    (0x54000000)
7530 -#define S3C24XX_SZ_IIC    SZ_1M
7531
7532  /* IIS controller */
7533  #define S3C2410_PA_IIS    (0x55000000)
7534 -#define S3C24XX_SZ_IIS    SZ_1M
7535 -
7536 -/* GPIO ports */
7537 -
7538 -/* the calculation for the VA of this must ensure that
7539 - * it is the same distance apart from the UART in the
7540 - * phsyical address space, as the initial mapping for the IO
7541 - * is done as a 1:1 maping. This puts it (currently) at
7542 - * 0xFA800000, which is not in the way of any current mapping
7543 - * by the base system.
7544 -*/
7545 -
7546 -#define S3C2410_PA_GPIO           (0x56000000)
7547 -#define S3C24XX_VA_GPIO           ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
7548 -#define S3C24XX_SZ_GPIO           SZ_1M
7549
7550  /* RTC */
7551  #define S3C2410_PA_RTC    (0x57000000)
7552 @@ -97,15 +47,12 @@
7553
7554  /* ADC */
7555  #define S3C2410_PA_ADC    (0x58000000)
7556 -#define S3C24XX_SZ_ADC    SZ_1M
7557
7558  /* SPI */
7559  #define S3C2410_PA_SPI    (0x59000000)
7560 -#define S3C24XX_SZ_SPI    SZ_1M
7561
7562  /* SDI */
7563  #define S3C2410_PA_SDI    (0x5A000000)
7564 -#define S3C24XX_SZ_SDI    SZ_1M
7565
7566  /* CAMIF */
7567  #define S3C2440_PA_CAMIF   (0x4F000000)
7568 @@ -120,13 +67,6 @@
7569  #define S3C2443_PA_HSMMC   (0x4A800000)
7570  #define S3C2443_SZ_HSMMC   (256)
7571
7572 -/* ISA style IO, for each machine to sort out mappings for, if it
7573 - * implements it. We reserve two 16M regions for ISA.
7574 - */
7575 -
7576 -#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
7577 -#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
7578 -
7579  /* physical addresses of all the chip-select areas */
7580
7581  #define S3C2410_CS0 (0x00000000)
7582 @@ -152,27 +92,16 @@
7583  #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
7584  #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
7585  #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
7586 -#define S3C24XX_PA_IIC      S3C2410_PA_IIC
7587  #define S3C24XX_PA_IIS      S3C2410_PA_IIS
7588  #define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
7589  #define S3C24XX_PA_RTC      S3C2410_PA_RTC
7590  #define S3C24XX_PA_ADC      S3C2410_PA_ADC
7591  #define S3C24XX_PA_SPI      S3C2410_PA_SPI
7592 +#define S3C24XX_PA_SDI      S3C2410_PA_SDI
7593 +#define S3C24XX_PA_NAND            S3C2410_PA_NAND
7594
7595 -/* deal with the registers that move under the 2412/2413 */
7596 -
7597 -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
7598 -#ifndef __ASSEMBLY__
7599 -extern void __iomem *s3c24xx_va_gpio2;
7600 -#endif
7601 -#ifdef CONFIG_CPU_S3C2412_ONLY
7602 -#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
7603 -#else
7604 -#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
7605 -#endif
7606 -#else
7607 -#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
7608 -#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
7609 -#endif
7610 +#define S3C_PA_IIC          S3C2410_PA_IIC
7611 +#define S3C_PA_UART        S3C24XX_PA_UART
7612 +#define S3C_PA_HSMMC0      S3C2443_PA_HSMMC
7613
7614  #endif /* __ASM_ARCH_MAP_H */
7615 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/mci.h
7616 ===================================================================
7617 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7618 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/mci.h       2009-01-02 00:01:56.000000000 +0100
7619 @@ -0,0 +1,13 @@
7620 +#ifndef _ARCH_MCI_H
7621 +#define _ARCH_MCI_H
7622 +
7623 +struct s3c24xx_mci_pdata {
7624 +       unsigned int    gpio_detect;
7625 +       unsigned int    gpio_wprotect;
7626 +       unsigned long   ocr_avail;
7627 +       unsigned int    do_dma;
7628 +       void            (*set_power)(unsigned char power_mode,
7629 +                                    unsigned short vdd);
7630 +};
7631 +
7632 +#endif /* _ARCH_NCI_H */
7633 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/neo1973-pm-gsm.h
7634 ===================================================================
7635 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7636 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/neo1973-pm-gsm.h    2009-01-02 00:01:56.000000000 +0100
7637 @@ -0,0 +1 @@
7638 +extern int gta_gsm_interrupts;
7639 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/pwm.h
7640 ===================================================================
7641 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7642 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/pwm.h       2009-01-02 00:01:56.000000000 +0100
7643 @@ -0,0 +1,46 @@
7644 +#ifndef __S3C2410_PWM_H
7645 +#define __S3C2410_PWM_H
7646 +
7647 +#include <linux/err.h>
7648 +#include <linux/platform_device.h>
7649 +#include <linux/clk.h>
7650 +
7651 +#include <mach/io.h>
7652 +#include <mach/hardware.h>
7653 +#include <asm/mach-types.h>
7654 +#include <plat/regs-timer.h>
7655 +#include <mach/gta01.h>
7656 +
7657 +enum pwm_timer {
7658 +       PWM0,
7659 +       PWM1,
7660 +       PWM2,
7661 +       PWM3,
7662 +       PWM4
7663 +};
7664 +
7665 +struct s3c2410_pwm {
7666 +       enum pwm_timer timerid;
7667 +       struct clk *pclk;
7668 +       unsigned long pclk_rate;
7669 +       unsigned long prescaler;
7670 +       unsigned long divider;
7671 +       unsigned long counter;
7672 +       unsigned long comparer;
7673 +};
7674 +
7675 +struct s3c24xx_pwm_platform_data{
7676 +        /* callback to attach platform children (to enforce suspend / resume
7677 +         * ordering */
7678 +        void (*attach_child_devices)(struct device *parent_device);
7679 +};
7680 +
7681 +int s3c2410_pwm_init(struct s3c2410_pwm *s3c2410_pwm);
7682 +int s3c2410_pwm_enable(struct s3c2410_pwm *s3c2410_pwm);
7683 +int s3c2410_pwm_disable(struct s3c2410_pwm *s3c2410_pwm);
7684 +int s3c2410_pwm_start(struct s3c2410_pwm *s3c2410_pwm);
7685 +int s3c2410_pwm_stop(struct s3c2410_pwm *s3c2410_pwm);
7686 +int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *s3c2410_pwm);
7687 +int s3c2410_pwm_dumpregs(void);
7688 +
7689 +#endif /* __S3C2410_PWM_H */
7690 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-clock.h
7691 ===================================================================
7692 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/regs-clock.h   2008-12-25 00:26:37.000000000 +0100
7693 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-clock.h        2009-01-02 00:01:56.000000000 +0100
7694 @@ -42,13 +42,6 @@
7695  #define S3C2410_CLKCON_IIS          (1<<17)
7696  #define S3C2410_CLKCON_SPI          (1<<18)
7697
7698 -#define S3C2410_PLLCON_MDIVSHIFT     12
7699 -#define S3C2410_PLLCON_PDIVSHIFT     4
7700 -#define S3C2410_PLLCON_SDIVSHIFT     0
7701 -#define S3C2410_PLLCON_MDIVMASK             ((1<<(1+(19-12)))-1)
7702 -#define S3C2410_PLLCON_PDIVMASK             ((1<<5)-1)
7703 -#define S3C2410_PLLCON_SDIVMASK             3
7704 -
7705  /* DCLKCON register addresses in gpio.h */
7706
7707  #define S3C2410_DCLKCON_DCLK0EN             (1<<0)
7708 @@ -76,32 +69,6 @@
7709  #define S3C2410_CLKSLOW_SLOWVAL(x)     (x)
7710  #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
7711
7712 -#ifndef __ASSEMBLY__
7713 -
7714 -#include <asm/div64.h>
7715 -
7716 -static inline unsigned int
7717 -s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
7718 -{
7719 -       unsigned int mdiv, pdiv, sdiv;
7720 -       uint64_t fvco;
7721 -
7722 -       mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
7723 -       pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
7724 -       sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
7725 -
7726 -       mdiv &= S3C2410_PLLCON_MDIVMASK;
7727 -       pdiv &= S3C2410_PLLCON_PDIVMASK;
7728 -       sdiv &= S3C2410_PLLCON_SDIVMASK;
7729 -
7730 -       fvco = (uint64_t)baseclk * (mdiv + 8);
7731 -       do_div(fvco, (pdiv + 2) << sdiv);
7732 -
7733 -       return (unsigned int)fvco;
7734 -}
7735 -
7736 -#endif /* __ASSEMBLY__ */
7737 -
7738  #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
7739
7740  /* extra registers */
7741 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
7742 ===================================================================
7743 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/regs-gpio.h    2008-12-25 00:26:37.000000000 +0100
7744 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-gpio.h 2009-01-02 00:01:56.000000000 +0100
7745 @@ -14,16 +14,7 @@
7746  #ifndef __ASM_ARCH_REGS_GPIO_H
7747  #define __ASM_ARCH_REGS_GPIO_H
7748
7749 -#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
7750 -
7751 -#define S3C2410_GPIO_BANKA   (32*0)
7752 -#define S3C2410_GPIO_BANKB   (32*1)
7753 -#define S3C2410_GPIO_BANKC   (32*2)
7754 -#define S3C2410_GPIO_BANKD   (32*3)
7755 -#define S3C2410_GPIO_BANKE   (32*4)
7756 -#define S3C2410_GPIO_BANKF   (32*5)
7757 -#define S3C2410_GPIO_BANKG   (32*6)
7758 -#define S3C2410_GPIO_BANKH   (32*7)
7759 +#include <mach/gpio-nrs.h>
7760
7761  #ifdef CONFIG_CPU_S3C2400
7762  #define S3C24XX_GPIO_BASE(x)  S3C2400_GPIO_BASE(x)
7763 @@ -1053,13 +1044,6 @@
7764  #define S3C24XX_EXTINT1           S3C24XX_GPIOREG2(0x8C)
7765  #define S3C24XX_EXTINT2           S3C24XX_GPIOREG2(0x90)
7766
7767 -/* values for S3C2410_EXTINT0/1/2 */
7768 -#define S3C2410_EXTINT_LOWLEV   (0x00)
7769 -#define S3C2410_EXTINT_HILEV    (0x01)
7770 -#define S3C2410_EXTINT_FALLEDGE         (0x02)
7771 -#define S3C2410_EXTINT_RISEEDGE         (0x04)
7772 -#define S3C2410_EXTINT_BOTHEDGE         (0x06)
7773 -
7774  /* interrupt filtering conrrol for EINT16..EINT23 */
7775  #define S3C2410_EINFLT0           S3C2410_GPIOREG(0x94)
7776  #define S3C2410_EINFLT1           S3C2410_GPIOREG(0x98)
7777 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
7778 ===================================================================
7779 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/regs-sdi.h     2008-12-25 00:26:37.000000000 +0100
7780 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-sdi.h  2009-01-02 00:01:56.000000000 +0100
7781 @@ -30,6 +30,7 @@
7782  #define S3C2410_SDIFSTA               (0x38)
7783
7784  #define S3C2410_SDIDATA               (0x3C)
7785 +#define S3C2410_SDIDATA_BYTE          (0x3C)
7786  #define S3C2410_SDIIMSK               (0x40)
7787
7788  #define S3C2440_SDIDATA               (0x40)
7789 @@ -37,6 +38,8 @@
7790
7791  #define S3C2440_SDICON_SDRESET        (1<<8)
7792  #define S3C2440_SDICON_MMCCLOCK       (1<<5)
7793 +#define S3C2440_SDIDATA_BYTE          (0x48)
7794 +
7795  #define S3C2410_SDICON_BYTEORDER      (1<<4)
7796  #define S3C2410_SDICON_SDIOIRQ        (1<<3)
7797  #define S3C2410_SDICON_RWAITEN        (1<<2)
7798 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/s3c24xx-serial.h
7799 ===================================================================
7800 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7801 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/s3c24xx-serial.h    2009-01-02 00:01:56.000000000 +0100
7802 @@ -0,0 +1,5 @@
7803 +#include <linux/resume-dependency.h>
7804 +
7805 +extern void s3c24xx_serial_console_set_silence(int silence);
7806 +extern void s3c24xx_serial_register_resume_dependency(struct resume_dependency *
7807 +                                            resume_dependency, int uart_index);
7808 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
7809 ===================================================================
7810 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/spi-gpio.h     2008-12-25 00:26:37.000000000 +0100
7811 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/spi-gpio.h  2009-01-02 00:43:03.000000000 +0100
7812 @@ -21,7 +21,15 @@ struct s3c2410_spigpio_info {
7813         int                      num_chipselect;
7814         int                      bus_num;
7815
7816 -       void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
7817 +       /*
7818 +        * FIXME: board_size and board_info DO NOT belong here.
7819 +        * These were already removed upstream... but we still rely on them
7820 +        * so leave for now and revisit this.
7821 +        */
7822 +       unsigned long            board_size;
7823 +       struct spi_board_info   *board_info;
7824 +
7825 +       void (*chip_select)(struct s3c2410_spigpio_info *spi, int csid, int cs);
7826  };
7827
7828
7829 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/spi.h
7830 ===================================================================
7831 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/spi.h  2008-12-25 00:26:37.000000000 +0100
7832 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/spi.h       2009-01-02 00:01:56.000000000 +0100
7833 @@ -22,5 +22,12 @@ struct s3c2410_spi_info {
7834         void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
7835  };
7836
7837 +/* Standard setup / suspend routines for SPI GPIO pins. */
7838 +
7839 +extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
7840 +                                                int enable);
7841 +
7842 +extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
7843 +                                             int enable);
7844
7845  #endif /* __ASM_ARCH_SPI_H */
7846 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/system-reset.h
7847 ===================================================================
7848 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/system-reset.h 2008-12-25 00:26:37.000000000 +0100
7849 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/system-reset.h      2009-01-02 00:01:56.000000000 +0100
7850 @@ -13,7 +13,7 @@
7851  #include <mach/hardware.h>
7852  #include <linux/io.h>
7853
7854 -#include <asm/plat-s3c/regs-watchdog.h>
7855 +#include <plat/regs-watchdog.h>
7856  #include <mach/regs-clock.h>
7857
7858  #include <linux/clk.h>
7859 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/tick.h
7860 ===================================================================
7861 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7862 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/tick.h      2009-01-02 00:01:56.000000000 +0100
7863 @@ -0,0 +1,15 @@
7864 +/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
7865 + *
7866 + * Copyright 2008 Simtec Electronics
7867 + *      Ben Dooks <ben@simtec.co.uk>
7868 + *      http://armlinux.simtec.co.uk/
7869 + *
7870 + * S3C2410 - timer tick support
7871 + */
7872 +
7873 +#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
7874 +
7875 +static inline int s3c24xx_ostimer_pending(void)
7876 +{
7877 +       return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
7878 +}
7879 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/timex.h
7880 ===================================================================
7881 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/timex.h        2008-12-25 00:26:37.000000000 +0100
7882 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
7883 @@ -1,26 +0,0 @@
7884 -/* arch/arm/mach-s3c2410/include/mach/timex.h
7885 - *
7886 - * Copyright (c) 2003-2005 Simtec Electronics
7887 - *     Ben Dooks <ben@simtec.co.uk>
7888 - *
7889 - * S3C2410 - time parameters
7890 - *
7891 - * This program is free software; you can redistribute it and/or modify
7892 - * it under the terms of the GNU General Public License version 2 as
7893 - * published by the Free Software Foundation.
7894 -*/
7895 -
7896 -#ifndef __ASM_ARCH_TIMEX_H
7897 -#define __ASM_ARCH_TIMEX_H
7898 -
7899 -/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
7900 - * a variable is useless. It seems as long as we make our timers an
7901 - * exact multiple of HZ, any value that makes a 1->1 correspondence
7902 - * for the time conversion functions to/from jiffies is acceptable.
7903 -*/
7904 -
7905 -
7906 -#define CLOCK_TICK_RATE 12000000
7907 -
7908 -
7909 -#endif /* __ASM_ARCH_TIMEX_H */
7910 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/ts.h
7911 ===================================================================
7912 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7913 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/ts.h        2009-01-02 00:01:56.000000000 +0100
7914 @@ -0,0 +1,35 @@
7915 +/* arch/arm/mach-s3c2410/include/mach/ts.h
7916 + *
7917 + * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
7918 + *
7919 + *
7920 + * This program is free software; you can redistribute it and/or modify
7921 + * it under the terms of the GNU General Public License version 2 as
7922 + * published by the Free Software Foundation.
7923 + *
7924 + *
7925 + *  Changelog:
7926 + *     24-Mar-2005     RTP     Created file
7927 + *     03-Aug-2005     RTP     Renamed to ts.h
7928 + */
7929 +
7930 +#ifndef __ASM_ARM_TS_H
7931 +#define __ASM_ARM_TS_H
7932 +
7933 +#include <linux/ts_filter.h>
7934 +
7935 +struct s3c2410_ts_mach_info {
7936 +        int delay;
7937 +        int presc;
7938 +        /* array of pointers to filter APIs we want to use, in order
7939 +         * ends on first NULL, all NULL is OK
7940 +         */
7941 +        struct ts_filter_api *filter_sequence[MAX_TS_FILTER_CHAIN];
7942 +        /* array of configuration ints, one for each filter above */
7943 +        void *filter_config[MAX_TS_FILTER_CHAIN];
7944 +};
7945 +
7946 +void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info);
7947 +
7948 +#endif /* __ASM_ARM_TS_H */
7949 +
7950 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/uncompress.h
7951 ===================================================================
7952 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/uncompress.h   2008-12-25 00:26:37.000000000 +0100
7953 +++ linux-2.6.28/arch/arm/mach-s3c2410/include/mach/uncompress.h        2009-01-02 00:01:56.000000000 +0100
7954 @@ -1,3 +1,4 @@
7955 +
7956  /* arch/arm/mach-s3c2410/include/mach/uncompress.h
7957   *
7958   * Copyright (c) 2003, 2007 Simtec Electronics
7959 Index: linux-2.6.28/arch/arm/mach-s3c2410/include/mach/vmalloc.h
7960 ===================================================================
7961 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/include/mach/vmalloc.h      2008-12-25 00:26:37.000000000 +0100
7962 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
7963 @@ -1,20 +0,0 @@
7964 -/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
7965 - *
7966 - * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
7967 - *
7968 - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
7969 - *                   http://www.simtec.co.uk/products/SWLINUX/
7970 - *
7971 - * This program is free software; you can redistribute it and/or modify
7972 - * it under the terms of the GNU General Public License version 2 as
7973 - * published by the Free Software Foundation.
7974 - *
7975 - * S3C2410 vmalloc definition
7976 -*/
7977 -
7978 -#ifndef __ASM_ARCH_VMALLOC_H
7979 -#define __ASM_ARCH_VMALLOC_H
7980 -
7981 -#define VMALLOC_END      (0xE0000000)
7982 -
7983 -#endif /* __ASM_ARCH_VMALLOC_H */
7984 Index: linux-2.6.28/arch/arm/mach-s3c2410/Kconfig
7985 ===================================================================
7986 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/Kconfig     2008-12-25 00:26:37.000000000 +0100
7987 +++ linux-2.6.28/arch/arm/mach-s3c2410/Kconfig  2009-01-02 00:01:56.000000000 +0100
7988 @@ -9,6 +9,7 @@ config CPU_S3C2410
7989         depends on ARCH_S3C2410
7990         select S3C2410_CLOCK
7991         select S3C2410_GPIO
7992 +       select S3C2410_PWM
7993         select CPU_LLSERIAL_S3C2410
7994         select S3C2410_PM if PM
7995         help
7996 @@ -32,11 +33,6 @@ config S3C2410_GPIO
7997         help
7998           GPIO code for S3C2410 and similar processors
7999
8000 -config S3C2410_CLOCK
8001 -       bool
8002 -       help
8003 -         Clock code for the S3C2410, and similar processors
8004 -
8005  config SIMTEC_NOR
8006         bool
8007         help
8008 @@ -49,6 +45,12 @@ config MACH_BAST_IDE
8009           Internal node for machines with an BAST style IDE
8010           interface
8011
8012 +config S3C2410_PWM
8013 +       bool
8014 +       help
8015 +         PWM timer code for the S3C2410, and similar processors
8016 +
8017 +
8018  menu "S3C2410 Machines"
8019
8020  config ARCH_SMDK2410
8021 @@ -84,6 +86,7 @@ config ARCH_BAST
8022         select PM_SIMTEC if PM
8023         select SIMTEC_NOR
8024         select MACH_BAST_IDE
8025 +       select S3C24XX_DCLK
8026         select ISA
8027         help
8028           Say Y here if you are using the Simtec Electronics EB2410ITX
8029 @@ -121,6 +124,7 @@ config MACH_TCT_HAMMER
8030  config MACH_VR1000
8031         bool "Thorcom VR1000"
8032         select PM_SIMTEC if PM
8033 +       select S3C24XX_DCLK
8034         select SIMTEC_NOR
8035         select MACH_BAST_IDE
8036         select CPU_S3C2410
8037 @@ -130,7 +134,16 @@ config MACH_VR1000
8038  config MACH_QT2410
8039         bool "QT2410"
8040         select CPU_S3C2410
8041 +       select DISPLAY_JBT6K74
8042         help
8043            Say Y here if you are using the Armzone QT2410
8044
8045 +config MACH_NEO1973_GTA01
8046 +       bool "FIC Neo1973 GSM Phone (GTA01 Hardware)"
8047 +       select CPU_S3C2410
8048 +       select MACH_NEO1973
8049 +       select SENSORS_PCF50606
8050 +       help
8051 +          Say Y here if you are using the FIC Neo1973 GSM Phone
8052 +
8053  endmenu
8054 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-amlm5900.c
8055 ===================================================================
8056 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-amlm5900.c     2008-12-25 00:26:37.000000000 +0100
8057 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-amlm5900.c  2009-01-02 00:01:56.000000000 +0100
8058 @@ -52,6 +52,7 @@
8059  #include <mach/regs-lcd.h>
8060  #include <mach/regs-gpio.h>
8061
8062 +#include <plat/iic.h>
8063  #include <plat/devs.h>
8064  #include <plat/cpu.h>
8065
8066 @@ -150,7 +151,7 @@ static struct platform_device *amlm5900_
8067  #endif
8068         &s3c_device_adc,
8069         &s3c_device_wdt,
8070 -       &s3c_device_i2c,
8071 +       &s3c_device_i2c0,
8072         &s3c_device_usb,
8073         &s3c_device_rtc,
8074         &s3c_device_usbgadget,
8075 @@ -233,6 +234,7 @@ static void __init amlm5900_init(void)
8076  #ifdef CONFIG_FB_S3C2410
8077         s3c24xx_fb_set_platdata(&amlm5900_fb_info);
8078  #endif
8079 +       s3c_i2c0_set_platdata(NULL);
8080         platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
8081  }
8082
8083 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-bast.c
8084 ===================================================================
8085 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-bast.c 2008-12-25 00:26:37.000000000 +0100
8086 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-bast.c      2009-01-02 00:01:56.000000000 +0100
8087 @@ -44,8 +44,8 @@
8088  #include <mach/regs-mem.h>
8089  #include <mach/regs-lcd.h>
8090
8091 -#include <asm/plat-s3c/nand.h>
8092 -#include <asm/plat-s3c/iic.h>
8093 +#include <plat/nand.h>
8094 +#include <plat/iic.h>
8095  #include <mach/fb.h>
8096
8097  #include <linux/mtd/mtd.h>
8098 @@ -406,7 +406,7 @@ static struct platform_device bast_sio =
8099   * standard 100KHz i2c bus frequency
8100  */
8101
8102 -static struct s3c2410_platform_i2c bast_i2c_info = {
8103 +static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
8104         .flags          = 0,
8105         .slave_addr     = 0x10,
8106         .bus_freq       = 100*1000,
8107 @@ -553,7 +553,7 @@ static struct platform_device *bast_devi
8108         &s3c_device_usb,
8109         &s3c_device_lcd,
8110         &s3c_device_wdt,
8111 -       &s3c_device_i2c,
8112 +       &s3c_device_i2c0,
8113         &s3c_device_rtc,
8114         &s3c_device_nand,
8115         &bast_device_dm9k,
8116 @@ -588,7 +588,8 @@ static void __init bast_map_io(void)
8117         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
8118
8119         s3c_device_nand.dev.platform_data = &bast_nand_info;
8120 -       s3c_device_i2c.dev.platform_data = &bast_i2c_info;
8121 +
8122 +       s3c_i2c0_set_platdata(&bast_i2c_info);
8123
8124         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
8125         s3c24xx_init_clocks(0);
8126 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-gta01.c
8127 ===================================================================
8128 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8129 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-gta01.c     2009-01-02 00:01:56.000000000 +0100
8130 @@ -0,0 +1,786 @@
8131 +/*
8132 + * linux/arch/arm/mach-s3c2410/mach-gta01.c
8133 + *
8134 + * S3C2410 Machine Support for the FIC Neo1973 GTA01
8135 + *
8136 + * Copyright (C) 2006-2007 by Openmoko, Inc.
8137 + * Author: Harald Welte <laforge@openmoko.org>
8138 + * All rights reserved.
8139 + *
8140 + * This program is free software; you can redistribute it and/or
8141 + * modify it under the terms of the GNU General Public License as
8142 + * published by the Free Software Foundation; either version 2 of
8143 + * the License, or (at your option) any later version.
8144 + *
8145 + * This program is distributed in the hope that it will be useful,
8146 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8147 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8148 + * GNU General Public License for more details.
8149 + *
8150 + * You should have received a copy of the GNU General Public License
8151 + * along with this program; if not, write to the Free Software
8152 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
8153 + * MA 02111-1307 USA
8154 + *
8155 + */
8156 +
8157 +#include <linux/kernel.h>
8158 +#include <linux/types.h>
8159 +#include <linux/interrupt.h>
8160 +#include <linux/list.h>
8161 +#include <linux/timer.h>
8162 +#include <linux/init.h>
8163 +#include <linux/workqueue.h>
8164 +#include <linux/platform_device.h>
8165 +#include <linux/i2c.h>
8166 +#include <linux/serial_core.h>
8167 +#include <mach/ts.h>
8168 +#include <linux/spi/spi.h>
8169 +#include <linux/spi/spi_bitbang.h>
8170 +#include <linux/mmc/mmc.h>
8171 +#include <linux/mmc/host.h>
8172 +
8173 +#include <linux/mtd/mtd.h>
8174 +#include <linux/mtd/nand.h>
8175 +#include <linux/mtd/nand_ecc.h>
8176 +#include <linux/mtd/partitions.h>
8177 +
8178 +#include <linux/mmc/host.h>
8179 +
8180 +#include <linux/pcf50606.h>
8181 +
8182 +#include <asm/mach/arch.h>
8183 +#include <asm/mach/map.h>
8184 +#include <asm/mach/irq.h>
8185 +
8186 +#include <mach/hardware.h>
8187 +#include <mach/io.h>
8188 +#include <asm/irq.h>
8189 +#include <asm/mach-types.h>
8190 +
8191 +#include <mach/regs-gpio.h>
8192 +#include <mach/fb.h>
8193 +#include <mach/mci.h>
8194 +#include <mach/spi.h>
8195 +#include <mach/spi-gpio.h>
8196 +#include <mach/usb-control.h>
8197 +
8198 +#include <mach/gta01.h>
8199 +
8200 +#include <plat/regs-serial.h>
8201 +#include <plat/nand.h>
8202 +#include <plat/devs.h>
8203 +#include <plat/cpu.h>
8204 +#include <plat/pm.h>
8205 +#include <plat/udc.h>
8206 +#include <plat/iic.h>
8207 +#include <asm/plat-s3c24xx/neo1973.h>
8208 +#include <mach/neo1973-pm-gsm.h>
8209 +
8210 +#include <linux/jbt6k74.h>
8211 +
8212 +#include <linux/ts_filter_mean.h>
8213 +#include <linux/ts_filter_median.h>
8214 +
8215 +
8216 +static struct map_desc gta01_iodesc[] __initdata = {
8217 +       {
8218 +               .virtual        = 0xe0000000,
8219 +               .pfn            = __phys_to_pfn(S3C2410_CS3+0x01000000),
8220 +               .length         = SZ_1M,
8221 +               .type           = MT_DEVICE
8222 +       },
8223 +};
8224 +
8225 +#define UCON S3C2410_UCON_DEFAULT
8226 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
8227 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
8228 +/* UFCON for the gta01 sets the FIFO trigger level at 4, not 8 */
8229 +#define UFCON_GTA01_PORT0 S3C2410_UFCON_FIFOMODE
8230 +
8231 +static struct s3c2410_uartcfg gta01_uartcfgs[] = {
8232 +       [0] = {
8233 +               .hwport      = 0,
8234 +               .flags       = 0,
8235 +               .ucon        = UCON,
8236 +               .ulcon       = ULCON,
8237 +               .ufcon       = UFCON_GTA01_PORT0,
8238 +       },
8239 +       [1] = {
8240 +               .hwport      = 1,
8241 +               .flags       = 0,
8242 +               .ucon        = UCON,
8243 +               .ulcon       = ULCON,
8244 +               .ufcon       = UFCON,
8245 +       },
8246 +};
8247 +
8248 +/* PMU driver info */
8249 +
8250 +static int pmu_callback(struct device *dev, unsigned int feature,
8251 +                       enum pmu_event event)
8252 +{
8253 +       switch (feature) {
8254 +       case PCF50606_FEAT_ACD:
8255 +               switch (event) {
8256 +               case PMU_EVT_INSERT:
8257 +                       pcf50606_charge_fast(pcf50606_global, 1);
8258 +                       break;
8259 +               case PMU_EVT_REMOVE:
8260 +                       pcf50606_charge_fast(pcf50606_global, 0);
8261 +                       break;
8262 +               default:
8263 +                       break;
8264 +               }
8265 +               break;
8266 +       default:
8267 +               break;
8268 +       }
8269 +
8270 +       return 0;
8271 +}
8272 +
8273 +static struct pcf50606_platform_data gta01_pcf_pdata = {
8274 +       .used_features  = PCF50606_FEAT_EXTON |
8275 +                         PCF50606_FEAT_MBC |
8276 +                         PCF50606_FEAT_BBC |
8277 +                         PCF50606_FEAT_RTC |
8278 +                         PCF50606_FEAT_WDT |
8279 +                         PCF50606_FEAT_CHGCUR |
8280 +                         PCF50606_FEAT_BATVOLT |
8281 +                         PCF50606_FEAT_BATTEMP,
8282 +       .onkey_seconds_required = 3,
8283 +       .cb             = &pmu_callback,
8284 +       .r_fix_batt     = 10000,
8285 +       .r_fix_batt_par = 10000,
8286 +       .r_sense_milli  = 220,
8287 +       .rails  = {
8288 +               [PCF50606_REGULATOR_D1REG] = {
8289 +                       .name           = "bt_3v15",
8290 +                       .voltage        = {
8291 +                               .init   = 3150,
8292 +                               .max    = 3150,
8293 +                       },
8294 +               },
8295 +               [PCF50606_REGULATOR_D2REG] = {
8296 +                       .name           = "gl_2v5",
8297 +                       .voltage        = {
8298 +                               .init   = 2500,
8299 +                               .max    = 2500,
8300 +                       },
8301 +               },
8302 +               [PCF50606_REGULATOR_D3REG] = {
8303 +                       .name           = "stby_1v8",
8304 +                       .flags          = PMU_VRAIL_F_SUSPEND_ON,
8305 +                       .voltage        = {
8306 +                               .init   = 1800,
8307 +                               .max    = 2100,
8308 +                       },
8309 +               },
8310 +               [PCF50606_REGULATOR_DCD] = {
8311 +                       .name           = "gl_1v5",
8312 +                       .voltage        = {
8313 +                               .init   = 1500,
8314 +                               .max    = 1500,
8315 +                       },
8316 +               },
8317 +               [PCF50606_REGULATOR_DCDE] = {
8318 +                       .name           = "io_3v3",
8319 +                       .flags          = PMU_VRAIL_F_SUSPEND_ON,
8320 +                       .voltage        = {
8321 +                               .init   = 3300,
8322 +                               .max    = 3330,
8323 +                       },
8324 +               },
8325 +               [PCF50606_REGULATOR_DCUD] = {
8326 +                       .name           = "core_1v8",
8327 +                       .flags          = PMU_VRAIL_F_SUSPEND_ON,
8328 +                       .voltage        = {
8329 +                               .init   = 2100,
8330 +                               .max    = 2100,
8331 +                       },
8332 +               },
8333 +               [PCF50606_REGULATOR_IOREG] = {
8334 +                       .name           = "codec_3v3",
8335 +                       .voltage        = {
8336 +                               .init   = 3300,
8337 +                               .max    = 3300,
8338 +                       },
8339 +               },
8340 +               [PCF50606_REGULATOR_LPREG] = {
8341 +                       .name           = "lcm_3v3",
8342 +                       .voltage        = {
8343 +                               .init   = 3300,
8344 +                               .max    = 3300,
8345 +                       },
8346 +               }
8347 +       },
8348 +};
8349 +
8350 +static void cfg_pmu_vrail(struct pmu_voltage_rail *vrail, char *name,
8351 +                         unsigned int flags, unsigned int init,
8352 +                         unsigned int max)
8353 +{
8354 +       vrail->name = name;
8355 +       vrail->flags = flags;
8356 +       vrail->voltage.init = init;
8357 +       vrail->voltage.max = max;
8358 +}
8359 +
8360 +static void mangle_pmu_pdata_by_system_rev(void)
8361 +{
8362 +       switch (system_rev) {
8363 +       case GTA01Bv4_SYSTEM_REV:
8364 +               gta01_pcf_pdata.used_features |= PCF50606_FEAT_ACD;
8365 +               break;
8366 +       case GTA01Bv3_SYSTEM_REV:
8367 +       case GTA01Bv2_SYSTEM_REV:
8368 +               gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
8369 +                                       .name = "user1";
8370 +               gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
8371 +                                       .flags &= ~PMU_VRAIL_F_SUSPEND_ON;
8372 +               gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
8373 +                                       .flags = PMU_VRAIL_F_UNUSED;
8374 +               break;
8375 +       case GTA01v4_SYSTEM_REV:
8376 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCUD],
8377 +                             "core_1v8", PMU_VRAIL_F_SUSPEND_ON, 1800, 1800);
8378 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D1REG],
8379 +                             "vrf_3v", 0, 3000, 3000);
8380 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG],
8381 +                             "vtcxo_2v8", 0, 2800, 2800);
8382 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCD],
8383 +                             "gl_3v5", 0, 3500, 3500);
8384 +               break;
8385 +       case GTA01v3_SYSTEM_REV:
8386 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D1REG],
8387 +                             "vrf_3v", 0, 3000, 3000);
8388 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D2REG],
8389 +                             "sd_3v3", 0, 3300, 3300);
8390 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG],
8391 +                             "codec_3v3", 0, 3300, 3300);
8392 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCD],
8393 +                             "gpsio_3v3", 0, 3300, 3300);
8394 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCUD],
8395 +                             "core_1v8", PMU_VRAIL_F_SUSPEND_ON, 1800, 1800);
8396 +               cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_IOREG],
8397 +                             "vtcxo_2v8", 0, 2800, 2800);
8398 +               break;
8399 +       }
8400 +}
8401 +
8402 +static struct resource gta01_pmu_resources[] = {
8403 +       [0] = {
8404 +               .flags  = IORESOURCE_IRQ,
8405 +               .start  = GTA01_IRQ_PCF50606,
8406 +               .end    = GTA01_IRQ_PCF50606,
8407 +       },
8408 +};
8409 +
8410 +struct platform_device gta01_pmu_dev = {
8411 +       .name           = "pcf50606",
8412 +       .num_resources  = ARRAY_SIZE(gta01_pmu_resources),
8413 +       .resource       = gta01_pmu_resources,
8414 +       .dev            = {
8415 +               .platform_data = &gta01_pcf_pdata,
8416 +       },
8417 +};
8418 +
8419 +/* LCD driver info */
8420 +
8421 +/* Configuration for 480x640 toppoly TD028TTEC1.
8422 + * Do not mark this as __initdata or it will break! */
8423 +static struct s3c2410fb_display gta01_displays[] =  {
8424 +       {
8425 +               .type           = S3C2410_LCDCON1_TFT,
8426 +               .width          = 43,
8427 +               .height         = 58,
8428 +               .xres           = 480,
8429 +               .yres           = 640,
8430 +               .bpp            = 16,
8431 +
8432 +               .pixclock       = 40000,        /* HCLK/4 */
8433 +               .left_margin    = 104,
8434 +               .right_margin   = 8,
8435 +               .hsync_len      = 8,
8436 +               .upper_margin   = 2,
8437 +               .lower_margin   = 16,
8438 +               .vsync_len      = 2,
8439 +               .lcdcon5        = S3C2410_LCDCON5_FRM565 |
8440 +                                 S3C2410_LCDCON5_INVVCLK |
8441 +                                 S3C2410_LCDCON5_INVVLINE |
8442 +                                 S3C2410_LCDCON5_INVVFRAME |
8443 +                                 S3C2410_LCDCON5_PWREN |
8444 +                                 S3C2410_LCDCON5_HWSWP,
8445 +       },
8446 +       {
8447 +               .type           = S3C2410_LCDCON1_TFT,
8448 +               .width          = 43,
8449 +               .height         = 58,
8450 +               .xres           = 480,
8451 +               .yres           = 640,
8452 +               .bpp            = 32,
8453 +
8454 +               .pixclock       = 40000,        /* HCLK/4 */
8455 +               .left_margin    = 104,
8456 +               .right_margin   = 8,
8457 +               .hsync_len      = 8,
8458 +               .upper_margin   = 2,
8459 +               .lower_margin   = 16,
8460 +               .vsync_len      = 2,
8461 +               .lcdcon5        = S3C2410_LCDCON5_FRM565 |
8462 +                                 S3C2410_LCDCON5_INVVCLK |
8463 +                                 S3C2410_LCDCON5_INVVLINE |
8464 +                                 S3C2410_LCDCON5_INVVFRAME |
8465 +                                 S3C2410_LCDCON5_PWREN |
8466 +                                 S3C2410_LCDCON5_HWSWP,
8467 +       },
8468 +       {
8469 +               .type           = S3C2410_LCDCON1_TFT,
8470 +               .width          = 43,
8471 +               .height         = 58,
8472 +               .xres           = 240,
8473 +               .yres           = 320,
8474 +               .bpp            = 16,
8475 +
8476 +               .pixclock       = 40000,        /* HCLK/4 */
8477 +               .left_margin    = 104,
8478 +               .right_margin   = 8,
8479 +               .hsync_len      = 8,
8480 +               .upper_margin   = 2,
8481 +               .lower_margin   = 16,
8482 +               .vsync_len      = 2,
8483 +               .lcdcon5        = S3C2410_LCDCON5_FRM565 |
8484 +                                 S3C2410_LCDCON5_INVVCLK |
8485 +                                 S3C2410_LCDCON5_INVVLINE |
8486 +                                 S3C2410_LCDCON5_INVVFRAME |
8487 +                                 S3C2410_LCDCON5_PWREN |
8488 +                                 S3C2410_LCDCON5_HWSWP,
8489 +       },
8490 +};
8491 +
8492 +static struct s3c2410fb_mach_info gta01_lcd_cfg __initdata = {
8493 +       .displays       = gta01_displays,
8494 +       .num_displays   = ARRAY_SIZE(gta01_displays),
8495 +       .default_display = 0,
8496 +
8497 +       .lpcsel         = ((0xCE6) & ~7) | 1<<4,
8498 +};
8499 +
8500 +static struct platform_device *gta01_devices[] __initdata = {
8501 +       &s3c_device_usb,
8502 +       &s3c_device_lcd,
8503 +       &s3c_device_wdt,
8504 +       &s3c_device_i2c0,
8505 +       &s3c_device_iis,
8506 +       &s3c_device_sdi,
8507 +       &s3c_device_usbgadget,
8508 +       &s3c_device_nand,
8509 +       &s3c_device_ts,
8510 +};
8511 +
8512 +static struct s3c2410_nand_set gta01_nand_sets[] = {
8513 +       [0] = {
8514 +               .name           = "neo1973-nand",
8515 +               .nr_chips       = 1,
8516 +               .flags          = S3C2410_NAND_BBT,
8517 +       },
8518 +};
8519 +
8520 +static struct s3c2410_platform_nand gta01_nand_info = {
8521 +       .tacls          = 20,
8522 +       .twrph0         = 60,
8523 +       .twrph1         = 20,
8524 +       .nr_sets        = ARRAY_SIZE(gta01_nand_sets),
8525 +       .sets           = gta01_nand_sets,
8526 +};
8527 +
8528 +static void gta01_mmc_set_power(unsigned char power_mode, unsigned short vdd)
8529 +{
8530 +       int bit;
8531 +       int mv = 1700; /* 1.7V for MMC_VDD_165_195 */
8532 +
8533 +       printk(KERN_DEBUG "mmc_set_power(power_mode=%u, vdd=%u)\n",
8534 +              power_mode, vdd);
8535 +
8536 +       switch (system_rev) {
8537 +       case GTA01v3_SYSTEM_REV:
8538 +               switch (power_mode) {
8539 +               case MMC_POWER_OFF:
8540 +                       pcf50606_onoff_set(pcf50606_global,
8541 +                                          PCF50606_REGULATOR_D2REG, 0);
8542 +                       break;
8543 +               case MMC_POWER_ON:
8544 +                       /* translate MMC_VDD_* VDD bit to mv */
8545 +                       for (bit = 8; bit != 24; bit++)
8546 +                               if (vdd == (1 << bit))
8547 +                                       mv += 100 * (bit - 4);
8548 +                       pcf50606_voltage_set(pcf50606_global,
8549 +                                            PCF50606_REGULATOR_D2REG, mv);
8550 +                       pcf50606_onoff_set(pcf50606_global,
8551 +                                          PCF50606_REGULATOR_D2REG, 1);
8552 +                       break;
8553 +               }
8554 +               break;
8555 +       case GTA01v4_SYSTEM_REV:
8556 +       case GTA01Bv2_SYSTEM_REV:
8557 +       case GTA01Bv3_SYSTEM_REV:
8558 +       case GTA01Bv4_SYSTEM_REV:
8559 +               switch (power_mode) {
8560 +               case MMC_POWER_OFF:
8561 +                       neo1973_gpb_setpin(GTA01_GPIO_SDMMC_ON, 1);
8562 +                       break;
8563 +               case MMC_POWER_ON:
8564 +                       neo1973_gpb_setpin(GTA01_GPIO_SDMMC_ON, 0);
8565 +                       break;
8566 +               }
8567 +               break;
8568 +       }
8569 +}
8570 +
8571 +static struct s3c24xx_mci_pdata gta01_mmc_cfg = {
8572 +       .gpio_detect    = GTA01_GPIO_nSD_DETECT,
8573 +       .set_power      = &gta01_mmc_set_power,
8574 +       .ocr_avail      = MMC_VDD_165_195|MMC_VDD_20_21|
8575 +                         MMC_VDD_21_22|MMC_VDD_22_23|MMC_VDD_23_24|
8576 +                         MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
8577 +                         MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
8578 +                         MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33,
8579 +};
8580 +
8581 +static void gta01_udc_command(enum s3c2410_udc_cmd_e cmd)
8582 +{
8583 +       printk(KERN_DEBUG "%s(%d)\n", __func__, cmd);
8584 +
8585 +       switch (cmd) {
8586 +       case S3C2410_UDC_P_ENABLE:
8587 +               neo1973_gpb_setpin(GTA01_GPIO_USB_PULLUP, 1);
8588 +               break;
8589 +       case S3C2410_UDC_P_DISABLE:
8590 +               neo1973_gpb_setpin(GTA01_GPIO_USB_PULLUP, 0);
8591 +               break;
8592 +       default:
8593 +               break;
8594 +       }
8595 +}
8596 +
8597 +/* use a work queue, since I2C API inherently schedules
8598 + * and we get called in hardirq context from UDC driver */
8599 +
8600 +struct vbus_draw {
8601 +       struct work_struct work;
8602 +       int ma;
8603 +};
8604 +static struct vbus_draw gta01_udc_vbus_drawer;
8605 +
8606 +static void __gta01_udc_vbus_draw(struct work_struct *work)
8607 +{
8608 +       /* this is a fix to work around boot-time ordering problems if the
8609 +        * s3c2410_udc is initialized before the pcf50606 driver has defined
8610 +        * pcf50606_global */
8611 +       if (!pcf50606_global)
8612 +               return;
8613 +
8614 +       if (gta01_udc_vbus_drawer.ma >= 500) {
8615 +               /* enable fast charge */
8616 +               printk(KERN_DEBUG "udc: enabling fast charge\n");
8617 +               pcf50606_charge_fast(pcf50606_global, 1);
8618 +       } else {
8619 +               /* disable fast charge */
8620 +               printk(KERN_DEBUG "udc: disabling fast charge\n");
8621 +               pcf50606_charge_fast(pcf50606_global, 0);
8622 +       }
8623 +}
8624 +
8625 +static void gta01_udc_vbus_draw(unsigned int ma)
8626 +{
8627 +       gta01_udc_vbus_drawer.ma = ma;
8628 +       schedule_work(&gta01_udc_vbus_drawer.work);
8629 +}
8630 +
8631 +static struct s3c2410_udc_mach_info gta01_udc_cfg = {
8632 +       .vbus_draw      = gta01_udc_vbus_draw,
8633 +};
8634 +
8635 +
8636 +/* touchscreen configuration */
8637 +
8638 +static struct ts_filter_median_configuration gta01_ts_median_config = {
8639 +       .extent = 31,
8640 +       .decimation_below = 24,
8641 +       .decimation_threshold = 8 * 3,
8642 +       .decimation_above = 12,
8643 +};
8644 +
8645 +static struct ts_filter_mean_configuration gta01_ts_mean_config = {
8646 +       .bits_filter_length = 5,
8647 +       .averaging_threshold = 12
8648 +};
8649 +
8650 +static struct s3c2410_ts_mach_info gta01_ts_cfg = {
8651 +       .delay = 10000,
8652 +       .presc = 0xff, /* slow as we can go */
8653 +       .filter_sequence = {
8654 +               [0] = &ts_filter_median_api,
8655 +               [1] = &ts_filter_mean_api,
8656 +       },
8657 +       .filter_config = {
8658 +               [0] = &gta01_ts_median_config,
8659 +               [1] = &gta01_ts_mean_config,
8660 +       },
8661 +};
8662 +
8663 +
8664 +/* SPI */
8665 +
8666 +static void gta01_jbt6k74_reset(int devidx, int level)
8667 +{
8668 +       /* empty place holder; gta01 does not yet use this */
8669 +       printk(KERN_DEBUG "gta01_jbt6k74_reset\n");
8670 +}
8671 +
8672 +static void gta01_jbt6k74_resuming(int devidx)
8673 +{
8674 +       gta01bl_deferred_resume();
8675 +}
8676 +
8677 +const struct jbt6k74_platform_data gta01_jbt6k74_pdata = {
8678 +       .reset          = gta01_jbt6k74_reset,
8679 +       .resuming       = gta01_jbt6k74_resuming,
8680 +};
8681 +
8682 +static struct spi_board_info gta01_spi_board_info[] = {
8683 +       {
8684 +               .modalias       = "jbt6k74",
8685 +               .platform_data  = &gta01_jbt6k74_pdata,
8686 +               /* controller_data */
8687 +               /* irq */
8688 +               .max_speed_hz   = 10 * 1000 * 1000,
8689 +               .bus_num        = 1,
8690 +               /* chip_select */
8691 +       },
8692 +};
8693 +
8694 +static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int csidx, int cs)
8695 +{
8696 +       switch (cs) {
8697 +       case BITBANG_CS_ACTIVE:
8698 +               s3c2410_gpio_setpin(S3C2410_GPG3, 0);
8699 +               break;
8700 +       case BITBANG_CS_INACTIVE:
8701 +               s3c2410_gpio_setpin(S3C2410_GPG3, 1);
8702 +               break;
8703 +       }
8704 +}
8705 +
8706 +static struct s3c2410_spigpio_info spi_gpio_cfg = {
8707 +       .pin_clk        = S3C2410_GPG7,
8708 +       .pin_mosi       = S3C2410_GPG6,
8709 +       .pin_miso       = S3C2410_GPG5,
8710 +       .board_size     = ARRAY_SIZE(gta01_spi_board_info),
8711 +       .board_info     = gta01_spi_board_info,
8712 +       .chip_select    = &spi_gpio_cs,
8713 +       .num_chipselect = 2,   /*** Should be 1 or 2 for gta01? ***/
8714 +};
8715 +
8716 +static struct resource s3c_spi_lcm_resource[] = {
8717 +       [0] = {
8718 +               .start = S3C2410_GPG3,
8719 +               .end   = S3C2410_GPG3,
8720 +       },
8721 +       [1] = {
8722 +               .start = S3C2410_GPG5,
8723 +               .end   = S3C2410_GPG5,
8724 +       },
8725 +       [2] = {
8726 +               .start = S3C2410_GPG6,
8727 +               .end   = S3C2410_GPG6,
8728 +       },
8729 +       [3] = {
8730 +               .start = S3C2410_GPG7,
8731 +               .end   = S3C2410_GPG7,
8732 +       },
8733 +};
8734 +
8735 +struct platform_device s3c_device_spi_lcm = {
8736 +       .name             = "spi_s3c24xx_gpio",
8737 +       .id               = 1,
8738 +       .num_resources    = ARRAY_SIZE(s3c_spi_lcm_resource),
8739 +       .resource         = s3c_spi_lcm_resource,
8740 +       .dev = {
8741 +               .platform_data = &spi_gpio_cfg,
8742 +       },
8743 +};
8744 +
8745 +static struct gta01bl_machinfo backlight_machinfo = {
8746 +       .default_intensity      = 1,
8747 +       .max_intensity          = 1,
8748 +       .limit_mask             = 1,
8749 +       .defer_resume_backlight = 1,
8750 +};
8751 +
8752 +static struct resource gta01_bl_resources[] = {
8753 +       [0] = {
8754 +               .start  = GTA01_GPIO_BACKLIGHT,
8755 +               .end    = GTA01_GPIO_BACKLIGHT,
8756 +       },
8757 +};
8758 +
8759 +struct platform_device gta01_bl_dev = {
8760 +       .name           = "gta01-bl",
8761 +       .num_resources  = ARRAY_SIZE(gta01_bl_resources),
8762 +       .resource       = gta01_bl_resources,
8763 +       .dev            = {
8764 +               .platform_data = &backlight_machinfo,
8765 +       },
8766 +};
8767 +
8768 +static struct resource gta01_led_resources[] = {
8769 +       [0] = {
8770 +               .start  = GTA01_GPIO_VIBRATOR_ON,
8771 +               .end    = GTA01_GPIO_VIBRATOR_ON,
8772 +       },
8773 +};
8774 +
8775 +struct platform_device gta01_led_dev = {
8776 +       .name           = "neo1973-vibrator",
8777 +       .num_resources  = ARRAY_SIZE(gta01_led_resources),
8778 +       .resource       = gta01_led_resources,
8779 +};
8780 +
8781 +static struct resource gta01_button_resources[] = {
8782 +       [0] = {
8783 +               .start = GTA01_GPIO_AUX_KEY,
8784 +               .end   = GTA01_GPIO_AUX_KEY,
8785 +       },
8786 +       [1] = {
8787 +               .start = GTA01_GPIO_HOLD_KEY,
8788 +               .end   = GTA01_GPIO_HOLD_KEY,
8789 +       },
8790 +       [2] = {
8791 +               .start = GTA01_GPIO_JACK_INSERT,
8792 +               .end   = GTA01_GPIO_JACK_INSERT,
8793 +       },
8794 +       [3] = {
8795 +               .start = 0,
8796 +               .end   = 0,
8797 +       },
8798 +       [4] = {
8799 +               .start = 0,
8800 +               .end   = 0,
8801 +       },
8802 +};
8803 +
8804 +struct platform_device gta01_button_dev = {
8805 +       .name           = "neo1973-button",
8806 +       .num_resources  = ARRAY_SIZE(gta01_button_resources),
8807 +       .resource       = gta01_button_resources,
8808 +};
8809 +
8810 +static struct platform_device gta01_pm_gsm_dev = {
8811 +       .name           = "neo1973-pm-gsm",
8812 +};
8813 +
8814 +/* USB */
8815 +static struct s3c2410_hcd_info gta01_usb_info = {
8816 +       .port[0]        = {
8817 +               .flags  = S3C_HCDFLG_USED,
8818 +       },
8819 +       .port[1]        = {
8820 +               .flags  = 0,
8821 +       },
8822 +};
8823 +
8824 +static void __init gta01_map_io(void)
8825 +{
8826 +       s3c24xx_init_io(gta01_iodesc, ARRAY_SIZE(gta01_iodesc));
8827 +       s3c24xx_init_clocks(12*1000*1000);
8828 +       s3c24xx_init_uarts(gta01_uartcfgs, ARRAY_SIZE(gta01_uartcfgs));
8829 +}
8830 +
8831 +static irqreturn_t gta01_modem_irq(int irq, void *param)
8832 +{
8833 +       printk(KERN_DEBUG "GSM wakeup interrupt (IRQ %d)\n", irq);
8834 +       gta_gsm_interrupts++;
8835 +       return IRQ_HANDLED;
8836 +}
8837 +
8838 +static void __init gta01_machine_init(void)
8839 +{
8840 +       int rc;
8841 +
8842 +       if (system_rev == GTA01v4_SYSTEM_REV ||
8843 +           system_rev == GTA01Bv2_SYSTEM_REV ||
8844 +           system_rev == GTA01Bv3_SYSTEM_REV ||
8845 +           system_rev == GTA01Bv4_SYSTEM_REV) {
8846 +               gta01_udc_cfg.udc_command = gta01_udc_command;
8847 +               gta01_mmc_cfg.ocr_avail = MMC_VDD_32_33;
8848 +       }
8849 +
8850 +       s3c_device_usb.dev.platform_data = &gta01_usb_info;
8851 +       s3c_device_nand.dev.platform_data = &gta01_nand_info;
8852 +       s3c_device_sdi.dev.platform_data = &gta01_mmc_cfg;
8853 +
8854 +       s3c24xx_fb_set_platdata(&gta01_lcd_cfg);
8855 +
8856 +       INIT_WORK(&gta01_udc_vbus_drawer.work, __gta01_udc_vbus_draw);
8857 +       s3c24xx_udc_set_platdata(&gta01_udc_cfg);
8858 +       s3c_i2c0_set_platdata(NULL);
8859 +       set_s3c2410ts_info(&gta01_ts_cfg);
8860 +
8861 +       /* Set LCD_RESET / XRES to high */
8862 +       s3c2410_gpio_cfgpin(S3C2410_GPC6, S3C2410_GPIO_OUTPUT);
8863 +       s3c2410_gpio_setpin(S3C2410_GPC6, 1);
8864 +
8865 +       /* SPI chip select is gpio output */
8866 +       s3c2410_gpio_cfgpin(S3C2410_GPG3, S3C2410_GPIO_OUTPUT);
8867 +       s3c2410_gpio_setpin(S3C2410_GPG3, 1);
8868 +       platform_device_register(&s3c_device_spi_lcm);
8869 +
8870 +       platform_device_register(&gta01_bl_dev);
8871 +       platform_device_register(&gta01_button_dev);
8872 +       platform_device_register(&gta01_pm_gsm_dev);
8873 +
8874 +       switch (system_rev) {
8875 +       case GTA01v3_SYSTEM_REV:
8876 +       case GTA01v4_SYSTEM_REV:
8877 +               /* just use the default (GTA01_IRQ_PCF50606) */
8878 +               break;
8879 +       case GTA01Bv2_SYSTEM_REV:
8880 +       case GTA01Bv3_SYSTEM_REV:
8881 +               /* just use the default (GTA01_IRQ_PCF50606) */
8882 +               gta01_led_resources[0].start =
8883 +                       gta01_led_resources[0].end = GTA01Bv2_GPIO_VIBRATOR_ON;
8884 +               break;
8885 +       case GTA01Bv4_SYSTEM_REV:
8886 +               gta01_pmu_resources[0].start =
8887 +                       gta01_pmu_resources[0].end = GTA01Bv4_IRQ_PCF50606;
8888 +               gta01_led_resources[0].start =
8889 +                       gta01_led_resources[0].end = GTA01Bv4_GPIO_VIBRATOR_ON;
8890 +               break;
8891 +       }
8892 +       mangle_pmu_pdata_by_system_rev();
8893 +       platform_device_register(&gta01_pmu_dev);
8894 +       platform_device_register(&gta01_led_dev);
8895 +
8896 +       platform_add_devices(gta01_devices, ARRAY_SIZE(gta01_devices));
8897 +
8898 +       s3c2410_pm_init();
8899 +
8900 +       set_irq_type(GTA01_IRQ_MODEM, IRQ_TYPE_EDGE_RISING);
8901 +       rc = request_irq(GTA01_IRQ_MODEM, gta01_modem_irq, IRQF_DISABLED,
8902 +                        "modem", NULL);
8903 +       enable_irq_wake(GTA01_IRQ_MODEM);
8904 +       printk(KERN_DEBUG  "Enabled GSM wakeup IRQ %d (rc=%d)\n",
8905 +              GTA01_IRQ_MODEM, rc);
8906 +}
8907 +
8908 +MACHINE_START(NEO1973_GTA01, "GTA01")
8909 +       .phys_io        = S3C2410_PA_UART,
8910 +       .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
8911 +       .boot_params    = S3C2410_SDRAM_PA + 0x100,
8912 +       .map_io         = gta01_map_io,
8913 +       .init_irq       = s3c24xx_init_irq,
8914 +       .init_machine   = gta01_machine_init,
8915 +       .timer          = &s3c24xx_timer,
8916 +MACHINE_END
8917 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-h1940.c
8918 ===================================================================
8919 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-h1940.c        2008-12-25 00:26:37.000000000 +0100
8920 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-h1940.c     2009-01-02 00:01:56.000000000 +0100
8921 @@ -38,11 +38,13 @@
8922  #include <mach/h1940.h>
8923  #include <mach/h1940-latch.h>
8924  #include <mach/fb.h>
8925 -#include <asm/plat-s3c24xx/udc.h>
8926 +#include <plat/udc.h>
8927 +#include <plat/iic.h>
8928
8929  #include <plat/clock.h>
8930  #include <plat/devs.h>
8931  #include <plat/cpu.h>
8932 +#include <plat/pll.h>
8933  #include <plat/pm.h>
8934
8935  static struct map_desc h1940_iodesc[] __initdata = {
8936 @@ -129,6 +131,11 @@ static struct s3c2410_udc_mach_info h194
8937         .vbus_pin_inverted      = 1,
8938  };
8939
8940 +static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = {
8941 +               .delay = 10000,
8942 +               .presc = 49,
8943 +               .oversampling_shift = 2,
8944 +};
8945
8946  /**
8947   * Set lcd on or off
8948 @@ -183,9 +190,10 @@ static struct platform_device *h1940_dev
8949         &s3c_device_usb,
8950         &s3c_device_lcd,
8951         &s3c_device_wdt,
8952 -       &s3c_device_i2c,
8953 +       &s3c_device_i2c0,
8954         &s3c_device_iis,
8955         &s3c_device_usbgadget,
8956 +       &s3c_device_ts,
8957         &s3c_device_leds,
8958         &s3c_device_bluetooth,
8959  };
8960 @@ -201,7 +209,7 @@ static void __init h1940_map_io(void)
8961  #ifdef CONFIG_PM_H1940
8962         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
8963  #endif
8964 -       s3c2410_pm_init();
8965 +       s3c_pm_init();
8966  }
8967
8968  static void __init h1940_init_irq(void)
8969 @@ -214,7 +222,9 @@ static void __init h1940_init(void)
8970         u32 tmp;
8971
8972         s3c24xx_fb_set_platdata(&h1940_fb_info);
8973 +       set_s3c2410ts_info(&h1940_ts_cfg);
8974         s3c24xx_udc_set_platdata(&h1940_udc_cfg);
8975 +       s3c_i2c0_set_platdata(NULL);
8976
8977         /* Turn off suspend on both USB ports, and switch the
8978          * selectable USB port to USB device mode. */
8979 @@ -223,10 +233,9 @@ static void __init h1940_init(void)
8980                               S3C2410_MISCCR_USBSUSPND0 |
8981                               S3C2410_MISCCR_USBSUSPND1, 0x0);
8982
8983 -       tmp = (
8984 -                0x78 << S3C2410_PLLCON_MDIVSHIFT)
8985 -             | (0x02 << S3C2410_PLLCON_PDIVSHIFT)
8986 -             | (0x03 << S3C2410_PLLCON_SDIVSHIFT);
8987 +       tmp =   (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
8988 +             | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
8989 +             | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
8990         writel(tmp, S3C2410_UPLLCON);
8991
8992         platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
8993 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-n30.c
8994 ===================================================================
8995 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-n30.c  2008-12-25 00:26:37.000000000 +0100
8996 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-n30.c       2009-01-02 00:01:56.000000000 +0100
8997 @@ -40,14 +40,14 @@
8998  #include <asm/mach/irq.h>
8999  #include <asm/mach/map.h>
9000
9001 -#include <asm/plat-s3c/iic.h>
9002 +#include <plat/iic.h>
9003  #include <plat/regs-serial.h>
9004
9005  #include <plat/clock.h>
9006  #include <plat/cpu.h>
9007  #include <plat/devs.h>
9008  #include <plat/s3c2410.h>
9009 -#include <asm/plat-s3c24xx/udc.h>
9010 +#include <plat/udc.h>
9011
9012  static struct map_desc n30_iodesc[] __initdata = {
9013         /* nothing here yet */
9014 @@ -320,7 +320,7 @@ static struct s3c2410fb_mach_info n30_fb
9015  static struct platform_device *n30_devices[] __initdata = {
9016         &s3c_device_lcd,
9017         &s3c_device_wdt,
9018 -       &s3c_device_i2c,
9019 +       &s3c_device_i2c0,
9020         &s3c_device_iis,
9021         &s3c_device_usb,
9022         &s3c_device_usbgadget,
9023 @@ -332,7 +332,7 @@ static struct platform_device *n30_devic
9024  static struct platform_device *n35_devices[] __initdata = {
9025         &s3c_device_lcd,
9026         &s3c_device_wdt,
9027 -       &s3c_device_i2c,
9028 +       &s3c_device_i2c0,
9029         &s3c_device_iis,
9030         &s3c_device_usbgadget,
9031         &n35_button_device,
9032 @@ -501,7 +501,7 @@ static void __init n30_init_irq(void)
9033  static void __init n30_init(void)
9034  {
9035         s3c24xx_fb_set_platdata(&n30_fb_info);
9036 -       s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
9037 +       s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
9038         s3c24xx_udc_set_platdata(&n30_udc_cfg);
9039
9040         /* Turn off suspend on both USB ports, and switch the
9041 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-otom.c
9042 ===================================================================
9043 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-otom.c 2008-12-25 00:26:37.000000000 +0100
9044 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-otom.c      2009-01-02 00:01:56.000000000 +0100
9045 @@ -35,6 +35,7 @@
9046  #include <plat/s3c2410.h>
9047  #include <plat/clock.h>
9048  #include <plat/devs.h>
9049 +#include <plat/iic.h>
9050  #include <plat/cpu.h>
9051
9052  static struct map_desc otom11_iodesc[] __initdata = {
9053 @@ -94,7 +95,7 @@ static struct platform_device *otom11_de
9054         &s3c_device_usb,
9055         &s3c_device_lcd,
9056         &s3c_device_wdt,
9057 -       &s3c_device_i2c,
9058 +       &s3c_device_i2c0,
9059         &s3c_device_iis,
9060         &s3c_device_rtc,
9061         &otom_device_nor,
9062 @@ -109,6 +110,7 @@ static void __init otom11_map_io(void)
9063
9064  static void __init otom11_init(void)
9065  {
9066 +       s3c_i2c0_set_platdata(NULL);
9067         platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
9068  }
9069
9070 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-qt2410.c
9071 ===================================================================
9072 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-qt2410.c       2008-12-25 00:26:37.000000000 +0100
9073 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-qt2410.c    2009-01-02 00:01:56.000000000 +0100
9074 @@ -1,6 +1,6 @@
9075  /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
9076   *
9077 - * Copyright (C) 2006 by OpenMoko, Inc.
9078 + * Copyright (C) 2006 by Openmoko, Inc.
9079   * Author: Harald Welte <laforge@openmoko.org>
9080   * All rights reserved.
9081   *
9082 @@ -50,10 +50,11 @@
9083  #include <mach/leds-gpio.h>
9084  #include <plat/regs-serial.h>
9085  #include <mach/fb.h>
9086 -#include <asm/plat-s3c/nand.h>
9087 -#include <asm/plat-s3c24xx/udc.h>
9088 +#include <plat/nand.h>
9089 +#include <plat/udc.h>
9090  #include <mach/spi.h>
9091  #include <mach/spi-gpio.h>
9092 +#include <plat/iic.h>
9093
9094  #include <plat/common-smdk.h>
9095  #include <plat/devs.h>
9096 @@ -213,7 +214,7 @@ static struct platform_device qt2410_led
9097
9098  /* SPI */
9099
9100 -static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
9101 +static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int csidx, int cs)
9102  {
9103         switch (cs) {
9104         case BITBANG_CS_ACTIVE:
9105 @@ -247,7 +248,7 @@ static struct platform_device *qt2410_de
9106         &s3c_device_usb,
9107         &s3c_device_lcd,
9108         &s3c_device_wdt,
9109 -       &s3c_device_i2c,
9110 +       &s3c_device_i2c0,
9111         &s3c_device_iis,
9112         &s3c_device_sdi,
9113         &s3c_device_usbgadget,
9114 @@ -320,6 +321,24 @@ static int __init qt2410_tft_setup(char
9115
9116  __setup("tft=", qt2410_tft_setup);
9117
9118 +static struct resource qt2410_button_resources[] = {
9119 +       [0] = {
9120 +               .start = S3C2410_GPF0,
9121 +               .end   = S3C2410_GPF0,
9122 +       },
9123 +       [1] = {
9124 +               .start = S3C2410_GPF2,
9125 +               .end   = S3C2410_GPF2,
9126 +       },
9127 +};
9128 +
9129 +struct platform_device qt2410_button_dev = {
9130 +       .name           ="qt2410-button",
9131 +       .num_resources  = ARRAY_SIZE(qt2410_button_resources),
9132 +       .resource       = qt2410_button_resources,
9133 +};
9134 +
9135 +
9136  static void __init qt2410_map_io(void)
9137  {
9138         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
9139 @@ -349,11 +368,12 @@ static void __init qt2410_machine_init(v
9140         s3c2410_gpio_setpin(S3C2410_GPB0, 1);
9141
9142         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
9143 +       s3c_i2c0_set_platdata(NULL);
9144
9145         s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
9146
9147         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
9148 -       s3c2410_pm_init();
9149 +       s3c_pm_init();
9150  }
9151
9152  MACHINE_START(QT2410, "QT2410")
9153 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-smdk2410.c
9154 ===================================================================
9155 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-smdk2410.c     2008-12-25 00:26:37.000000000 +0100
9156 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-smdk2410.c  2009-01-02 00:01:56.000000000 +0100
9157 @@ -47,6 +47,7 @@
9158  #include <asm/mach-types.h>
9159
9160  #include <plat/regs-serial.h>
9161 +#include <plat/iic.h>
9162
9163  #include <plat/devs.h>
9164  #include <plat/cpu.h>
9165 @@ -89,7 +90,7 @@ static struct platform_device *smdk2410_
9166         &s3c_device_usb,
9167         &s3c_device_lcd,
9168         &s3c_device_wdt,
9169 -       &s3c_device_i2c,
9170 +       &s3c_device_i2c0,
9171         &s3c_device_iis,
9172  };
9173
9174 @@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void)
9175
9176  static void __init smdk2410_init(void)
9177  {
9178 +       s3c_i2c0_set_platdata(NULL);
9179         platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
9180         smdk_machine_init();
9181  }
9182 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-tct_hammer.c
9183 ===================================================================
9184 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-tct_hammer.c   2008-12-25 00:26:37.000000000 +0100
9185 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-tct_hammer.c        2009-01-02 00:01:56.000000000 +0100
9186 @@ -45,6 +45,7 @@
9187  #include <asm/mach-types.h>
9188
9189  #include <plat/regs-serial.h>
9190 +#include <plat/iic.h>
9191  #include <plat/devs.h>
9192  #include <plat/cpu.h>
9193
9194 @@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer
9195  static struct platform_device *tct_hammer_devices[] __initdata = {
9196         &s3c_device_adc,
9197         &s3c_device_wdt,
9198 -       &s3c_device_i2c,
9199 +       &s3c_device_i2c0,
9200         &s3c_device_usb,
9201         &s3c_device_rtc,
9202         &s3c_device_usbgadget,
9203 @@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(voi
9204
9205  static void __init tct_hammer_init(void)
9206  {
9207 +       s3c_i2c0_set_platdata(NULL);
9208         platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
9209  }
9210
9211 Index: linux-2.6.28/arch/arm/mach-s3c2410/mach-vr1000.c
9212 ===================================================================
9213 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/mach-vr1000.c       2008-12-25 00:26:37.000000000 +0100
9214 +++ linux-2.6.28/arch/arm/mach-s3c2410/mach-vr1000.c    2009-01-02 00:01:56.000000000 +0100
9215 @@ -47,6 +47,7 @@
9216  #include <plat/clock.h>
9217  #include <plat/devs.h>
9218  #include <plat/cpu.h>
9219 +#include <plat/iic.h>
9220
9221  #include "usb-simtec.h"
9222  #include "nor-simtec.h"
9223 @@ -334,7 +335,7 @@ static struct platform_device *vr1000_de
9224         &s3c_device_usb,
9225         &s3c_device_lcd,
9226         &s3c_device_wdt,
9227 -       &s3c_device_i2c,
9228 +       &s3c_device_i2c0,
9229         &s3c_device_adc,
9230         &serial_device,
9231         &vr1000_dm9k0,
9232 @@ -384,6 +385,7 @@ static void __init vr1000_map_io(void)
9233
9234  static void __init vr1000_init(void)
9235  {
9236 +       s3c_i2c0_set_platdata(NULL);
9237         platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
9238
9239         i2c_register_board_info(0, vr1000_i2c_devs,
9240 Index: linux-2.6.28/arch/arm/mach-s3c2410/Makefile
9241 ===================================================================
9242 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/Makefile    2008-12-25 00:26:37.000000000 +0100
9243 +++ linux-2.6.28/arch/arm/mach-s3c2410/Makefile 2009-01-02 00:01:56.000000000 +0100
9244 @@ -15,7 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
9245  obj-$(CONFIG_CPU_S3C2410_DMA)  += dma.o
9246  obj-$(CONFIG_S3C2410_PM)       += pm.o sleep.o
9247  obj-$(CONFIG_S3C2410_GPIO)     += gpio.o
9248 -obj-$(CONFIG_S3C2410_CLOCK)    += clock.o
9249 +#obj-$(CONFIG_S3C2410_CLOCK)   += clock.o
9250 +obj-$(CONFIG_S3C2410_PWM)      += pwm.o
9251
9252  # Machine support
9253
9254 @@ -38,3 +39,5 @@ obj-$(CONFIG_SIMTEC_NOR)      += nor-simtec.o
9255  # machine additions
9256
9257  obj-$(CONFIG_MACH_BAST_IDE)    += bast-ide.o
9258 +obj-$(CONFIG_MACH_NEO1973_GTA01)+= mach-gta01.o
9259 +
9260 Index: linux-2.6.28/arch/arm/mach-s3c2410/pm.c
9261 ===================================================================
9262 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/pm.c        2008-12-25 00:26:37.000000000 +0100
9263 +++ linux-2.6.28/arch/arm/mach-s3c2410/pm.c     2009-01-02 00:01:56.000000000 +0100
9264 @@ -37,21 +37,14 @@
9265  #include <plat/cpu.h>
9266  #include <plat/pm.h>
9267
9268 -#ifdef CONFIG_S3C2410_PM_DEBUG
9269 -extern void pm_dbg(const char *fmt, ...);
9270 -#define DBG(fmt...) pm_dbg(fmt)
9271 -#else
9272 -#define DBG(fmt...) printk(KERN_DEBUG fmt)
9273 -#endif
9274 -
9275  static void s3c2410_pm_prepare(void)
9276  {
9277         /* ensure at least GSTATUS3 has the resume address */
9278
9279 -       __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
9280 +       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
9281
9282 -       DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
9283 -       DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
9284 +       S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
9285 +       S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
9286
9287         if (machine_is_h1940()) {
9288                 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
9289 Index: linux-2.6.28/arch/arm/mach-s3c2410/pwm.c
9290 ===================================================================
9291 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
9292 +++ linux-2.6.28/arch/arm/mach-s3c2410/pwm.c    2009-01-02 00:01:56.000000000 +0100
9293 @@ -0,0 +1,288 @@
9294 +/*
9295 + * arch/arm/mach-s3c2410/3c2410-pwm.c
9296 + *
9297 + * Copyright (c) by Javi Roman <javiroman@kernel-labs.org>
9298 + *              for the Openmoko Project.
9299 + *
9300 + *     S3C2410A SoC PWM support
9301 + *
9302 + * This program is free software; you can redistribute it and/or modify
9303 + * it under the terms of the GNU General Public License as published by
9304 + * the Free Software Foundation; either version 2 of the License, or
9305 + * (at your option) any later version.
9306 + *
9307 + * You should have received a copy of the GNU General Public License
9308 + * along with this program; if not, write to the Free Software
9309 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
9310 + *
9311 + */
9312 +
9313 +#include <linux/kernel.h>
9314 +#include <linux/init.h>
9315 +#include <linux/clk.h>
9316 +#include <linux/device.h>
9317 +#include <mach/hardware.h>
9318 +#include <plat/regs-timer.h>
9319 +#include <mach/pwm.h>
9320 +#include <asm/io.h>
9321 +
9322 +#ifdef CONFIG_PM
9323 +       static unsigned long standby_reg_tcon;
9324 +       static unsigned long standby_reg_tcfg0;
9325 +       static unsigned long standby_reg_tcfg1;
9326 +#endif
9327 +
9328 +int s3c2410_pwm_disable(struct s3c2410_pwm *pwm)
9329 +{
9330 +       unsigned long tcon;
9331 +
9332 +       /* stop timer */
9333 +       tcon = __raw_readl(S3C2410_TCON);
9334 +       tcon &= 0xffffff00;
9335 +       __raw_writel(tcon, S3C2410_TCON);
9336 +
9337 +       clk_disable(pwm->pclk);
9338 +       clk_put(pwm->pclk);
9339 +
9340 +       return 0;
9341 +}
9342 +EXPORT_SYMBOL_GPL(s3c2410_pwm_disable);
9343 +
9344 +int s3c2410_pwm_init(struct s3c2410_pwm *pwm)
9345 +{
9346 +       pwm->pclk = clk_get(NULL, "timers");
9347 +       if (IS_ERR(pwm->pclk))
9348 +               return PTR_ERR(pwm->pclk);
9349 +
9350 +       clk_enable(pwm->pclk);
9351 +       pwm->pclk_rate = clk_get_rate(pwm->pclk);
9352 +       return 0;
9353 +}
9354 +EXPORT_SYMBOL_GPL(s3c2410_pwm_init);
9355 +
9356 +int s3c2410_pwm_enable(struct s3c2410_pwm *pwm)
9357 +{
9358 +       unsigned long tcfg0, tcfg1, tcnt, tcmp;
9359 +
9360 +       /* control registers bits */
9361 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
9362 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
9363 +
9364 +       /* divider & scaler slection */
9365 +       switch (pwm->timerid) {
9366 +       case PWM0:
9367 +               tcfg1 &= ~S3C2410_TCFG1_MUX0_MASK;
9368 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
9369 +               break;
9370 +       case PWM1:
9371 +               tcfg1 &= ~S3C2410_TCFG1_MUX1_MASK;
9372 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
9373 +               break;
9374 +       case PWM2:
9375 +               tcfg1 &= ~S3C2410_TCFG1_MUX2_MASK;
9376 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
9377 +               break;
9378 +       case PWM3:
9379 +               tcfg1 &= ~S3C2410_TCFG1_MUX3_MASK;
9380 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
9381 +               break;
9382 +       case PWM4:
9383 +               /* timer four is not capable of doing PWM */
9384 +               break;
9385 +       default:
9386 +               clk_disable(pwm->pclk);
9387 +               clk_put(pwm->pclk);
9388 +               return -1;
9389 +       }
9390 +
9391 +       /* divider & scaler values */
9392 +       tcfg1 |= pwm->divider;
9393 +       __raw_writel(tcfg1, S3C2410_TCFG1);
9394 +
9395 +       switch (pwm->timerid) {
9396 +       case PWM0:
9397 +       case PWM1:
9398 +               tcfg0 |= pwm->prescaler;
9399 +               __raw_writel(tcfg0, S3C2410_TCFG0);
9400 +               break;
9401 +       default:
9402 +               if ((tcfg0 | pwm->prescaler) != tcfg0) {
9403 +                       printk(KERN_WARNING "not changing prescaler of PWM %u,"
9404 +                              " since it's shared with timer4 (clock tick)\n",
9405 +                              pwm->timerid);
9406 +               }
9407 +               break;
9408 +       }
9409 +
9410 +       /* timer count and compare buffer initial values */
9411 +       tcnt = pwm->counter;
9412 +       tcmp = pwm->comparer;
9413 +
9414 +       __raw_writel(tcnt, S3C2410_TCNTB(pwm->timerid));
9415 +       __raw_writel(tcmp, S3C2410_TCMPB(pwm->timerid));
9416 +
9417 +       /* ensure timer is stopped */
9418 +       s3c2410_pwm_stop(pwm);
9419 +
9420 +       return 0;
9421 +}
9422 +EXPORT_SYMBOL_GPL(s3c2410_pwm_enable);
9423 +
9424 +int s3c2410_pwm_start(struct s3c2410_pwm *pwm)
9425 +{
9426 +       unsigned long tcon;
9427 +
9428 +       tcon = __raw_readl(S3C2410_TCON);
9429 +
9430 +       switch (pwm->timerid) {
9431 +       case PWM0:
9432 +               tcon |= S3C2410_TCON_T0START;
9433 +               tcon &= ~S3C2410_TCON_T0MANUALUPD;
9434 +               break;
9435 +       case PWM1:
9436 +               tcon |= S3C2410_TCON_T1START;
9437 +               tcon &= ~S3C2410_TCON_T1MANUALUPD;
9438 +               break;
9439 +       case PWM2:
9440 +               tcon |= S3C2410_TCON_T2START;
9441 +               tcon &= ~S3C2410_TCON_T2MANUALUPD;
9442 +               break;
9443 +       case PWM3:
9444 +               tcon |= S3C2410_TCON_T3START;
9445 +               tcon &= ~S3C2410_TCON_T3MANUALUPD;
9446 +               break;
9447 +       case PWM4:
9448 +               /* timer four is not capable of doing PWM */
9449 +       default:
9450 +               return -ENODEV;
9451 +       }
9452 +
9453 +       __raw_writel(tcon, S3C2410_TCON);
9454 +
9455 +       return 0;
9456 +}
9457 +EXPORT_SYMBOL_GPL(s3c2410_pwm_start);
9458 +
9459 +int s3c2410_pwm_stop(struct s3c2410_pwm *pwm)
9460 +{
9461 +       unsigned long tcon;
9462 +
9463 +       tcon = __raw_readl(S3C2410_TCON);
9464 +
9465 +       switch (pwm->timerid) {
9466 +       case PWM0:
9467 +               tcon &= ~0x00000000;
9468 +               tcon |= S3C2410_TCON_T0RELOAD;
9469 +               tcon |= S3C2410_TCON_T0MANUALUPD;
9470 +               break;
9471 +       case PWM1:
9472 +               tcon &= ~0x00000080;
9473 +               tcon |= S3C2410_TCON_T1RELOAD;
9474 +               tcon |= S3C2410_TCON_T1MANUALUPD;
9475 +               break;
9476 +       case PWM2:
9477 +               tcon &= ~0x00000800;
9478 +               tcon |= S3C2410_TCON_T2RELOAD;
9479 +               tcon |= S3C2410_TCON_T2MANUALUPD;
9480 +               break;
9481 +       case PWM3:
9482 +               tcon &= ~0x00008000;
9483 +               tcon |= S3C2410_TCON_T3RELOAD;
9484 +               tcon |= S3C2410_TCON_T3MANUALUPD;
9485 +               break;
9486 +       case PWM4:
9487 +               /* timer four is not capable of doing PWM */
9488 +       default:
9489 +               return -ENODEV;
9490 +       }
9491 +
9492 +       __raw_writel(tcon, S3C2410_TCON);
9493 +
9494 +       return 0;
9495 +}
9496 +EXPORT_SYMBOL_GPL(s3c2410_pwm_stop);
9497 +
9498 +int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *pwm)
9499 +{
9500 +       __raw_writel(reg_value, S3C2410_TCMPB(pwm->timerid));
9501 +
9502 +       return 0;
9503 +}
9504 +EXPORT_SYMBOL_GPL(s3c2410_pwm_duty_cycle);
9505 +
9506 +int s3c2410_pwm_dumpregs(void)
9507 +{
9508 +       printk(KERN_INFO "TCON: %08lx, TCFG0: %08lx, TCFG1: %08lx\n",
9509 +                       (unsigned long) __raw_readl(S3C2410_TCON),
9510 +                       (unsigned long) __raw_readl(S3C2410_TCFG0),
9511 +                       (unsigned long) __raw_readl(S3C2410_TCFG1));
9512 +
9513 +       return 0;
9514 +}
9515 +EXPORT_SYMBOL_GPL(s3c2410_pwm_dumpregs);
9516 +
9517 +static int __init s3c24xx_pwm_probe(struct platform_device *pdev)
9518 +{
9519 +       struct s3c24xx_pwm_platform_data *pdata = pdev->dev.platform_data;
9520 +
9521 +       dev_info(&pdev->dev, "s3c24xx_pwm is registered \n");
9522 +
9523 +       /* if platform was interested, give him a chance to register
9524 +        * platform devices that switch power with us as the parent
9525 +        * at registration time -- ensures suspend / resume ordering
9526 +        */
9527 +       if (pdata)
9528 +               if (pdata->attach_child_devices)
9529 +                       (pdata->attach_child_devices)(&pdev->dev);
9530 +
9531 +       return 0;
9532 +}
9533 +
9534 +#ifdef CONFIG_PM
9535 +static int s3c24xx_pwm_suspend(struct platform_device *pdev, pm_message_t state)
9536 +{
9537 +       /* PWM config should be kept in suspending */
9538 +       standby_reg_tcon = __raw_readl(S3C2410_TCON);
9539 +       standby_reg_tcfg0 = __raw_readl(S3C2410_TCFG0);
9540 +       standby_reg_tcfg1 = __raw_readl(S3C2410_TCFG1);
9541 +
9542 +       return 0;
9543 +}
9544 +
9545 +static int s3c24xx_pwm_resume(struct platform_device *pdev)
9546 +{
9547 +       __raw_writel(standby_reg_tcon, S3C2410_TCON);
9548 +       __raw_writel(standby_reg_tcfg0, S3C2410_TCFG0);
9549 +       __raw_writel(standby_reg_tcfg1, S3C2410_TCFG1);
9550 +
9551 +       return 0;
9552 +}
9553 +#else
9554 +#define sc32440_pwm_suspend    NULL
9555 +#define sc32440_pwm_resume     NULL
9556 +#endif
9557 +
9558 +static struct platform_driver s3c24xx_pwm_driver = {
9559 +       .driver = {
9560 +               .name   = "s3c24xx_pwm",
9561 +               .owner  = THIS_MODULE,
9562 +       },
9563 +       .probe   = s3c24xx_pwm_probe,
9564 +       .suspend = s3c24xx_pwm_suspend,
9565 +       .resume  = s3c24xx_pwm_resume,
9566 +};
9567 +
9568 +static int __init s3c24xx_pwm_init(void)
9569 +{
9570 +       return platform_driver_register(&s3c24xx_pwm_driver);
9571 +}
9572 +
9573 +static void __exit s3c24xx_pwm_exit(void)
9574 +{
9575 +}
9576 +
9577 +MODULE_AUTHOR("Javi Roman <javiroman@kernel-labs.org>");
9578 +MODULE_LICENSE("GPL");
9579 +
9580 +module_init(s3c24xx_pwm_init);
9581 +module_exit(s3c24xx_pwm_exit);
9582 Index: linux-2.6.28/arch/arm/mach-s3c2410/s3c2410.c
9583 ===================================================================
9584 --- linux-2.6.28.orig/arch/arm/mach-s3c2410/s3c2410.c   2008-12-25 00:26:37.000000000 +0100
9585 +++ linux-2.6.28/arch/arm/mach-s3c2410/s3c2410.c        2009-01-02 00:01:56.000000000 +0100
9586 @@ -16,6 +16,7 @@
9587  #include <linux/list.h>
9588  #include <linux/timer.h>
9589  #include <linux/init.h>
9590 +#include <linux/clk.h>
9591  #include <linux/sysdev.h>
9592  #include <linux/serial_core.h>
9593  #include <linux/platform_device.h>
9594 @@ -28,6 +29,8 @@
9595  #include <mach/hardware.h>
9596  #include <asm/irq.h>
9597
9598 +#include <plat/cpu-freq.h>
9599 +
9600  #include <mach/regs-clock.h>
9601  #include <plat/regs-serial.h>
9602
9603 @@ -35,6 +38,7 @@
9604  #include <plat/cpu.h>
9605  #include <plat/devs.h>
9606  #include <plat/clock.h>
9607 +#include <plat/pll.h>
9608
9609  /* Initial IO mappings */
9610
9611 @@ -59,25 +63,28 @@ void __init s3c2410_init_uarts(struct s3
9612   * machine specific initialisation.
9613  */
9614
9615 -void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size)
9616 +void __init s3c2410_map_io(void)
9617  {
9618 -       /* register our io-tables */
9619 -
9620         iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
9621 -       iotable_init(mach_desc, mach_size);
9622  }
9623
9624 -void __init s3c2410_init_clocks(int xtal)
9625 +void __init_or_cpufreq s3c2410_setup_clocks(void)
9626  {
9627 +       struct clk *xtal_clk;
9628         unsigned long tmp;
9629 +       unsigned long xtal;
9630         unsigned long fclk;
9631         unsigned long hclk;
9632         unsigned long pclk;
9633
9634 +       xtal_clk = clk_get(NULL, "xtal");
9635 +       xtal = clk_get_rate(xtal_clk);
9636 +       clk_put(xtal_clk);
9637 +
9638         /* now we've got our machine bits initialised, work out what
9639          * clocks we've got */
9640
9641 -       fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
9642 +       fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
9643
9644         tmp = __raw_readl(S3C2410_CLKDIVN);
9645
9646 @@ -95,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal
9647          * console to use them
9648          */
9649
9650 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
9651 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
9652 +}
9653 +
9654 +void __init s3c2410_init_clocks(int xtal)
9655 +{
9656 +       s3c24xx_register_baseclocks(xtal);
9657 +       s3c2410_setup_clocks();
9658         s3c2410_baseclk_add();
9659  }
9660
9661 Index: linux-2.6.28/arch/arm/mach-s3c2412/clock.c
9662 ===================================================================
9663 --- linux-2.6.28.orig/arch/arm/mach-s3c2412/clock.c     2008-12-25 00:26:37.000000000 +0100
9664 +++ linux-2.6.28/arch/arm/mach-s3c2412/clock.c  2009-01-02 00:01:56.000000000 +0100
9665 @@ -93,12 +93,6 @@ static int s3c2412_upll_enable(struct cl
9666
9667  /* clock selections */
9668
9669 -/* CPU EXTCLK input */
9670 -static struct clk clk_ext = {
9671 -       .name           = "extclk",
9672 -       .id             = -1,
9673 -};
9674 -
9675  static struct clk clk_erefclk = {
9676         .name           = "erefclk",
9677         .id             = -1,
9678 @@ -773,5 +767,6 @@ int __init s3c2412_baseclk_add(void)
9679                 s3c2412_clkcon_enable(clkp, 0);
9680         }
9681
9682 +       s3c_pwmclk_init();
9683         return 0;
9684  }
9685 Index: linux-2.6.28/arch/arm/mach-s3c2412/dma.c
9686 ===================================================================
9687 --- linux-2.6.28.orig/arch/arm/mach-s3c2412/dma.c       2008-12-25 00:26:37.000000000 +0100
9688 +++ linux-2.6.28/arch/arm/mach-s3c2412/dma.c    2009-01-02 00:01:56.000000000 +0100
9689 @@ -26,13 +26,13 @@
9690
9691  #include <plat/regs-serial.h>
9692  #include <mach/regs-gpio.h>
9693 -#include <asm/plat-s3c/regs-ac97.h>
9694 +#include <plat/regs-ac97.h>
9695  #include <mach/regs-mem.h>
9696  #include <mach/regs-lcd.h>
9697  #include <mach/regs-sdi.h>
9698  #include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
9699  #include <asm/plat-s3c24xx/regs-iis.h>
9700 -#include <asm/plat-s3c24xx/regs-spi.h>
9701 +#include <plat/regs-spi.h>
9702
9703  #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
9704
9705 Index: linux-2.6.28/arch/arm/mach-s3c2412/mach-jive.c
9706 ===================================================================
9707 --- linux-2.6.28.orig/arch/arm/mach-s3c2412/mach-jive.c 2008-12-25 00:26:37.000000000 +0100
9708 +++ linux-2.6.28/arch/arm/mach-s3c2412/mach-jive.c      2009-01-02 00:01:56.000000000 +0100
9709 @@ -31,8 +31,8 @@
9710  #include <asm/mach/irq.h>
9711
9712  #include <plat/regs-serial.h>
9713 -#include <asm/plat-s3c/nand.h>
9714 -#include <asm/plat-s3c/iic.h>
9715 +#include <plat/nand.h>
9716 +#include <plat/iic.h>
9717
9718  #include <mach/regs-power.h>
9719  #include <mach/regs-gpio.h>
9720 @@ -52,7 +52,8 @@
9721  #include <plat/devs.h>
9722  #include <plat/cpu.h>
9723  #include <plat/pm.h>
9724 -#include <asm/plat-s3c24xx/udc.h>
9725 +#include <plat/udc.h>
9726 +#include <plat/iic.h>
9727
9728  static struct map_desc jive_iodesc[] __initdata = {
9729  };
9730 @@ -450,14 +451,14 @@ static struct spi_board_info __initdata
9731
9732  /* I2C bus and device configuration. */
9733
9734 -static struct s3c2410_platform_i2c jive_i2c_cfg = {
9735 +static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
9736         .max_freq       = 80 * 1000,
9737         .bus_freq       = 50 * 1000,
9738         .flags          = S3C_IICFLG_FILTER,
9739         .sda_delay      = 2,
9740  };
9741
9742 -static struct i2c_board_info jive_i2c_devs[] = {
9743 +static struct i2c_board_info jive_i2c_devs[] __initdata = {
9744         [0] = {
9745                 I2C_BOARD_INFO("lis302dl", 0x1c),
9746                 .irq    = IRQ_EINT14,
9747 @@ -470,7 +471,7 @@ static struct platform_device *jive_devi
9748         &s3c_device_usb,
9749         &s3c_device_rtc,
9750         &s3c_device_wdt,
9751 -       &s3c_device_i2c,
9752 +       &s3c_device_i2c0,
9753         &s3c_device_lcd,
9754         &jive_device_lcdspi,
9755         &jive_device_wm8750,
9756 @@ -492,7 +493,7 @@ static int jive_pm_suspend(struct sys_de
9757          * correct address to resume from. */
9758
9759         __raw_writel(0x2BED, S3C2412_INFORM0);
9760 -       __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
9761 +       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
9762
9763         return 0;
9764  }
9765 @@ -628,7 +629,7 @@ static void __init jive_machine_init(voi
9766
9767         /* initialise the power management now we've setup everything. */
9768
9769 -       s3c2410_pm_init();
9770 +       s3c_pm_init();
9771
9772         s3c_device_nand.dev.platform_data = &jive_nand_info;
9773
9774 @@ -663,7 +664,7 @@ static void __init jive_machine_init(voi
9775
9776         spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
9777
9778 -       s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
9779 +       s3c_i2c0_set_platdata(&jive_i2c_cfg);
9780         i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
9781
9782         pm_power_off = jive_power_off;
9783 Index: linux-2.6.28/arch/arm/mach-s3c2412/mach-smdk2413.c
9784 ===================================================================
9785 --- linux-2.6.28.orig/arch/arm/mach-s3c2412/mach-smdk2413.c     2008-12-25 00:26:37.000000000 +0100
9786 +++ linux-2.6.28/arch/arm/mach-s3c2412/mach-smdk2413.c  2009-01-02 00:01:56.000000000 +0100
9787 @@ -37,7 +37,8 @@
9788  #include <mach/regs-lcd.h>
9789
9790  #include <mach/idle.h>
9791 -#include <asm/plat-s3c24xx/udc.h>
9792 +#include <plat/udc.h>
9793 +#include <plat/iic.h>
9794  #include <mach/fb.h>
9795
9796  #include <plat/s3c2410.h>
9797 @@ -105,7 +106,7 @@ static struct platform_device *smdk2413_
9798         &s3c_device_usb,
9799         //&s3c_device_lcd,
9800         &s3c_device_wdt,
9801 -       &s3c_device_i2c,
9802 +       &s3c_device_i2c0,
9803         &s3c_device_iis,
9804         &s3c_device_usbgadget,
9805  };
9806 @@ -142,6 +143,7 @@ static void __init smdk2413_machine_init
9807
9808
9809         s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
9810 +       s3c_i2c0_set_platdata(NULL);
9811
9812         platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
9813         smdk_machine_init();
9814 Index: linux-2.6.28/arch/arm/mach-s3c2412/mach-vstms.c
9815 ===================================================================
9816 --- linux-2.6.28.orig/arch/arm/mach-s3c2412/mach-vstms.c        2008-12-25 00:26:37.000000000 +0100
9817 +++ linux-2.6.28/arch/arm/mach-s3c2412/mach-vstms.c     2009-01-02 00:01:56.000000000 +0100
9818 @@ -39,7 +39,8 @@
9819  #include <mach/idle.h>
9820  #include <mach/fb.h>
9821
9822 -#include <asm/plat-s3c/nand.h>
9823 +#include <plat/iic.h>
9824 +#include <plat/nand.h>
9825
9826  #include <plat/s3c2410.h>
9827  #include <plat/s3c2412.h>
9828 @@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstm
9829  static struct platform_device *vstms_devices[] __initdata = {
9830         &s3c_device_usb,
9831         &s3c_device_wdt,
9832 -       &s3c_device_i2c,
9833 +       &s3c_device_i2c0,
9834         &s3c_device_iis,
9835         &s3c_device_rtc,
9836         &s3c_device_nand,
9837 @@ -151,6 +152,7 @@ static void __init vstms_map_io(void)
9838
9839  static void __init vstms_init(void)
9840  {
9841 +       s3c_i2c0_set_platdata(NULL);
9842         platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
9843  }
9844
9845 Index: linux-2.6.28/arch/arm/mach-s3c2412/pm.c
9846 ===================================================================
9847 --- linux-2.6.28.orig/arch/arm/mach-s3c2412/pm.c        2008-12-25 00:26:37.000000000 +0100
9848 +++ linux-2.6.28/arch/arm/mach-s3c2412/pm.c     2009-01-02 00:01:56.000000000 +0100
9849 @@ -85,7 +85,7 @@ static struct sleep_save s3c2412_sleep[]
9850
9851  static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state)
9852  {
9853 -       s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9854 +       s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9855         return 0;
9856  }
9857
9858 @@ -98,7 +98,7 @@ static int s3c2412_pm_resume(struct sys_
9859         tmp |=  S3C2412_PWRCFG_STANDBYWFI_IDLE;
9860         __raw_writel(tmp, S3C2412_PWRCFG);
9861
9862 -       s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9863 +       s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
9864         return 0;
9865  }
9866
9867 Index: linux-2.6.28/arch/arm/mach-s3c2412/s3c2412.c
9868 ===================================================================
9869 --- linux-2.6.28.orig/arch/arm/mach-s3c2412/s3c2412.c   2008-12-25 00:26:37.000000000 +0100
9870 +++ linux-2.6.28/arch/arm/mach-s3c2412/s3c2412.c        2009-01-02 00:01:56.000000000 +0100
9871 @@ -16,6 +16,7 @@
9872  #include <linux/list.h>
9873  #include <linux/timer.h>
9874  #include <linux/init.h>
9875 +#include <linux/clk.h>
9876  #include <linux/delay.h>
9877  #include <linux/sysdev.h>
9878  #include <linux/serial_core.h>
9879 @@ -33,13 +34,15 @@
9880  #include <mach/reset.h>
9881  #include <mach/idle.h>
9882
9883 +#include <plat/cpu-freq.h>
9884 +
9885  #include <mach/regs-clock.h>
9886  #include <plat/regs-serial.h>
9887  #include <mach/regs-power.h>
9888  #include <mach/regs-gpio.h>
9889  #include <mach/regs-gpioj.h>
9890  #include <mach/regs-dsc.h>
9891 -#include <asm/plat-s3c24xx/regs-spi.h>
9892 +#include <plat/regs-spi.h>
9893  #include <mach/regs-s3c2412.h>
9894
9895  #include <plat/s3c2412.h>
9896 @@ -47,6 +50,7 @@
9897  #include <plat/devs.h>
9898  #include <plat/clock.h>
9899  #include <plat/pm.h>
9900 +#include <plat/pll.h>
9901
9902  #ifndef CONFIG_CPU_S3C2412_ONLY
9903  void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
9904 @@ -136,7 +140,7 @@ static void s3c2412_hard_reset(void)
9905   * machine specific initialisation.
9906  */
9907
9908 -void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
9909 +void __init s3c2412_map_io(void)
9910  {
9911         /* move base of IO */
9912
9913 @@ -153,20 +157,25 @@ void __init s3c2412_map_io(struct map_de
9914         /* register our io-tables */
9915
9916         iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
9917 -       iotable_init(mach_desc, mach_size);
9918  }
9919
9920 -void __init s3c2412_init_clocks(int xtal)
9921 +void __init_or_cpufreq s3c2412_setup_clocks(void)
9922  {
9923 +       struct clk *xtal_clk;
9924         unsigned long tmp;
9925 +       unsigned long xtal;
9926         unsigned long fclk;
9927         unsigned long hclk;
9928         unsigned long pclk;
9929
9930 +       xtal_clk = clk_get(NULL, "xtal");
9931 +       xtal = clk_get_rate(xtal_clk);
9932 +       clk_put(xtal_clk);
9933 +
9934         /* now we've got our machine bits initialised, work out what
9935          * clocks we've got */
9936
9937 -       fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
9938 +       fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
9939
9940         clk_mpll.rate = fclk;
9941
9942 @@ -183,11 +192,17 @@ void __init s3c2412_init_clocks(int xtal
9943         printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
9944                print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
9945
9946 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
9947 +}
9948 +
9949 +void __init s3c2412_init_clocks(int xtal)
9950 +{
9951         /* initialise the clocks here, to allow other things like the
9952          * console to use them
9953          */
9954
9955 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
9956 +       s3c24xx_register_baseclocks(xtal);
9957 +       s3c2412_setup_clocks();
9958         s3c2412_baseclk_add();
9959  }
9960
9961 @@ -216,5 +231,8 @@ int __init s3c2412_init(void)
9962  {
9963         printk("S3C2412: Initialising architecture\n");
9964
9965 +       /* make sure SD/MMC driver can distinguish 2412 from 2410 */
9966 +       s3c_device_sdi.name = "s3c2412-sdi";
9967 +
9968         return sysdev_register(&s3c2412_sysdev);
9969  }
9970 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/bits.h
9971 ===================================================================
9972 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
9973 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/bits.h    2009-01-02 00:01:56.000000000 +0100
9974 @@ -0,0 +1,48 @@
9975 +/*
9976 + *  Copyright (C) Samsung Electroincs  2003
9977 + *  Author: SW.LEE <hitchcar@samsung.com>
9978 + *
9979 + * This program is free software; you can redistribute it and/or modify
9980 + * it under the terms of the GNU General Public License as published by
9981 + * the Free Software Foundation; either version 2 of the License, or
9982 + * (at your option) any later version.
9983 + *
9984 + */
9985 +
9986 +#ifndef __SW_BITS_H
9987 +#define __SW_BITS_H
9988 +
9989 +#define BIT0                            0x00000001
9990 +#define BIT1                            0x00000002
9991 +#define BIT2                            0x00000004
9992 +#define BIT3                            0x00000008
9993 +#define BIT4                            0x00000010
9994 +#define BIT5                            0x00000020
9995 +#define BIT6                            0x00000040
9996 +#define BIT7                            0x00000080
9997 +#define BIT8                            0x00000100
9998 +#define BIT9                            0x00000200
9999 +#define BIT10                           0x00000400
10000 +#define BIT11                           0x00000800
10001 +#define BIT12                           0x00001000
10002 +#define BIT13                           0x00002000
10003 +#define BIT14                           0x00004000
10004 +#define BIT15                           0x00008000
10005 +#define BIT16                           0x00010000
10006 +#define BIT17                           0x00020000
10007 +#define BIT18                           0x00040000
10008 +#define BIT19                           0x00080000
10009 +#define BIT20                           0x00100000
10010 +#define BIT21                           0x00200000
10011 +#define BIT22                           0x00400000
10012 +#define BIT23                           0x00800000
10013 +#define BIT24                           0x01000000
10014 +#define BIT25                           0x02000000
10015 +#define BIT26                           0x04000000
10016 +#define BIT27                           0x08000000
10017 +#define BIT28                           0x10000000
10018 +#define BIT29                           0x20000000
10019 +#define BIT30                           0x40000000
10020 +#define BIT31                           0x80000000
10021 +
10022 +#endif
10023 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/camif.c
10024 ===================================================================
10025 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
10026 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/camif.c   2009-01-02 00:01:56.000000000 +0100
10027 @@ -0,0 +1,1047 @@
10028 +/*
10029 + *   Copyright (C) 2004 Samsung Electronics
10030 + *       SW.LEE <hitchcar@samsung.com>
10031 + *
10032 + * This file is subject to the terms and conditions of the GNU General Public
10033 + * License 2. See the file COPYING in the main directory of this archive
10034 + * for more details.
10035 + */
10036 +
10037 +#include <linux/module.h>
10038 +#include <linux/kernel.h>
10039 +#include <linux/init.h>
10040 +#include <linux/sched.h>
10041 +#include <linux/irq.h>
10042 +#include <linux/completion.h>
10043 +#include <linux/delay.h>
10044 +#include <linux/slab.h>
10045 +#include <linux/vmalloc.h>
10046 +#include <linux/miscdevice.h>
10047 +#include <linux/wait.h>
10048 +#include <linux/miscdevice.h>
10049 +#include <asm/io.h>
10050 +#include <asm/semaphore.h>
10051 +#include <asm/hardware.h>
10052 +#include <asm/uaccess.h>
10053 +#include <linux/device.h>
10054 +#include <linux/dma-mapping.h>
10055 +#include <linux/clk.h>
10056 +
10057 +#ifdef CONFIG_ARCH_S3C24A0A
10058 +#include <asm/arch/S3C24A0.h>
10059 +#include <asm/arch/clocks.h>
10060 +#else
10061 +#include <asm/arch/regs-gpio.h>
10062 +#include <asm/arch/regs-gpioj.h>
10063 +#include <asm/arch/regs-irq.h>
10064 +#endif
10065 +
10066 +#include "cam_reg.h"
10067 +//#define SW_DEBUG
10068 +#define CONFIG_VIDEO_V4L1_COMPAT
10069 +#include <linux/videodev.h>
10070 +#include "camif.h"
10071 +#include "miscdevice.h"
10072 +
10073 +static int camif_dma_burst(camif_cfg_t *);
10074 +static int camif_scaler(camif_cfg_t *);
10075 +
10076 +/* For SXGA Image */
10077 +#define RESERVE_MEM  15*1024*1024
10078 +#define YUV_MEM      10*1024*1024
10079 +#define RGB_MEM      (RESERVE_MEM - YUV_MEM)
10080 +
10081 +static int camif_malloc(camif_cfg_t *cfg)
10082 +{
10083 +       unsigned int t_size;
10084 +       unsigned int daon = cfg->target_x *cfg->target_y;
10085 +
10086 +       if(cfg->dma_type & CAMIF_CODEC) {
10087 +               if (cfg->fmt & CAMIF_OUT_YCBCR420) {
10088 +                       t_size = daon * 3 / 2 ;
10089 +               }
10090 +               else  { t_size = daon * 2; /* CAMIF_OUT_YCBCR422 */ }
10091 +               t_size = t_size *cfg->pp_num;
10092 +
10093 +#ifndef SAMSUNG_SXGA_CAM
10094 +               cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
10095 +                                                     t_size, &cfg->pp_phys_buf,
10096 +                                                     GFP_KERNEL);
10097 +#else
10098 +               printk(KERN_INFO "Reserving High RAM Addresses \n");
10099 +               cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM);
10100 +               cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf, YUV_MEM);
10101 +#endif
10102 +
10103 +               if ( !cfg->pp_virt_buf ) {
10104 +                       printk(KERN_ERR"CAMERA:Failed to request YCBCR MEM\n");
10105 +                       return -ENOMEM;
10106 +               }
10107 +               memset(cfg->pp_virt_buf, 0, t_size);
10108 +               cfg->pp_totalsize = t_size;
10109 +               return 0;
10110 +       }
10111 +       if ( cfg->dma_type & CAMIF_PREVIEW ) {
10112 +               if (cfg->fmt & CAMIF_RGB16)
10113 +                       t_size = daon * 2; /*  4byte per two pixel*/
10114 +               else {
10115 +                       assert(cfg->fmt & CAMIF_RGB24);
10116 +                       t_size = daon * 4; /* 4byte per one pixel */
10117 +               }
10118 +               t_size = t_size * cfg->pp_num;
10119 +#ifndef SAMSUNG_SXGA_CAM
10120 +               cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
10121 +                                                     t_size, &cfg->pp_phys_buf,
10122 +                                                     GFP_KERNEL);
10123 +#else
10124 +               printk(KERN_INFO "Reserving High RAM Addresses \n");
10125 +               cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM ) + YUV_MEM;
10126 +               cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf,RGB_MEM);
10127 +#endif
10128 +               if ( !cfg->pp_virt_buf ) {
10129 +                       printk(KERN_ERR"CAMERA:Failed to request RGB MEM\n");
10130 +                       return -ENOMEM;
10131 +               }
10132 +               memset(cfg->pp_virt_buf, 0, t_size);
10133 +               cfg->pp_totalsize = t_size;
10134 +               return 0;
10135 +       }
10136 +
10137 +       return 0;               /* Never come. */
10138 +}
10139 +
10140 +static int camif_demalloc(camif_cfg_t *cfg)
10141 +{
10142 +#ifndef SAMSUNG_SXGA_CAM
10143 +       if ( cfg->pp_virt_buf ) {
10144 +               dma_free_coherent(cfg->v->dev, cfg->pp_totalsize,
10145 +                                 cfg->pp_virt_buf, cfg->pp_phys_buf);
10146 +               cfg->pp_virt_buf = 0;
10147 +       }
10148 +#else
10149 +       iounmap(cfg->pp_virt_buf);
10150 +       cfg->pp_virt_buf = 0;
10151 +#endif
10152 +       return 0;
10153 +}
10154 +
10155 +/*
10156 + * advise a person to use this func in ISR
10157 + * index value indicates the next frame count to be used
10158 + */
10159 +int camif_g_frame_num(camif_cfg_t *cfg)
10160 +{
10161 +       int index = 0;
10162 +
10163 +       if (cfg->dma_type & CAMIF_CODEC ) {
10164 +               index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
10165 +               DPRINTK("CAMIF_CODEC frame %d \n", index);
10166 +       }
10167 +       else {
10168 +               assert(cfg->dma_type & CAMIF_PREVIEW );
10169 +               index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
10170 +               DPRINTK("CAMIF_PREVIEW frame %d  0x%08X \n", index,
10171 +                       readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
10172 +       }
10173 +       cfg->now_frame_num = (index + 2) % 4; /* When 4 PingPong */
10174 +       return index; /* meaningless */
10175 +}
10176 +
10177 +static int camif_pp_codec(camif_cfg_t *cfg)
10178 +{
10179 +       u32 i, c_size; /* Cb,Cr size */
10180 +       u32 one_p_size;
10181 +       u32 daon = cfg->target_x * cfg->target_y;
10182 +       if (cfg->fmt & CAMIF_OUT_YCBCR420)
10183 +               c_size = daon / 4;
10184 +       else {
10185 +               assert(cfg->fmt & CAMIF_OUT_YCBCR422);
10186 +               c_size = daon / 2;
10187 +       }
10188 +       switch ( cfg->pp_num ) {
10189 +       case 1 :
10190 +               for (i =0 ; i < 4; i++) {
10191 +                       cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
10192 +                       cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
10193 +                       cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon;
10194 +                       cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon;
10195 +                       cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size;
10196 +                       cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size;
10197 +                       writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
10198 +                       writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
10199 +                       writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10200 +               }
10201 +               break;
10202 +       case 2:
10203 +#define  TRY   (( i%2 ) ? 1 :0)
10204 +               one_p_size = daon + 2*c_size;
10205 +               for (i = 0; i < 4  ; i++) {
10206 +                       cfg->img_buf[i].virt_y = cfg->pp_virt_buf + TRY * one_p_size;
10207 +                       cfg->img_buf[i].phys_y = cfg->pp_phys_buf + TRY * one_p_size;
10208 +                       cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + TRY * one_p_size;
10209 +                       cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + TRY * one_p_size;
10210 +                       cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + TRY * one_p_size;
10211 +                       cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + TRY * one_p_size;
10212 +                       writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
10213 +                       writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
10214 +                       writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10215 +               }
10216 +               break;
10217 +       case 4:
10218 +               one_p_size = daon + 2*c_size;
10219 +               for (i = 0; i < 4 ; i++) {
10220 +                       cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
10221 +                       cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
10222 +                       cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + i * one_p_size;
10223 +                       cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + i * one_p_size;
10224 +                       cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + i * one_p_size;
10225 +                       cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + i * one_p_size;
10226 +                       writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
10227 +                       writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
10228 +                       writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10229 +               }
10230 +               break;
10231 +       default:
10232 +               printk("Invalid PingPong Number %d \n",cfg->pp_num);
10233 +               panic("halt\n");
10234 +}
10235 +       return 0;
10236 +}
10237 +
10238 +/* RGB Buffer Allocation */
10239 +static int camif_pp_preview(camif_cfg_t *cfg)
10240 +{
10241 +       int i;
10242 +       u32 daon = cfg->target_x * cfg->target_y;
10243 +
10244 +       if(cfg->fmt & CAMIF_RGB24)
10245 +               daon = daon * 4 ;
10246 +       else {
10247 +               assert (cfg->fmt & CAMIF_RGB16);
10248 +               daon = daon *2;
10249 +       }
10250 +       switch ( cfg->pp_num ) {
10251 +               case 1:
10252 +                       for ( i = 0; i < 4 ; i++ ) {
10253 +                               cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf ;
10254 +                               cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf ;
10255 +                               writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10256 +                       }
10257 +                       break;
10258 +               case 2:
10259 +                       for ( i = 0; i < 4 ; i++) {
10260 +                               cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + TRY * daon;
10261 +                               cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + TRY * daon;
10262 +                               writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10263 +                       }
10264 +                       break;
10265 +               case 4:
10266 +                       for ( i = 0; i < 4 ; i++) {
10267 +                               cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + i * daon;
10268 +                               cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + i * daon;
10269 +                               writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
10270 +                       }
10271 +                       break;
10272 +               default:
10273 +                       printk("Invalid PingPong Number %d \n",cfg->pp_num);
10274 +                       panic("halt\n");
10275 +       }
10276 +       return 0;
10277 +}
10278 +
10279 +static int camif_pingpong(camif_cfg_t *cfg)
10280 +{
10281 +       if (cfg->dma_type & CAMIF_CODEC ) {
10282 +               camif_pp_codec(cfg);
10283 +       }
10284 +
10285 +       if ( cfg->dma_type & CAMIF_PREVIEW) {
10286 +               camif_pp_preview(cfg);
10287 +       }
10288 +       return 0;
10289 +}
10290 +
10291 +
10292 +/***********       Image Convert *******************************/
10293 +/*  Return Format
10294 + *  Supported by Hardware
10295 + *  V4L2_PIX_FMT_YUV420,
10296 + *  V4L2_PIX_FMT_YUV422P,
10297 + *  V4L2_PIX_FMT_BGR32 (BGR4)
10298 + * -----------------------------------
10299 + *  V4L2_PIX_FMT_RGB565(X)
10300 + *  Currenly 2byte --> BGR656 Format
10301 + *  S3C2440A,S3C24A0 supports vairants with reversed FMT_RGB565
10302 +    i.e  blue toward the least, red towards the most significant bit
10303 +    --  by SW.LEE
10304 + */
10305 +
10306 +
10307 +/*
10308 + * After calling camif_g_frame_num,
10309 + * this func must be called
10310 + */
10311 +u8 * camif_g_frame(camif_cfg_t *cfg)
10312 +{
10313 +       u8 * ret = NULL;
10314 +       int cnt = cfg->now_frame_num;
10315 +
10316 +       if(cfg->dma_type & CAMIF_PREVIEW) {
10317 +               ret = cfg->img_buf[cnt].virt_rgb;
10318 +       }
10319 +       if (cfg->dma_type & CAMIF_CODEC) {
10320 +               ret = cfg->img_buf[cnt].virt_y;
10321 +       }
10322 +       return ret;
10323 +}
10324 +
10325 +/* This function must be called in module initial time */
10326 +static int camif_source_fmt(camif_gc_t *gc)
10327 +{
10328 +       u32 cmd = 0;
10329 +
10330 +       /* Configure CISRCFMT --Source Format */
10331 +       if (gc->itu_fmt & CAMIF_ITU601) {
10332 +               cmd = CAMIF_ITU601;
10333 +       }
10334 +       else {
10335 +               assert ( gc->itu_fmt & CAMIF_ITU656);
10336 +               cmd = CAMIF_ITU656;
10337 +       }
10338 +       cmd  |= SOURCE_HSIZE(gc->source_x)| SOURCE_VSIZE(gc->source_y);
10339 +       /* Order422 */
10340 +       cmd |=  gc->order422;
10341 +       writel(cmd, camregs + S3C2440_CAM_REG_CISRCFMT);
10342 +
10343 +       return 0 ;
10344 +}
10345 +
10346 +
10347 +/*
10348 + * Codec Input YCBCR422 will be Fixed
10349 + */
10350 +static int camif_target_fmt(camif_cfg_t *cfg)
10351 +{
10352 +       u32 cmd = 0;
10353 +
10354 +       if (cfg->dma_type & CAMIF_CODEC) {
10355 +               /* YCBCR setting */
10356 +               cmd = TARGET_HSIZE(cfg->target_x)| TARGET_VSIZE(cfg->target_y);
10357 +               if ( cfg->fmt & CAMIF_OUT_YCBCR420 ) {
10358 +                       cmd |= OUT_YCBCR420|IN_YCBCR422;
10359 +               }
10360 +               else {
10361 +                       assert(cfg->fmt & CAMIF_OUT_YCBCR422);
10362 +                       cmd |= OUT_YCBCR422|IN_YCBCR422;
10363 +               }
10364 +               writel(cmd | cfg->flip, camregs + S3C2440_CAM_REG_CICOTRGFMT);
10365 +
10366 +       } else {
10367 +               assert(cfg->dma_type & CAMIF_PREVIEW);
10368 +               writel(TARGET_HSIZE(cfg->target_x)|TARGET_VSIZE(cfg->target_y)|cfg->flip,
10369 +                       camregs + S3C2440_CAM_REG_CIPRTRGFMT);
10370 +       }
10371 +       return 0;
10372 +}
10373 +
10374 +void camif_change_flip(camif_cfg_t *cfg)
10375 +{
10376 +       u32 cmd = readl(camregs + S3C2440_CAM_REG_CICOTRGFMT);
10377 +
10378 +       cmd &= ~(BIT14|BIT15);
10379 +       cmd |= cfg->flip;
10380 +
10381 +       writel(cmd, camregs + S3C2440_CAM_REG_CICOTRGFMT);
10382 +}
10383 +
10384 +
10385 +
10386 +/* Must:
10387 + * Before calling this function,
10388 + * you must use "camif_dynamic_open"
10389 + * If you want to enable both CODEC and preview
10390 + *  you must do it at the same time.
10391 + */
10392 +int camif_capture_start(camif_cfg_t *cfg)
10393 +{
10394 +       u32 n_cmd = 0;          /* Next Command */
10395 +
10396 +       switch(cfg->exec) {
10397 +       case CAMIF_BOTH_DMA_ON:
10398 +               camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
10399 +               writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
10400 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10401 +               writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
10402 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10403 +               n_cmd = CAMIF_CAP_PREVIEW_ON | CAMIF_CAP_CODEC_ON;
10404 +               break;
10405 +       case CAMIF_DMA_ON:
10406 +               camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
10407 +               if (cfg->dma_type&CAMIF_CODEC) {
10408 +                       writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
10409 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10410 +                       n_cmd = CAMIF_CAP_CODEC_ON;
10411 +               } else {
10412 +                       writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
10413 +                            SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10414 +                       n_cmd = CAMIF_CAP_PREVIEW_ON;
10415 +               }
10416 +
10417 +               /* wait until Sync Time expires */
10418 +               /* First settting, to wait VSYNC fall  */
10419 +               /* By VESA spec,in 640x480 @60Hz
10420 +                       MAX Delay Time is around 64us which "while" has.*/
10421 +               while(VSYNC & readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
10422 +               break;
10423 +       default:
10424 +               break;
10425 +}
10426 +       writel(n_cmd | CAMIF_CAP_ON, camregs + S3C2440_CAM_REG_CIIMGCPT);
10427 +       return 0;
10428 +}
10429 +
10430 +
10431 +int camif_capture_stop(camif_cfg_t *cfg)
10432 +{
10433 +       u32 n_cmd = readl(camregs + S3C2440_CAM_REG_CIIMGCPT);  /* Next Command */
10434 +
10435 +       switch(cfg->exec) {
10436 +       case CAMIF_BOTH_DMA_OFF:
10437 +               writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
10438 +                       ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10439 +               writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
10440 +                       ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10441 +               n_cmd = 0;
10442 +               break;
10443 +       case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
10444 +       case CAMIF_DMA_OFF:
10445 +               if (cfg->dma_type&CAMIF_CODEC) {
10446 +                       writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
10447 +                           ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
10448 +                       n_cmd &= ~CAMIF_CAP_CODEC_ON;
10449 +                       if (!(n_cmd & CAMIF_CAP_PREVIEW_ON))
10450 +                               n_cmd = 0;
10451 +               } else {
10452 +                       writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
10453 +                           ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10454 +                       n_cmd &= ~CAMIF_CAP_PREVIEW_ON;
10455 +                       if (!(n_cmd & CAMIF_CAP_CODEC_ON))
10456 +                               n_cmd = 0;
10457 +               }
10458 +               break;
10459 +       default:
10460 +               panic("Unexpected \n");
10461 +       }
10462 +       writel(n_cmd, camregs + S3C2440_CAM_REG_CIIMGCPT);
10463 +
10464 +       if (cfg->exec == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ  */
10465 +               if (cfg->dma_type & CAMIF_CODEC)
10466 +                       writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
10467 +                            LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
10468 +               else
10469 +                       writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
10470 +                            LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
10471 +       }
10472 +#if 0
10473 +       else {                          /* to make internal state machine of CAMERA stop */
10474 +               camif_reset(CAMIF_RESET, 0);
10475 +       }
10476 +#endif
10477 +       return 0;
10478 +}
10479 +
10480 +
10481 +/* LastIRQEn is autoclear */
10482 +void camif_last_irq_en(camif_cfg_t *cfg)
10483 +{
10484 +       if ((cfg->exec == CAMIF_BOTH_DMA_ON) || (cfg->dma_type & CAMIF_CODEC))
10485 +               writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
10486 +                       LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
10487 +
10488 +       if ((cfg->exec == CAMIF_BOTH_DMA_ON) || !(cfg->dma_type & CAMIF_CODEC))
10489 +               writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
10490 +                       LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
10491 +}
10492 +
10493 +static int
10494 +camif_scaler_internal(u32 srcWidth, u32 dstWidth, u32 *ratio, u32 *shift)
10495 +{
10496 +       if(srcWidth>=64*dstWidth){
10497 +               printk(KERN_ERR"CAMERA:out of prescaler range: srcWidth /dstWidth = %d(< 64)\n",
10498 +                        srcWidth/dstWidth);
10499 +               return 1;
10500 +       }
10501 +       else if(srcWidth>=32*dstWidth){
10502 +               *ratio=32;
10503 +               *shift=5;
10504 +       }
10505 +       else if(srcWidth>=16*dstWidth){
10506 +               *ratio=16;
10507 +               *shift=4;
10508 +       }
10509 +       else if(srcWidth>=8*dstWidth){
10510 +               *ratio=8;
10511 +               *shift=3;
10512 +       }
10513 +       else if(srcWidth>=4*dstWidth){
10514 +               *ratio=4;
10515 +               *shift=2;
10516 +       }
10517 +       else if(srcWidth>=2*dstWidth){
10518 +               *ratio=2;
10519 +               *shift=1;
10520 +       }
10521 +       else {
10522 +               *ratio=1;
10523 +               *shift=0;
10524 +       }
10525 +       return 0;
10526 +}
10527 +
10528 +
10529 +int camif_g_fifo_status(camif_cfg_t *cfg)
10530 +{
10531 +       u32 reg;
10532 +
10533 +       if (cfg->dma_type & CAMIF_CODEC) {
10534 +               u32 flag = CO_OVERFLOW_Y | CO_OVERFLOW_CB | CO_OVERFLOW_CR;
10535 +               reg = readl(camregs + S3C2440_CAM_REG_CICOSTATUS);
10536 +               if (reg & flag) {
10537 +                       printk("CODEC: FIFO error(0x%08x) and corrected\n",reg);
10538 +                       /* FIFO Error Count ++  */
10539 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
10540 +                               CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR,
10541 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10542 +
10543 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
10544 +                               ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
10545 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10546 +                       return 1; /* Error */
10547 +               }
10548 +       }
10549 +       if (cfg->dma_type & CAMIF_PREVIEW) {
10550 +               u32 flag = PR_OVERFLOW_CB | PR_OVERFLOW_CR;
10551 +               reg = readl(camregs + S3C2440_CAM_REG_CIPRSTATUS);
10552 +               if (reg & flag) {
10553 +                       printk("PREVIEW:FIFO error(0x%08x) and corrected\n",reg);
10554 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
10555 +                               CO_FIFO_CB | CO_FIFO_CR,
10556 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10557 +
10558 +                       writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
10559 +                               ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
10560 +                               camregs + S3C2440_CAM_REG_CIWDOFST);
10561 +                       /* FIFO Error Count ++  */
10562 +                       return 1; /* Error */
10563 +               }
10564 +       }
10565 +       return 0;               /* No Error */
10566 +}
10567 +
10568 +
10569 +/* Policy:
10570 + * if codec or preview define the win offset,
10571 + *    other must follow that value.
10572 + */
10573 +int camif_win_offset(camif_gc_t *gc )
10574 +{
10575 +       u32 h = gc->win_hor_ofst;
10576 +       u32 v = gc->win_ver_ofst;
10577 +
10578 +       /*Clear Overflow */
10579 +       writel(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR | PR_FIFO_CB | PR_FIFO_CB,
10580 +               camregs + S3C2440_CAM_REG_CIWDOFST);
10581 +       writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
10582 +
10583 +       if (!h && !v)   {
10584 +               writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
10585 +               return 0;
10586 +       }
10587 +
10588 +       writel(WINOFEN | WINHOROFST(h) | WINVEROFST(v), camregs + S3C2440_CAM_REG_CIWDOFST);
10589 +       return 0;
10590 +}
10591 +
10592 +/*
10593 + * when you change the resolution in a specific camera,
10594 + * sometimes, it is necessary to change the polarity
10595 + *                                       -- SW.LEE
10596 + */
10597 +static void camif_polarity(camif_gc_t *gc)
10598 +{
10599 +       u32 cmd = readl(camregs + S3C2440_CAM_REG_CIGCTRL);;
10600 +
10601 +       cmd = cmd & ~(BIT26|BIT25|BIT24); /* clear polarity */
10602 +       if (gc->polarity_pclk)
10603 +               cmd |= GC_INVPOLPCLK;
10604 +       if (gc->polarity_vsync)
10605 +               cmd |= GC_INVPOLVSYNC;
10606 +       if (gc->polarity_href)
10607 +               cmd |= GC_INVPOLHREF;
10608 +       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10609 +              cmd, camregs + S3C2440_CAM_REG_CIGCTRL);
10610 +}
10611 +
10612 +
10613 +int camif_dynamic_open(camif_cfg_t *cfg)
10614 +{
10615 +       camif_win_offset(cfg->gc);
10616 +       camif_polarity(cfg->gc);
10617 +
10618 +       if(camif_scaler(cfg)) {
10619 +               printk(KERN_ERR "CAMERA:Preview Scaler, Change WinHorOfset or Target Size\n");
10620 +               return 1;
10621 +       }
10622 +       camif_target_fmt(cfg);
10623 +       if (camif_dma_burst(cfg)) {
10624 +               printk(KERN_ERR "CAMERA:DMA Busrt Length Error \n");
10625 +               return 1;
10626 +       }
10627 +       if(camif_malloc(cfg) ) {
10628 +               printk(KERN_ERR "    Instead of using consistent_alloc()\n"
10629 +                               "    lease use dedicated memory allocation for DMA memory\n");
10630 +               return -1;
10631 +       }
10632 +       camif_pingpong(cfg);
10633 +       return 0;
10634 +}
10635 +
10636 +int camif_dynamic_close(camif_cfg_t *cfg)
10637 +{
10638 +       camif_demalloc(cfg);
10639 +       return 0;
10640 +}
10641 +
10642 +static int camif_target_area(camif_cfg_t *cfg)
10643 +{
10644 +       u32 rect = cfg->target_x * cfg->target_y;
10645 +
10646 +       if (cfg->dma_type & CAMIF_CODEC)
10647 +               writel(rect, camregs + S3C2440_CAM_REG_CICOTAREA);
10648 +
10649 +       if (cfg->dma_type & CAMIF_PREVIEW)
10650 +               writel(rect, camregs + S3C2440_CAM_REG_CIPRTAREA);
10651 +
10652 +       return 0;
10653 +}
10654 +
10655 +static int inline camif_hw_reg(camif_cfg_t *cfg)
10656 +{
10657 +       u32 cmd = 0;
10658 +
10659 +       if (cfg->dma_type & CAMIF_CODEC) {
10660 +               writel(PRE_SHIFT(cfg->sc.shfactor) |
10661 +                      PRE_HRATIO(cfg->sc.prehratio) |
10662 +                      PRE_VRATIO(cfg->sc.prevratio),
10663 +                      camregs + S3C2440_CAM_REG_CICOSCPRERATIO);
10664 +               writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
10665 +                      PRE_DST_HEIGHT(cfg->sc.predst_y),
10666 +                      camregs + S3C2440_CAM_REG_CICOSCPREDST);
10667 +
10668 +               /* Differ from Preview */
10669 +               if (cfg->sc.scalerbypass)
10670 +                       cmd |= SCALERBYPASS;
10671 +               if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
10672 +                       cmd |= BIT30|BIT29;
10673 +               writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) |
10674 +                      MAIN_VRATIO(cfg->sc.mainvratio),
10675 +                      camregs + S3C2440_CAM_REG_CICOSCCTRL);
10676 +               return 0;
10677 +       }
10678 +       if (cfg->dma_type & CAMIF_PREVIEW) {
10679 +               writel(PRE_SHIFT(cfg->sc.shfactor) |
10680 +                      PRE_HRATIO(cfg->sc.prehratio) |
10681 +                      PRE_VRATIO(cfg->sc.prevratio),
10682 +                      camregs + S3C2440_CAM_REG_CIPRSCPRERATIO);
10683 +               writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
10684 +                      PRE_DST_HEIGHT(cfg->sc.predst_y),
10685 +                      camregs + S3C2440_CAM_REG_CIPRSCPREDST);
10686 +               /* Differ from Codec */
10687 +               if (cfg->fmt & CAMIF_RGB24)
10688 +                       cmd |= RGB_FMT24;
10689 +               if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
10690 +                       cmd |= BIT29 | BIT28;
10691 +               writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) | S_METHOD |
10692 +                      MAIN_VRATIO(cfg->sc.mainvratio),
10693 +                      camregs + S3C2440_CAM_REG_CIPRSCCTRL);
10694 +               return 0;
10695 +       }
10696 +
10697 +       panic("CAMERA:DMA_TYPE Wrong \n");
10698 +       return 0;
10699 +}
10700 +
10701 +
10702 +/* Configure Pre-scaler control  & main scaler control register */
10703 +static int camif_scaler(camif_cfg_t *cfg)
10704 +{
10705 +       int tx = cfg->target_x, ty = cfg->target_y;
10706 +       int sx, sy;
10707 +
10708 +       if (tx <= 0 || ty <= 0)
10709 +               panic("CAMERA: Invalid target size \n");
10710 +
10711 +       sx = cfg->gc->source_x - 2 * cfg->gc->win_hor_ofst;
10712 +       sy = cfg->gc->source_y - 2 * cfg->gc->win_ver_ofst;
10713 +       if (sx <= 0 || sy <= 0)
10714 +               panic("CAMERA: Invalid source size \n");
10715 +
10716 +       cfg->sc.modified_src_x = sx;
10717 +       cfg->sc.modified_src_y = sy;
10718 +
10719 +       /* Pre-scaler control register 1 */
10720 +       camif_scaler_internal(sx, tx, &cfg->sc.prehratio, &cfg->sc.hfactor);
10721 +       camif_scaler_internal(sy, ty, &cfg->sc.prevratio, &cfg->sc.vfactor);
10722 +
10723 +       if (cfg->dma_type & CAMIF_PREVIEW)
10724 +               if ((sx / cfg->sc.prehratio) > 640) {
10725 +                       printk(KERN_INFO "CAMERA: Internal Preview line "
10726 +                                        "buffer is 640 pixels\n");
10727 +                       return 1; /* Error */
10728 +               }
10729 +
10730 +       cfg->sc.shfactor = 10 - (cfg->sc.hfactor + cfg->sc.vfactor);
10731 +       /* Pre-scaler control register 2 */
10732 +       cfg->sc.predst_x = sx / cfg->sc.prehratio;
10733 +       cfg->sc.predst_y = sy / cfg->sc.prevratio;
10734 +
10735 +       /* Main-scaler control register */
10736 +       cfg->sc.mainhratio = (sx << 8) / (tx << cfg->sc.hfactor);
10737 +       cfg->sc.mainvratio = (sy << 8) / (ty << cfg->sc.vfactor);
10738 +       DPRINTK(" sx %d, sy %d tx %d ty %d  \n", sx, sy, tx, ty);
10739 +       DPRINTK(" hfactor %d  vfactor %d \n",cfg->sc.hfactor, cfg->sc.vfactor);
10740 +
10741 +       cfg->sc.scaleup_h  = (sx <= tx) ? 1: 0;
10742 +       cfg->sc.scaleup_v  = (sy <= ty) ? 1: 0;
10743 +       if (cfg->sc.scaleup_h != cfg->sc.scaleup_v)
10744 +               printk(KERN_ERR "scaleup_h must be same to scaleup_v \n");
10745 +
10746 +       camif_hw_reg(cfg);
10747 +       camif_target_area(cfg);
10748 +
10749 +       return 0;
10750 +}
10751 +
10752 +/******************************************************
10753 + CalculateBurstSize - Calculate the busrt lengths
10754 + Description:
10755 + - dstHSize: the number of the byte of H Size.
10756 +********************************************************/
10757 +static void camif_g_bsize(u32 hsize, u32 *mburst, u32 *rburst)
10758 +{
10759 +       u32 tmp;
10760 +
10761 +       tmp = (hsize / 4) % 16;
10762 +       switch(tmp) {
10763 +       case 0:
10764 +               *mburst=16;
10765 +               *rburst=16;
10766 +               break;
10767 +       case 4:
10768 +               *mburst=16;
10769 +               *rburst=4;
10770 +               break;
10771 +       case 8:
10772 +               *mburst=16;
10773 +               *rburst=8;
10774 +               break;
10775 +       default:
10776 +               tmp=(hsize / 4) % 8;
10777 +               switch(tmp) {
10778 +               case 0:
10779 +                       *mburst = 8;
10780 +                       *rburst = 8;
10781 +                       break;
10782 +               case 4:
10783 +                       *mburst = 8;
10784 +                       *rburst = 4;
10785 +               default:
10786 +                       *mburst = 4;
10787 +                       tmp = (hsize / 4) % 4;
10788 +                       *rburst= (tmp) ? tmp: 4;
10789 +                       break;
10790 +       }
10791 +               break;
10792 +       }
10793 +}
10794 +
10795 +/* SXGA 1028x1024*/
10796 +/* XGA 1024x768 */
10797 +/* SVGA 800x600 */
10798 +/* VGA 640x480 */
10799 +/* CIF 352x288 */
10800 +/* QVGA 320x240 */
10801 +/* QCIF 176x144 */
10802 +/* ret val
10803 +        1 : DMA Size Error
10804 +*/
10805 +#define BURST_ERR 1
10806 +static int camif_dma_burst(camif_cfg_t *cfg)
10807 +{
10808 +       int width = cfg->target_x;
10809 +
10810 +       if (cfg->dma_type & CAMIF_CODEC ) {
10811 +               u32 yburst_m, yburst_r;
10812 +               u32 cburst_m, cburst_r;
10813 +               /* CODEC DMA WIDHT is multiple of 16 */
10814 +               if (width % 16)
10815 +                       return BURST_ERR;   /* DMA Burst Length Error */
10816 +               camif_g_bsize(width, &yburst_m, &yburst_r);
10817 +               camif_g_bsize(width / 2, &cburst_m, &cburst_r);
10818 +
10819 +               writel(YBURST_M(yburst_m) | CBURST_M(cburst_m) |
10820 +                      YBURST_R(yburst_r) | CBURST_R(cburst_r),
10821 +                      camregs + S3C2440_CAM_REG_CICOCTRL);
10822 +       }
10823 +
10824 +       if (cfg->dma_type & CAMIF_PREVIEW) {
10825 +               u32 rgburst_m, rgburst_r;
10826 +               if(cfg->fmt == CAMIF_RGB24) {
10827 +                       if (width % 2)
10828 +                               return BURST_ERR;   /* DMA Burst Length Error */
10829 +                       camif_g_bsize(width*4,&rgburst_m,&rgburst_r);
10830 +               } else {                /* CAMIF_RGB16 */
10831 +                       if ((width / 2) %2)
10832 +                               return BURST_ERR; /* DMA Burst Length Error */
10833 +                       camif_g_bsize(width*2,&rgburst_m,&rgburst_r);
10834 +               }
10835 +
10836 +               writel(RGBURST_M(rgburst_m) | RGBURST_R(rgburst_r),
10837 +                      camregs + S3C2440_CAM_REG_CIPRCTRL);
10838 +       }
10839 +       return 0;
10840 +}
10841 +
10842 +static int camif_gpio_init(void)
10843 +{
10844 +#ifdef CONFIG_ARCH_S3C24A0A
10845 +       /* S3C24A0A has the dedicated signal pins for Camera */
10846 +#else
10847 +       s3c2410_gpio_cfgpin(S3C2440_GPJ0, S3C2440_GPJ0_CAMDATA0);
10848 +       s3c2410_gpio_cfgpin(S3C2440_GPJ1, S3C2440_GPJ1_CAMDATA1);
10849 +       s3c2410_gpio_cfgpin(S3C2440_GPJ2, S3C2440_GPJ2_CAMDATA2);
10850 +       s3c2410_gpio_cfgpin(S3C2440_GPJ3, S3C2440_GPJ3_CAMDATA3);
10851 +       s3c2410_gpio_cfgpin(S3C2440_GPJ4, S3C2440_GPJ4_CAMDATA4);
10852 +       s3c2410_gpio_cfgpin(S3C2440_GPJ5, S3C2440_GPJ5_CAMDATA5);
10853 +       s3c2410_gpio_cfgpin(S3C2440_GPJ6, S3C2440_GPJ6_CAMDATA6);
10854 +       s3c2410_gpio_cfgpin(S3C2440_GPJ7, S3C2440_GPJ7_CAMDATA7);
10855 +
10856 +       s3c2410_gpio_cfgpin(S3C2440_GPJ8, S3C2440_GPJ8_CAMPCLK);
10857 +       s3c2410_gpio_cfgpin(S3C2440_GPJ9, S3C2440_GPJ9_CAMVSYNC);
10858 +       s3c2410_gpio_cfgpin(S3C2440_GPJ10, S3C2440_GPJ10_CAMHREF);
10859 +       s3c2410_gpio_cfgpin(S3C2440_GPJ11, S3C2440_GPJ11_CAMCLKOUT);
10860 +       s3c2410_gpio_cfgpin(S3C2440_GPJ12, S3C2440_GPJ12_CAMRESET);
10861 +#endif
10862 +        return 0;
10863 +}
10864 +
10865 +
10866 +#define ROUND_ADD 0x100000
10867 +
10868 +#ifdef CONFIG_ARCH_S3C24A0A
10869 +int camif_clock_init(camif_gc_t *gc)
10870 +{
10871 +       unsigned int upll, camclk_div, camclk;
10872 +
10873 +       if (!gc) camclk = 24000000;
10874 +       else  {
10875 +               camclk = gc->camclk;
10876 +               if (camclk > 48000000)
10877 +                       printk(KERN_ERR "Wrong Camera Clock\n");
10878 +       }
10879 +
10880 +       CLKCON |= CLKCON_CAM_UPLL | CLKCON_CAM_HCLK;
10881 +       upll = get_bus_clk(GET_UPLL);
10882 +       printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
10883 +       UPLLCON = FInsrt(56, fPLL_MDIV) | FInsrt(2, fPLL_PDIV)| FInsrt(1, fPLL_SDIV);
10884 +       upll = get_bus_clk(GET_UPLL);
10885 +
10886 +       camclk_div = (upll+ROUND_ADD) / camclk - 1;
10887 +       CLKDIVN = (CLKDIVN & 0xFF) | CLKDIVN_CAM(camclk_div);
10888 +       printk(KERN_INFO"CAMERA:upll %d MACRO 0x%08X CLKDIVN 0x%08X \n",
10889 +                               upll, CLKDIVN_CAM(camclk_div), CLKDIVN);
10890 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);  /* Dummy ? */
10891 +
10892 +       return 0;
10893 +}
10894 +#else
10895 +int camif_clock_init(camif_gc_t *gc)
10896 +{
10897 +       unsigned int camclk;
10898 +       struct clk *clk_camif = clk_get(NULL, "camif");
10899 +       struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
10900 +
10901 +       if (!gc)
10902 +               camclk = 24000000;
10903 +       else {
10904 +               camclk = gc->camclk;
10905 +               if (camclk > 48000000)
10906 +                       printk(KERN_ERR "Wrong Camera Clock\n");
10907 +       }
10908 +
10909 +       clk_set_rate(clk_camif, camclk);
10910 +
10911 +       clk_enable(clk_camif);
10912 +       clk_enable(clk_camif_upll);
10913 +
10914 +
10915 +#if 0
10916 +       CLKCON |= CLKCON_CAMIF;
10917 +       upll = elfin_get_bus_clk(GET_UPLL);
10918 +       printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
10919 +       {
10920 +               UPLLCON = FInsrt(60, fPLL_MDIV) | FInsrt(4, fPLL_PDIV)| FInsrt(1, fPLL_SDIV);
10921 +               CLKDIVN |= DIVN_UPLL;   /* For USB */
10922 +               upll = elfin_get_bus_clk(GET_UPLL);
10923 +       }
10924 +
10925 +       camclk_div = (upll+ROUND_ADD) /(camclk * 2) -1;
10926 +       CAMDIVN = CAMCLK_SET_DIV|(camclk_div&0xf);
10927 +       printk(KERN_INFO "CAMERA:upll %08d  cam_clk %08d CAMDIVN 0x%08x \n",upll,camclk, CAMDIVN);
10928 +#endif
10929 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);  /* Dummy ? */
10930 +
10931 +       return 0;
10932 +}
10933 +#endif
10934 +
10935 +/*
10936 +   Reset Camera IP in CPU
10937 +   Reset External Sensor
10938 + */
10939 +void camif_reset(int is, int delay)
10940 +{
10941 +       switch (is) {
10942 +               case CAMIF_RESET:
10943 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10944 +                              GC_SWRST,
10945 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10946 +                       mdelay(1);
10947 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10948 +                              ~GC_SWRST,
10949 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10950 +                       break;
10951 +               case CAMIF_EX_RESET_AH: /*Active High */
10952 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10953 +                              ~GC_CAMRST,
10954 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10955 +                       udelay(200);
10956 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10957 +                              GC_CAMRST,
10958 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10959 +                       udelay(delay);
10960 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10961 +                              ~GC_CAMRST,
10962 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10963 +                       break;
10964 +               case CAMIF_EX_RESET_AL: /*Active Low */
10965 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10966 +                              GC_CAMRST,
10967 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10968 +                       udelay(200);
10969 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
10970 +                              ~GC_CAMRST,
10971 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10972 +                       udelay(delay);
10973 +                       writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
10974 +                              GC_CAMRST,
10975 +                              camregs + S3C2440_CAM_REG_CIGCTRL);
10976 +                       break;
10977 +               default:
10978 +                       break;
10979 +       }
10980 +}
10981 +
10982 +/* For Camera Operation,
10983 + * we can give the high priority to REQ2 of ARBITER1
10984 + */
10985 +
10986 +/* Please move me into proper place
10987 + *  camif_gc_t is not because "rmmod imgsenor" will delete the instance of camif_gc_t
10988 + */
10989 +static u32 old_priority;
10990 +
10991 +static void camif_bus_priority(int flag)
10992 +{
10993 +       if (flag) {
10994 +#ifdef CONFIG_ARCH_S3C24A0A
10995 +               old_priority = PRIORITY0;
10996 +               PRIORITY0 = PRIORITY_I_FIX;
10997 +               PRIORITY1 = PRIORITY_I_FIX;
10998 +
10999 +#else
11000 +               old_priority = readl(S3C2410_PRIORITY);
11001 +               writel(readl(S3C2410_PRIORITY) & ~(3<<7), S3C2410_PRIORITY);
11002 +               writel(readl(S3C2410_PRIORITY) |  (1<<7), S3C2410_PRIORITY); /* Arbiter 1, REQ2 first */
11003 +               writel(readl(S3C2410_PRIORITY) & ~(1<<1), S3C2410_PRIORITY); /* Disable Priority Rotate */
11004 +#endif
11005 +       }
11006 +       else {
11007 +#ifdef CONFIG_ARCH_S3C24A0A
11008 +               PRIORITY0 = old_priority;
11009 +               PRIORITY1 = old_priority;
11010 +#else
11011 +               writel(old_priority, S3C2410_PRIORITY);
11012 +#endif
11013 +       }
11014 +}
11015 +
11016 +static void inline camif_clock_off(void)
11017 +{
11018 +#if defined (CONFIG_ARCH_S3C24A0A)
11019 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
11020 +
11021 +       CLKCON &= ~CLKCON_CAM_UPLL;
11022 +       CLKCON &= ~CLKCON_CAM_HCLK;
11023 +#else
11024 +       struct clk *clk_camif = clk_get(NULL, "camif");
11025 +       struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
11026 +
11027 +       writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
11028 +
11029 +       clk_disable(clk_camif);
11030 +       clk_disable(clk_camif_upll);
11031 +#endif
11032 +}
11033 +
11034 +
11035 +/* Init external image sensor
11036 + *  Before make some value into image senor,
11037 + *  you must set up the pixel clock.
11038 + */
11039 +void camif_setup_sensor(void)
11040 +{
11041 +       camif_reset(CAMIF_RESET, 0);
11042 +       camif_gpio_init();
11043 +       camif_clock_init(NULL);
11044 +/* Sometimes ,Before loading I2C module, we need the reset signal */
11045 +#ifdef CONFIG_ARCH_S3C24A0A
11046 +       camif_reset(CAMIF_EX_RESET_AL,1000);
11047 +#else
11048 +       camif_reset(CAMIF_EX_RESET_AH,1000);
11049 +#endif
11050 +}
11051 +
11052 +void camif_hw_close(camif_cfg_t *cfg)
11053 +{
11054 +       camif_bus_priority(0);
11055 +       camif_clock_off();
11056 +}
11057 +
11058 +void camif_hw_open(camif_gc_t *gc)
11059 +{
11060 +       camif_source_fmt(gc);
11061 +       camif_win_offset(gc);
11062 +       camif_bus_priority(1);
11063 +}
11064 +
11065 +
11066 +
11067 +/*
11068 + * Local variables:
11069 + * tab-width: 8
11070 + *  c-indent-level: 8
11071 + *  c-basic-offset: 8
11072 + *  c-set-style: "K&R"
11073 + * End:
11074 + */
11075 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/camif_fsm.c
11076 ===================================================================
11077 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
11078 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/camif_fsm.c       2009-01-02 00:01:56.000000000 +0100
11079 @@ -0,0 +1,432 @@
11080 +/*
11081 +    Copyright (C) 2004 Samsung Electronics
11082 +                     SW.LEE <hitchcar@sec.samsung.com>
11083 +
11084 +    This program is free software; you can redistribute it and/or modify
11085 +    it under the terms of the GNU General Public License as published by
11086 +    the Free Software Foundation; either version 2 of the License, or
11087 +    (at your option) any later version.
11088 +*/
11089 +
11090 +#include <linux/version.h>
11091 +#include <linux/module.h>
11092 +#include <linux/delay.h>
11093 +#include <linux/errno.h>
11094 +#include <linux/fs.h>
11095 +#include <linux/kernel.h>
11096 +#include <linux/major.h>
11097 +#include <linux/slab.h>
11098 +#include <linux/poll.h>
11099 +#include <linux/signal.h>
11100 +#include <linux/ioport.h>
11101 +#include <linux/sched.h>
11102 +#include <linux/types.h>
11103 +#include <linux/interrupt.h>
11104 +#include <linux/kmod.h>
11105 +#include <linux/vmalloc.h>
11106 +#include <linux/init.h>
11107 +#include <linux/pagemap.h>
11108 +#include <asm/io.h>
11109 +#include <asm/irq.h>
11110 +#include <asm/semaphore.h>
11111 +#include <linux/miscdevice.h>
11112 +
11113 +#define CONFIG_VIDEO_V4L1_COMPAT
11114 +#include <linux/videodev.h>
11115 +#include "camif.h"
11116 +
11117 +//#define SW_DEBUG
11118 +static void camif_start_p_with_c(camif_cfg_t *cfg);
11119 +
11120 +#include "camif.h"
11121 +const char *fsm_version =
11122 +        "$Id: camif_fsm.c,v 1.3 2004/04/27 10:26:28 swlee Exp $";
11123 +
11124 +
11125 +/*
11126 + * FSM function is the place where Synchronization in not necessary
11127 + * because IRS calls this functions.
11128 + */
11129 +
11130 +ssize_t camif_p_1fsm_start(camif_cfg_t *cfg)
11131 +{
11132 +       //camif_reset(CAMIF_RESET,0);
11133 +       cfg->exec = CAMIF_DMA_ON;
11134 +       camif_capture_start(cfg);
11135 +       camif_last_irq_en(cfg);
11136 +       cfg->status = CAMIF_STARTED;
11137 +       cfg->fsm = CAMIF_1nd_INT;
11138 +       return 0;
11139 +}
11140 +
11141 +
11142 +ssize_t camif_p_2fsm_start(camif_cfg_t *cfg)
11143 +{
11144 +       camif_reset(CAMIF_RESET,0);/* FIFO Count goes to zero */
11145 +       cfg->exec = CAMIF_DMA_ON;
11146 +       camif_capture_start(cfg);
11147 +       cfg->status = CAMIF_STARTED;
11148 +       cfg->fsm = CAMIF_1nd_INT;
11149 +       return 0;
11150 +}
11151 +
11152 +
11153 +ssize_t camif_4fsm_start(camif_cfg_t *cfg)
11154 +{
11155 +       camif_reset(CAMIF_RESET,0); /* FIFO Count goes to zero */
11156 +       cfg->exec = CAMIF_DMA_ON;
11157 +       camif_capture_start(cfg);
11158 +       cfg->status = CAMIF_STARTED;
11159 +       cfg->fsm = CAMIF_1nd_INT;
11160 +       cfg->perf.frames = 0;
11161 +       return 0;
11162 +}
11163 +
11164 +
11165 +/* Policy:
11166 +     cfg->perf.frames  set in camif_fsm.c
11167 +     cfg->status set in video-driver.c
11168 + */
11169 +
11170 +/*
11171 + * Don't insert camif_reset(CAM_RESET, 0 ) into this func
11172 + */
11173 +ssize_t camif_p_stop(camif_cfg_t *cfg)
11174 +{
11175 +       cfg->exec = CAMIF_DMA_OFF;
11176 +//     cfg->status = CAMIF_STOPPED;
11177 +       camif_capture_stop(cfg);
11178 +       cfg->perf.frames = 0;   /* Dupplicated ? */
11179 +       return 0;
11180 +}
11181 +
11182 +/* When C working, P asks C to play togehter */
11183 +/* Only P must call this function */
11184 +void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other)
11185 +{
11186 +//     cfg->gc->other = get_camif(CODEC_MINOR);
11187 +       cfg->gc->other = other;
11188 +       camif_start_p_with_c(cfg);
11189 +}
11190 +
11191 +static void camif_start_p_with_c(camif_cfg_t *cfg)
11192 +{
11193 +       camif_cfg_t *other = (camif_cfg_t *)cfg->gc->other;
11194 +       /* Preview Stop */
11195 +       cfg->exec = CAMIF_DMA_OFF;
11196 +       camif_capture_stop(cfg);
11197 +       /* Start P and C */
11198 +       camif_reset(CAMIF_RESET, 0);
11199 +       cfg->exec =CAMIF_BOTH_DMA_ON;
11200 +       camif_capture_start(cfg);
11201 +       cfg->fsm = CAMIF_1nd_INT; /* For Preview */
11202 +       if(!other) panic("Unexpected Error \n");
11203 +       other->fsm = CAMIF_1nd_INT; /* For Preview */
11204 +}
11205 +
11206 +static void camif_auto_restart(camif_cfg_t *cfg)
11207 +{
11208 +//     if (cfg->dma_type & CAMIF_CODEC) return;
11209 +       if (cfg->auto_restart)
11210 +               camif_start_p_with_c(cfg);
11211 +}
11212 +
11213 +
11214 +/* Supposed that PREVIEW already running
11215 + * request PREVIEW to start with Codec
11216 + */
11217 +static int camif_check_global(camif_cfg_t *cfg)
11218 +{
11219 +       int ret = 0;
11220 +
11221 +        if (down_interruptible(&cfg->gc->lock))
11222 +                       return -ERESTARTSYS;
11223 +        if ( cfg->gc->status & CWANT2START ) {
11224 +               cfg->gc->status &= ~CWANT2START;
11225 +               cfg->auto_restart = 1;
11226 +               ret = 1;
11227 +       }
11228 +       else {
11229 +               ret = 0; /* There is no codec */
11230 +               cfg->auto_restart = 0; /* Duplicated ..Dummy */
11231 +       }
11232 +
11233 +       up(&cfg->gc->lock);
11234 +
11235 +        return ret;
11236 +}
11237 +
11238 +/*
11239 + *    1nd INT : Start Interrupt
11240 + *    Xnd INT : enable Last IRQ : pingpong get the valid data
11241 + *    Ynd INT : Stop Codec or Preview : pingpong get the valid data
11242 + *    Znd INT : Last IRQ : valid data
11243 + */
11244 +#define CHECK_FREQ 5
11245 +int camif_enter_p_4fsm(camif_cfg_t *cfg)
11246 +{
11247 +       int ret = 0;
11248 +
11249 +       cfg->perf.frames++;
11250 +       if (cfg->fsm == CAMIF_NORMAL_INT)
11251 +       if (cfg->perf.frames % CHECK_FREQ == 0)
11252 +               ret = camif_check_global(cfg);
11253 +       if (ret > 0) cfg->fsm = CAMIF_Xnd_INT; /* Codec wait for Preview */
11254 +
11255 +       switch (cfg->fsm) {
11256 +               case CAMIF_1nd_INT:           /* Start IRQ */
11257 +                       cfg->fsm = CAMIF_NORMAL_INT;
11258 +                       ret = INSTANT_SKIP;
11259 +                       DPRINTK(KERN_INFO "1nd INT \n");
11260 +                       break;
11261 +               case CAMIF_NORMAL_INT:
11262 +                       cfg->status = CAMIF_INT_HAPPEN;
11263 +                       cfg->fsm = CAMIF_NORMAL_INT;
11264 +                       ret = INSTANT_GO;
11265 +                       DPRINTK(KERN_INFO "NORMAL INT \n");
11266 +                       break;
11267 +               case CAMIF_Xnd_INT:
11268 +                       camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
11269 +                       cfg->status = CAMIF_INT_HAPPEN;
11270 +                       cfg->fsm = CAMIF_Ynd_INT;
11271 +                       ret = INSTANT_GO;
11272 +                       DPRINTK(KERN_INFO "Xnd INT \n");
11273 +                       break;
11274 +               case CAMIF_Ynd_INT:        /* Capture Stop */
11275 +                       cfg->exec = CAMIF_DMA_OFF;
11276 +                       cfg->status = CAMIF_INT_HAPPEN;
11277 +                       camif_capture_stop(cfg);
11278 +                       cfg->fsm = CAMIF_Znd_INT;
11279 +                       ret = INSTANT_GO;
11280 +                       DPRINTK(KERN_INFO "Ynd INT \n");
11281 +                       break;
11282 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11283 +                       cfg->fsm = CAMIF_DUMMY_INT;
11284 +                       cfg->status = CAMIF_INT_HAPPEN;
11285 +                       ret = INSTANT_GO;
11286 +                       camif_auto_restart(cfg);  /* Automatically Restart Camera */
11287 +                       DPRINTK(KERN_INFO "Znd INT \n");
11288 +                       break;
11289 +               case CAMIF_DUMMY_INT:
11290 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11291 +                       ret = INSTANT_SKIP;
11292 +//                     DPRINTK(KERN_INFO "Dummy INT \n");
11293 +                       break;
11294 +               default:
11295 +                       printk(KERN_INFO "Unexpect INT %d \n",cfg->fsm);
11296 +                       ret = INSTANT_SKIP;
11297 +                       break;
11298 +       }
11299 +       return ret;
11300 +}
11301 +
11302 +
11303 +/*
11304 + * NO autorestart included in this function
11305 + */
11306 +int camif_enter_c_4fsm(camif_cfg_t *cfg)
11307 +{
11308 +       int ret;
11309 +
11310 +       cfg->perf.frames++;
11311 +#if 0
11312 +       if (   (cfg->fsm==CAMIF_NORMAL_INT)
11313 +           && (cfg->perf.frames>cfg->restart_limit-1)
11314 +          )
11315 +               cfg->fsm = CAMIF_Xnd_INT;
11316 +#endif
11317 +       switch (cfg->fsm) {
11318 +               case CAMIF_1nd_INT:           /* Start IRQ */
11319 +                       cfg->fsm = CAMIF_NORMAL_INT;
11320 +//                     cfg->status = CAMIF_STARTED; /* need this to meet auto-restart */
11321 +                       ret = INSTANT_SKIP;
11322 +                       DPRINTK(KERN_INFO "1nd INT \n");
11323 +                       break;
11324 +               case CAMIF_NORMAL_INT:
11325 +                       cfg->status = CAMIF_INT_HAPPEN;
11326 +                       cfg->fsm = CAMIF_NORMAL_INT;
11327 +                       ret = INSTANT_GO;
11328 +                       DPRINTK(KERN_INFO "NORMALd INT \n");
11329 +                       break;
11330 +               case CAMIF_Xnd_INT:
11331 +                       camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
11332 +                       cfg->status = CAMIF_INT_HAPPEN;
11333 +                       cfg->fsm = CAMIF_Ynd_INT;
11334 +                       ret = INSTANT_GO;
11335 +                       DPRINTK(KERN_INFO "Xnd INT \n");
11336 +                       break;
11337 +               case CAMIF_Ynd_INT:        /* Capture Stop */
11338 +                       cfg->exec = CAMIF_DMA_OFF;
11339 +                       cfg->status = CAMIF_INT_HAPPEN;
11340 +                       camif_capture_stop(cfg);
11341 +                       cfg->fsm = CAMIF_Znd_INT;
11342 +                       ret = INSTANT_GO;
11343 +                       DPRINTK(KERN_INFO "Ynd INT \n");
11344 +                       break;
11345 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11346 +                       cfg->fsm = CAMIF_DUMMY_INT;
11347 +                       cfg->status = CAMIF_INT_HAPPEN;
11348 +                       ret = INSTANT_GO;
11349 +                       DPRINTK(KERN_INFO "Znd INT \n");
11350 +                       break;
11351 +               case CAMIF_DUMMY_INT:
11352 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11353 +                       ret = INSTANT_SKIP;
11354 +                       break;
11355 +               default:
11356 +                       printk(KERN_INFO "Unexpect INT %d \n",cfg->fsm);
11357 +                       ret = INSTANT_SKIP;
11358 +                       break;
11359 +       }
11360 +       return ret;
11361 +}
11362 +
11363 +/* 4 Interrups State Machine is for two pingpong
11364 + *    1nd INT : Start Interrupt
11365 + *    Xnd INT : enable Last IRQ : pingpong get the valid data
11366 + *    Ynd INT : Stop Codec or Preview : pingpong get the valid data
11367 + *    Znd INT : Last IRQ : valid data
11368 + *
11369 + * Note:
11370 + *    Before calling this func, you must call camif_reset
11371 + */
11372 +
11373 +int camif_enter_2fsm(camif_cfg_t *cfg) /* Codec FSM */
11374 +{
11375 +       int ret;
11376 +
11377 +       cfg->perf.frames++;
11378 +       switch (cfg->fsm) {
11379 +               case CAMIF_1nd_INT:           /* Start IRQ */
11380 +                       cfg->fsm = CAMIF_Xnd_INT;
11381 +                       ret = INSTANT_SKIP;
11382 +//                     printk(KERN_INFO "1nd INT \n");
11383 +                       break;
11384 +               case CAMIF_Xnd_INT:
11385 +                       camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
11386 +                       cfg->now_frame_num = 0;
11387 +                       cfg->status = CAMIF_INT_HAPPEN;
11388 +                       cfg->fsm = CAMIF_Ynd_INT;
11389 +                       ret = INSTANT_GO;
11390 +//                     printk(KERN_INFO "2nd INT \n");
11391 +                       break;
11392 +               case CAMIF_Ynd_INT:        /* Capture Stop */
11393 +                       cfg->exec = CAMIF_DMA_OFF;
11394 +                       cfg->now_frame_num = 1;
11395 +                       cfg->status = CAMIF_INT_HAPPEN;
11396 +                       camif_capture_stop(cfg);
11397 +                       cfg->fsm = CAMIF_Znd_INT;
11398 +                       ret = INSTANT_GO;
11399 +//                     printk(KERN_INFO "Ynd INT \n");
11400 +                       break;
11401 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11402 +                       cfg->now_frame_num = 0;
11403 +//                     cfg->fsm = CAMIF_DUMMY_INT;
11404 +                       cfg->status = CAMIF_INT_HAPPEN;
11405 +                       ret = INSTANT_GO;
11406 +//                     printk(KERN_INFO "Znd INT \n");
11407 +                       break;
11408 +               case CAMIF_DUMMY_INT:
11409 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11410 +                       ret = INSTANT_SKIP;
11411 +                       printk(KERN_INFO "Dummy INT \n");
11412 +                       break;
11413 +               default:  /* CAMIF_PENDING_INT */
11414 +                       printk(KERN_INFO "Unexpect INT \n");
11415 +                       ret = INSTANT_SKIP;
11416 +                       break;
11417 +       }
11418 +       return ret;
11419 +}
11420 +
11421 +
11422 +/* 2 Interrups State Machine is for one pingpong
11423 + *    1nd INT : Stop Codec or Preview : pingpong get the valid data
11424 + *    2nd INT : Last IRQ : dummy data
11425 + */
11426 +int camif_enter_1fsm(camif_cfg_t *cfg) /* Codec FSM */
11427 +{
11428 +       int ret;
11429 +
11430 +       cfg->perf.frames++;
11431 +       switch (cfg->fsm) {
11432 +               case CAMIF_Ynd_INT:             /* IRQ for Enabling LAST IRQ */
11433 +                       cfg->exec = CAMIF_DMA_OFF;
11434 +                       camif_capture_stop(cfg);
11435 +                       cfg->fsm = CAMIF_Znd_INT;
11436 +                       ret = INSTANT_SKIP;
11437 +       //              printk(KERN_INFO "Ynd INT \n");
11438 +                       break;
11439 +               case CAMIF_Znd_INT:             /*  LAST IRQ (Dummy IRQ */
11440 +                       cfg->fsm = CAMIF_DUMMY_INT;
11441 +                       cfg->status = CAMIF_INT_HAPPEN;
11442 +                       ret = INSTANT_GO;
11443 +       //              printk(KERN_INFO "Znd INT \n");
11444 +                       break;
11445 +               case CAMIF_DUMMY_INT:
11446 +                       cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
11447 +                       ret = INSTANT_SKIP;
11448 +                       printk(KERN_INFO "Dummy INT \n");
11449 +                       break;
11450 +               default:
11451 +                       printk(KERN_INFO "Unexpect INT \n");
11452 +                       ret = INSTANT_SKIP;
11453 +                       break;
11454 +       }
11455 +       return ret;
11456 +}
11457 +
11458 +
11459 +/*
11460 + *  GLOBAL STATUS CONTROL FUNCTION
11461 + *
11462 + */
11463 +
11464 +
11465 +/* Supposed that PREVIEW already running
11466 + * request PREVIEW to start with Codec
11467 + */
11468 +int camif_callback_start(camif_cfg_t *cfg)
11469 +{
11470 +        int  doit = 1;
11471 +        while (doit) {
11472 +                if (down_interruptible(&cfg->gc->lock)) {
11473 +                        return -ERESTARTSYS;
11474 +                }
11475 +                cfg->gc->status = CWANT2START;
11476 +                cfg->gc->other = cfg;
11477 +                up(&cfg->gc->lock);
11478 +                doit = 0;
11479 +        }
11480 +        return 0;
11481 +}
11482 +
11483 +/*
11484 + * Return status of Preview Machine
11485 +  ret value :
11486 +      0: Preview is not working
11487 +      X: Codec must follow PREVIEW start
11488 +*/
11489 +int camif_check_preview(camif_cfg_t *cfg)
11490 +{
11491 +        int ret = 0;
11492 +
11493 +        if (down_interruptible(&cfg->gc->lock)) {
11494 +                        ret = -ERESTARTSYS;
11495 +                        return ret;
11496 +        }
11497 +        if (cfg->gc->user == 1) ret = 0;
11498 +     //   else if (cfg->gc->status & PNOTWORKING) ret = 0;
11499 +        else ret = 1;
11500 +        up(&cfg->gc->lock);
11501 +        return ret;
11502 +}
11503 +
11504 +
11505 +
11506 +
11507 +/*
11508 + * Local variables:
11509 + * c-basic-offset: 8
11510 + * End:
11511 + */
11512 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/camif.h
11513 ===================================================================
11514 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
11515 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/camif.h   2009-01-02 00:01:56.000000000 +0100
11516 @@ -0,0 +1,304 @@
11517 +/*
11518 +    FIMC2.0  Camera Header File
11519 +
11520 +    Copyright (C) 2003 Samsung Electronics (SW.LEE: hitchcar@samsung.com)
11521 +
11522 +       Author : SW.LEE <hitchcar@samsung.com>
11523 +
11524 +    This program is free software; you can redistribute it and/or modify
11525 +    it under the terms of the GNU General Public License as published by
11526 +    the Free Software Foundation; either version 2 of the License, or
11527 +    (at your option) any later version.
11528 +*
11529 +*/
11530 +
11531 +
11532 +#ifndef __FIMC20_CAMIF_H_
11533 +#define __FIMC20_CAMIF_H_
11534 +
11535 +#ifdef __KERNEL__
11536 +
11537 +#include "bits.h"
11538 +#include "videodev.h"
11539 +#include <asm/types.h>
11540 +#include <linux/i2c.h>
11541 +
11542 +#endif  /* __KERNEL__ */
11543 +
11544 +#ifndef O_NONCAP
11545 +#define O_NONCAP O_TRUNC
11546 +#endif
11547 +
11548 +/* Codec or Preview Status */
11549 +#define CAMIF_STARTED         BIT1
11550 +#define CAMIF_STOPPED         BIT2
11551 +#define CAMIF_INT_HAPPEN      BIT3
11552 +
11553 +/* Codec or Preview  : Interrupt FSM */
11554 +#define CAMIF_1nd_INT         BIT7
11555 +#define CAMIF_Xnd_INT         BIT8
11556 +#define CAMIF_Ynd_INT         BIT9
11557 +#define CAMIF_Znd_INT         BIT10
11558 +#define CAMIF_NORMAL_INT      BIT11
11559 +#define CAMIF_DUMMY_INT       BIT12
11560 +#define CAMIF_PENDING_INT     0
11561 +
11562 +
11563 +/* CAMIF RESET Definition */
11564 +#define CAMIF_RESET           BIT0
11565 +#define CAMIF_EX_RESET_AL     BIT1     /* Active Low */
11566 +#define CAMIF_EX_RESET_AH     BIT2     /* Active High */
11567 +
11568 +
11569 +enum camif_itu_fmt {
11570 +       CAMIF_ITU601 = BIT31,
11571 +       CAMIF_ITU656 = 0
11572 +};
11573 +
11574 +/* It is possbie to use two device simultaneously */
11575 +enum camif_dma_type {
11576 +       CAMIF_PREVIEW = BIT0,
11577 +       CAMIF_CODEC   = BIT1,
11578 +};
11579 +
11580 +enum camif_order422 {
11581 +       CAMIF_YCBYCR = 0,
11582 +       CAMIF_YCRYCB = BIT14,
11583 +       CAMIF_CBYCRY = BIT15,
11584 +       CAMIF_CRYCBY = BIT14 | BIT15
11585 +};
11586 +
11587 +enum flip_mode {
11588 +        CAMIF_FLIP   = 0,
11589 +        CAMIF_FLIP_X = BIT14,
11590 +        CAMIF_FLIP_Y = BIT15,
11591 +        CAMIF_FLIP_MIRROR = BIT14 |BIT15,
11592 +};
11593 +
11594 +enum camif_codec_fmt {
11595 +       /* Codec part */
11596 +        CAMIF_IN_YCBCR420  = BIT0, /* Currently IN_YCBCR format fixed */
11597 +        CAMIF_IN_YCBCR422  = BIT1,
11598 +        CAMIF_OUT_YCBCR420 = BIT4,
11599 +        CAMIF_OUT_YCBCR422 = BIT5,
11600 +       /* Preview Part */
11601 +       CAMIF_RGB16        = BIT2,
11602 +       CAMIF_RGB24        = BIT3,
11603 +};
11604 +
11605 +enum camif_capturing {
11606 +        CAMIF_BOTH_DMA_ON  = BIT4,
11607 +       CAMIF_DMA_ON       = BIT3,
11608 +       CAMIF_BOTH_DMA_OFF = BIT1,
11609 +       CAMIF_DMA_OFF      = BIT0,
11610 +       /*------------------------*/
11611 +       CAMIF_DMA_OFF_L_IRQ= BIT5,
11612 +};
11613 +
11614 +typedef struct camif_performance
11615 +{
11616 +       int     frames;
11617 +       int     framesdropped;
11618 +       __u64   bytesin;
11619 +       __u64   bytesout;
11620 +       __u32   reserved[4];
11621 +} camif_perf_t;
11622 +
11623 +
11624 +typedef struct {
11625 +        dma_addr_t  phys_y;
11626 +        dma_addr_t  phys_cb;
11627 +        dma_addr_t  phys_cr;
11628 +        u8          *virt_y;
11629 +        u8          *virt_cb;
11630 +        u8          *virt_cr;
11631 +        dma_addr_t  phys_rgb;
11632 +        u8          *virt_rgb;
11633 +}img_buf_t;
11634 +
11635 +
11636 +/* this structure convers the CIWDOFFST, prescaler, mainscaler */
11637 +typedef struct {
11638 +       u32 modified_src_x;     /* After windows applyed to source_x */
11639 +       u32 modified_src_y;
11640 +       u32 hfactor;
11641 +       u32 vfactor;
11642 +       u32 shfactor;           /* SHfactor = 10 - ( hfactor + vfactor ) */
11643 +       u32 prehratio;
11644 +       u32 prevratio;
11645 +       u32 predst_x;
11646 +       u32 predst_y;
11647 +       u32 scaleup_h;
11648 +       u32 scaleup_v;
11649 +       u32 mainhratio;
11650 +       u32 mainvratio;
11651 +       u32 scalerbypass;       /* only codec */
11652 +} scaler_t;
11653 +
11654 +
11655 +enum v4l2_status {
11656 +        CAMIF_V4L2_INIT    = BIT0,
11657 +        CAMIF_v4L2_DIRTY   = BIT1,
11658 +};
11659 +
11660 +
11661 +/* Global Status Definition */
11662 +#define PWANT2START   BIT0
11663 +#define CWANT2START   BIT1
11664 +#define BOTH_STARTED  (PWANT2START|CWANT2START)
11665 +#define PNOTWORKING   BIT4
11666 +#define C_WORKING     BIT5
11667 +
11668 +typedef struct {
11669 +       struct semaphore         lock;
11670 +        enum camif_itu_fmt       itu_fmt;
11671 +        enum camif_order422      order422;
11672 +       u32                      win_hor_ofst;
11673 +       u32                      win_ver_ofst;
11674 +        u32                      camclk;  /* External Image Sensor Camera Clock */
11675 +        u32                      source_x;
11676 +        u32                      source_y;
11677 +       u32                      polarity_pclk;
11678 +       u32                      polarity_vsync;
11679 +       u32                      polarity_href;
11680 +       struct i2c_client        *sensor;
11681 +       u32                      user; /* MAX 2 (codec, preview) */
11682 +       u32                      old_priority; /* BUS PRIORITY register */
11683 +       u32                      status;
11684 +       u32                      init_sensor;/* initializing sensor */
11685 +       void                     *other;    /* Codec camif_cfg_t */
11686 +       u32                      reset_type;    /* External Sensor Reset  Type */
11687 +       u32                      reset_udelay;
11688 +} camif_gc_t;                  /* gobal control register */
11689 +
11690 +
11691 +/* when  App want to change v4l2 parameter,
11692 + * we instantly store it into v4l2_t v2
11693 + * and then reflect it to hardware
11694 + */
11695 +typedef struct v4l2 {
11696 +       struct v4l2_fmtdesc     *fmtdesc;
11697 +       struct v4l2_pix_format   fmt; /* current pixel format */
11698 +       struct v4l2_input        input;
11699 +        struct video_picture     picture;
11700 +       enum v4l2_status         status;
11701 +       int     used_fmt ;      /* used format index  */
11702 +} v4l2_t;
11703 +
11704 +
11705 +typedef struct camif_c_t {
11706 +        struct video_device      *v;
11707 +       /* V4L2 param only for v4l2 driver */
11708 +       v4l2_t                    v2;
11709 +       camif_gc_t               *gc; /* Common between Codec and Preview */
11710 +       /* logical parameter */
11711 +       wait_queue_head_t        waitq;
11712 +       u32                      status; /* Start/Stop */
11713 +       u32                      fsm; /* Start/Stop */
11714 +       u32                      open_count; /* duplicated */
11715 +       int                      irq;
11716 +       char                     shortname[16];
11717 +        u32                      target_x;
11718 +        u32                      target_y;
11719 +       scaler_t                 sc;
11720 +       enum flip_mode           flip;
11721 +        enum camif_dma_type      dma_type;
11722 +       /* 4 pingpong Frame memory */
11723 +        u8                       *pp_virt_buf;
11724 +        dma_addr_t               pp_phys_buf;
11725 +        u32                      pp_totalsize;
11726 +       u32                      pp_num; /* used pingpong memory number */
11727 +        img_buf_t                img_buf[4];
11728 +        enum camif_codec_fmt     fmt;
11729 +        enum camif_capturing     exec;
11730 +       camif_perf_t             perf;
11731 +       u32                      now_frame_num;
11732 +       u32                      auto_restart; /* Only For Preview */
11733 +} camif_cfg_t;
11734 +
11735 +#ifdef SW_DEBUG
11736 +#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
11737 +#else
11738 +#define DPRINTK(fmt, args...)
11739 +#endif
11740 +
11741 +
11742 +#ifdef SW_DEBUG
11743 +#define assert(expr) \
11744 +        if(!(expr)) {                                   \
11745 +        printk( "Assertion failed! %s,%s,%s,line=%d\n", \
11746 +        #expr,__FILE__,__FUNCTION__,__LINE__);          \
11747 +        }
11748 +#else
11749 +#define assert(expr)
11750 +#endif
11751 +
11752 +
11753 +
11754 +extern int camif_capture_start(camif_cfg_t *);
11755 +extern int camif_capture_stop(camif_cfg_t *);
11756 +extern int camif_g_frame_num(camif_cfg_t *);
11757 +extern u8 * camif_g_frame(camif_cfg_t *);
11758 +extern int  camif_win_offset(camif_gc_t *);
11759 +extern void camif_hw_open(camif_gc_t *);
11760 +extern void camif_hw_close(camif_cfg_t *);
11761 +extern int camif_dynamic_open(camif_cfg_t *);
11762 +extern int camif_dynamic_close(camif_cfg_t *);
11763 +extern void camif_reset(int,int);
11764 +extern void camif_setup_sensor(void);
11765 +extern int camif_g_fifo_status(camif_cfg_t *);
11766 +extern void camif_last_irq_en(camif_cfg_t *);
11767 +extern void camif_change_flip(camif_cfg_t *);
11768 +
11769 +
11770 +/* Todo
11771 + *  API Interface function to both Character and V4L2 Drivers
11772 + */
11773 +extern int camif_do_write(struct file *,const char *, size_t, loff_t *);
11774 +extern int camif_do_ioctl(struct inode *, struct file *,unsigned int, void *);
11775 +
11776 +
11777 +/*
11778 + * API for Decoder (S5x532, OV7620..)
11779 + */
11780 +void camif_register_decoder(struct i2c_client *);
11781 +void camif_unregister_decoder(struct i2c_client*);
11782 +
11783 +
11784 +
11785 +/* API for FSM */
11786 +#define INSTANT_SKIP 0
11787 +#define INSTANT_GO   1
11788 +
11789 +extern ssize_t camif_p_1fsm_start(camif_cfg_t *);
11790 +extern ssize_t camif_p_2fsm_start(camif_cfg_t *);
11791 +extern ssize_t camif_4fsm_start(camif_cfg_t *);
11792 +extern ssize_t camif_p_stop(camif_cfg_t *);
11793 +extern int camif_enter_p_4fsm(camif_cfg_t *);
11794 +extern int camif_enter_c_4fsm(camif_cfg_t *);
11795 +extern int camif_enter_2fsm(camif_cfg_t *);
11796 +extern int camif_enter_1fsm(camif_cfg_t *);
11797 +extern int camif_check_preview(camif_cfg_t *);
11798 +extern int camif_callback_start(camif_cfg_t *);
11799 +extern int camif_clock_init(camif_gc_t *);
11800 +
11801 +/*
11802 + *  V4L2 Part
11803 + */
11804 +#define VID_HARDWARE_SAMSUNG_FIMC20   236
11805 +
11806 +
11807 +
11808 +
11809 +
11810 +#endif
11811 +
11812 +
11813 +/*
11814 + * Local variables:
11815 + * tab-width: 8
11816 + *  c-indent-level: 8
11817 + *  c-basic-offset: 8
11818 + *  c-set-style: "K&R"
11819 + * End:
11820 + */
11821 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/cam_reg.h
11822 ===================================================================
11823 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
11824 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/cam_reg.h 2009-01-02 00:01:56.000000000 +0100
11825 @@ -0,0 +1,234 @@
11826 + /*----------------------------------------------------------
11827 +  *   (C) 2004 Samsung Electronics
11828 +  *   SW.LEE < hitchcar@samsung.com>
11829 +  *
11830 +  ----------------------------------------------------------- */
11831 +
11832 +#ifndef __FIMC20_CAMERA_H__
11833 +#define __FIMC20_CAMERA_H__
11834 +
11835 +extern u32 * camregs;
11836 +
11837 +#ifdef CONFIG_ARCH_S3C24A0
11838 +#define CAM_BASE_ADD             0x48000000
11839 +#else /* S3C2440A */
11840 +#define CAM_BASE_ADD             0x4F000000
11841 +#endif
11842 +
11843 +#if ! defined(FExtr)
11844 +#define UData(Data)     ((unsigned long) (Data))
11845 +#define FExtr(Data, Field) \
11846 +                        ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
11847 +#define FInsrt(Value, Field) \
11848 +                        (UData (Value) << FShft (Field))
11849 +#define FSize(Field)    ((Field) >> 16)
11850 +#define FShft(Field)    ((Field) & 0x0000FFFF)
11851 +#define FMsk(Field)     (((UData (1) << FSize (Field)) - 1) << FShft (Field))
11852 +#define FAlnMsk(Field)  ((UData (1) << FSize (Field)) - 1)
11853 +#define F1stBit(Field)  (UData (1) << FShft (Field))
11854 +#define Fld(Size, Shft) (((Size) << 16) + (Shft))
11855 +#endif
11856 +
11857 +/*
11858 + * CAMERA IP
11859 + * P-port is used as RGB Capturing device which including scale and crop
11860 + *  those who want to see(preview ) the image on display needs RGB image.
11861 + *
11862 + * C-port is used as YCbCr(4:2:0, 4:2:2) Capturing device which including the scale and crop
11863 + *   the prefix of C-port have the meaning of "Codec" ex. mpeg4, h263.. which requries the
11864 +     YCBCB format not RGB
11865 + */
11866 +
11867 +#define S3C2440_CAM_REG_CISRCFMT            (0x00) // RW Input Source Format
11868 +#define S3C2440_CAM_REG_CIWDOFST            (0x04) // Window offset register
11869 +#define S3C2440_CAM_REG_CIGCTRL             (0x08) // Global control register
11870 +#define S3C2440_CAM_REG_CICOYSA0            (0x18) // Y 1 st frame start ads
11871 +#define S3C2440_CAM_REG_CICOYSA1            (0x1C) // Y 2 nd frame start ads
11872 +#define S3C2440_CAM_REG_CICOYSA2            (0x20) // Y 3 rd frame start ads
11873 +#define S3C2440_CAM_REG_CICOYSA3            (0x24) // Y 4 th frame start ads
11874 +#define S3C2440_CAM_REG_CICOCBSA0           (0x28) // Cb 1 st frame start ads
11875 +#define S3C2440_CAM_REG_CICOCBSA1           (0x2C) // Cb 2 nd frame start ads
11876 +#define S3C2440_CAM_REG_CICOCBSA2           (0x30) // Cb 3 rd frame start ads
11877 +#define S3C2440_CAM_REG_CICOCBSA3           (0x34) // Cb 4 th frame start ads
11878 +#define S3C2440_CAM_REG_CICOCRSA0           (0x38) // Cr 1 st frame start ads
11879 +#define S3C2440_CAM_REG_CICOCRSA1           (0x3C) // Cr 2 nd frame start ads
11880 +#define S3C2440_CAM_REG_CICOCRSA2           (0x40) // Cr 3 rd frame start ads
11881 +#define S3C2440_CAM_REG_CICOCRSA3           (0x44) // Cr 4 th frame start ads
11882 +#define S3C2440_CAM_REG_CICOTRGFMT          (0x48) // Target img format of codec
11883 +#define S3C2440_CAM_REG_CICOCTRL            (0x4C) // Codec DMA control related
11884 +#define S3C2440_CAM_REG_CICOSCPRERATIO      (0x50) // Codec pre-scaler ratio
11885 +#define S3C2440_CAM_REG_CICOSCPREDST        (0x54) // Codec pre-scaler dest
11886 +#define S3C2440_CAM_REG_CICOSCCTRL          (0x58) // Codec main-scaler control
11887 +#define S3C2440_CAM_REG_CICOTAREA           (0x5C) // Codec pre-scaler dest
11888 +#define S3C2440_CAM_REG_CICOSTATUS          (0x64) // Codec path status
11889 +#define S3C2440_CAM_REG_CIPRCLRSA0          (0x6C) // RGB 1 st frame start ads
11890 +#define S3C2440_CAM_REG_CIPRCLRSA1          (0x70) // RGB 2 nd frame start ads
11891 +#define S3C2440_CAM_REG_CIPRCLRSA2          (0x74) // RGB 3 rd frame start ads
11892 +#define S3C2440_CAM_REG_CIPRCLRSA3          (0x78) // RGB 4 th frame start ads
11893 +#define S3C2440_CAM_REG_CIPRTRGFMT          (0x7C) // Target img fmt of preview
11894 +#define S3C2440_CAM_REG_CIPRCTRL            (0x80) // Preview DMA ctl related
11895 +#define S3C2440_CAM_REG_CIPRSCPRERATIO      (0x84) // Preview pre-scaler ratio
11896 +#define S3C2440_CAM_REG_CIPRSCPREDST        (0x88) // Preview pre-scaler dest
11897 +#define S3C2440_CAM_REG_CIPRSCCTRL          (0x8C) // Preview main-scaler ctl
11898 +#define S3C2440_CAM_REG_CIPRTAREA           (0x90) // Preview pre-scaler dest
11899 +#define S3C2440_CAM_REG_CIPRSTATUS          (0x98) // Preview path status
11900 +#define S3C2440_CAM_REG_CIIMGCPT            (0xA0) // Image capture enable cmd
11901 +
11902 +#define S3C2440_CAM_REG_CICOYSA(__x)        (0x18 + (__x)*4 )
11903 +#define S3C2440_CAM_REG_CICOCBSA(__x)       (0x28 + (__x)*4 )
11904 +#define S3C2440_CAM_REG_CICOCRSA(__x)       (0x38 + (__x)*4 )
11905 +#define S3C2440_CAM_REG_CIPRCLRSA(__x)      (0x6C + (__x)*4 )
11906 +
11907 +/* CISRCFMT BitField */
11908 +#define SRCFMT_ITU601       BIT31
11909 +#define SRCFMT_ITU656       0
11910 +#define SRCFMT_UVOFFSET_128 BIT30
11911 +#define fCAM_SIZE_H         Fld(13, 16)
11912 +#define fCAM_SIZE_V         Fld(13, 0)
11913 +#define SOURCE_HSIZE(x)     FInsrt((x), fCAM_SIZE_H)
11914 +#define SOURCE_VSIZE(x)     FInsrt((x), fCAM_SIZE_V)
11915 +
11916 +
11917 +/* Window Option Register */
11918 +#define WINOFEN             BIT31
11919 +#define CO_FIFO_Y           BIT30
11920 +#define CO_FIFO_CB          BIT15
11921 +#define CO_FIFO_CR          BIT14
11922 +#define PR_FIFO_CB          BIT13
11923 +#define PR_FIFO_CR          BIT12
11924 +#define fWINHOR             Fld(11, 16)
11925 +#define fWINVER             Fld(11, 0)
11926 +#define WINHOROFST(x)       FInsrt((x), fWINHOR)
11927 +#define WINVEROFST(x)       FInsrt((x), fWINVER)
11928 +
11929 +/* Global Control Register */
11930 +#define GC_SWRST            BIT31
11931 +#define GC_CAMRST           BIT30
11932 +#define GC_INVPOLPCLK       BIT26
11933 +#define GC_INVPOLVSYNC      BIT25
11934 +#define GC_INVPOLHREF       BIT24
11935 +
11936 +/*--------------------------------------------------
11937 +                REGISTER BIT FIELD DEFINITION TO
11938 +                          YCBCR and RGB
11939 +----------------------------------------------------*/
11940 +/* Codec Target Format Register */
11941 +#define IN_YCBCR420         0
11942 +#define IN_YCBCR422         BIT31
11943 +#define OUT_YCBCR420        0
11944 +#define OUT_YCBCR422        BIT30
11945 +
11946 +#if 0
11947 +#define FLIP_NORMAL        0
11948 +#define FLIP_X              (BIT14)
11949 +#define FLIP_Y              (BIT15)
11950 +#define FLIP_MIRROR         (BIT14|BIT15)
11951 +#endif
11952 +
11953 +/**  BEGIN    ************************************/
11954 +/* Cotents: Common in both P and C port          */
11955 +#define fTARGET_HSIZE       Fld(13,16)
11956 +#define TARGET_HSIZE(x)     FInsrt((x), fTARGET_HSIZE)
11957 +#define fTARGET_VSIZE       Fld(13,0)
11958 +#define TARGET_VSIZE(x)     FInsrt((x), fTARGET_VSIZE)
11959 +#define FLIP_X_MIRROR       BIT14
11960 +#define FLIP_Y_MIRROR       BIT15
11961 +#define FLIP_180_MIRROR     (BIT14 | BIT15)
11962 +/**  END     *************************************/
11963 +
11964 +/* Codec DMA Control Register */
11965 +#define fYBURST_M           Fld(5,19)
11966 +#define fYBURST_R           Fld(5,14)
11967 +#define fCBURST_M           Fld(5,9)
11968 +#define fCBURST_R           Fld(5,4)
11969 +#define YBURST_M(x)         FInsrt((x), fYBURST_M)
11970 +#define CBURST_M(x)         FInsrt((x), fCBURST_M)
11971 +#define YBURST_R(x)         FInsrt((x), fYBURST_R)
11972 +#define CBURST_R(x)         FInsrt((x), fCBURST_R)
11973 +#define LAST_IRQ_EN         BIT2              /* Common in both P and C port */
11974 +/*
11975 + *  Check the done signal of capturing image for JPEG
11976 + *  !!! AutoClear Bit
11977 + */
11978 +
11979 +
11980 +/* (Codec, Preview ) Pre-Scaler Control Register 1 */
11981 +#define fSHIFT              Fld(4,28)
11982 +#define PRE_SHIFT(x)        FInsrt((x), fSHIFT)
11983 +#define fRATIO_H            Fld(7,16)
11984 +#define PRE_HRATIO(x)       FInsrt((x), fRATIO_H)
11985 +#define fRATIO_V            Fld(7,0)
11986 +#define PRE_VRATIO(x)       FInsrt((x), fRATIO_V)
11987 +
11988 +/* (Codec, Preview ) Pre-Scaler Control Register 2*/
11989 +#define fDST_WIDTH          Fld(12,16)
11990 +#define fDST_HEIGHT         Fld(12,0)
11991 +#define PRE_DST_WIDTH(x)    FInsrt((x), fDST_WIDTH)
11992 +#define PRE_DST_HEIGHT(x)   FInsrt((x), fDST_HEIGHT)
11993 +
11994 +
11995 +/* (Codec, Preview) Main-scaler control Register */
11996 +#define S_METHOD            BIT31  /* Sampling method only for P-port */
11997 +#define SCALERSTART         BIT15
11998 +/* Codec scaler bypass for upper 2048x2048
11999 +   where ImgCptEn_CoSC and ImgCptEn_PrSC should be 0
12000 +*/
12001 +
12002 +#define SCALERBYPASS        BIT31
12003 +#define RGB_FMT24           BIT30
12004 +#define RGB_FMT16           0
12005 +
12006 +/*
12007 +#define SCALE_UP_H          BIT29
12008 +#define SCALE_UP_V          BIT28
12009 +*/
12010 +
12011 +#define fMAIN_HRATIO        Fld(9, 16)
12012 +#define MAIN_HRATIO(x)      FInsrt((x), fMAIN_HRATIO)
12013 +
12014 +#define SCALER_START        BIT15
12015 +
12016 +#define fMAIN_VRATIO        Fld(9, 0)
12017 +#define MAIN_VRATIO(x)      FInsrt((x), fMAIN_VRATIO)
12018 +
12019 +/* (Codec, Preview ) DMA Target AREA Register */
12020 +#define fCICOTAREA          Fld(26,0)
12021 +#define TARGET_DMA_AREA(x)  FInsrt((x), fCICOTAREA)
12022 +
12023 +/* Preview DMA Control Register */
12024 +#define fRGBURST_M          Fld(5,19)
12025 +#define fRGBURST_R          Fld(5,14)
12026 +#define RGBURST_M(x)        FInsrt((x), fRGBURST_M)
12027 +#define RGBURST_R(x)        FInsrt((x), fRGBURST_R)
12028 +
12029 +
12030 +/* (Codec, Preview) Status Register */
12031 +#define CO_OVERFLOW_Y       BIT31
12032 +#define CO_OVERFLOW_CB      BIT30
12033 +#define CO_OVERFLOW_CR      BIT29
12034 +#define PR_OVERFLOW_CB      BIT31
12035 +#define PR_OVERFLOW_CR      BIT30
12036 +
12037 +#define VSYNC               BIT28
12038 +
12039 +#define fFRAME_CNT          Fld(2,26)
12040 +#define FRAME_CNT(x)        FExtr((x),fFRAME_CNT)
12041 +
12042 +#define WIN_OFF_EN          BIT25
12043 +#define fFLIP_MODE          Fld(2,23)
12044 +#define FLIP_MODE(x)        EExtr((x), fFLIP_MODE)
12045 +#define CAP_STATUS_CAMIF    BIT22
12046 +#define CAP_STATUS_CODEC    BIT21
12047 +#define CAP_STATUS_PREVIEW  BIT21
12048 +#define VSYNC_A             BIT20
12049 +#define VSYNC_B             BIT19
12050 +
12051 +/* Image Capture Enable Regiser */
12052 +#define        CAMIF_CAP_ON         BIT31
12053 +#define CAMIF_CAP_CODEC_ON   BIT30
12054 +#define CAMIF_CAP_PREVIEW_ON BIT29
12055 +
12056 +
12057 +
12058 +
12059 +#endif /* S3C2440_CAMER_H */
12060 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/imgsensor.c
12061 ===================================================================
12062 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12063 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/imgsensor.c       2009-01-02 00:01:56.000000000 +0100
12064 @@ -0,0 +1,250 @@
12065 +/*
12066 + *  Copyright (C) 2004 Samsung Electronics
12067 + *             SW.LEE <hitchcar@samsung.com>
12068 + *
12069 + *  Copyright (C) 2000 Russell King : pcf8583.c
12070 + *
12071 + * This program is free software; you can redistribute it and/or modify
12072 + * it under the terms of the GNU General Public License version 2 as
12073 + * published by the Free Software Foundation.
12074 + *
12075 + *  Driver for FIMC20 Camera Decoder
12076 + */
12077 +
12078 +
12079 +#include <linux/module.h>
12080 +#include <linux/kernel.h>
12081 +#include <linux/init.h>
12082 +#include <linux/i2c.h>
12083 +#include <linux/slab.h>
12084 +#include <linux/string.h>
12085 +#include <linux/init.h>
12086 +#include <linux/delay.h>
12087 +
12088 +
12089 +#ifdef CONFIG_ARCH_S3C24A0A
12090 +#else
12091 +//#include <asm/arch/S3C2440.h>
12092 +#endif
12093 +
12094 +#define SW_DEBUG
12095 +#define CONFIG_VIDEO_V4L1_COMPAT
12096 +#include <linux/videodev.h>
12097 +#include "camif.h"
12098 +#include "sensor.h"
12099 +
12100 +#ifndef SAMSUNG_SXGA_CAM
12101 +#include "s5x532_rev36.h"
12102 +#else
12103 +#include "sxga.h"
12104 +#endif
12105 +
12106 +static struct i2c_driver s5x532_driver;
12107 +static camif_gc_t data = {
12108 +       itu_fmt:      CAMIF_ITU601,
12109 +       order422:     CAMIF_YCBYCR,
12110 +       camclk:       24000000,
12111 +#ifndef SAMSUNG_SXGA_CAM
12112 +       source_x:     640,
12113 +       source_y:     480,
12114 +       win_hor_ofst: 112,
12115 +       win_ver_ofst: 20,
12116 +#else
12117 +       source_x:     1280,
12118 +       source_y:     1024,
12119 +       win_hor_ofst: 0,
12120 +       win_ver_ofst: 0,
12121 +#endif
12122 +       polarity_pclk:1,
12123 +       polarity_href:0,
12124 +#ifdef CONFIG_ARCH_S3C24A0A
12125 +       reset_type:CAMIF_EX_RESET_AL, /* Active Low */
12126 +#else
12127 +       reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
12128 +#endif
12129 +       reset_udelay:2000,
12130 +};
12131 +
12132 +#define CAM_ID 0x5a
12133 +
12134 +static unsigned short ignore = I2C_CLIENT_END;
12135 +static unsigned short normal_addr[] = { (CAM_ID>>1), I2C_CLIENT_END };
12136 +static struct i2c_client_address_data addr_data = {
12137 +       normal_i2c:             normal_addr,
12138 +       probe:                  &ignore,
12139 +       ignore:                 &ignore,
12140 +};
12141 +
12142 +s5x532_t s5x532_regs_mirror[S5X532_REGS];
12143 +
12144 +unsigned char
12145 +s5x532_read(struct i2c_client *client, unsigned char subaddr)
12146 +{
12147 +       int ret;
12148 +       unsigned char buf[1];
12149 +       struct i2c_msg msg ={ client->addr, 0, 1, buf};
12150 +       buf[0] = subaddr;
12151 +
12152 +       ret = i2c_transfer(client->adapter,&msg, 1) == 1 ? 0 : -EIO;
12153 +       if (ret == -EIO) {
12154 +         printk(" I2C write Error \n");
12155 +         return -EIO;
12156 +       }
12157 +
12158 +       msg.flags = I2C_M_RD;
12159 +       ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
12160 +
12161 +       return buf[0];
12162 +}
12163 +
12164 +
12165 +static int
12166 +s5x532_write(struct i2c_client *client,
12167 +                 unsigned char subaddr, unsigned char val)
12168 +{
12169 +       unsigned char buf[2];
12170 +       struct i2c_msg msg = { client->addr, 0, 2, buf};
12171 +
12172 +       buf[0]= subaddr;
12173 +       buf[1]= val;
12174 +
12175 +       return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
12176 +}
12177 +
12178 +void inline s5x532_init(struct i2c_client *sam_client)
12179 +{
12180 +       int i;
12181 +
12182 +       printk(KERN_ERR "s5x532_init  \n");
12183 +       for (i = 0; i < S5X532_INIT_REGS; i++) {
12184 +               s5x532_write(sam_client,
12185 +                             s5x532_reg[i].subaddr, s5x532_reg[i].value );
12186 +       }
12187 +
12188 +#ifdef YOU_WANT_TO_CHECK_IMG_SENSOR
12189 +       for (i = 0; i < S5X532_INIT_REGS;i++) {
12190 +               if ( s5x532_reg[i].subaddr == PAGE_ADDRESS ) {
12191 +                       s5x532_write(sam_client,
12192 +                             s5x532_reg[i].subaddr, s5x532_reg[i].value);
12193 +
12194 +                       printk(KERN_ERR "Page: Subaddr %02x = 0x%02x\n",
12195 +                              s5x532_reg[i].subaddr, s5x532_regs_mirror[i].value);
12196 +
12197 +
12198 +               } else
12199 +               {
12200 +                       s5x532_regs_mirror[i].subaddr = s5x532_reg[i].subaddr;
12201 +                       s5x532_regs_mirror[i].value =
12202 +                       s5x532_read(sam_client,s5x532_reg[i].subaddr);
12203 +                       printk(KERN_ERR "Subaddr %02x = 0x%02x\n",
12204 +                              s5x532_reg[i].subaddr, s5x532_regs_mirror[i].value);
12205 +               }
12206 +       }
12207 +#endif
12208 +
12209 +}
12210 +
12211 +static int
12212 +s5x532_attach(struct i2c_adapter *adap, int addr, int kind)
12213 +{
12214 +       struct i2c_client *c;
12215 +
12216 +       c = kmalloc(sizeof(*c), GFP_KERNEL);
12217 +       if (!c) return -ENOMEM;
12218 +
12219 +       strcpy(c->name, "S5X532");
12220 +//     c->id           = s5x532_driver.id;
12221 +       c->flags        = 0 /* I2C_CLIENT_ALLOW_USE */;
12222 +       c->addr         = addr;
12223 +       c->adapter      = adap;
12224 +       c->driver       = &s5x532_driver;
12225 +       data.sensor     = c;
12226 +       i2c_set_clientdata(c, &data);
12227 +
12228 +       camif_register_decoder(c);
12229 +       return i2c_attach_client(c);
12230 +}
12231 +
12232 +static int s5x532_probe(struct i2c_adapter *adap)
12233 +{
12234 +       return i2c_probe(adap, &addr_data, s5x532_attach);
12235 +}
12236 +
12237 +static int s5x532_detach(struct i2c_client *client)
12238 +{
12239 +       i2c_detach_client(client);
12240 +       camif_unregister_decoder(client);
12241 +       return 0;
12242 +}
12243 +
12244 +static int
12245 +s5x532_command(struct i2c_client *client, unsigned int cmd, void *arg)
12246 +{
12247 +        switch (cmd) {
12248 +        case SENSOR_INIT:
12249 +                 s5x532_init(client);
12250 +                printk(KERN_INFO "CAMERA: S5X532 Sensor initialized\n");
12251 +                break;
12252 +       case USER_ADD:
12253 +               /* MOD_INC_USE_COUNT; uh.. 2.6 deals with this, old-timer */
12254 +               break;
12255 +       case USER_EXIT:
12256 +               /* MOD_DEC_USE_COUNT; */
12257 +               break;
12258 +/* Todo
12259 +       case SENSOR_BRIGHTNESS:
12260 +               change_sensor();
12261 +               break;
12262 +*/
12263 +       default:
12264 +               panic("Unexpect Sensor Command \n");
12265 +               break;
12266 +        }
12267 +       return 0;
12268 +}
12269 +
12270 +static struct i2c_driver s5x532_driver = {
12271 +       driver:         { name:         "S5X532" },
12272 +       id:             0, /* optional in i2c-id.h I2C_ALGO_S3C, */
12273 +       attach_adapter: s5x532_probe,
12274 +       detach_client:  s5x532_detach,
12275 +       command:        s5x532_command
12276 +};
12277 +
12278 +static void iic_gpio_port(void)
12279 +{
12280 +/*    FIXME: no gpio config for i2c !!!
12281 +#ifdef CONFIG_ARCH_S3C24A0A
12282 +#else
12283 +       GPECON &=  ~(0xf <<28);
12284 +       GPECON |=    0xa <<28;
12285 +#endif
12286 +*/
12287 +}
12288 +
12289 +static __init int camif_sensor_init(void)
12290 +{
12291 +        iic_gpio_port();
12292 +       return i2c_add_driver(&s5x532_driver);
12293 +}
12294 +
12295 +
12296 +static __init void camif_sensor_exit(void)
12297 +{
12298 +       i2c_del_driver(&s5x532_driver);
12299 +}
12300 +
12301 +module_init(camif_sensor_init)
12302 +module_exit(camif_sensor_exit)
12303 +
12304 +MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
12305 +MODULE_DESCRIPTION("I2C Client Driver For Fimc2.0 MISC Driver");
12306 +MODULE_LICENSE("GPL");
12307 +
12308 +
12309 +
12310 +/*
12311 + * Local variables:
12312 + * c-basic-offset: 8
12313 + * End:
12314 + */
12315 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/Kconfig
12316 ===================================================================
12317 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12318 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/Kconfig   2009-01-02 00:01:56.000000000 +0100
12319 @@ -0,0 +1,7 @@
12320 +
12321 +config S3C2440_CAMERA
12322 +       bool "S3C24xx Camera interface"
12323 +       depends on ARCH_S3C2410
12324 +       help
12325 +         Camera driver for S3C2440 camera unit
12326 +
12327 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/Makefile
12328 ===================================================================
12329 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12330 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/Makefile  2009-01-02 00:01:56.000000000 +0100
12331 @@ -0,0 +1,8 @@
12332 +obj-$(CONFIG_S3C2440_CAMERA) += \
12333 +       videodev.o \
12334 +       imgsensor.o \
12335 +       video-driver.o \
12336 +       camif.o \
12337 +       camif_fsm.o \
12338 +       qt-driver.o
12339 +
12340 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/miscdevice.h
12341 ===================================================================
12342 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12343 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/miscdevice.h      2009-01-02 00:01:56.000000000 +0100
12344 @@ -0,0 +1,18 @@
12345 +
12346 + /*----------------------------------------------------------
12347 +  *   (C) 2004 Samsung Electronics
12348 +  *   SW.LEE < hitchcar@samsung.com>
12349 +  *
12350 +  ----------------------------------------------------------- */
12351 +
12352 +#ifndef _LINUX_S3C_MISCDEVICE_H
12353 +#define _LINUX_S3C_MISCDEVICE_H
12354 +
12355 +#define CODEC_MINOR 212
12356 +#define PREVIEW_MINOR 213
12357 +
12358 +
12359 +
12360 +
12361 +
12362 +#endif
12363 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/qt-driver.c
12364 ===================================================================
12365 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12366 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/qt-driver.c       2009-01-02 00:01:56.000000000 +0100
12367 @@ -0,0 +1,172 @@
12368 +/*
12369 + * SW.LEE <hitchcar@samsung.com>
12370 + *
12371 + * This file is subject to the terms and conditions of the GNU General Public
12372 + * License 2. See the file COPYING in the main directory of this archive
12373 + * for more details.
12374 + */
12375 +
12376 +#include <linux/version.h>
12377 +#include <linux/module.h>
12378 +#include <linux/delay.h>
12379 +#include <linux/errno.h>
12380 +#include <linux/fs.h>
12381 +#include <linux/kernel.h>
12382 +#include <linux/major.h>
12383 +#include <linux/slab.h>
12384 +#include <linux/poll.h>
12385 +#include <linux/signal.h>
12386 +#include <linux/ioport.h>
12387 +#include <linux/sched.h>
12388 +#include <linux/types.h>
12389 +#include <linux/interrupt.h>
12390 +#include <linux/kmod.h>
12391 +#include <linux/vmalloc.h>
12392 +#include <linux/init.h>
12393 +#include <asm/io.h>
12394 +#include <asm/page.h>
12395 +#include <asm/irq.h>
12396 +#include <asm/semaphore.h>
12397 +#include <linux/miscdevice.h>
12398 +
12399 +//#define SW_DEBUG
12400 +
12401 +#define CONFIG_VIDEO_V4L1_COMPAT
12402 +#include <linux/videodev.h>
12403 +#include "camif.h"
12404 +#include "miscdevice.h"
12405 +#include "cam_reg.h"
12406 +#include "sensor.h"
12407 +#include "userapp.h"
12408 +
12409 +extern camif_cfg_t * get_camif(int nr);
12410 +
12411 +
12412 +/************************* Sharp Zarus API **************************
12413 +* refering to Camera Driver API for SL-5000D/SL-5600 revision 1.00
12414 +*                              April 11, 2002.
12415 +  SW.LEE <hitchcar@sec.samsung.com>
12416 +               I want to use Sharp Camera Application.
12417 +*
12418 +*/
12419 +
12420 +#define READ_MODE_STATUS       0x1
12421 +#define READ_MODE_IMAGE                0x0
12422 +#define CAPTURE_SPEED
12423 +#define        H_FLIP
12424 +#define V_FLIP
12425 +typedef enum sharp_readmode
12426 +{
12427 +        IMAGE = 0, STATUS = 1,
12428 +        FASTER = 0, BETTER = 2,
12429 +        XNOFLIP = 0, XFLIP = 4,
12430 +        YNOFLIP = 0, YFLIP = 8,
12431 +        AUTOMATICFLIP = -1
12432 +} ReadMode_t;
12433 +
12434 +
12435 +static struct sharp_param_t {
12436 +       ReadMode_t readMode;
12437 +       char CameraStatus[4];
12438 +} sharp_param = { STATUS, {'s','m','c','A'}};
12439 +
12440 +
12441 +camif_param_t qt_parm = { 640,480,240,320,16,0};
12442 +
12443 +static void setReadMode(const char *b,size_t count)
12444 +{
12445 +       int i =   *(b+2) - 48 ;
12446 +       if ( 4 == count ) {
12447 +               i = (*(b+3) - 48)  + i * 10;
12448 +       }
12449 +
12450 +       //      DPRINTK(" setReadMode %s conversion value %d \n",b , i);
12451 +       if ( i & STATUS ) {
12452 +       //      DPRINTK(" STATUS MODE \n");
12453 +               sharp_param.readMode = i;
12454 +       }
12455 +       else  {
12456 +       //      DPRINTK(" IMAGE MODE \n");
12457 +               sharp_param.readMode = i;
12458 +       }
12459 +}
12460 +
12461 +
12462 +
12463 +
12464 +extern ssize_t camif_p_read(struct file *, char *, size_t , loff_t *);
12465 +
12466 +ssize_t z_read(struct file *f, char *buf, size_t count, loff_t *pos)
12467 +{
12468 +       size_t end;
12469 +
12470 +       if (sharp_param.readMode & STATUS ) {
12471 +               buf[0] = sharp_param.CameraStatus[0];
12472 +               buf[1] = sharp_param.CameraStatus[1];
12473 +               buf[2] = sharp_param.CameraStatus[2];
12474 +               buf[3] = sharp_param.CameraStatus[3];
12475 +               end = 4;
12476 +               return end;
12477 +       }
12478 +       else {  /* Image ReadMode */
12479 +               /*
12480 +               if (( sharp_param.readMode & (BETTER|X  FLIP|YFLIP)))
12481 +                       DPRINTK("  Not Supporting BETTER|XFLIP|YFLIP\n");
12482 +               */
12483 +               return camif_p_read(f,buf,count,pos);
12484 +       }
12485 +}
12486 +
12487 +static void z_config(camif_cfg_t *cfg,int x, int y)
12488 +{
12489 +       cfg->target_x = x;
12490 +       cfg->target_y = y;
12491 +       cfg->fmt = CAMIF_RGB16;
12492 +       if (camif_dynamic_open(cfg)) {
12493 +               panic(" Eror Happens \n");
12494 +       }
12495 +}
12496 +
12497 +
12498 +ssize_t z_write(struct file *f, const char *b, size_t c, loff_t *pos)
12499 +{
12500 +       int array[5];
12501 +       int zoom = 1;
12502 +       camif_cfg_t *cfg;
12503 +
12504 +       cfg = get_camif(MINOR(f->f_dentry->d_inode->i_rdev));
12505 +//     DPRINTK(" param %s count %d \n",b, c );
12506 +
12507 +       switch(*b) {
12508 +       case 'M':
12509 +               setReadMode(b, c);
12510 +               break;
12511 +       case 'B':       /* Clear the latch flag of shutter button */
12512 +               DPRINTK("  clear latch flag of camera's shutter button\n");
12513 +               sharp_param.CameraStatus[0]='s';
12514 +               break;
12515 +       case 'Y':       /* I don't know how to set Shutter pressed */
12516 +               DPRINTK("  set latch flag n");
12517 +               sharp_param.CameraStatus[0]='S';
12518 +               break;
12519 +       case 'S':       /* Camera Image Resolution */
12520 +       case 'R':       /* Donot support Rotation */
12521 +       DPRINTK(" param %s count %d \n",b, c );
12522 +               get_options((char *)(b+2), 5, array);
12523 +               if ( array[3] == 512 ) zoom = 2;
12524 +               z_config(cfg, array[1] * zoom , array[2] * zoom );
12525 +               camif_4fsm_start(cfg);
12526 +               break;
12527 +       case 'C':
12528 +       DPRINTK(" param %s count %d \n",b, c );
12529 +               DPRINTK("  Start the camera to capture \n");
12530 +               sharp_param.CameraStatus[2]='C';
12531 +               camif_4fsm_start(cfg);
12532 +               break;
12533 +       default:
12534 +               printk("Unexpected  param %s count %d \n",b, c );
12535 +       }
12536 +
12537 +       return c;
12538 +}
12539 +
12540 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/qt.h
12541 ===================================================================
12542 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12543 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/qt.h      2009-01-02 00:01:56.000000000 +0100
12544 @@ -0,0 +1,18 @@
12545 +/*
12546 + * SW.LEE <hitchcar@samsung.com>
12547 + *
12548 + * This file is subject to the terms and conditions of the GNU General Public
12549 + * License 2. See the file COPYING in the main directory of this archive
12550 + * for more details.
12551 + */
12552 +
12553 +#ifndef __Z_API_H_
12554 +#define __Z_API_H_
12555 +
12556 +extern ssize_t z_read(struct file *f, char *buf, size_t count, loff_t *pos);
12557 +extern ssize_t z_write(struct file *f, const char *b, size_t c, loff_t *pos);
12558 +
12559 +
12560 +
12561 +#endif
12562 +
12563 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/s5x532.h
12564 ===================================================================
12565 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12566 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/s5x532.h  2009-01-02 00:01:56.000000000 +0100
12567 @@ -0,0 +1,143 @@
12568 +/*
12569 + * 2004 (C) Samsung Electronics
12570 + *  SW.LEE <hitchcar@sec.samsung.com>
12571 + * This file is subject to the terms and conditions of the GNU General Public
12572 + * License 2. See the file COPYING in the main directory of this archive
12573 + * for more details.
12574 + */
12575 +
12576 +
12577 +#ifndef _SMDK2440_S5X532_H_
12578 +#define _SMDK2440_S5X532_H_
12579 +
12580 +
12581 +#define CHIP_DELAY 0xFF
12582 +
12583 +typedef struct samsung_t{
12584 +       unsigned char subaddr;
12585 +       unsigned char value;
12586 +       unsigned char page;
12587 +} s5x532_t;
12588 +
12589 +s5x532_t s5x532_reg[] = {
12590 +       // page 5
12591 +       {0xec,0x05},
12592 +       {0x08,0x55,0x5},
12593 +       {0x0a,0x75,0x5},
12594 +       {0x0c,0x90,0x5},
12595 +       {0x0e,0x18,0x5},
12596 +       {0x12,0x09,0x5},
12597 +       {0x14,0x9d,0x5},
12598 +       {0x16,0x90,0x5},
12599 +       {0x1a,0x18,0x5},
12600 +       {0x1c,0x0c,0x5},
12601 +       {0x1e,0x09,0x5},
12602 +       {0x20,0x06,0x5},
12603 +       {0x22,0x20,0x5},
12604 +       {0x2a,0x00,0x5},
12605 +       {0x2d,0x04,0x5},
12606 +       {0x12,0x24,0x5},
12607 +       // page 3
12608 +       {0xec,0x03,0x3},
12609 +       {0x0c,0x09,0x3},
12610 +       {0x6c,0x09,0x3},
12611 +       {0x2b,0x10,0x3}, // momo clock inversion
12612 +       // page 2
12613 +       {0xec,0x02,0x2},
12614 +       {0x03,0x09,0x2},
12615 +       {0x05,0x08,0x2},
12616 +       {0x06,0x01,0x2},
12617 +       {0x07,0xf8,0x2},
12618 +       {0x15,0x25,0x2},
12619 +       {0x30,0x29,0x2},
12620 +       {0x36,0x12,0x2},
12621 +       {0x38,0x04,0x2},
12622 +       {0x1b,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
12623 +       {0x1c,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
12624 +       // page 1
12625 +       {0xec,0x01,0x1},
12626 +       {0x00,0x03,0x1}, //
12627 +       {0x0a,0x08,0x1}, // 0x0-QQVGA, 0x06-CIF, 0x02-QCIF, 0x08-VGA, 0x04-QVGA, 0x0a-SXGA
12628 +       {0x0c,0x00,0x1}, // Pattern selectio. 0-CIS, 1-Color bar, 2-Ramp, 3-Blue screen
12629 +       {0x10,0x27,0x1},
12630 +       // 0x21-ITU-R656(CrYCbY), 0x25-ITU-R601(CrYCbY), 0x26-ITU-R601(YCbYCr)
12631 +       {0x50,0x21,0x1},                // Hblank
12632 +       {0x51,0x00,0x1},                // Hblank
12633 +       {0x52,0xA1,0x1},                // Hblank
12634 +       {0x53,0x02,0x1},                // Hblank
12635 +       {0x54,0x01,0x1},                // Vblank
12636 +       {0x55,0x00,0x1},                // Vblank
12637 +       {0x56,0xE1,0x1},                // Vblank
12638 +       {0x57,0x01,0x1},                // Vblank
12639 +       {0x58,0x21,0x1},                // Hsync
12640 +       {0x59,0x00,0x1},                // Hsync
12641 +       {0x5a,0xA1,0x1},                // Hsync
12642 +       {0x5b,0x02,0x1},                // Hsync
12643 +       {0x5c,0x03,0x1},                // Vref
12644 +       {0x5d,0x00,0x1},                // Vref
12645 +       {0x5e,0x05,0x1},                // Vref
12646 +       {0x5f,0x00,0x1},                // Vref
12647 +       {0x70,0x0E,0x1},
12648 +       {0x71,0xD6,0x1},
12649 +       {0x72,0x30,0x1},
12650 +       {0x73,0xDB,0x1},
12651 +       {0x74,0x0E,0x1},
12652 +       {0x75,0xD6,0x1},
12653 +       {0x76,0x18,0x1},
12654 +       {0x77,0xF5,0x1},
12655 +       {0x78,0x0E,0x1},
12656 +       {0x79,0xD6,0x1},
12657 +       {0x7a,0x28,0x1},
12658 +       {0x7b,0xE6,0x1},
12659 +       {0x50,0x00,0x1},
12660 +       {0x5c,0x00,0x1},
12661 +
12662 +       // page 0
12663 +       {0xec,0x00,0x0},
12664 +       {0x79,0x01,0x0},
12665 +       {0x58,0x90,0x0},
12666 +       {0x59,0xA0,0x0},
12667 +       {0x5a,0x50,0x0},
12668 +       {0x5b,0x70,0x0},
12669 +       {0x5c,0xD0,0x0},
12670 +       {0x5d,0xC0,0x0},
12671 +       {0x5e,0x28,0x0},
12672 +       {0x5f,0x08,0x0},
12673 +       {0x50,0x90,0x0},
12674 +       {0x51,0xA0,0x0},
12675 +       {0x52,0x50,0x0},
12676 +       {0x53,0x70,0x0},
12677 +       {0x54,0xD0,0x0},
12678 +       {0x55,0xC0,0x0},
12679 +       {0x56,0x28,0x0},
12680 +       {0x57,0x00,0x0},
12681 +       {0x48,0x90,0x0},
12682 +       {0x49,0xA0,0x0},
12683 +       {0x4a,0x50,0x0},
12684 +       {0x4b,0x70,0x0},
12685 +       {0x4c,0xD0,0x0},
12686 +       {0x4d,0xC0,0x0},
12687 +       {0x4e,0x28,0x0},
12688 +       {0x4f,0x08,0x0},
12689 +       {0x72,0x82,0x0}, // main clock = 24MHz:0xd2, 16M:0x82, 12M:0x54
12690 +       {0x75,0x05,0x0} // absolute vertical mirror.  junon
12691 +
12692 +};
12693 +
12694 +
12695 +#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
12696 +#define S5X532_RISC_REGS 0xEB
12697 +#define S5X532_ISP_REGS 0xFB /* S5C7323X */
12698 +#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
12699 +
12700 +
12701 +#define PAGE_ADDRESS      0xEC
12702 +
12703 +//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
12704 +#define S5X532_REGS (0x1000)
12705 +
12706 +
12707 +
12708 +#endif
12709 +
12710 +
12711 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/s5x532_rev36.h
12712 ===================================================================
12713 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12714 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/s5x532_rev36.h    2009-01-02 00:01:56.000000000 +0100
12715 @@ -0,0 +1,208 @@
12716 +/*
12717 + * 2004 (C) Samsung Electronics
12718 + *  SW.LEE <hitchcar@sec.samsung.com>
12719 + * This file is subject to the terms and conditions of the GNU General Public
12720 + * License 2. See the file COPYING in the main directory of this archive
12721 + * for more details.
12722 + */
12723 +
12724 +
12725 +#ifndef _SMDK2440_S5X532_H_
12726 +#define _SMDK2440_S5X532_H_
12727 +
12728 +
12729 +#define CHIP_DELAY 0xFF
12730 +
12731 +typedef struct samsung_t{
12732 +       unsigned char subaddr;
12733 +       unsigned char value;
12734 +       unsigned char page;
12735 +} s5x532_t;
12736 +
12737 +s5x532_t s5x532_reg[] = {
12738 +
12739 +       //=============== page0 ===============//
12740 +       {0xec,0x00,0x00},
12741 +       {0x02,0x00,0x00},
12742 +       {0x14,0x60,0x00},
12743 +       {0x15,0x60,0x00},
12744 +       {0x16,0x60,0x00},
12745 +       {0x1b,0x20,0x00},
12746 +       {0x1c,0x20,0x00},
12747 +       {0x1d,0x20,0x00},
12748 +       {0x1e,0x20,0x00},
12749 +       {0x72,0xdc,0x00},
12750 +       {0x73,0x11,0x00},
12751 +       {0x76,0x82,0x00},
12752 +       {0x77,0x90,0x00},
12753 +       {0x78,0x6c,0x00},
12754 +       {0x0a,0x02,0x00},
12755 +       {0x34,0x0d,0x00},
12756 +       {0x35,0x0a,0x00},
12757 +       {0x36,0x05,0x00},
12758 +       {0x37,0x05,0x00},
12759 +       {0x38,0x06,0x00},
12760 +       {0x39,0x08,0x00},
12761 +       {0x3A,0x0d,0x00},
12762 +       {0x3B,0x0d,0x00},
12763 +       {0x3C,0x18,0x00},
12764 +       {0x3D,0xE0,0x00},
12765 +       {0x3E,0x20,0x00},
12766 +       {0x66,0x02,0x00},
12767 +       {0x6c,0x40,0x00},
12768 +       {0x7c,0x01,0x00},
12769 +       {0x0D,0x24,0x00},
12770 +       {0x40,0x1B,0x00},
12771 +       {0x41,0x4F,0x00},
12772 +       {0x42,0x24,0x00},
12773 +       {0x43,0x3E,0x00},
12774 +       {0x44,0x32,0x00},
12775 +       {0x45,0x30,0x00},
12776 +       {0x48,0xa0,0x00},
12777 +       {0x49,0xd0,0x00},
12778 +       {0x4A,0x28,0x00},
12779 +       {0x4B,0x7d,0x00},
12780 +       {0x4C,0xd0,0x00},
12781 +       {0x4D,0xe0,0x00},
12782 +       {0x4E,0x1a,0x00},
12783 +       {0x4F,0xa0,0x00},
12784 +       {0x50,0xc0,0x00},
12785 +       {0x51,0xc0,0x00},
12786 +       {0x52,0x42,0x00},
12787 +       {0x53,0x7e,0x00},
12788 +       {0x54,0xc0,0x00},
12789 +       {0x55,0xf0,0x00},
12790 +       {0x56,0x1e,0x00},
12791 +       {0x57,0xe0,0x00},
12792 +       {0x58,0xc0,0x00},
12793 +       {0x59,0xa0,0x00},
12794 +       {0x5A,0x4a,0x00},
12795 +       {0x5B,0x7e,0x00},
12796 +       {0x5C,0xc0,0x00},
12797 +       {0x5D,0xf0,0x00},
12798 +       {0x5E,0x2a,0x00},
12799 +       {0x5F,0x10,0x00},
12800 +       {0x79,0x00,0x00},
12801 +       {0x7a,0x00,0x00},
12802 +       {0xe0,0x0f,0x00},
12803 +       {0xe3,0x14,0x00},
12804 +       {0xe5,0x48,0x00},
12805 +       {0xe7,0x58,0x00},
12806 +
12807 +       //=============== page1 ===============//
12808 +       {0xec,0x01,0x01},
12809 +       {0x10,0x05,0x01},
12810 +       {0x20,0xde,0x01},
12811 +       {0x0b,0x06,0x01},
12812 +       {0x30,0x00,0x01},
12813 +       {0x31,0x00,0x01},
12814 +       {0x32,0x00,0x01},
12815 +       {0x24,0x28,0x01},
12816 +       {0x25,0x3F,0x01},
12817 +       {0x26,0x65,0x01},
12818 +       {0x27,0xA1,0x01},
12819 +       {0x28,0xFF,0x01},
12820 +       {0x29,0x96,0x01},
12821 +       {0x2A,0x85,0x01},
12822 +       {0x2B,0xFF,0x01},
12823 +       {0x2C,0x00,0x01},
12824 +       {0x2D,0x1B,0x01},
12825 +       {0xB0,0x28,0x01},
12826 +       {0xB1,0x3F,0x01},
12827 +       {0xB2,0x65,0x01},
12828 +       {0xB3,0xA1,0x01},
12829 +       {0xB4,0xFF,0x01},
12830 +       {0xB5,0x96,0x01},
12831 +       {0xB6,0x85,0x01},
12832 +       {0xB7,0xFF,0x01},
12833 +       {0xB8,0x00,0x01},
12834 +       {0xB9,0x1B,0x01},
12835 +       {0x15,0x15,0x01},
12836 +       {0x18,0x85,0x01},
12837 +       {0x1f,0x05,0x01},
12838 +       {0x87,0x40,0x01},
12839 +       {0x37,0x60,0x01},
12840 +       {0x38,0xd5,0x01},
12841 +       {0x48,0xa0,0x01},
12842 +       {0x61,0x54,0x01},
12843 +       {0x62,0x54,0x01},
12844 +       {0x63,0x14,0x01},
12845 +       {0x64,0x14,0x01},
12846 +       {0x6d,0x12,0x01},
12847 +       {0x78,0x09,0x01},
12848 +       {0x79,0xD7,0x01},
12849 +       {0x7A,0x14,0x01},
12850 +       {0x7B,0xEE,0x01},
12851 +
12852 +       //=============== page2 ===============//
12853 +       {0xec,0x02,0x02},
12854 +       {0x2c,0x76,0x02},
12855 +       {0x25,0x25,0x02},
12856 +       {0x27,0x27,0x02},
12857 +       {0x30,0x29,0x02},
12858 +       {0x36,0x08,0x02},
12859 +       {0x38,0x04,0x02},
12860 +
12861 +       //=============== page3 ===============//
12862 +       {0xec,0x03,0x03},
12863 +       {0x08,0x00,0x03},
12864 +       {0x09,0x33,0x03},
12865 +
12866 +       //=============== page4 ===============//
12867 +       {0xec,0x04,0x04},
12868 +       {0x00,0x21,0x04},
12869 +       {0x01,0x00,0x04},
12870 +       {0x02,0x9d,0x04},
12871 +       {0x03,0x02,0x04},
12872 +       {0x04,0x04,0x04},
12873 +       {0x05,0x00,0x04},
12874 +       {0x06,0x1f,0x04},
12875 +       {0x07,0x02,0x04},
12876 +       {0x08,0x21,0x04},
12877 +       {0x09,0x00,0x04},
12878 +       {0x0a,0x9d,0x04},
12879 +       {0x0b,0x02,0x04},
12880 +       {0x0c,0x04,0x04},
12881 +       {0x0d,0x00,0x04},
12882 +       {0x0e,0x20,0x04},
12883 +       {0x0f,0x02,0x04},
12884 +       {0x1b,0x3c,0x04},
12885 +       {0x1c,0x3c,0x04},
12886 +
12887 +       //=============== page5 ===============//
12888 +       {0xec,0x05,0x05},
12889 +       {0x1f,0x00,0x05},
12890 +       {0x08,0x59,0x05},
12891 +       {0x0a,0x71,0x05},
12892 +       {0x1e,0x23,0x05},
12893 +       {0x0e,0x3c,0x05},
12894 +
12895 +       //=============== page7 ===============//
12896 +       {0xec,0x07,0x07},
12897 +       {0x11,0xfe,0x07},
12898 +
12899 +       // added by junon
12900 +       {0xec,0x01,0x07},
12901 +       {0x10,0x26,0x07},
12902 +       // 0x21-ITU-R656(CbYCrY), 0x25-ITU-R601(CbYCrY), 0x26-ITU-R601(YCrYCb)
12903 +
12904 +
12905 +};
12906 +
12907 +
12908 +#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
12909 +#define S5X532_RISC_REGS 0xEB
12910 +#define S5X532_ISP_REGS 0xFB /* S5C7323X */
12911 +#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
12912 +
12913 +
12914 +#define PAGE_ADDRESS      0xEC
12915 +
12916 +//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
12917 +#define S5X532_REGS (0x1000)
12918 +
12919 +
12920 +
12921 +#endif
12922 +
12923 +
12924 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/sensor.h
12925 ===================================================================
12926 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12927 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/sensor.h  2009-01-02 00:01:56.000000000 +0100
12928 @@ -0,0 +1,20 @@
12929 +/*
12930 + *
12931 + *  Copyright (C) 2004 Samsung Electronics
12932 + *            SW.LEE <hitchcar@sec.samsung.com>
12933 + *
12934 + * This program is free software; you can redistribute it and/or modify
12935 + * it under the terms of the GNU General Public License version 2 as
12936 + * published by the Free Software Foundation.
12937 + */
12938 +
12939 +#ifndef __SENSOR_CMD_H_
12940 +#define __SENSOR_CMD_H_
12941 +
12942 +#include "bits.h"
12943 +
12944 +#define SENSOR_INIT    BIT0
12945 +#define USER_ADD        BIT1
12946 +#define USER_EXIT       BIT2
12947 +
12948 +#endif
12949 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/sxga.h
12950 ===================================================================
12951 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
12952 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/sxga.h    2009-01-02 00:01:56.000000000 +0100
12953 @@ -0,0 +1,504 @@
12954 +/*
12955 + * 2004 (C) Samsung Electronics
12956 + *  SW.LEE <hitchcar@sec.samsung.com>
12957 + * This file is subject to the terms and conditions of the GNU General Public
12958 + * License 2. See the file COPYING in the main directory of this archive
12959 + * for more details.
12960 + */
12961 +
12962 +
12963 +#ifndef _SAMSUNG_SXGA_H_
12964 +#define _SAMSUNG_SXGA_H_
12965 +
12966 +
12967 +#define CHIP_DELAY 0xFF
12968 +
12969 +typedef struct samsung_t{
12970 +       unsigned char subaddr;
12971 +       unsigned char value;
12972 +       unsigned char page;
12973 +} s5x532_t;
12974 +
12975 +s5x532_t s5x532_reg[] = {
12976 +       // page 0
12977 +       {0xec,0x00,0x0},
12978 +       {0x0c,0x38,0x0},
12979 +       {0x0d,0x24,0x0},
12980 +       {0x13,0x10,0x0},
12981 +       {0x14,0x10,0x0},
12982 +       {0x15,0x10,0x0},
12983 +       {0x16,0x10,0x0},
12984 +       {0x17,0x20,0x0},
12985 +       {0x18,0x30,0x0},
12986 +       {0x19,0x30,0x0},
12987 +       {0x1a,0x10,0x0},
12988 +       {0x1b,0x10,0x0},
12989 +
12990 +       {0x2d,0x40,0x0},
12991 +       {0x3e,0x10,0x0},
12992 +       {0x34,0x0a,0x0},
12993 +       {0x39,0x04,0x0},
12994 +       {0x3a,0x02,0x0},
12995 +       {0x31,0x05,0x0},
12996 +
12997 +       {0x40,0x1d,0x0},
12998 +       {0x41,0x50,0x0},
12999 +       {0x42,0x24,0x0},
13000 +       {0x43,0x3f,0x0},
13001 +       {0x44,0x30,0x0},
13002 +       {0x45,0x31,0x0},
13003 +
13004 +       {0x48,0xa0,0x0},
13005 +       {0x49,0xc0,0x0},
13006 +       {0x4a,0x58,0x0},
13007 +       {0x4b,0x50,0x0},
13008 +       {0x4c,0xb0,0x0},
13009 +       {0x4d,0xc0,0x0},
13010 +       {0x4e,0x30,0x0},
13011 +       {0x4f,0x20,0x0},
13012 +
13013 +       {0x50,0xa0,0x0},
13014 +       {0x51,0xc0,0x0},
13015 +       {0x52,0x50,0x0},
13016 +       {0x53,0x60,0x0},
13017 +       {0x54,0xb0,0x0},
13018 +       {0x55,0xc0,0x0},
13019 +       {0x56,0x20,0x0},
13020 +       {0x57,0x08,0x0},
13021 +//     {0x72,0x50,0x0}, // Clock 16
13022 +       {0x72,0x78,0x0}, // Clock 24Mhz
13023 +//     {0x72,0xf0,0x0}, // Clock 48Mhz
13024 +       // page 1
13025 +       {0xec,0x01,0x1},
13026 +       {0x10,0x17,0x1}, // ITU-R601
13027 +                        /*
13028 +                          [3:2] : out_sel
13029 +                            00 : 656
13030 +                            01 : 601
13031 +                            10 : RGB
13032 +                            11 : CIS
13033 +                          [1] : YC_SEL
13034 +                          [0] : CBCR_SEL
13035 +                        */
13036 +
13037 +       {0x0b,0x06,0x1}, // 6
13038 +       {0x20,0xa8,0x1}, //b0); // Highlight C Supp 040215
13039 +       {0x22,0x26,0x1}, //2f); 040225
13040 +
13041 +       {0x24,0x08,0x1}, //00); //1F); 040226
13042 +       {0x25,0x10,0x1}, //10); //34);
13043 +       {0x26,0x40,0x1}, //56);
13044 +       {0x27,0x80,0x1}, //8D);
13045 +       {0x28,0x2c,0x1}, //E7);
13046 +       {0x29,0xd6,0x1}, //7C);
13047 +       {0x2A,0x0c,0x1}, //70);
13048 +       {0x2B,0xFF,0x1}, //FF);
13049 +       {0x2C,0x00,0x1}, //00);
13050 +       {0x2D,0x5f,0x1}, //1B);
13051 +       //
13052 +       {0xB0,0x08,0x1}, //00); //1F); 040226
13053 +       {0xB1,0x10,0x1}, //10); //34);50
13054 +       {0xB2,0x40,0x1}, //36);
13055 +       {0xB3,0x80,0x1}, //6D);
13056 +       {0xB4,0x2c,0x1}, //b7);
13057 +       {0xB5,0xd6,0x1}, //7C);
13058 +       {0xB6,0x0c,0x1}, //70);
13059 +       {0xB7,0xFF,0x1}, //FF);
13060 +       {0xB8,0x00,0x1}, //00);
13061 +       {0xB9,0x5f,0x1}, //1B);
13062 +
13063 +
13064 +       {0xc2,0x01,0x1}, // shading On
13065 +       {0xc3,0x80,0x1},
13066 +       {0xc4,0x02,0x1},
13067 +       {0xc5,0x00,0x1},
13068 +       {0xc6,0x01,0x1},
13069 +       {0xc7,0x00,0x1},
13070 +       {0xc8,0x05,0x1},
13071 +       {0xc9,0x00,0x1},
13072 +       {0xca,0x04,0x1},
13073 +
13074 +       // shading 5
13075 +       {0xd0,0xb5,0x1},
13076 +       {0xd1,0x9c,0x1},
13077 +       {0xd2,0x8d,0x1},
13078 +       {0xd3,0x84,0x1},
13079 +       {0xd4,0x84,0x1},
13080 +       {0xd5,0x91,0x1},
13081 +       {0xd6,0xa0,0x1},
13082 +       {0xd7,0xb5,0x1},
13083 +
13084 +       {0xd8,0xc0,0x1},
13085 +       {0xd9,0xa6,0x1},
13086 +       {0xda,0x93,0x1},
13087 +       {0xdb,0x85,0x1},
13088 +       {0xdc,0x85,0x1},
13089 +       {0xdd,0x90,0x1},
13090 +       {0xde,0xa0,0x1},
13091 +       {0xdf,0xb8,0x1},
13092 +
13093 +       // Page 2
13094 +       {0xec,0x02,0x02},
13095 +
13096 +       {0x2d,0x02,0x02},
13097 +       {0x20,0x13,0x02},
13098 +       {0x21,0x13,0x2},
13099 +       {0x22,0x13,0x2},
13100 +       {0x23,0x13,0x2},
13101 +       {0x2e,0x85,0x2},
13102 +       {0x2f,0x34,0x2},
13103 +       {0x30,0x00,0x2},
13104 +       {0x28,0x94,0x2},
13105 +
13106 +
13107 +       // page 3
13108 +       {0xec,0x03,0x03},
13109 +       {0x10,0x00,0x3},
13110 +       {0x20,0x00,0x3},
13111 +       {0x21,0x20,0x3},
13112 +       {0x22,0x00,0x3},
13113 +       {0x23,0x00,0x3},
13114 +       {0x40,0x20,0x3},
13115 +       {0x41,0x20,0x3},
13116 +       {0x42,0x20,0x3},
13117 +       {0x43,0x20,0x3},
13118 +       {0x60,0x00,0x3},
13119 +       {0x61,0x00,0x3},
13120 +       {0x62,0x00,0x3},
13121 +       {0x63,0x00,0x3},
13122 +       {0x64,0x04,0x3},
13123 +       {0x65,0x1C,0x3},
13124 +       {0x66,0x05,0x3},
13125 +       {0x67,0x1C,0x3},
13126 +       {0x68,0x00,0x3},
13127 +       {0x69,0x2D,0x3},
13128 +       {0x6a,0x00,0x3},
13129 +       {0x6b,0x72,0x3},
13130 +       {0x6c,0x00,0x3},
13131 +       {0x6d,0x00,0x3},
13132 +       {0x6e,0x16,0x3}, // 2.38
13133 +       {0x6f,0x16,0x3}, // 2.38
13134 +       {0x70,0x00,0x3},
13135 +       {0x71,0x00,0x3},
13136 +       {0x72,0x45,0x3},
13137 +       {0x73,0x00,0x3},
13138 +       {0x74,0x1C,0x3},
13139 +       {0x75,0x05,0x3},
13140 +
13141 +       {0x80,0x00,0x3},  //for 0.02 _ 44
13142 +       {0x81,0x00,0x3},
13143 +       {0x82,0x00,0x3},
13144 +       {0x83,0x00,0x3},
13145 +       {0x84,0x04,0x3},
13146 +       {0x85,0x1c,0x3},
13147 +       {0x86,0x05,0x3},
13148 +       {0x87,0x1c,0x3},
13149 +       {0x88,0x00,0x3},
13150 +       {0x89,0x2d,0x3},
13151 +       {0x8a,0x00,0x3},
13152 +       {0x8b,0xcc,0x3},
13153 +       {0x8c,0x00,0x3},
13154 +       {0x8d,0x00,0x3},
13155 +       {0x8e,0x08,0x3},
13156 +       {0x8f,0x08,0x3},
13157 +       {0x90,0x01,0x3},
13158 +       {0x91,0x00,0x3},
13159 +       {0x92,0x91,0x3},
13160 +       {0x93,0x00,0x3},
13161 +       {0x94,0x88,0x3},
13162 +       {0x95,0x02,0x3},
13163 +
13164 +
13165 +
13166 +       // page 4
13167 +       {0xec,0x04,0x04},
13168 +       {0x3f,0x09,0x04}, // VGA : old board :0x08 , new board ; 0X09
13169 +       {0x18,0x00,0x04},  // sxga
13170 +       {0x1c,0x41,0x04},
13171 +       {0x20,0x41,0x04}, // vga center 040215
13172 +       {0x22,0xc1,0x04},// a1);
13173 +       {0x23,0x02,0x04},
13174 +       {0x28,0x41,0x04},
13175 +       {0x2a,0xc1,0x04},// a1);
13176 +       {0x2b,0x02,0x04},
13177 +
13178 +       {0x3c,0x0b,0x04}, //f);  // vga
13179 +       {0x58,0x11,0x04},
13180 +       {0x5c,0x14,0x04},
13181 +       {0x60,0x21,0x04},
13182 +       {0x61,0x00,0x04},
13183 +       {0x62,0xB1,0x04},
13184 +       {0x63,0x02,0x04},
13185 +       {0x64,0x01,0x04},
13186 +       {0x65,0x00,0x04},
13187 +       {0x66,0x01,0x04},
13188 +       {0x67,0x02,0x04},
13189 +       {0x68,0x21,0x04},
13190 +       {0x69,0x00,0x04},
13191 +       {0x6a,0xB1,0x04},
13192 +       {0x6b,0x02,0x04},
13193 +       {0x6c,0x01,0x04},
13194 +       {0x6d,0x00,0x04},
13195 +       {0x6e,0x01,0x04},
13196 +       {0x6f,0x02,0x04},
13197 +       {0x70,0x2D,0x04},
13198 +       {0x71,0x00,0x04},
13199 +       {0x72,0xd3,0x04}, // 14
13200 +       {0x73,0x05,0x04}, // 15
13201 +       {0x74,0x1C,0x04},
13202 +       {0x75,0x05,0x04},
13203 +       {0x76,0x1b,0x04}, // HendL
13204 +       {0x77,0x0b,0x04}, // HendH
13205 +       {0x78,0x01,0x04}, // 5.00
13206 +       {0x79,0x80,0x04}, // 5.2a
13207 +       {0x7a,0x33,0x04},
13208 +       {0x7b,0x00,0x04},
13209 +       {0x7c,0x38,0x04}, // 5.0e
13210 +       {0x7d,0x03,0x04},
13211 +       {0x7e,0x00,0x04},
13212 +       {0x7f,0x0A,0x04},
13213 +
13214 +       {0x80,0x2e,0x04},
13215 +       {0x81,0x00,0x04},
13216 +       {0x82,0xae,0x04},
13217 +       {0x83,0x02,0x04},
13218 +       {0x84,0x00,0x04},
13219 +       {0x85,0x00,0x04},
13220 +       {0x86,0x01,0x04},
13221 +       {0x87,0x02,0x04},
13222 +       {0x88,0x2e,0x04},
13223 +       {0x89,0x00,0x04},
13224 +       {0x8a,0xae,0x04},
13225 +       {0x8b,0x02,0x04},
13226 +       {0x8c,0x1c,0x04},
13227 +       {0x8d,0x00,0x04},
13228 +       {0x8e,0x04,0x04},
13229 +       {0x8f,0x02,0x04},
13230 +       {0x90,0x2d,0x04},
13231 +       {0x91,0x00,0x04},
13232 +       {0x92,0xa5,0x04},
13233 +       {0x93,0x00,0x04},
13234 +       {0x94,0x88,0x04},
13235 +       {0x95,0x02,0x04},
13236 +       {0x96,0xb3,0x04},
13237 +       {0x97,0x06,0x04},
13238 +       {0x98,0x01,0x04},
13239 +       {0x99,0x00,0x04},
13240 +       {0x9a,0x33,0x04},
13241 +       {0x9b,0x30,0x04},
13242 +       {0x9c,0x50,0x04},
13243 +       {0x9d,0x30,0x04},
13244 +       {0x9e,0x01,0x04},
13245 +       {0x9f,0x08,0x04},
13246 +
13247 +       // page 5
13248 +       {0xec,0x05,0x05},
13249 +       {0x5a,0x22,0x05},
13250 +
13251 +       // page 6
13252 +       {0xec,0x06,0x06},
13253 +       {0x14,0x1e,0x06},
13254 +       {0x15,0xb4,0x04},
13255 +       {0x16,0x25,0x04},
13256 +       {0x17,0x74,0x04},
13257 +
13258 +       {0x10,0x48,0x04},
13259 +       {0x11,0xa0,0x04},
13260 +       {0x12,0x40,0x04},  // 040216  AE1 window ÁÙÀÓ
13261 +       {0x13,0x70,0x04},
13262 +
13263 +       {0x1a,0x29,0x04},  // 040217  AWB window ÁÙÀÓ
13264 +       {0x30,0x40,0x04},
13265 +       {0x31,0xa2,0x04},
13266 +       {0x32,0x50,0x04},
13267 +       {0x33,0xbc,0x04},
13268 +       {0x34,0x10,0x04},
13269 +       {0x35,0xd2,0x04},
13270 +       {0x36,0x18,0x04},
13271 +       {0x37,0xf5,0x04},
13272 +       {0x38,0x10,0x04},
13273 +       {0x39,0xd3,0x04},
13274 +       {0x3a,0x1a,0x04},
13275 +       {0x3b,0xf0,0x04},
13276 +
13277 +       // page 7
13278 +       {0xec,0x07,0x07},
13279 +       {0x08,0xff,0x7},
13280 +       {0x38,0x01,0x7}, //07); 040315
13281 +       {0x39,0x01,0x7}, //02); //4);  040223   040315
13282 +       {0x11,0xfe,0x7},  //fe);   // green -2  040303
13283 +       {0x2a,0x20,0x7},
13284 +       {0x2b,0x20,0x7},
13285 +       {0x2c,0x10,0x7},
13286 +       {0x2d,0x00,0x7},
13287 +       {0x2e,0xf0,0x7},
13288 +       {0x2f,0xd0,0x7},
13289 +       {0x3a,0xf0,0x7},
13290 +       {0x23,0x07,0x7},  //  for ESD
13291 +
13292 +       // page 0
13293 +       {0xec,0x00,0x00},
13294 +       {0x8a,0x04,0x00},
13295 +
13296 +       // page 1
13297 +       {0xec,0x01,0x01},
13298 +       {0xe5,0xb0,0x01},
13299 +       {0xe5,0xb0,0x01},
13300 +       {0xc2,0x01,0x01},
13301 +
13302 +       {0x61,0x7b,0x01},
13303 +       {0x62,0x7b,0x01},
13304 +       {0x63,0x1b,0x01},
13305 +       {0x64,0x1b,0x01},
13306 +
13307 +       // page 0
13308 +       {0xec,0x00,0x00},
13309 +       {0x7e,0x04,0x00},
13310 +
13311 +       // page 4
13312 +       {0xec,0x04,0x04},
13313 +       {0x04,0x02,0x04},
13314 +       {0x06,0x02,0x04},
13315 +
13316 +       // page 1
13317 +       {0xec,0x01,0x01},
13318 +       {0x10,0x05,0x01},
13319 +       {0x54,0x02,0x01},
13320 +       {0x56,0x02,0x01},
13321 +
13322 +       // page 3
13323 +       {0xec,0x03,0x03},
13324 +       {0x0e,0x08,0x03},
13325 +       {0x0f,0x08,0x03},
13326 +
13327 +       // page 4
13328 +       {0xec,0x04,0x04},
13329 +       {0x00,0x30,0x04},
13330 +       {0x0a,0x30,0x04},
13331 +
13332 +       // page 5
13333 +       {0xec,0x05,0x05},
13334 +       {0x08,0x33,0x05},
13335 +
13336 +       // page 0
13337 +       {0xec,0x00,0x00},
13338 +       {0x02,0x00,0x00},
13339 +
13340 +       // page 4
13341 +//scale out
13342 +       {0xec,0x04,0x04},
13343 +       {0x02,0x20,0x04},
13344 +       {0x1c,0x4f,0x04},
13345 +
13346 +       // page 1
13347 +       {0xec,0x01,0x01},
13348 +       {0x52,0x20,0x01},
13349 +
13350 +       // page 5
13351 +       {0xec,0x05,0x05},
13352 +       {0x0e,0x4f,0x05},
13353 +
13354 +//ae speed
13355 +       // page 0
13356 +       {0xec,0x00,0x00},
13357 +       {0x92,0x80,0x00},
13358 +       {0x93,0x02,0x00},
13359 +       {0x94,0x04,0x00},
13360 +       {0x95,0x04,0x00},
13361 +       {0x96,0x04,0x00},
13362 +       {0x97,0x04,0x00},
13363 +       {0x9b,0x47,0x00},
13364 +
13365 +       {0xec,0x00,0x00},
13366 +       {0x40,0x17,0x00},
13367 +       {0x41,0x4c,0x00},
13368 +       {0x42,0x1d,0x00},
13369 +       {0x43,0x3e,0x00},
13370 +       {0x44,0x2a,0x00},
13371 +       {0x45,0x2d,0x00},
13372 +
13373 +       {0xec,0x01,0x01},
13374 +       {0x20,0xd0,0x01},   //high light color reference
13375 +
13376 +       {0xec,0x00,0x00},
13377 +       {0x7e,0x00,0x00},
13378 +       {0x73,0x11,0x00}, // 41
13379 +       {0x78,0x78,0x00},
13380 +
13381 +       {0xec,0x07,0x07},
13382 +       {0x1b,0x3e,0x07},
13383 +
13384 +       {0xec,0x00,0x00},
13385 +       {0x48,0xA0,0x00}, //s48C0
13386 +       {0x49,0xB0,0x00}, //s49B0
13387 +       {0x4a,0x30,0x00}, //s4a20
13388 +       {0x4b,0x70,0x00}, //s4b70
13389 +       {0x4c,0xD0,0x00}, //s4cA0
13390 +       {0x4d,0xB0,0x00}, //s4dB0
13391 +       {0x4e,0x30,0x00}, //s4e30
13392 +       {0x4f,0xF0,0x00}, //s4fF0
13393 +       {0x50,0xA0,0x00}, //s50D0
13394 +       {0x51,0xB0,0x00}, //s51B0
13395 +       {0x52,0x25,0x00}, //s5210
13396 +       {0x53,0x70,0x00}, //s5370
13397 +       {0x54,0xD0,0x00}, //s5490
13398 +       {0x55,0xD0,0x00}, //s55B0
13399 +       {0x56,0x3A,0x00}, //s5640
13400 +       {0x57,0xD0,0x00}, //s57D0
13401 +       {0x58,0xA0,0x00}, //s58D0
13402 +       {0x59,0xA0,0x00}, //s59B0
13403 +       {0x5a,0x32,0x00}, //s5a0A
13404 +       {0x5b,0x7A,0x00}, //s5b7A
13405 +       {0x5c,0xB0,0x00}, //s5c90
13406 +       {0x5d,0xC0,0x00}, //s5dC0
13407 +       {0x5e,0x3E,0x00}, //s5e4A
13408 +       {0x5f,0xfa,0x00}, //s5fD0
13409 +
13410 +       // gamma
13411 +       {0xec,0x01,0x01},
13412 +       {0x24,0x31,0x01},
13413 +       {0x25,0x4C,0x01},
13414 +       {0x26,0x75,0x01},
13415 +       {0x27,0xB5,0x01},
13416 +       {0x28,0x17,0x01},
13417 +       {0x29,0xAE,0x01},
13418 +       {0x2A,0x97,0x01},
13419 +       {0x2B,0xFF,0x01},
13420 +       {0x2C,0x00,0x01},
13421 +       {0x2D,0x5B,0x01},
13422 +
13423 +       {0xB0,0x31,0x01},
13424 +       {0xB1,0x4C,0x01},
13425 +       {0xB2,0x75,0x01},
13426 +       {0xB3,0xB5,0x01},
13427 +       {0xB4,0x17,0x01},
13428 +       {0xB5,0xAE,0x01},
13429 +       {0xB6,0x97,0x01},
13430 +       {0xB7,0xFF,0x01},
13431 +       {0xB8,0x00,0x01},
13432 +       {0xB9,0x5B,0x01},
13433 +
13434 +       {0xec,0x00,0x00},
13435 +       {0x77,0xb0,0x00},
13436 +       {0x39,0x06,0x00},
13437 +       {0x3a,0x08,0x00},
13438 +
13439 +};
13440 +
13441 +
13442 +#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
13443 +#define S5X532_RISC_REGS 0xEB
13444 +#define S5X532_ISP_REGS 0xFB /* S5C7323X */
13445 +#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
13446 +
13447 +
13448 +#define PAGE_ADDRESS      0xEC
13449 +
13450 +//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
13451 +#define S5X532_REGS (0x1000)
13452 +
13453 +
13454 +
13455 +#endif
13456 +
13457 +
13458 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/userapp.h
13459 ===================================================================
13460 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
13461 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/userapp.h 2009-01-02 00:01:56.000000000 +0100
13462 @@ -0,0 +1,44 @@
13463 +/*
13464 +    Character Driver API Interface
13465 +
13466 +    Copyright (C) 2003 Samsung Electronics (SW.LEE: hitchcar@samsung.com)
13467 +
13468 +    This program is free software; you can redistribute it and/or modify
13469 +    it under the terms of the GNU General Public License as published by
13470 +    the Free Software Foundation; either version 2 of the License, or
13471 +    (at your option) any later version.
13472 +
13473 +*/
13474 +
13475 +#ifndef __FIMC20_CAMIF_USR_APP_H_
13476 +#define __FIMC20_CAMIF_USR_APP_H_
13477 +
13478 +
13479 +/*
13480 + * IOCTL Command for Character Driver
13481 + */
13482 +
13483 +#define CMD_CAMERA_INIT   0x23
13484 +/*  Test Application Usage */
13485 +typedef struct {
13486 +        int src_x;
13487 +        int src_y;
13488 +        int dst_x;
13489 +        int dst_y;
13490 +        int bpp;
13491 +        int flip;
13492 +} camif_param_t;
13493 +
13494 +
13495 +
13496 +#endif
13497 +
13498 +
13499 +/*
13500 + * Local variables:
13501 + * tab-width: 8
13502 + *  c-indent-level: 8
13503 + *  c-basic-offset: 8
13504 + *  c-set-style: "K&R"
13505 + * End:
13506 + */
13507 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/v4l2_api.c
13508 ===================================================================
13509 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
13510 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/v4l2_api.c        2009-01-02 00:01:56.000000000 +0100
13511 @@ -0,0 +1,311 @@
13512 +/*
13513 + * . 2004-01-03: SW.LEE <hitchcar@sec.samsung.com>
13514 + *
13515 + * This file is subject to the terms and conditions of the GNU General Public
13516 + * License 2. See the file COPYING in the main directory of this archive
13517 + * for more details.
13518 + */
13519 +
13520 +#include <linux/config.h>
13521 +#include <linux/module.h>
13522 +#include <linux/kernel.h>
13523 +#include <linux/init.h>
13524 +#include <linux/sched.h>
13525 +#include <linux/irq.h>
13526 +#include <linux/tqueue.h>
13527 +#include <linux/locks.h>
13528 +#include <linux/completion.h>
13529 +#include <linux/delay.h>
13530 +#include <linux/slab.h>
13531 +#include <linux/vmalloc.h>
13532 +#include <linux/miscdevice.h>
13533 +#include <linux/wait.h>
13534 +
13535 +#include <asm/io.h>
13536 +#include <asm/semaphore.h>
13537 +#include <asm/hardware.h>
13538 +#include <asm/uaccess.h>
13539 +
13540 +#include <asm/arch/cpu_s3c2440.h>
13541 +#include <asm/arch/S3C2440.h>
13542 +
13543 +#include "camif.h"
13544 +#include "videodev.h"
13545 +
13546 +/*
13547 +  Codec_formats/Preview_format[0] must be same to initial value of
13548 +  preview_init_param/codec_init_param
13549 +*/
13550 +
13551 +const struct v4l2_fmtdesc codec_formats[] = {
13552 +       {
13553 +               .index     = 0,
13554 +               .type      = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13555 +//             .flags     = FORMAT_FLAGS_PLANAR,
13556 +               .description = "4:2:2, planar, Y-Cb-Cr",
13557 +               .pixelformat = V4L2_PIX_FMT_YUV422P,
13558 +
13559 +       },{
13560 +               .index    = 1,
13561 +               .type     = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13562 +//             .flags    = FORMAT_FLAGS_PLANAR,
13563 +               .name     = "4:2:0, planar, Y-Cb-Cr",
13564 +               .fourcc   = V4L2_PIX_FMT_YUV420,
13565 +       }
13566 +};
13567 +
13568 +
13569 +/* Todo
13570 +   FIMC V4L2_PIX_FMT_RGB565 is not same to that of V4L2spec
13571 +   and so we need image convert to FIMC V4l2_PIX_FMT_RGB565.
13572 +*/
13573 +const struct v4l2_fmtdesc preview_formats[] = {
13574 +       {
13575 +               .index    = 1,
13576 +               .type     = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13577 +               .description = "16 bpp RGB, le",
13578 +               .fourcc   = V4L2_PIX_FMT_RGB565,
13579 +//             .flags    = FORMAT_FLAGS_PACKED,
13580 +       },
13581 +       {
13582 +               .index    = 0,
13583 +               .type     = V4L2_BUF_TYPE_VIDEO_CAPTURE,
13584 +//             .flags    = FORMAT_FLAGS_PACKED,
13585 +               .description = "32 bpp RGB, le",
13586 +               .fourcc   = V4L2_PIX_FMT_BGR32,
13587 +       }
13588 +}
13589 +
13590 +#define NUM_F       ARRARY_SIZE(preview_formats)
13591 +
13592 +
13593 +/*
13594 + * This function and v4l2 structure made for V4L2 API functions
13595 + *     App <--> v4l2 <--> logical param <--> hardware
13596 + */
13597 +static int camif_get_v4l2(camif_cfg_t *cfg)
13598 +{
13599 +       return 0;
13600 +}
13601 +
13602 +
13603 +/*
13604 +** Gives the depth of a video4linux2 fourcc aka pixel format in bits.
13605 +*/
13606 +static int pixfmt2depth(int pixfmt,int *fmtptr)
13607 +{
13608 +       int fmt, depth;
13609 +
13610 +       switch (pixfmt) {
13611 +       case V4L2_PIX_FMT_RGB565:
13612 +       case V4L2_PIX_FMT_RGB565X:
13613 +               fmt = CAMIF_RGB_16;
13614 +               depth = 16;
13615 +               break;
13616 +       case V4L2_PIX_FMT_BGR24: /* Not tested */
13617 +       case V4L2_PIX_FMT_RGB24:
13618 +               fmt = CAMIF_RGB_24;
13619 +               depth = 24;
13620 +               break;
13621 +       case V4L2_PIX_FMT_BGR32:
13622 +       case V4L2_PIX_FMT_RGB32:
13623 +               fmt = CAMIF_RGB_24;
13624 +               depth 32;
13625 +               break;
13626 +       case V4L2_PIX_FMT_GREY: /* Not tested  */
13627 +               fmt = CAMIF_OUT_YCBCR420;
13628 +               depth = 8;
13629 +               break;
13630 +       case V4L2_PIX_FMT_YUYV:
13631 +       case V4L2_PIX_FMT_UYVY:
13632 +       case V4L2_PIX_FMT_YUV422P:
13633 +               fmt = CAMIF_OUT_YCBCR422;
13634 +               depth = 16;
13635 +               break;
13636 +       case V4L2_PIX_FMT_YUV420:
13637 +               fmt = CAMIF_OUT_YCBCR420;
13638 +               depth = 12;
13639 +               break;
13640 +       }
13641 +       if (fmtptr) *fmtptr = fmt;
13642 +       return depth;
13643 +}
13644 +
13645 +
13646 +
13647 +static int camif_s_v4l2(camif_cfg_t *cfg)
13648 +{
13649 +       int num = cfg->v2.used_fmt;
13650 +
13651 +       if ( !(cfg->v2.status&CAMIF_V4L2_INIT)) {
13652 +               int depth;
13653 +               int fourcc = v2.fmtdesc[num].pixelformat;
13654 +
13655 +               /* To define v4l2_fmtsdesc */
13656 +               if (cfg->dma_type == CAMIF_CODEC)
13657 +                       cfg->v2->fmtdesc = codec_formats;
13658 +               else
13659 +                       cfg->v2->fmtdesc = preview_formats;
13660 +
13661 +               /* To define v4l2_format used currently */
13662 +               cfg->v2.fmt.width    = cfg->target_x;
13663 +               cfg->v2.fmt.height   = cfg->target_y;
13664 +               cfg->v2.fmt.field    = V4L2_FIELD_NONE;
13665 +               cfg->v2.fmt.pixelformat = fourcc;
13666 +               depth       = pixfmt2depth(fourcc,NULL);
13667 +               cfg->v2.fmt.bytesperline= cfg->v2.fmt.width*depth >> 3;
13668 +               cfg->v2.fmt.sizeimage =
13669 +                       cfg->v2.fmt.height * cfg->v2.fmt.bytesperline;
13670 +
13671 +               /* To define v4l2_input */
13672 +               cfg->v2.input.index  = 0;
13673 +               if (cfg->dma_type == CAMIF_CODEC)
13674 +                       snprintf(cfg->v2.input.name, 31, "CAMIF CODEC");
13675 +               else
13676 +                       snprintf(cfg->v2.input.name, 31, "CAMIF PREVIEW");
13677 +               cfg->v2.input.type = V4L2_INPUT_TYPE_CAMERA;
13678 +
13679 +               /* Write the Status of v4l2 machine */
13680 +               cfg->v2.status |= CAMIF_V4L2_INIT;
13681 +        }
13682 +       return 0;
13683 +}
13684 +
13685 +
13686 +static int camif_g_fmt(camif_cfg_t *cfg, struct v4l2_format *f)
13687 +{
13688 +       int size = sizeof(struct v4l2_pix_format);
13689 +
13690 +       switch (f->type) {
13691 +       case V4L2_BUF_TYPE_VIDEO_CAPTURE:
13692 +               memset(&f->fmt.pix,0,size);
13693 +               memcpy(&f->fmt.pix,&cfg->v2.fmt,size);
13694 +               return 0;
13695 +       default:
13696 +               return -EINVAL;
13697 +       }
13698 +}
13699 +
13700 +
13701 +/* Copy v4l2 parameter into other element of camif_cfg_t */
13702 +static int camif_s_try(camif_cfg_t *cfg, int f)
13703 +{
13704 +       int fmt;
13705 +       cfg->target_x = cfg->v2.fmt.width;
13706 +       cfg->target_y = cfg->v2.fmt.height;
13707 +       pixfmt2depth(cfg->v2.fmt.pixelformat,&fmt);
13708 +       cfg->fmt = fmt;
13709 +       camif_dynamic_conf(cfg);
13710 +}
13711 +
13712 +
13713 +static int camif_s_fmt(camif_cfg_t *cfg, struct v4l2_format *f)
13714 +{
13715 +       int retval;
13716 +
13717 +       switch (f->type) {
13718 +       case V4L2_BUF_TYPE_VIDEO_CAPTURE:
13719 +       {
13720 +               /* update our state informations */
13721 +//             down(&fh->cap.lock);
13722 +               cfg->v2.fmt          = f->pix;
13723 +               cfg->v2.status       |= CAMIF_v4L2_DIRTY;
13724 +               camif_dynamic_conf(cfg);
13725 +               cfg->v2.status      &= ~CAMIF_v4L2_DIRTY; /* dummy ? */
13726 +//             up(&fh->cap.lock);
13727 +
13728 +               return 0;
13729 +       }
13730 +       default:
13731 +               return -EINVAL;
13732 +       }
13733 +
13734 +}
13735 +
13736 +/* Refer ioctl of  videodeX.c  and bttv-driver.c */
13737 +int camif_do_ioctl
13738 +(struct inode *inode, struct file *file,unsigned int cmd, void * arg)
13739 +{
13740 +       camif_cfg_t *cfg = file->private_data;
13741 +       int ret = 0;
13742 +
13743 +       switch (cmd) {
13744 +        case VIDIOC_QUERYCAP:
13745 +               {
13746 +                       struct v4l2_capability *cap = arg;
13747 +
13748 +                       strcpy(cap->driver,"Fimc Camera");
13749 +                       strlcpy(cap->card,cfg->v->name,sizeof(cap->card));
13750 +                       sprintf(cap->bus_info,"FIMC 2.0 AHB Bus");
13751 +                       cap->version = 0;
13752 +                       cap->capabilities =
13753 +                               V4L2_CAP_VIDEO_CAPTURE |V4L2_CAP_READWRITE;
13754 +                       return 0;
13755 +               }
13756 +       case VIDIOC_G_FMT:
13757 +               {
13758 +                       struct v4l2_format *f = arg;
13759 +                       return camif_g_fmt(cfg,f);
13760 +               }
13761 +       case VIDIOC_S_FMT:
13762 +               {
13763 +                       struct v4l2_format *f = arg;
13764 +                       return camif_s_fmt(cfg,f);
13765 +               }
13766 +
13767 +       case VIDIOC_ENUM_FMT:
13768 +               {
13769 +                       struct v4l2_fmtdesc *f = arg;
13770 +                       enum v4l2_buf_type type = f->type;
13771 +                       int index = f->index;
13772 +
13773 +                       if (index >= NUM_F)
13774 +                               return -EINVAL;
13775 +                       switch (f->type) {
13776 +                       case V4L2_BUF_TYPE_VIDEO_CAPTURE:
13777 +                               break;
13778 +                       case V4L2_BUF_TYPE_VIDEO_OVERLAY:
13779 +                       case V4L2_BUF_TYPE_VBI_CAPTURE:
13780 +                                       default:
13781 +                       return -EINVAL;
13782 +                       }
13783 +                       memset(f,0,sizeof(*f));
13784 +                       memcpy(f,cfg->v2.fmtdesc+index,sizeof(*f));
13785 +                       return 0;
13786 +               }
13787 +       case VIDIOC_G_INPUT:
13788 +               {
13789 +                       u32 *i = arg;
13790 +                       *i = cfg->v2.input;
13791 +                       return 0;
13792 +               }
13793 +       case VIDIOC_S_INPUT:
13794 +               {
13795 +                       int index = *((int *)arg);
13796 +                       if (index != 0)
13797 +                               return -EINVAL;
13798 +                       cfg->v2.input.index = index;
13799 +                       return 0;
13800 +               }
13801 +
13802 +       default:
13803 +               return -ENOIOCTLCMD; /* errno.h */
13804 +       } /* End of Switch  */
13805 +
13806 +
13807 +}
13808 +
13809 +
13810 +
13811 +
13812 +
13813 +
13814 +
13815 +/*
13816 + * Local variables:
13817 + * tab-width: 8
13818 + *  c-indent-level: 8
13819 + *  c-basic-offset: 8
13820 + *  c-set-style: "K&R"
13821 + * End:
13822 + */
13823 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/videodev2.h
13824 ===================================================================
13825 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
13826 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/videodev2.h       2009-01-02 00:01:56.000000000 +0100
13827 @@ -0,0 +1,938 @@
13828 +#ifndef __LINUX_VIDEODEV2_H
13829 +#define __LINUX_VIDEODEV2_H
13830 +/*
13831 + *     Video for Linux Two
13832 + *
13833 + *     Header file for v4l or V4L2 drivers and applications, for
13834 + *     Linux kernels 2.2.x or 2.4.x.
13835 + *
13836 + *     See http://bytesex.org/v4l/ for API specs and other
13837 + *     v4l2 documentation.
13838 + *
13839 + *     Author: Bill Dirks <bdirks@pacbell.net>
13840 + *             Justin Schoeman
13841 + *             et al.
13842 + */
13843 +#ifdef __KERNEL__
13844 +#include <linux/time.h> /* need struct timeval */
13845 +#endif
13846 +
13847 +/*
13848 + *     M I S C E L L A N E O U S
13849 + */
13850 +
13851 +/*  Four-character-code (FOURCC) */
13852 +#define v4l2_fourcc(a,b,c,d)\
13853 +        (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
13854 +
13855 +/*
13856 + *     E N U M S
13857 + */
13858 +enum v4l2_field {
13859 +       V4L2_FIELD_ANY        = 0, /* driver can choose from none,
13860 +                                     top, bottom, interlaced
13861 +                                     depending on whatever it thinks
13862 +                                     is approximate ... */
13863 +       V4L2_FIELD_NONE       = 1, /* this device has no fields ... */
13864 +       V4L2_FIELD_TOP        = 2, /* top field only */
13865 +       V4L2_FIELD_BOTTOM     = 3, /* bottom field only */
13866 +       V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */
13867 +       V4L2_FIELD_SEQ_TB     = 5, /* both fields sequential into one
13868 +                                     buffer, top-bottom order */
13869 +       V4L2_FIELD_SEQ_BT     = 6, /* same as above + bottom-top order */
13870 +       V4L2_FIELD_ALTERNATE  = 7, /* both fields alternating into
13871 +                                     separate buffers */
13872 +};
13873 +#define V4L2_FIELD_HAS_TOP(field)      \
13874 +       ((field) == V4L2_FIELD_TOP      ||\
13875 +        (field) == V4L2_FIELD_INTERLACED ||\
13876 +        (field) == V4L2_FIELD_SEQ_TB   ||\
13877 +        (field) == V4L2_FIELD_SEQ_BT)
13878 +#define V4L2_FIELD_HAS_BOTTOM(field)   \
13879 +       ((field) == V4L2_FIELD_BOTTOM   ||\
13880 +        (field) == V4L2_FIELD_INTERLACED ||\
13881 +        (field) == V4L2_FIELD_SEQ_TB   ||\
13882 +        (field) == V4L2_FIELD_SEQ_BT)
13883 +#define V4L2_FIELD_HAS_BOTH(field)     \
13884 +       ((field) == V4L2_FIELD_INTERLACED ||\
13885 +        (field) == V4L2_FIELD_SEQ_TB   ||\
13886 +        (field) == V4L2_FIELD_SEQ_BT)
13887 +
13888 +enum v4l2_buf_type {
13889 +       V4L2_BUF_TYPE_VIDEO_CAPTURE  = 1,
13890 +       V4L2_BUF_TYPE_VIDEO_OUTPUT   = 2,
13891 +       V4L2_BUF_TYPE_VIDEO_OVERLAY  = 3,
13892 +       V4L2_BUF_TYPE_VBI_CAPTURE    = 4,
13893 +       V4L2_BUF_TYPE_VBI_OUTPUT     = 5,
13894 +       V4L2_BUF_TYPE_PRIVATE        = 0x80,
13895 +};
13896 +
13897 +enum v4l2_ctrl_type {
13898 +       V4L2_CTRL_TYPE_INTEGER       = 1,
13899 +       V4L2_CTRL_TYPE_BOOLEAN       = 2,
13900 +       V4L2_CTRL_TYPE_MENU          = 3,
13901 +       V4L2_CTRL_TYPE_BUTTON        = 4,
13902 +};
13903 +
13904 +enum v4l2_tuner_type {
13905 +       V4L2_TUNER_RADIO             = 1,
13906 +       V4L2_TUNER_ANALOG_TV         = 2,
13907 +};
13908 +
13909 +enum v4l2_memory {
13910 +       V4L2_MEMORY_MMAP             = 1,
13911 +       V4L2_MEMORY_USERPTR          = 2,
13912 +       V4L2_MEMORY_OVERLAY          = 3,
13913 +};
13914 +
13915 +/* see also http://vektor.theorem.ca/graphics/ycbcr/ */
13916 +enum v4l2_colorspace {
13917 +       /* ITU-R 601 -- broadcast NTSC/PAL */
13918 +       V4L2_COLORSPACE_SMPTE170M     = 1,
13919 +
13920 +       /* 1125-Line (US) HDTV */
13921 +       V4L2_COLORSPACE_SMPTE240M     = 2,
13922 +
13923 +       /* HD and modern captures. */
13924 +       V4L2_COLORSPACE_REC709        = 3,
13925 +
13926 +       /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */
13927 +       V4L2_COLORSPACE_BT878         = 4,
13928 +
13929 +       /* These should be useful.  Assume 601 extents. */
13930 +       V4L2_COLORSPACE_470_SYSTEM_M  = 5,
13931 +       V4L2_COLORSPACE_470_SYSTEM_BG = 6,
13932 +
13933 +       /* I know there will be cameras that send this.  So, this is
13934 +        * unspecified chromaticities and full 0-255 on each of the
13935 +        * Y'CbCr components
13936 +        */
13937 +       V4L2_COLORSPACE_JPEG          = 7,
13938 +
13939 +       /* For RGB colourspaces, this is probably a good start. */
13940 +       V4L2_COLORSPACE_SRGB          = 8,
13941 +};
13942 +
13943 +enum v4l2_priority {
13944 +       V4L2_PRIORITY_UNSET       = 0,  /* not initialized */
13945 +       V4L2_PRIORITY_BACKGROUND  = 1,
13946 +       V4L2_PRIORITY_INTERACTIVE = 2,
13947 +       V4L2_PRIORITY_RECORD      = 3,
13948 +       V4L2_PRIORITY_DEFAULT     = V4L2_PRIORITY_INTERACTIVE,
13949 +};
13950 +
13951 +struct v4l2_rect {
13952 +       __s32   left;
13953 +       __s32   top;
13954 +       __s32   width;
13955 +       __s32   height;
13956 +};
13957 +
13958 +struct v4l2_fract {
13959 +       __u32   numerator;
13960 +       __u32   denominator;
13961 +};
13962 +
13963 +/*
13964 + *     D R I V E R   C A P A B I L I T I E S
13965 + */
13966 +struct v4l2_capability
13967 +{
13968 +       __u8    driver[16];     /* i.e. "bttv" */
13969 +       __u8    card[32];       /* i.e. "Hauppauge WinTV" */
13970 +       __u8    bus_info[32];   /* "PCI:" + pci_name(pci_dev) */
13971 +       __u32   version;        /* should use KERNEL_VERSION() */
13972 +       __u32   capabilities;   /* Device capabilities */
13973 +       __u32   reserved[4];
13974 +};
13975 +
13976 +/* Values for 'capabilities' field */
13977 +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001  /* Is a video capture device */
13978 +#define V4L2_CAP_VIDEO_OUTPUT  0x00000002  /* Is a video output device */
13979 +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004  /* Can do video overlay */
13980 +#define V4L2_CAP_VBI_CAPTURE   0x00000010  /* Is a VBI capture device */
13981 +#define V4L2_CAP_VBI_OUTPUT    0x00000020  /* Is a VBI output device */
13982 +#define V4L2_CAP_RDS_CAPTURE   0x00000100  /* RDS data capture */
13983 +
13984 +#define V4L2_CAP_TUNER         0x00010000  /* has a tuner */
13985 +#define V4L2_CAP_AUDIO         0x00020000  /* has audio support */
13986 +#define V4L2_CAP_RADIO         0x00040000  /* is a radio device */
13987 +
13988 +#define V4L2_CAP_READWRITE      0x01000000  /* read/write systemcalls */
13989 +#define V4L2_CAP_ASYNCIO        0x02000000  /* async I/O */
13990 +#define V4L2_CAP_STREAMING      0x04000000  /* streaming I/O ioctls */
13991 +
13992 +/*
13993 + *     V I D E O   I M A G E   F O R M A T
13994 + */
13995 +
13996 +struct v4l2_pix_format
13997 +{
13998 +       __u32                   width;
13999 +       __u32                   height;
14000 +       __u32                   pixelformat;
14001 +       enum v4l2_field         field;
14002 +       __u32                   bytesperline;   /* for padding, zero if unused */
14003 +       __u32                   sizeimage;
14004 +        enum v4l2_colorspace   colorspace;
14005 +       __u32                   priv;           /* private data, depends on pixelformat */
14006 +};
14007 +
14008 +/*           Pixel format    FOURCC                  depth  Description   */
14009 +#define V4L2_PIX_FMT_RGB332  v4l2_fourcc('R','G','B','1') /*  8  RGB-3-3-2     */
14010 +#define V4L2_PIX_FMT_RGB555  v4l2_fourcc('R','G','B','O') /* 16  RGB-5-5-5     */
14011 +#define V4L2_PIX_FMT_RGB565  v4l2_fourcc('R','G','B','P') /* 16  RGB-5-6-5     */
14012 +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R','G','B','Q') /* 16  RGB-5-5-5 BE  */
14013 +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R','G','B','R') /* 16  RGB-5-6-5 BE  */
14014 +#define V4L2_PIX_FMT_BGR24   v4l2_fourcc('B','G','R','3') /* 24  BGR-8-8-8     */
14015 +#define V4L2_PIX_FMT_RGB24   v4l2_fourcc('R','G','B','3') /* 24  RGB-8-8-8     */
14016 +#define V4L2_PIX_FMT_BGR32   v4l2_fourcc('B','G','R','4') /* 32  BGR-8-8-8-8   */
14017 +#define V4L2_PIX_FMT_RGB32   v4l2_fourcc('R','G','B','4') /* 32  RGB-8-8-8-8   */
14018 +#define V4L2_PIX_FMT_GREY    v4l2_fourcc('G','R','E','Y') /*  8  Greyscale     */
14019 +#define V4L2_PIX_FMT_YVU410  v4l2_fourcc('Y','V','U','9') /*  9  YVU 4:1:0     */
14020 +#define V4L2_PIX_FMT_YVU420  v4l2_fourcc('Y','V','1','2') /* 12  YVU 4:2:0     */
14021 +#define V4L2_PIX_FMT_YUYV    v4l2_fourcc('Y','U','Y','V') /* 16  YUV 4:2:2     */
14022 +#define V4L2_PIX_FMT_UYVY    v4l2_fourcc('U','Y','V','Y') /* 16  YUV 4:2:2     */
14023 +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4','2','2','P') /* 16  YVU422 planar */
14024 +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4','1','1','P') /* 16  YVU411 planar */
14025 +#define V4L2_PIX_FMT_Y41P    v4l2_fourcc('Y','4','1','P') /* 12  YUV 4:1:1     */
14026 +
14027 +/* two planes -- one Y, one Cr + Cb interleaved  */
14028 +#define V4L2_PIX_FMT_NV12    v4l2_fourcc('N','V','1','2') /* 12  Y/CbCr 4:2:0  */
14029 +#define V4L2_PIX_FMT_NV21    v4l2_fourcc('N','V','2','1') /* 12  Y/CrCb 4:2:0  */
14030 +
14031 +/*  The following formats are not defined in the V4L2 specification */
14032 +#define V4L2_PIX_FMT_YUV410  v4l2_fourcc('Y','U','V','9') /*  9  YUV 4:1:0     */
14033 +#define V4L2_PIX_FMT_YUV420  v4l2_fourcc('Y','U','1','2') /* 12  YUV 4:2:0     */
14034 +#define V4L2_PIX_FMT_YYUV    v4l2_fourcc('Y','Y','U','V') /* 16  YUV 4:2:2     */
14035 +#define V4L2_PIX_FMT_HI240   v4l2_fourcc('H','I','2','4') /*  8  8-bit color   */
14036 +
14037 +/* compressed formats */
14038 +#define V4L2_PIX_FMT_MJPEG    v4l2_fourcc('M','J','P','G') /* Motion-JPEG   */
14039 +#define V4L2_PIX_FMT_JPEG     v4l2_fourcc('J','P','E','G') /* JFIF JPEG     */
14040 +#define V4L2_PIX_FMT_DV       v4l2_fourcc('d','v','s','d') /* 1394          */
14041 +#define V4L2_PIX_FMT_MPEG     v4l2_fourcc('M','P','E','G') /* MPEG          */
14042 +
14043 +/*  Vendor-specific formats   */
14044 +#define V4L2_PIX_FMT_WNVA     v4l2_fourcc('W','N','V','A') /* Winnov hw compress */
14045 +
14046 +/*
14047 + *     F O R M A T   E N U M E R A T I O N
14048 + */
14049 +struct v4l2_fmtdesc
14050 +{
14051 +       __u32               index;             /* Format number      */
14052 +       enum v4l2_buf_type  type;              /* buffer type        */
14053 +       __u32               flags;
14054 +       __u8                description[32];   /* Description string */
14055 +       __u32               pixelformat;       /* Format fourcc      */
14056 +       __u32               reserved[4];
14057 +};
14058 +
14059 +#define V4L2_FMT_FLAG_COMPRESSED 0x0001
14060 +
14061 +
14062 +/*
14063 + *     T I M E C O D E
14064 + */
14065 +struct v4l2_timecode
14066 +{
14067 +       __u32   type;
14068 +       __u32   flags;
14069 +       __u8    frames;
14070 +       __u8    seconds;
14071 +       __u8    minutes;
14072 +       __u8    hours;
14073 +       __u8    userbits[4];
14074 +};
14075 +
14076 +/*  Type  */
14077 +#define V4L2_TC_TYPE_24FPS             1
14078 +#define V4L2_TC_TYPE_25FPS             2
14079 +#define V4L2_TC_TYPE_30FPS             3
14080 +#define V4L2_TC_TYPE_50FPS             4
14081 +#define V4L2_TC_TYPE_60FPS             5
14082 +
14083 +/*  Flags  */
14084 +#define V4L2_TC_FLAG_DROPFRAME         0x0001 /* "drop-frame" mode */
14085 +#define V4L2_TC_FLAG_COLORFRAME                0x0002
14086 +#define V4L2_TC_USERBITS_field         0x000C
14087 +#define V4L2_TC_USERBITS_USERDEFINED   0x0000
14088 +#define V4L2_TC_USERBITS_8BITCHARS     0x0008
14089 +/* The above is based on SMPTE timecodes */
14090 +
14091 +
14092 +/*
14093 + *     C O M P R E S S I O N   P A R A M E T E R S
14094 + */
14095 +#if 0
14096 +/* ### generic compression settings don't work, there is too much
14097 + * ### codec-specific stuff.  Maybe reuse that for MPEG codec settings
14098 + * ### later ... */
14099 +struct v4l2_compression
14100 +{
14101 +       __u32   quality;
14102 +       __u32   keyframerate;
14103 +       __u32   pframerate;
14104 +       __u32   reserved[5];
14105 +
14106 +/*  what we'll need for MPEG, extracted from some postings on
14107 +    the v4l list (Gert Vervoort, PlasmaJohn).
14108 +
14109 +system stream:
14110 +  - type: elementary stream(ES), packatised elementary stream(s) (PES)
14111 +    program stream(PS), transport stream(TS)
14112 +  - system bitrate
14113 +  - PS packet size (DVD: 2048 bytes, VCD: 2324 bytes)
14114 +  - TS video PID
14115 +  - TS audio PID
14116 +  - TS PCR PID
14117 +  - TS system information tables (PAT, PMT, CAT, NIT and SIT)
14118 +  - (MPEG-1 systems stream vs. MPEG-2 program stream (TS not supported
14119 +    by MPEG-1 systems)
14120 +
14121 +audio:
14122 +  - type: MPEG (+Layer I,II,III), AC-3, LPCM
14123 +  - bitrate
14124 +  - sampling frequency (DVD: 48 Khz, VCD: 44.1 KHz, 32 kHz)
14125 +  - Trick Modes? (ff, rew)
14126 +  - Copyright
14127 +  - Inverse Telecine
14128 +
14129 +video:
14130 +  - picturesize (SIF, 1/2 D1, 2/3 D1, D1) and PAL/NTSC norm can be set
14131 +    through excisting V4L2 controls
14132 +  - noise reduction, parameters encoder specific?
14133 +  - MPEG video version: MPEG-1, MPEG-2
14134 +  - GOP (Group Of Pictures) definition:
14135 +    - N: number of frames per GOP
14136 +    - M: distance between reference (I,P) frames
14137 +    - open/closed GOP
14138 +  - quantiser matrix: inter Q matrix (64 bytes) and intra Q matrix (64 bytes)
14139 +  - quantiser scale: linear or logarithmic
14140 +  - scanning: alternate or zigzag
14141 +  - bitrate mode: CBR (constant bitrate) or VBR (variable bitrate).
14142 +  - target video bitrate for CBR
14143 +  - target video bitrate for VBR
14144 +  - maximum video bitrate for VBR - min. quantiser value for VBR
14145 +  - max. quantiser value for VBR
14146 +  - adaptive quantisation value
14147 +  - return the number of bytes per GOP or bitrate for bitrate monitoring
14148 +
14149 +*/
14150 +};
14151 +#endif
14152 +
14153 +struct v4l2_jpegcompression
14154 +{
14155 +       int quality;
14156 +
14157 +       int  APPn;              /* Number of APP segment to be written,
14158 +                                * must be 0..15 */
14159 +       int  APP_len;           /* Length of data in JPEG APPn segment */
14160 +       char APP_data[60];      /* Data in the JPEG APPn segment. */
14161 +
14162 +       int  COM_len;           /* Length of data in JPEG COM segment */
14163 +       char COM_data[60];      /* Data in JPEG COM segment */
14164 +
14165 +       __u32 jpeg_markers;     /* Which markers should go into the JPEG
14166 +                                * output. Unless you exactly know what
14167 +                                * you do, leave them untouched.
14168 +                                * Inluding less markers will make the
14169 +                                * resulting code smaller, but there will
14170 +                                * be fewer aplications which can read it.
14171 +                                * The presence of the APP and COM marker
14172 +                                * is influenced by APP_len and COM_len
14173 +                                * ONLY, not by this property! */
14174 +
14175 +#define V4L2_JPEG_MARKER_DHT (1<<3)    /* Define Huffman Tables */
14176 +#define V4L2_JPEG_MARKER_DQT (1<<4)    /* Define Quantization Tables */
14177 +#define V4L2_JPEG_MARKER_DRI (1<<5)    /* Define Restart Interval */
14178 +#define V4L2_JPEG_MARKER_COM (1<<6)    /* Comment segment */
14179 +#define V4L2_JPEG_MARKER_APP (1<<7)    /* App segment, driver will
14180 +                                        * allways use APP0 */
14181 +};
14182 +
14183 +
14184 +/*
14185 + *     M E M O R Y - M A P P I N G   B U F F E R S
14186 + */
14187 +struct v4l2_requestbuffers
14188 +{
14189 +       __u32                   count;
14190 +       enum v4l2_buf_type      type;
14191 +       enum v4l2_memory        memory;
14192 +       __u32                   reserved[2];
14193 +};
14194 +
14195 +struct v4l2_buffer
14196 +{
14197 +       __u32                   index;
14198 +       enum v4l2_buf_type      type;
14199 +       __u32                   bytesused;
14200 +       __u32                   flags;
14201 +       enum v4l2_field         field;
14202 +       struct timeval          timestamp;
14203 +       struct v4l2_timecode    timecode;
14204 +       __u32                   sequence;
14205 +
14206 +       /* memory location */
14207 +       enum v4l2_memory        memory;
14208 +       union {
14209 +               __u32           offset;
14210 +               unsigned long   userptr;
14211 +       } m;
14212 +       __u32                   length;
14213 +
14214 +       __u32                   reserved[2];
14215 +};
14216 +
14217 +/*  Flags for 'flags' field */
14218 +#define V4L2_BUF_FLAG_MAPPED   0x0001  /* Buffer is mapped (flag) */
14219 +#define V4L2_BUF_FLAG_QUEUED   0x0002  /* Buffer is queued for processing */
14220 +#define V4L2_BUF_FLAG_DONE     0x0004  /* Buffer is ready */
14221 +#define V4L2_BUF_FLAG_KEYFRAME 0x0008  /* Image is a keyframe (I-frame) */
14222 +#define V4L2_BUF_FLAG_PFRAME   0x0010  /* Image is a P-frame */
14223 +#define V4L2_BUF_FLAG_BFRAME   0x0020  /* Image is a B-frame */
14224 +#define V4L2_BUF_FLAG_TIMECODE 0x0100  /* timecode field is valid */
14225 +
14226 +/*
14227 + *     O V E R L A Y   P R E V I E W
14228 + */
14229 +struct v4l2_framebuffer
14230 +{
14231 +       __u32                   capability;
14232 +       __u32                   flags;
14233 +/* FIXME: in theory we should pass something like PCI device + memory
14234 + * region + offset instead of some physical address */
14235 +       void*                   base;
14236 +       struct v4l2_pix_format  fmt;
14237 +};
14238 +/*  Flags for the 'capability' field. Read only */
14239 +#define V4L2_FBUF_CAP_EXTERNOVERLAY    0x0001
14240 +#define V4L2_FBUF_CAP_CHROMAKEY                0x0002
14241 +#define V4L2_FBUF_CAP_LIST_CLIPPING     0x0004
14242 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING  0x0008
14243 +/*  Flags for the 'flags' field. */
14244 +#define V4L2_FBUF_FLAG_PRIMARY         0x0001
14245 +#define V4L2_FBUF_FLAG_OVERLAY         0x0002
14246 +#define V4L2_FBUF_FLAG_CHROMAKEY       0x0004
14247 +
14248 +struct v4l2_clip
14249 +{
14250 +       struct v4l2_rect        c;
14251 +       struct v4l2_clip        *next;
14252 +};
14253 +
14254 +struct v4l2_window
14255 +{
14256 +       struct v4l2_rect        w;
14257 +       enum v4l2_field         field;
14258 +       __u32                   chromakey;
14259 +       struct v4l2_clip        *clips;
14260 +       __u32                   clipcount;
14261 +       void                    *bitmap;
14262 +};
14263 +
14264 +
14265 +/*
14266 + *     C A P T U R E   P A R A M E T E R S
14267 + */
14268 +struct v4l2_captureparm
14269 +{
14270 +       __u32              capability;    /*  Supported modes */
14271 +       __u32              capturemode;   /*  Current mode */
14272 +       struct v4l2_fract  timeperframe;  /*  Time per frame in .1us units */
14273 +       __u32              extendedmode;  /*  Driver-specific extensions */
14274 +       __u32              readbuffers;   /*  # of buffers for read */
14275 +       __u32              reserved[4];
14276 +};
14277 +/*  Flags for 'capability' and 'capturemode' fields */
14278 +#define V4L2_MODE_HIGHQUALITY  0x0001  /*  High quality imaging mode */
14279 +#define V4L2_CAP_TIMEPERFRAME  0x1000  /*  timeperframe field is supported */
14280 +
14281 +struct v4l2_outputparm
14282 +{
14283 +       __u32              capability;   /*  Supported modes */
14284 +       __u32              outputmode;   /*  Current mode */
14285 +       struct v4l2_fract  timeperframe; /*  Time per frame in seconds */
14286 +       __u32              extendedmode; /*  Driver-specific extensions */
14287 +       __u32              writebuffers; /*  # of buffers for write */
14288 +       __u32              reserved[4];
14289 +};
14290 +
14291 +/*
14292 + *     I N P U T   I M A G E   C R O P P I N G
14293 + */
14294 +
14295 +struct v4l2_cropcap {
14296 +       enum v4l2_buf_type      type;
14297 +        struct v4l2_rect        bounds;
14298 +        struct v4l2_rect        defrect;
14299 +        struct v4l2_fract       pixelaspect;
14300 +};
14301 +
14302 +struct v4l2_crop {
14303 +       enum v4l2_buf_type      type;
14304 +       struct v4l2_rect        c;
14305 +};
14306 +
14307 +/*
14308 + *      A N A L O G   V I D E O   S T A N D A R D
14309 + */
14310 +
14311 +typedef __u64 v4l2_std_id;
14312 +
14313 +/* one bit for each */
14314 +#define V4L2_STD_PAL_B          ((v4l2_std_id)0x00000001)
14315 +#define V4L2_STD_PAL_B1         ((v4l2_std_id)0x00000002)
14316 +#define V4L2_STD_PAL_G          ((v4l2_std_id)0x00000004)
14317 +#define V4L2_STD_PAL_H          ((v4l2_std_id)0x00000008)
14318 +#define V4L2_STD_PAL_I          ((v4l2_std_id)0x00000010)
14319 +#define V4L2_STD_PAL_D          ((v4l2_std_id)0x00000020)
14320 +#define V4L2_STD_PAL_D1         ((v4l2_std_id)0x00000040)
14321 +#define V4L2_STD_PAL_K          ((v4l2_std_id)0x00000080)
14322 +
14323 +#define V4L2_STD_PAL_M          ((v4l2_std_id)0x00000100)
14324 +#define V4L2_STD_PAL_N          ((v4l2_std_id)0x00000200)
14325 +#define V4L2_STD_PAL_Nc         ((v4l2_std_id)0x00000400)
14326 +#define V4L2_STD_PAL_60         ((v4l2_std_id)0x00000800)
14327 +
14328 +#define V4L2_STD_NTSC_M         ((v4l2_std_id)0x00001000)
14329 +#define V4L2_STD_NTSC_M_JP      ((v4l2_std_id)0x00002000)
14330 +
14331 +#define V4L2_STD_SECAM_B        ((v4l2_std_id)0x00010000)
14332 +#define V4L2_STD_SECAM_D        ((v4l2_std_id)0x00020000)
14333 +#define V4L2_STD_SECAM_G        ((v4l2_std_id)0x00040000)
14334 +#define V4L2_STD_SECAM_H        ((v4l2_std_id)0x00080000)
14335 +#define V4L2_STD_SECAM_K        ((v4l2_std_id)0x00100000)
14336 +#define V4L2_STD_SECAM_K1       ((v4l2_std_id)0x00200000)
14337 +#define V4L2_STD_SECAM_L        ((v4l2_std_id)0x00400000)
14338 +
14339 +/* ATSC/HDTV */
14340 +#define V4L2_STD_ATSC_8_VSB     ((v4l2_std_id)0x01000000)
14341 +#define V4L2_STD_ATSC_16_VSB    ((v4l2_std_id)0x02000000)
14342 +
14343 +/* some common needed stuff */
14344 +#define V4L2_STD_PAL_BG                (V4L2_STD_PAL_B         |\
14345 +                                V4L2_STD_PAL_B1        |\
14346 +                                V4L2_STD_PAL_G)
14347 +#define V4L2_STD_PAL_DK                (V4L2_STD_PAL_D         |\
14348 +                                V4L2_STD_PAL_D1        |\
14349 +                                V4L2_STD_PAL_K)
14350 +#define V4L2_STD_PAL           (V4L2_STD_PAL_BG        |\
14351 +                                V4L2_STD_PAL_DK        |\
14352 +                                V4L2_STD_PAL_H         |\
14353 +                                V4L2_STD_PAL_I)
14354 +#define V4L2_STD_NTSC           (V4L2_STD_NTSC_M       |\
14355 +                                V4L2_STD_NTSC_M_JP)
14356 +#define V4L2_STD_SECAM         (V4L2_STD_SECAM_B       |\
14357 +                                V4L2_STD_SECAM_D       |\
14358 +                                V4L2_STD_SECAM_G       |\
14359 +                                V4L2_STD_SECAM_H       |\
14360 +                                V4L2_STD_SECAM_K       |\
14361 +                                V4L2_STD_SECAM_K1      |\
14362 +                                V4L2_STD_SECAM_L)
14363 +
14364 +#define V4L2_STD_525_60                (V4L2_STD_PAL_M         |\
14365 +                                V4L2_STD_PAL_60        |\
14366 +                                V4L2_STD_NTSC)
14367 +#define V4L2_STD_625_50                (V4L2_STD_PAL           |\
14368 +                                V4L2_STD_PAL_N         |\
14369 +                                V4L2_STD_PAL_Nc        |\
14370 +                                V4L2_STD_SECAM)
14371 +
14372 +#define V4L2_STD_UNKNOWN        0
14373 +#define V4L2_STD_ALL            (V4L2_STD_525_60       |\
14374 +                                V4L2_STD_625_50)
14375 +
14376 +struct v4l2_standard
14377 +{
14378 +       __u32                index;
14379 +       v4l2_std_id          id;
14380 +       __u8                 name[24];
14381 +       struct v4l2_fract    frameperiod; /* Frames, not fields */
14382 +       __u32                framelines;
14383 +       __u32                reserved[4];
14384 +};
14385 +
14386 +
14387 +/*
14388 + *     V I D E O   I N P U T S
14389 + */
14390 +struct v4l2_input
14391 +{
14392 +       __u32        index;             /*  Which input */
14393 +       __u8         name[32];          /*  Label */
14394 +       __u32        type;              /*  Type of input */
14395 +       __u32        audioset;          /*  Associated audios (bitfield) */
14396 +       __u32        tuner;             /*  Associated tuner */
14397 +       v4l2_std_id  std;
14398 +       __u32        status;
14399 +       __u32        reserved[4];
14400 +};
14401 +/*  Values for the 'type' field */
14402 +#define V4L2_INPUT_TYPE_TUNER          1
14403 +#define V4L2_INPUT_TYPE_CAMERA         2
14404 +
14405 +/* field 'status' - general */
14406 +#define V4L2_IN_ST_NO_POWER    0x00000001  /* Attached device is off */
14407 +#define V4L2_IN_ST_NO_SIGNAL   0x00000002
14408 +#define V4L2_IN_ST_NO_COLOR    0x00000004
14409 +
14410 +/* field 'status' - analog */
14411 +#define V4L2_IN_ST_NO_H_LOCK   0x00000100  /* No horizontal sync lock */
14412 +#define V4L2_IN_ST_COLOR_KILL  0x00000200  /* Color killer is active */
14413 +
14414 +/* field 'status' - digital */
14415 +#define V4L2_IN_ST_NO_SYNC     0x00010000  /* No synchronization lock */
14416 +#define V4L2_IN_ST_NO_EQU      0x00020000  /* No equalizer lock */
14417 +#define V4L2_IN_ST_NO_CARRIER  0x00040000  /* Carrier recovery failed */
14418 +
14419 +/* field 'status' - VCR and set-top box */
14420 +#define V4L2_IN_ST_MACROVISION 0x01000000  /* Macrovision detected */
14421 +#define V4L2_IN_ST_NO_ACCESS   0x02000000  /* Conditional access denied */
14422 +#define V4L2_IN_ST_VTR         0x04000000  /* VTR time constant */
14423 +
14424 +/*
14425 + *     V I D E O   O U T P U T S
14426 + */
14427 +struct v4l2_output
14428 +{
14429 +       __u32        index;             /*  Which output */
14430 +       __u8         name[32];          /*  Label */
14431 +       __u32        type;              /*  Type of output */
14432 +       __u32        audioset;          /*  Associated audios (bitfield) */
14433 +       __u32        modulator;         /*  Associated modulator */
14434 +       v4l2_std_id  std;
14435 +       __u32        reserved[4];
14436 +};
14437 +/*  Values for the 'type' field */
14438 +#define V4L2_OUTPUT_TYPE_MODULATOR             1
14439 +#define V4L2_OUTPUT_TYPE_ANALOG                        2
14440 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY      3
14441 +
14442 +/*
14443 + *     C O N T R O L S
14444 + */
14445 +struct v4l2_control
14446 +{
14447 +       __u32                id;
14448 +       __s32                value;
14449 +};
14450 +
14451 +/*  Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
14452 +struct v4l2_queryctrl
14453 +{
14454 +       __u32                id;
14455 +       enum v4l2_ctrl_type  type;
14456 +       __u8                 name[32];  /* Whatever */
14457 +       __s32                minimum;   /* Note signedness */
14458 +       __s32                maximum;
14459 +       __s32                step;
14460 +       __s32                default_value;
14461 +       __u32                flags;
14462 +       __u32                reserved[2];
14463 +};
14464 +
14465 +/*  Used in the VIDIOC_QUERYMENU ioctl for querying menu items */
14466 +struct v4l2_querymenu
14467 +{
14468 +       __u32           id;
14469 +       __u32           index;
14470 +       __u8            name[32];       /* Whatever */
14471 +       __u32           reserved;
14472 +};
14473 +
14474 +/*  Control flags  */
14475 +#define V4L2_CTRL_FLAG_DISABLED                0x0001
14476 +#define V4L2_CTRL_FLAG_GRABBED         0x0002
14477 +
14478 +/*  Control IDs defined by V4L2 */
14479 +#define V4L2_CID_BASE                  0x00980900
14480 +/*  IDs reserved for driver specific controls */
14481 +#define V4L2_CID_PRIVATE_BASE          0x08000000
14482 +
14483 +#define V4L2_CID_BRIGHTNESS            (V4L2_CID_BASE+0)
14484 +#define V4L2_CID_CONTRAST              (V4L2_CID_BASE+1)
14485 +#define V4L2_CID_SATURATION            (V4L2_CID_BASE+2)
14486 +#define V4L2_CID_HUE                   (V4L2_CID_BASE+3)
14487 +#define V4L2_CID_AUDIO_VOLUME          (V4L2_CID_BASE+5)
14488 +#define V4L2_CID_AUDIO_BALANCE         (V4L2_CID_BASE+6)
14489 +#define V4L2_CID_AUDIO_BASS            (V4L2_CID_BASE+7)
14490 +#define V4L2_CID_AUDIO_TREBLE          (V4L2_CID_BASE+8)
14491 +#define V4L2_CID_AUDIO_MUTE            (V4L2_CID_BASE+9)
14492 +#define V4L2_CID_AUDIO_LOUDNESS                (V4L2_CID_BASE+10)
14493 +#define V4L2_CID_BLACK_LEVEL           (V4L2_CID_BASE+11)
14494 +#define V4L2_CID_AUTO_WHITE_BALANCE    (V4L2_CID_BASE+12)
14495 +#define V4L2_CID_DO_WHITE_BALANCE      (V4L2_CID_BASE+13)
14496 +#define V4L2_CID_RED_BALANCE           (V4L2_CID_BASE+14)
14497 +#define V4L2_CID_BLUE_BALANCE          (V4L2_CID_BASE+15)
14498 +#define V4L2_CID_GAMMA                 (V4L2_CID_BASE+16)
14499 +#define V4L2_CID_WHITENESS             (V4L2_CID_GAMMA) /* ? Not sure */
14500 +#define V4L2_CID_EXPOSURE              (V4L2_CID_BASE+17)
14501 +#define V4L2_CID_AUTOGAIN              (V4L2_CID_BASE+18)
14502 +#define V4L2_CID_GAIN                  (V4L2_CID_BASE+19)
14503 +#define V4L2_CID_HFLIP                 (V4L2_CID_BASE+20)
14504 +#define V4L2_CID_VFLIP                 (V4L2_CID_BASE+21)
14505 +#define V4L2_CID_HCENTER               (V4L2_CID_BASE+22)
14506 +#define V4L2_CID_VCENTER               (V4L2_CID_BASE+23)
14507 +#define V4L2_CID_LASTP1                        (V4L2_CID_BASE+24) /* last CID + 1 */
14508 +
14509 +/*
14510 + *     T U N I N G
14511 + */
14512 +struct v4l2_tuner
14513 +{
14514 +       __u32                   index;
14515 +       __u8                    name[32];
14516 +       enum v4l2_tuner_type    type;
14517 +       __u32                   capability;
14518 +       __u32                   rangelow;
14519 +       __u32                   rangehigh;
14520 +       __u32                   rxsubchans;
14521 +       __u32                   audmode;
14522 +       __s32                   signal;
14523 +       __s32                   afc;
14524 +       __u32                   reserved[4];
14525 +};
14526 +
14527 +struct v4l2_modulator
14528 +{
14529 +       __u32                   index;
14530 +       __u8                    name[32];
14531 +       __u32                   capability;
14532 +       __u32                   rangelow;
14533 +       __u32                   rangehigh;
14534 +       __u32                   txsubchans;
14535 +       __u32                   reserved[4];
14536 +};
14537 +
14538 +/*  Flags for the 'capability' field */
14539 +#define V4L2_TUNER_CAP_LOW             0x0001
14540 +#define V4L2_TUNER_CAP_NORM            0x0002
14541 +#define V4L2_TUNER_CAP_STEREO          0x0010
14542 +#define V4L2_TUNER_CAP_LANG2           0x0020
14543 +#define V4L2_TUNER_CAP_SAP             0x0020
14544 +#define V4L2_TUNER_CAP_LANG1           0x0040
14545 +
14546 +/*  Flags for the 'rxsubchans' field */
14547 +#define V4L2_TUNER_SUB_MONO            0x0001
14548 +#define V4L2_TUNER_SUB_STEREO          0x0002
14549 +#define V4L2_TUNER_SUB_LANG2           0x0004
14550 +#define V4L2_TUNER_SUB_SAP             0x0004
14551 +#define V4L2_TUNER_SUB_LANG1           0x0008
14552 +
14553 +/*  Values for the 'audmode' field */
14554 +#define V4L2_TUNER_MODE_MONO           0x0000
14555 +#define V4L2_TUNER_MODE_STEREO         0x0001
14556 +#define V4L2_TUNER_MODE_LANG2          0x0002
14557 +#define V4L2_TUNER_MODE_SAP            0x0002
14558 +#define V4L2_TUNER_MODE_LANG1          0x0003
14559 +
14560 +struct v4l2_frequency
14561 +{
14562 +       __u32                 tuner;
14563 +       enum v4l2_tuner_type  type;
14564 +        __u32                frequency;
14565 +       __u32                 reserved[8];
14566 +};
14567 +
14568 +/*
14569 + *     A U D I O
14570 + */
14571 +struct v4l2_audio
14572 +{
14573 +       __u32   index;
14574 +       __u8    name[32];
14575 +       __u32   capability;
14576 +       __u32   mode;
14577 +       __u32   reserved[2];
14578 +};
14579 +/*  Flags for the 'capability' field */
14580 +#define V4L2_AUDCAP_STEREO             0x00001
14581 +#define V4L2_AUDCAP_AVL                        0x00002
14582 +
14583 +/*  Flags for the 'mode' field */
14584 +#define V4L2_AUDMODE_AVL               0x00001
14585 +
14586 +struct v4l2_audioout
14587 +{
14588 +       __u32   index;
14589 +       __u8    name[32];
14590 +       __u32   capability;
14591 +       __u32   mode;
14592 +       __u32   reserved[2];
14593 +};
14594 +
14595 +/*
14596 + *     D A T A   S E R V I C E S   ( V B I )
14597 + *
14598 + *     Data services API by Michael Schimek
14599 + */
14600 +
14601 +struct v4l2_vbi_format
14602 +{
14603 +       __u32   sampling_rate;          /* in 1 Hz */
14604 +       __u32   offset;
14605 +       __u32   samples_per_line;
14606 +       __u32   sample_format;          /* V4L2_PIX_FMT_* */
14607 +       __s32   start[2];
14608 +       __u32   count[2];
14609 +       __u32   flags;                  /* V4L2_VBI_* */
14610 +       __u32   reserved[2];            /* must be zero */
14611 +};
14612 +
14613 +/*  VBI flags  */
14614 +#define V4L2_VBI_UNSYNC                (1<< 0)
14615 +#define V4L2_VBI_INTERLACED    (1<< 1)
14616 +
14617 +
14618 +/*
14619 + *     A G G R E G A T E   S T R U C T U R E S
14620 + */
14621 +
14622 +/*     Stream data format
14623 + */
14624 +struct v4l2_format
14625 +{
14626 +       enum v4l2_buf_type type;
14627 +       union
14628 +       {
14629 +               struct v4l2_pix_format  pix;  // V4L2_BUF_TYPE_VIDEO_CAPTURE
14630 +               struct v4l2_window      win;  // V4L2_BUF_TYPE_VIDEO_OVERLAY
14631 +               struct v4l2_vbi_format  vbi;  // V4L2_BUF_TYPE_VBI_CAPTURE
14632 +               __u8    raw_data[200];        // user-defined
14633 +       } fmt;
14634 +};
14635 +
14636 +
14637 +/*     Stream type-dependent parameters
14638 + */
14639 +struct v4l2_streamparm
14640 +{
14641 +       enum v4l2_buf_type type;
14642 +       union
14643 +       {
14644 +               struct v4l2_captureparm capture;
14645 +               struct v4l2_outputparm  output;
14646 +               __u8    raw_data[200];  /* user-defined */
14647 +       } parm;
14648 +};
14649 +
14650 +
14651 +
14652 +/*
14653 + *     I O C T L   C O D E S   F O R   V I D E O   D E V I C E S
14654 + *
14655 + */
14656 +#define VIDIOC_QUERYCAP                _IOR  ('V',  0, struct v4l2_capability)
14657 +#define VIDIOC_RESERVED                _IO   ('V',  1)
14658 +#define VIDIOC_ENUM_FMT         _IOWR ('V',  2, struct v4l2_fmtdesc)
14659 +#define VIDIOC_G_FMT           _IOWR ('V',  4, struct v4l2_format)
14660 +#define VIDIOC_S_FMT           _IOWR ('V',  5, struct v4l2_format)
14661 +#if 0
14662 +#define VIDIOC_G_COMP          _IOR  ('V',  6, struct v4l2_compression)
14663 +#define VIDIOC_S_COMP          _IOW  ('V',  7, struct v4l2_compression)
14664 +#endif
14665 +#define VIDIOC_REQBUFS         _IOWR ('V',  8, struct v4l2_requestbuffers)
14666 +#define VIDIOC_QUERYBUF                _IOWR ('V',  9, struct v4l2_buffer)
14667 +#define VIDIOC_G_FBUF          _IOR  ('V', 10, struct v4l2_framebuffer)
14668 +#define VIDIOC_S_FBUF          _IOW  ('V', 11, struct v4l2_framebuffer)
14669 +#define VIDIOC_OVERLAY         _IOW  ('V', 14, int)
14670 +#define VIDIOC_QBUF            _IOWR ('V', 15, struct v4l2_buffer)
14671 +#define VIDIOC_DQBUF           _IOWR ('V', 17, struct v4l2_buffer)
14672 +#define VIDIOC_STREAMON                _IOW  ('V', 18, int)
14673 +#define VIDIOC_STREAMOFF       _IOW  ('V', 19, int)
14674 +#define VIDIOC_G_PARM          _IOWR ('V', 21, struct v4l2_streamparm)
14675 +#define VIDIOC_S_PARM          _IOWR ('V', 22, struct v4l2_streamparm)
14676 +#define VIDIOC_G_STD           _IOR  ('V', 23, v4l2_std_id)
14677 +#define VIDIOC_S_STD           _IOW  ('V', 24, v4l2_std_id)
14678 +#define VIDIOC_ENUMSTD         _IOWR ('V', 25, struct v4l2_standard)
14679 +#define VIDIOC_ENUMINPUT       _IOWR ('V', 26, struct v4l2_input)
14680 +#define VIDIOC_G_CTRL          _IOWR ('V', 27, struct v4l2_control)
14681 +#define VIDIOC_S_CTRL          _IOWR ('V', 28, struct v4l2_control)
14682 +#define VIDIOC_G_TUNER         _IOWR ('V', 29, struct v4l2_tuner)
14683 +#define VIDIOC_S_TUNER         _IOW  ('V', 30, struct v4l2_tuner)
14684 +#define VIDIOC_G_AUDIO         _IOR  ('V', 33, struct v4l2_audio)
14685 +#define VIDIOC_S_AUDIO         _IOW  ('V', 34, struct v4l2_audio)
14686 +#define VIDIOC_QUERYCTRL       _IOWR ('V', 36, struct v4l2_queryctrl)
14687 +#define VIDIOC_QUERYMENU       _IOWR ('V', 37, struct v4l2_querymenu)
14688 +#define VIDIOC_G_INPUT         _IOR  ('V', 38, int)
14689 +#define VIDIOC_S_INPUT         _IOWR ('V', 39, int)
14690 +#define VIDIOC_G_OUTPUT                _IOR  ('V', 46, int)
14691 +#define VIDIOC_S_OUTPUT                _IOWR ('V', 47, int)
14692 +#define VIDIOC_ENUMOUTPUT      _IOWR ('V', 48, struct v4l2_output)
14693 +#define VIDIOC_G_AUDOUT                _IOR  ('V', 49, struct v4l2_audioout)
14694 +#define VIDIOC_S_AUDOUT                _IOW  ('V', 50, struct v4l2_audioout)
14695 +#define VIDIOC_G_MODULATOR     _IOWR ('V', 54, struct v4l2_modulator)
14696 +#define VIDIOC_S_MODULATOR     _IOW  ('V', 55, struct v4l2_modulator)
14697 +#define VIDIOC_G_FREQUENCY     _IOWR ('V', 56, struct v4l2_frequency)
14698 +#define VIDIOC_S_FREQUENCY     _IOW  ('V', 57, struct v4l2_frequency)
14699 +#define VIDIOC_CROPCAP         _IOR  ('V', 58, struct v4l2_cropcap)
14700 +#define VIDIOC_G_CROP          _IOWR ('V', 59, struct v4l2_crop)
14701 +#define VIDIOC_S_CROP          _IOW  ('V', 60, struct v4l2_crop)
14702 +#define VIDIOC_G_JPEGCOMP      _IOR  ('V', 61, struct v4l2_jpegcompression)
14703 +#define VIDIOC_S_JPEGCOMP      _IOW  ('V', 62, struct v4l2_jpegcompression)
14704 +#define VIDIOC_QUERYSTD        _IOR  ('V', 63, v4l2_std_id)
14705 +#define VIDIOC_TRY_FMT         _IOWR ('V', 64, struct v4l2_format)
14706 +#define VIDIOC_ENUMAUDIO       _IOWR ('V', 65, struct v4l2_audio)
14707 +#define VIDIOC_ENUMAUDOUT      _IOWR ('V', 66, struct v4l2_audioout)
14708 +#define VIDIOC_G_PRIORITY       _IOR  ('V', 67, enum v4l2_priority)
14709 +#define VIDIOC_S_PRIORITY       _IOW  ('V', 68, enum v4l2_priority)
14710 +
14711 +/* for compatibility, will go away some day */
14712 +#define VIDIOC_OVERLAY_OLD             _IOWR ('V', 14, int)
14713 +#define VIDIOC_S_PARM_OLD              _IOW  ('V', 22, struct v4l2_streamparm)
14714 +#define VIDIOC_S_CTRL_OLD              _IOW  ('V', 28, struct v4l2_control)
14715 +#define VIDIOC_G_AUDIO_OLD             _IOWR ('V', 33, struct v4l2_audio)
14716 +#define VIDIOC_G_AUDOUT_OLD            _IOWR ('V', 49, struct v4l2_audioout)
14717 +
14718 +#define BASE_VIDIOC_PRIVATE    192             /* 192-255 are private */
14719 +
14720 +
14721 +#ifdef __KERNEL__
14722 +/*
14723 + *
14724 + *     V 4 L 2   D R I V E R   H E L P E R   A P I
14725 + *
14726 + *     Some commonly needed functions for drivers (v4l2-common.o module)
14727 + */
14728 +#include <linux/fs.h>
14729 +
14730 +/*  Video standard functions  */
14731 +extern unsigned int v4l2_video_std_fps(struct v4l2_standard *vs);
14732 +extern int v4l2_video_std_construct(struct v4l2_standard *vs,
14733 +                                   int id, char *name);
14734 +
14735 +/* prority handling */
14736 +struct v4l2_prio_state {
14737 +       atomic_t prios[4];
14738 +};
14739 +int v4l2_prio_init(struct v4l2_prio_state *global);
14740 +int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local,
14741 +                    enum v4l2_priority new);
14742 +int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local);
14743 +int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local);
14744 +enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global);
14745 +int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
14746 +
14747 +/* names for fancy debug output */
14748 +extern char *v4l2_field_names[];
14749 +extern char *v4l2_type_names[];
14750 +extern char *v4l2_ioctl_names[];
14751 +
14752 +/*  Compatibility layer interface  --  v4l1-compat module */
14753 +typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
14754 +                          unsigned int cmd, void *arg);
14755 +int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
14756 +                              int cmd, void *arg, v4l2_kioctl driver_ioctl);
14757 +
14758 +#endif /* __KERNEL__ */
14759 +#endif /* __LINUX_VIDEODEV2_H */
14760 +
14761 +/*
14762 + * Local variables:
14763 + * c-basic-offset: 8
14764 + * End:
14765 + */
14766 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/videodev.c
14767 ===================================================================
14768 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
14769 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/videodev.c        2009-01-02 00:01:56.000000000 +0100
14770 @@ -0,0 +1,332 @@
14771 +/*
14772 + * Video capture interface for Linux Character Device Driver.
14773 + *              based on
14774 + *              Alan Cox, <alan@redhat.com> video4linux
14775 + *
14776 + * Author:      SW.LEE <hitchcar@samsung.com>
14777 + *              2004 (C) Samsung Electronics
14778 + *              Modified for S3C2440/S3C24A0 Interface
14779 + *
14780 + * This file is released under the GPLv2
14781 + */
14782 +
14783 +
14784 +#include <linux/module.h>
14785 +#include <linux/types.h>
14786 +#include <linux/kernel.h>
14787 +#include <linux/sched.h>
14788 +#include <linux/smp_lock.h>
14789 +#include <linux/mm.h>
14790 +#include <linux/string.h>
14791 +#include <linux/errno.h>
14792 +#include <linux/init.h>
14793 +#include <linux/kmod.h>
14794 +#include <linux/slab.h>
14795 +/* #include <linux/devfs_fs_kernel.h> */
14796 +#include <linux/miscdevice.h>
14797 +#include <asm/uaccess.h>
14798 +#include <asm/system.h>
14799 +#include <asm/semaphore.h>
14800 +
14801 +
14802 +
14803 +#define CONFIG_VIDEO_V4L1_COMPAT
14804 +#include <linux/videodev.h>
14805 +#include "camif.h"
14806 +#include "miscdevice.h"
14807 +
14808 +
14809 +static DECLARE_MUTEX(videodev_lock);
14810 +
14811 +const char *fimc_version = "$Id: videodev.c,v 1.1.1.1 2004/04/27 03:52:50 swlee Exp $";
14812 +
14813 +#define VIDEO_NAME              "video4linux"
14814 +
14815 +
14816 +#define VIDEO_NUM_DEVICES      2
14817 +static struct video_device *video_device[VIDEO_NUM_DEVICES];
14818 +
14819 +static inline struct video_device * get_vd(int nr)
14820 +{
14821 +       if ( nr == CODEC_MINOR)
14822 +               return video_device[0];
14823 +       else {
14824 +               assert ( nr & PREVIEW_MINOR);
14825 +               return video_device[1];
14826 +       }
14827 +}
14828 +
14829 +static inline void set_vd ( struct video_device * vd, int nr)
14830 +{
14831 +       if ( nr == CODEC_MINOR)
14832 +               video_device[0] = vd;
14833 +       else {
14834 +               assert ( nr & PREVIEW_MINOR);
14835 +               video_device[1] = vd;
14836 +       }
14837 +}
14838 +
14839 +static inline int video_release(struct inode *inode, struct file *f)
14840 +{
14841 +       int minor = MINOR(inode->i_rdev);
14842 +       struct video_device *vfd;
14843 +
14844 +       vfd = get_vd(minor);
14845 +#if 1 /* needed until all drivers are fixed */
14846 +       if (!vfd->release)
14847 +               return 0;
14848 +#endif
14849 +       vfd->release(vfd);
14850 +       return 0;
14851 +}
14852 +
14853 +struct video_device* video_devdata(struct file *file)
14854 +{
14855 +       return video_device[iminor(file->f_dentry->d_inode)];
14856 +}
14857 +
14858 +
14859 +/*
14860 + *     Open a video device.
14861 + */
14862 +static int video_open(struct inode *inode, struct file *file)
14863 +{
14864 +       int minor = MINOR(inode->i_rdev);
14865 +       int err = 0;
14866 +       struct video_device *vfl;
14867 +       struct file_operations const *old_fops;
14868 +
14869 +       down(&videodev_lock);
14870 +
14871 +       vfl = get_vd(minor);
14872 +
14873 +       old_fops = file->f_op;
14874 +       file->f_op = fops_get(vfl->fops);
14875 +       if(file->f_op->open)
14876 +               err = file->f_op->open(inode,file);
14877 +       if (err) {
14878 +               fops_put(file->f_op);
14879 +               file->f_op = fops_get(old_fops);
14880 +       }
14881 +       fops_put(old_fops);
14882 +       up(&videodev_lock);
14883 +       return err;
14884 +}
14885 +
14886 +/*
14887 + * open/release helper functions -- handle exclusive opens
14888 + */
14889 +extern int video_exclusive_open(struct inode *inode, struct file *file)
14890 +{
14891 +       struct  video_device *vfl = get_vd(MINOR(inode->i_rdev));
14892 +       int retval = 0;
14893 +
14894 +       mutex_lock(&vfl->lock);
14895 +       if (vfl->users) {
14896 +               retval = -EBUSY;
14897 +       } else {
14898 +               vfl->users++;
14899 +       }
14900 +       mutex_unlock(&vfl->lock);
14901 +       return retval;
14902 +}
14903 +
14904 +extern int video_exclusive_release(struct inode *inode, struct file *file)
14905 +{
14906 +       struct  video_device *vfl = get_vd(MINOR(inode->i_rdev));
14907 +       vfl->users--;
14908 +       return 0;
14909 +}
14910 +
14911 +int
14912 +video_usercopy(struct inode *inode, struct file *file,
14913 +              unsigned int cmd, unsigned long arg,
14914 +              int (*func)(struct inode *inode, struct file *file,
14915 +                          unsigned int cmd, void *arg))
14916 +{
14917 +       char    sbuf[128];
14918 +       void    *mbuf = NULL;
14919 +       void    *parg = NULL;
14920 +       int     err  = -EINVAL;
14921 +
14922 +       //      cmd = video_fix_command(cmd);
14923 +
14924 +       /*  Copy arguments into temp kernel buffer  */
14925 +       switch (_IOC_DIR(cmd)) {
14926 +       case _IOC_NONE:
14927 +               parg = (void *)arg;
14928 +               break;
14929 +       case _IOC_READ:
14930 +       case _IOC_WRITE:
14931 +       case (_IOC_WRITE | _IOC_READ):
14932 +               if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
14933 +                       parg = sbuf;
14934 +               } else {
14935 +                       /* too big to allocate from stack */
14936 +                       mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL);
14937 +                       if (NULL == mbuf)
14938 +                               return -ENOMEM;
14939 +                       parg = mbuf;
14940 +               }
14941 +
14942 +               err = -EFAULT;
14943 +               if (_IOC_DIR(cmd) & _IOC_WRITE)
14944 +                       if (copy_from_user(parg, (void *)arg, _IOC_SIZE(cmd)))
14945 +                               goto out;
14946 +               break;
14947 +       }
14948 +
14949 +       /* call driver */
14950 +       err = func(inode, file, cmd, parg);
14951 +       if (err == -ENOIOCTLCMD)
14952 +               err = -EINVAL;
14953 +       if (err < 0)
14954 +               goto out;
14955 +
14956 +       /*  Copy results into user buffer  */
14957 +       switch (_IOC_DIR(cmd))
14958 +       {
14959 +       case _IOC_READ:
14960 +       case (_IOC_WRITE | _IOC_READ):
14961 +               if (copy_to_user((void *)arg, parg, _IOC_SIZE(cmd)))
14962 +                       err = -EFAULT;
14963 +               break;
14964 +       }
14965 +
14966 +out:
14967 +       if (mbuf)
14968 +               kfree(mbuf);
14969 +       return err;
14970 +}
14971 +
14972 +
14973 +static struct file_operations video_fops=
14974 +{
14975 +       .owner          = THIS_MODULE,
14976 +       .llseek         = no_llseek,
14977 +       .open           = video_open,
14978 +       .release        = video_release,
14979 +};
14980 +
14981 +static struct miscdevice codec_dev = {
14982 +       minor: CODEC_MINOR,
14983 +       name : "codec",
14984 +       fops : &video_fops
14985 +};
14986 +
14987 +static struct miscdevice preview_dev = {
14988 +       minor: PREVIEW_MINOR,
14989 +       name : "preview",
14990 +       fops : &video_fops
14991 +};
14992 +
14993 +
14994 +/**
14995 + *     video_register_device - register video4linux devices
14996 + *     @vfd:  video device structure we want to register
14997 + *     @type: type of device to register
14998 + *     @nr:   minor number
14999 + *
15000 + *     Zero is returned on success.
15001 + *      type : ignored.
15002 + *      nr :
15003 + *           0 Codec index
15004 + *           1 Preview index
15005 + */
15006 +int video_register_device(struct video_device *vfd, int type, int nr)
15007 +{
15008 +       int ret=0;
15009 +
15010 +       /* pick a minor number */
15011 +       down(&videodev_lock);
15012 +       set_vd (vfd, nr);
15013 +       vfd->minor=nr;
15014 +       up(&videodev_lock);
15015 +
15016 +       switch (vfd->minor) {
15017 +               case CODEC_MINOR:
15018 +                       ret = misc_register(&codec_dev);
15019 +                       if (ret) {
15020 +                               printk(KERN_ERR
15021 +                                               "can't misc_register : codec on minor=%d\n", CODEC_MINOR);
15022 +                               panic(" Give me misc codec \n");
15023 +                       }
15024 +                       break;
15025 +               case PREVIEW_MINOR:
15026 +                       ret = misc_register(&preview_dev);
15027 +                       if (ret) {
15028 +                               printk(KERN_ERR
15029 +                                               "can't misc_register (preview) on minor=%d\n", PREVIEW_MINOR);
15030 +                               panic(" Give me misc codec \n");
15031 +                       }
15032 +                       break;
15033 +       }
15034 +
15035 +#if 0 /* needed until all drivers are fixed */
15036 +       if (!vfd->release)
15037 +               printk(KERN_WARNING "videodev: \"%s\" has no release callback. "
15038 +                               "Please fix your driver for proper sysfs support, see "
15039 +                               "http://lwn.net/Articles/36850/\n", vfd->name);
15040 +#endif
15041 +       return 0;
15042 +}
15043 +
15044 +/**
15045 + *     video_unregister_device - unregister a video4linux device
15046 + *     @vfd: the device to unregister
15047 + *
15048 + *     This unregisters the passed device and deassigns the minor
15049 + *     number. Future open calls will be met with errors.
15050 + */
15051 +
15052 +void video_unregister_device(struct video_device *vfd)
15053 +{
15054 +       down(&videodev_lock);
15055 +
15056 +       if(get_vd(vfd->minor)!=vfd)
15057 +               panic("videodev: bad unregister");
15058 +
15059 +       if (vfd->minor== CODEC_MINOR)
15060 +               misc_deregister(&codec_dev);
15061 +       else
15062 +               misc_deregister(&preview_dev);
15063 +       set_vd (NULL, vfd->minor);
15064 +       up(&videodev_lock);
15065 +}
15066 +
15067 +
15068 +/*
15069 + *     Initialise video for linux
15070 + */
15071 +
15072 +static int __init videodev_init(void)
15073 +{
15074 +//     printk(KERN_INFO "FIMC2.0 Built:"__DATE__" "__TIME__"\n%s\n",fimc_version);
15075 +       return 0;
15076 +}
15077 +
15078 +static void __exit videodev_exit(void)
15079 +{
15080 +}
15081 +
15082 +module_init(videodev_init)
15083 +module_exit(videodev_exit)
15084 +
15085 +EXPORT_SYMBOL(video_register_device);
15086 +EXPORT_SYMBOL(fimc_version);
15087 +EXPORT_SYMBOL(video_unregister_device);
15088 +EXPORT_SYMBOL(video_usercopy);
15089 +EXPORT_SYMBOL(video_exclusive_open);
15090 +EXPORT_SYMBOL(video_exclusive_release);
15091 +
15092 +
15093 +MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
15094 +MODULE_DESCRIPTION("VideoDev For FIMC2.0 MISC Drivers");
15095 +MODULE_LICENSE("GPL");
15096 +
15097 +
15098 +/*
15099 + * Local variables:
15100 + * c-basic-offset: 8
15101 + * End:
15102 + */
15103 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/videodev.h
15104 ===================================================================
15105 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
15106 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/videodev.h        2009-01-02 00:01:56.000000000 +0100
15107 @@ -0,0 +1,108 @@
15108 +//#ifndef __LINUX_S3C_VIDEODEV_H
15109 +//#define __LINUX_S3C_VIDEODEV_H
15110 +
15111 +#include <linux/types.h>
15112 +#include <linux/version.h>
15113 +#include <media/v4l2-dev.h>
15114 +
15115 +#if 0
15116 +struct video_device
15117 +{
15118 +       /* device info */
15119 +       //      struct device *dev;
15120 +       char name[32];
15121 +       int type;       /* v4l1 */
15122 +       int type2;      /* v4l2 */
15123 +       int hardware;
15124 +       int minor;
15125 +
15126 +       /* device ops + callbacks */
15127 +       struct file_operations *fops;
15128 +       void (*release)(struct video_device *vfd);
15129 +
15130 +
15131 +#if 1 /* to be removed in 2.7.x */
15132 +       /* obsolete -- fops->owner is used instead */
15133 +       struct module *owner;
15134 +       /* dev->driver_data will be used instead some day.
15135 +        * Use the video_{get|set}_drvdata() helper functions,
15136 +        * so the switch over will be transparent for you.
15137 +        * Or use {pci|usb}_{get|set}_drvdata() directly. */
15138 +       void *priv;
15139 +#endif
15140 +
15141 +       /* for videodev.c intenal usage -- please don't touch */
15142 +       int users;                     /* video_exclusive_{open|close} ... */
15143 +       struct semaphore lock;         /* ... helper function uses these   */
15144 +       char devfs_name[64];           /* devfs */
15145 +       //      struct class_device class_dev; /* sysfs */
15146 +};
15147 +
15148 +#define VIDEO_MAJOR    81
15149 +
15150 +#define VFL_TYPE_GRABBER       0
15151 +
15152 +
15153 +extern int video_register_device(struct video_device *, int type, int nr);
15154 +extern void video_unregister_device(struct video_device *);
15155 +extern struct video_device* video_devdata(struct file*);
15156 +
15157 +
15158 +
15159 +struct video_picture
15160 +{
15161 +        __u16   brightness;
15162 +        __u16   hue;
15163 +        __u16   colour;
15164 +        __u16   contrast;
15165 +        __u16   whiteness;      /* Black and white only */
15166 +        __u16   depth;          /* Capture depth */
15167 +        __u16   palette;        /* Palette in use */
15168 +#define VIDEO_PALETTE_GREY      1       /* Linear greyscale */
15169 +#define VIDEO_PALETTE_HI240     2       /* High 240 cube (BT848) */
15170 +#define VIDEO_PALETTE_RGB565    3       /* 565 16 bit RGB */
15171 +#define VIDEO_PALETTE_RGB24     4       /* 24bit RGB */
15172 +#define VIDEO_PALETTE_RGB32     5       /* 32bit RGB */
15173 +#define VIDEO_PALETTE_RGB555    6       /* 555 15bit RGB */
15174 +#define VIDEO_PALETTE_YUV422    7       /* YUV422 capture */
15175 +#define VIDEO_PALETTE_YUYV      8
15176 +#define VIDEO_PALETTE_UYVY      9       /* The great thing about standards is ... */
15177 +#define VIDEO_PALETTE_YUV420    10
15178 +#define VIDEO_PALETTE_YUV411    11      /* YUV411 capture */
15179 +#define VIDEO_PALETTE_RAW       12      /* RAW capture (BT848) */
15180 +#define VIDEO_PALETTE_YUV422P   13      /* YUV 4:2:2 Planar */
15181 +#define VIDEO_PALETTE_YUV411P   14      /* YUV 4:1:1 Planar */
15182 +#define VIDEO_PALETTE_YUV420P   15      /* YUV 4:2:0 Planar */
15183 +#define VIDEO_PALETTE_YUV410P   16      /* YUV 4:1:0 Planar */
15184 +#define VIDEO_PALETTE_PLANAR    13      /* start of planar entries */
15185 +#define VIDEO_PALETTE_COMPONENT 7       /* start of component entries */
15186 +};
15187 +
15188 +extern int video_exclusive_open(struct inode *inode, struct file *file);
15189 +extern int video_exclusive_release(struct inode *inode, struct file *file);
15190 +extern int video_usercopy(struct inode *inode, struct file *file,
15191 +                          unsigned int cmd, unsigned long arg,
15192 +                          int (*func)(struct inode *inode, struct file *file,
15193 +                                      unsigned int cmd, void *arg));
15194 +
15195 +
15196 +
15197 +
15198 +#define VID_TYPE_CAPTURE        1       /* Can capture */
15199 +#define VID_TYPE_CLIPPING       32      /* Can clip */
15200 +#define VID_TYPE_FRAMERAM       64      /* Uses the frame buffer memory */
15201 +#define VID_TYPE_SCALES         128     /* Scalable */
15202 +#define VID_TYPE_SUBCAPTURE     512     /* Can capture subareas of the image */
15203 +
15204 +
15205 +
15206 +#endif
15207 +//#endif
15208 +
15209 +#define VID_HARDWARE_SAMSUNG_FIMC  255
15210 +
15211 +/*
15212 + * Local variables:
15213 + * c-basic-offset: 8
15214 + * End:
15215 + */
15216 Index: linux-2.6.28/arch/arm/mach-s3c2440/camera/video-driver.c
15217 ===================================================================
15218 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
15219 +++ linux-2.6.28/arch/arm/mach-s3c2440/camera/video-driver.c    2009-01-02 00:01:56.000000000 +0100
15220 @@ -0,0 +1,624 @@
15221 +/*
15222 +    Copyright (C) 2004 Samsung Electronics
15223 +                     SW.LEE <hitchcar@sec.samsung.com>
15224 +    This program is free software; you can redistribute it and/or modify
15225 +    it under the terms of the GNU General Public License as published by
15226 +    the Free Software Foundation; either version 2 of the License, or
15227 +    (at your option) any later version.
15228 +*/
15229 +
15230 +#include <linux/version.h>
15231 +#include <linux/module.h>
15232 +#include <linux/delay.h>
15233 +#include <linux/errno.h>
15234 +#include <linux/fs.h>
15235 +#include <linux/kernel.h>
15236 +#include <linux/major.h>
15237 +#include <linux/slab.h>
15238 +#include <linux/poll.h>
15239 +#include <linux/signal.h>
15240 +#include <linux/ioport.h>
15241 +#include <linux/sched.h>
15242 +#include <linux/types.h>
15243 +#include <linux/interrupt.h>
15244 +#include <linux/kmod.h>
15245 +#include <linux/vmalloc.h>
15246 +#include <linux/init.h>
15247 +#include <asm/io.h>
15248 +#include <asm/page.h>
15249 +#include <asm/irq.h>
15250 +#include <asm/semaphore.h>
15251 +#include <linux/miscdevice.h>
15252 +#include <asm/arch/irqs.h>
15253 +
15254 +//#define SW_DEBUG
15255 +#define CONFIG_VIDEO_V4L1_COMPAT
15256 +#include <linux/videodev.h>
15257 +#include "camif.h"
15258 +#include "miscdevice.h"
15259 +#include "cam_reg.h"
15260 +#include "sensor.h"
15261 +#include "userapp.h"
15262 +
15263 +#ifdef Z_API
15264 +#include "qt.h"
15265 +#endif
15266 +
15267 +/* Codec and Preview */
15268 +#define CAMIF_NUM  2
15269 +static camif_cfg_t  fimc[CAMIF_NUM];
15270 +u32 *camregs;
15271 +
15272 +static const char *driver_version =
15273 +       "$Id: video-driver.c,v 1.9 2004/06/02 03:10:36 swlee Exp $";
15274 +extern const char *fimc_version;
15275 +extern const char *fsm_version;
15276 +
15277 +extern void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other);
15278 +
15279 +camif_cfg_t * get_camif(int nr)
15280 +{
15281 +       camif_cfg_t *ret = NULL;
15282 +       switch(nr) {
15283 +       case CODEC_MINOR:
15284 +               ret = &fimc[0];
15285 +               break;
15286 +       case PREVIEW_MINOR:
15287 +               ret = &fimc[1];
15288 +               break;
15289 +       default:
15290 +               panic("Unknow Minor Number \n");
15291 +       }
15292 +       return ret;
15293 +}
15294 +
15295 +
15296 +static int camif_codec_start(camif_cfg_t *cfg)
15297 +{
15298 +       int  ret = 0;
15299 +       ret =camif_check_preview(cfg);
15300 +       switch(ret) {
15301 +       case 0:                 /* Play alone */
15302 +               DPRINTK("Start Alone \n");
15303 +               camif_4fsm_start(cfg);
15304 +               cfg->gc->status |= C_WORKING;
15305 +               break;
15306 +       case -ERESTARTSYS:       /* Busy , retry */
15307 +               //DPRINTK("Error \n");
15308 +               printk("Error \n");
15309 +               break;
15310 +       case 1:
15311 +               DPRINTK("need callback \n");
15312 +               ret = camif_callback_start(cfg);
15313 +               if(ret < 0 ) {
15314 +                       printk(KERN_INFO "Busy RESTART \n");
15315 +                       return ret; /* Busy, retry */
15316 +               }
15317 +               break;
15318 +       }
15319 +       return ret;
15320 +}
15321 +
15322 +
15323 +ssize_t camif_write (struct file *f, const char *b, size_t c,loff_t *offset)
15324 +{
15325 +       camif_cfg_t *cfg;
15326 +
15327 +       c = 0;                  /* return value */
15328 +       DPRINTK("\n");
15329 +       cfg = get_camif(MINOR(f->f_dentry->d_inode->i_rdev));
15330 +       switch (*b) {
15331 +               case 'O':
15332 +                       if (cfg->dma_type & CAMIF_PREVIEW) {
15333 +                               if (cfg->gc->status & C_WORKING) {
15334 +                                       camif_start_c_with_p(cfg,get_camif(CODEC_MINOR));
15335 +                               }
15336 +                               else  {
15337 +                                       camif_4fsm_start(cfg);
15338 +                               }
15339 +                       }
15340 +                       else{
15341 +                               c = camif_codec_start(cfg);
15342 +                               if(c < 0) c = 1; /* Error and neet to retry */
15343 +                       }
15344 +
15345 +                       break;
15346 +               case 'X':
15347 +                       camif_p_stop(cfg);
15348 +                       break;
15349 +               default:
15350 +                       panic("CAMERA:camif_write: Unexpected Param\n");
15351 +       }
15352 +       DPRINTK("end\n");
15353 +
15354 +       return c;
15355 +}
15356 +
15357 +
15358 +ssize_t camif_p_read(struct file *file, char *buf, size_t count, loff_t *pos)
15359 +{
15360 +       camif_cfg_t *cfg = NULL;
15361 +       size_t end;
15362 +
15363 +       cfg = get_camif(MINOR(file->f_dentry->d_inode->i_rdev));
15364 +       cfg->status = CAMIF_STARTED;
15365 +
15366 +       if (wait_event_interruptible(cfg->waitq,cfg->status == CAMIF_INT_HAPPEN))
15367 +               return -ERESTARTSYS;
15368 +
15369 +       cfg->status = CAMIF_STOPPED;
15370 +       end = min_t(size_t, cfg->pp_totalsize /cfg->pp_num, count);
15371 +       if (copy_to_user(buf, camif_g_frame(cfg), end))
15372 +               return -EFAULT;
15373 +
15374 +       return end;
15375 +}
15376 +
15377 +
15378 +static ssize_t
15379 +camif_c_read(struct file *file, char *buf, size_t count, loff_t *pos)
15380 +{
15381 +       camif_cfg_t *cfg = NULL;
15382 +       size_t end;
15383 +
15384 +       /* cfg = file->private_data; */
15385 +       cfg = get_camif(MINOR(file->f_dentry->d_inode->i_rdev));
15386 +#if 0
15387 +       if(file->f_flags & O_NONBLOCK) {
15388 +               printk(KERN_ERR"Don't Support NON_BLOCK \n");
15389 +       }
15390 +#endif
15391 +
15392 +      /* Change the below wait_event_interruptible func */
15393 +       if (wait_event_interruptible(cfg->waitq,cfg->status == CAMIF_INT_HAPPEN))
15394 +              return -ERESTARTSYS;
15395 +       cfg->status = CAMIF_STOPPED;
15396 +       end = min_t(size_t, cfg->pp_totalsize /cfg->pp_num, count);
15397 +       if (copy_to_user(buf, camif_g_frame(cfg), end))
15398 +              return -EFAULT;
15399 +       return end;
15400 +}
15401 +
15402 +
15403 +static irqreturn_t camif_c_irq(int irq, void *dev_id)
15404 +{
15405 +        camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
15406 +
15407 +       DPRINTK("\n");
15408 +       camif_g_fifo_status(cfg);
15409 +       camif_g_frame_num(cfg);
15410 +       if(camif_enter_c_4fsm(cfg) != INSTANT_SKIP)
15411 +               wake_up_interruptible(&cfg->waitq);
15412 +
15413 +       return IRQ_HANDLED;
15414 +}
15415 +
15416 +static irqreturn_t camif_p_irq(int irq, void *dev_id)
15417 +{
15418 +        camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
15419 +
15420 +       DPRINTK("\n");
15421 +       camif_g_fifo_status(cfg);
15422 +       camif_g_frame_num(cfg);
15423 +       if(camif_enter_p_4fsm(cfg) != INSTANT_SKIP)
15424 +               wake_up_interruptible(&cfg->waitq);
15425 +#if 0
15426 +       if( (cfg->perf.frames % 5) == 0)
15427 +               DPRINTK("5\n");
15428 +#endif
15429 +
15430 +       return IRQ_HANDLED;
15431 +}
15432 +
15433 +static void camif_release_irq(camif_cfg_t *cfg)
15434 +{
15435 +       disable_irq(cfg->irq);
15436 +       free_irq(cfg->irq, cfg);
15437 +}
15438 +
15439 +static int camif_irq_request(camif_cfg_t *cfg)
15440 +{
15441 +       int ret = 0;
15442 +
15443 +       if (cfg->dma_type & CAMIF_CODEC) {
15444 +               if ((ret = request_irq(cfg->irq, camif_c_irq,
15445 +                              0, cfg->shortname, cfg))) {
15446 +                       printk("request_irq(CAM_C) failed.\n");
15447 +               }
15448 +       }
15449 +       if (cfg->dma_type & CAMIF_PREVIEW) {
15450 +               if ((ret = request_irq(cfg->irq, camif_p_irq,
15451 +                              0, cfg->shortname, cfg))) {
15452 +                       printk("request_irq(CAM_P) failed.\n");
15453 +               }
15454 +       }
15455 +       return 0;
15456 +}
15457 +
15458 +static void camif_init_sensor(camif_cfg_t *cfg)
15459 +{
15460 +       camif_gc_t *gc =  cfg->gc;
15461 +       if (!gc->sensor)
15462 +               panic("CAMERA:I2C Client(Img Sensor)Not registered\n");
15463 +       if(!gc->init_sensor) {
15464 +               camif_reset(gc->reset_type, gc->reset_udelay);
15465 +               gc->sensor->driver->command(gc->sensor,SENSOR_INIT,NULL);
15466 +               gc->init_sensor = 1; /*sensor init done */
15467 +       }
15468 +       gc->sensor->driver->command(gc->sensor, USER_ADD, NULL);
15469 +}
15470 +
15471 +static int camif_open(struct inode *inode, struct file *file)
15472 +{
15473 +       int err;
15474 +       camif_cfg_t * cfg = get_camif(MINOR(inode->i_rdev));
15475 +
15476 +       if(cfg->dma_type & CAMIF_PREVIEW) {
15477 +               if(down_interruptible(&cfg->gc->lock))
15478 +                       return -ERESTARTSYS;
15479 +               if (cfg->dma_type & CAMIF_PREVIEW) {
15480 +                       cfg->gc->status &= ~PNOTWORKING;
15481 +               }
15482 +               up(&cfg->gc->lock);
15483 +       }
15484 +       err = video_exclusive_open(inode,file);
15485 +       cfg->gc->user++;
15486 +       cfg->status = CAMIF_STOPPED;
15487 +       if (err < 0)  return err;
15488 +       if (file->f_flags & O_NONCAP ) {
15489 +               printk("Don't Support Non-capturing open \n");
15490 +               return 0;
15491 +       }
15492 +       file->private_data = cfg;
15493 +       camif_irq_request(cfg);
15494 +       camif_init_sensor(cfg);
15495 +       return 0;
15496 +}
15497 +
15498 +#if 0
15499 +static void print_pregs(void)
15500 +{
15501 +       printk(" CISRCFMT 0x%08X  \n", CISRCFMT);
15502 +       printk(" CIWDOFST 0x%08X  \n", CIWDOFST);
15503 +       printk(" CIGCTRL  0x%08X  \n", CIGCTRL);
15504 +       printk(" CIPRTRGFMT 0x%08X  \n", CIPRTRGFMT);
15505 +       printk(" CIPRCTRL 0x%08X  \n", CIPRCTRL);
15506 +       printk(" CIPRSCPRERATIO 0x%08X  \n", CIPRSCPRERATIO);
15507 +       printk(" CIPRSCPREDST 0x%08X  \n", CIPRSCPREDST);
15508 +       printk(" CIPRSCCTRL 0x%08X  \n", CIPRSCCTRL);
15509 +       printk(" CIPRTAREA 0x%08X  \n", CIPRTAREA);
15510 +       printk(" CIPRSTATUS 0x%08X  \n", CIPRSTATUS);
15511 +       printk(" CIIMGCPT 0x%08X  \n", CIIMGCPT);
15512 +}
15513 +
15514 +static void print_cregs(void)
15515 +{
15516 +       printk(" CISRCFMT 0x%08X  \n", CISRCFMT);
15517 +       printk(" CIWDOFST 0x%08X  \n", CIWDOFST);
15518 +       printk(" CIGCTRL  0x%08X  \n", CIGCTRL);
15519 +       printk(" CICOCTRL 0x%8X   \n", CICOCTRL);
15520 +       printk(" CICOSCPRERATIO 0x%08X  \n", CICOSCPRERATIO);
15521 +       printk(" CICOSCPREDST 0x%08X  \n", CICOSCPREDST);
15522 +       printk(" CICOSCCTRL 0x%08X  \n", CICOSCCTRL);
15523 +       printk(" CICOTAREA 0x%08X  \n", CICOTAREA);
15524 +       printk(" CICOSTATUS 0x%8X \n", CICOSTATUS);
15525 +       printk(" CIIMGCPT 0x%08X  \n", CIIMGCPT);
15526 +}
15527 +#endif
15528 +
15529 +
15530 +static int camif_release(struct inode *inode, struct file *file)
15531 +{
15532 +       camif_cfg_t * cfg = get_camif(MINOR(inode->i_rdev));
15533 +
15534 +       //DPRINTK(" cfg->status 0x%0X cfg->gc->status 0x%0X \n", cfg->status,cfg->gc->status );
15535 +       if (cfg->dma_type & CAMIF_PREVIEW) {
15536 +               if(down_interruptible(&cfg->gc->lock))
15537 +                       return -ERESTARTSYS;
15538 +               cfg->gc->status &= ~PWANT2START;
15539 +               cfg->gc->status |= PNOTWORKING;
15540 +               up(&cfg->gc->lock);
15541 +       }
15542 +       else {
15543 +               cfg->gc->status &= ~CWANT2START; /* No need semaphore */
15544 +       }
15545 +       camif_dynamic_close(cfg);
15546 +       camif_release_irq(cfg);
15547 +       video_exclusive_release(inode,file);
15548 +       camif_p_stop(cfg);
15549 +       cfg->gc->sensor->driver->command(cfg->gc->sensor, USER_EXIT, NULL);
15550 +       cfg->gc->user--;
15551 +       cfg->status = CAMIF_STOPPED;
15552 +       return 0;
15553 +}
15554 +
15555 +static void fimc_config(camif_cfg_t *cfg,u32 x, u32 y, int bpp)
15556 +{
15557 +       cfg->target_x = x;
15558 +       cfg->target_y = y;
15559 +
15560 +       switch (bpp) {
15561 +       case 16:
15562 +               cfg->fmt = CAMIF_RGB16;
15563 +               break;
15564 +       case 24:
15565 +               cfg->fmt = CAMIF_RGB24;
15566 +               break;
15567 +       case 420:
15568 +               cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
15569 +               break;
15570 +       case 422:
15571 +               cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR422;
15572 +               break;
15573 +       default:
15574 +               panic("Wrong BPP \n");
15575 +       }
15576 +}
15577 +
15578 +
15579 +static int
15580 +camif_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
15581 +{
15582 +       int ret = 0;
15583 +       camif_cfg_t *cfg  = file->private_data;
15584 +       camif_param_t par;
15585 +
15586 +       switch (cmd) {
15587 +               case CMD_CAMERA_INIT:
15588 +                       if (copy_from_user(&par,(camif_param_t *)arg,
15589 +                                               sizeof(camif_param_t)))
15590 +                               return -EFAULT;
15591 +                       fimc_config(cfg,par.dst_x, par.dst_y, par.bpp);
15592 +                       if (camif_dynamic_open(cfg)) {
15593 +                               printk(" Eror Happens \n");
15594 +                               ret = -1;
15595 +                       }
15596 +
15597 +                       switch (par.flip) {
15598 +                       case 3 :
15599 +                               cfg->flip = CAMIF_FLIP_MIRROR;
15600 +                               break;
15601 +                       case 1 :
15602 +                               cfg->flip = CAMIF_FLIP_X;
15603 +                               break;
15604 +                       case 2 :
15605 +                               cfg->flip = CAMIF_FLIP_Y;
15606 +                               break;
15607 +                       case 0 :
15608 +                       default:
15609 +                               cfg->flip = CAMIF_FLIP;
15610 +                       }
15611 +                       break;
15612 +       /* Todo
15613 +               case CMD_SENSOR_BRIGHTNESS:
15614 +                       cfg->gc->sensor->driver->command(cfg->gc->sensor, SENSOR_BRIGHTNESS, NULL);
15615 +                       break;
15616 +       */
15617 +               default:
15618 +                       ret = -EINVAL;
15619 +                       break;
15620 +       }
15621 +
15622 +       return ret;
15623 +}
15624 +
15625 +
15626 +#if 0
15627 +static int camif_ioctl(struct inode *inode, struct file *file,
15628 +                     unsigned int cmd, unsigned long arg)
15629 +{
15630 +//     camif_cfg_t *cfg  = file->private_data;
15631 +
15632 +
15633 +       switch (cmd) {
15634 +/*     case Some_other_action */
15635 +       default:
15636 +               return video_usercopy(inode, file, cmd, arg, camif_do_ioctl);
15637 +       }
15638 +}
15639 +#endif
15640 +
15641 +static struct file_operations camif_c_fops =
15642 +{
15643 +       .owner    = THIS_MODULE,
15644 +       .open     = camif_open,
15645 +       .release  = camif_release,
15646 +       .ioctl    = camif_ioctl,
15647 +       .read     = camif_c_read,
15648 +       .write    = camif_write,
15649 +};
15650 +
15651 +static struct file_operations camif_p_fops =
15652 +{
15653 +       .owner    = THIS_MODULE,
15654 +       .open     = camif_open,
15655 +       .release  = camif_release,
15656 +       .ioctl    = camif_ioctl,
15657 +#ifdef Z_API
15658 +       .read     = z_read,
15659 +       .write    = z_write,
15660 +#else
15661 +       .read     = camif_p_read,
15662 +       .write    = camif_write,
15663 +#endif
15664 +};
15665 +
15666 +static struct video_device codec_template =
15667 +{
15668 +       .name     = "CODEC_IF",
15669 +       .type     = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
15670 +/*     .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
15671 +       .fops     = &camif_c_fops,
15672 +//     .release  = camif_release
15673 +       .minor    = -1,
15674 +};
15675 +
15676 +static struct video_device preview_template =
15677 +{
15678 +       .name     = "PREVIEW_IF",
15679 +       .type     = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
15680 +/*     .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
15681 +       .fops     = &camif_p_fops,
15682 +       .minor    = -1,
15683 +};
15684 +
15685 +static int preview_init(camif_cfg_t *cfg)
15686 +{
15687 +       char name[16]="CAM_PREVIEW";
15688 +
15689 +       memset(cfg, 0, sizeof(camif_cfg_t));
15690 +       cfg->target_x = 640;
15691 +       cfg->target_y = 480;
15692 +       cfg->pp_num   = 4;
15693 +       cfg->dma_type = CAMIF_PREVIEW;
15694 +       cfg->fmt      = CAMIF_RGB16;
15695 +       cfg->flip     = CAMIF_FLIP_Y;
15696 +       cfg->v        = &preview_template;
15697 +       mutex_init(&cfg->v->lock);
15698 +       cfg->irq       = IRQ_S3C2440_CAM_P;
15699 +
15700 +       strcpy(cfg->shortname,name);
15701 +        init_waitqueue_head(&cfg->waitq);
15702 +       cfg->status = CAMIF_STOPPED;
15703 +       return cfg->status;
15704 +}
15705 +
15706 +static int codec_init(camif_cfg_t *cfg)
15707 +{
15708 +       char name[16]="CAM_CODEC";
15709 +
15710 +       memset(cfg, 0, sizeof(camif_cfg_t));
15711 +       cfg->target_x = 176;
15712 +       cfg->target_y = 144;
15713 +       cfg->pp_num   = 4;
15714 +       cfg->dma_type = CAMIF_CODEC;
15715 +       cfg->fmt      = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
15716 +       cfg->flip     = CAMIF_FLIP_X;
15717 +       cfg->v         = &codec_template;
15718 +       mutex_init(&cfg->v->lock);
15719 +       cfg->irq       = IRQ_S3C2440_CAM_C;
15720 +       strcpy(cfg->shortname,name);
15721 +       init_waitqueue_head(&cfg->waitq);
15722 +       cfg->status = CAMIF_STOPPED;
15723 +       return cfg->status;
15724 +}
15725 +
15726 +static void camif_init(void)
15727 +{
15728 +       camif_setup_sensor();
15729 +}
15730 +
15731 +
15732 +
15733 +static void print_version(void)
15734 +{
15735 +       printk(KERN_INFO"FIMC built:"__DATE__ " "__TIME__"\n%s\n%s\n%s\n",
15736 +                                       fimc_version, driver_version,fsm_version);
15737 +}
15738 +
15739 +
15740 +static int camif_m_in(void)
15741 +{
15742 +       int ret = -EINVAL;
15743 +       camif_cfg_t * cfg;
15744 +
15745 +       printk(KERN_INFO"Starting S3C2440 Camera Driver\n");
15746 +
15747 +       camregs = ioremap(CAM_BASE_ADD, 0x100);
15748 +       if (!camregs) {
15749 +               printk(KERN_ERR"Unable to map camera regs\n");
15750 +               ret = -ENOMEM;
15751 +               goto bail1;
15752 +       }
15753 +
15754 +       camif_init();
15755 +       cfg = get_camif(CODEC_MINOR);
15756 +       codec_init(cfg);
15757 +
15758 +       ret = video_register_device(cfg->v,0,CODEC_MINOR);
15759 +       if (ret) {
15760 +                       printk(KERN_ERR"Couldn't register codec driver.\n");
15761 +                       goto bail2;
15762 +       }
15763 +       cfg = get_camif(PREVIEW_MINOR);
15764 +       preview_init(cfg);
15765 +       ret = video_register_device(cfg->v,0,PREVIEW_MINOR);
15766 +       if (ret) {
15767 +                       printk(KERN_ERR"Couldn't register preview driver.\n");
15768 +                       goto bail3; /* hm seems it us unregistered the once */
15769 +       }
15770 +
15771 +       print_version();
15772 +       return 0;
15773 +
15774 +bail3:
15775 +       video_unregister_device(cfg->v);
15776 +bail2:
15777 +       iounmap(camregs);
15778 +       camregs = NULL;
15779 +bail1:
15780 +       return ret;
15781 +}
15782 +
15783 +static void unconfig_device(camif_cfg_t *cfg)
15784 +{
15785 +       video_unregister_device(cfg->v);
15786 +       camif_hw_close(cfg);
15787 +       iounmap(camregs);
15788 +       //memset(cfg, 0, sizeof(camif_cfg_t));
15789 +       camregs = NULL;
15790 +}
15791 +
15792 +static void camif_m_out(void)  /* module out */
15793 +{
15794 +       camif_cfg_t *cfg;
15795 +
15796 +       cfg = get_camif(CODEC_MINOR);
15797 +       unconfig_device(cfg);
15798 +       cfg = get_camif(PREVIEW_MINOR);
15799 +       unconfig_device(cfg);
15800 +
15801 +       return;
15802 +}
15803 +
15804 +void camif_register_decoder(struct i2c_client *ptr)
15805 +{
15806 +       camif_cfg_t *cfg;
15807 +       void * data = i2c_get_clientdata(ptr);
15808 +
15809 +       cfg =get_camif(CODEC_MINOR);
15810 +       cfg->gc = (camif_gc_t *)(data);
15811 +
15812 +       cfg =get_camif(PREVIEW_MINOR);
15813 +       cfg->gc = (camif_gc_t *)(data);
15814 +
15815 +       sema_init(&cfg->gc->lock, 1); /* global lock for both Codec and Preview */
15816 +       cfg->gc->status |= PNOTWORKING; /* Default Value */
15817 +       camif_hw_open(cfg->gc);
15818 +}
15819 +
15820 +void camif_unregister_decoder(struct i2c_client *ptr)
15821 +{
15822 +       camif_gc_t *gc;
15823 +       void * data = i2c_get_clientdata(ptr);
15824 +
15825 +       gc = (camif_gc_t *)(data);
15826 +       gc->init_sensor = 0; /* need to modify */
15827 +}
15828 +
15829 +module_init(camif_m_in);
15830 +module_exit(camif_m_out);
15831 +
15832 +EXPORT_SYMBOL(camif_register_decoder);
15833 +EXPORT_SYMBOL(camif_unregister_decoder);
15834 +
15835 +MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
15836 +MODULE_DESCRIPTION("Video-Driver For Fimc2.0 MISC Drivers");
15837 +MODULE_LICENSE("GPL");
15838 +
15839 +
15840 +/*
15841 + * Local variables:
15842 + * c-basic-offset: 8
15843 + * End:
15844 + */
15845 Index: linux-2.6.28/arch/arm/mach-s3c2440/dma.c
15846 ===================================================================
15847 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/dma.c       2008-12-25 00:26:37.000000000 +0100
15848 +++ linux-2.6.28/arch/arm/mach-s3c2440/dma.c    2009-01-02 00:01:56.000000000 +0100
15849 @@ -25,12 +25,12 @@
15850
15851  #include <plat/regs-serial.h>
15852  #include <mach/regs-gpio.h>
15853 -#include <asm/plat-s3c/regs-ac97.h>
15854 +#include <plat/regs-ac97.h>
15855  #include <mach/regs-mem.h>
15856  #include <mach/regs-lcd.h>
15857  #include <mach/regs-sdi.h>
15858  #include <asm/plat-s3c24xx/regs-iis.h>
15859 -#include <asm/plat-s3c24xx/regs-spi.h>
15860 +#include <plat/regs-spi.h>
15861
15862  static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
15863         [DMACH_XD0] = {
15864 Index: linux-2.6.28/arch/arm/mach-s3c2440/fiq_c_isr.c
15865 ===================================================================
15866 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
15867 +++ linux-2.6.28/arch/arm/mach-s3c2440/fiq_c_isr.c      2009-01-02 00:01:56.000000000 +0100
15868 @@ -0,0 +1,321 @@
15869 +/*
15870 + * Copyright 2007  Andy Green <andy@warmcat.com>
15871 + * S3C modfifications
15872 + * Copyright 2008 Andy Green <andy@openmoko.com>
15873 + */
15874 +
15875 +#include <linux/module.h>
15876 +#include <linux/kernel.h>
15877 +#include <mach/hardware.h>
15878 +#include <asm/fiq.h>
15879 +#include "fiq_c_isr.h"
15880 +#include <linux/sysfs.h>
15881 +#include <linux/device.h>
15882 +#include <linux/delay.h>
15883 +#include <linux/platform_device.h>
15884 +
15885 +#include <asm/io.h>
15886 +
15887 +#include <plat/cpu.h>
15888 +#include <plat/irq.h>
15889 +
15890 +#include <mach/pwm.h>
15891 +#include <plat/regs-timer.h>
15892 +
15893 +/*
15894 + * Major Caveats for using FIQ
15895 + * ---------------------------
15896 + *
15897 + * 1) it CANNOT touch any vmalloc()'d memory, only memory
15898 + *    that was kmalloc()'d.  Static allocations in the monolithic kernel
15899 + *    are kmalloc()'d so they are okay.  You can touch memory-mapped IO, but
15900 + *    the pointer for it has to have been stored in kmalloc'd memory.  The
15901 + *    reason for this is simple: every now and then Linux turns off interrupts
15902 + *    and reorders the paging tables.  If a FIQ happens during this time, the
15903 + *    virtual memory space can be partly or entirely disordered or missing.
15904 + *
15905 + * 2) Because vmalloc() is used when a module is inserted, THIS FIQ
15906 + *    ISR HAS TO BE IN THE MONOLITHIC KERNEL, not a module.  But the way
15907 + *    it is set up, you can all to enable and disable it from your module
15908 + *    and intercommunicate with it through struct fiq_ipc
15909 + *    fiq_ipc which you can define in
15910 + *    asm/archfiq_ipc_type.h.  The reason is the same as above, a
15911 + *    FIQ could happen while even the ISR is not present in virtual memory
15912 + *    space due to pagetables being changed at the time.
15913 + *
15914 + * 3) You can't call any Linux API code except simple macros
15915 + *    - understand that FIQ can come in at any time, no matter what
15916 + *      state of undress the kernel may privately be in, thinking it
15917 + *      locked the door by turning off interrupts... FIQ is an
15918 + *      unstoppable monster force (which is its value)
15919 + *    - they are not vmalloc()'d memory safe
15920 + *    - they might do crazy stuff like sleep: FIQ pisses fire and
15921 + *      is not interested in 'sleep' that the weak seem to need
15922 + *    - calling APIs from FIQ can re-enter un-renterable things
15923 + *    - summary: you cannot interoperate with linux APIs directly in the FIQ ISR
15924 + *
15925 + * If you follow these rules, it is fantastic, an extremely powerful, solid,
15926 + * genuine hard realtime feature.
15927 + *
15928 + */
15929 +
15930 +/* more than enough to cover our jump instruction to the isr */
15931 +#define SIZEOF_FIQ_JUMP 4
15932 +
15933 +#define FIQ_VECTOR 0xffff001c
15934 +
15935 +/* we put the stack at the area after the FIQ vector */
15936 +#define FIQ_STACK_SIZE 256
15937 +
15938 +/* only one FIQ ISR possible, okay to do these here */
15939 +u32 _fiq_ack_mask; /* used by isr exit define */
15940 +unsigned long _fiq_count_fiqs; /* used by isr exit define */
15941 +static int _fiq_irq; /* private ; irq index we were started with, or 0 */
15942 +struct s3c2410_pwm pwm_timer_fiq;
15943 +int _fiq_timer_index;
15944 +u16 _fiq_timer_divisor;
15945 +u8 fiq_ready;
15946 +
15947 +/* this function must live in the monolithic kernel somewhere!  A module is
15948 + * NOT good enough!
15949 + */
15950 +extern void __attribute__ ((naked)) s3c2440_fiq_isr(void);
15951 +
15952 +static void fiq_set_vector_and_regs(void);
15953 +
15954 +
15955 +/* this is copied into the hard FIQ vector during init */
15956 +
15957 +static void __attribute__ ((naked)) s3c2440_FIQ_Branch(void)
15958 +{
15959 +       asm __volatile__ (
15960 +               "mov pc, r8 ; "
15961 +       );
15962 +}
15963 +
15964 +/* sysfs */
15965 +
15966 +static ssize_t show_count(struct device *dev, struct device_attribute *attr,
15967 +                        char *buf)
15968 +{
15969 +       return sprintf(buf, "%ld\n", _fiq_count_fiqs);
15970 +}
15971 +
15972 +static DEVICE_ATTR(count, 0444, show_count, NULL);
15973 +
15974 +static struct attribute *s3c2440_fiq_sysfs_entries[] = {
15975 +       &dev_attr_count.attr,
15976 +       NULL
15977 +};
15978 +
15979 +static struct attribute_group s3c2440_fiq_attr_group = {
15980 +       .name   = "fiq",
15981 +       .attrs  = s3c2440_fiq_sysfs_entries,
15982 +};
15983 +
15984 +/*
15985 + * call this from your kernel module to set up the FIQ ISR to service FIQs,
15986 + * You need to have configured your FIQ input pin before anything will happen
15987 + *
15988 + * call it with, eg, IRQ_TIMER3 from asm-arm/arch-s3c2410/irqs.h
15989 + *
15990 + * you still need to clear the source interrupt in S3C2410_INTMSK to get
15991 + * anything good happening
15992 + */
15993 +static int fiq_init_irq_source(int irq_index_fiq)
15994 +{
15995 +       int rc = 0;
15996 +
15997 +       if (!irq_index_fiq) /* no interrupt */
15998 +               goto bail;
15999 +
16000 +       local_fiq_disable();
16001 +
16002 +       _fiq_irq = irq_index_fiq;
16003 +       _fiq_ack_mask = 1 << (irq_index_fiq - S3C2410_CPUIRQ_OFFSET);
16004 +       _fiq_timer_index = (irq_index_fiq - IRQ_TIMER0);
16005 +
16006 +       /* set up the timer to operate as a pwm device */
16007 +
16008 +       rc = s3c2410_pwm_init(&pwm_timer_fiq);
16009 +       if (rc)
16010 +               goto bail;
16011 +
16012 +       pwm_timer_fiq.timerid = PWM0 + _fiq_timer_index;
16013 +       pwm_timer_fiq.prescaler = (6 - 1) / 2;
16014 +       pwm_timer_fiq.divider = S3C2410_TCFG1_MUX3_DIV2;
16015 +       /* default rate == ~32us */
16016 +       pwm_timer_fiq.counter = pwm_timer_fiq.comparer = 3000;
16017 +
16018 +       rc = s3c2410_pwm_enable(&pwm_timer_fiq);
16019 +       if (rc)
16020 +               goto bail;
16021 +
16022 +       s3c2410_pwm_start(&pwm_timer_fiq);
16023 +
16024 +       _fiq_timer_divisor = 0xffff; /* so kick will work initially */
16025 +
16026 +       /* let our selected interrupt be a magic FIQ interrupt */
16027 +       __raw_writel(_fiq_ack_mask, S3C2410_INTMOD);
16028 +
16029 +       /* it's ready to go as soon as we unmask the source in S3C2410_INTMSK */
16030 +       local_fiq_enable();
16031 +bail:
16032 +       return rc;
16033 +}
16034 +
16035 +
16036 +/* call this from your kernel module to disable generation of FIQ actions */
16037 +static void fiq_disable_irq_source(void)
16038 +{
16039 +       /* nothing makes FIQ any more */
16040 +       __raw_writel(0, S3C2410_INTMOD);
16041 +       local_fiq_disable();
16042 +       _fiq_irq = 0; /* no active source interrupt now either */
16043 +}
16044 +
16045 +/*
16046 + * fiq_kick() forces a FIQ event to happen shortly after leaving the routine
16047 + */
16048 +void fiq_kick(void)
16049 +{
16050 +       unsigned long flags;
16051 +       u32 tcon;
16052 +
16053 +       if (!fiq_ready) {
16054 +               printk(KERN_ERR "fiq_kick called before fiq probed\n");
16055 +               return;
16056 +       }
16057 +
16058 +       /* we have to take care about FIQ because this modification is
16059 +        * non-atomic, FIQ could come in after the read and before the
16060 +        * writeback and its changes to the register would be lost
16061 +        * (platform INTMSK mod code is taken care of already)
16062 +        */
16063 +       local_save_flags(flags);
16064 +       local_fiq_disable();
16065 +       /* allow FIQs to resume */
16066 +       __raw_writel(__raw_readl(S3C2410_INTMSK) &
16067 +                    ~(1 << (_fiq_irq - S3C2410_CPUIRQ_OFFSET)),
16068 +                    S3C2410_INTMSK);
16069 +       tcon = __raw_readl(S3C2410_TCON) & ~S3C2410_TCON_T3START;
16070 +       /* fake the timer to a count of 1 */
16071 +       __raw_writel(1, S3C2410_TCNTB(_fiq_timer_index));
16072 +       __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD, S3C2410_TCON);
16073 +       __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD | S3C2410_TCON_T3START,
16074 +                    S3C2410_TCON);
16075 +       __raw_writel(tcon | S3C2410_TCON_T3START, S3C2410_TCON);
16076 +       local_irq_restore(flags);
16077 +}
16078 +EXPORT_SYMBOL_GPL(fiq_kick);
16079 +
16080 +
16081 +
16082 +
16083 +static int __init sc32440_fiq_probe(struct platform_device *pdev)
16084 +{
16085 +       struct resource *r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
16086 +       struct sc32440_fiq_platform_data *pdata = pdev->dev.platform_data;
16087 +       int ret;
16088 +
16089 +       if (!r)
16090 +               return -EIO;
16091 +
16092 +       /* configure for the interrupt we are meant to use */
16093 +       printk(KERN_INFO "Enabling FIQ using irq %d\n", r->start);
16094 +
16095 +       fiq_set_vector_and_regs();
16096 +       fiq_init_irq_source(r->start);
16097 +
16098 +       ret = sysfs_create_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
16099 +       if (ret)
16100 +               return ret;
16101 +
16102 +       fiq_ready = 1;
16103 +
16104 +       /*
16105 +        * if wanted, users can defer registration of devices
16106 +        * that depend on FIQ until after we register, and can use our
16107 +        * device as parent so suspend-resume ordering is correct
16108 +        */
16109 +       if (pdata->attach_child_devices)
16110 +               (pdata->attach_child_devices)(&pdev->dev);
16111 +
16112 +       return 0;
16113 +}
16114 +
16115 +static int sc32440_fiq_remove(struct platform_device *pdev)
16116 +{
16117 +       fiq_disable_irq_source();
16118 +       sysfs_remove_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
16119 +
16120 +       return 0;
16121 +}
16122 +
16123 +static void fiq_set_vector_and_regs(void)
16124 +{
16125 +       struct pt_regs regs;
16126 +
16127 +       /* prep the special FIQ mode regs */
16128 +       memset(&regs, 0, sizeof(regs));
16129 +       regs.ARM_r8 = (unsigned long)s3c2440_fiq_isr;
16130 +       regs.ARM_r10 = FIQ_VECTOR + SIZEOF_FIQ_JUMP;
16131 +       regs.ARM_sp = FIQ_VECTOR + SIZEOF_FIQ_JUMP + FIQ_STACK_SIZE - 4;
16132 +
16133 +       /* copy our jump to the real ISR into the hard vector address */
16134 +       set_fiq_handler(s3c2440_FIQ_Branch, SIZEOF_FIQ_JUMP);
16135 +
16136 +       /* set up the special FIQ-mode-only registers from our regs */
16137 +       set_fiq_regs(&regs);
16138 +}
16139 +
16140 +#ifdef CONFIG_PM
16141 +static int sc32440_fiq_suspend(struct platform_device *pdev, pm_message_t state)
16142 +{
16143 +       /* nothing makes FIQ any more */
16144 +       __raw_writel(0, S3C2410_INTMOD);
16145 +       local_fiq_disable();
16146 +
16147 +       return 0;
16148 +}
16149 +
16150 +static int sc32440_fiq_resume(struct platform_device *pdev)
16151 +{
16152 +       fiq_set_vector_and_regs();
16153 +       fiq_init_irq_source(_fiq_irq);
16154 +       return 0;
16155 +}
16156 +#else
16157 +#define sc32440_fiq_suspend    NULL
16158 +#define sc32440_fiq_resume     NULL
16159 +#endif
16160 +
16161 +static struct platform_driver sc32440_fiq_driver = {
16162 +       .driver = {
16163 +               .name   = "sc32440_fiq",
16164 +               .owner  = THIS_MODULE,
16165 +       },
16166 +
16167 +       .probe   = sc32440_fiq_probe,
16168 +       .remove  = __devexit_p(sc32440_fiq_remove),
16169 +       .suspend = sc32440_fiq_suspend,
16170 +       .resume  = sc32440_fiq_resume,
16171 +};
16172 +
16173 +static int __init sc32440_fiq_init(void)
16174 +{
16175 +       fiq_set_vector_and_regs();
16176 +
16177 +       return platform_driver_register(&sc32440_fiq_driver);
16178 +}
16179 +
16180 +static void __exit sc32440_fiq_exit(void)
16181 +{
16182 +       fiq_disable_irq_source();
16183 +}
16184 +
16185 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
16186 +MODULE_LICENSE("GPL");
16187 +
16188 +module_init(sc32440_fiq_init);
16189 +module_exit(sc32440_fiq_exit);
16190 Index: linux-2.6.28/arch/arm/mach-s3c2440/fiq_c_isr.h
16191 ===================================================================
16192 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
16193 +++ linux-2.6.28/arch/arm/mach-s3c2440/fiq_c_isr.h      2009-01-02 00:01:56.000000000 +0100
16194 @@ -0,0 +1,76 @@
16195 +#ifndef _LINUX_FIQ_C_ISR_H
16196 +#define _LINUX_FIQ_C_ISR_H
16197 +
16198 +#include <mach/regs-irq.h>
16199 +#include <linux/platform_device.h>
16200 +
16201 +extern unsigned long _fiq_count_fiqs;
16202 +extern u32 _fiq_ack_mask;
16203 +extern int _fiq_timer_index;
16204 +extern u16 _fiq_timer_divisor;
16205 +
16206 +/* platform data */
16207 +
16208 +struct sc32440_fiq_platform_data {
16209 +       /*
16210 +        * give an opportunity to use us as parent for
16211 +        * devices that depend on us
16212 +        */
16213 +       void (*attach_child_devices)(struct device *parent_device);
16214 +};
16215 +
16216 +/* This CANNOT be implemented in a module -- it has to be used in code
16217 + * included in the monolithic kernel
16218 + */
16219 +
16220 +#define FIQ_HANDLER_START() \
16221 +void __attribute__ ((naked)) s3c2440_fiq_isr(void) \
16222 +{\
16223 +       /*\
16224 +        * you can declare local vars here, take care to set the frame size\
16225 +        *  below accordingly if there are more than a few dozen bytes of them\
16226 +        */\
16227 +
16228 +/* stick your locals here :-)
16229 + * Do NOT initialize them here!  define them and initialize them after
16230 + * FIQ_HANDLER_ENTRY() is done.
16231 + */
16232 +
16233 +#define FIQ_HANDLER_ENTRY(LOCALS, FRAME) \
16234 +       const int _FIQ_FRAME_SIZE = FRAME; \
16235 +       /* entry takes care to store registers we will be treading on here */\
16236 +       asm __volatile__ (\
16237 +               /* stash FIQ and r0-r8 normal regs */\
16238 +               "stmdb  sp!, {r0-r12, lr};"\
16239 +               /* allow SP to get some space */\
16240 +               "sub     sp, sp, %1 ;"\
16241 +               /* !! THIS SETS THE FRAME, adjust to > sizeof locals */\
16242 +               "sub     fp, sp, %0 ;"\
16243 +               :\
16244 +               : "rI" (LOCALS), "rI" (FRAME)\
16245 +               :"r9"\
16246 +       );
16247 +
16248 +/* stick your ISR code here and then end with... */
16249 +
16250 +#define FIQ_HANDLER_END() \
16251 +       _fiq_count_fiqs++;\
16252 +       __raw_writel(_fiq_ack_mask, S3C2410_SRCPND);\
16253 +\
16254 +       /* exit back to normal mode restoring everything */\
16255 +       asm __volatile__ (\
16256 +               /* pop our allocation */\
16257 +               "add     sp, sp, %0 ;"\
16258 +               /* return FIQ regs back to pristine state\
16259 +                * and get normal regs back\
16260 +                */\
16261 +               "ldmia  sp!, {r0-r12, lr};"\
16262 +\
16263 +               /* return */\
16264 +               "subs   pc, lr, #4;"\
16265 +               : \
16266 +               : "rI" (_FIQ_FRAME_SIZE) \
16267 +       );\
16268 +}
16269 +
16270 +#endif /* _LINUX_FIQ_C_ISR_H */
16271 Index: linux-2.6.28/arch/arm/mach-s3c2440/Kconfig
16272 ===================================================================
16273 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/Kconfig     2008-12-25 00:26:37.000000000 +0100
16274 +++ linux-2.6.28/arch/arm/mach-s3c2440/Kconfig  2009-01-02 00:01:56.000000000 +0100
16275 @@ -22,12 +22,20 @@ config S3C2440_DMA
16276         help
16277           Support for S3C2440 specific DMA code5A
16278
16279 +config S3C2440_C_FIQ
16280 +       bool "FIQ ISR support in C"
16281 +       depends on ARCH_S3C2410
16282 +       select FIQ
16283 +       help
16284 +         Support for S3C2440 FIQ support in C -- see
16285 +         ./arch/arm/mach-s3c2440/fiq_c_isr.c
16286
16287  menu "S3C2440 Machines"
16288
16289  config MACH_ANUBIS
16290         bool "Simtec Electronics ANUBIS"
16291         select CPU_S3C2440
16292 +       select S3C24XX_DCLK
16293         select PM_SIMTEC if PM
16294         select HAVE_PATA_PLATFORM
16295         help
16296 @@ -37,6 +45,7 @@ config MACH_ANUBIS
16297  config MACH_OSIRIS
16298         bool "Simtec IM2440D20 (OSIRIS) module"
16299         select CPU_S3C2440
16300 +       select S3C24XX_DCLK
16301         select PM_SIMTEC if PM
16302         help
16303           Say Y here if you are using the Simtec IM2440D20 module, also
16304 @@ -74,5 +83,30 @@ config MACH_AT2440EVB
16305         help
16306           Say Y here if you are using the AT2440EVB development board
16307
16308 +config MACH_NEO1973_GTA02
16309 +       bool "FIC Neo1973 GSM Phone (GTA02 Hardware)"
16310 +       select CPU_S3C2442
16311 +       select MFD_PCF50633
16312 +       select INPUT_PCF50633_PMU
16313 +       select PCF50633_ADC
16314 +       select PCF50633_GPIO
16315 +       select RTC_DRV_PCF50633
16316 +       select REGULATOR_PCF50633
16317 +       select CHARGER_PCF50633
16318 +       select POWER_SUPPLY
16319 +       select GTA02_HDQ
16320 +       select MACH_NEO1973
16321 +       help
16322 +          Say Y here if you are using the FIC Neo1973 GSM Phone
16323 +
16324 +config NEO1973_GTA02_2440
16325 +       bool "Old FIC Neo1973 GTA02 hardware using S3C2440 CPU"
16326 +       depends on MACH_NEO1973_GTA02
16327 +       select CPU_S3C2440
16328 +       help
16329 +          Say Y here if you are using an early hardware revision
16330 +          of the FIC/Openmoko Neo1973 GTA02 GSM Phone.
16331 +
16332  endmenu
16333
16334 +#source "arch/arm/mach-s3c2440/camera/Kconfig"
16335 Index: linux-2.6.28/arch/arm/mach-s3c2440/mach-anubis.c
16336 ===================================================================
16337 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/mach-anubis.c       2008-12-25 00:26:37.000000000 +0100
16338 +++ linux-2.6.28/arch/arm/mach-s3c2440/mach-anubis.c    2009-01-02 00:01:56.000000000 +0100
16339 @@ -39,7 +39,8 @@
16340  #include <mach/regs-gpio.h>
16341  #include <mach/regs-mem.h>
16342  #include <mach/regs-lcd.h>
16343 -#include <asm/plat-s3c/nand.h>
16344 +#include <plat/nand.h>
16345 +#include <plat/iic.h>
16346
16347  #include <linux/mtd/mtd.h>
16348  #include <linux/mtd/nand.h>
16349 @@ -404,7 +405,7 @@ static struct platform_device *anubis_de
16350         &s3c_device_usb,
16351         &s3c_device_wdt,
16352         &s3c_device_adc,
16353 -       &s3c_device_i2c,
16354 +       &s3c_device_i2c0,
16355         &s3c_device_rtc,
16356         &s3c_device_nand,
16357         &anubis_device_ide0,
16358 @@ -468,6 +469,7 @@ static void __init anubis_map_io(void)
16359
16360  static void __init anubis_init(void)
16361  {
16362 +       s3c_i2c0_set_platdata(NULL);
16363         platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
16364
16365         i2c_register_board_info(0, anubis_i2c_devs,
16366 Index: linux-2.6.28/arch/arm/mach-s3c2440/mach-at2440evb.c
16367 ===================================================================
16368 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/mach-at2440evb.c    2008-12-25 00:26:37.000000000 +0100
16369 +++ linux-2.6.28/arch/arm/mach-s3c2440/mach-at2440evb.c 2009-01-02 00:01:56.000000000 +0100
16370 @@ -35,7 +35,8 @@
16371  #include <mach/regs-gpio.h>
16372  #include <mach/regs-mem.h>
16373  #include <mach/regs-lcd.h>
16374 -#include <asm/plat-s3c/nand.h>
16375 +#include <plat/nand.h>
16376 +#include <plat/iic.h>
16377
16378  #include <linux/mtd/mtd.h>
16379  #include <linux/mtd/nand.h>
16380 @@ -166,7 +167,7 @@ static struct platform_device *at2440evb
16381         &s3c_device_usb,
16382         &s3c_device_wdt,
16383         &s3c_device_adc,
16384 -       &s3c_device_i2c,
16385 +       &s3c_device_i2c0,
16386         &s3c_device_rtc,
16387         &s3c_device_nand,
16388         &at2440evb_device_eth,
16389 @@ -183,6 +184,7 @@ static void __init at2440evb_map_io(void
16390
16391  static void __init at2440evb_init(void)
16392  {
16393 +       s3c_i2c0_set_platdata(NULL);
16394         platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
16395  }
16396
16397 Index: linux-2.6.28/arch/arm/mach-s3c2440/mach-gta02.c
16398 ===================================================================
16399 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
16400 +++ linux-2.6.28/arch/arm/mach-s3c2440/mach-gta02.c     2009-01-02 00:01:56.000000000 +0100
16401 @@ -0,0 +1,1778 @@
16402 +/*
16403 + * linux/arch/arm/mach-s3c2440/mach-gta02.c
16404 + *
16405 + * S3C2440 Machine Support for the FIC GTA02 (Neo1973)
16406 + *
16407 + * Copyright (C) 2006-2007 by Openmoko, Inc.
16408 + * Author: Harald Welte <laforge@openmoko.org>
16409 + * All rights reserved.
16410 + *
16411 + * This program is free software; you can redistribute it and/or
16412 + * modify it under the terms of the GNU General Public License as
16413 + * published by the Free Software Foundation; either version 2 of
16414 + * the License, or (at your option) any later version.
16415 + *
16416 + * This program is distributed in the hope that it will be useful,
16417 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16418 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16419 + * GNU General Public License for more details.
16420 + *
16421 + * You should have received a copy of the GNU General Public License
16422 + * along with this program; if not, write to the Free Software
16423 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16424 + * MA 02111-1307 USA
16425 + *
16426 + */
16427 +
16428 +#include <linux/kernel.h>
16429 +#include <linux/types.h>
16430 +#include <linux/interrupt.h>
16431 +#include <linux/list.h>
16432 +#include <linux/delay.h>
16433 +#include <linux/timer.h>
16434 +#include <linux/init.h>
16435 +#include <linux/workqueue.h>
16436 +#include <linux/platform_device.h>
16437 +#include <linux/serial_core.h>
16438 +#include <linux/spi/spi.h>
16439 +#include <linux/spi/glamo.h>
16440 +#include <linux/spi/spi_bitbang.h>
16441 +#include <linux/mmc/host.h>
16442 +
16443 +#include <linux/mtd/mtd.h>
16444 +#include <linux/mtd/nand.h>
16445 +#include <linux/mtd/nand_ecc.h>
16446 +#include <linux/mtd/partitions.h>
16447 +#include <linux/mtd/physmap.h>
16448 +
16449 +#include <linux/i2c.h>
16450 +#include <linux/backlight.h>
16451 +#include <linux/regulator/machine.h>
16452 +
16453 +#include <linux/mfd/pcf50633/core.h>
16454 +#include <linux/mfd/pcf50633/mbc.h>
16455 +#include <linux/mfd/pcf50633/adc.h>
16456 +#include <linux/mfd/pcf50633/gpio.h>
16457 +#include <linux/mfd/pcf50633/led.h>
16458 +
16459 +#include <linux/lis302dl.h>
16460 +
16461 +#include <asm/mach/arch.h>
16462 +#include <asm/mach/map.h>
16463 +#include <asm/mach/irq.h>
16464 +
16465 +#include <mach/hardware.h>
16466 +#include <mach/io.h>
16467 +#include <asm/irq.h>
16468 +#include <asm/mach-types.h>
16469 +
16470 +#include <mach/regs-irq.h>
16471 +#include <mach/regs-gpio.h>
16472 +#include <mach/regs-gpioj.h>
16473 +#include <mach/fb.h>
16474 +#include <mach/mci.h>
16475 +#include <mach/ts.h>
16476 +#include <mach/spi.h>
16477 +#include <mach/spi-gpio.h>
16478 +#include <mach/usb-control.h>
16479 +#include <mach/regs-mem.h>
16480 +
16481 +#include <mach/gta02.h>
16482 +
16483 +#include <plat/regs-serial.h>
16484 +#include <plat/nand.h>
16485 +#include <plat/devs.h>
16486 +#include <plat/cpu.h>
16487 +#include <plat/pm.h>
16488 +#include <plat/udc.h>
16489 +#include <plat/iic.h>
16490 +#include <asm/plat-s3c24xx/neo1973.h>
16491 +#include <mach/neo1973-pm-gsm.h>
16492 +#include <mach/gta02-pm-wlan.h>
16493 +
16494 +#include <linux/jbt6k74.h>
16495 +
16496 +#include <linux/glamofb.h>
16497 +
16498 +#include <mach/fiq_ipc_gta02.h>
16499 +#include "fiq_c_isr.h"
16500 +#include <linux/gta02_hdq.h>
16501 +#include <linux/bq27000_battery.h>
16502 +
16503 +#include <linux/i2c.h>
16504 +
16505 +#include "../plat-s3c24xx/neo1973_pm_gps.h"
16506 +
16507 +#include <linux/ts_filter_linear.h>
16508 +#include <linux/ts_filter_mean.h>
16509 +#include <linux/ts_filter_median.h>
16510 +#include <linux/ts_filter_group.h>
16511 +
16512 +/* arbitrates which sensor IRQ owns the shared SPI bus */
16513 +static spinlock_t motion_irq_lock;
16514 +
16515 +/* define FIQ IPC struct */
16516 +/*
16517 + * contains stuff FIQ ISR modifies and normal kernel code can see and use
16518 + * this is defined in <arch/arm/mach-s3c2410/include/mach/fiq_ipc_gta02.h>, you should customize
16519 + * the definition in there and include the same definition in your kernel
16520 + * module that wants to interoperate with your FIQ code.
16521 + */
16522 +struct fiq_ipc fiq_ipc;
16523 +EXPORT_SYMBOL(fiq_ipc);
16524 +
16525 +#define DIVISOR_FROM_US(x) ((x) << 3)
16526 +
16527 +#define FIQ_DIVISOR_VIBRATOR DIVISOR_FROM_US(100)
16528 +
16529 +#ifdef CONFIG_GTA02_HDQ
16530 +/* HDQ specific */
16531 +#define HDQ_SAMPLE_PERIOD_US 20
16532 +/* private HDQ FSM state -- all other info interesting for caller in fiq_ipc */
16533 +static enum hdq_bitbang_states hdq_state;
16534 +static u8 hdq_ctr;
16535 +static u8 hdq_ctr2;
16536 +static u8 hdq_bit;
16537 +static u8 hdq_shifter;
16538 +static u8 hdq_tx_data_done;
16539 +
16540 +#define FIQ_DIVISOR_HDQ DIVISOR_FROM_US(HDQ_SAMPLE_PERIOD_US)
16541 +#endif
16542 +/* define FIQ ISR */
16543 +
16544 +FIQ_HANDLER_START()
16545 +/* define your locals here -- no initializers though */
16546 +       u16 divisor;
16547 +FIQ_HANDLER_ENTRY(64, 64)
16548 +/* Your ISR here :-) */
16549 +       divisor = 0xffff;
16550 +
16551 +       /* Vibrator servicing */
16552 +
16553 +       if (fiq_ipc.vib_pwm_latched || fiq_ipc.vib_pwm) { /* not idle */
16554 +               if (((u8)_fiq_count_fiqs) == fiq_ipc.vib_pwm_latched)
16555 +                       neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 0);
16556 +               if (((u8)_fiq_count_fiqs) == 0) {
16557 +                       fiq_ipc.vib_pwm_latched = fiq_ipc.vib_pwm;
16558 +                       if (fiq_ipc.vib_pwm_latched)
16559 +                               neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 1);
16560 +               }
16561 +               divisor = FIQ_DIVISOR_VIBRATOR;
16562 +       }
16563 +
16564 +#ifdef CONFIG_GTA02_HDQ
16565 +       /* HDQ servicing */
16566 +
16567 +       switch (hdq_state) {
16568 +       case HDQB_IDLE:
16569 +               if (fiq_ipc.hdq_request_ctr == fiq_ipc.hdq_transaction_ctr)
16570 +                       break;
16571 +               hdq_ctr = 210 / HDQ_SAMPLE_PERIOD_US;
16572 +               s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
16573 +               s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
16574 +               hdq_tx_data_done = 0;
16575 +               hdq_state = HDQB_TX_BREAK;
16576 +               break;
16577 +
16578 +       case HDQB_TX_BREAK: /* issue low for > 190us */
16579 +               if (--hdq_ctr == 0) {
16580 +                       hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
16581 +                       hdq_state = HDQB_TX_BREAK_RECOVERY;
16582 +                       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
16583 +               }
16584 +               break;
16585 +
16586 +       case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */
16587 +               if (--hdq_ctr)
16588 +                       break;
16589 +               hdq_shifter = fiq_ipc.hdq_ads;
16590 +               hdq_bit = 8; /* 8 bits of ads / rw */
16591 +               hdq_tx_data_done = 0; /* doing ads */
16592 +               /* fallthru on last one */
16593 +       case HDQB_ADS_CALC:
16594 +               if (hdq_shifter & 1)
16595 +                       hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US;
16596 +               else
16597 +                       hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US;
16598 +               /* carefully precompute the other phase length */
16599 +               hdq_ctr2 = (210 - (hdq_ctr * HDQ_SAMPLE_PERIOD_US)) /
16600 +                               HDQ_SAMPLE_PERIOD_US;
16601 +               hdq_state = HDQB_ADS_LOW;
16602 +               hdq_shifter >>= 1;
16603 +               hdq_bit--;
16604 +               s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
16605 +               break;
16606 +
16607 +       case HDQB_ADS_LOW:
16608 +               if (--hdq_ctr)
16609 +                       break;
16610 +               s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
16611 +               hdq_state = HDQB_ADS_HIGH;
16612 +               break;
16613 +
16614 +       case HDQB_ADS_HIGH:
16615 +               if (--hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */
16616 +                       break;
16617 +               if (hdq_bit) { /* more bits to do */
16618 +                       hdq_state = HDQB_ADS_CALC;
16619 +                       break;
16620 +               }
16621 +               /* no more bits, wait it out until hdq_ctr2 exhausted */
16622 +               if (hdq_ctr2)
16623 +                       break;
16624 +               /* ok no more bits and very last state */
16625 +               hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
16626 +               /* FIXME 0 = read */
16627 +               if (fiq_ipc.hdq_ads & 0x80) { /* write the byte out */
16628 +                        /* set delay before payload */
16629 +                       hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
16630 +                       /* already high, no need to write */
16631 +                       hdq_state = HDQB_WAIT_TX;
16632 +                       break;
16633 +               }
16634 +               /* read the next byte */
16635 +               hdq_bit = 8; /* 8 bits of data */
16636 +               hdq_ctr = 3000 / HDQ_SAMPLE_PERIOD_US;
16637 +               hdq_state = HDQB_WAIT_RX;
16638 +               s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT);
16639 +               break;
16640 +
16641 +       case HDQB_WAIT_TX: /* issue low for > 40us */
16642 +               if (--hdq_ctr)
16643 +                       break;
16644 +               if (!hdq_tx_data_done) { /* was that the data sent? */
16645 +                       hdq_tx_data_done++;
16646 +                       hdq_shifter = fiq_ipc.hdq_tx_data;
16647 +                       hdq_bit = 8; /* 8 bits of data */
16648 +                       hdq_state = HDQB_ADS_CALC; /* start sending */
16649 +                       break;
16650 +               }
16651 +               fiq_ipc.hdq_error = 0;
16652 +               fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16653 +               hdq_state = HDQB_IDLE; /* all tx is done */
16654 +               /* idle in input mode, it's pulled up by 10K */
16655 +               s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT);
16656 +               break;
16657 +
16658 +       case HDQB_WAIT_RX: /* wait for battery to talk to us */
16659 +               if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin) == 0) {
16660 +                       /* it talks to us! */
16661 +                       hdq_ctr2 = 1;
16662 +                       hdq_bit = 8; /* 8 bits of data */
16663 +                       /* timeout */
16664 +                       hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
16665 +                       hdq_state = HDQB_DATA_RX_LOW;
16666 +                       break;
16667 +               }
16668 +               if (--hdq_ctr == 0) { /* timed out, error */
16669 +                       fiq_ipc.hdq_error = 1;
16670 +                       fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16671 +                       hdq_state = HDQB_IDLE; /* abort */
16672 +               }
16673 +               break;
16674 +
16675 +       /*
16676 +        * HDQ basically works by measuring the low time of the bit cell
16677 +        * 32-50us --> '1', 80 - 145us --> '0'
16678 +        */
16679 +
16680 +       case HDQB_DATA_RX_LOW:
16681 +               if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) {
16682 +                       fiq_ipc.hdq_rx_data >>= 1;
16683 +                       if (hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US))
16684 +                               fiq_ipc.hdq_rx_data |= 0x80;
16685 +
16686 +                       if (--hdq_bit == 0) {
16687 +                               fiq_ipc.hdq_error = 0;
16688 +                               fiq_ipc.hdq_transaction_ctr =
16689 +                                                       fiq_ipc.hdq_request_ctr;
16690 +
16691 +                               hdq_state = HDQB_IDLE;
16692 +                       } else
16693 +                               hdq_state = HDQB_DATA_RX_HIGH;
16694 +                       /* timeout */
16695 +                       hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US;
16696 +                       hdq_ctr2 = 1;
16697 +                       break;
16698 +               }
16699 +               hdq_ctr2++;
16700 +               if (--hdq_ctr)
16701 +                       break;
16702 +                /* timed out, error */
16703 +               fiq_ipc.hdq_error = 2;
16704 +               fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16705 +               hdq_state = HDQB_IDLE; /* abort */
16706 +               break;
16707 +
16708 +       case HDQB_DATA_RX_HIGH:
16709 +               if (!s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) {
16710 +                       /* it talks to us! */
16711 +                       hdq_ctr2 = 1;
16712 +                       /* timeout */
16713 +                       hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US;
16714 +                       hdq_state = HDQB_DATA_RX_LOW;
16715 +                       break;
16716 +               }
16717 +               if (--hdq_ctr)
16718 +                       break;
16719 +               /* timed out, error */
16720 +               fiq_ipc.hdq_error = 3;
16721 +               fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
16722 +
16723 +               /* we're in input mode already */
16724 +               hdq_state = HDQB_IDLE; /* abort */
16725 +               break;
16726 +       }
16727 +
16728 +       if (hdq_state != HDQB_IDLE) /* ie, not idle */
16729 +               if (divisor > FIQ_DIVISOR_HDQ)
16730 +                       divisor = FIQ_DIVISOR_HDQ; /* keep us going */
16731 +#endif
16732 +
16733 +       /* disable further timer interrupts if nobody has any work
16734 +        * or adjust rate according to who still has work
16735 +        *
16736 +        * CAUTION: it means forground code must disable FIQ around
16737 +        * its own non-atomic S3C2410_INTMSK changes... not common
16738 +        * thankfully and taken care of by the fiq-basis patch
16739 +        */
16740 +       if (divisor == 0xffff) /* mask the fiq irq source */
16741 +               __raw_writel(__raw_readl(S3C2410_INTMSK) | _fiq_ack_mask,
16742 +                            S3C2410_INTMSK);
16743 +       else /* still working, maybe at a different rate */
16744 +               __raw_writel(divisor, S3C2410_TCNTB(_fiq_timer_index));
16745 +       _fiq_timer_divisor = divisor;
16746 +
16747 +FIQ_HANDLER_END()
16748 +
16749 +
16750 +/*
16751 + * this gets called every 1ms when we paniced.
16752 + */
16753 +
16754 +static long gta02_panic_blink(long count)
16755 +{
16756 +       long delay = 0;
16757 +       static long last_blink;
16758 +       static char led;
16759 +
16760 +       if (count - last_blink < 100) /* 200ms period, fast blink */
16761 +               return 0;
16762 +
16763 +       led ^= 1;
16764 +       s3c2410_gpio_cfgpin(GTA02_GPIO_AUX_LED, S3C2410_GPIO_OUTPUT);
16765 +       neo1973_gpb_setpin(GTA02_GPIO_AUX_LED, led);
16766 +
16767 +       last_blink = count;
16768 +       return delay;
16769 +}
16770 +
16771 +
16772 +/**
16773 + * returns PCB revision information in b9,b8 and b2,b1,b0
16774 + * Pre-GTA02 A6 returns 0x000
16775 + *     GTA02 A6 returns 0x101
16776 + *     ...
16777 + */
16778 +
16779 +int gta02_get_pcb_revision(void)
16780 +{
16781 +       int n;
16782 +       int u = 0;
16783 +       static unsigned long pinlist[] = {
16784 +               GTA02_PCB_ID1_0,
16785 +               GTA02_PCB_ID1_1,
16786 +               GTA02_PCB_ID1_2,
16787 +               GTA02_PCB_ID2_0,
16788 +               GTA02_PCB_ID2_1,
16789 +       };
16790 +       static int pin_offset[] = {
16791 +               0, 1, 2, 8, 9
16792 +       };
16793 +
16794 +       for (n = 0 ; n < ARRAY_SIZE(pinlist); n++) {
16795 +               /*
16796 +                * set the PCB version GPIO to be pulled-down input
16797 +                * force low briefly first
16798 +                */
16799 +               s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_OUTPUT);
16800 +               s3c2410_gpio_setpin(pinlist[n], 0);
16801 +               /* misnomer: it is a pullDOWN in 2442 */
16802 +               s3c2410_gpio_pullup(pinlist[n], 1);
16803 +               s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_INPUT);
16804 +
16805 +               udelay(10);
16806 +
16807 +               if (s3c2410_gpio_getpin(pinlist[n]))
16808 +                       u |= 1 << pin_offset[n];
16809 +
16810 +               /*
16811 +               * when not being interrogated, all of the revision GPIO
16812 +               * are set to output HIGH without pulldown so no current flows
16813 +               * if they are NC or pulled up.
16814 +               */
16815 +               s3c2410_gpio_setpin(pinlist[n], 1);
16816 +               s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_OUTPUT);
16817 +               /* misnomer: it is a pullDOWN in 2442 */
16818 +               s3c2410_gpio_pullup(pinlist[n], 0);
16819 +       }
16820 +
16821 +       return u;
16822 +}
16823 +
16824 +struct platform_device gta02_version_device = {
16825 +       .name           = "neo1973-version",
16826 +       .num_resources  = 0,
16827 +};
16828 +
16829 +struct platform_device gta02_resume_reason_device = {
16830 +       .name           = "neo1973-resume",
16831 +       .num_resources  = 0,
16832 +};
16833 +
16834 +struct platform_device gta02_memconfig_device = {
16835 +       .name           = "neo1973-memconfig",
16836 +       .num_resources  = 0,
16837 +};
16838 +
16839 +static struct map_desc gta02_iodesc[] __initdata = {
16840 +       {
16841 +               .virtual        = 0xe0000000,
16842 +               .pfn            = __phys_to_pfn(S3C2410_CS3+0x01000000),
16843 +               .length         = SZ_1M,
16844 +               .type           = MT_DEVICE
16845 +       },
16846 +};
16847 +
16848 +#define UCON S3C2410_UCON_DEFAULT
16849 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
16850 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
16851 +
16852 +static struct s3c2410_uartcfg gta02_uartcfgs[] = {
16853 +       [0] = {
16854 +               .hwport      = 0,
16855 +               .flags       = 0,
16856 +               .ucon        = UCON,
16857 +               .ulcon       = ULCON,
16858 +               .ufcon       = UFCON,
16859 +       },
16860 +       [1] = {
16861 +               .hwport      = 1,
16862 +               .flags       = 0,
16863 +               .ucon        = UCON,
16864 +               .ulcon       = ULCON,
16865 +               .ufcon       = UFCON,
16866 +       },
16867 +       [2] = {
16868 +               .hwport      = 2,
16869 +               .flags       = 0,
16870 +               .ucon        = UCON,
16871 +               .ulcon       = ULCON,
16872 +               .ufcon       = UFCON,
16873 +       },
16874 +
16875 +};
16876 +
16877 +/* BQ27000 Battery */
16878 +
16879 +static int gta02_get_charger_online_status(void)
16880 +{
16881 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
16882 +
16883 +       return pcf->mbc.usb_online;
16884 +}
16885 +
16886 +static int gta02_get_charger_active_status(void)
16887 +{
16888 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
16889 +
16890 +       return pcf->mbc.usb_active;
16891 +}
16892 +
16893 +
16894 +struct bq27000_platform_data bq27000_pdata = {
16895 +       .name = "battery",
16896 +       .rsense_mohms = 20,
16897 +       .hdq_read = gta02hdq_read,
16898 +       .hdq_write = gta02hdq_write,
16899 +       .hdq_initialized = gta02hdq_initialized,
16900 +       .get_charger_online_status = gta02_get_charger_online_status,
16901 +       .get_charger_active_status = gta02_get_charger_active_status
16902 +};
16903 +
16904 +struct platform_device bq27000_battery_device = {
16905 +       .name           = "bq27000-battery",
16906 +       .dev = {
16907 +               .platform_data = &bq27000_pdata,
16908 +       },
16909 +};
16910 +
16911 +#define ADC_NOM_CHG_DETECT_1A 6
16912 +#define ADC_NOM_CHG_DETECT_USB 43
16913 +
16914 +static void
16915 +gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res)
16916 +{
16917 +       int  ma;
16918 +
16919 +       /* Interpret charger type */
16920 +       if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) {
16921 +
16922 +               /* Stop GPO driving out now that we have a IA charger */
16923 +               pcf50633_gpio_set(pcf, PCF50633_GPO, 0);
16924 +
16925 +               ma = 1000;
16926 +       } else
16927 +               ma = 100;
16928 +
16929 +       pcf50633_mbc_usb_curlim_set(pcf, ma);
16930 +}
16931 +
16932 +static struct delayed_work gta02_charger_work;
16933 +static int gta02_usb_vbus_draw;
16934 +
16935 +static void gta02_charger_worker(struct work_struct *work)
16936 +{
16937 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
16938 +
16939 +       if (gta02_usb_vbus_draw) {
16940 +               pcf50633_mbc_usb_curlim_set(pcf, gta02_usb_vbus_draw);
16941 +               return;
16942 +       } else {
16943 +               pcf50633_adc_async_read(pcf,
16944 +                       PCF50633_ADCC1_MUX_ADCIN1,
16945 +                       PCF50633_ADCC1_AVERAGE_16,
16946 +                       gta02_configure_pmu_for_charger, NULL);
16947 +               return;
16948 +       }
16949 +}
16950 +
16951 +#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000)
16952 +static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq)
16953 +{
16954 +       if (irq == PCF50633_IRQ_USBINS) {
16955 +               schedule_delayed_work(&gta02_charger_work,
16956 +                               GTA02_CHARGER_CONFIGURE_TIMEOUT);
16957 +               return;
16958 +       } else if (irq == PCF50633_IRQ_USBREM) {
16959 +               cancel_delayed_work_sync(&gta02_charger_work);
16960 +               gta02_usb_vbus_draw = 0;
16961 +       }
16962 +}
16963 +
16964 +static struct platform_device gta01_pm_gps_dev = {
16965 +       .name           = "neo1973-pm-gps",
16966 +};
16967 +
16968 +static struct platform_device gta01_pm_bt_dev = {
16969 +       .name           = "neo1973-pm-bt",
16970 +};
16971 +
16972 +static struct platform_device gta02_pm_gsm_dev = {
16973 +       .name           = "neo1973-pm-gsm",
16974 +};
16975 +
16976 +/* this is called when pc50633 is probed, unfortunately quite late in the
16977 + * day since it is an I2C bus device.  Here we can belatedly define some
16978 + * platform devices with the advantage that we can mark the pcf50633 as the
16979 + * parent.  This makes them get suspended and resumed with their parent
16980 + * the pcf50633 still around.
16981 + */
16982 +
16983 +static struct platform_device gta02_glamo_dev;
16984 +static void mangle_glamo_res_by_system_rev(void);
16985 +
16986 +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf);
16987 +static void gta02_pmu_regulator_registered(struct pcf50633 *pcf, int id);
16988 +
16989 +static struct platform_device gta02_pm_wlan_dev = {
16990 +       .name           = "gta02-pm-wlan",
16991 +};
16992 +
16993 +static struct regulator_consumer_supply ldo4_consumers[] = {
16994 +       {
16995 +               .dev = &gta01_pm_bt_dev.dev,
16996 +               .supply = "BT_3V2",
16997 +       },
16998 +};
16999 +
17000 +static struct regulator_consumer_supply ldo5_consumers[] = {
17001 +       {
17002 +               .dev = &gta01_pm_gps_dev.dev,
17003 +               .supply = "RF_3V",
17004 +       },
17005 +};
17006 +
17007 +/*
17008 + * We need this dummy thing to fill the regulator consumers
17009 + */
17010 +static struct platform_device gta02_mmc_dev = {
17011 +       /* details filled in by glamo core */
17012 +};
17013 +
17014 +static struct regulator_consumer_supply hcldo_consumers[] = {
17015 +       {
17016 +               .dev = &gta02_mmc_dev.dev,
17017 +               .supply = "SD_3V3",
17018 +       },
17019 +};
17020 +
17021 +static char *gta02_batteries[] = {
17022 +       "battery",
17023 +};
17024 +
17025 +struct pcf50633_platform_data gta02_pcf_pdata = {
17026 +       .resumers = {
17027 +               [0] =   PCF50633_INT1_USBINS |
17028 +                       PCF50633_INT1_USBREM |
17029 +                       PCF50633_INT1_ALARM,
17030 +               [1] =   PCF50633_INT2_ONKEYF,
17031 +               [2] =   PCF50633_INT3_ONKEY1S,
17032 +               [3] =   PCF50633_INT4_LOWSYS |
17033 +                       PCF50633_INT4_LOWBAT |
17034 +                       PCF50633_INT4_HIGHTMP,
17035 +       },
17036 +
17037 +       .batteries = gta02_batteries,
17038 +       .num_batteries = ARRAY_SIZE(gta02_batteries),
17039 +
17040 +       .reg_init_data = {
17041 +               [PCF50633_REGULATOR_AUTO] = {
17042 +                       .constraints = {
17043 +                               .min_uV = 3300000,
17044 +                               .max_uV = 3300000,
17045 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17046 +                               .boot_on = 1,
17047 +                               .apply_uV = 1,
17048 +                               .state_mem = {
17049 +                                       .enabled = 1,
17050 +                               },
17051 +                       },
17052 +                       .num_consumer_supplies = 0,
17053 +               },
17054 +               [PCF50633_REGULATOR_DOWN1] = {
17055 +                       .constraints = {
17056 +                               .min_uV = 1300000,
17057 +                               .max_uV = 1600000,
17058 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17059 +                               .boot_on = 1,
17060 +                               .apply_uV = 1,
17061 +                       },
17062 +                       .num_consumer_supplies = 0,
17063 +               },
17064 +               [PCF50633_REGULATOR_DOWN2] = {
17065 +                       .constraints = {
17066 +                               .min_uV = 1800000,
17067 +                               .max_uV = 1800000,
17068 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17069 +                               .apply_uV = 1,
17070 +                               .boot_on = 1,
17071 +                               .state_mem = {
17072 +                                       .enabled = 1,
17073 +                               },
17074 +                       },
17075 +                       .num_consumer_supplies = 0,
17076 +               },
17077 +               [PCF50633_REGULATOR_HCLDO] = {
17078 +                       .constraints = {
17079 +                               .min_uV = 2000000,
17080 +                               .max_uV = 3300000,
17081 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17082 +                               .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
17083 +                               .boot_on = 1,
17084 +                       },
17085 +                       .num_consumer_supplies = 1,
17086 +                       .consumer_supplies = hcldo_consumers,
17087 +               },
17088 +               [PCF50633_REGULATOR_LDO1] = {
17089 +                       .constraints = {
17090 +                               .min_uV = 1300000,
17091 +                               .max_uV = 1300000,
17092 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17093 +                               .apply_uV = 1,
17094 +                       },
17095 +                       .num_consumer_supplies = 0,
17096 +               },
17097 +               [PCF50633_REGULATOR_LDO2] = {
17098 +                       .constraints = {
17099 +                               .min_uV = 3300000,
17100 +                               .max_uV = 3300000,
17101 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17102 +                               .apply_uV = 1,
17103 +                       },
17104 +                       .num_consumer_supplies = 0,
17105 +               },
17106 +               [PCF50633_REGULATOR_LDO3] = {
17107 +                       .constraints = {
17108 +                               .min_uV = 3000000,
17109 +                               .max_uV = 3000000,
17110 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17111 +                               .apply_uV = 1,
17112 +                       },
17113 +                       .num_consumer_supplies = 0,
17114 +               },
17115 +               [PCF50633_REGULATOR_LDO4] = {
17116 +                       .constraints = {
17117 +                               .min_uV = 3200000,
17118 +                               .max_uV = 3200000,
17119 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17120 +                               .apply_uV = 1,
17121 +                       },
17122 +                       .num_consumer_supplies = 1,
17123 +                       .consumer_supplies = ldo4_consumers,
17124 +               },
17125 +               [PCF50633_REGULATOR_LDO5] = {
17126 +                       .constraints = {
17127 +                               .min_uV = 1500000,
17128 +                               .max_uV = 1500000,
17129 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17130 +                               .apply_uV = 1,
17131 +                       },
17132 +                       .num_consumer_supplies = 1,
17133 +                       .consumer_supplies = ldo5_consumers,
17134 +               },
17135 +               [PCF50633_REGULATOR_LDO6] = {
17136 +                       .constraints = {
17137 +                               .min_uV = 0,
17138 +                               .max_uV = 3300000,
17139 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17140 +                       },
17141 +                       .num_consumer_supplies = 0,
17142 +               },
17143 +               [PCF50633_REGULATOR_MEMLDO] = {
17144 +                       .constraints = {
17145 +                               .min_uV = 1800000,
17146 +                               .max_uV = 1800000,
17147 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
17148 +                               .state_mem = {
17149 +                                       .enabled = 1,
17150 +                               },
17151 +                       },
17152 +                       .num_consumer_supplies = 0,
17153 +               },
17154 +
17155 +       },
17156 +       .probe_done = gta02_pmu_attach_child_devices,
17157 +       .regulator_registered = gta02_pmu_regulator_registered,
17158 +       .mbc_event_callback = gta02_pmu_event_callback,
17159 +};
17160 +
17161 +static void mangle_pmu_pdata_by_system_rev(void)
17162 +{
17163 +       struct regulator_init_data *reg_init_data;
17164 +
17165 +       reg_init_data = gta02_pcf_pdata.reg_init_data;
17166 +
17167 +       switch (system_rev) {
17168 +       case GTA02v1_SYSTEM_REV:
17169 +               /* FIXME: this is only in v1 due to wrong PMU variant */
17170 +               reg_init_data[PCF50633_REGULATOR_DOWN2]
17171 +                                       .constraints.state_mem.enabled = 1;
17172 +               break;
17173 +       case GTA02v2_SYSTEM_REV:
17174 +       case GTA02v3_SYSTEM_REV:
17175 +       case GTA02v4_SYSTEM_REV:
17176 +       case GTA02v5_SYSTEM_REV:
17177 +       case GTA02v6_SYSTEM_REV:
17178 +               reg_init_data[PCF50633_REGULATOR_LDO1]
17179 +                                       .constraints.min_uV = 3300000;
17180 +               reg_init_data[PCF50633_REGULATOR_LDO1]
17181 +                                       .constraints.min_uV = 3300000;
17182 +               reg_init_data[PCF50633_REGULATOR_LDO1]
17183 +                                       .constraints.state_mem.enabled = 0;
17184 +
17185 +               reg_init_data[PCF50633_REGULATOR_LDO5]
17186 +                                       .constraints.min_uV = 3000000;
17187 +               reg_init_data[PCF50633_REGULATOR_LDO5]
17188 +                                       .constraints.max_uV = 3000000;
17189 +
17190 +               reg_init_data[PCF50633_REGULATOR_LDO6]
17191 +                                       .constraints.min_uV = 3000000;
17192 +               reg_init_data[PCF50633_REGULATOR_LDO6]
17193 +                                       .constraints.max_uV = 3000000;
17194 +               reg_init_data[PCF50633_REGULATOR_LDO6]
17195 +                                       .constraints.apply_uV = 1;
17196 +               break;
17197 +       default:
17198 +               break;
17199 +       }
17200 +}
17201 +
17202 +#ifdef CONFIG_GTA02_HDQ
17203 +/* HDQ */
17204 +
17205 +static void gta02_hdq_attach_child_devices(struct device *parent_device)
17206 +{
17207 +       switch (system_rev) {
17208 +       case GTA02v5_SYSTEM_REV:
17209 +       case GTA02v6_SYSTEM_REV:
17210 +               bq27000_battery_device.dev.parent = parent_device;
17211 +               platform_device_register(&bq27000_battery_device);
17212 +               break;
17213 +       default:
17214 +               break;
17215 +       }
17216 +}
17217 +
17218 +static struct resource gta02_hdq_resources[] = {
17219 +       [0] = {
17220 +               .start  = GTA02v5_GPIO_HDQ,
17221 +               .end    = GTA02v5_GPIO_HDQ,
17222 +       },
17223 +};
17224 +
17225 +struct gta02_hdq_platform_data gta02_hdq_platform_data = {
17226 +       .attach_child_devices = gta02_hdq_attach_child_devices
17227 +};
17228 +
17229 +struct platform_device gta02_hdq_device = {
17230 +       .name           = "gta02-hdq",
17231 +       .num_resources  = 1,
17232 +       .resource       = gta02_hdq_resources,
17233 +       .dev            = {
17234 +               .platform_data = &gta02_hdq_platform_data,
17235 +       },
17236 +};
17237 +#endif
17238 +
17239 +/* vibrator (child of FIQ) */
17240 +
17241 +static struct resource gta02_vibrator_resources[] = {
17242 +       [0] = {
17243 +               .start  = GTA02_GPIO_VIBRATOR_ON,
17244 +               .end    = GTA02_GPIO_VIBRATOR_ON,
17245 +       },
17246 +};
17247 +
17248 +static struct platform_device gta02_vibrator_dev = {
17249 +       .name           = "neo1973-vibrator",
17250 +       .num_resources  = ARRAY_SIZE(gta02_vibrator_resources),
17251 +       .resource       = gta02_vibrator_resources,
17252 +};
17253 +
17254 +/* FIQ, used PWM regs, so not child of PWM */
17255 +
17256 +static void gta02_fiq_attach_child_devices(struct device *parent_device)
17257 +{
17258 +#ifdef CONFIG_GTA02_HDQ
17259 +       switch (system_rev) {
17260 +       case GTA02v5_SYSTEM_REV:
17261 +       case GTA02v6_SYSTEM_REV:
17262 +               gta02_hdq_device.dev.parent = parent_device;
17263 +               platform_device_register(&gta02_hdq_device);
17264 +               gta02_vibrator_dev.dev.parent = parent_device;
17265 +               platform_device_register(&gta02_vibrator_dev);
17266 +               break;
17267 +       default:
17268 +               break;
17269 +       }
17270 +#endif
17271 +}
17272 +
17273 +
17274 +static struct resource sc32440_fiq_resources[] = {
17275 +       [0] = {
17276 +               .flags  = IORESOURCE_IRQ,
17277 +               .start  = IRQ_TIMER3,
17278 +               .end    = IRQ_TIMER3,
17279 +       },
17280 +};
17281 +
17282 +struct sc32440_fiq_platform_data gta02_sc32440_fiq_platform_data = {
17283 +       .attach_child_devices = gta02_fiq_attach_child_devices
17284 +};
17285 +
17286 +struct platform_device sc32440_fiq_device = {
17287 +       .name           = "sc32440_fiq",
17288 +       .num_resources  = 1,
17289 +       .resource       = sc32440_fiq_resources,
17290 +       .dev            = {
17291 +               .platform_data = &gta02_sc32440_fiq_platform_data,
17292 +       },
17293 +};
17294 +
17295 +/* NOR Flash */
17296 +
17297 +#define GTA02_FLASH_BASE       0x18000000 /* GCS3 */
17298 +#define GTA02_FLASH_SIZE       0x200000 /* 2MBytes */
17299 +
17300 +static struct physmap_flash_data gta02_nor_flash_data = {
17301 +       .width          = 2,
17302 +};
17303 +
17304 +static struct resource gta02_nor_flash_resource = {
17305 +       .start          = GTA02_FLASH_BASE,
17306 +       .end            = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1,
17307 +       .flags          = IORESOURCE_MEM,
17308 +};
17309 +
17310 +static struct platform_device gta02_nor_flash = {
17311 +       .name           = "physmap-flash",
17312 +       .id             = 0,
17313 +       .dev            = {
17314 +                               .platform_data  = &gta02_nor_flash_data,
17315 +                       },
17316 +       .resource       = &gta02_nor_flash_resource,
17317 +       .num_resources  = 1,
17318 +};
17319 +
17320 +
17321 +struct platform_device s3c24xx_pwm_device = {
17322 +       .name           = "s3c24xx_pwm",
17323 +       .num_resources  = 0,
17324 +};
17325 +
17326 +static struct i2c_board_info gta02_i2c_devs[] __initdata = {
17327 +       {
17328 +               I2C_BOARD_INFO("pcf50633", 0x73),
17329 +               .irq = GTA02_IRQ_PCF50633,
17330 +               .platform_data = &gta02_pcf_pdata,
17331 +       },
17332 +};
17333 +
17334 +static struct s3c2410_nand_set gta02_nand_sets[] = {
17335 +       [0] = {
17336 +               .name           = "neo1973-nand",
17337 +               .nr_chips       = 1,
17338 +               .flags          = S3C2410_NAND_BBT,
17339 +       },
17340 +};
17341 +
17342 +/* choose a set of timings derived from S3C@2442B MCP54
17343 + * data sheet (K5D2G13ACM-D075 MCP Memory)
17344 + */
17345 +
17346 +static struct s3c2410_platform_nand gta02_nand_info = {
17347 +       .tacls          = 0,
17348 +       .twrph0         = 25,
17349 +       .twrph1         = 15,
17350 +       .nr_sets        = ARRAY_SIZE(gta02_nand_sets),
17351 +       .sets           = gta02_nand_sets,
17352 +       .software_ecc   = 1,
17353 +};
17354 +
17355 +
17356 +static void gta02_s3c_mmc_set_power(unsigned char power_mode,
17357 +    unsigned short vdd)
17358 +{
17359 +       gta02_wlan_power(
17360 +           power_mode == MMC_POWER_ON ||
17361 +           power_mode == MMC_POWER_UP);
17362 +}
17363 +
17364 +
17365 +static struct s3c24xx_mci_pdata gta02_s3c_mmc_cfg = {
17366 +       .set_power      = gta02_s3c_mmc_set_power,
17367 +};
17368 +
17369 +static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd)
17370 +{
17371 +       switch (cmd) {
17372 +       case S3C2410_UDC_P_ENABLE:
17373 +               printk(KERN_DEBUG "%s S3C2410_UDC_P_ENABLE\n", __func__);
17374 +               neo1973_gpb_setpin(GTA02_GPIO_USB_PULLUP, 1);
17375 +               break;
17376 +       case S3C2410_UDC_P_DISABLE:
17377 +               printk(KERN_DEBUG "%s S3C2410_UDC_P_DISABLE\n", __func__);
17378 +               neo1973_gpb_setpin(GTA02_GPIO_USB_PULLUP, 0);
17379 +               break;
17380 +       case S3C2410_UDC_P_RESET:
17381 +               printk(KERN_DEBUG "%s S3C2410_UDC_P_RESET\n", __func__);
17382 +               /* FIXME! */
17383 +               break;
17384 +       default:
17385 +               break;
17386 +       }
17387 +}
17388 +
17389 +/* get PMU to set USB current limit accordingly */
17390 +
17391 +static void gta02_udc_vbus_draw(unsigned int ma)
17392 +{
17393 +        if (!gta02_pcf_pdata.pcf) {
17394 +               printk(KERN_ERR "********** NULL gta02_pcf_pdata.pcf *****\n");
17395 +               return;
17396 +       }
17397 +
17398 +       gta02_usb_vbus_draw = ma;
17399 +
17400 +       schedule_delayed_work(&gta02_charger_work,
17401 +                               GTA02_CHARGER_CONFIGURE_TIMEOUT);
17402 +}
17403 +
17404 +static struct s3c2410_udc_mach_info gta02_udc_cfg = {
17405 +       .vbus_draw      = gta02_udc_vbus_draw,
17406 +       .udc_command    = gta02_udc_command,
17407 +
17408 +};
17409 +
17410 +
17411 +/* touchscreen configuration */
17412 +
17413 +static struct ts_filter_linear_configuration gta02_ts_linear_config = {
17414 +       .constants = {1, 0, 0, 0, 1, 0, 1},     /* don't modify coords */
17415 +       .coord0 = 0,
17416 +       .coord1 = 1,
17417 +};
17418 +
17419 +static struct ts_filter_group_configuration gta02_ts_group_config = {
17420 +       .extent = 12,
17421 +       .close_enough = 10,
17422 +       .threshold = 6,         /* at least half of the points in a group */
17423 +       .attempts = 10,
17424 +};
17425 +
17426 +static struct ts_filter_median_configuration gta02_ts_median_config = {
17427 +       .extent = 20,
17428 +       .decimation_below = 3,
17429 +       .decimation_threshold = 8 * 3,
17430 +       .decimation_above = 4,
17431 +};
17432 +
17433 +static struct ts_filter_mean_configuration gta02_ts_mean_config = {
17434 +       .bits_filter_length = 2, /* 4 points */
17435 +};
17436 +
17437 +static struct s3c2410_ts_mach_info gta02_ts_cfg = {
17438 +       .delay = 10000,
17439 +       .presc = 0xff, /* slow as we can go */
17440 +       .filter_sequence = {
17441 +               [0] = &ts_filter_group_api,
17442 +               [1] = &ts_filter_median_api,
17443 +               [2] = &ts_filter_mean_api,
17444 +               [3] = &ts_filter_linear_api,
17445 +       },
17446 +       .filter_config = {
17447 +               [0] = &gta02_ts_group_config,
17448 +               [1] = &gta02_ts_median_config,
17449 +               [2] = &gta02_ts_mean_config,
17450 +               [3] = &gta02_ts_linear_config,
17451 +       },
17452 +};
17453 +
17454 +
17455 +static void gta02_bl_set_intensity(int intensity)
17456 +{
17457 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
17458 +       int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT);
17459 +       int ret;
17460 +
17461 +       intensity >>= 2;
17462 +
17463 +       if (intensity == old_intensity)
17464 +               return;
17465 +
17466 +       /* We can't do this anywhere else */
17467 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5);
17468 +
17469 +       if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3))
17470 +               old_intensity = 0;
17471 +
17472 +       /*
17473 +        * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60)
17474 +        * if seen, you have to re-enable the LED unit
17475 +        */
17476 +       if (!intensity || !old_intensity)
17477 +               pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0);
17478 +
17479 +       if (!intensity) /* illegal to set LEDOUT to 0 */
17480 +               ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f,
17481 +                                                                            2);
17482 +       else
17483 +               ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f,
17484 +                              intensity);
17485 +
17486 +       if (intensity)
17487 +               pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2);
17488 +
17489 +}
17490 +
17491 +static struct generic_bl_info gta02_bl_info = {
17492 +       .name                   = "gta02-bl",
17493 +       .max_intensity          = 0xff,
17494 +       .default_intensity      = 0xff,
17495 +       .set_bl_intensity       = gta02_bl_set_intensity,
17496 +};
17497 +
17498 +static struct platform_device gta02_bl_dev = {
17499 +       .name             = "generic-bl",
17500 +       .id               = 1,
17501 +       .dev = {
17502 +               .platform_data = &gta02_bl_info,
17503 +       },
17504 +};
17505 +
17506 +/* SPI: LCM control interface attached to Glamo3362 */
17507 +
17508 +static void gta02_jbt6k74_reset(int devidx, int level)
17509 +{
17510 +       glamo_lcm_reset(level);
17511 +}
17512 +
17513 +static void gta02_jbt6k74_probe_completed(struct device *dev)
17514 +{
17515 +       struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
17516 +
17517 +       /* Switch on backlight. Qi does not do it for us */
17518 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x01);
17519 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
17520 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
17521 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
17522 +
17523 +       gta02_bl_dev.dev.parent = dev;
17524 +       platform_device_register(&gta02_bl_dev);
17525 +}
17526 +
17527 +const struct jbt6k74_platform_data jbt6k74_pdata = {
17528 +       .reset          = gta02_jbt6k74_reset,
17529 +       .probe_completed = gta02_jbt6k74_probe_completed,
17530 +};
17531 +
17532 +static struct spi_board_info gta02_spi_board_info[] = {
17533 +       {
17534 +               .modalias       = "jbt6k74",
17535 +               /* platform_data */
17536 +               .platform_data  = &jbt6k74_pdata,
17537 +               /* controller_data */
17538 +               /* irq */
17539 +               .max_speed_hz   = 100 * 1000,
17540 +               .bus_num        = 2,
17541 +               /* chip_select */
17542 +       },
17543 +};
17544 +
17545 +#if 0 /* currently this is not used and we use gpio spi */
17546 +static struct glamo_spi_info glamo_spi_cfg = {
17547 +       .board_size     = ARRAY_SIZE(gta02_spi_board_info),
17548 +       .board_info     = gta02_spi_board_info,
17549 +};
17550 +#endif /* 0 */
17551 +
17552 +static struct glamo_spigpio_info glamo_spigpio_cfg = {
17553 +       .pin_clk        = GLAMO_GPIO10_OUTPUT,
17554 +       .pin_mosi       = GLAMO_GPIO11_OUTPUT,
17555 +       .pin_cs         = GLAMO_GPIO12_OUTPUT,
17556 +       .pin_miso       = 0,
17557 +       .board_size     = ARRAY_SIZE(gta02_spi_board_info),
17558 +       .board_info     = gta02_spi_board_info,
17559 +};
17560 +
17561 +/* SPI: Accelerometers attached to SPI of s3c244x */
17562 +
17563 +/*
17564 + * Situation is that Linux SPI can't work in an interrupt context, so we
17565 + * implement our own bitbang here.  Arbitration is needed because not only
17566 + * can this interrupt happen at any time even if foreground wants to use
17567 + * the bitbang API from Linux, but multiple motion sensors can be on the
17568 + * same SPI bus, and multiple interrupts can happen.
17569 + *
17570 + * Foreground / interrupt arbitration is okay because the interrupts are
17571 + * disabled around all the foreground SPI code.
17572 + *
17573 + * Interrupt / Interrupt arbitration is evidently needed, otherwise we
17574 + * lose edge-triggered service after a while due to the two sensors sharing
17575 + * the SPI bus having irqs at the same time eventually.
17576 + *
17577 + * Servicing is typ 75 - 100us at 400MHz.
17578 + */
17579 +
17580 +/* #define DEBUG_SPEW_MS */
17581 +#define MG_PER_SAMPLE 18
17582 +
17583 +struct lis302dl_platform_data lis302_pdata_top;
17584 +struct lis302dl_platform_data lis302_pdata_bottom;
17585 +
17586 +/*
17587 + * generic SPI RX and TX bitbang
17588 + * only call with interrupts off!
17589 + */
17590 +
17591 +static void __gta02_lis302dl_bitbang(struct lis302dl_info *lis, u8 *tx,
17592 +                                            int tx_bytes, u8 *rx, int rx_bytes)
17593 +{
17594 +       struct lis302dl_platform_data *pdata = lis->pdata;
17595 +       int n;
17596 +       u8 shifter = 0;
17597 +       unsigned long other_cs;
17598 +
17599 +       /*
17600 +        * Huh... "quirk"... CS on this device is not really "CS" like you can
17601 +        * expect.
17602 +        *
17603 +        * When it is 0 it selects SPI interface mode.
17604 +        * When it is 1 it selects I2C interface mode.
17605 +        *
17606 +        * Because we have 2 devices on one interface we have to make sure
17607 +        * that the "disabled" device (actually in I2C mode) don't think we're
17608 +        * talking to it.
17609 +        *
17610 +        * When we talk to the "enabled" device, the "disabled" device sees
17611 +        * the clocks as I2C clocks, creating havoc.
17612 +        *
17613 +        * I2C sees MOSI going LOW while CLK HIGH as a START action, thus we
17614 +        * must ensure this is never issued.
17615 +        */
17616 +
17617 +       if (&lis302_pdata_top == pdata)
17618 +               other_cs = lis302_pdata_bottom.pin_chip_select;
17619 +       else
17620 +               other_cs = lis302_pdata_top.pin_chip_select;
17621 +
17622 +       s3c2410_gpio_setpin(other_cs, 1);
17623 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
17624 +       s3c2410_gpio_setpin(pdata->pin_clk, 1);
17625 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 0);
17626 +
17627 +       /* send the register index, r/w and autoinc bits */
17628 +       for (n = 0; n < (tx_bytes << 3); n++) {
17629 +               if (!(n & 7))
17630 +                       shifter = ~tx[n >> 3];
17631 +               s3c2410_gpio_setpin(pdata->pin_clk, 0);
17632 +               s3c2410_gpio_setpin(pdata->pin_mosi, !(shifter & 0x80));
17633 +               s3c2410_gpio_setpin(pdata->pin_clk, 1);
17634 +               shifter <<= 1;
17635 +       }
17636 +
17637 +       for (n = 0; n < (rx_bytes << 3); n++) { /* 8 bits each */
17638 +               s3c2410_gpio_setpin(pdata->pin_clk, 0);
17639 +               shifter <<= 1;
17640 +               if (s3c2410_gpio_getpin(pdata->pin_miso))
17641 +                       shifter |= 1;
17642 +               if ((n & 7) == 7)
17643 +                       rx[n >> 3] = shifter;
17644 +               s3c2410_gpio_setpin(pdata->pin_clk, 1);
17645 +       }
17646 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
17647 +       s3c2410_gpio_setpin(other_cs, 1);
17648 +}
17649 +
17650 +
17651 +static int gta02_lis302dl_bitbang_read_reg(struct lis302dl_info *lis, u8 reg)
17652 +{
17653 +       u8 data = 0xc0 | reg; /* read, autoincrement */
17654 +       unsigned long flags;
17655 +
17656 +       local_irq_save(flags);
17657 +
17658 +       __gta02_lis302dl_bitbang(lis, &data, 1, &data, 1);
17659 +
17660 +       local_irq_restore(flags);
17661 +
17662 +       return data;
17663 +}
17664 +
17665 +static void gta02_lis302dl_bitbang_write_reg(struct lis302dl_info *lis, u8 reg,
17666 +                                                                        u8 val)
17667 +{
17668 +       u8 data[2] = { 0x00 | reg, val }; /* write, no autoincrement */
17669 +       unsigned long flags;
17670 +
17671 +       local_irq_save(flags);
17672 +
17673 +       __gta02_lis302dl_bitbang(lis, &data[0], 2, NULL, 0);
17674 +
17675 +       local_irq_restore(flags);
17676 +
17677 +}
17678 +
17679 +
17680 +void gta02_lis302dl_suspend_io(struct lis302dl_info *lis, int resume)
17681 +{
17682 +       struct lis302dl_platform_data *pdata = lis->pdata;
17683 +
17684 +       if (!resume) {
17685 +                /*
17686 +                * we don't want to power them with a high level
17687 +                * because GSENSOR_3V3 is not up during suspend
17688 +                */
17689 +               s3c2410_gpio_setpin(pdata->pin_chip_select, 0);
17690 +               s3c2410_gpio_setpin(pdata->pin_clk, 0);
17691 +               s3c2410_gpio_setpin(pdata->pin_mosi, 0);
17692 +               /* misnomer: it is a pullDOWN in 2442 */
17693 +               s3c2410_gpio_pullup(pdata->pin_miso, 1);
17694 +               return;
17695 +       }
17696 +
17697 +       /* back to normal */
17698 +       s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
17699 +       s3c2410_gpio_setpin(pdata->pin_clk, 1);
17700 +       /* misnomer: it is a pullDOWN in 2442 */
17701 +       s3c2410_gpio_pullup(pdata->pin_miso, 0);
17702 +
17703 +       s3c2410_gpio_cfgpin(pdata->pin_chip_select, S3C2410_GPIO_OUTPUT);
17704 +       s3c2410_gpio_cfgpin(pdata->pin_clk, S3C2410_GPIO_OUTPUT);
17705 +       s3c2410_gpio_cfgpin(pdata->pin_mosi, S3C2410_GPIO_OUTPUT);
17706 +       s3c2410_gpio_cfgpin(pdata->pin_miso, S3C2410_GPIO_INPUT);
17707 +
17708 +}
17709 +
17710 +
17711 +
17712 +struct lis302dl_platform_data lis302_pdata_top = {
17713 +               .name           = "lis302-1 (top)",
17714 +               .pin_chip_select= S3C2410_GPD12,
17715 +               .pin_clk        = S3C2410_GPG7,
17716 +               .pin_mosi       = S3C2410_GPG6,
17717 +               .pin_miso       = S3C2410_GPG5,
17718 +               .interrupt      = GTA02_IRQ_GSENSOR_1,
17719 +               .open_drain     = 1, /* altered at runtime by PCB rev */
17720 +               .lis302dl_bitbang = __gta02_lis302dl_bitbang,
17721 +               .lis302dl_bitbang_reg_read = gta02_lis302dl_bitbang_read_reg,
17722 +               .lis302dl_bitbang_reg_write = gta02_lis302dl_bitbang_write_reg,
17723 +               .lis302dl_suspend_io = gta02_lis302dl_suspend_io,
17724 +};
17725 +
17726 +struct lis302dl_platform_data lis302_pdata_bottom = {
17727 +               .name           = "lis302-2 (bottom)",
17728 +               .pin_chip_select= S3C2410_GPD13,
17729 +               .pin_clk        = S3C2410_GPG7,
17730 +               .pin_mosi       = S3C2410_GPG6,
17731 +               .pin_miso       = S3C2410_GPG5,
17732 +               .interrupt      = GTA02_IRQ_GSENSOR_2,
17733 +               .open_drain     = 1, /* altered at runtime by PCB rev */
17734 +               .lis302dl_bitbang = __gta02_lis302dl_bitbang,
17735 +               .lis302dl_bitbang_reg_read = gta02_lis302dl_bitbang_read_reg,
17736 +               .lis302dl_bitbang_reg_write = gta02_lis302dl_bitbang_write_reg,
17737 +               .lis302dl_suspend_io = gta02_lis302dl_suspend_io,
17738 +};
17739 +
17740 +
17741 +static struct platform_device s3c_device_spi_acc1 = {
17742 +       .name             = "lis302dl",
17743 +       .id               = 1,
17744 +       .dev = {
17745 +               .platform_data = &lis302_pdata_top,
17746 +       },
17747 +};
17748 +
17749 +static struct platform_device s3c_device_spi_acc2 = {
17750 +       .name             = "lis302dl",
17751 +       .id               = 2,
17752 +       .dev = {
17753 +               .platform_data = &lis302_pdata_bottom,
17754 +       },
17755 +};
17756 +
17757 +static struct resource gta02_led_resources[] = {
17758 +       {
17759 +               .name   = "gta02-power:orange",
17760 +               .start  = GTA02_GPIO_PWR_LED1,
17761 +               .end    = GTA02_GPIO_PWR_LED1,
17762 +       }, {
17763 +               .name   = "gta02-power:blue",
17764 +               .start  = GTA02_GPIO_PWR_LED2,
17765 +               .end    = GTA02_GPIO_PWR_LED2,
17766 +       }, {
17767 +               .name   = "gta02-aux:red",
17768 +               .start  = GTA02_GPIO_AUX_LED,
17769 +               .end    = GTA02_GPIO_AUX_LED,
17770 +       },
17771 +};
17772 +
17773 +struct platform_device gta02_led_dev = {
17774 +       .name           = "gta02-led",
17775 +       .num_resources  = ARRAY_SIZE(gta02_led_resources),
17776 +       .resource       = gta02_led_resources,
17777 +};
17778 +
17779 +static struct resource gta02_button_resources[] = {
17780 +       [0] = {
17781 +               .start = GTA02_GPIO_AUX_KEY,
17782 +               .end   = GTA02_GPIO_AUX_KEY,
17783 +       },
17784 +       [1] = {
17785 +               .start = GTA02_GPIO_HOLD_KEY,
17786 +               .end   = GTA02_GPIO_HOLD_KEY,
17787 +       },
17788 +       [2] = {
17789 +               .start = GTA02_GPIO_JACK_INSERT,
17790 +               .end   = GTA02_GPIO_JACK_INSERT,
17791 +       },
17792 +       [3] = {
17793 +               .start = 0,
17794 +               .end   = 0,
17795 +       },
17796 +       [4] = {
17797 +               .start = 0,
17798 +               .end   = 0,
17799 +       },
17800 +};
17801 +
17802 +static struct platform_device gta02_button_dev = {
17803 +       .name           = "neo1973-button",
17804 +       .num_resources  = ARRAY_SIZE(gta02_button_resources),
17805 +       .resource       = gta02_button_resources,
17806 +};
17807 +
17808 +
17809 +static struct platform_device gta02_pm_usbhost_dev = {
17810 +       .name           = "neo1973-pm-host",
17811 +};
17812 +
17813 +
17814 +/* USB */
17815 +static struct s3c2410_hcd_info gta02_usb_info = {
17816 +       .port[0]        = {
17817 +               .flags  = S3C_HCDFLG_USED,
17818 +       },
17819 +       .port[1]        = {
17820 +               .flags  = 0,
17821 +       },
17822 +};
17823 +
17824 +static int glamo_irq_is_wired(void)
17825 +{
17826 +       int rc;
17827 +       int count = 0;
17828 +
17829 +       /*
17830 +       * GTA02 S-Media IRQs prior to A5 are broken due to a lack of
17831 +       * a pullup on the INT# line.  Check for the bad behaviour.
17832 +       */
17833 +       s3c2410_gpio_setpin(S3C2410_GPG4, 0);
17834 +       s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_OUTP);
17835 +       s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_INP);
17836 +       /*
17837 +       * we force it low ourselves for a moment and resume being input.
17838 +       * If there is a pullup, it won't stay low for long.  But if the
17839 +       * level converter is there as on < A5 revision, the weak keeper
17840 +       * on the input of the LC will hold the line low indefinitiely
17841 +       */
17842 +       do
17843 +               rc = s3c2410_gpio_getpin(S3C2410_GPG4);
17844 +       while ((!rc) && ((count++) < 10));
17845 +       if (rc) { /* it got pulled back up, it's good */
17846 +               printk(KERN_INFO "Detected S-Media IRQ# pullup, "
17847 +               "enabling interrupt\n");
17848 +               return 0;
17849 +       } else  /* Gah we can't work with this level converter */
17850 +               printk(KERN_WARNING "** Detected bad IRQ# circuit found"
17851 +               " on pre-A5 GTA02: S-Media interrupt disabled **\n");
17852 +       return -ENODEV;
17853 +}
17854 +
17855 +static int gta02_glamo_can_set_mmc_power(void)
17856 +{
17857 +       switch (system_rev) {
17858 +               case GTA02v3_SYSTEM_REV:
17859 +               case GTA02v4_SYSTEM_REV:
17860 +               case GTA02v5_SYSTEM_REV:
17861 +               case GTA02v6_SYSTEM_REV:
17862 +                       return 1;
17863 +       }
17864 +
17865 +       return 0;
17866 +}
17867 +
17868 +/* Smedia Glamo 3362 */
17869 +
17870 +/*
17871 + * we crank down SD Card clock dynamically when GPS is powered
17872 + */
17873 +
17874 +static int gta02_glamo_mci_use_slow(void)
17875 +{
17876 +       return neo1973_pm_gps_is_on();
17877 +}
17878 +
17879 +static void gta02_glamo_external_reset(int level)
17880 +{
17881 +       s3c2410_gpio_setpin(GTA02_GPIO_3D_RESET, level);
17882 +       s3c2410_gpio_cfgpin(GTA02_GPIO_3D_RESET, S3C2410_GPIO_OUTPUT);
17883 +}
17884 +
17885 +static struct glamofb_platform_data gta02_glamo_pdata = {
17886 +       .width          = 43,
17887 +       .height         = 58,
17888 +        /* 24.5MHz --> 40.816ns */
17889 +       .pixclock       = 40816,
17890 +       .left_margin    = 8,
17891 +       .right_margin   = 16,
17892 +       .upper_margin   = 2,
17893 +       .lower_margin   = 16,
17894 +       .hsync_len      = 8,
17895 +       .vsync_len      = 2,
17896 +       .fb_mem_size    = 0x400000, /* glamo has 8 megs of SRAM. we use 4 */
17897 +       .xres           = {
17898 +               .min    = 240,
17899 +               .max    = 640,
17900 +               .defval = 480,
17901 +       },
17902 +       .yres           = {
17903 +               .min    = 320,
17904 +               .max    = 640,
17905 +               .defval = 640,
17906 +       },
17907 +       .bpp            = {
17908 +               .min    = 16,
17909 +               .max    = 16,
17910 +               .defval = 16,
17911 +       },
17912 +       //.spi_info     = &glamo_spi_cfg,
17913 +       .spigpio_info   = &glamo_spigpio_cfg,
17914 +
17915 +       /* glamo MMC function platform data */
17916 +       .mmc_dev = &gta02_mmc_dev,
17917 +       .glamo_can_set_mci_power = gta02_glamo_can_set_mmc_power,
17918 +       .glamo_mci_use_slow = gta02_glamo_mci_use_slow,
17919 +       .glamo_irq_is_wired = glamo_irq_is_wired,
17920 +       .glamo_external_reset = gta02_glamo_external_reset
17921 +};
17922 +
17923 +static struct resource gta02_glamo_resources[] = {
17924 +       [0] = {
17925 +               .start  = S3C2410_CS1,
17926 +               .end    = S3C2410_CS1 + 0x1000000 - 1,
17927 +               .flags  = IORESOURCE_MEM,
17928 +       },
17929 +       [1] = {
17930 +               .start  = GTA02_IRQ_3D,
17931 +               .end    = GTA02_IRQ_3D,
17932 +               .flags  = IORESOURCE_IRQ,
17933 +       },
17934 +       [2] = {
17935 +               .start = GTA02v1_GPIO_3D_RESET,
17936 +               .end   = GTA02v1_GPIO_3D_RESET,
17937 +       },
17938 +};
17939 +
17940 +static struct platform_device gta02_glamo_dev = {
17941 +       .name           = "glamo3362",
17942 +       .num_resources  = ARRAY_SIZE(gta02_glamo_resources),
17943 +       .resource       = gta02_glamo_resources,
17944 +       .dev            = {
17945 +               .platform_data  = &gta02_glamo_pdata,
17946 +       },
17947 +};
17948 +
17949 +static void mangle_glamo_res_by_system_rev(void)
17950 +{
17951 +       switch (system_rev) {
17952 +       case GTA02v1_SYSTEM_REV:
17953 +               break;
17954 +       default:
17955 +               gta02_glamo_resources[2].start = GTA02_GPIO_3D_RESET;
17956 +               gta02_glamo_resources[2].end = GTA02_GPIO_3D_RESET;
17957 +               break;
17958 +       }
17959 +
17960 +       switch (system_rev) {
17961 +       case GTA02v1_SYSTEM_REV:
17962 +       case GTA02v2_SYSTEM_REV:
17963 +       case GTA02v3_SYSTEM_REV:
17964 +       /* case GTA02v4_SYSTEM_REV: - FIXME: handle this later */
17965 +               /* The hardware is missing a pull-up resistor and thus can't
17966 +                * support the Smedia Glamo IRQ */
17967 +               gta02_glamo_resources[1].start = 0;
17968 +               gta02_glamo_resources[1].end = 0;
17969 +               break;
17970 +       }
17971 +}
17972 +
17973 +static void __init gta02_map_io(void)
17974 +{
17975 +       s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
17976 +       s3c24xx_init_clocks(12000000);
17977 +       s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
17978 +}
17979 +
17980 +static irqreturn_t gta02_modem_irq(int irq, void *param)
17981 +{
17982 +       printk(KERN_DEBUG "modem wakeup interrupt\n");
17983 +       gta_gsm_interrupts++;
17984 +       return IRQ_HANDLED;
17985 +}
17986 +
17987 +static irqreturn_t ar6000_wow_irq(int irq, void *param)
17988 +{
17989 +       printk(KERN_DEBUG "ar6000_wow interrupt\n");
17990 +       return IRQ_HANDLED;
17991 +}
17992 +
17993 +/*
17994 + * hardware_ecc=1|0
17995 + */
17996 +static char hardware_ecc_str[4] __initdata = "";
17997 +
17998 +static int __init hardware_ecc_setup(char *str)
17999 +{
18000 +       if (str)
18001 +               strlcpy(hardware_ecc_str, str, sizeof(hardware_ecc_str));
18002 +       return 1;
18003 +}
18004 +
18005 +__setup("hardware_ecc=", hardware_ecc_setup);
18006 +
18007 +/* these are the guys that don't need to be children of PMU */
18008 +
18009 +static struct platform_device *gta02_devices[] __initdata = {
18010 +       &gta02_version_device,
18011 +       &s3c_device_usb,
18012 +       &s3c_device_wdt,
18013 +       &gta02_memconfig_device,
18014 +       &s3c_device_sdi,
18015 +       &s3c_device_usbgadget,
18016 +       &s3c_device_nand,
18017 +       &gta02_nor_flash,
18018 +
18019 +       &sc32440_fiq_device,
18020 +       &s3c24xx_pwm_device,
18021 +       &gta02_led_dev,
18022 +       &gta02_pm_wlan_dev, /* not dependent on PMU */
18023 +
18024 +       &s3c_device_iis,
18025 +       &s3c_device_i2c0,
18026 +};
18027 +
18028 +/* these guys DO need to be children of PMU */
18029 +
18030 +static struct platform_device *gta02_devices_pmu_children[] = {
18031 +       &s3c_device_ts, /* input 1 */
18032 +       &gta02_pm_gsm_dev,
18033 +       &gta02_pm_usbhost_dev,
18034 +       &s3c_device_spi_acc1, /* input 2 */
18035 +       &s3c_device_spi_acc2, /* input 3 */
18036 +       &gta02_button_dev, /* input 4 */
18037 +       &gta02_resume_reason_device,
18038 +};
18039 +
18040 +static void gta02_pmu_regulator_registered(struct pcf50633 *pcf, int id)
18041 +{
18042 +       struct platform_device *regulator, *pdev;
18043 +
18044 +       regulator = pcf->pmic.pdev[id];
18045 +
18046 +       switch(id) {
18047 +               case PCF50633_REGULATOR_LDO4:
18048 +                       pdev = &gta01_pm_bt_dev;
18049 +                       break;
18050 +               case PCF50633_REGULATOR_LDO5:
18051 +                       pdev = &gta01_pm_gps_dev;
18052 +                       break;
18053 +               case PCF50633_REGULATOR_HCLDO:
18054 +                       pdev = &gta02_glamo_dev;
18055 +                       break;
18056 +               default:
18057 +                       return;
18058 +       }
18059 +
18060 +       pdev->dev.parent = &regulator->dev;
18061 +       platform_device_register(pdev);
18062 +}
18063 +
18064 +/* this is called when pc50633 is probed, unfortunately quite late in the
18065 + * day since it is an I2C bus device.  Here we can belatedly define some
18066 + * platform devices with the advantage that we can mark the pcf50633 as the
18067 + * parent.  This makes them get suspended and resumed with their parent
18068 + * the pcf50633 still around.
18069 + */
18070 +
18071 +static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf)
18072 +{
18073 +       int n;
18074 +
18075 +       for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++)
18076 +               gta02_devices_pmu_children[n]->dev.parent = pcf->dev;
18077 +
18078 +       mangle_glamo_res_by_system_rev();
18079 +       platform_add_devices(gta02_devices_pmu_children,
18080 +                                       ARRAY_SIZE(gta02_devices_pmu_children));
18081 +}
18082 +
18083 +
18084 +static void __init gta02_machine_init(void)
18085 +{
18086 +       int rc;
18087 +
18088 +       /* set the panic callback to make AUX blink fast */
18089 +       panic_blink = gta02_panic_blink;
18090 +
18091 +       switch (system_rev) {
18092 +       case GTA02v6_SYSTEM_REV:
18093 +               /* we need push-pull interrupt from motion sensors */
18094 +               lis302_pdata_top.open_drain = 0;
18095 +               lis302_pdata_bottom.open_drain = 0;
18096 +               break;
18097 +       default:
18098 +               break;
18099 +       }
18100 +
18101 +       spin_lock_init(&motion_irq_lock);
18102 +       INIT_DELAYED_WORK(&gta02_charger_work, gta02_charger_worker);
18103 +
18104 +       /* Glamo chip select optimization */
18105 +/*      *((u32 *)(S3C2410_MEMREG(((1 + 1) << 2)))) = 0x1280; */
18106 +
18107 +       /* do not force soft ecc if we are asked to use hardware_ecc */
18108 +       if (hardware_ecc_str[0] == '1')
18109 +               gta02_nand_info.software_ecc = 0;
18110 +
18111 +       s3c_device_usb.dev.platform_data = &gta02_usb_info;
18112 +       s3c_device_nand.dev.platform_data = &gta02_nand_info;
18113 +       s3c_device_sdi.dev.platform_data = &gta02_s3c_mmc_cfg;
18114 +
18115 +       /* acc sensor chip selects */
18116 +       s3c2410_gpio_setpin(S3C2410_GPD12, 1);
18117 +       s3c2410_gpio_cfgpin(S3C2410_GPD12, S3C2410_GPIO_OUTPUT);
18118 +       s3c2410_gpio_setpin(S3C2410_GPD13, 1);
18119 +       s3c2410_gpio_cfgpin(S3C2410_GPD13, S3C2410_GPIO_OUTPUT);
18120 +
18121 +       s3c24xx_udc_set_platdata(&gta02_udc_cfg);
18122 +       s3c_i2c0_set_platdata(NULL);
18123 +       set_s3c2410ts_info(&gta02_ts_cfg);
18124 +
18125 +       mangle_glamo_res_by_system_rev();
18126 +
18127 +       i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
18128 +
18129 +       mangle_pmu_pdata_by_system_rev();
18130 +
18131 +       platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
18132 +
18133 +       s3c_pm_init();
18134 +
18135 +       /* Make sure the modem can wake us up */
18136 +       set_irq_type(GTA02_IRQ_MODEM, IRQ_TYPE_EDGE_RISING);
18137 +       rc = request_irq(GTA02_IRQ_MODEM, gta02_modem_irq, IRQF_DISABLED,
18138 +                        "modem", NULL);
18139 +       if (rc < 0)
18140 +               printk(KERN_ERR "GTA02: can't request GSM modem wakeup IRQ\n");
18141 +       enable_irq_wake(GTA02_IRQ_MODEM);
18142 +
18143 +       /* Make sure the wifi module can wake us up*/
18144 +       set_irq_type(GTA02_IRQ_WLAN_GPIO1, IRQ_TYPE_EDGE_RISING);
18145 +       rc = request_irq(GTA02_IRQ_WLAN_GPIO1, ar6000_wow_irq, IRQF_DISABLED,
18146 +                       "ar6000", NULL);
18147 +
18148 +       if (rc < 0)
18149 +               printk(KERN_ERR "GTA02: can't request ar6k wakeup IRQ\n");
18150 +       enable_irq_wake(GTA02_IRQ_WLAN_GPIO1);
18151 +}
18152 +
18153 +void DEBUG_LED(int n)
18154 +{
18155 +//     int *p = NULL;
18156 +       switch (n) {
18157 +       case 0:
18158 +               neo1973_gpb_setpin(GTA02_GPIO_PWR_LED1, 1);
18159 +               break;
18160 +       case 1:
18161 +               neo1973_gpb_setpin(GTA02_GPIO_PWR_LED2, 1);
18162 +               break;
18163 +       default:
18164 +               neo1973_gpb_setpin(GTA02_GPIO_AUX_LED, 1);
18165 +               break;
18166 +       }
18167 +//     printk(KERN_ERR"die %d\n", *p);
18168 +}
18169 +EXPORT_SYMBOL_GPL(DEBUG_LED);
18170 +
18171 +MACHINE_START(NEO1973_GTA02, "GTA02")
18172 +       .phys_io        = S3C2410_PA_UART,
18173 +       .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
18174 +       .boot_params    = S3C2410_SDRAM_PA + 0x100,
18175 +       .map_io         = gta02_map_io,
18176 +       .init_irq       = s3c24xx_init_irq,
18177 +       .init_machine   = gta02_machine_init,
18178 +       .timer          = &s3c24xx_timer,
18179 +MACHINE_END
18180 Index: linux-2.6.28/arch/arm/mach-s3c2440/mach-nexcoder.c
18181 ===================================================================
18182 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/mach-nexcoder.c     2008-12-25 00:26:37.000000000 +0100
18183 +++ linux-2.6.28/arch/arm/mach-s3c2440/mach-nexcoder.c  2009-01-02 00:01:56.000000000 +0100
18184 @@ -37,6 +37,7 @@
18185  //#include <asm/debug-ll.h>
18186  #include <mach/regs-gpio.h>
18187  #include <plat/regs-serial.h>
18188 +#include <plat/iic.h>
18189
18190  #include <plat/s3c2410.h>
18191  #include <plat/s3c2440.h>
18192 @@ -107,7 +108,7 @@ static struct platform_device *nexcoder_
18193         &s3c_device_usb,
18194         &s3c_device_lcd,
18195         &s3c_device_wdt,
18196 -       &s3c_device_i2c,
18197 +       &s3c_device_i2c0,
18198         &s3c_device_iis,
18199         &s3c_device_rtc,
18200         &s3c_device_camif,
18201 @@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void)
18202
18203  static void __init nexcoder_init(void)
18204  {
18205 +       s3c_i2c0_set_platdata(NULL);
18206         platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
18207  };
18208
18209 Index: linux-2.6.28/arch/arm/mach-s3c2440/mach-osiris.c
18210 ===================================================================
18211 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/mach-osiris.c       2008-12-25 00:26:37.000000000 +0100
18212 +++ linux-2.6.28/arch/arm/mach-s3c2440/mach-osiris.c    2009-01-02 00:01:56.000000000 +0100
18213 @@ -37,7 +37,8 @@
18214  #include <mach/regs-gpio.h>
18215  #include <mach/regs-mem.h>
18216  #include <mach/regs-lcd.h>
18217 -#include <asm/plat-s3c/nand.h>
18218 +#include <plat/nand.h>
18219 +#include <plat/iic.h>
18220
18221  #include <linux/mtd/mtd.h>
18222  #include <linux/mtd/nand.h>
18223 @@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_
18224  /* Standard Osiris devices */
18225
18226  static struct platform_device *osiris_devices[] __initdata = {
18227 -       &s3c_device_i2c,
18228 +       &s3c_device_i2c0,
18229         &s3c_device_wdt,
18230         &s3c_device_nand,
18231         &osiris_pcmcia,
18232 @@ -398,6 +399,8 @@ static void __init osiris_init(void)
18233         sysdev_class_register(&osiris_pm_sysclass);
18234         sysdev_register(&osiris_pm_sysdev);
18235
18236 +       s3c_i2c0_set_platdata(NULL);
18237 +
18238         i2c_register_board_info(0, osiris_i2c_devs,
18239                                 ARRAY_SIZE(osiris_i2c_devs));
18240
18241 Index: linux-2.6.28/arch/arm/mach-s3c2440/mach-rx3715.c
18242 ===================================================================
18243 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/mach-rx3715.c       2008-12-25 00:26:37.000000000 +0100
18244 +++ linux-2.6.28/arch/arm/mach-s3c2440/mach-rx3715.c    2009-01-02 00:01:56.000000000 +0100
18245 @@ -42,7 +42,7 @@
18246  #include <mach/regs-lcd.h>
18247
18248  #include <mach/h1940.h>
18249 -#include <asm/plat-s3c/nand.h>
18250 +#include <plat/nand.h>
18251  #include <mach/fb.h>
18252
18253  #include <plat/clock.h>
18254 @@ -179,7 +179,7 @@ static struct platform_device *rx3715_de
18255         &s3c_device_usb,
18256         &s3c_device_lcd,
18257         &s3c_device_wdt,
18258 -       &s3c_device_i2c,
18259 +       &s3c_device_i2c0,
18260         &s3c_device_iis,
18261         &s3c_device_nand,
18262  };
18263 @@ -203,7 +203,7 @@ static void __init rx3715_init_machine(v
18264  #ifdef CONFIG_PM_H1940
18265         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
18266  #endif
18267 -       s3c2410_pm_init();
18268 +       s3c_pm_init();
18269
18270         s3c24xx_fb_set_platdata(&rx3715_fb_info);
18271         platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
18272 Index: linux-2.6.28/arch/arm/mach-s3c2440/mach-smdk2440.c
18273 ===================================================================
18274 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/mach-smdk2440.c     2008-12-25 00:26:37.000000000 +0100
18275 +++ linux-2.6.28/arch/arm/mach-s3c2440/mach-smdk2440.c  2009-01-02 00:01:56.000000000 +0100
18276 @@ -37,6 +37,7 @@
18277
18278  #include <mach/idle.h>
18279  #include <mach/fb.h>
18280 +#include <plat/iic.h>
18281
18282  #include <plat/s3c2410.h>
18283  #include <plat/s3c2440.h>
18284 @@ -152,7 +153,7 @@ static struct platform_device *smdk2440_
18285         &s3c_device_usb,
18286         &s3c_device_lcd,
18287         &s3c_device_wdt,
18288 -       &s3c_device_i2c,
18289 +       &s3c_device_i2c0,
18290         &s3c_device_iis,
18291  };
18292
18293 @@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void)
18294  static void __init smdk2440_machine_init(void)
18295  {
18296         s3c24xx_fb_set_platdata(&smdk2440_fb_info);
18297 +       s3c_i2c0_set_platdata(NULL);
18298
18299         platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
18300         smdk_machine_init();
18301 Index: linux-2.6.28/arch/arm/mach-s3c2440/Makefile
18302 ===================================================================
18303 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/Makefile    2008-12-25 00:26:37.000000000 +0100
18304 +++ linux-2.6.28/arch/arm/mach-s3c2440/Makefile 2009-01-02 00:01:56.000000000 +0100
18305 @@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_S3C2440)     += s3c2440.o d
18306  obj-$(CONFIG_CPU_S3C2440)      += irq.o
18307  obj-$(CONFIG_CPU_S3C2440)      += clock.o
18308  obj-$(CONFIG_S3C2440_DMA)      += dma.o
18309 +obj-$(CONFIG_S3C2440_C_FIQ)    += fiq_c_isr.o
18310
18311  # Machine support
18312
18313 @@ -22,3 +23,6 @@ obj-$(CONFIG_MACH_RX3715)     += mach-rx3715
18314  obj-$(CONFIG_ARCH_S3C2440)     += mach-smdk2440.o
18315  obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
18316  obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
18317 +obj-$(CONFIG_MACH_HXD8)                += mach-hxd8.o
18318 +obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
18319 +
18320 Index: linux-2.6.28/arch/arm/mach-s3c2440/s3c2440.c
18321 ===================================================================
18322 --- linux-2.6.28.orig/arch/arm/mach-s3c2440/s3c2440.c   2008-12-25 00:26:37.000000000 +0100
18323 +++ linux-2.6.28/arch/arm/mach-s3c2440/s3c2440.c        2009-01-02 00:01:56.000000000 +0100
18324 @@ -46,6 +46,9 @@ int __init s3c2440_init(void)
18325         s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
18326         s3c_device_wdt.resource[1].end   = IRQ_S3C2440_WDT;
18327
18328 +       /* make sure SD/MMC driver can distinguish 2440 from 2410 */
18329 +       s3c_device_sdi.name = "s3c2440-sdi";
18330 +
18331         /* register our system device for everything else */
18332
18333         return sysdev_register(&s3c2440_sysdev);
18334 Index: linux-2.6.28/arch/arm/mach-s3c2442/Kconfig
18335 ===================================================================
18336 --- linux-2.6.28.orig/arch/arm/mach-s3c2442/Kconfig     2008-12-25 00:26:37.000000000 +0100
18337 +++ linux-2.6.28/arch/arm/mach-s3c2442/Kconfig  2009-01-02 00:01:56.000000000 +0100
18338 @@ -6,10 +6,11 @@
18339
18340  config CPU_S3C2442
18341         bool
18342 -       depends on ARCH_S3C2410
18343 +       depends on CPU_S3C2440
18344         select S3C2410_CLOCK
18345         select S3C2410_GPIO
18346         select S3C2410_PM if PM
18347 +       select S3C2440_DMA if S3C2410_DMA
18348         select CPU_S3C244X
18349         select CPU_LLSERIAL_S3C2440
18350         help
18351 Index: linux-2.6.28/arch/arm/mach-s3c2442/s3c2442.c
18352 ===================================================================
18353 --- linux-2.6.28.orig/arch/arm/mach-s3c2442/s3c2442.c   2008-12-25 00:26:37.000000000 +0100
18354 +++ linux-2.6.28/arch/arm/mach-s3c2442/s3c2442.c        2009-01-02 00:01:56.000000000 +0100
18355 @@ -21,6 +21,7 @@
18356
18357  #include <plat/s3c2442.h>
18358  #include <plat/cpu.h>
18359 +#include <plat/devs.h>
18360
18361  static struct sys_device s3c2442_sysdev = {
18362         .cls            = &s3c2442_sysclass,
18363 @@ -30,5 +31,8 @@ int __init s3c2442_init(void)
18364  {
18365         printk("S3C2442: Initialising architecture\n");
18366
18367 +       /* make sure SD/MMC driver can distinguish 2440 from 2410 */
18368 +       s3c_device_sdi.name = "s3c2440-sdi";
18369 +
18370         return sysdev_register(&s3c2442_sysdev);
18371  }
18372 Index: linux-2.6.28/arch/arm/mach-s3c2443/clock.c
18373 ===================================================================
18374 --- linux-2.6.28.orig/arch/arm/mach-s3c2443/clock.c     2008-12-25 00:26:37.000000000 +0100
18375 +++ linux-2.6.28/arch/arm/mach-s3c2443/clock.c  2009-01-02 00:01:56.000000000 +0100
18376 @@ -39,6 +39,8 @@
18377
18378  #include <mach/regs-s3c2443-clock.h>
18379
18380 +#include <plat/cpu-freq.h>
18381 +
18382  #include <plat/s3c2443.h>
18383  #include <plat/clock.h>
18384  #include <plat/cpu.h>
18385 @@ -145,12 +147,6 @@ static unsigned long s3c2443_roundrate_c
18386
18387  /* clock selections */
18388
18389 -/* CPU EXTCLK input */
18390 -static struct clk clk_ext = {
18391 -       .name           = "ext",
18392 -       .id             = -1,
18393 -};
18394 -
18395  static struct clk clk_mpllref = {
18396         .name           = "mpllref",
18397         .parent         = &clk_xtal,
18398 @@ -165,14 +161,6 @@ static struct clk clk_mpll = {
18399  };
18400  #endif
18401
18402 -static struct clk clk_epllref;
18403 -
18404 -static struct clk clk_epll = {
18405 -       .name           = "epll",
18406 -       .parent         = &clk_epllref,
18407 -       .id             = -1,
18408 -};
18409 -
18410  static struct clk clk_i2s_ext = {
18411         .name           = "i2s-ext",
18412         .id             = -1,
18413 @@ -1011,22 +999,20 @@ static struct clk *clks[] __initdata = {
18414         &clk_prediv,
18415  };
18416
18417 -void __init s3c2443_init_clocks(int xtal)
18418 +void __init_or_cpufreq s3c2443_setup_clocks(void)
18419  {
18420 -       unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
18421         unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
18422         unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
18423 +       struct clk *xtal_clk;
18424 +       unsigned long xtal;
18425         unsigned long pll;
18426         unsigned long fclk;
18427         unsigned long hclk;
18428         unsigned long pclk;
18429 -       struct clk *clkp;
18430 -       int ret;
18431 -       int ptr;
18432
18433 -       /* s3c2443 parents h and p clocks from prediv */
18434 -       clk_h.parent = &clk_prediv;
18435 -       clk_p.parent = &clk_prediv;
18436 +       xtal_clk = clk_get(NULL, "xtal");
18437 +       xtal = clk_get_rate(xtal_clk);
18438 +       clk_put(xtal_clk);
18439
18440         pll = s3c2443_get_mpll(mpllcon, xtal);
18441         clk_msysclk.rate = pll;
18442 @@ -1036,13 +1022,29 @@ void __init s3c2443_init_clocks(int xtal
18443         hclk /= s3c2443_get_hdiv(clkdiv0);
18444         pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
18445
18446 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
18447 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
18448
18449         printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
18450                (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
18451                print_mhz(pll), print_mhz(fclk),
18452                print_mhz(hclk), print_mhz(pclk));
18453
18454 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
18455 +}
18456 +
18457 +void __init s3c2443_init_clocks(int xtal)
18458 +{
18459 +       struct clk *clkp;
18460 +       unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
18461 +       int ret;
18462 +       int ptr;
18463 +
18464 +       /* s3c2443 parents h and p clocks from prediv */
18465 +       clk_h.parent = &clk_prediv;
18466 +       clk_p.parent = &clk_prediv;
18467 +
18468 +       s3c24xx_register_baseclocks(xtal);
18469 +       s3c2443_setup_clocks();
18470         s3c2443_clk_initparents();
18471
18472         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
18473 @@ -1056,7 +1058,7 @@ void __init s3c2443_init_clocks(int xtal
18474         }
18475
18476         clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
18477 -
18478 +       clk_epll.parent = &clk_epllref;
18479         clk_usb_bus.parent = &clk_usb_bus_host;
18480
18481         /* ensure usb bus clock is within correct rate of 48MHz */
18482 @@ -1105,4 +1107,6 @@ void __init s3c2443_init_clocks(int xtal
18483
18484                 (clkp->enable)(clkp, 0);
18485         }
18486 +
18487 +       s3c_pwmclk_init();
18488  }
18489 Index: linux-2.6.28/arch/arm/mach-s3c2443/dma.c
18490 ===================================================================
18491 --- linux-2.6.28.orig/arch/arm/mach-s3c2443/dma.c       2008-12-25 00:26:37.000000000 +0100
18492 +++ linux-2.6.28/arch/arm/mach-s3c2443/dma.c    2009-01-02 00:01:56.000000000 +0100
18493 @@ -26,12 +26,12 @@
18494
18495  #include <plat/regs-serial.h>
18496  #include <mach/regs-gpio.h>
18497 -#include <asm/plat-s3c/regs-ac97.h>
18498 +#include <plat/regs-ac97.h>
18499  #include <mach/regs-mem.h>
18500  #include <mach/regs-lcd.h>
18501  #include <mach/regs-sdi.h>
18502  #include <asm/plat-s3c24xx/regs-iis.h>
18503 -#include <asm/plat-s3c24xx/regs-spi.h>
18504 +#include <plat/regs-spi.h>
18505
18506  #define MAP(x) { \
18507                 [0]     = (x) | DMA_CH_VALID,   \
18508 Index: linux-2.6.28/arch/arm/mach-s3c2443/Kconfig
18509 ===================================================================
18510 --- linux-2.6.28.orig/arch/arm/mach-s3c2443/Kconfig     2008-12-25 00:26:37.000000000 +0100
18511 +++ linux-2.6.28/arch/arm/mach-s3c2443/Kconfig  2009-01-02 00:01:56.000000000 +0100
18512 @@ -24,6 +24,7 @@ config MACH_SMDK2443
18513         bool "SMDK2443"
18514         select CPU_S3C2443
18515         select MACH_SMDK
18516 +       select S3C_DEV_HSMMC
18517         help
18518           Say Y here if you are using an SMDK2443
18519
18520 Index: linux-2.6.28/arch/arm/mach-s3c2443/mach-smdk2443.c
18521 ===================================================================
18522 --- linux-2.6.28.orig/arch/arm/mach-s3c2443/mach-smdk2443.c     2008-12-25 00:26:37.000000000 +0100
18523 +++ linux-2.6.28/arch/arm/mach-s3c2443/mach-smdk2443.c  2009-01-02 00:01:56.000000000 +0100
18524 @@ -37,6 +37,7 @@
18525
18526  #include <mach/idle.h>
18527  #include <mach/fb.h>
18528 +#include <plat/iic.h>
18529
18530  #include <plat/s3c2410.h>
18531  #include <plat/s3c2440.h>
18532 @@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_u
18533
18534  static struct platform_device *smdk2443_devices[] __initdata = {
18535         &s3c_device_wdt,
18536 -       &s3c_device_i2c,
18537 -       &s3c_device_hsmmc,
18538 +       &s3c_device_i2c0,
18539 +       &s3c_device_hsmmc0,
18540  };
18541
18542  static void __init smdk2443_map_io(void)
18543 @@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void)
18544
18545  static void __init smdk2443_machine_init(void)
18546  {
18547 +       s3c_i2c0_set_platdata(NULL);
18548         platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
18549         smdk_machine_init();
18550  }
18551 Index: linux-2.6.28/arch/arm/mach-s3c2443/s3c2443.c
18552 ===================================================================
18553 --- linux-2.6.28.orig/arch/arm/mach-s3c2443/s3c2443.c   2008-12-25 00:26:37.000000000 +0100
18554 +++ linux-2.6.28/arch/arm/mach-s3c2443/s3c2443.c        2009-01-02 00:01:56.000000000 +0100
18555 @@ -81,10 +81,9 @@ void __init s3c2443_init_uarts(struct s3
18556   * machine specific initialisation.
18557   */
18558
18559 -void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size)
18560 +void __init s3c2443_map_io(void)
18561  {
18562         iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
18563 -       iotable_init(mach_desc, mach_size);
18564  }
18565
18566  /* need to register class before we actually register the device, and
18567 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
18568 ===================================================================
18569 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18570 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/debug-macro.S       2009-01-02 00:01:56.000000000 +0100
18571 @@ -0,0 +1,28 @@
18572 +/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
18573 + *
18574 + * This program is free software; you can redistribute it and/or modify
18575 + * it under the terms of the GNU General Public License version 2 as
18576 + * published by the Free Software Foundation.
18577 +*/
18578 +
18579 +/* pull in the relevant register and map files. */
18580 +
18581 +#include <mach/map.h>
18582 +#include <plat/regs-serial.h>
18583 +
18584 +       .macro addruart, rx
18585 +               mrc     p15, 0, \rx, c1, c0
18586 +               tst     \rx, #1
18587 +               ldreq   \rx, = S3C24XX_PA_UART
18588 +               ldrne   \rx, = S3C24XX_VA_UART
18589 +#if CONFIG_DEBUG_S3C_UART != 0
18590 +               add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
18591 +#endif
18592 +       .endm
18593 +
18594 +/* include the reset of the code which will do the work, we're only
18595 + * compiling for a single cpu processor type so the default of s3c2440
18596 + * will be fine with us.
18597 + */
18598 +
18599 +#include <plat/debug-macro.S>
18600 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/io.h
18601 ===================================================================
18602 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18603 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/io.h        2009-01-02 00:01:56.000000000 +0100
18604 @@ -0,0 +1,16 @@
18605 +/* arch/arm/mach-s3c24a0/include/mach/io.h
18606 + *
18607 + * Copyright 2008 Simtec Electronics
18608 + *     Ben Dooks <ben-linux@fluff.org>
18609 + *
18610 + * IO access and mapping routines for the S3C24A0
18611 + */
18612 +
18613 +#ifndef __ASM_ARM_ARCH_IO_H
18614 +#define __ASM_ARM_ARCH_IO_H
18615 +
18616 +/* No current ISA/PCI bus support. */
18617 +#define __io(a)                ((void __iomem *)(a))
18618 +#define __mem_pci(a)   (a)
18619 +
18620 +#endif
18621 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/irqs.h
18622 ===================================================================
18623 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18624 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/irqs.h      2009-01-02 00:01:56.000000000 +0100
18625 @@ -0,0 +1,117 @@
18626 +/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
18627 + *
18628 + * Copyright (c) 2003-2005 Simtec Electronics
18629 + *   Ben Dooks <ben@simtec.co.uk>
18630 + *
18631 + * This program is free software; you can redistribute it and/or modify
18632 + * it under the terms of the GNU General Public License version 2 as
18633 + * published by the Free Software Foundation.
18634 +*/
18635 +
18636 +
18637 +#ifndef __ASM_ARCH_24A0_IRQS_H
18638 +#define __ASM_ARCH_24A0_IRQS_H __FILE__
18639 +
18640 +#define IRQ_EINT0t2    S3C2410_IRQ(0)  /* 16 */
18641 +/* for generic entry-macro.S */
18642 +#define IRQ_EINT0      IRQ_EINT0t2
18643 +
18644 +#define IRQ_EINT3t6    S3C2410_IRQ(1)
18645 +#define IRQ_EINT7t10   S3C2410_IRQ(2)
18646 +#define IRQ_EINT11t14  S3C2410_IRQ(3)
18647 +#define IRQ_EINT15t18  S3C2410_IRQ(4)  /* 20 */
18648 +#define IRQ_TICK       S3C2410_IRQ(5)
18649 +#define IRQ_DCTQ       S3C2410_IRQ(6)
18650 +#define IRQ_MC         S3C2410_IRQ(7)
18651 +#define IRQ_ME         S3C2410_IRQ(8)  /* 24 */
18652 +#define IRQ_KEYPAD     S3C2410_IRQ(9)
18653 +#define IRQ_TIMER0     S3C2410_IRQ(10)
18654 +#define IRQ_TIMER1     S3C2410_IRQ(11)
18655 +#define IRQ_TIMER2     S3C2410_IRQ(12)
18656 +#define IRQ_TIMER3_4   S3C2410_IRQ(13)
18657 +#define IRQ_OS_TIMER   IRQ_TIMER3_4
18658 +#define IRQ_LCD                S3C2410_IRQ(14)
18659 +#define IRQ_CAM_C      S3C2410_IRQ(15)
18660 +#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
18661 +#define IRQ_UART0      S3C2410_IRQ(17)
18662 +#define IRQ_CAM_P      S3C2410_IRQ(18)
18663 +#define IRQ_MODEM      S3C2410_IRQ(19)
18664 +#define IRQ_DMA                S3C2410_IRQ(20)
18665 +#define IRQ_SDI                S3C2410_IRQ(21)
18666 +#define IRQ_SPI0       S3C2410_IRQ(22)
18667 +#define IRQ_UART1      S3C2410_IRQ(23)
18668 +#define IRQ_AC97_NFLASH        S3C2410_IRQ(24) /* 40 */
18669 +#define IRQ_USBD       S3C2410_IRQ(25)
18670 +#define IRQ_USBH       S3C2410_IRQ(26)
18671 +#define IRQ_IIC                S3C2410_IRQ(27)
18672 +#define IRQ_IRDA_MSTICK        S3C2410_IRQ(28) /* 44 */
18673 +#define IRQ_VLX_SPI1   S3C2410_IRQ(29)
18674 +#define IRQ_RTC                S3C2410_IRQ(30) /* 46 */
18675 +#define IRQ_ADC_PEN     S3C2410_IRQ(31)
18676 +
18677 +/* interrupts generated from the external interrupts sources */
18678 +#define IRQ_EINT00     S3C2410_IRQ(32) /* 48 */
18679 +#define IRQ_EINT1      S3C2410_IRQ(33)
18680 +#define IRQ_EINT2      S3C2410_IRQ(34)
18681 +#define IRQ_EINT3      S3C2410_IRQ(35)
18682 +#define IRQ_EINT4      S3C2410_IRQ(36)
18683 +#define IRQ_EINT5      S3C2410_IRQ(37)
18684 +#define IRQ_EINT6      S3C2410_IRQ(38)
18685 +#define IRQ_EINT7      S3C2410_IRQ(39)
18686 +#define IRQ_EINT8      S3C2410_IRQ(40)
18687 +#define IRQ_EINT9      S3C2410_IRQ(41)
18688 +#define IRQ_EINT10     S3C2410_IRQ(42)
18689 +#define IRQ_EINT11     S3C2410_IRQ(43)
18690 +#define IRQ_EINT12     S3C2410_IRQ(44)
18691 +#define IRQ_EINT13     S3C2410_IRQ(45)
18692 +#define IRQ_EINT14     S3C2410_IRQ(46)
18693 +#define IRQ_EINT15     S3C2410_IRQ(47)
18694 +#define IRQ_EINT16     S3C2410_IRQ(48)
18695 +#define IRQ_EINT17     S3C2410_IRQ(49)
18696 +#define IRQ_EINT18     S3C2410_IRQ(50)
18697 +
18698 +#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00)
18699 +
18700 +/* SUB IRQS */
18701 +#define IRQ_S3CUART_RX0                S3C2410_IRQ(51) /* 67 */
18702 +#define IRQ_S3CUART_TX0                S3C2410_IRQ(52)
18703 +#define IRQ_S3CUART_ERR0       S3C2410_IRQ(53)
18704 +
18705 +#define IRQ_S3CUART_RX1                S3C2410_IRQ(54)
18706 +#define IRQ_S3CUART_TX1                S3C2410_IRQ(55)
18707 +#define IRQ_S3CUART_ERR1       S3C2410_IRQ(56)
18708 +
18709 +#define IRQ_S3CUART_RX2                (0x0)
18710 +#define IRQ_S3CUART_TX2                (0x0)
18711 +#define IRQ_S3CUART_ERR2       (0x0)
18712 +
18713 +
18714 +#define IRQ_IRDA       S3C2410_IRQ(57)
18715 +#define IRQ_MSTICK     S3C2410_IRQ(58)
18716 +#define IRQ_RESERVED0  S3C2410_IRQ(59)
18717 +#define IRQ_RESERVED1  S3C2410_IRQ(60)
18718 +#define IRQ_RESERVED2  S3C2410_IRQ(61)
18719 +#define IRQ_TIMER3     S3C2410_IRQ(62)
18720 +#define IRQ_TIMER4     S3C2410_IRQ(63)
18721 +#define IRQ_WDT                S3C2410_IRQ(64)
18722 +#define IRQ_BATFLT     S3C2410_IRQ(65)
18723 +#define IRQ_POST       S3C2410_IRQ(66)
18724 +#define IRQ_DISP_FIFO  S3C2410_IRQ(67)
18725 +#define IRQ_PENUP      S3C2410_IRQ(68)
18726 +#define IRQ_PENDN      S3C2410_IRQ(69)
18727 +#define IRQ_ADC                S3C2410_IRQ(70)
18728 +#define IRQ_DISP_FRAME S3C2410_IRQ(71)
18729 +#define IRQ_NFLASH     S3C2410_IRQ(72)
18730 +#define IRQ_AC97       S3C2410_IRQ(73)
18731 +#define IRQ_SPI1       S3C2410_IRQ(74)
18732 +#define IRQ_VLX                S3C2410_IRQ(75)
18733 +#define IRQ_DMA0       S3C2410_IRQ(76)
18734 +#define IRQ_DMA1       S3C2410_IRQ(77)
18735 +#define IRQ_DMA2       S3C2410_IRQ(78)
18736 +#define IRQ_DMA3       S3C2410_IRQ(79)
18737 +
18738 +#define IRQ_TC         (0x0)
18739 +
18740 +#define NR_IRQS                (IRQ_DMA3+1)
18741 +
18742 +#endif /* __ASM_ARCH_24A0_IRQS_H */
18743 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/map.h
18744 ===================================================================
18745 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18746 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/map.h       2009-01-02 00:01:56.000000000 +0100
18747 @@ -0,0 +1,85 @@
18748 +/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
18749 + *
18750 + * Copyright 2003,2007  Simtec Electronics
18751 + *     http://armlinux.simtec.co.uk/
18752 + *     Ben Dooks <ben@simtec.co.uk>
18753 + *
18754 + * S3C24A0 - Memory map definitions
18755 + *
18756 + * This program is free software; you can redistribute it and/or modify
18757 + * it under the terms of the GNU General Public License version 2 as
18758 + * published by the Free Software Foundation.
18759 +*/
18760 +
18761 +#ifndef __ASM_ARCH_24A0_MAP_H
18762 +#define __ASM_ARCH_24A0_MAP_H __FILE__
18763 +
18764 +#include <plat/map-base.h>
18765 +#include <plat/map.h>
18766 +
18767 +#define S3C24A0_PA_IO_BASE     (0x40000000)
18768 +#define S3C24A0_PA_CLKPWR      (0x40000000)
18769 +#define S3C24A0_PA_IRQ         (0x40200000)
18770 +#define S3C24A0_PA_DMA         (0x40400000)
18771 +#define S3C24A0_PA_MEMCTRL     (0x40C00000)
18772 +#define S3C24A0_PA_NAND                (0x40C00000)
18773 +#define S3C24A0_PA_SROM                (0x40C20000)
18774 +#define S3C24A0_PA_SDRAM       (0x40C40000)
18775 +#define S3C24A0_PA_BUSM                (0x40CE0000)
18776 +#define S3C24A0_PA_USBHOST     (0x41000000)
18777 +#define S3C24A0_PA_MODEMIF     (0x41180000)
18778 +#define S3C24A0_PA_IRDA                (0x41800000)
18779 +#define S3C24A0_PA_TIMER       (0x44000000)
18780 +#define S3C24A0_PA_WATCHDOG    (0x44100000)
18781 +#define S3C24A0_PA_RTC         (0x44200000)
18782 +#define S3C24A0_PA_UART                (0x44400000)
18783 +#define S3C24A0_PA_UART0       (S3C24A0_PA_UART)
18784 +#define S3C24A0_PA_UART1       (S3C24A0_PA_UART + 0x4000)
18785 +#define S3C24A0_PA_SPI         (0x44500000)
18786 +#define S3C24A0_PA_IIC         (0x44600000)
18787 +#define S3C24A0_PA_IIS         (0x44700000)
18788 +#define S3C24A0_PA_GPIO                (0x44800000)
18789 +#define S3C24A0_PA_KEYIF       (0x44900000)
18790 +#define S3C24A0_PA_USBDEV      (0x44A00000)
18791 +#define S3C24A0_PA_AC97                (0x45000000)
18792 +#define S3C24A0_PA_ADC         (0x45800000)
18793 +#define S3C24A0_PA_SDI         (0x46000000)
18794 +#define S3C24A0_PA_MS          (0x46100000)
18795 +#define S3C24A0_PA_LCD         (0x4A000000)
18796 +#define S3C24A0_PA_VPOST       (0x4A100000)
18797 +
18798 +/* physical addresses of all the chip-select areas */
18799 +
18800 +#define S3C24A0_CS0    (0x00000000)
18801 +#define S3C24A0_CS1    (0x04000000)
18802 +#define S3C24A0_CS2    (0x08000000)
18803 +#define S3C24A0_CS3    (0x0C000000)
18804 +#define S3C24A0_CS4    (0x10000000)
18805 +#define S3C24A0_CS5    (0x40000000)
18806 +
18807 +#define S3C24A0_SDRAM_PA       (S3C24A0_CS4)
18808 +
18809 +/* Use a single interface for common resources between S3C24XX cpus */
18810 +
18811 +#define S3C24XX_PA_IRQ         S3C24A0_PA_IRQ
18812 +#define S3C24XX_PA_MEMCTRL     S3C24A0_PA_MEMCTRL
18813 +#define S3C24XX_PA_USBHOST     S3C24A0_PA_USBHOST
18814 +#define S3C24XX_PA_DMA         S3C24A0_PA_DMA
18815 +#define S3C24XX_PA_CLKPWR      S3C24A0_PA_CLKPWR
18816 +#define S3C24XX_PA_LCD         S3C24A0_PA_LCD
18817 +#define S3C24XX_PA_UART                S3C24A0_PA_UART
18818 +#define S3C24XX_PA_TIMER       S3C24A0_PA_TIMER
18819 +#define S3C24XX_PA_USBDEV      S3C24A0_PA_USBDEV
18820 +#define S3C24XX_PA_WATCHDOG    S3C24A0_PA_WATCHDOG
18821 +#define S3C24XX_PA_IIS         S3C24A0_PA_IIS
18822 +#define S3C24XX_PA_GPIO                S3C24A0_PA_GPIO
18823 +#define S3C24XX_PA_RTC         S3C24A0_PA_RTC
18824 +#define S3C24XX_PA_ADC         S3C24A0_PA_ADC
18825 +#define S3C24XX_PA_SPI         S3C24A0_PA_SPI
18826 +#define S3C24XX_PA_SDI         S3C24A0_PA_SDI
18827 +#define S3C24XX_PA_NAND                S3C24A0_PA_NAND
18828 +
18829 +#define S3C_PA_UART            S3C24A0_PA_UART
18830 +#define S3C_PA_IIC             S3C24A0_PA_IIC
18831 +
18832 +#endif /* __ASM_ARCH_24A0_MAP_H */
18833 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/memory.h
18834 ===================================================================
18835 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18836 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/memory.h    2009-01-02 00:01:56.000000000 +0100
18837 @@ -0,0 +1,19 @@
18838 +/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
18839 + *  from linux/include/asm-arm/arch-rpc/memory.h
18840 + *
18841 + *  Copyright (C) 1996,1997,1998 Russell King.
18842 + *
18843 + * This program is free software; you can redistribute it and/or modify
18844 + * it under the terms of the GNU General Public License version 2 as
18845 + * published by the Free Software Foundation.
18846 +*/
18847 +
18848 +#ifndef __ASM_ARCH_24A0_MEMORY_H
18849 +#define __ASM_ARCH_24A0_MEMORY_H __FILE__
18850 +
18851 +#define PHYS_OFFSET UL(0x10000000)
18852 +
18853 +#define __virt_to_bus(x) __virt_to_phys(x)
18854 +#define __bus_to_virt(x) __phys_to_virt(x)
18855 +
18856 +#endif
18857 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
18858 ===================================================================
18859 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18860 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-clock.h        2009-01-02 00:01:56.000000000 +0100
18861 @@ -0,0 +1,88 @@
18862 +/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
18863 + *
18864 + * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
18865 + *                   http://armlinux.simtec.co.uk/
18866 + *
18867 + * This program is free software; you can redistribute it and/or modify
18868 + * it under the terms of the GNU General Public License version 2 as
18869 + * published by the Free Software Foundation.
18870 + *
18871 + * S3C24A0 clock register definitions
18872 +*/
18873 +
18874 +#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
18875 +#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
18876 +
18877 +#define S3C24A0_MPLLCON                S3C2410_CLKREG(0x10)
18878 +#define S3C24A0_UPLLCON                S3C2410_CLKREG(0x14)
18879 +#define S3C24A0_CLKCON         S3C2410_CLKREG(0x20)
18880 +#define S3C24A0_CLKSRC         S3C2410_CLKREG(0x24)
18881 +#define S3C24A0_CLKDIVN                S3C2410_CLKREG(0x28)
18882 +
18883 +/* CLKCON register bits */
18884 +
18885 +#define S3C24A0_CLKCON_VLX     (1<<29)
18886 +#define S3C24A0_CLKCON_VPOST   (1<<28)
18887 +#define S3C24A0_CLKCON_WDT     (1<<27) /* reserved */
18888 +#define S3C24A0_CLKCON_MPEGDCTQ        (1<<26)
18889 +#define S3C24A0_CLKCON_VPOSTIF (1<<25)
18890 +#define S3C24A0_CLKCON_MPEG4IF (1<<24)
18891 +#define S3C24A0_CLKCON_CAM_UPLL        (1<<23)
18892 +#define S3C24A0_CLKCON_LCDC    (1<<22)
18893 +#define S3C24A0_CLKCON_CAM_HCLK        (1<<21)
18894 +#define S3C24A0_CLKCON_MPEG4   (1<<20)
18895 +#define S3C24A0_CLKCON_KEYPAD  (1<<19)
18896 +#define S3C24A0_CLKCON_ADC     (1<<18)
18897 +#define S3C24A0_CLKCON_SDI     (1<<17)
18898 +#define S3C24A0_CLKCON_MS      (1<<16) /* memory stick */
18899 +#define S3C24A0_CLKCON_USBD    (1<<15)
18900 +#define S3C24A0_CLKCON_GPIO    (1<<14)
18901 +#define S3C24A0_CLKCON_IIS     (1<<13)
18902 +#define S3C24A0_CLKCON_IIC     (1<<12)
18903 +#define S3C24A0_CLKCON_SPI     (1<<11)
18904 +#define S3C24A0_CLKCON_UART1   (1<<10)
18905 +#define S3C24A0_CLKCON_UART0   (1<<9)
18906 +#define S3C24A0_CLKCON_PWMT    (1<<8)
18907 +#define S3C24A0_CLKCON_USBH    (1<<7)
18908 +#define S3C24A0_CLKCON_AC97    (1<<6)
18909 +#define S3C24A0_CLKCON_IrDA    (1<<4)
18910 +#define S3C24A0_CLKCON_IDLE    (1<<2)
18911 +#define S3C24A0_CLKCON_MON     (1<<1)
18912 +#define S3C24A0_CLKCON_STOP    (1<<0)
18913 +
18914 +/* CLKSRC register bits */
18915 +
18916 +#define S3C24A0_CLKSRC_OSC     (1<<8)  /* CLKSRC */
18917 +#define S3C24A0_CLKSRC_UPLL    (1<<7)
18918 +#define S3C24A0_CLKSRC_MPLL    (1<<5)
18919 +#define S3C24A0_CLKSRC_EXT     (1<<4)
18920 +
18921 +/* Use a single interface with the common code, for s3c24xx */
18922 +
18923 +#define S3C2410_MPLLCON                S3C24A0_MPLLCON
18924 +#define S3C2410_UPLLCON                S3C24A0_UPLLCON
18925 +#define S3C2410_CLKCON         S3C24A0_CLKCON
18926 +#define S3C2410_CLKSLOW                S3C24A0_CLKSRC
18927 +#define S3C2410_CLKDIVN                S3C24A0_CLKDIVN
18928 +
18929 +#define S3C2410_CLKCON_IDLE    S3C24A0_CLKCON_IDLE
18930 +#define S3C2410_CLKCON_POWER   S3C24A0_CLKCON_STOP
18931 +#define S3C2410_CLKCON_LCDC    S3C24A0_CLKCON_LCDC
18932 +#define S3C2410_CLKCON_USBH    S3C24A0_CLKCON_USBH
18933 +#define S3C2410_CLKCON_USBD    S3C24A0_CLKCON_USBD
18934 +#define S3C2410_CLKCON_PWMT    S3C24A0_CLKCON_PWMT
18935 +#define S3C2410_CLKCON_SDI     S3C24A0_CLKCON_SDI
18936 +#define S3C2410_CLKCON_UART0   S3C24A0_CLKCON_UART0
18937 +#define S3C2410_CLKCON_UART1   S3C24A0_CLKCON_UART1
18938 +#define S3C2410_CLKCON_GPIO    S3C24A0_CLKCON_GPIO
18939 +#define S3C2410_CLKCON_ADC     S3C24A0_CLKCON_ADC
18940 +#define S3C2410_CLKCON_IIC     S3C24A0_CLKCON_IIC
18941 +#define S3C2410_CLKCON_IIS     S3C24A0_CLKCON_IIS
18942 +#define S3C2410_CLKCON_SPI     S3C24A0_CLKCON_SPI
18943 +
18944 +#define S3C2410_CLKSLOW_UCLK_OFF       S3C24A0_CLKSRC_UPLL
18945 +#define S3C2410_CLKSLOW_MPLL_OFF       S3C24A0_CLKSRC_MPLL
18946 +#define S3C2410_CLKSLOW_SLOW           (0xFF)
18947 +#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
18948 +
18949 +#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
18950 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
18951 ===================================================================
18952 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18953 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-irq.h  2009-01-02 00:01:56.000000000 +0100
18954 @@ -0,0 +1,25 @@
18955 +/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
18956 + *
18957 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
18958 + *                   http://www.simtec.co.uk/products/SWLINUX/
18959 + *
18960 + * This program is free software; you can redistribute it and/or modify
18961 + * it under the terms of the GNU General Public License version 2 as
18962 + * published by the Free Software Foundation.
18963 +*/
18964 +
18965 +
18966 +#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
18967 +#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
18968 +
18969 +
18970 +#define S3C2410_EINTMASK       S3C2410_EINTREG(0x034)
18971 +#define S3C2410_EINTPEND       S3C2410_EINTREG(0X038)
18972 +
18973 +#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x034)
18974 +#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X038)
18975 +
18976 +#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
18977 +
18978 +
18979 +
18980 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/system.h
18981 ===================================================================
18982 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
18983 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/system.h    2009-01-02 00:01:56.000000000 +0100
18984 @@ -0,0 +1,25 @@
18985 +/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
18986 + *
18987 + * Copyright 2008 Simtec Electronics
18988 + *     Ben Dooks <ben@simtec.co.uk>
18989 + *
18990 + * S3C24A0 - System function defines and includes
18991 + *
18992 + * This program is free software; you can redistribute it and/or modify
18993 + * it under the terms of the GNU General Public License version 2 as
18994 + * published by the Free Software Foundation.
18995 +*/
18996 +
18997 +#include <mach/hardware.h>
18998 +#include <asm/io.h>
18999 +
19000 +#include <mach/map.h>
19001 +
19002 +static void arch_idle(void)
19003 +{
19004 +       /* currently no specific idle support. */
19005 +}
19006 +
19007 +void (*s3c24xx_reset_hook)(void);
19008 +
19009 +#include <asm/plat-s3c24xx/system-reset.h>
19010 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/tick.h
19011 ===================================================================
19012 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19013 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/tick.h      2009-01-02 00:01:56.000000000 +0100
19014 @@ -0,0 +1,15 @@
19015 +/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
19016 + *
19017 + * Copyright 2008 Simtec Electronics
19018 + *      Ben Dooks <ben@simtec.co.uk>
19019 + *      http://armlinux.simtec.co.uk/
19020 + *
19021 + * S3C24A0 - timer tick support
19022 + */
19023 +
19024 +#define SUBSRC_TIMER4  (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
19025 +
19026 +static inline int s3c24xx_ostimer_pending(void)
19027 +{
19028 +       return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
19029 +}
19030 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/timex.h
19031 ===================================================================
19032 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19033 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/timex.h     2009-01-02 00:01:56.000000000 +0100
19034 @@ -0,0 +1,18 @@
19035 +/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
19036 + *
19037 + * Copyright (c) 2008 Simtec Electronics
19038 + *     Ben Dooks <ben@simtec.co.uk>
19039 + *
19040 + * S3C2410 - time parameters
19041 + *
19042 + * This program is free software; you can redistribute it and/or modify
19043 + * it under the terms of the GNU General Public License version 2 as
19044 + * published by the Free Software Foundation.
19045 +*/
19046 +
19047 +#ifndef __ASM_ARCH_TIMEX_H
19048 +#define __ASM_ARCH_TIMEX_H
19049 +
19050 +#define CLOCK_TICK_RATE 12000000
19051 +
19052 +#endif /* __ASM_ARCH_TIMEX_H */
19053 Index: linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
19054 ===================================================================
19055 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19056 +++ linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/vmalloc.h   2009-01-02 00:01:56.000000000 +0100
19057 @@ -0,0 +1,17 @@
19058 +/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
19059 + *
19060 + * Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
19061 +
19062 + * This program is free software; you can redistribute it and/or modify
19063 + * it under the terms of the GNU General Public License version 2 as
19064 + * published by the Free Software Foundation.
19065 + *
19066 + * S3C24A0 vmalloc definition
19067 +*/
19068 +
19069 +#ifndef __ASM_ARCH_VMALLOC_H
19070 +#define __ASM_ARCH_VMALLOC_H
19071 +
19072 +#define VMALLOC_END      (0xE0000000)
19073 +
19074 +#endif /* __ASM_ARCH_VMALLOC_H */
19075 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/debug-macro.S
19076 ===================================================================
19077 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19078 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/debug-macro.S       2009-01-02 00:01:56.000000000 +0100
19079 @@ -0,0 +1,39 @@
19080 +/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
19081 + *
19082 + * Copyright 2008 Openmoko, Inc.
19083 + * Copyright 2008 Simtec Electronics
19084 + *     http://armlinux.simtec.co.uk/
19085 + *     Ben Dooks <ben@simtec.co.uk>
19086 + *
19087 + * This program is free software; you can redistribute it and/or modify
19088 + * it under the terms of the GNU General Public License version 2 as
19089 + * published by the Free Software Foundation.
19090 +*/
19091 +
19092 +/* pull in the relevant register and map files. */
19093 +
19094 +#include <mach/map.h>
19095 +#include <plat/regs-serial.h>
19096 +
19097 +       /* note, for the boot process to work we have to keep the UART
19098 +        * virtual address aligned to an 1MiB boundary for the L1
19099 +        * mapping the head code makes. We keep the UART virtual address
19100 +        * aligned and add in the offset when we load the value here.
19101 +        */
19102 +
19103 +       .macro addruart, rx
19104 +               mrc     p15, 0, \rx, c1, c0
19105 +               tst     \rx, #1
19106 +               ldreq   \rx, = S3C_PA_UART
19107 +               ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
19108 +#if CONFIG_DEBUG_S3C_UART != 0
19109 +               add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
19110 +#endif
19111 +       .endm
19112 +
19113 +/* include the reset of the code which will do the work, we're only
19114 + * compiling for a single cpu processor type so the default of s3c2440
19115 + * will be fine with us.
19116 + */
19117 +
19118 +#include <plat/debug-macro.S>
19119 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/dma.h
19120 ===================================================================
19121 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19122 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/dma.h       2009-01-02 00:01:56.000000000 +0100
19123 @@ -0,0 +1,16 @@
19124 +/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
19125 + *
19126 + * Copyright 2008 Openmoko, Inc.
19127 + * Copyright 2008 Simtec Electronics
19128 + *      Ben Dooks <ben@simtec.co.uk>
19129 + *      http://armlinux.simtec.co.uk/
19130 + *
19131 + * S3C6400 - DMA support
19132 + */
19133 +
19134 +#ifndef __ASM_ARCH_DMA_H
19135 +#define __ASM_ARCH_DMA_H __FILE__
19136 +
19137 +/* currently nothing here, placeholder */
19138 +
19139 +#endif /* __ASM_ARCH_IRQ_H */
19140 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/entry-macro.S
19141 ===================================================================
19142 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19143 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/entry-macro.S       2009-01-02 00:01:56.000000000 +0100
19144 @@ -0,0 +1,44 @@
19145 +/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
19146 + *
19147 + * Copyright 2008 Openmoko, Inc.
19148 + * Copyright 2008 Simtec Electronics
19149 + *     http://armlinux.simtec.co.uk/
19150 + *     Ben Dooks <ben@simtec.co.uk>
19151 + *
19152 + * Low-level IRQ helper macros for the Samsung S3C64XX series
19153 + *
19154 + * This file is licensed under  the terms of the GNU General Public
19155 + * License version 2. This program is licensed "as is" without any
19156 + * warranty of any kind, whether express or implied.
19157 +*/
19158 +
19159 +#include <asm/hardware/vic.h>
19160 +#include <mach/map.h>
19161 +#include <plat/irqs.h>
19162 +
19163 +       .macro  disable_fiq
19164 +       .endm
19165 +
19166 +       .macro  get_irqnr_preamble, base, tmp
19167 +       ldr     \base, =S3C_VA_VIC0
19168 +       .endm
19169 +
19170 +       .macro  arch_ret_to_user, tmp1, tmp2
19171 +       .endm
19172 +
19173 +       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
19174 +
19175 +       @ check the vic0
19176 +       mov     \irqnr, # S3C_IRQ_OFFSET + 31
19177 +       ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
19178 +       teq     \irqstat, #0
19179 +
19180 +       @ otherwise try vic1
19181 +       addeq   \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
19182 +       addeq   \irqnr, \irqnr, #32
19183 +       ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
19184 +       teqeq   \irqstat, #0
19185 +
19186 +       clzne   \irqstat, \irqstat
19187 +       subne   \irqnr, \irqnr, \irqstat
19188 +       .endm
19189 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio-core.h
19190 ===================================================================
19191 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19192 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio-core.h 2009-01-02 00:01:56.000000000 +0100
19193 @@ -0,0 +1,21 @@
19194 +/* arch/arm/mach-s3c6400/include/mach/gpio-core.h
19195 + *
19196 + * Copyright 2008 Openmoko, Inc.
19197 + * Copyright 2008 Simtec Electronics
19198 + *      Ben Dooks <ben@simtec.co.uk>
19199 + *      http://armlinux.simtec.co.uk/
19200 + *
19201 + * S3C64XX - GPIO core support
19202 + *
19203 + * This program is free software; you can redistribute it and/or modify
19204 + * it under the terms of the GNU General Public License version 2 as
19205 + * published by the Free Software Foundation.
19206 +*/
19207 +
19208 +#ifndef __ASM_ARCH_GPIO_CORE_H
19209 +#define __ASM_ARCH_GPIO_CORE_H __FILE__
19210 +
19211 +/* currently we just include the platform support */
19212 +#include <plat/gpio-core.h>
19213 +
19214 +#endif /* __ASM_ARCH_GPIO_CORE_H */
19215 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio.h
19216 ===================================================================
19217 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19218 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio.h      2009-01-02 00:01:56.000000000 +0100
19219 @@ -0,0 +1,96 @@
19220 +/* arch/arm/mach-s3c6400/include/mach/gpio.h
19221 + *
19222 + * Copyright 2008 Openmoko, Inc.
19223 + * Copyright 2008 Simtec Electronics
19224 + *     http://armlinux.simtec.co.uk/
19225 + *     Ben Dooks <ben@simtec.co.uk>
19226 + *
19227 + * S3C6400 - GPIO lib support
19228 + *
19229 + * This program is free software; you can redistribute it and/or modify
19230 + * it under the terms of the GNU General Public License version 2 as
19231 + * published by the Free Software Foundation.
19232 +*/
19233 +
19234 +#define gpio_get_value __gpio_get_value
19235 +#define gpio_set_value __gpio_set_value
19236 +#define gpio_cansleep  __gpio_cansleep
19237 +#define gpio_to_irq    __gpio_to_irq
19238 +
19239 +/* GPIO bank sizes */
19240 +#define S3C64XX_GPIO_A_NR      (8)
19241 +#define S3C64XX_GPIO_B_NR      (7)
19242 +#define S3C64XX_GPIO_C_NR      (8)
19243 +#define S3C64XX_GPIO_D_NR      (5)
19244 +#define S3C64XX_GPIO_E_NR      (5)
19245 +#define S3C64XX_GPIO_F_NR      (16)
19246 +#define S3C64XX_GPIO_G_NR      (7)
19247 +#define S3C64XX_GPIO_H_NR      (10)
19248 +#define S3C64XX_GPIO_I_NR      (16)
19249 +#define S3C64XX_GPIO_J_NR      (12)
19250 +#define S3C64XX_GPIO_K_NR      (16)
19251 +#define S3C64XX_GPIO_L_NR      (15)
19252 +#define S3C64XX_GPIO_M_NR      (6)
19253 +#define S3C64XX_GPIO_N_NR      (16)
19254 +#define S3C64XX_GPIO_O_NR      (16)
19255 +#define S3C64XX_GPIO_P_NR      (15)
19256 +#define S3C64XX_GPIO_Q_NR      (9)
19257 +
19258 +/* GPIO bank numbes */
19259 +
19260 +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
19261 + * space for debugging purposes so that any accidental
19262 + * change from one gpio bank to another can be caught.
19263 +*/
19264 +
19265 +#define S3C64XX_GPIO_NEXT(__gpio) \
19266 +       ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
19267 +
19268 +enum s3c_gpio_number {
19269 +       S3C64XX_GPIO_A_START = 0,
19270 +       S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
19271 +       S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
19272 +       S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
19273 +       S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
19274 +       S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
19275 +       S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
19276 +       S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
19277 +       S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
19278 +       S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
19279 +       S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
19280 +       S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
19281 +       S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
19282 +       S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
19283 +       S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
19284 +       S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
19285 +       S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
19286 +};
19287 +
19288 +/* S3C64XX GPIO number definitions. */
19289 +
19290 +#define S3C64XX_GPA(_nr)       (S3C64XX_GPIO_A_START + (_nr))
19291 +#define S3C64XX_GPB(_nr)       (S3C64XX_GPIO_B_START + (_nr))
19292 +#define S3C64XX_GPC(_nr)       (S3C64XX_GPIO_C_START + (_nr))
19293 +#define S3C64XX_GPD(_nr)       (S3C64XX_GPIO_D_START + (_nr))
19294 +#define S3C64XX_GPE(_nr)       (S3C64XX_GPIO_E_START + (_nr))
19295 +#define S3C64XX_GPF(_nr)       (S3C64XX_GPIO_F_START + (_nr))
19296 +#define S3C64XX_GPG(_nr)       (S3C64XX_GPIO_G_START + (_nr))
19297 +#define S3C64XX_GPH(_nr)       (S3C64XX_GPIO_H_START + (_nr))
19298 +#define S3C64XX_GPI(_nr)       (S3C64XX_GPIO_I_START + (_nr))
19299 +#define S3C64XX_GPJ(_nr)       (S3C64XX_GPIO_J_START + (_nr))
19300 +#define S3C64XX_GPK(_nr)       (S3C64XX_GPIO_K_START + (_nr))
19301 +#define S3C64XX_GPL(_nr)       (S3C64XX_GPIO_L_START + (_nr))
19302 +#define S3C64XX_GPM(_nr)       (S3C64XX_GPIO_M_START + (_nr))
19303 +#define S3C64XX_GPN(_nr)       (S3C64XX_GPIO_N_START + (_nr))
19304 +#define S3C64XX_GPO(_nr)       (S3C64XX_GPIO_O_START + (_nr))
19305 +#define S3C64XX_GPP(_nr)       (S3C64XX_GPIO_P_START + (_nr))
19306 +#define S3C64XX_GPQ(_nr)       (S3C64XX_GPIO_Q_START + (_nr))
19307 +
19308 +/* the end of the S3C64XX specific gpios */
19309 +#define S3C64XX_GPIO_END       (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
19310 +#define S3C_GPIO_END           S3C64XX_GPIO_END
19311 +
19312 +/* define the number of gpios we need to the one after the GPQ() range */
19313 +#define ARCH_NR_GPIOS  (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
19314 +
19315 +#include <asm-generic/gpio.h>
19316 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/hardware.h
19317 ===================================================================
19318 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19319 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/hardware.h  2009-01-02 00:01:56.000000000 +0100
19320 @@ -0,0 +1,16 @@
19321 +/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
19322 + *
19323 + * Copyright 2008 Openmoko, Inc.
19324 + * Copyright 2008 Simtec Electronics
19325 + *      Ben Dooks <ben@simtec.co.uk>
19326 + *      http://armlinux.simtec.co.uk/
19327 + *
19328 + * S3C6400 - Hardware support
19329 + */
19330 +
19331 +#ifndef __ASM_ARCH_HARDWARE_H
19332 +#define __ASM_ARCH_HARDWARE_H __FILE__
19333 +
19334 +/* currently nothing here, placeholder */
19335 +
19336 +#endif /* __ASM_ARCH_IRQ_H */
19337 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/irqs.h
19338 ===================================================================
19339 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19340 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/irqs.h      2009-01-02 00:01:56.000000000 +0100
19341 @@ -0,0 +1,20 @@
19342 +/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h
19343 + *
19344 + * Copyright 2008 Openmoko, Inc.
19345 + * Copyright 2008 Simtec Electronics
19346 + *      Ben Dooks <ben@simtec.co.uk>
19347 + *      http://armlinux.simtec.co.uk/
19348 + *
19349 + * S3C6400 - IRQ definitions
19350 + */
19351 +
19352 +#ifndef __ASM_ARCH_IRQS_H
19353 +#define __ASM_ARCH_IRQS_H __FILE__
19354 +
19355 +#ifndef __ASM_ARM_IRQ_H
19356 +#error "Do not include this directly, instead #include <asm/irq.h>"
19357 +#endif
19358 +
19359 +#include <plat/irqs.h>
19360 +
19361 +#endif /* __ASM_ARCH_IRQ_H */
19362 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/map.h
19363 ===================================================================
19364 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19365 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/map.h       2009-01-02 00:01:56.000000000 +0100
19366 @@ -0,0 +1,71 @@
19367 +/* linux/arch/arm/mach-s3c6400/include/mach/map.h
19368 + *
19369 + * Copyright 2008 Openmoko, Inc.
19370 + * Copyright 2008 Simtec Electronics
19371 + *     http://armlinux.simtec.co.uk/
19372 + *     Ben Dooks <ben@simtec.co.uk>
19373 + *
19374 + * S3C64XX - Memory map definitions
19375 + *
19376 + * This program is free software; you can redistribute it and/or modify
19377 + * it under the terms of the GNU General Public License version 2 as
19378 + * published by the Free Software Foundation.
19379 +*/
19380 +
19381 +#ifndef __ASM_ARCH_MAP_H
19382 +#define __ASM_ARCH_MAP_H __FILE__
19383 +
19384 +#include <plat/map-base.h>
19385 +
19386 +/* HSMMC units */
19387 +#define S3C64XX_PA_HSMMC(x)    (0x7C200000 + ((x) * 0x100000))
19388 +#define S3C64XX_PA_HSMMC0      S3C64XX_PA_HSMMC(0)
19389 +#define S3C64XX_PA_HSMMC1      S3C64XX_PA_HSMMC(1)
19390 +#define S3C64XX_PA_HSMMC2      S3C64XX_PA_HSMMC(2)
19391 +
19392 +#define S3C_PA_UART            (0x7F005000)
19393 +#define S3C_PA_UART0           (S3C_PA_UART + 0x00)
19394 +#define S3C_PA_UART1           (S3C_PA_UART + 0x400)
19395 +#define S3C_PA_UART2           (S3C_PA_UART + 0x800)
19396 +#define S3C_PA_UART3           (S3C_PA_UART + 0xC00)
19397 +#define S3C_UART_OFFSET                (0x400)
19398 +
19399 +/* See notes on UART VA mapping in debug-macro.S */
19400 +#define S3C_VA_UARTx(x)        (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
19401 +
19402 +#define S3C_VA_UART0           S3C_VA_UARTx(0)
19403 +#define S3C_VA_UART1           S3C_VA_UARTx(1)
19404 +#define S3C_VA_UART2           S3C_VA_UARTx(2)
19405 +#define S3C_VA_UART3           S3C_VA_UARTx(3)
19406 +
19407 +#define S3C64XX_PA_FB          (0x77100000)
19408 +#define S3C64XX_PA_SYSCON      (0x7E00F000)
19409 +#define S3C64XX_PA_TIMER       (0x7F006000)
19410 +#define S3C64XX_PA_IIC0                (0x7F004000)
19411 +#define S3C64XX_PA_IIC1                (0x7F00F000)
19412 +
19413 +#define S3C64XX_PA_GPIO                (0x7F008000)
19414 +#define S3C64XX_VA_GPIO                S3C_ADDR(0x00500000)
19415 +#define S3C64XX_SZ_GPIO                SZ_4K
19416 +
19417 +#define S3C64XX_PA_SDRAM       (0x50000000)
19418 +#define S3C64XX_PA_VIC0                (0x71200000)
19419 +#define S3C64XX_PA_VIC1                (0x71300000)
19420 +
19421 +#define S3C64XX_PA_MODEM       (0x74108000)
19422 +#define S3C64XX_VA_MODEM       S3C_ADDR(0x00600000)
19423 +
19424 +/* place VICs close together */
19425 +#define S3C_VA_VIC0            (S3C_VA_IRQ + 0x00)
19426 +#define S3C_VA_VIC1            (S3C_VA_IRQ + 0x10000)
19427 +
19428 +/* compatibiltiy defines. */
19429 +#define S3C_PA_TIMER           S3C64XX_PA_TIMER
19430 +#define S3C_PA_HSMMC0          S3C64XX_PA_HSMMC0
19431 +#define S3C_PA_HSMMC1          S3C64XX_PA_HSMMC1
19432 +#define S3C_PA_HSMMC2          S3C64XX_PA_HSMMC2
19433 +#define S3C_PA_IIC             S3C64XX_PA_IIC0
19434 +#define S3C_PA_IIC1            S3C64XX_PA_IIC1
19435 +#define S3C_PA_FB              S3C64XX_PA_FB
19436 +
19437 +#endif /* __ASM_ARCH_6400_MAP_H */
19438 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/memory.h
19439 ===================================================================
19440 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19441 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/memory.h    2009-01-02 00:01:56.000000000 +0100
19442 @@ -0,0 +1,21 @@
19443 +/* arch/arm/mach-s3c6400/include/mach/memory.h
19444 + *
19445 + * Copyright 2008 Openmoko, Inc.
19446 + * Copyright 2008 Simtec Electronics
19447 + *      Ben Dooks <ben@simtec.co.uk>
19448 + *      http://armlinux.simtec.co.uk/
19449 + *
19450 + * This program is free software; you can redistribute it and/or modify
19451 + * it under the terms of the GNU General Public License version 2 as
19452 + * published by the Free Software Foundation.
19453 +*/
19454 +
19455 +#ifndef __ASM_ARCH_MEMORY_H
19456 +#define __ASM_ARCH_MEMORY_H
19457 +
19458 +#define PHYS_OFFSET     UL(0x50000000)
19459 +
19460 +#define __virt_to_bus(x) __virt_to_phys(x)
19461 +#define __bus_to_virt(x) __phys_to_virt(x)
19462 +
19463 +#endif
19464 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
19465 ===================================================================
19466 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19467 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/pwm-clock.h 2009-01-02 00:01:56.000000000 +0100
19468 @@ -0,0 +1,56 @@
19469 +/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
19470 + *
19471 + * Copyright 2008 Openmoko, Inc.
19472 + * Copyright 2008 Simtec Electronics
19473 + *      Ben Dooks <ben@simtec.co.uk>
19474 + *      http://armlinux.simtec.co.uk/
19475 + *
19476 + * S3C64xx - pwm clock and timer support
19477 + */
19478 +
19479 +/**
19480 + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
19481 + * @tcfg: The timer TCFG1 register bits shifted down to 0.
19482 + *
19483 + * Return true if the given configuration from TCFG1 is a TCLK instead
19484 + * any of the TDIV clocks.
19485 + */
19486 +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
19487 +{
19488 +       return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
19489 +}
19490 +
19491 +/**
19492 + * tcfg_to_divisor() - convert tcfg1 setting to a divisor
19493 + * @tcfg1: The tcfg1 setting, shifted down.
19494 + *
19495 + * Get the divisor value for the given tcfg1 setting. We assume the
19496 + * caller has already checked to see if this is not a TCLK source.
19497 + */
19498 +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
19499 +{
19500 +       return 1 << tcfg1;
19501 +}
19502 +
19503 +/**
19504 + * pwm_tdiv_has_div1() - does the tdiv setting have a /1
19505 + *
19506 + * Return true if we have a /1 in the tdiv setting.
19507 + */
19508 +static inline unsigned int pwm_tdiv_has_div1(void)
19509 +{
19510 +       return 1;
19511 +}
19512 +
19513 +/**
19514 + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
19515 + * @div: The divisor to calculate the bit information for.
19516 + *
19517 + * Turn a divisor into the necessary bit field for TCFG1.
19518 + */
19519 +static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
19520 +{
19521 +       return ilog2(div);
19522 +}
19523 +
19524 +#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
19525 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-clock.h
19526 ===================================================================
19527 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19528 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-clock.h        2009-01-02 00:01:56.000000000 +0100
19529 @@ -0,0 +1,16 @@
19530 +/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
19531 + *
19532 + * Copyright 2008 Openmoko, Inc.
19533 + * Copyright 2008 Simtec Electronics
19534 + *     http://armlinux.simtec.co.uk/
19535 + *     Ben Dooks <ben@simtec.co.uk>
19536 + *
19537 + * S3C64XX - clock register compatibility with s3c24xx
19538 + *
19539 + * This program is free software; you can redistribute it and/or modify
19540 + * it under the terms of the GNU General Public License version 2 as
19541 + * published by the Free Software Foundation.
19542 +*/
19543 +
19544 +#include <plat/regs-clock.h>
19545 +
19546 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-fb.h
19547 ===================================================================
19548 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19549 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-fb.h   2009-01-02 00:01:56.000000000 +0100
19550 @@ -0,0 +1,259 @@
19551 +/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
19552 + *
19553 + * Copyright 2008 Openmoko, Inc.
19554 + * Copyright 2008 Simtec Electronics
19555 + *      http://armlinux.simtec.co.uk/
19556 + *      Ben Dooks <ben@simtec.co.uk>
19557 + *
19558 + * S3C64XX - new-style framebuffer register definitions
19559 + *
19560 + * This is the register set for the new style framebuffer interface
19561 + * found from the S3C2443 onwards and specifically the S3C64XX series
19562 + * S3C6400 and S3C6410.
19563 + *
19564 + * The file contains the cpu specific items which change between whichever
19565 + * architecture is selected. See <plat/regs-fb.h> for the core definitions
19566 + * that are the same.
19567 + *
19568 + * This program is free software; you can redistribute it and/or modify
19569 + * it under the terms of the GNU General Public License version 2 as
19570 + * published by the Free Software Foundation.
19571 +*/
19572 +
19573 +/* include the core definitions here, in case we really do need to
19574 + * override them at a later date.
19575 +*/
19576 +
19577 +#include <plat/regs-fb.h>
19578 +
19579 +#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
19580 +#define VIDCON1_FSTATUS_EVEN   (1 << 15)
19581 +
19582 +/* Video timing controls */
19583 +#define VIDTCON0                               (0x10)
19584 +#define VIDTCON1                               (0x14)
19585 +#define VIDTCON2                               (0x18)
19586 +
19587 +/* Window position controls */
19588 +
19589 +#define WINCON(_win)                           (0x20 + ((_win) * 4))
19590 +
19591 +/* OSD1 and OSD4 do not have register D */
19592 +
19593 +#define VIDOSD_A(_win)                         (0x40 + ((_win) * 16))
19594 +#define VIDOSD_B(_win)                         (0x44 + ((_win) * 16))
19595 +#define VIDOSD_C(_win)                         (0x48 + ((_win) * 16))
19596 +#define VIDOSD_D(_win)                         (0x4C + ((_win) * 16))
19597 +
19598 +/* Video buffer addresses */
19599 +
19600 +#define VIDW_BUF_START(_buff)                  (0xA0 + ((_buff) * 8))
19601 +#define VIDW_BUF_START1(_buff)                 (0xA4 + ((_buff) * 8))
19602 +#define VIDW_BUF_END(_buff)                    (0xD0 + ((_buff) * 8))
19603 +#define VIDW_BUF_END1(_buff)                   (0xD4 + ((_buff) * 8))
19604 +#define VIDW_BUF_SIZE(_buff)                   (0x100 + ((_buff) * 4))
19605 +
19606 +#define VIDINTCON0                             (0x130)
19607 +
19608 +#define WxKEYCONy(_win, _con)                  ((0x140 + ((_win) * 8)) + ((_con) * 4))
19609 +
19610 +/* WINCONx */
19611 +
19612 +#define WINCONx_CSCWIDTH_MASK                  (0x3 << 26)
19613 +#define WINCONx_CSCWIDTH_SHIFT                 (26)
19614 +#define WINCONx_CSCWIDTH_WIDE                  (0x0 << 26)
19615 +#define WINCONx_CSCWIDTH_NARROW                        (0x3 << 26)
19616 +
19617 +#define WINCONx_ENLOCAL                                (1 << 22)
19618 +#define WINCONx_BUFSTATUS                      (1 << 21)
19619 +#define WINCONx_BUFSEL                         (1 << 20)
19620 +#define WINCONx_BUFAUTOEN                      (1 << 19)
19621 +#define WINCONx_YCbCr                          (1 << 13)
19622 +
19623 +#define WINCON1_LOCALSEL_CAMIF                 (1 << 23)
19624 +
19625 +#define WINCON2_LOCALSEL_CAMIF                 (1 << 23)
19626 +#define WINCON2_BLD_PIX                                (1 << 6)
19627 +
19628 +#define WINCON2_ALPHA_SEL                      (1 << 1)
19629 +#define WINCON2_BPPMODE_MASK                   (0xf << 2)
19630 +#define WINCON2_BPPMODE_SHIFT                  (2)
19631 +#define WINCON2_BPPMODE_1BPP                   (0x0 << 2)
19632 +#define WINCON2_BPPMODE_2BPP                   (0x1 << 2)
19633 +#define WINCON2_BPPMODE_4BPP                   (0x2 << 2)
19634 +#define WINCON2_BPPMODE_8BPP_1232              (0x4 << 2)
19635 +#define WINCON2_BPPMODE_16BPP_565              (0x5 << 2)
19636 +#define WINCON2_BPPMODE_16BPP_A1555            (0x6 << 2)
19637 +#define WINCON2_BPPMODE_16BPP_I1555            (0x7 << 2)
19638 +#define WINCON2_BPPMODE_18BPP_666              (0x8 << 2)
19639 +#define WINCON2_BPPMODE_18BPP_A1665            (0x9 << 2)
19640 +#define WINCON2_BPPMODE_19BPP_A1666            (0xa << 2)
19641 +#define WINCON2_BPPMODE_24BPP_888              (0xb << 2)
19642 +#define WINCON2_BPPMODE_24BPP_A1887            (0xc << 2)
19643 +#define WINCON2_BPPMODE_25BPP_A1888            (0xd << 2)
19644 +#define WINCON2_BPPMODE_28BPP_A4888            (0xd << 2)
19645 +
19646 +#define WINCON3_BLD_PIX                                (1 << 6)
19647 +
19648 +#define WINCON3_ALPHA_SEL                      (1 << 1)
19649 +#define WINCON3_BPPMODE_MASK                   (0xf << 2)
19650 +#define WINCON3_BPPMODE_SHIFT                  (2)
19651 +#define WINCON3_BPPMODE_1BPP                   (0x0 << 2)
19652 +#define WINCON3_BPPMODE_2BPP                   (0x1 << 2)
19653 +#define WINCON3_BPPMODE_4BPP                   (0x2 << 2)
19654 +#define WINCON3_BPPMODE_16BPP_565              (0x5 << 2)
19655 +#define WINCON3_BPPMODE_16BPP_A1555            (0x6 << 2)
19656 +#define WINCON3_BPPMODE_16BPP_I1555            (0x7 << 2)
19657 +#define WINCON3_BPPMODE_18BPP_666              (0x8 << 2)
19658 +#define WINCON3_BPPMODE_18BPP_A1665            (0x9 << 2)
19659 +#define WINCON3_BPPMODE_19BPP_A1666            (0xa << 2)
19660 +#define WINCON3_BPPMODE_24BPP_888              (0xb << 2)
19661 +#define WINCON3_BPPMODE_24BPP_A1887            (0xc << 2)
19662 +#define WINCON3_BPPMODE_25BPP_A1888            (0xd << 2)
19663 +#define WINCON3_BPPMODE_28BPP_A4888            (0xd << 2)
19664 +
19665 +#define VIDINTCON0_FIFIOSEL_WINDOW2            (0x10 << 5)
19666 +#define VIDINTCON0_FIFIOSEL_WINDOW3            (0x20 << 5)
19667 +#define VIDINTCON0_FIFIOSEL_WINDOW4            (0x40 << 5)
19668 +
19669 +#define DITHMODE                               (0x170)
19670 +#define WINxMAP(_win)                          (0x180 + ((_win) * 4))
19671 +
19672 +
19673 +#define DITHMODE_R_POS_MASK                    (0x3 << 5)
19674 +#define DITHMODE_R_POS_SHIFT                   (5)
19675 +#define DITHMODE_R_POS_8BIT                    (0x0 << 5)
19676 +#define DITHMODE_R_POS_6BIT                    (0x1 << 5)
19677 +#define DITHMODE_R_POS_5BIT                    (0x2 << 5)
19678 +
19679 +#define DITHMODE_G_POS_MASK                    (0x3 << 3)
19680 +#define DITHMODE_G_POS_SHIFT                   (3)
19681 +#define DITHMODE_G_POS_8BIT                    (0x0 << 3)
19682 +#define DITHMODE_G_POS_6BIT                    (0x1 << 3)
19683 +#define DITHMODE_G_POS_5BIT                    (0x2 << 3)
19684 +
19685 +#define DITHMODE_B_POS_MASK                    (0x3 << 1)
19686 +#define DITHMODE_B_POS_SHIFT                   (1)
19687 +#define DITHMODE_B_POS_8BIT                    (0x0 << 1)
19688 +#define DITHMODE_B_POS_6BIT                    (0x1 << 1)
19689 +#define DITHMODE_B_POS_5BIT                    (0x2 << 1)
19690 +
19691 +#define DITHMODE_DITH_EN                       (1 << 0)
19692 +
19693 +#define WPALCON                                        (0x1A0)
19694 +
19695 +#define WPALCON_W4PAL_16BPP_A555               (1 << 8)
19696 +#define WPALCON_W3PAL_16BPP_A555               (1 << 7)
19697 +#define WPALCON_W2PAL_16BPP_A555               (1 << 6)
19698 +
19699 +/* Palette registers */
19700 +
19701 +#define WIN2_PAL(_entry)                       (0x300 + ((_entry) * 2))
19702 +#define WIN3_PAL(_entry)                       (0x320 + ((_entry) * 2))
19703 +#define WIN4_PAL(_entry)                       (0x340 + ((_entry) * 2))
19704 +#define WIN0_PAL(_entry)                       (0x400 + ((_entry) * 4))
19705 +#define WIN1_PAL(_entry)                       (0x800 + ((_entry) * 4))
19706 +
19707 +/* system specific implementation code for palette sizes, and other
19708 + * information that changes depending on which architecture is being
19709 + * compiled.
19710 +*/
19711 +
19712 +/* return true if window _win has OSD register D */
19713 +#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
19714 +
19715 +static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
19716 +{
19717 +       if (win < 2)
19718 +               return 256;
19719 +       if (win < 4)
19720 +               return 16;
19721 +       if (win == 4)
19722 +               return 4;
19723 +
19724 +       BUG();  /* shouldn't get here */
19725 +}
19726 +
19727 +static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
19728 +{
19729 +       /* all windows can do 1/2 bpp */
19730 +
19731 +       if ((bpp == 25 || bpp == 19) && win == 0)
19732 +               return 0;       /* win 0 does not have 19 or 25bpp modes */
19733 +
19734 +       if (bpp == 4 && win == 4)
19735 +               return 0;
19736 +
19737 +       if (bpp == 8 && (win >= 3))
19738 +               return 0;       /* win 3/4 cannot do 8bpp in any mode */
19739 +
19740 +       return 1;
19741 +}
19742 +
19743 +static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
19744 +{
19745 +       switch (window) {
19746 +       case 0: return WIN0_PAL(reg);
19747 +       case 1: return WIN1_PAL(reg);
19748 +       case 2: return WIN2_PAL(reg);
19749 +       case 3: return WIN3_PAL(reg);
19750 +       case 4: return WIN4_PAL(reg);
19751 +       }
19752 +
19753 +       BUG();
19754 +}
19755 +
19756 +static inline int s3c_fb_pal_is16(unsigned int window)
19757 +{
19758 +       return window > 1;
19759 +}
19760 +
19761 +struct s3c_fb_palette {
19762 +       struct fb_bitfield      r;
19763 +       struct fb_bitfield      g;
19764 +       struct fb_bitfield      b;
19765 +       struct fb_bitfield      a;
19766 +};
19767 +
19768 +static inline void s3c_fb_init_palette(unsigned int window,
19769 +                                      struct s3c_fb_palette *palette)
19770 +{
19771 +       if (window < 2) {
19772 +               /* Windows 0/1 are 8/8/8 or A/8/8/8 */
19773 +               palette->r.offset = 16;
19774 +               palette->r.length = 8;
19775 +               palette->g.offset = 8;
19776 +               palette->g.length = 8;
19777 +               palette->b.offset = 0;
19778 +               palette->b.length = 8;
19779 +       } else {
19780 +               /* currently we assume RGB 5/6/5 */
19781 +               palette->r.offset = 11;
19782 +               palette->r.length = 5;
19783 +               palette->g.offset = 5;
19784 +               palette->g.length = 6;
19785 +               palette->b.offset = 0;
19786 +               palette->b.length = 5;
19787 +       }
19788 +}
19789 +
19790 +/* Notes on per-window bpp settings
19791 + *
19792 + * Value       Win0     Win1     Win2     Win3     Win 4
19793 + * 0000                1(P)     1(P)     1(P)     1(P)     1(P)
19794 + * 0001                2(P)     2(P)     2(P)     2(P)     2(P)
19795 + * 0010                4(P)     4(P)     4(P)     4(P)     -none-
19796 + * 0011                8(P)     8(P)     -none-   -none-   -none-
19797 + * 0100                -none-   8(A232)  8(A232)  -none-   -none-
19798 + * 0101                16(565)  16(565)  16(565)  16(565)   16(565)
19799 + * 0110                -none-   16(A555) 16(A555) 16(A555)  16(A555)
19800 + * 0111                16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
19801 + * 1000                18(666)  18(666)  18(666)  18(666)   18(666)
19802 + * 1001                -none-   18(A665) 18(A665) 18(A665)  16(A665)
19803 + * 1010                -none-   19(A666) 19(A666) 19(A666)  19(A666)
19804 + * 1011                24(888)  24(888)  24(888)  24(888)   24(888)
19805 + * 1100                -none-   24(A887) 24(A887) 24(A887)  24(A887)
19806 + * 1101                -none-   25(A888) 25(A888) 25(A888)  25(A888)
19807 + * 1110                -none-   -none-   -none-   -none-    -none-
19808 + * 1111                -none-   -none-   -none-   -none-    -none-
19809 +*/
19810 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-irq.h
19811 ===================================================================
19812 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19813 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-irq.h  2009-01-02 00:01:56.000000000 +0100
19814 @@ -0,0 +1,20 @@
19815 +/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
19816 + *
19817 + * Copyright 2008 Openmoko, Inc.
19818 + * Copyright 2008 Simtec Electronics
19819 + *     http://armlinux.simtec.co.uk/
19820 + *     Ben Dooks <ben@simtec.co.uk>
19821 + *
19822 + * S3C64XX - IRQ register definitions
19823 + *
19824 + * This program is free software; you can redistribute it and/or modify
19825 + * it under the terms of the GNU General Public License version 2 as
19826 + * published by the Free Software Foundation.
19827 +*/
19828 +
19829 +#ifndef __ASM_ARCH_REGS_IRQ_H
19830 +#define __ASM_ARCH_REGS_IRQ_H __FILE__
19831 +
19832 +#include <asm/hardware/vic.h>
19833 +
19834 +#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
19835 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/system.h
19836 ===================================================================
19837 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19838 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/system.h    2009-01-02 00:01:56.000000000 +0100
19839 @@ -0,0 +1,44 @@
19840 +/* linux/arch/arm/mach-s3c6400/include/mach/system.h
19841 + *
19842 + * Copyright 2008 Openmoko, Inc.
19843 + * Copyright 2008 Simtec Electronics
19844 + *      Ben Dooks <ben@simtec.co.uk>
19845 + *      http://armlinux.simtec.co.uk/
19846 + *
19847 + * S3C6400 - system implementation
19848 + */
19849 +
19850 +#ifndef __ASM_ARCH_SYSTEM_H
19851 +#define __ASM_ARCH_SYSTEM_H __FILE__
19852 +
19853 +#include <linux/io.h>
19854 +#include <mach/map.h>
19855 +
19856 +#include <plat/regs-sys.h>
19857 +#include <plat/regs-syscon-power.h>
19858 +
19859 +static void arch_idle(void)
19860 +{
19861 +       unsigned long flags;
19862 +       u32 mode;
19863 +
19864 +       /* ensure that if we execute the cpu idle sequence that we
19865 +        * go into idle mode instead of powering off. */
19866 +
19867 +       local_irq_save(flags);
19868 +       mode = __raw_readl(S3C64XX_PWR_CFG);
19869 +       mode &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
19870 +       mode |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
19871 +       __raw_writel(mode, S3C64XX_PWR_CFG);
19872 +
19873 +       local_irq_restore(flags);
19874 +
19875 +       cpu_do_idle();
19876 +}
19877 +
19878 +static void arch_reset(char mode)
19879 +{
19880 +       /* nothing here yet */
19881 +}
19882 +
19883 +#endif /* __ASM_ARCH_IRQ_H */
19884 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/tick.h
19885 ===================================================================
19886 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19887 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/tick.h      2009-01-02 00:01:56.000000000 +0100
19888 @@ -0,0 +1,29 @@
19889 +/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
19890 + *
19891 + * Copyright 2008 Openmoko, Inc.
19892 + * Copyright 2008 Simtec Electronics
19893 + *     http://armlinux.simtec.co.uk/
19894 + *     Ben Dooks <ben@simtec.co.uk>
19895 + *
19896 + * S3C64XX - Timer tick support definitions
19897 + *
19898 + * This program is free software; you can redistribute it and/or modify
19899 + * it under the terms of the GNU General Public License version 2 as
19900 + * published by the Free Software Foundation.
19901 +*/
19902 +
19903 +#ifndef __ASM_ARCH_TICK_H
19904 +#define __ASM_ARCH_TICK_H __FILE__
19905 +
19906 +/* note, the timer interrutps turn up in 2 places, the vic and then
19907 + * the timer block. We take the VIC as the base at the moment.
19908 + */
19909 +static inline u32 s3c24xx_ostimer_pending(void)
19910 +{
19911 +       u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
19912 +       return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
19913 +}
19914 +
19915 +#define TICK_MAX       (0xffffffff)
19916 +
19917 +#endif /* __ASM_ARCH_6400_TICK_H */
19918 Index: linux-2.6.28/arch/arm/mach-s3c6400/include/mach/uncompress.h
19919 ===================================================================
19920 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19921 +++ linux-2.6.28/arch/arm/mach-s3c6400/include/mach/uncompress.h        2009-01-02 00:01:56.000000000 +0100
19922 @@ -0,0 +1,28 @@
19923 +/* arch/arm/mach-s3c6400/include/mach/uncompress.h
19924 + *
19925 + * Copyright 2008 Openmoko, Inc.
19926 + * Copyright 2008 Simtec Electronics
19927 + *     http://armlinux.simtec.co.uk/
19928 + *     Ben Dooks <ben@simtec.co.uk>
19929 + *
19930 + * S3C6400 - uncompress code
19931 + *
19932 + * This program is free software; you can redistribute it and/or modify
19933 + * it under the terms of the GNU General Public License version 2 as
19934 + * published by the Free Software Foundation.
19935 +*/
19936 +
19937 +#ifndef __ASM_ARCH_UNCOMPRESS_H
19938 +#define __ASM_ARCH_UNCOMPRESS_H
19939 +
19940 +#include <mach/map.h>
19941 +#include <plat/uncompress.h>
19942 +
19943 +static void arch_detect_cpu(void)
19944 +{
19945 +       /* we do not need to do any cpu detection here at the moment. */
19946 +       fifo_mask = S3C2440_UFSTAT_TXMASK;
19947 +       fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
19948 +}
19949 +
19950 +#endif /* __ASM_ARCH_UNCOMPRESS_H */
19951 Index: linux-2.6.28/arch/arm/mach-s3c6400/Kconfig
19952 ===================================================================
19953 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19954 +++ linux-2.6.28/arch/arm/mach-s3c6400/Kconfig  2009-01-02 00:01:56.000000000 +0100
19955 @@ -0,0 +1,8 @@
19956 +# arch/arm/mach-s3c6400/Kconfig
19957 +#
19958 +# Copyright 2008 Openmoko, Inc.
19959 +#      Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
19960 +#
19961 +# Licensed under GPLv2
19962 +
19963 +# Currently nothing here, this will be added later
19964 Index: linux-2.6.28/arch/arm/mach-s3c6400/Makefile
19965 ===================================================================
19966 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19967 +++ linux-2.6.28/arch/arm/mach-s3c6400/Makefile 2009-01-02 00:01:56.000000000 +0100
19968 @@ -0,0 +1,15 @@
19969 +# arch/arm/mach-s3c6400/Makefile
19970 +#
19971 +# Copyright 2008 Openmoko, Inc.
19972 +# Copyright 2008 Simtec Electronics
19973 +#
19974 +# Licensed under GPLv2
19975 +
19976 +obj-y                          :=
19977 +obj-m                          :=
19978 +obj-n                          :=
19979 +obj-                           :=
19980 +
19981 +# Core support for S3C6400 system
19982 +
19983 +obj-n                          += blank.o
19984 Index: linux-2.6.28/arch/arm/mach-s3c6400/Makefile.boot
19985 ===================================================================
19986 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19987 +++ linux-2.6.28/arch/arm/mach-s3c6400/Makefile.boot    2009-01-02 00:01:56.000000000 +0100
19988 @@ -0,0 +1,2 @@
19989 +   zreladdr-y  := 0x50008000
19990 +params_phys-y  := 0x50000100
19991 Index: linux-2.6.28/arch/arm/mach-s3c6410/cpu.c
19992 ===================================================================
19993 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
19994 +++ linux-2.6.28/arch/arm/mach-s3c6410/cpu.c    2009-01-02 00:01:56.000000000 +0100
19995 @@ -0,0 +1,101 @@
19996 +/* linux/arch/arm/mach-s3c6410/cpu.c
19997 + *
19998 + * Copyright 2008 Simtec Electronics
19999 + * Copyright 2008 Simtec Electronics
20000 + *     Ben Dooks <ben@simtec.co.uk>
20001 + *     http://armlinux.simtec.co.uk/
20002 + *
20003 + * This program is free software; you can redistribute it and/or modify
20004 + * it under the terms of the GNU General Public License version 2 as
20005 + * published by the Free Software Foundation.
20006 +*/
20007 +
20008 +#include <linux/kernel.h>
20009 +#include <linux/types.h>
20010 +#include <linux/interrupt.h>
20011 +#include <linux/list.h>
20012 +#include <linux/timer.h>
20013 +#include <linux/init.h>
20014 +#include <linux/clk.h>
20015 +#include <linux/io.h>
20016 +#include <linux/sysdev.h>
20017 +#include <linux/serial_core.h>
20018 +#include <linux/platform_device.h>
20019 +
20020 +#include <asm/mach/arch.h>
20021 +#include <asm/mach/map.h>
20022 +#include <asm/mach/irq.h>
20023 +
20024 +#include <mach/hardware.h>
20025 +#include <asm/irq.h>
20026 +
20027 +#include <plat/cpu-freq.h>
20028 +#include <plat/regs-serial.h>
20029 +
20030 +#include <plat/cpu.h>
20031 +#include <plat/devs.h>
20032 +#include <plat/clock.h>
20033 +#include <plat/sdhci.h>
20034 +#include <plat/iic-core.h>
20035 +#include <plat/s3c6400.h>
20036 +#include <plat/s3c6410.h>
20037 +
20038 +/* Initial IO mappings */
20039 +
20040 +static struct map_desc s3c6410_iodesc[] __initdata = {
20041 +};
20042 +
20043 +/* s3c6410_map_io
20044 + *
20045 + * register the standard cpu IO areas
20046 +*/
20047 +
20048 +void __init s3c6410_map_io(void)
20049 +{
20050 +       iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
20051 +
20052 +       /* initialise device information early */
20053 +       s3c6410_default_sdhci0();
20054 +       s3c6410_default_sdhci1();
20055 +
20056 +       /* the i2c devices are directly compatible with s3c2440 */
20057 +       s3c_i2c0_setname("s3c2440-i2c");
20058 +       s3c_i2c1_setname("s3c2440-i2c");
20059 +}
20060 +
20061 +void __init s3c6410_init_clocks(int xtal)
20062 +{
20063 +       printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
20064 +       s3c24xx_register_baseclocks(xtal);
20065 +       s3c64xx_register_clocks();
20066 +       s3c6400_register_clocks();
20067 +       s3c6400_setup_clocks();
20068 +}
20069 +
20070 +void __init s3c6410_init_irq(void)
20071 +{
20072 +       /* VIC0 is missing IRQ7, VIC1 is fully populated. */
20073 +       s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
20074 +}
20075 +
20076 +struct sysdev_class s3c6410_sysclass = {
20077 +       .name   = "s3c6410-core",
20078 +};
20079 +
20080 +static struct sys_device s3c6410_sysdev = {
20081 +       .cls    = &s3c6410_sysclass,
20082 +};
20083 +
20084 +static int __init s3c6410_core_init(void)
20085 +{
20086 +       return sysdev_class_register(&s3c6410_sysclass);
20087 +}
20088 +
20089 +core_initcall(s3c6410_core_init);
20090 +
20091 +int __init s3c6410_init(void)
20092 +{
20093 +       printk("S3C6410: Initialising architecture\n");
20094 +
20095 +       return sysdev_register(&s3c6410_sysdev);
20096 +}
20097 Index: linux-2.6.28/arch/arm/mach-s3c6410/include/mach/om-gta03.h
20098 ===================================================================
20099 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
20100 +++ linux-2.6.28/arch/arm/mach-s3c6410/include/mach/om-gta03.h  2009-01-02 00:01:56.000000000 +0100
20101 @@ -0,0 +1,91 @@
20102 +/*
20103 + * GTA03 GPIO Mappings
20104 + *
20105 + * (C) 2008 by Openmoko Inc.
20106 + * Author: Andy Green <andy@openmoko.com>
20107 + * All rights reserved.
20108 + *
20109 + * This program is free software; you can redistribute it and/or modify
20110 + * it under the terms of the GNU General Public License version 2 as
20111 + * published by the Free Software Foundation
20112 + *
20113 + */
20114 +
20115 +#ifndef _OM_GTA03_H
20116 +#define _OM_GTA03_H
20117 +
20118 +#include <mach/gpio.h>
20119 +#include <mach/irqs.h>
20120 +#include <linux/mfd/pcf50633/core.h>
20121 +
20122 +extern struct pcf50633_platform_data om_gta03_pcf_pdata;
20123 +
20124 +/* ATAG_REVISION from bootloader */
20125 +#define GTA03v1_SYSTEM_REV     0x00000001
20126 +
20127 +#define GTA03_GPIO_VIBRATOR_ON         S3C64XX_GPF(13)
20128 +#define GTA03_GPIO_CLKOUT              S3C64XX_GPF(14)
20129 +
20130 +#define GTA03_GPIO_ACCEL_MISO          S3C64XX_GPC(0)
20131 +#define GTA03_GPIO_ACCEL_CLK           S3C64XX_GPC(1)
20132 +#define GTA03_GPIO_ACCEL_MOSI          S3C64XX_GPC(2)
20133 +
20134 +#define GTA03_GPIO_LCM_MISO            S3C64XX_GPC(4)
20135 +#define GTA03_GPIO_LCM_CLK             S3C64XX_GPC(5)
20136 +#define GTA03_GPIO_LCM_MOSI            S3C64XX_GPC(6)
20137 +#define GTA03_GPIO_LCM_CS              S3C64XX_GPC(7)
20138 +
20139 +#define GTA03_GPIO_BTPCM_SHARED_SCLK   S3C64XX_GPE(0)
20140 +#define GTA03_GPIO_BTPCM_SHARED_EXTCLK S3C64XX_GPE(1)
20141 +#define GTA03_GPIO_BTPCM_SHARED_FSYNC  S3C64XX_GPE(2)
20142 +#define GTA03_GPIO_BTPCM_SHARED_SIN    S3C64XX_GPE(3)
20143 +#define GTA03_GPIO_BTPCM_SHARED_SOUT   S3C64XX_GPE(4)
20144 +
20145 +#define GTA03_GPIO_WLAN_RESET          S3C64XX_GPH(6)
20146 +#define GTA03_GPIO_HDQ                 S3C64XX_GPH(7)
20147 +#define GTA03_GPIO_WLAN_PWRDN          S3C64XX_GPH(8)
20148 +
20149 +#define GTA03_GPIO_VERSION2            S3C64XX_GPI(0)
20150 +#define GTA03_GPIO_VERSION1            S3C64XX_GPI(1)
20151 +#define GTA03_GPIO_VERSION0            S3C64XX_GPI(8)
20152 +
20153 +#define GTA03_GPIO_NWLAN_POWER         S3C64XX_GPK(0)
20154 +#define GTA03_GPIO_MODEN_ON            S3C64XX_GPK(2)
20155 +
20156 +#define GTA03_GPIO_TP_RESET            S3C64XX_GPM(0)
20157 +#define GTA03_GPIO_GPS_LNA_EN          S3C64XX_GPM(2)
20158 +
20159 +#define GTA03_GPIO_USB_FLT             S3C64XX_GPM(4)
20160 +#define GTA03_GPIO_USB_OC              S3C64XX_GPM(5)
20161 +
20162 +#define GTA03_GPIO_ACCEL_INT1          S3C64XX_GPN(0)
20163 +#define GTA03_GPIO_KEY_MINUS           S3C64XX_GPN(1)
20164 +#define GTA03_GPIO_KEY_PLUS            S3C64XX_GPN(2)
20165 +#define GTA03_GPIO_PWR_IND             S3C64XX_GPN(3)
20166 +#define GTA03_GPIO_PWR_IRQ             S3C64XX_GPN(4)
20167 +#define GTA03_GPIO_TOUCH               S3C64XX_GPN(5)
20168 +#define GTA03_GPIO_JACK_INSERT         S3C64XX_GPN(6)
20169 +#define GTA03_GPIO_GPS_INT             S3C64XX_GPN(7)
20170 +#define GTA03_GPIO_HOLD                        S3C64XX_GPN(8)
20171 +#define GTA03_GPIO_WLAN_WAKEUP         S3C64XX_GPN(9)
20172 +#define GTA03_GPIO_ACCEL_INT2          S3C64XX_GPN(10)
20173 +#define GTA03_GPIO_IO1                 S3C64XX_GPN(11)
20174 +#define GTA03_GPIO_NONKEYWAKE          S3C64XX_GPN(12)
20175 +
20176 +#define GTA03_GPIO_N_MODEM_RESET       S3C64XX_GPO(1)
20177 +
20178 +#define GTA03_IRQ_GSENSOR_1    S3C_EINT(0)
20179 +#define GTA03_IRQ_KEY_MINUS    S3C_EINT(1)
20180 +#define GTA03_IRQ_KEY_PLUS     S3C_EINT(2)
20181 +#define GTA03_IRQ_PWR_IND      S3C_EINT(3)
20182 +#define GTA03_IRQ_PMU          S3C_EINT(4)
20183 +#define GTA03_IRQ_TOUCH                S3C_EINT(5)
20184 +#define GTA03_IRQ_JACK_INSERT  S3C_EINT(6)
20185 +#define GTA03_IRQ_GPS_INT      S3C_EINT(7)
20186 +#define GTA03_IRQ_NHOLD                S3C_EINT(8)
20187 +#define GTA03_IRQ_WLAN_WAKEUP  S3C_EINT(9)
20188 +#define GTA03_IRQ_GSENSOR_2    S3C_EINT(10)
20189 +#define GTA03_IRQ_IO1          S3C_EINT(11)
20190 +#define GTA03_IRQ_NONKEYWAKE   S3C_EINT(12)
20191 +
20192 +#endif /* _OM_GTA03_H */
20193 Index: linux-2.6.28/arch/arm/mach-s3c6410/Kconfig
20194 ===================================================================
20195 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
20196 +++ linux-2.6.28/arch/arm/mach-s3c6410/Kconfig  2009-01-02 00:01:56.000000000 +0100
20197 @@ -0,0 +1,80 @@
20198 +# arch/arm/mach-s3c6410/Kconfig
20199 +#
20200 +# Copyright 2008 Openmoko, Inc.
20201 +# Copyright 2008 Simtec Electronics
20202 +#
20203 +# Licensed under GPLv2
20204 +
20205 +# Configuration options for the S3C6410 CPU
20206 +
20207 +config CPU_S3C6410
20208 +       bool
20209 +       select CPU_S3C6400_INIT
20210 +       select CPU_S3C6400_CLOCK
20211 +       help
20212 +         Enable S3C6410 CPU support
20213 +
20214 +config S3C6410_SETUP_SDHCI
20215 +       bool
20216 +       help
20217 +         Internal helper functions for S3C6410 based SDHCI systems
20218 +
20219 +config MACH_SMDK6410
20220 +       bool "SMDK6410"
20221 +       select CPU_S3C6410
20222 +       select S3C_DEV_HSMMC
20223 +       select S3C_DEV_HSMMC1
20224 +       select S3C_DEV_I2C1
20225 +       select S3C_DEV_FB
20226 +       select S3C6410_SETUP_SDHCI
20227 +       select S3C64XX_SETUP_I2C1
20228 +       select S3C64XX_SETUP_FB_24BPP
20229 +       help
20230 +         Machine support for the Samsung SMDK6410
20231 +
20232 +# At least some of the SMDK6410s were shipped with the card detect
20233 +# for the MMC/SD slots connected to the same input. This means that
20234 +# either the boards need to be altered to have channel0 to an alternate
20235 +# configuration or that only one slot can be used.
20236 +
20237 +choice
20238 +       prompt "SMDK6410 MMC/SD slot setup"
20239 +       depends on MACH_SMDK6410
20240 +
20241 +config SMDK6410_SD_CH0
20242 +       bool "Use channel 0 only"
20243 +       depends on MACH_SMDK6410
20244 +       help
20245 +          Select CON7 (channel 0) as the MMC/SD slot, as
20246 +         at least some SMDK6410 boards come with the
20247 +         resistors fitted so that the card detects for
20248 +         channels 0 and 1 are the same.
20249 +
20250 +config SMDK6410_SD_CH1
20251 +       bool "Use channel 1 only"
20252 +       depends on MACH_SMDK6410
20253 +       help
20254 +          Select CON6 (channel 1) as the MMC/SD slot, as
20255 +         at least some SMDK6410 boards come with the
20256 +         resistors fitted so that the card detects for
20257 +         channels 0 and 1 are the same.
20258 +
20259 +endchoice
20260 +
20261 +config MACH_OPENMOKO_GTA03
20262 +        bool "Openmoko GTA03 Phone"
20263 +       select CPU_S3C6410
20264 +       select S3C_DEV_HSMMC
20265 +       select S3C_DEV_HSMMC1
20266 +       select S3C_DEV_I2C1
20267 +       select S3C6410_SETUP_SDHCI
20268 +       select S3C64XX_SETUP_I2C1
20269 +       select S3C_DEV_FB
20270 +       select S3C64XX_SETUP_FB_24BPP
20271 +#      select SENSORS_PCF50633
20272 +       select POWER_SUPPLY
20273 +#      select GTA02_HDQ
20274 +       select MACH_NEO1973
20275 +       help
20276 +          Machine support for the Openmoko GTA03 Phone
20277 +
20278 Index: linux-2.6.28/arch/arm/mach-s3c6410/mach-om-gta03.c
20279 ===================================================================
20280 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
20281 +++ linux-2.6.28/arch/arm/mach-s3c6410/mach-om-gta03.c  2009-01-02 00:01:56.000000000 +0100
20282 @@ -0,0 +1,654 @@
20283 +/* linux/arch/arm/mach-s3c6410/mach-om_gta03.c
20284 + *
20285 + * Copyright 2008 Openmoko, Inc.
20286 + * Andy Green <andy@openmoko.org>
20287 + *
20288 + * based on mach_om_gta03.c which is
20289 + *
20290 + * Copyright 2008 Openmoko, Inc.
20291 + * Copyright 2008 Simtec Electronics
20292 + *     Ben Dooks <ben@simtec.co.uk>
20293 + *     http://armlinux.simtec.co.uk/
20294 + *
20295 + * This program is free software; you can redistribute it and/or modify
20296 + * it under the terms of the GNU General Public License version 2 as
20297 + * published by the Free Software Foundation.
20298 + *
20299 +*/
20300 +
20301 +#include <linux/kernel.h>
20302 +#include <linux/types.h>
20303 +#include <linux/interrupt.h>
20304 +#include <linux/list.h>
20305 +#include <linux/timer.h>
20306 +#include <linux/init.h>
20307 +#include <linux/serial_core.h>
20308 +#include <linux/platform_device.h>
20309 +#include <linux/io.h>
20310 +#include <linux/i2c.h>
20311 +#include <linux/fb.h>
20312 +#include <linux/delay.h>
20313 +#include <linux/lis302dl.h>
20314 +
20315 +#include <video/platform_lcd.h>
20316 +
20317 +#include <asm/mach/arch.h>
20318 +#include <asm/mach/map.h>
20319 +#include <asm/mach/irq.h>
20320 +
20321 +#include <mach/hardware.h>
20322 +#include <mach/map.h>
20323 +#include <mach/regs-fb.h>
20324 +
20325 +#include <asm/irq.h>
20326 +#include <asm/mach-types.h>
20327 +
20328 +#include <plat/regs-serial.h>
20329 +#include <plat/iic.h>
20330 +#include <plat/fb.h>
20331 +#include <plat/gpio-cfg.h>
20332 +#include <plat/pm.h>
20333 +
20334 +#include <plat/s3c6410.h>
20335 +#include <plat/clock.h>
20336 +#include <plat/devs.h>
20337 +#include <plat/cpu.h>
20338 +
20339 +/* #include <plat/udc.h> */
20340 +#include <linux/i2c.h>
20341 +#include <linux/backlight.h>
20342 +#include <linux/regulator/machine.h>
20343 +
20344 +#include <mach/om-gta03.h>
20345 +
20346 +#include <linux/mfd/pcf50633/core.h>
20347 +#include <linux/mfd/pcf50633/mbc.h>
20348 +#include <linux/mfd/pcf50633/adc.h>
20349 +#include <linux/mfd/pcf50633/gpio.h>
20350 +#include <linux/mfd/pcf50633/led.h>
20351 +
20352 +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
20353 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
20354 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
20355 +
20356 +static struct s3c2410_uartcfg om_gta03_uartcfgs[] __initdata = {
20357 +       [0] = {
20358 +               .hwport      = 0,
20359 +               .flags       = 0,
20360 +               .ucon        = 0x3c5,
20361 +               .ulcon       = 0x03,
20362 +               .ufcon       = 0x51,
20363 +       },
20364 +       [1] = {
20365 +               .hwport      = 1,
20366 +               .flags       = 0,
20367 +               .ucon        = 0x3c5,
20368 +               .ulcon       = 0x03,
20369 +               .ufcon       = 0x51,
20370 +       },
20371 +       [2] = {
20372 +               .hwport      = 2,
20373 +               .flags       = 0,
20374 +               .ucon        = 0x3c5,
20375 +               .ulcon       = 0x03,
20376 +               .ufcon       = 0x51,
20377 +       },
20378 +       [3] = {
20379 +               .hwport      = 3,
20380 +               .flags       = 0,
20381 +               .ucon        = 0x3c5,
20382 +               .ulcon       = 0x03,
20383 +               .ufcon       = 0x51,
20384 +       },
20385 +};
20386 +
20387 +
20388 +/*
20389 + * Situation is that Linux SPI can't work in an interrupt context, so we
20390 + * implement our own bitbang here.  Arbitration is needed because not only
20391 + * can this interrupt happen at any time even if foreground wants to use
20392 + * the bitbang API from Linux, but multiple motion sensors can be on the
20393 + * same SPI bus, and multiple interrupts can happen.
20394 + *
20395 + * Foreground / interrupt arbitration is okay because the interrupts are
20396 + * disabled around all the foreground SPI code.
20397 + *
20398 + * Interrupt / Interrupt arbitration is evidently needed, otherwise we
20399 + * lose edge-triggered service after a while due to the two sensors sharing
20400 + * the SPI bus having irqs at the same time eventually.
20401 + *
20402 + * Servicing is typ 75 - 100us at 400MHz.
20403 + */
20404 +
20405 +/* #define DEBUG_SPEW_MS */
20406 +#define MG_PER_SAMPLE 18
20407 +
20408 +struct lis302dl_platform_data lis302_pdata;
20409 +
20410 +/*
20411 + * generic SPI RX and TX bitbang
20412 + * only call with interrupts off!
20413 + */
20414 +
20415 +static void __gta03_lis302dl_bitbang(struct lis302dl_info *lis, u8 *tx,
20416 +                                            int tx_bytes, u8 *rx, int rx_bytes)
20417 +{
20418 +       struct lis302dl_platform_data *pdata = lis->pdata;
20419 +       int n;
20420 +       u8 shifter = 0;
20421 +
20422 +       gpio_direction_output(pdata->pin_chip_select, 1);
20423 +       gpio_direction_output(pdata->pin_clk, 1);
20424 +       gpio_direction_output(pdata->pin_chip_select, 0);
20425 +
20426 +       /* send the register index, r/w and autoinc bits */
20427 +       for (n = 0; n < (tx_bytes << 3); n++) {
20428 +               if (!(n & 7))
20429 +                       shifter = ~tx[n >> 3];
20430 +               gpio_direction_output(pdata->pin_clk, 0);
20431 +               gpio_direction_output(pdata->pin_mosi, !(shifter & 0x80));
20432 +               gpio_direction_output(pdata->pin_clk, 1);
20433 +               shifter <<= 1;
20434 +       }
20435 +
20436 +       for (n = 0; n < (rx_bytes << 3); n++) { /* 8 bits each */
20437 +               gpio_direction_output(pdata->pin_clk, 0);
20438 +               shifter <<= 1;
20439 +               if (gpio_direction_input(pdata->pin_miso))
20440 +                       shifter |= 1;
20441 +               if ((n & 7) == 7)
20442 +                       rx[n >> 3] = shifter;
20443 +               gpio_direction_output(pdata->pin_clk, 1);
20444 +       }
20445 +       gpio_direction_output(pdata->pin_chip_select, 1);
20446 +}
20447 +
20448 +
20449 +static int gta03_lis302dl_bitbang_read_reg(struct lis302dl_info *lis, u8 reg)
20450 +{
20451 +       u8 data = 0xc0 | reg; /* read, autoincrement */
20452 +       unsigned long flags;
20453 +
20454 +       local_irq_save(flags);
20455 +
20456 +       __gta03_lis302dl_bitbang(lis, &data, 1, &data, 1);
20457 +
20458 +       local_irq_restore(flags);
20459 +
20460 +       return data;
20461 +}
20462 +
20463 +static void gta03_lis302dl_bitbang_write_reg(struct lis302dl_info *lis, u8 reg,
20464 +                                                                        u8 val)
20465 +{
20466 +       u8 data[2] = { 0x00 | reg, val }; /* write, no autoincrement */
20467 +       unsigned long flags;
20468 +
20469 +       local_irq_save(flags);
20470 +
20471 +       __gta03_lis302dl_bitbang(lis, &data[0], 2, NULL, 0);
20472 +
20473 +       local_irq_restore(flags);
20474 +
20475 +}
20476 +
20477 +
20478 +void gta03_lis302dl_suspend_io(struct lis302dl_info *lis, int resume)
20479 +{
20480 +       struct lis302dl_platform_data *pdata = lis->pdata;
20481 +
20482 +       if (!resume) {
20483 +                /*
20484 +                * we don't want to power them with a high level
20485 +                * because GSENSOR_3V3 is not up during suspend
20486 +                */
20487 +               gpio_direction_output(pdata->pin_chip_select, 0);
20488 +               gpio_direction_output(pdata->pin_clk, 0);
20489 +               gpio_direction_output(pdata->pin_mosi, 0);
20490 +               s3c_gpio_setpull(pdata->pin_miso, S3C_GPIO_PULL_DOWN);
20491 +
20492 +               return;
20493 +       }
20494 +
20495 +       /* back to normal */
20496 +       gpio_direction_output(pdata->pin_chip_select, 1);
20497 +       gpio_direction_output(pdata->pin_clk, 1);
20498 +       s3c_gpio_setpull(pdata->pin_miso, S3C_GPIO_PULL_NONE);
20499 +
20500 +       s3c_gpio_cfgpin(pdata->pin_chip_select, S3C_GPIO_SFN(1));
20501 +       s3c_gpio_cfgpin(pdata->pin_clk, S3C_GPIO_SFN(1));
20502 +       s3c_gpio_cfgpin(pdata->pin_mosi, S3C_GPIO_SFN(1));
20503 +       s3c_gpio_cfgpin(pdata->pin_miso, S3C_GPIO_SFN(0));
20504 +
20505 +}
20506 +
20507 +struct lis302dl_platform_data lis302_pdata = {
20508 +               .name           = "lis302",
20509 +               .pin_chip_select= S3C64XX_GPC(3), /* NC */
20510 +               .pin_clk        = GTA03_GPIO_ACCEL_CLK,
20511 +               .pin_mosi       = GTA03_GPIO_ACCEL_MOSI,
20512 +               .pin_miso       = GTA03_GPIO_ACCEL_MISO,
20513 +               .interrupt      = GTA03_IRQ_GSENSOR_1,
20514 +               .open_drain     = 0,
20515 +               .lis302dl_bitbang = __gta03_lis302dl_bitbang,
20516 +               .lis302dl_bitbang_reg_read = gta03_lis302dl_bitbang_read_reg,
20517 +               .lis302dl_bitbang_reg_write = gta03_lis302dl_bitbang_write_reg,
20518 +               .lis302dl_suspend_io = gta03_lis302dl_suspend_io,
20519 +};
20520 +
20521 +static struct platform_device s3c_device_spi_acc1 = {
20522 +       .name             = "lis302dl",
20523 +       .id               = 1,
20524 +       .dev = {
20525 +               .platform_data = &lis302_pdata,
20526 +       },
20527 +};
20528 +
20529 +
20530 +
20531 +/* framebuffer and LCD setup. */
20532 +
20533 +/* GPF15 = LCD backlight control
20534 + * GPF13 => Panel power
20535 + * GPN5 = LCD nRESET signal
20536 + * PWM_TOUT1 => backlight brightness
20537 + */
20538 +
20539 +static void om_gta03_lcd_power_set(struct plat_lcd_data *pd,
20540 +                                  unsigned int power)
20541 +{
20542 +
20543 +}
20544 +
20545 +static struct plat_lcd_data om_gta03_lcd_power_data = {
20546 +       .set_power      = om_gta03_lcd_power_set,
20547 +};
20548 +
20549 +static struct platform_device om_gta03_lcd_powerdev = {
20550 +       .name                   = "platform-lcd",
20551 +       .dev.parent             = &s3c_device_fb.dev,
20552 +       .dev.platform_data      = &om_gta03_lcd_power_data,
20553 +};
20554 +
20555 +static struct s3c_fb_pd_win om_gta03_fb_win0 = {
20556 +       /* this is to ensure we use win0 */
20557 +       .win_mode       = {
20558 +               .pixclock       = 40816,
20559 +               .left_margin    = 8,
20560 +               .right_margin   = 16,
20561 +               .upper_margin   = 2,
20562 +               .lower_margin   = 16,
20563 +               .hsync_len      = 8,
20564 +               .vsync_len      = 2,
20565 +               .xres           = 640,
20566 +               .yres           = 480,
20567 +       },
20568 +       .max_bpp        = 32,
20569 +       .default_bpp    = 16,
20570 +};
20571 +
20572 +static struct s3c_fb_platdata om_gta03_lcd_pdata __initdata = {
20573 +       .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
20574 +       .win[0]         = &om_gta03_fb_win0,
20575 +       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
20576 +       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
20577 +};
20578 +
20579 +
20580 +struct map_desc om_gta03_6410_iodesc[] = {};
20581 +
20582 +static struct resource om_gta03_button_resources[] = {
20583 +       [0] = {
20584 +               .start = 0,
20585 +               .end   = 0,
20586 +       },
20587 +       [1] = {
20588 +               .start = GTA03_GPIO_HOLD,
20589 +               .end   = GTA03_GPIO_HOLD,
20590 +       },
20591 +       [2] = {
20592 +               .start = GTA03_GPIO_JACK_INSERT,
20593 +               .end   = GTA03_GPIO_JACK_INSERT,
20594 +       },
20595 +       [3] = {
20596 +               .start = GTA03_GPIO_KEY_PLUS,
20597 +               .end   = GTA03_GPIO_KEY_PLUS,
20598 +       },
20599 +       [4] = {
20600 +               .start = GTA03_GPIO_KEY_MINUS,
20601 +               .end   = GTA03_GPIO_KEY_MINUS,
20602 +       },
20603 +};
20604 +
20605 +static struct platform_device om_gta03_button_dev = {
20606 +       .name           = "neo1973-button",
20607 +       .num_resources  = ARRAY_SIZE(om_gta03_button_resources),
20608 +       .resource       = om_gta03_button_resources,
20609 +};
20610 +
20611 +
20612 +/********************** PMU ***************************/
20613 +/*
20614 + * GTA03 PMU Mapping info
20615 + *
20616 + *  name  maxcurr  default    Nom   consumers
20617 + *
20618 + *  AUTO   1100mA  ON  3.3V   3.3V  Main 3.3V rail
20619 + *  DOWN1   500mA  ON  1.2V   1.2V  CPU VddARM, VddINT, VddMPLL, VddOTGI
20620 + *  DOWN2   500mA  ON  1.8V   1.8V  CPU VddAlive via LDO, Memories, WLAN
20621 + *  LED      25mA  OFF        18V   Backlight
20622 + *  HCLDO   200mA  OFF        2.8V  Camera 2V8
20623 + *  LDO1     50mA  ON  3.3V   3.3V  Accel
20624 + *  LDO2     50mA  OFF        1.5V  Camera 1V5
20625 + *  LDO3     50mA  OFF        3.3V  CODEC 3.3V
20626 + *  LDO4    150mA  ON  2.8V   2.7V  uSD power
20627 + *  LDO5    150mA  OFF        3.0V  GPS 3V
20628 + *  LDO6     50mA  ON  3.0V   3.0V  LCM 3V
20629 + *
20630 + */
20631 +
20632 +
20633 +/* PMU driver info */
20634 +
20635 +
20636 +static struct regulator_consumer_supply ldo4_consumers[] = {
20637 +       {
20638 +               .dev = &s3c_device_hsmmc0.dev,
20639 +               .supply = "SD_3V",
20640 +       },
20641 +};
20642 +
20643 +static struct platform_device om_gta03_features_dev = {
20644 +       .name           = "om-gta03",
20645 +};
20646 +
20647 +static struct regulator_consumer_supply ldo5_consumers[] = {
20648 +       {
20649 +               .dev = &om_gta03_features_dev.dev,
20650 +               .supply = "RF_3V",
20651 +       },
20652 +};
20653 +
20654 +
20655 +static void om_gta03_pmu_event_callback(struct pcf50633 *pcf, int irq)
20656 +{
20657 +#if 0
20658 +       if (irq == PCF50633_IRQ_USBINS) {
20659 +               schedule_delayed_work(&gta02_charger_work,
20660 +                               GTA02_CHARGER_CONFIGURE_TIMEOUT);
20661 +               return;
20662 +       } else if (irq == PCF50633_IRQ_USBREM) {
20663 +               cancel_delayed_work_sync(&gta02_charger_work);
20664 +               pcf50633_mbc_usb_curlim_set(pcf, 0);
20665 +               gta02_usb_vbus_draw = 0;
20666 +       }
20667 +
20668 +       bq27000_charging_state_change(&bq27000_battery_device);
20669 +#endif
20670 +}
20671 +
20672 +
20673 +static void om_gta03_pcf50633_attach_child_devices(struct pcf50633 *pcf);
20674 +static void om_gta03_pmu_regulator_registered(struct pcf50633 *pcf, int id);
20675 +
20676 +struct pcf50633_platform_data om_gta03_pcf_pdata = {
20677 +
20678 +       .resumers = {
20679 +               [0] = PCF50633_INT1_USBINS |
20680 +                     PCF50633_INT1_USBREM |
20681 +                     PCF50633_INT1_ALARM,
20682 +               [1] = PCF50633_INT2_ONKEYF,
20683 +               [2] = PCF50633_INT3_ONKEY1S
20684 +       },
20685 +
20686 +       .reg_init_data = {
20687 +               /* GTA03: Main 3.3V rail */
20688 +               [PCF50633_REGULATOR_AUTO] = {
20689 +                       .constraints = {
20690 +                               .min_uV = 3300000,
20691 +                               .max_uV = 3300000,
20692 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20693 +                               .apply_uV = 1,
20694 +                               .state_mem = {
20695 +                                       .enabled = 1,
20696 +                               },
20697 +                       },
20698 +                       .num_consumer_supplies = 0,
20699 +               },
20700 +               /* GTA03: CPU core power */
20701 +               [PCF50633_REGULATOR_DOWN1] = {
20702 +                       .constraints = {
20703 +                               .min_uV = 900000,
20704 +                               .max_uV = 1200000,
20705 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20706 +                               .apply_uV = 1,
20707 +                       },
20708 +                       .num_consumer_supplies = 0,
20709 +               },
20710 +               /* GTA03: Memories */
20711 +               [PCF50633_REGULATOR_DOWN2] = {
20712 +                       .constraints = {
20713 +                               .min_uV = 1800000,
20714 +                               .max_uV = 1800000,
20715 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20716 +                               .apply_uV = 1,
20717 +                               .state_mem = {
20718 +                                       .enabled = 1,
20719 +                               },
20720 +                       },
20721 +                       .num_consumer_supplies = 0,
20722 +               },
20723 +               /* GTA03: Camera 2V8 */
20724 +               [PCF50633_REGULATOR_HCLDO] = {
20725 +                       .constraints = {
20726 +                               .min_uV = 2800000,
20727 +                               .max_uV = 2800000,
20728 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20729 +                       },
20730 +                       .num_consumer_supplies = 0,
20731 +/*                     .consumer_supplies = hcldo_consumers, */
20732 +               },
20733 +
20734 +               /* GTA03: Accel 3V3 */
20735 +               [PCF50633_REGULATOR_LDO1] = {
20736 +                       .constraints = {
20737 +                               .min_uV = 3300000,
20738 +                               .max_uV = 3300000,
20739 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20740 +                               .apply_uV = 1,
20741 +                       },
20742 +                       .num_consumer_supplies = 0,
20743 +               },
20744 +               /* GTA03: Camera 1V5 */
20745 +               [PCF50633_REGULATOR_LDO2] = {
20746 +                       .constraints = {
20747 +                               .min_uV = 1500000,
20748 +                               .max_uV = 1500000,
20749 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20750 +                               .apply_uV = 1,
20751 +                       },
20752 +                       .num_consumer_supplies = 0,
20753 +               },
20754 +               /* GTA03: Codec 3.3V */
20755 +               [PCF50633_REGULATOR_LDO3] = {
20756 +                       .constraints = {
20757 +                               .min_uV = 3300000,
20758 +                               .max_uV = 3300000,
20759 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20760 +                               .apply_uV = 1,
20761 +                       },
20762 +                       .num_consumer_supplies = 0,
20763 +               },
20764 +               /* GTA03: uSD Power */
20765 +               [PCF50633_REGULATOR_LDO4] = {
20766 +                       .constraints = {
20767 +                               .min_uV = 3000000,
20768 +                               .max_uV = 3000000,
20769 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20770 +                               .apply_uV = 1,
20771 +                       },
20772 +                       .num_consumer_supplies = 1,
20773 +                       .consumer_supplies = ldo4_consumers,
20774 +               },
20775 +               /* GTA03: GPS 3V */
20776 +               [PCF50633_REGULATOR_LDO5] = {
20777 +                       .constraints = {
20778 +                               .min_uV = 3000000,
20779 +                               .max_uV = 3000000,
20780 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20781 +                               .apply_uV = 1,
20782 +                       },
20783 +                       .num_consumer_supplies = 1,
20784 +                       .consumer_supplies = ldo5_consumers,
20785 +               },
20786 +               /* GTA03: LCM 3V */
20787 +               [PCF50633_REGULATOR_LDO6] = {
20788 +                       .constraints = {
20789 +                               .min_uV = 3000000,
20790 +                               .max_uV = 3000000,
20791 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20792 +                               .state_mem = {
20793 +                                       .enabled = 1,
20794 +                               },
20795 +                       },
20796 +                       .num_consumer_supplies = 0,
20797 +               },
20798 +               /* power for memories in suspend */
20799 +               [PCF50633_REGULATOR_MEMLDO] = {
20800 +                       .constraints = {
20801 +                               .min_uV = 1800000,
20802 +                               .max_uV = 1800000,
20803 +                               .valid_modes_mask = REGULATOR_MODE_NORMAL,
20804 +                               .state_mem = {
20805 +                                       .enabled = 1,
20806 +                               },
20807 +                       },
20808 +                       .num_consumer_supplies = 0,
20809 +               },
20810 +
20811 +       },
20812 +       .probe_done = om_gta03_pcf50633_attach_child_devices,
20813 +       .regulator_registered = om_gta03_pmu_regulator_registered,
20814 +       .mbc_event_callback = om_gta03_pmu_event_callback,
20815 +};
20816 +
20817 +
20818 +static struct i2c_board_info om_gta03_i2c_devs[] __initdata = {
20819 +       {
20820 +               I2C_BOARD_INFO("pcf50633", 0x73),
20821 +               .irq = GTA03_IRQ_PMU,
20822 +               .platform_data = &om_gta03_pcf_pdata,
20823 +       },
20824 +       {
20825 +               I2C_BOARD_INFO("pcap7200", 0x0a),
20826 +               .irq = GTA03_IRQ_TOUCH,
20827 +       },
20828 +
20829 +};
20830 +
20831 +
20832 +static struct platform_device *om_gta03_devices[] __initdata = {
20833 +       &s3c_device_fb,
20834 +       &s3c_device_i2c0,
20835 +       &s3c_device_hsmmc1, /* SDIO to WLAN */
20836 +};
20837 +
20838 +
20839 +static void om_gta03_pmu_regulator_registered(struct pcf50633 *pcf, int id)
20840 +{
20841 +       struct platform_device *regulator, *pdev;
20842 +
20843 +       regulator = pcf->pmic.pdev[id];
20844 +
20845 +       switch(id) {
20846 +               case PCF50633_REGULATOR_LDO4:
20847 +                       pdev = &s3c_device_hsmmc0;
20848 +                       break;
20849 +               case PCF50633_REGULATOR_LDO5: /* GPS regulator */
20850 +                       pdev = &om_gta03_features_dev;
20851 +                       break;
20852 +               case PCF50633_REGULATOR_LDO6:
20853 +                       pdev = &om_gta03_lcd_powerdev;
20854 +                       break;
20855 +               default:
20856 +                       return;
20857 +       }
20858 +
20859 +       pdev->dev.parent = &regulator->dev;
20860 +       platform_device_register(pdev);
20861 +}
20862 +
20863 +static struct platform_device *om_gta03_devices_pmu_children[] = {
20864 +       &om_gta03_button_dev,
20865 +       &s3c_device_spi_acc1, /* relies on PMU reg for power */
20866 +};
20867 +
20868 +/* this is called when pc50633 is probed, unfortunately quite late in the
20869 + * day since it is an I2C bus device.  Here we can belatedly define some
20870 + * platform devices with the advantage that we can mark the pcf50633 as the
20871 + * parent.  This makes them get suspended and resumed with their parent
20872 + * the pcf50633 still around.
20873 + */
20874 +
20875 +static void om_gta03_pcf50633_attach_child_devices(struct pcf50633 *pcf)
20876 +{
20877 +       int n;
20878 +
20879 +       for (n = 0; n < ARRAY_SIZE(om_gta03_devices_pmu_children); n++)
20880 +               om_gta03_devices_pmu_children[n]->dev.parent = pcf->dev;
20881 +
20882 +       platform_add_devices(om_gta03_devices_pmu_children,
20883 +                                    ARRAY_SIZE(om_gta03_devices_pmu_children));
20884 +
20885 +       /* Switch on backlight. Qi does not do it for us */
20886 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
20887 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
20888 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
20889 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x3f);
20890 +
20891 +}
20892 +
20893 +
20894 +
20895 +extern void s3c64xx_init_io(struct map_desc *, int);
20896 +
20897 +static void __init om_gta03_map_io(void)
20898 +{
20899 +       s3c64xx_init_io(om_gta03_6410_iodesc, ARRAY_SIZE(om_gta03_6410_iodesc));
20900 +       s3c24xx_init_clocks(12000000);
20901 +       s3c24xx_init_uarts(om_gta03_uartcfgs, ARRAY_SIZE(om_gta03_uartcfgs));
20902 +}
20903 +
20904 +static void __init om_gta03_machine_init(void)
20905 +{
20906 +       s3c_pm_init();
20907 +
20908 +       s3c_i2c0_set_platdata(NULL);
20909 +       s3c_fb_set_platdata(&om_gta03_lcd_pdata);
20910 +
20911 +       s3c_gpio_setpull(S3C64XX_GPH(0), S3C_GPIO_PULL_UP);
20912 +       s3c_gpio_setpull(S3C64XX_GPH(1), S3C_GPIO_PULL_UP);
20913 +       s3c_gpio_setpull(S3C64XX_GPH(2), S3C_GPIO_PULL_UP);
20914 +       s3c_gpio_setpull(S3C64XX_GPH(3), S3C_GPIO_PULL_UP);
20915 +       s3c_gpio_setpull(S3C64XX_GPH(4), S3C_GPIO_PULL_UP);
20916 +       s3c_gpio_setpull(S3C64XX_GPH(5), S3C_GPIO_PULL_UP);
20917 +
20918 +
20919 +       i2c_register_board_info(0, om_gta03_i2c_devs,
20920 +                                                ARRAY_SIZE(om_gta03_i2c_devs));
20921 +
20922 +       platform_add_devices(om_gta03_devices, ARRAY_SIZE(om_gta03_devices));
20923 +}
20924 +
20925 +MACHINE_START(OPENMOKO_GTA03, "OM-GTA03")
20926 +       /* Maintainer: Andy Green <andy@openmoko.com> */
20927 +       .phys_io        = S3C_PA_UART & 0xfff00000,
20928 +       .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
20929 +       .boot_params    = S3C64XX_PA_SDRAM + 0x100,
20930 +
20931 +       .init_irq       = s3c6410_init_irq,
20932 +       .map_io         = om_gta03_map_io,
20933 +       .init_machine   = om_gta03_machine_init,
20934 +       .timer          = &s3c24xx_timer,
20935 +MACHINE_END
20936 +
20937 Index: linux-2.6.28/arch/arm/mach-s3c6410/mach-smdk6410.c
20938 ===================================================================
20939 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
20940 +++ linux-2.6.28/arch/arm/mach-s3c6410/mach-smdk6410.c  2009-01-02 00:01:56.000000000 +0100
20941 @@ -0,0 +1,205 @@
20942 +/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
20943 + *
20944 + * Copyright 2008 Openmoko, Inc.
20945 + * Copyright 2008 Simtec Electronics
20946 + *     Ben Dooks <ben@simtec.co.uk>
20947 + *     http://armlinux.simtec.co.uk/
20948 + *
20949 + * This program is free software; you can redistribute it and/or modify
20950 + * it under the terms of the GNU General Public License version 2 as
20951 + * published by the Free Software Foundation.
20952 + *
20953 +*/
20954 +
20955 +#include <linux/kernel.h>
20956 +#include <linux/types.h>
20957 +#include <linux/interrupt.h>
20958 +#include <linux/list.h>
20959 +#include <linux/timer.h>
20960 +#include <linux/init.h>
20961 +#include <linux/serial_core.h>
20962 +#include <linux/platform_device.h>
20963 +#include <linux/io.h>
20964 +#include <linux/i2c.h>
20965 +#include <linux/fb.h>
20966 +#include <linux/gpio.h>
20967 +#include <linux/delay.h>
20968 +
20969 +#include <video/platform_lcd.h>
20970 +
20971 +#include <asm/mach/arch.h>
20972 +#include <asm/mach/map.h>
20973 +#include <asm/mach/irq.h>
20974 +
20975 +#include <mach/hardware.h>
20976 +#include <mach/regs-fb.h>
20977 +#include <mach/map.h>
20978 +
20979 +#include <asm/irq.h>
20980 +#include <asm/mach-types.h>
20981 +
20982 +#include <plat/regs-serial.h>
20983 +#include <plat/regs-modem.h>
20984 +#include <plat/regs-gpio.h>
20985 +#include <plat/regs-sys.h>
20986 +#include <plat/iic.h>
20987 +#include <plat/fb.h>
20988 +#include <plat/pm.h>
20989 +
20990 +#include <plat/s3c6410.h>
20991 +#include <plat/clock.h>
20992 +#include <plat/devs.h>
20993 +#include <plat/cpu.h>
20994 +
20995 +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
20996 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
20997 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
20998 +
20999 +static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
21000 +       [0] = {
21001 +               .hwport      = 0,
21002 +               .flags       = 0,
21003 +               .ucon        = 0x3c5,
21004 +               .ulcon       = 0x03,
21005 +               .ufcon       = 0x51,
21006 +       },
21007 +       [1] = {
21008 +               .hwport      = 1,
21009 +               .flags       = 0,
21010 +               .ucon        = 0x3c5,
21011 +               .ulcon       = 0x03,
21012 +               .ufcon       = 0x51,
21013 +       },
21014 +};
21015 +
21016 +/* framebuffer and LCD setup. */
21017 +
21018 +/* GPF15 = LCD backlight control
21019 + * GPF13 => Panel power
21020 + * GPN5 = LCD nRESET signal
21021 + * PWM_TOUT1 => backlight brightness
21022 + */
21023 +
21024 +static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
21025 +                                  unsigned int power)
21026 +{
21027 +       if (power) {
21028 +               gpio_direction_output(S3C64XX_GPF(13), 1);
21029 +               gpio_direction_output(S3C64XX_GPF(15), 1);
21030 +
21031 +               /* fire nRESET on power up */
21032 +               gpio_direction_output(S3C64XX_GPN(5), 0);
21033 +               msleep(10);
21034 +               gpio_direction_output(S3C64XX_GPN(5), 1);
21035 +               msleep(1);
21036 +       } else {
21037 +               gpio_direction_output(S3C64XX_GPF(15), 0);
21038 +               gpio_direction_output(S3C64XX_GPF(13), 0);
21039 +       }
21040 +}
21041 +
21042 +static struct plat_lcd_data smdk6410_lcd_power_data = {
21043 +       .set_power      = smdk6410_lcd_power_set,
21044 +};
21045 +
21046 +static struct platform_device smdk6410_lcd_powerdev = {
21047 +       .name                   = "platform-lcd",
21048 +       .dev.parent             = &s3c_device_fb.dev,
21049 +       .dev.platform_data      = &smdk6410_lcd_power_data,
21050 +};
21051 +
21052 +static struct s3c_fb_pd_win smdk6410_fb_win0 = {
21053 +       /* this is to ensure we use win0 */
21054 +       .win_mode       = {
21055 +               .pixclock       = 41094,
21056 +               .left_margin    = 8,
21057 +               .right_margin   = 13,
21058 +               .upper_margin   = 7,
21059 +               .lower_margin   = 5,
21060 +               .hsync_len      = 3,
21061 +               .vsync_len      = 1,
21062 +               .xres           = 800,
21063 +               .yres           = 480,
21064 +       },
21065 +       .max_bpp        = 32,
21066 +       .default_bpp    = 16,
21067 +};
21068 +
21069 +/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
21070 +static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
21071 +       .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
21072 +       .win[0]         = &smdk6410_fb_win0,
21073 +       .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
21074 +       .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
21075 +};
21076 +
21077 +struct map_desc smdk6410_iodesc[] = {};
21078 +
21079 +static struct platform_device *smdk6410_devices[] __initdata = {
21080 +#ifdef CONFIG_SMDK6410_SD_CH0
21081 +       &s3c_device_hsmmc0,
21082 +#endif
21083 +#ifdef CONFIG_SMDK6410_SD_CH1
21084 +       &s3c_device_hsmmc1,
21085 +#endif
21086 +       &s3c_device_i2c0,
21087 +       &s3c_device_i2c1,
21088 +       &s3c_device_fb,
21089 +       &smdk6410_lcd_powerdev,
21090 +};
21091 +
21092 +static struct i2c_board_info i2c_devs0[] __initdata = {
21093 +       { I2C_BOARD_INFO("24c08", 0x50), },
21094 +       { I2C_BOARD_INFO("WM8580", 0X1b), },
21095 +};
21096 +
21097 +static struct i2c_board_info i2c_devs1[] __initdata = {
21098 +       { I2C_BOARD_INFO("24c128", 0x57), },    /* Samsung S524AD0XD1 */
21099 +};
21100 +
21101 +static void __init smdk6410_map_io(void)
21102 +{
21103 +       u32 tmp;
21104 +
21105 +       s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
21106 +       s3c24xx_init_clocks(12000000);
21107 +       s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
21108 +
21109 +       /* set the LCD type */
21110 +
21111 +       tmp = __raw_readl(S3C64XX_SPCON);
21112 +       tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
21113 +       tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
21114 +       __raw_writel(tmp, S3C64XX_SPCON);
21115 +
21116 +       /* remove the lcd bypass */
21117 +       tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
21118 +       tmp &= ~MIFPCON_LCD_BYPASS;
21119 +       __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
21120 +}
21121 +
21122 +static void __init smdk6410_machine_init(void)
21123 +{
21124 +       s3c_pm_init();
21125 +
21126 +       s3c_i2c0_set_platdata(NULL);
21127 +       s3c_i2c1_set_platdata(NULL);
21128 +       s3c_fb_set_platdata(&smdk6410_lcd_pdata);
21129 +
21130 +       i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
21131 +       i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
21132 +
21133 +       platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
21134 +}
21135 +
21136 +MACHINE_START(SMDK6410, "SMDK6410")
21137 +       /* Maintainer: Ben Dooks <ben@fluff.org> */
21138 +       .phys_io        = S3C_PA_UART & 0xfff00000,
21139 +       .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
21140 +       .boot_params    = S3C64XX_PA_SDRAM + 0x100,
21141 +
21142 +       .init_irq       = s3c6410_init_irq,
21143 +       .map_io         = smdk6410_map_io,
21144 +       .init_machine   = smdk6410_machine_init,
21145 +       .timer          = &s3c24xx_timer,
21146 +MACHINE_END
21147 Index: linux-2.6.28/arch/arm/mach-s3c6410/Makefile
21148 ===================================================================
21149 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
21150 +++ linux-2.6.28/arch/arm/mach-s3c6410/Makefile 2009-01-02 00:01:56.000000000 +0100
21151 @@ -0,0 +1,26 @@
21152 +# arch/arm/plat-s3c6410/Makefile
21153 +#
21154 +# Copyright 2008 Openmoko, Inc.
21155 +# Copyright 2008 Simtec Electronics
21156 +#
21157 +# Licensed under GPLv2
21158 +
21159 +obj-y                          :=
21160 +obj-m                          :=
21161 +obj-n                          :=
21162 +obj-                           :=
21163 +
21164 +# Core support for S3C6410 system
21165 +
21166 +obj-$(CONFIG_CPU_S3C6410)      += cpu.o
21167 +
21168 +# Helper and device support
21169 +
21170 +obj-$(CONFIG_S3C6410_SETUP_SDHCI)      += setup-sdhci.o
21171 +
21172 +# machine support
21173 +
21174 +obj-$(CONFIG_MACH_SMDK6410)    += mach-smdk6410.o
21175 +obj-$(CONFIG_MACH_OPENMOKO_GTA03)      += mach-om-gta03.o \
21176 +                                          om-gta03-features.o
21177 +
21178 Index: linux-2.6.28/arch/arm/mach-s3c6410/om-gta03-features.c
21179 ===================================================================
21180 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
21181 +++ linux-2.6.28/arch/arm/mach-s3c6410/om-gta03-features.c      2009-01-02 00:01:56.000000000 +0100
21182 @@ -0,0 +1,344 @@
21183 +/*
21184 + * Support for features of Openmoko GTA03
21185 + *
21186 + * (C) 2008 by Openmoko Inc.
21187 + * Author: Andy Green <andy@openmoko.com>
21188 + * All rights reserved.
21189 + *
21190 + * Somewhat based on the GTA01 / 02 neo1973_pm_ stuff mainly by Harald Welte
21191 + *
21192 + * This program is free software; you can redistribute it and/or modify
21193 + * it under the terms of the GNU General Public License version 2 as
21194 + * published by the Free Software Foundation
21195 + *
21196 + */
21197 +
21198 +#include <linux/module.h>
21199 +#include <linux/init.h>
21200 +#include <linux/kernel.h>
21201 +#include <linux/delay.h>
21202 +#include <linux/platform_device.h>
21203 +
21204 +#include <mach/hardware.h>
21205 +#include <mach/om-gta03.h>
21206 +#include <asm/mach-types.h>
21207 +
21208 +#include <linux/regulator/consumer.h>
21209 +#include <linux/mfd/pcf50633/core.h>
21210 +#include <linux/mfd/pcf50633/gpio.h>
21211 +#include <linux/mmc/host.h>
21212 +
21213 +#include <plat/sdhci.h>
21214 +#include <plat/devs.h>
21215 +
21216 +#include <plat/gpio-cfg.h>
21217 +
21218 +enum feature {
21219 +       OM_GTA03_GPS,           /* power to GPS section and LNA */
21220 +       OM_GTA03_WLAN_BT,       /* WLAN and BT Module */
21221 +       OM_GTA03_GSM,           /* GSM module */
21222 +       OM_GTA03_USBHOST,       /* USB Host power generation */
21223 +       OM_GTA03_VIB,           /* Vibrator */
21224 +
21225 +       OM_GTA03_FEATURE_COUNT  /* always last */
21226 +};
21227 +
21228 +
21229 +struct om_gta03_feature_info {
21230 +       const char * name;
21231 +       int depower_on_suspend;
21232 +       int on;
21233 +};
21234 +
21235 +static struct om_gta03_feature_info feature_info[OM_GTA03_FEATURE_COUNT] = {
21236 +       [OM_GTA03_GPS] =        { "gps_power",          1, 0 },
21237 +       [OM_GTA03_WLAN_BT] =    { "wlan_bt_power",      1, 0 },
21238 +       [OM_GTA03_GSM] =        { "gsm_power",          0, 0 },
21239 +       [OM_GTA03_USBHOST] =    { "usbhost_power",      1, 0 },
21240 +       [OM_GTA03_VIB] =        { "vibrator_power",     1, 0 },
21241 +};
21242 +
21243 +static struct regulator *gps_regulator;
21244 +
21245 +
21246 +
21247 +static void om_gta03_features_pwron_set_on(enum feature feature)
21248 +{
21249 +       int gpio;
21250 +
21251 +       switch (feature) {
21252 +       case OM_GTA03_GPS:
21253 +               regulator_enable(gps_regulator);
21254 +               /* enable LNA */
21255 +               gpio_direction_output(GTA03_GPIO_GPS_LNA_EN, 1);
21256 +               break;
21257 +       case OM_GTA03_WLAN_BT:
21258 +
21259 +               for (gpio = S3C64XX_GPH(0); gpio < S3C64XX_GPH(6); gpio++) {
21260 +                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); /* sdio */
21261 +                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
21262 +               }
21263 +               /* assert reset */
21264 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_RESET, S3C_GPIO_PULL_NONE);
21265 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_RESET, S3C_GPIO_SFN(1));
21266 +               gpio_direction_output(GTA03_GPIO_WLAN_RESET, 0);
21267 +
21268 +               /* "full power down (active low)" -- deassert it*/
21269 +               gpio_direction_output(GTA03_GPIO_WLAN_PWRDN, 1);
21270 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_PULL_NONE);
21271 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_SFN(1));
21272 +
21273 +               /* enable P-Channel mosfet switch for power */
21274 +               gpio_direction_output(GTA03_GPIO_NWLAN_POWER, 0);
21275 +               s3c_gpio_setpull(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_PULL_NONE);
21276 +               s3c_gpio_cfgpin(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_SFN(1));
21277 +               msleep(50);
21278 +               /* deassert reset */
21279 +               gpio_direction_output(GTA03_GPIO_WLAN_RESET, 1);
21280 +               msleep(1500);
21281 +               sdhci_s3c_force_presence_change(&s3c_device_hsmmc1);
21282 +               break;
21283 +       case OM_GTA03_GSM:
21284 +               /* give power to GSM module */
21285 +               s3c_gpio_setpull(GTA03_GPIO_N_MODEM_RESET, S3C_GPIO_PULL_NONE);
21286 +               s3c_gpio_cfgpin(GTA03_GPIO_N_MODEM_RESET, S3C_GPIO_SFN(1));
21287 +               gpio_direction_output(GTA03_GPIO_N_MODEM_RESET, 0);
21288 +
21289 +               gpio_direction_output(GTA03_GPIO_MODEN_ON, 0);
21290 +               s3c_gpio_setpull(GTA03_GPIO_MODEN_ON, S3C_GPIO_PULL_NONE);
21291 +               s3c_gpio_cfgpin(GTA03_GPIO_MODEN_ON, S3C_GPIO_SFN(1));
21292 +               msleep(1);
21293 +               gpio_direction_output(GTA03_GPIO_N_MODEM_RESET, 1);
21294 +               break;
21295 +       case OM_GTA03_USBHOST:
21296 +               pcf50633_gpio_set(om_gta03_pcf_pdata.pcf, PCF50633_GPO, 1);
21297 +               break;
21298 +       case OM_GTA03_VIB:
21299 +               gpio_direction_output(GTA03_GPIO_VIBRATOR_ON, 1);
21300 +               break;
21301 +       default:
21302 +               break;
21303 +       }
21304 +}
21305 +
21306 +static void om_gta03_features_pwron_set_off(enum feature feature)
21307 +{
21308 +       int gpio;
21309 +
21310 +       switch (feature) {
21311 +       case OM_GTA03_GPS:
21312 +               /* disable LNA */
21313 +               gpio_direction_output(GTA03_GPIO_GPS_LNA_EN, 0);
21314 +               regulator_disable(gps_regulator);
21315 +               break;
21316 +       case OM_GTA03_WLAN_BT:
21317 +               gpio_direction_output(GTA03_GPIO_WLAN_RESET, 0);
21318 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_RESET, S3C_GPIO_PULL_NONE);
21319 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_RESET, S3C_GPIO_SFN(1));
21320 +
21321 +               gpio_direction_output(GTA03_GPIO_WLAN_PWRDN, 0);
21322 +               s3c_gpio_setpull(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_PULL_NONE);
21323 +               s3c_gpio_cfgpin(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_SFN(1));
21324 +               msleep(500);
21325 +               /* remove power from WLAN / BT module */
21326 +               gpio_direction_output(GTA03_GPIO_NWLAN_POWER, 1);
21327 +               s3c_gpio_setpull(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_PULL_NONE);
21328 +               s3c_gpio_cfgpin(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_SFN(1));
21329 +
21330 +               sdhci_s3c_force_presence_change(&s3c_device_hsmmc1);
21331 +               for (gpio = S3C64XX_GPH(0); gpio < S3C64XX_GPH(6); gpio++) {
21332 +                       s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); /* input */
21333 +                       s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN);
21334 +               }
21335 +               break;
21336 +       case OM_GTA03_GSM:
21337 +               /* remove power from WLAN / BT module */
21338 +               gpio_direction_output(GTA03_GPIO_MODEN_ON, 1);
21339 +               s3c_gpio_setpull(GTA03_GPIO_MODEN_ON, S3C_GPIO_PULL_NONE);
21340 +               s3c_gpio_cfgpin(GTA03_GPIO_MODEN_ON, S3C_GPIO_SFN(1));
21341 +               break;
21342 +       case OM_GTA03_USBHOST:
21343 +               pcf50633_gpio_set(om_gta03_pcf_pdata.pcf, PCF50633_GPO, 0);
21344 +               break;
21345 +       case OM_GTA03_VIB:
21346 +               gpio_direction_output(GTA03_GPIO_VIBRATOR_ON, 0);
21347 +               break;
21348 +       default:
21349 +               break;
21350 +       }
21351 +}
21352 +
21353 +static void om_gta03_features_pwron_set(enum feature feature, int on)
21354 +{
21355 +       if ((on) && (!feature_info[feature].on))
21356 +               om_gta03_features_pwron_set_on(feature);
21357 +       else
21358 +               if ((!on) && (feature_info[feature].on))
21359 +                       om_gta03_features_pwron_set_off(feature);
21360 +}
21361 +
21362 +static ssize_t om_gta03_feature_read(struct device *dev,
21363 +                                      struct device_attribute *attr, char *buf)
21364 +{
21365 +       int on;
21366 +       int feature = 0;
21367 +       int hit = 0;
21368 +
21369 +       while (!hit && feature < OM_GTA03_FEATURE_COUNT) {
21370 +               if (!strcmp(attr->attr.name, feature_info[feature].name))
21371 +                       hit = 1;
21372 +               else
21373 +                       feature++;
21374 +       }
21375 +
21376 +       if (!hit)
21377 +               return -EINVAL;
21378 +
21379 +       switch (feature) {
21380 +       case OM_GTA03_GPS:
21381 +               on = regulator_is_enabled(gps_regulator);
21382 +               break;
21383 +       case OM_GTA03_USBHOST:
21384 +               on = pcf50633_gpio_get(om_gta03_pcf_pdata.pcf, PCF50633_GPO);
21385 +               break;
21386 +       default:
21387 +               on = feature_info[feature].on;
21388 +       }
21389 +
21390 +       *buf++ = '0' + on;
21391 +       *buf++='\n';
21392 +       *buf = '\0';
21393 +
21394 +       return 3;
21395 +}
21396 +
21397 +static ssize_t om_gta03_feature_write(struct device *dev,
21398 +                                       struct device_attribute *attr,
21399 +                                       const char *buf, size_t count)
21400 +{
21401 +       int on = !!simple_strtoul(buf, NULL, 10);
21402 +       int feature = 0;
21403 +       int hit = 0;
21404 +
21405 +       while (!hit && feature < OM_GTA03_FEATURE_COUNT) {
21406 +               if (!strcmp(attr->attr.name, feature_info[feature].name))
21407 +                       hit = 1;
21408 +               else
21409 +                       feature++;
21410 +       }
21411 +
21412 +       if (!hit)
21413 +               return -EINVAL;
21414 +
21415 +       om_gta03_features_pwron_set(feature, on);
21416 +       feature_info[feature].on = on;
21417 +
21418 +       return count;
21419 +}
21420 +
21421 +
21422 +static DEVICE_ATTR(gps_power, 0644, om_gta03_feature_read,
21423 +                                                       om_gta03_feature_write);
21424 +
21425 +static DEVICE_ATTR(wlan_bt_power, 0644, om_gta03_feature_read,
21426 +                                                       om_gta03_feature_write);
21427 +
21428 +static DEVICE_ATTR(gsm_power, 0644, om_gta03_feature_read,
21429 +                                                       om_gta03_feature_write);
21430 +
21431 +static DEVICE_ATTR(usbhost_power, 0644, om_gta03_feature_read,
21432 +                                                       om_gta03_feature_write);
21433 +
21434 +static DEVICE_ATTR(vibrator_power, 0644, om_gta03_feature_read,
21435 +                                                       om_gta03_feature_write);
21436 +
21437 +
21438 +static struct attribute *om_gta03_features_sysfs_entries[] = {
21439 +       &dev_attr_gps_power.attr,
21440 +       &dev_attr_wlan_bt_power.attr,
21441 +       &dev_attr_gsm_power.attr,
21442 +       &dev_attr_usbhost_power.attr,
21443 +       &dev_attr_vibrator_power.attr,
21444 +       NULL
21445 +};
21446 +
21447 +
21448 +static struct attribute_group om_gta03_features_attr_group = {
21449 +       .name   = NULL,
21450 +       .attrs  = om_gta03_features_sysfs_entries,
21451 +};
21452 +
21453 +static int __init om_gta03_features_probe(struct platform_device *pdev)
21454 +{
21455 +       gps_regulator = regulator_get(&pdev->dev, "RF_3V");
21456 +       dev_info(&pdev->dev, "starting\n");
21457 +
21458 +       return sysfs_create_group(&pdev->dev.kobj,
21459 +                                                &om_gta03_features_attr_group);
21460 +}
21461 +
21462 +static int om_gta03_features_remove(struct platform_device *pdev)
21463 +{
21464 +
21465 +       regulator_put(gps_regulator);
21466 +       sysfs_remove_group(&pdev->dev.kobj, &om_gta03_features_attr_group);
21467 +
21468 +       return 0;
21469 +}
21470 +
21471 +
21472 +#ifdef CONFIG_PM
21473 +static int om_gta03_features_suspend(struct platform_device *pdev,
21474 +                                    pm_message_t state)
21475 +{
21476 +       int feature;
21477 +
21478 +       for (feature = 0; feature < OM_GTA03_FEATURE_COUNT; feature++)
21479 +               if (feature_info[feature].depower_on_suspend)
21480 +                       om_gta03_features_pwron_set_off(feature);
21481 +
21482 +       return 0;
21483 +}
21484 +
21485 +static int om_gta03_features_resume(struct platform_device *pdev)
21486 +{
21487 +       int feature;
21488 +
21489 +       for (feature = 0; feature < OM_GTA03_FEATURE_COUNT; feature++)
21490 +               if (feature_info[feature].depower_on_suspend)
21491 +                       if (feature_info[feature].on)
21492 +                               om_gta03_features_pwron_set_on(feature);
21493 +
21494 +       return 0;
21495 +}
21496 +#else
21497 +#define om_gta03_features_suspend      NULL
21498 +#define om_gta03_features_resume       NULL
21499 +#endif
21500 +
21501 +static struct platform_driver om_gta03_features_driver = {
21502 +       .probe          = om_gta03_features_probe,
21503 +       .remove         = om_gta03_features_remove,
21504 +       .suspend        = om_gta03_features_suspend,
21505 +       .resume         = om_gta03_features_resume,
21506 +       .driver         = {
21507 +               .name           = "om-gta03",
21508 +       },
21509 +};
21510 +
21511 +static int __devinit om_gta03_features_init(void)
21512 +{
21513 +       return platform_driver_register(&om_gta03_features_driver);
21514 +}
21515 +
21516 +static void om_gta03_features_exit(void)
21517 +{
21518 +       platform_driver_unregister(&om_gta03_features_driver);
21519 +}
21520 +
21521 +module_init(om_gta03_features_init);
21522 +module_exit(om_gta03_features_exit);
21523 +
21524 +MODULE_LICENSE("GPL");
21525 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
21526 +MODULE_DESCRIPTION("Openmoko GTA03 Feature Driver");
21527 Index: linux-2.6.28/arch/arm/mach-s3c6410/setup-sdhci.c
21528 ===================================================================
21529 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
21530 +++ linux-2.6.28/arch/arm/mach-s3c6410/setup-sdhci.c    2009-01-02 00:01:56.000000000 +0100
21531 @@ -0,0 +1,103 @@
21532 +/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
21533 + *
21534 + * Copyright 2008 Simtec Electronics
21535 + * Copyright 2008 Simtec Electronics
21536 + *     Ben Dooks <ben@simtec.co.uk>
21537 + *     http://armlinux.simtec.co.uk/
21538 + *
21539 + * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
21540 + *
21541 + * This program is free software; you can redistribute it and/or modify
21542 + * it under the terms of the GNU General Public License version 2 as
21543 + * published by the Free Software Foundation.
21544 +*/
21545 +
21546 +#include <linux/kernel.h>
21547 +#include <linux/types.h>
21548 +#include <linux/interrupt.h>
21549 +#include <linux/platform_device.h>
21550 +#include <linux/io.h>
21551 +
21552 +#include <linux/mmc/card.h>
21553 +#include <linux/mmc/host.h>
21554 +
21555 +#include <mach/gpio.h>
21556 +#include <plat/gpio-cfg.h>
21557 +#include <plat/regs-sdhci.h>
21558 +#include <plat/sdhci.h>
21559 +
21560 +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
21561 +
21562 +char *s3c6410_hsmmc_clksrcs[4] = {
21563 +       [0] = "hsmmc",
21564 +       [1] = "hsmmc",
21565 +       [2] = "mmc_bus",
21566 +       /* [3] = "48m", - note not succesfully used yet */
21567 +};
21568 +
21569 +void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
21570 +{
21571 +       unsigned int gpio;
21572 +       unsigned int end;
21573 +
21574 +       end = S3C64XX_GPG(2 + width);
21575 +
21576 +       /* Set all the necessary GPG pins to special-function 0 */
21577 +       for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
21578 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
21579 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
21580 +       }
21581 +
21582 +       /* FIXME this needs defining in machine as to if we even have CD */
21583 +       s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
21584 +       s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
21585 +}
21586 +
21587 +void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
21588 +                                   void __iomem *r,
21589 +                                   struct mmc_ios *ios,
21590 +                                   struct mmc_card *card)
21591 +{
21592 +       u32 ctrl2, ctrl3;
21593 +
21594 +       /* don't need to alter anything acording to card-type */
21595 +
21596 +       writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
21597 +
21598 +       ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
21599 +       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
21600 +       ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
21601 +                 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
21602 +                 S3C_SDHCI_CTRL2_ENFBCLKRX |
21603 +                 S3C_SDHCI_CTRL2_DFCNT_NONE |
21604 +                 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
21605 +
21606 +       if (ios->clock < 25 * 1000000)
21607 +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
21608 +                        S3C_SDHCI_CTRL3_FCSEL2 |
21609 +                        S3C_SDHCI_CTRL3_FCSEL1 |
21610 +                        S3C_SDHCI_CTRL3_FCSEL0);
21611 +       else
21612 +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
21613 +
21614 +       printk(KERN_INFO "%s: %p CTRL 2=%08x, 3=%08x\n", __func__, r, ctrl2, ctrl3);
21615 +       writel(ctrl2, r + S3C_SDHCI_CONTROL2);
21616 +       writel(ctrl3, r + S3C_SDHCI_CONTROL3);
21617 +}
21618 +
21619 +void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
21620 +{
21621 +       unsigned int gpio;
21622 +       unsigned int end;
21623 +
21624 +       end = S3C64XX_GPH(2 + width);
21625 +
21626 +       /* Set all the necessary GPG pins to special-function 0 */
21627 +       for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
21628 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
21629 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
21630 +       }
21631 +
21632 +//     s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
21633 +//     s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
21634 +}
21635 Index: linux-2.6.28/arch/arm/Makefile
21636 ===================================================================
21637 --- linux-2.6.28.orig/arch/arm/Makefile 2008-12-25 00:26:37.000000000 +0100
21638 +++ linux-2.6.28/arch/arm/Makefile      2009-01-02 00:01:56.000000000 +0100
21639 @@ -121,7 +121,10 @@ endif
21640   machine-$(CONFIG_ARCH_OMAP3)     := omap2
21641      plat-$(CONFIG_ARCH_OMAP)      := omap
21642   machine-$(CONFIG_ARCH_S3C2410)           := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
21643 + machine-$(CONFIG_ARCH_S3C24A0)           := s3c24a0
21644      plat-$(CONFIG_PLAT_S3C24XX)           := s3c24xx s3c
21645 + machine-$(CONFIG_ARCH_S3C64XX)           := s3c6400 s3c6410
21646 +    plat-$(CONFIG_PLAT_S3C64XX)           := s3c64xx s3c
21647   machine-$(CONFIG_ARCH_LH7A40X)           := lh7a40x
21648   machine-$(CONFIG_ARCH_VERSATILE)  := versatile
21649   machine-$(CONFIG_ARCH_IMX)       := imx
21650 Index: linux-2.6.28/arch/arm/mm/Kconfig
21651 ===================================================================
21652 --- linux-2.6.28.orig/arch/arm/mm/Kconfig       2008-12-25 00:26:37.000000000 +0100
21653 +++ linux-2.6.28/arch/arm/mm/Kconfig    2009-01-02 00:01:56.000000000 +0100
21654 @@ -183,14 +183,14 @@ config CPU_ARM926T
21655         depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
21656                 MACH_VERSATILE_AB || ARCH_OMAP730 || \
21657                 ARCH_OMAP16XX || MACH_REALVIEW_EB || \
21658 -               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
21659 +               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \
21660                 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
21661                 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
21662                 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
21663                 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
21664         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
21665                 ARCH_OMAP730 || ARCH_OMAP16XX || \
21666 -               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
21667 +               ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \
21668                 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
21669                 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
21670                 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
21671 @@ -400,9 +400,10 @@ config CPU_FEROCEON_OLD_ID
21672  # ARMv6
21673  config CPU_V6
21674         bool "Support ARM V6 processor"
21675 -       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
21676 +       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || ARCH_S3C64XX
21677         default y if ARCH_MX3
21678         default y if ARCH_MSM
21679 +       default y if ARCH_S3C64XX
21680         select CPU_32v6
21681         select CPU_ABRT_EV6
21682         select CPU_PABRT_NOIFAR
21683 Index: linux-2.6.28/arch/arm/plat-s3c/clock.c
21684 ===================================================================
21685 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
21686 +++ linux-2.6.28/arch/arm/plat-s3c/clock.c      2009-01-02 00:01:56.000000000 +0100
21687 @@ -0,0 +1,369 @@
21688 +/* linux/arch/arm/plat-s3c24xx/clock.c
21689 + *
21690 + * Copyright (c) 2004-2005 Simtec Electronics
21691 + *     Ben Dooks <ben@simtec.co.uk>
21692 + *
21693 + * S3C24XX Core clock control support
21694 + *
21695 + * Based on, and code from linux/arch/arm/mach-versatile/clock.c
21696 + **
21697 + **  Copyright (C) 2004 ARM Limited.
21698 + **  Written by Deep Blue Solutions Limited.
21699 + *
21700 + *
21701 + * This program is free software; you can redistribute it and/or modify
21702 + * it under the terms of the GNU General Public License as published by
21703 + * the Free Software Foundation; either version 2 of the License, or
21704 + * (at your option) any later version.
21705 + *
21706 + * This program is distributed in the hope that it will be useful,
21707 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
21708 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21709 + * GNU General Public License for more details.
21710 + *
21711 + * You should have received a copy of the GNU General Public License
21712 + * along with this program; if not, write to the Free Software
21713 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21714 +*/
21715 +
21716 +#include <linux/init.h>
21717 +#include <linux/module.h>
21718 +#include <linux/kernel.h>
21719 +#include <linux/list.h>
21720 +#include <linux/errno.h>
21721 +#include <linux/err.h>
21722 +#include <linux/platform_device.h>
21723 +#include <linux/sysdev.h>
21724 +#include <linux/interrupt.h>
21725 +#include <linux/ioport.h>
21726 +#include <linux/clk.h>
21727 +#include <linux/spinlock.h>
21728 +#include <linux/delay.h>
21729 +#include <linux/io.h>
21730 +
21731 +#include <mach/hardware.h>
21732 +#include <asm/irq.h>
21733 +
21734 +#include <plat/cpu-freq.h>
21735 +
21736 +#include <plat/clock.h>
21737 +#include <plat/cpu.h>
21738 +
21739 +/* clock information */
21740 +
21741 +static LIST_HEAD(clocks);
21742 +
21743 +/* We originally used an mutex here, but some contexts (see resume)
21744 + * are calling functions such as clk_set_parent() with IRQs disabled
21745 + * causing an BUG to be triggered.
21746 + */
21747 +DEFINE_SPINLOCK(clocks_lock);
21748 +
21749 +/* enable and disable calls for use with the clk struct */
21750 +
21751 +static int clk_null_enable(struct clk *clk, int enable)
21752 +{
21753 +       return 0;
21754 +}
21755 +
21756 +/* Clock API calls */
21757 +
21758 +struct clk *clk_get(struct device *dev, const char *id)
21759 +{
21760 +       struct clk *p;
21761 +       struct clk *clk = ERR_PTR(-ENOENT);
21762 +       int idno;
21763 +
21764 +       if (dev == NULL || dev->bus != &platform_bus_type)
21765 +               idno = -1;
21766 +       else
21767 +               idno = to_platform_device(dev)->id;
21768 +
21769 +       spin_lock(&clocks_lock);
21770 +
21771 +       list_for_each_entry(p, &clocks, list) {
21772 +               if (p->id == idno &&
21773 +                   strcmp(id, p->name) == 0 &&
21774 +                   try_module_get(p->owner)) {
21775 +                       clk = p;
21776 +                       break;
21777 +               }
21778 +       }
21779 +
21780 +       /* check for the case where a device was supplied, but the
21781 +        * clock that was being searched for is not device specific */
21782 +
21783 +       if (IS_ERR(clk)) {
21784 +               list_for_each_entry(p, &clocks, list) {
21785 +                       if (p->id == -1 && strcmp(id, p->name) == 0 &&
21786 +                           try_module_get(p->owner)) {
21787 +                               clk = p;
21788 +                               break;
21789 +                       }
21790 +               }
21791 +       }
21792 +
21793 +       spin_unlock(&clocks_lock);
21794 +       return clk;
21795 +}
21796 +
21797 +void clk_put(struct clk *clk)
21798 +{
21799 +       module_put(clk->owner);
21800 +}
21801 +
21802 +int clk_enable(struct clk *clk)
21803 +{
21804 +       if (IS_ERR(clk) || clk == NULL)
21805 +               return -EINVAL;
21806 +
21807 +       clk_enable(clk->parent);
21808 +
21809 +       spin_lock(&clocks_lock);
21810 +
21811 +       if ((clk->usage++) == 0)
21812 +               (clk->enable)(clk, 1);
21813 +
21814 +       spin_unlock(&clocks_lock);
21815 +       return 0;
21816 +}
21817 +
21818 +void clk_disable(struct clk *clk)
21819 +{
21820 +       if (IS_ERR(clk) || clk == NULL)
21821 +               return;
21822 +
21823 +       spin_lock(&clocks_lock);
21824 +
21825 +       if ((--clk->usage) == 0)
21826 +               (clk->enable)(clk, 0);
21827 +
21828 +       spin_unlock(&clocks_lock);
21829 +       clk_disable(clk->parent);
21830 +}
21831 +
21832 +
21833 +unsigned long clk_get_rate(struct clk *clk)
21834 +{
21835 +       if (IS_ERR(clk))
21836 +               return 0;
21837 +
21838 +       if (clk->rate != 0)
21839 +               return clk->rate;
21840 +
21841 +       if (clk->get_rate != NULL)
21842 +               return (clk->get_rate)(clk);
21843 +
21844 +       if (clk->parent != NULL)
21845 +               return clk_get_rate(clk->parent);
21846 +
21847 +       return clk->rate;
21848 +}
21849 +
21850 +long clk_round_rate(struct clk *clk, unsigned long rate)
21851 +{
21852 +       if (!IS_ERR(clk) && clk->round_rate)
21853 +               return (clk->round_rate)(clk, rate);
21854 +
21855 +       return rate;
21856 +}
21857 +
21858 +int clk_set_rate(struct clk *clk, unsigned long rate)
21859 +{
21860 +       int ret;
21861 +
21862 +       if (IS_ERR(clk))
21863 +               return -EINVAL;
21864 +
21865 +       /* We do not default just do a clk->rate = rate as
21866 +        * the clock may have been made this way by choice.
21867 +        */
21868 +
21869 +       WARN_ON(clk->set_rate == NULL);
21870 +
21871 +       if (clk->set_rate == NULL)
21872 +               return -EINVAL;
21873 +
21874 +       spin_lock(&clocks_lock);
21875 +       ret = (clk->set_rate)(clk, rate);
21876 +       spin_unlock(&clocks_lock);
21877 +
21878 +       return ret;
21879 +}
21880 +
21881 +struct clk *clk_get_parent(struct clk *clk)
21882 +{
21883 +       return clk->parent;
21884 +}
21885 +
21886 +int clk_set_parent(struct clk *clk, struct clk *parent)
21887 +{
21888 +       int ret = 0;
21889 +
21890 +       if (IS_ERR(clk))
21891 +               return -EINVAL;
21892 +
21893 +       spin_lock(&clocks_lock);
21894 +
21895 +       if (clk->set_parent)
21896 +               ret = (clk->set_parent)(clk, parent);
21897 +
21898 +       spin_unlock(&clocks_lock);
21899 +
21900 +       return ret;
21901 +}
21902 +
21903 +EXPORT_SYMBOL(clk_get);
21904 +EXPORT_SYMBOL(clk_put);
21905 +EXPORT_SYMBOL(clk_enable);
21906 +EXPORT_SYMBOL(clk_disable);
21907 +EXPORT_SYMBOL(clk_get_rate);
21908 +EXPORT_SYMBOL(clk_round_rate);
21909 +EXPORT_SYMBOL(clk_set_rate);
21910 +EXPORT_SYMBOL(clk_get_parent);
21911 +EXPORT_SYMBOL(clk_set_parent);
21912 +
21913 +/* base clocks */
21914 +
21915 +static int clk_default_setrate(struct clk *clk, unsigned long rate)
21916 +{
21917 +       clk->rate = rate;
21918 +       return 0;
21919 +}
21920 +
21921 +struct clk clk_xtal = {
21922 +       .name           = "xtal",
21923 +       .id             = -1,
21924 +       .rate           = 0,
21925 +       .parent         = NULL,
21926 +       .ctrlbit        = 0,
21927 +};
21928 +
21929 +struct clk clk_ext = {
21930 +       .name           = "ext",
21931 +       .id             = -1,
21932 +};
21933 +
21934 +struct clk clk_epll = {
21935 +       .name           = "epll",
21936 +       .id             = -1,
21937 +};
21938 +
21939 +struct clk clk_mpll = {
21940 +       .name           = "mpll",
21941 +       .id             = -1,
21942 +       .set_rate       = clk_default_setrate,
21943 +};
21944 +
21945 +struct clk clk_upll = {
21946 +       .name           = "upll",
21947 +       .id             = -1,
21948 +       .parent         = NULL,
21949 +       .ctrlbit        = 0,
21950 +};
21951 +
21952 +struct clk clk_f = {
21953 +       .name           = "fclk",
21954 +       .id             = -1,
21955 +       .rate           = 0,
21956 +       .parent         = &clk_mpll,
21957 +       .ctrlbit        = 0,
21958 +       .set_rate       = clk_default_setrate,
21959 +};
21960 +
21961 +struct clk clk_h = {
21962 +       .name           = "hclk",
21963 +       .id             = -1,
21964 +       .rate           = 0,
21965 +       .parent         = NULL,
21966 +       .ctrlbit        = 0,
21967 +       .set_rate       = clk_default_setrate,
21968 +};
21969 +
21970 +struct clk clk_p = {
21971 +       .name           = "pclk",
21972 +       .id             = -1,
21973 +       .rate           = 0,
21974 +       .parent         = NULL,
21975 +       .ctrlbit        = 0,
21976 +       .set_rate       = clk_default_setrate,
21977 +};
21978 +
21979 +struct clk clk_usb_bus = {
21980 +       .name           = "usb-bus",
21981 +       .id             = -1,
21982 +       .rate           = 0,
21983 +       .parent         = &clk_upll,
21984 +};
21985 +
21986 +
21987 +
21988 +struct clk s3c24xx_uclk = {
21989 +       .name           = "uclk",
21990 +       .id             = -1,
21991 +};
21992 +
21993 +/* initialise the clock system */
21994 +
21995 +int s3c24xx_register_clock(struct clk *clk)
21996 +{
21997 +       clk->owner = THIS_MODULE;
21998 +
21999 +       if (clk->enable == NULL)
22000 +               clk->enable = clk_null_enable;
22001 +
22002 +       /* add to the list of available clocks */
22003 +
22004 +       /* Quick check to see if this clock has already been registered. */
22005 +       BUG_ON(clk->list.prev != clk->list.next);
22006 +
22007 +       spin_lock(&clocks_lock);
22008 +       list_add(&clk->list, &clocks);
22009 +       spin_unlock(&clocks_lock);
22010 +
22011 +       return 0;
22012 +}
22013 +
22014 +int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
22015 +{
22016 +       int fails = 0;
22017 +
22018 +       for (; nr_clks > 0; nr_clks--, clks++) {
22019 +               if (s3c24xx_register_clock(*clks) < 0)
22020 +                       fails++;
22021 +       }
22022 +
22023 +       return fails;
22024 +}
22025 +
22026 +/* initalise all the clocks */
22027 +
22028 +int __init s3c24xx_register_baseclocks(unsigned long xtal)
22029 +{
22030 +       printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
22031 +
22032 +       clk_xtal.rate = xtal;
22033 +
22034 +       /* register our clocks */
22035 +
22036 +       if (s3c24xx_register_clock(&clk_xtal) < 0)
22037 +               printk(KERN_ERR "failed to register master xtal\n");
22038 +
22039 +       if (s3c24xx_register_clock(&clk_mpll) < 0)
22040 +               printk(KERN_ERR "failed to register mpll clock\n");
22041 +
22042 +       if (s3c24xx_register_clock(&clk_upll) < 0)
22043 +               printk(KERN_ERR "failed to register upll clock\n");
22044 +
22045 +       if (s3c24xx_register_clock(&clk_f) < 0)
22046 +               printk(KERN_ERR "failed to register cpu fclk\n");
22047 +
22048 +       if (s3c24xx_register_clock(&clk_h) < 0)
22049 +               printk(KERN_ERR "failed to register cpu hclk\n");
22050 +
22051 +       if (s3c24xx_register_clock(&clk_p) < 0)
22052 +               printk(KERN_ERR "failed to register cpu pclk\n");
22053 +
22054 +       return 0;
22055 +}
22056 +
22057 Index: linux-2.6.28/arch/arm/plat-s3c/dev-fb.c
22058 ===================================================================
22059 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22060 +++ linux-2.6.28/arch/arm/plat-s3c/dev-fb.c     2009-01-02 00:01:56.000000000 +0100
22061 @@ -0,0 +1,72 @@
22062 +/* linux/arch/arm/plat-s3c/dev-fb.c
22063 + *
22064 + * Copyright 2008 Simtec Electronics
22065 + *     Ben Dooks <ben@simtec.co.uk>
22066 + *     http://armlinux.simtec.co.uk/
22067 + *
22068 + * S3C series device definition for framebuffer device
22069 + *
22070 + * This program is free software; you can redistribute it and/or modify
22071 + * it under the terms of the GNU General Public License version 2 as
22072 + * published by the Free Software Foundation.
22073 +*/
22074 +
22075 +#include <linux/kernel.h>
22076 +#include <linux/string.h>
22077 +#include <linux/platform_device.h>
22078 +#include <linux/fb.h>
22079 +
22080 +#include <mach/map.h>
22081 +#include <mach/regs-fb.h>
22082 +
22083 +#include <plat/fb.h>
22084 +#include <plat/devs.h>
22085 +#include <plat/cpu.h>
22086 +
22087 +static struct resource s3c_fb_resource[] = {
22088 +       [0] = {
22089 +               .start = S3C_PA_FB,
22090 +               .end   = S3C_PA_FB + SZ_16K - 1,
22091 +               .flags = IORESOURCE_MEM,
22092 +       },
22093 +       [1] = {
22094 +               .start = IRQ_LCD_VSYNC,
22095 +               .end   = IRQ_LCD_VSYNC,
22096 +               .flags = IORESOURCE_IRQ,
22097 +       },
22098 +       [2] = {
22099 +               .start = IRQ_LCD_FIFO,
22100 +               .end   = IRQ_LCD_FIFO,
22101 +               .flags = IORESOURCE_IRQ,
22102 +       },
22103 +       [3] = {
22104 +               .start = IRQ_LCD_SYSTEM,
22105 +               .end   = IRQ_LCD_SYSTEM,
22106 +               .flags = IORESOURCE_IRQ,
22107 +       },
22108 +};
22109 +
22110 +struct platform_device s3c_device_fb = {
22111 +       .name             = "s3c-fb",
22112 +       .id               = -1,
22113 +       .num_resources    = ARRAY_SIZE(s3c_fb_resource),
22114 +       .resource         = s3c_fb_resource,
22115 +       .dev.dma_mask     = &s3c_device_fb.dev.coherent_dma_mask,
22116 +       .dev.coherent_dma_mask = 0xffffffffUL,
22117 +};
22118 +
22119 +void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
22120 +{
22121 +       struct s3c_fb_platdata *npd;
22122 +
22123 +       if (!pd) {
22124 +               printk(KERN_ERR "%s: no platform data\n", __func__);
22125 +               return;
22126 +       }
22127 +
22128 +       npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
22129 +       if (!npd)
22130 +               printk(KERN_ERR "%s: no memory for platform data\n", __func__);
22131 +
22132 +       s3c_device_fb.dev.platform_data = npd;
22133 +}
22134 Index: linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc1.c
22135 ===================================================================
22136 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22137 +++ linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc1.c 2009-01-02 00:01:56.000000000 +0100
22138 @@ -0,0 +1,68 @@
22139 +/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
22140 + *
22141 + * Copyright (c) 2008 Simtec Electronics
22142 + *     Ben Dooks <ben@simtec.co.uk>
22143 + *     http://armlinux.simtec.co.uk/
22144 + *
22145 + * S3C series device definition for hsmmc device 1
22146 + *
22147 + * This program is free software; you can redistribute it and/or modify
22148 + * it under the terms of the GNU General Public License version 2 as
22149 + * published by the Free Software Foundation.
22150 +*/
22151 +
22152 +#include <linux/kernel.h>
22153 +#include <linux/platform_device.h>
22154 +#include <linux/mmc/host.h>
22155 +
22156 +#include <mach/map.h>
22157 +#include <plat/sdhci.h>
22158 +#include <plat/devs.h>
22159 +#include <plat/cpu.h>
22160 +
22161 +#define S3C_SZ_HSMMC   (0x1000)
22162 +
22163 +static struct resource s3c_hsmmc1_resource[] = {
22164 +       [0] = {
22165 +               .start = S3C_PA_HSMMC1,
22166 +               .end   = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
22167 +               .flags = IORESOURCE_MEM,
22168 +       },
22169 +       [1] = {
22170 +               .start = IRQ_HSMMC1,
22171 +               .end   = IRQ_HSMMC1,
22172 +               .flags = IORESOURCE_IRQ,
22173 +       }
22174 +};
22175 +
22176 +static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
22177 +
22178 +struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
22179 +       .max_width      = 4,
22180 +       .host_caps      = (MMC_CAP_4_BIT_DATA |
22181 +                          MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
22182 +};
22183 +
22184 +struct platform_device s3c_device_hsmmc1 = {
22185 +       .name           = "s3c-sdhci",
22186 +       .id             = 1,
22187 +       .num_resources  = ARRAY_SIZE(s3c_hsmmc1_resource),
22188 +       .resource       = s3c_hsmmc1_resource,
22189 +       .dev            = {
22190 +               .dma_mask               = &s3c_device_hsmmc1_dmamask,
22191 +               .coherent_dma_mask      = 0xffffffffUL,
22192 +               .platform_data          = &s3c_hsmmc1_def_platdata,
22193 +       },
22194 +};
22195 +
22196 +void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
22197 +{
22198 +       struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
22199 +
22200 +       set->max_width = pd->max_width;
22201 +
22202 +       if (pd->cfg_gpio)
22203 +               set->cfg_gpio = pd->cfg_gpio;
22204 +       if (pd->cfg_card)
22205 +               set->cfg_card = pd->cfg_card;
22206 +}
22207 Index: linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc.c
22208 ===================================================================
22209 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22210 +++ linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc.c  2009-01-02 00:01:56.000000000 +0100
22211 @@ -0,0 +1,68 @@
22212 +/* linux/arch/arm/plat-s3c/dev-hsmmc.c
22213 + *
22214 + * Copyright (c) 2008 Simtec Electronics
22215 + *     Ben Dooks <ben@simtec.co.uk>
22216 + *     http://armlinux.simtec.co.uk/
22217 + *
22218 + * S3C series device definition for hsmmc devices
22219 + *
22220 + * This program is free software; you can redistribute it and/or modify
22221 + * it under the terms of the GNU General Public License version 2 as
22222 + * published by the Free Software Foundation.
22223 +*/
22224 +
22225 +#include <linux/kernel.h>
22226 +#include <linux/platform_device.h>
22227 +#include <linux/mmc/host.h>
22228 +
22229 +#include <mach/map.h>
22230 +#include <plat/sdhci.h>
22231 +#include <plat/devs.h>
22232 +#include <plat/cpu.h>
22233 +
22234 +#define S3C_SZ_HSMMC   (0x1000)
22235 +
22236 +static struct resource s3c_hsmmc_resource[] = {
22237 +       [0] = {
22238 +               .start = S3C_PA_HSMMC0,
22239 +               .end   = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
22240 +               .flags = IORESOURCE_MEM,
22241 +       },
22242 +       [1] = {
22243 +               .start = IRQ_HSMMC0,
22244 +               .end   = IRQ_HSMMC0,
22245 +               .flags = IORESOURCE_IRQ,
22246 +       }
22247 +};
22248 +
22249 +static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
22250 +
22251 +struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
22252 +       .max_width      = 4,
22253 +       .host_caps      = (MMC_CAP_4_BIT_DATA |
22254 +                          MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
22255 +};
22256 +
22257 +struct platform_device s3c_device_hsmmc0 = {
22258 +       .name           = "s3c-sdhci",
22259 +       .id             = 0,
22260 +       .num_resources  = ARRAY_SIZE(s3c_hsmmc_resource),
22261 +       .resource       = s3c_hsmmc_resource,
22262 +       .dev            = {
22263 +               .dma_mask               = &s3c_device_hsmmc_dmamask,
22264 +               .coherent_dma_mask      = 0xffffffffUL,
22265 +               .platform_data          = &s3c_hsmmc0_def_platdata,
22266 +       },
22267 +};
22268 +
22269 +void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
22270 +{
22271 +       struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
22272 +
22273 +       set->max_width = pd->max_width;
22274 +
22275 +       if (pd->cfg_gpio)
22276 +               set->cfg_gpio = pd->cfg_gpio;
22277 +       if (pd->cfg_card)
22278 +               set->cfg_card = pd->cfg_card;
22279 +}
22280 Index: linux-2.6.28/arch/arm/plat-s3c/dev-i2c0.c
22281 ===================================================================
22282 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22283 +++ linux-2.6.28/arch/arm/plat-s3c/dev-i2c0.c   2009-01-02 00:01:56.000000000 +0100
22284 @@ -0,0 +1,71 @@
22285 +/* linux/arch/arm/plat-s3c/dev-i2c0.c
22286 + *
22287 + * Copyright 2008 Simtec Electronics
22288 + *     Ben Dooks <ben@simtec.co.uk>
22289 + *     http://armlinux.simtec.co.uk/
22290 + *
22291 + * S3C series device definition for i2c device 0
22292 + *
22293 + * This program is free software; you can redistribute it and/or modify
22294 + * it under the terms of the GNU General Public License version 2 as
22295 + * published by the Free Software Foundation.
22296 +*/
22297 +
22298 +#include <linux/kernel.h>
22299 +#include <linux/string.h>
22300 +#include <linux/platform_device.h>
22301 +
22302 +#include <mach/map.h>
22303 +
22304 +#include <plat/regs-iic.h>
22305 +#include <plat/iic.h>
22306 +#include <plat/devs.h>
22307 +#include <plat/cpu.h>
22308 +
22309 +static struct resource s3c_i2c_resource[] = {
22310 +       [0] = {
22311 +               .start = S3C_PA_IIC,
22312 +               .end   = S3C_PA_IIC + SZ_4K - 1,
22313 +               .flags = IORESOURCE_MEM,
22314 +       },
22315 +       [1] = {
22316 +               .start = IRQ_IIC,
22317 +               .end   = IRQ_IIC,
22318 +               .flags = IORESOURCE_IRQ,
22319 +       },
22320 +};
22321 +
22322 +struct platform_device s3c_device_i2c0 = {
22323 +       .name             = "s3c2410-i2c",
22324 +#ifdef CONFIG_S3C_DEV_I2C1
22325 +       .id               = 0,
22326 +#else
22327 +       .id               = -1,
22328 +#endif
22329 +       .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
22330 +       .resource         = s3c_i2c_resource,
22331 +};
22332 +
22333 +static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
22334 +       .flags          = 0,
22335 +       .slave_addr     = 0x10,
22336 +       .bus_freq       = 100*1000,
22337 +       .max_freq       = 400*1000,
22338 +       .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
22339 +};
22340 +
22341 +void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
22342 +{
22343 +       struct s3c2410_platform_i2c *npd;
22344 +
22345 +       if (!pd)
22346 +               pd = &default_i2c_data0;
22347 +
22348 +       npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
22349 +       if (!npd)
22350 +               printk(KERN_ERR "%s: no memory for platform data\n", __func__);
22351 +       else if (!npd->cfg_gpio)
22352 +               npd->cfg_gpio = s3c_i2c0_cfg_gpio;
22353 +
22354 +       s3c_device_i2c0.dev.platform_data = npd;
22355 +}
22356 Index: linux-2.6.28/arch/arm/plat-s3c/dev-i2c1.c
22357 ===================================================================
22358 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22359 +++ linux-2.6.28/arch/arm/plat-s3c/dev-i2c1.c   2009-01-02 00:01:56.000000000 +0100
22360 @@ -0,0 +1,68 @@
22361 +/* linux/arch/arm/plat-s3c/dev-i2c1.c
22362 + *
22363 + * Copyright 2008 Simtec Electronics
22364 + *     Ben Dooks <ben@simtec.co.uk>
22365 + *     http://armlinux.simtec.co.uk/
22366 + *
22367 + * S3C series device definition for i2c device 1
22368 + *
22369 + * This program is free software; you can redistribute it and/or modify
22370 + * it under the terms of the GNU General Public License version 2 as
22371 + * published by the Free Software Foundation.
22372 +*/
22373 +
22374 +#include <linux/kernel.h>
22375 +#include <linux/string.h>
22376 +#include <linux/platform_device.h>
22377 +
22378 +#include <mach/map.h>
22379 +
22380 +#include <plat/regs-iic.h>
22381 +#include <plat/iic.h>
22382 +#include <plat/devs.h>
22383 +#include <plat/cpu.h>
22384 +
22385 +static struct resource s3c_i2c_resource[] = {
22386 +       [0] = {
22387 +               .start = S3C_PA_IIC1,
22388 +               .end   = S3C_PA_IIC1 + SZ_4K - 1,
22389 +               .flags = IORESOURCE_MEM,
22390 +       },
22391 +       [1] = {
22392 +               .start = IRQ_IIC1,
22393 +               .end   = IRQ_IIC1,
22394 +               .flags = IORESOURCE_IRQ,
22395 +       },
22396 +};
22397 +
22398 +struct platform_device s3c_device_i2c1 = {
22399 +       .name             = "s3c2410-i2c",
22400 +       .id               = 1,
22401 +       .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
22402 +       .resource         = s3c_i2c_resource,
22403 +};
22404 +
22405 +static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
22406 +       .flags          = 0,
22407 +       .bus_num        = 1,
22408 +       .slave_addr     = 0x10,
22409 +       .bus_freq       = 100*1000,
22410 +       .max_freq       = 400*1000,
22411 +       .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
22412 +};
22413 +
22414 +void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
22415 +{
22416 +       struct s3c2410_platform_i2c *npd;
22417 +
22418 +       if (!pd)
22419 +               pd = &default_i2c_data1;
22420 +
22421 +       npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
22422 +       if (!npd)
22423 +               printk(KERN_ERR "%s: no memory for platform data\n", __func__);
22424 +       else if (!npd->cfg_gpio)
22425 +               npd->cfg_gpio = s3c_i2c1_cfg_gpio;
22426 +
22427 +       s3c_device_i2c1.dev.platform_data = npd;
22428 +}
22429 Index: linux-2.6.28/arch/arm/plat-s3c/gpio.c
22430 ===================================================================
22431 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22432 +++ linux-2.6.28/arch/arm/plat-s3c/gpio.c       2009-01-02 00:01:56.000000000 +0100
22433 @@ -0,0 +1,156 @@
22434 +/* linux/arch/arm/plat-s3c/gpio.c
22435 + *
22436 + * Copyright 2008 Simtec Electronics
22437 + *     Ben Dooks <ben@simtec.co.uk>
22438 + *     http://armlinux.simtec.co.uk/
22439 + *
22440 + * S3C series GPIO core
22441 + *
22442 + * This program is free software; you can redistribute it and/or modify
22443 + * it under the terms of the GNU General Public License version 2 as
22444 + * published by the Free Software Foundation.
22445 +*/
22446 +
22447 +#include <linux/kernel.h>
22448 +#include <linux/init.h>
22449 +#include <linux/io.h>
22450 +#include <linux/gpio.h>
22451 +
22452 +#include <mach/gpio-core.h>
22453 +
22454 +#ifdef CONFIG_S3C_GPIO_TRACK
22455 +struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
22456 +
22457 +static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
22458 +{
22459 +       unsigned int gpn;
22460 +       int i;
22461 +
22462 +       gpn = chip->chip.base;
22463 +       for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
22464 +               BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
22465 +               s3c_gpios[gpn] = chip;
22466 +       }
22467 +}
22468 +#endif /* CONFIG_S3C_GPIO_TRACK */
22469 +
22470 +/* Default routines for controlling GPIO, based on the original S3C24XX
22471 + * GPIO functions which deal with the case where each gpio bank of the
22472 + * chip is as following:
22473 + *
22474 + * base + 0x00: Control register, 2 bits per gpio
22475 + *             gpio n: 2 bits starting at (2*n)
22476 + *             00 = input, 01 = output, others mean special-function
22477 + * base + 0x04: Data register, 1 bit per gpio
22478 + *             bit n: data bit n
22479 +*/
22480 +
22481 +static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
22482 +{
22483 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22484 +       void __iomem *base = ourchip->base;
22485 +       unsigned long flags;
22486 +       unsigned long con;
22487 +
22488 +       local_irq_save(flags);
22489 +
22490 +       con = __raw_readl(base + 0x00);
22491 +       con &= ~(3 << (offset * 2));
22492 +
22493 +       __raw_writel(con, base + 0x00);
22494 +
22495 +       local_irq_restore(flags);
22496 +       return 0;
22497 +}
22498 +
22499 +static int s3c_gpiolib_output(struct gpio_chip *chip,
22500 +                             unsigned offset, int value)
22501 +{
22502 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22503 +       void __iomem *base = ourchip->base;
22504 +       unsigned long flags;
22505 +       unsigned long dat;
22506 +       unsigned long con;
22507 +
22508 +       local_irq_save(flags);
22509 +
22510 +       dat = __raw_readl(base + 0x04);
22511 +       dat &= ~(1 << offset);
22512 +       if (value)
22513 +               dat |= 1 << offset;
22514 +       __raw_writel(dat, base + 0x04);
22515 +
22516 +       con = __raw_readl(base + 0x00);
22517 +       con &= ~(3 << (offset * 2));
22518 +       con |= 1 << (offset * 2);
22519 +
22520 +       __raw_writel(con, base + 0x00);
22521 +       __raw_writel(dat, base + 0x04);
22522 +
22523 +       local_irq_restore(flags);
22524 +       return 0;
22525 +}
22526 +
22527 +static void s3c_gpiolib_set(struct gpio_chip *chip,
22528 +                           unsigned offset, int value)
22529 +{
22530 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22531 +       void __iomem *base = ourchip->base;
22532 +       unsigned long flags;
22533 +       unsigned long dat;
22534 +
22535 +       local_irq_save(flags);
22536 +
22537 +       dat = __raw_readl(base + 0x04);
22538 +       dat &= ~(1 << offset);
22539 +       if (value)
22540 +               dat |= 1 << offset;
22541 +       __raw_writel(dat, base + 0x04);
22542 +
22543 +       local_irq_restore(flags);
22544 +}
22545 +
22546 +static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
22547 +{
22548 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
22549 +       unsigned long val;
22550 +
22551 +       val = __raw_readl(ourchip->base + 0x04);
22552 +       val >>= offset;
22553 +       val &= 1;
22554 +
22555 +       return val;
22556 +}
22557 +
22558 +__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
22559 +{
22560 +       struct gpio_chip *gc = &chip->chip;
22561 +       int ret;
22562 +
22563 +       BUG_ON(!chip->base);
22564 +       BUG_ON(!gc->label);
22565 +       BUG_ON(!gc->ngpio);
22566 +
22567 +       if (!gc->direction_input)
22568 +               gc->direction_input = s3c_gpiolib_input;
22569 +       if (!gc->direction_output)
22570 +               gc->direction_output = s3c_gpiolib_output;
22571 +       if (!gc->set)
22572 +               gc->set = s3c_gpiolib_set;
22573 +       if (!gc->get)
22574 +               gc->get = s3c_gpiolib_get;
22575 +
22576 +#ifdef CONFIG_PM
22577 +       if (chip->pm != NULL) {
22578 +               if (!chip->pm->save || !chip->pm->resume)
22579 +                       printk(KERN_ERR "gpio: %s has missing PM functions\n",
22580 +                              gc->label);
22581 +       } else
22582 +               printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
22583 +#endif
22584 +
22585 +       /* gpiochip_add() prints own failure message on error. */
22586 +       ret = gpiochip_add(gc);
22587 +       if (ret >= 0)
22588 +               s3c_gpiolib_track(chip);
22589 +}
22590 Index: linux-2.6.28/arch/arm/plat-s3c/gpio-config.c
22591 ===================================================================
22592 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22593 +++ linux-2.6.28/arch/arm/plat-s3c/gpio-config.c        2009-01-02 00:01:56.000000000 +0100
22594 @@ -0,0 +1,163 @@
22595 +/* linux/arch/arm/plat-s3c/gpio-config.c
22596 + *
22597 + * Copyright 2008 Openmoko, Inc.
22598 + * Copyright 2008 Simtec Electronics
22599 + *     Ben Dooks <ben@simtec.co.uk>
22600 + *     http://armlinux.simtec.co.uk/
22601 + *
22602 + * S3C series GPIO configuration core
22603 + *
22604 + * This program is free software; you can redistribute it and/or modify
22605 + * it under the terms of the GNU General Public License version 2 as
22606 + * published by the Free Software Foundation.
22607 +*/
22608 +
22609 +#include <linux/kernel.h>
22610 +#include <linux/gpio.h>
22611 +#include <linux/io.h>
22612 +
22613 +#include <mach/gpio-core.h>
22614 +#include <plat/gpio-cfg.h>
22615 +#include <plat/gpio-cfg-helpers.h>
22616 +
22617 +int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
22618 +{
22619 +       struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
22620 +       unsigned long flags;
22621 +       int offset;
22622 +       int ret;
22623 +
22624 +       if (!chip)
22625 +               return -EINVAL;
22626 +
22627 +       offset = pin - chip->chip.base;
22628 +
22629 +       local_irq_save(flags);
22630 +       ret = s3c_gpio_do_setcfg(chip, offset, config);
22631 +       local_irq_restore(flags);
22632 +
22633 +       return ret;
22634 +}
22635 +
22636 +int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
22637 +{
22638 +       struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
22639 +       unsigned long flags;
22640 +       int offset, ret;
22641 +
22642 +       if (!chip)
22643 +               return -EINVAL;
22644 +
22645 +       offset = pin - chip->chip.base;
22646 +
22647 +       local_irq_save(flags);
22648 +       ret = s3c_gpio_do_setpull(chip, offset, pull);
22649 +       local_irq_restore(flags);
22650 +
22651 +       return ret;
22652 +}
22653 +
22654 +#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
22655 +int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
22656 +                                 unsigned int off, unsigned int cfg)
22657 +{
22658 +       void __iomem *reg = chip->base;
22659 +       unsigned int shift = off;
22660 +       u32 con;
22661 +
22662 +       if (s3c_gpio_is_cfg_special(cfg)) {
22663 +               cfg &= 0xf;
22664 +
22665 +               /* Map output to 0, and SFN2 to 1 */
22666 +               cfg -= 1;
22667 +               if (cfg > 1)
22668 +                       return -EINVAL;
22669 +
22670 +               cfg <<= shift;
22671 +       }
22672 +
22673 +       con = __raw_readl(reg);
22674 +       con &= ~(0x1 << shift);
22675 +       con |= cfg;
22676 +       __raw_writel(con, reg);
22677 +
22678 +       return 0;
22679 +}
22680 +
22681 +int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
22682 +                           unsigned int off, unsigned int cfg)
22683 +{
22684 +       void __iomem *reg = chip->base;
22685 +       unsigned int shift = off * 2;
22686 +       u32 con;
22687 +
22688 +       if (s3c_gpio_is_cfg_special(cfg)) {
22689 +               cfg &= 0xf;
22690 +               if (cfg > 3)
22691 +                       return -EINVAL;
22692 +
22693 +               cfg <<= shift;
22694 +       }
22695 +
22696 +       con = __raw_readl(reg);
22697 +       con &= ~(0x3 << shift);
22698 +       con |= cfg;
22699 +       __raw_writel(con, reg);
22700 +
22701 +       return 0;
22702 +}
22703 +#endif
22704 +
22705 +#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
22706 +int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
22707 +                                unsigned int off, unsigned int cfg)
22708 +{
22709 +       void __iomem *reg = chip->base;
22710 +       unsigned int shift = (off & 7) * 4;
22711 +       u32 con;
22712 +
22713 +       if (off < 8 && chip->chip.ngpio >= 8)
22714 +               reg -= 4;
22715 +
22716 +       if (s3c_gpio_is_cfg_special(cfg)) {
22717 +               cfg &= 0xf;
22718 +               cfg <<= shift;
22719 +       }
22720 +
22721 +       con = __raw_readl(reg);
22722 +       con &= ~(0xf << shift);
22723 +       con |= cfg;
22724 +       __raw_writel(con, reg);
22725 +
22726 +       return 0;
22727 +}
22728 +#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
22729 +
22730 +#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
22731 +int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
22732 +                           unsigned int off, s3c_gpio_pull_t pull)
22733 +{
22734 +       void __iomem *reg = chip->base + 0x08;
22735 +       int shift = off * 2;
22736 +       u32 pup;
22737 +
22738 +       pup = __raw_readl(reg);
22739 +       pup &= ~(3 << shift);
22740 +       pup |= pull << shift;
22741 +       __raw_writel(pup, reg);
22742 +
22743 +       return 0;
22744 +}
22745 +
22746 +s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
22747 +                                       unsigned int off)
22748 +{
22749 +       void __iomem *reg = chip->base + 0x08;
22750 +       int shift = off * 2;
22751 +       u32 pup = __raw_readl(reg);
22752 +
22753 +       pup >>= shift;
22754 +       pup &= 0x3;
22755 +       return (__force s3c_gpio_pull_t)pup;
22756 +}
22757 +#endif
22758 Index: linux-2.6.28/arch/arm/plat-s3c/include/mach/io.h
22759 ===================================================================
22760 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22761 +++ linux-2.6.28/arch/arm/plat-s3c/include/mach/io.h    2009-01-02 00:01:56.000000000 +0100
22762 @@ -0,0 +1,18 @@
22763 +/* arch/arm/plat-s3c/include/mach/io.h
22764 + *
22765 + * Copyright 2008 Simtec Electronics
22766 + *     Ben Dooks <ben-linux@fluff.org>
22767 + *
22768 + * Default IO routines for plat-s3c based systems, such as S3C24A0
22769 + */
22770 +
22771 +#ifndef __ASM_ARM_ARCH_IO_H
22772 +#define __ASM_ARM_ARCH_IO_H
22773 +
22774 +/* No current ISA/PCI bus support. */
22775 +#define __io(a)                ((void __iomem *)(a))
22776 +#define __mem_pci(a)   (a)
22777 +
22778 +#define IO_SPACE_LIMIT (0xFFFFFFFF)
22779 +
22780 +#endif
22781 Index: linux-2.6.28/arch/arm/plat-s3c/include/mach/timex.h
22782 ===================================================================
22783 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22784 +++ linux-2.6.28/arch/arm/plat-s3c/include/mach/timex.h 2009-01-02 00:01:56.000000000 +0100
22785 @@ -0,0 +1,26 @@
22786 +/* arch/arm/mach-s3c2410/include/mach/timex.h
22787 + *
22788 + * Copyright (c) 2003-2005 Simtec Electronics
22789 + *     Ben Dooks <ben@simtec.co.uk>
22790 + *
22791 + * S3C2410 - time parameters
22792 + *
22793 + * This program is free software; you can redistribute it and/or modify
22794 + * it under the terms of the GNU General Public License version 2 as
22795 + * published by the Free Software Foundation.
22796 +*/
22797 +
22798 +#ifndef __ASM_ARCH_TIMEX_H
22799 +#define __ASM_ARCH_TIMEX_H
22800 +
22801 +/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
22802 + * a variable is useless. It seems as long as we make our timers an
22803 + * exact multiple of HZ, any value that makes a 1->1 correspondence
22804 + * for the time conversion functions to/from jiffies is acceptable.
22805 +*/
22806 +
22807 +
22808 +#define CLOCK_TICK_RATE 12000000
22809 +
22810 +
22811 +#endif /* __ASM_ARCH_TIMEX_H */
22812 Index: linux-2.6.28/arch/arm/plat-s3c/include/mach/vmalloc.h
22813 ===================================================================
22814 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22815 +++ linux-2.6.28/arch/arm/plat-s3c/include/mach/vmalloc.h       2009-01-02 00:01:56.000000000 +0100
22816 @@ -0,0 +1,20 @@
22817 +/* arch/arm/plat-s3c/include/mach/vmalloc.h
22818 + *
22819 + * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
22820 + *
22821 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
22822 + *                   http://www.simtec.co.uk/products/SWLINUX/
22823 + *
22824 + * This program is free software; you can redistribute it and/or modify
22825 + * it under the terms of the GNU General Public License version 2 as
22826 + * published by the Free Software Foundation.
22827 + *
22828 + * S3C2410 vmalloc definition
22829 +*/
22830 +
22831 +#ifndef __ASM_ARCH_VMALLOC_H
22832 +#define __ASM_ARCH_VMALLOC_H
22833 +
22834 +#define VMALLOC_END      (0xE0000000)
22835 +
22836 +#endif /* __ASM_ARCH_VMALLOC_H */
22837 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/clock.h
22838 ===================================================================
22839 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22840 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/clock.h 2009-01-02 00:01:56.000000000 +0100
22841 @@ -0,0 +1,88 @@
22842 +/* linux/arch/arm/plat-s3c/include/plat/clock.h
22843 + *
22844 + * Copyright (c) 2004-2005 Simtec Electronics
22845 + *     http://www.simtec.co.uk/products/SWLINUX/
22846 + *     Written by Ben Dooks, <ben@simtec.co.uk>
22847 + *
22848 + * This program is free software; you can redistribute it and/or modify
22849 + * it under the terms of the GNU General Public License version 2 as
22850 + * published by the Free Software Foundation.
22851 +*/
22852 +
22853 +#include <linux/spinlock.h>
22854 +
22855 +struct clk {
22856 +       struct list_head      list;
22857 +       struct module        *owner;
22858 +       struct clk           *parent;
22859 +       const char           *name;
22860 +       int                   id;
22861 +       int                   usage;
22862 +       unsigned long         rate;
22863 +       unsigned long         ctrlbit;
22864 +
22865 +       int                 (*enable)(struct clk *, int enable);
22866 +       int                 (*set_rate)(struct clk *c, unsigned long rate);
22867 +       unsigned long       (*get_rate)(struct clk *c);
22868 +       unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
22869 +       int                 (*set_parent)(struct clk *c, struct clk *parent);
22870 +};
22871 +
22872 +/* other clocks which may be registered by board support */
22873 +
22874 +extern struct clk s3c24xx_dclk0;
22875 +extern struct clk s3c24xx_dclk1;
22876 +extern struct clk s3c24xx_clkout0;
22877 +extern struct clk s3c24xx_clkout1;
22878 +extern struct clk s3c24xx_uclk;
22879 +
22880 +extern struct clk clk_usb_bus;
22881 +
22882 +/* core clock support */
22883 +
22884 +extern struct clk clk_f;
22885 +extern struct clk clk_h;
22886 +extern struct clk clk_p;
22887 +extern struct clk clk_mpll;
22888 +extern struct clk clk_upll;
22889 +extern struct clk clk_epll;
22890 +extern struct clk clk_xtal;
22891 +extern struct clk clk_ext;
22892 +
22893 +/* S3C64XX specific clocks */
22894 +extern struct clk clk_27m;
22895 +extern struct clk clk_48m;
22896 +
22897 +/* exports for arch/arm/mach-s3c2410
22898 + *
22899 + * Please DO NOT use these outside of arch/arm/mach-s3c2410
22900 +*/
22901 +
22902 +extern spinlock_t clocks_lock;
22903 +
22904 +extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
22905 +
22906 +extern int s3c24xx_register_clock(struct clk *clk);
22907 +extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
22908 +
22909 +extern int s3c24xx_register_baseclocks(unsigned long xtal);
22910 +
22911 +extern void s3c64xx_register_clocks(void);
22912 +
22913 +extern void s3c24xx_setup_clocks(unsigned long fclk,
22914 +                                unsigned long hclk,
22915 +                                unsigned long pclk);
22916 +
22917 +extern void s3c2410_setup_clocks(void);
22918 +extern void s3c2412_setup_clocks(void);
22919 +extern void s3c244x_setup_clocks(void);
22920 +extern void s3c2443_setup_clocks(void);
22921 +
22922 +/* S3C64XX specific functions and clocks */
22923 +
22924 +extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
22925 +
22926 +/* Init for pwm clock code */
22927 +
22928 +extern void s3c_pwmclk_init(void);
22929 +
22930 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu-freq.h
22931 ===================================================================
22932 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
22933 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu-freq.h      2009-01-02 00:01:56.000000000 +0100
22934 @@ -0,0 +1,94 @@
22935 +/* arch/arm/plat-s3c/include/plat/cpu-freq.h
22936 + *
22937 + * Copyright (c) 2006,2007 Simtec Electronics
22938 + *     http://armlinux.simtec.co.uk/
22939 + *     Ben Dooks <ben@simtec.co.uk>
22940 + *
22941 + * S3C CPU frequency scaling support - driver and board
22942 + *
22943 + * This program is free software; you can redistribute it and/or modify
22944 + * it under the terms of the GNU General Public License version 2 as
22945 + * published by the Free Software Foundation.
22946 +*/
22947 +
22948 +#include <linux/cpufreq.h>
22949 +
22950 +struct s3c_cpufreq_info;
22951 +struct s3c_cpufreq_board;
22952 +struct s3c_iotimings;
22953 +
22954 +struct s3c_freq {
22955 +       unsigned long   fclk;
22956 +       unsigned long   armclk;
22957 +       unsigned long   hclk_tns;       /* in 10ths of ns */
22958 +       unsigned long   hclk;
22959 +       unsigned long   pclk;
22960 +};
22961 +
22962 +/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
22963 + * notification can use this information that is not provided by just
22964 + * having the core frequency alone.
22965 + */
22966 +
22967 +struct s3c_cpufreq_freqs {
22968 +       struct cpufreq_freqs    freqs;
22969 +       struct s3c_freq         old;
22970 +       struct s3c_freq         new;
22971 +};
22972 +
22973 +#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
22974 +
22975 +struct s3c_clkdivs {
22976 +       int             p_divisor;      /* fclk / pclk */
22977 +       int             h_divisor;      /* fclk / hclk */
22978 +       int             arm_divisor;    /* not all cpus have this. */
22979 +       unsigned char   dvs;            /* using dvs mode to arm. */
22980 +};
22981 +
22982 +#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
22983 +
22984 +struct s3c_pllval {
22985 +       unsigned long           freq;
22986 +       unsigned long           pll_reg;
22987 +};
22988 +
22989 +struct s3c_cpufreq_config {
22990 +       struct s3c_freq         freq;
22991 +       struct s3c_pllval       pll;
22992 +       struct s3c_clkdivs      divs;
22993 +       struct s3c_cpufreq_info *info;  /* for core, not drivers */
22994 +       struct s3c_cpufreq_board *board;
22995 +};
22996 +
22997 +/* s3c_cpufreq_board
22998 + *
22999 + * per-board configuraton information, such as memory refresh and
23000 + * how to initialise IO timings.
23001 + */
23002 +struct s3c_cpufreq_board {
23003 +       unsigned int    refresh;        /* refresh period in ns */
23004 +       unsigned int    auto_io:1;      /* automatically init io timings. */
23005 +       unsigned int    need_io:1;      /* set if needs io timing support. */
23006 +
23007 +       /* any non-zero field in here is taken as an upper limit. */
23008 +       struct s3c_freq max;    /* frequency limits */
23009 +};
23010 +
23011 +/* Things depending on frequency scaling. */
23012 +#ifdef CONFIG_CPU_FREQ_S3C
23013 +#define __init_or_cpufreq
23014 +#else
23015 +#define __init_or_cpufreq __init
23016 +#endif
23017 +
23018 +/* Board functions */
23019 +
23020 +#ifdef CONFIG_CPU_FREQ_S3C
23021 +extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
23022 +#else
23023 +
23024 +static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
23025 +{
23026 +       return 0;
23027 +}
23028 +#endif  /* CONFIG_CPU_FREQ_S3C */
23029 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu.h
23030 ===================================================================
23031 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23032 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu.h   2009-01-02 00:01:56.000000000 +0100
23033 @@ -0,0 +1,74 @@
23034 +/* linux/arch/arm/plat-s3c/include/plat/cpu.h
23035 + *
23036 + * Copyright (c) 2004-2005 Simtec Electronics
23037 + *     Ben Dooks <ben@simtec.co.uk>
23038 + *
23039 + * Header file for S3C24XX CPU support
23040 + *
23041 + * This program is free software; you can redistribute it and/or modify
23042 + * it under the terms of the GNU General Public License version 2 as
23043 + * published by the Free Software Foundation.
23044 +*/
23045 +
23046 +/* todo - fix when rmk changes iodescs to use `void __iomem *` */
23047 +
23048 +#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
23049 +
23050 +#ifndef MHZ
23051 +#define MHZ (1000*1000)
23052 +#endif
23053 +
23054 +#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
23055 +
23056 +/* forward declaration */
23057 +struct s3c24xx_uart_resources;
23058 +struct platform_device;
23059 +struct s3c2410_uartcfg;
23060 +struct map_desc;
23061 +
23062 +/* per-cpu initialisation function table. */
23063 +
23064 +struct cpu_table {
23065 +       unsigned long   idcode;
23066 +       unsigned long   idmask;
23067 +       void            (*map_io)(void);
23068 +       void            (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
23069 +       void            (*init_clocks)(int xtal);
23070 +       int             (*init)(void);
23071 +       const char      *name;
23072 +};
23073 +
23074 +extern void s3c_init_cpu(unsigned long idcode,
23075 +                        struct cpu_table *cpus, unsigned int cputab_size);
23076 +
23077 +/* core initialisation functions */
23078 +
23079 +extern void s3c24xx_init_irq(void);
23080 +extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
23081 +
23082 +extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
23083 +extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
23084 +
23085 +extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
23086 +
23087 +extern void s3c24xx_init_clocks(int xtal);
23088 +
23089 +extern void s3c24xx_init_uartdevs(char *name,
23090 +                                 struct s3c24xx_uart_resources *res,
23091 +                                 struct s3c2410_uartcfg *cfg, int no);
23092 +
23093 +/* timer for 2410/2440 */
23094 +
23095 +struct sys_timer;
23096 +extern struct sys_timer s3c24xx_timer;
23097 +
23098 +/* system device classes */
23099 +
23100 +extern struct sysdev_class s3c2410_sysclass;
23101 +extern struct sysdev_class s3c2412_sysclass;
23102 +extern struct sysdev_class s3c2440_sysclass;
23103 +extern struct sysdev_class s3c2442_sysclass;
23104 +extern struct sysdev_class s3c2443_sysclass;
23105 +extern struct sysdev_class s3c6410_sysclass;
23106 +extern struct sysdev_class s3c64xx_sysclass;
23107 +
23108 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/debug-macro.S
23109 ===================================================================
23110 --- linux-2.6.28.orig/arch/arm/plat-s3c/include/plat/debug-macro.S      2008-12-25 00:26:37.000000000 +0100
23111 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/debug-macro.S   2009-01-02 00:01:56.000000000 +0100
23112 @@ -20,7 +20,7 @@
23113         .endm
23114
23115  #ifndef fifo_level
23116 -#define fifo_level fifo_level_s3c2410
23117 +#define fifo_level fifo_level_s3c2440
23118  #endif
23119
23120         .macro  fifo_full_s3c2440 rd, rx
23121 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/devs.h
23122 ===================================================================
23123 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23124 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/devs.h  2009-01-02 00:01:56.000000000 +0100
23125 @@ -0,0 +1,55 @@
23126 +/* linux/include/asm-arm/plat-s3c24xx/devs.h
23127 + *
23128 + * Copyright (c) 2004 Simtec Electronics
23129 + * Ben Dooks <ben@simtec.co.uk>
23130 + *
23131 + * Header file for s3c2410 standard platform devices
23132 + *
23133 + * This program is free software; you can redistribute it and/or modify
23134 + * it under the terms of the GNU General Public License version 2 as
23135 + * published by the Free Software Foundation.
23136 +*/
23137 +#include <linux/platform_device.h>
23138 +
23139 +struct s3c24xx_uart_resources {
23140 +       struct resource         *resources;
23141 +       unsigned long            nr_resources;
23142 +};
23143 +
23144 +extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
23145 +extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
23146 +
23147 +extern struct platform_device *s3c24xx_uart_devs[];
23148 +extern struct platform_device *s3c24xx_uart_src[];
23149 +
23150 +extern struct platform_device s3c_device_timer[];
23151 +
23152 +extern struct platform_device s3c_device_fb;
23153 +extern struct platform_device s3c_device_usb;
23154 +extern struct platform_device s3c_device_lcd;
23155 +extern struct platform_device s3c_device_wdt;
23156 +extern struct platform_device s3c_device_i2c0;
23157 +extern struct platform_device s3c_device_i2c1;
23158 +extern struct platform_device s3c_device_iis;
23159 +extern struct platform_device s3c_device_rtc;
23160 +extern struct platform_device s3c_device_adc;
23161 +extern struct platform_device s3c_device_sdi;
23162 +extern struct platform_device s3c_device_hsmmc0;
23163 +extern struct platform_device s3c_device_hsmmc1;
23164 +extern struct platform_device s3c_device_hsmmc2;
23165 +
23166 +extern struct platform_device s3c_device_spi0;
23167 +extern struct platform_device s3c_device_spi1;
23168 +
23169 +extern struct platform_device s3c_device_nand;
23170 +
23171 +extern struct platform_device s3c_device_usbgadget;
23172 +
23173 +extern struct platform_device s3c_device_ts;
23174 +
23175 +/* s3c2440 specific devices */
23176 +
23177 +#ifdef CONFIG_CPU_S3C2440
23178 +
23179 +extern struct platform_device s3c_device_camif;
23180 +#endif
23181 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/fb.h
23182 ===================================================================
23183 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23184 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/fb.h    2009-01-02 00:01:56.000000000 +0100
23185 @@ -0,0 +1,73 @@
23186 +/* linux/arch/arm/plat-s3c/include/plat/fb.h
23187 + *
23188 + * Copyright 2008 Openmoko, Inc.
23189 + * Copyright 2008 Simtec Electronics
23190 + *     http://armlinux.simtec.co.uk/
23191 + *     Ben Dooks <ben@simtec.co.uk>
23192 + *
23193 + * S3C - FB platform data definitions
23194 + *
23195 + * This program is free software; you can redistribute it and/or modify
23196 + * it under the terms of the GNU General Public License version 2 as
23197 + * published by the Free Software Foundation.
23198 +*/
23199 +
23200 +#ifndef __PLAT_S3C_FB_H
23201 +#define __PLAT_S3C_FB_H __FILE__
23202 +
23203 +/**
23204 + * struct s3c_fb_pd_win - per window setup data
23205 + * @win_mode: The display parameters to initialise (not for window 0)
23206 + * @virtual_x: The virtual X size.
23207 + * @virtual_y: The virtual Y size.
23208 + */
23209 +struct s3c_fb_pd_win {
23210 +       struct fb_videomode     win_mode;
23211 +
23212 +       unsigned short          default_bpp;
23213 +       unsigned short          max_bpp;
23214 +       unsigned short          virtual_x;
23215 +       unsigned short          virtual_y;
23216 +};
23217 +
23218 +/**
23219 + * struct s3c_fb_platdata -  S3C driver platform specific information
23220 + * @setup_gpio: Setup the external GPIO pins to the right state to transfer
23221 + *             the data from the display system to the connected display
23222 + *             device.
23223 + * @vidcon0: The base vidcon0 values to control the panel data format.
23224 + * @vidcon1: The base vidcon1 values to control the panel data output.
23225 + * @win: The setup data for each hardware window, or NULL for unused.
23226 + * @display_mode: The LCD output display mode.
23227 + *
23228 + * The platform data supplies the video driver with all the information
23229 + * it requires to work with the display(s) attached to the machine. It
23230 + * controls the initial mode, the number of display windows (0 is always
23231 + * the base framebuffer) that are initialised etc.
23232 + *
23233 + */
23234 +struct s3c_fb_platdata {
23235 +       void    (*setup_gpio)(void);
23236 +
23237 +       struct s3c_fb_pd_win    *win[S3C_FB_MAX_WIN];
23238 +
23239 +       u32                      vidcon0;
23240 +       u32                      vidcon1;
23241 +};
23242 +
23243 +/**
23244 + * s3c_fb_set_platdata() - Setup the FB device with platform data.
23245 + * @pd: The platform data to set. The data is copied from the passed structure
23246 + *      so the machine data can mark the data __initdata so that any unused
23247 + *      machines will end up dumping their data at runtime.
23248 + */
23249 +extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
23250 +
23251 +/**
23252 + * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
23253 + *
23254 + * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
23255 + */
23256 +extern void s3c64xx_fb_gpio_setup_24bpp(void);
23257 +
23258 +#endif /* __PLAT_S3C_FB_H */
23259 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg.h
23260 ===================================================================
23261 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23262 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg.h      2009-01-02 00:01:56.000000000 +0100
23263 @@ -0,0 +1,110 @@
23264 +/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
23265 + *
23266 + * Copyright 2008 Openmoko, Inc.
23267 + * Copyright 2008 Simtec Electronics
23268 + *     http://armlinux.simtec.co.uk/
23269 + *     Ben Dooks <ben@simtec.co.uk>
23270 + *
23271 + * S3C Platform - GPIO pin configuration
23272 + *
23273 + * This program is free software; you can redistribute it and/or modify
23274 + * it under the terms of the GNU General Public License version 2 as
23275 + * published by the Free Software Foundation.
23276 +*/
23277 +
23278 +/* This file contains the necessary definitions to get the basic gpio
23279 + * pin configuration done such as setting a pin to input or output or
23280 + * changing the pull-{up,down} configurations.
23281 + */
23282 +
23283 +/* Note, this interface is being added to the s3c64xx arch first and will
23284 + * be added to the s3c24xx systems later.
23285 + */
23286 +
23287 +#ifndef __PLAT_GPIO_CFG_H
23288 +#define __PLAT_GPIO_CFG_H __FILE__
23289 +
23290 +typedef unsigned int __bitwise__ s3c_gpio_pull_t;
23291 +
23292 +/* forward declaration if gpio-core.h hasn't been included */
23293 +struct s3c_gpio_chip;
23294 +
23295 +/**
23296 + * struct s3c_gpio_cfg GPIO configuration
23297 + * @cfg_eint: Configuration setting when used for external interrupt source
23298 + * @get_pull: Read the current pull configuration for the GPIO
23299 + * @set_pull: Set the current pull configuraiton for the GPIO
23300 + * @set_config: Set the current configuration for the GPIO
23301 + * @get_config: Read the current configuration for the GPIO
23302 + *
23303 + * Each chip can have more than one type of GPIO bank available and some
23304 + * have different capabilites even when they have the same control register
23305 + * layouts. Provide an point to vector control routine and provide any
23306 + * per-bank configuration information that other systems such as the
23307 + * external interrupt code will need.
23308 + */
23309 +struct s3c_gpio_cfg {
23310 +       unsigned int    cfg_eint;
23311 +
23312 +       s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
23313 +       int             (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
23314 +                                   s3c_gpio_pull_t pull);
23315 +
23316 +       unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
23317 +       int      (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
23318 +                              unsigned config);
23319 +};
23320 +
23321 +#define S3C_GPIO_SPECIAL_MARK  (0xfffffff0)
23322 +#define S3C_GPIO_SPECIAL(x)    (S3C_GPIO_SPECIAL_MARK | (x))
23323 +
23324 +/* Defines for generic pin configurations */
23325 +#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
23326 +#define S3C_GPIO_OUTPUT        (S3C_GPIO_SPECIAL(1))
23327 +#define S3C_GPIO_SFN(x)        (S3C_GPIO_SPECIAL(x))
23328 +
23329 +#define s3c_gpio_is_cfg_special(_cfg) \
23330 +       (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
23331 +
23332 +/**
23333 + * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
23334 + * @pin pin The pin number to configure.
23335 + * @pin to The configuration for the pin's function.
23336 + *
23337 + * Configure which function is actually connected to the external
23338 + * pin, such as an gpio input, output or some form of special function
23339 + * connected to an internal peripheral block.
23340 + */
23341 +extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
23342 +
23343 +/* Define values for the pull-{up,down} available for each gpio pin.
23344 + *
23345 + * These values control the state of the weak pull-{up,down} resistors
23346 + * available on most pins on the S3C series. Not all chips support both
23347 + * up or down settings, and it may be dependant on the chip that is being
23348 + * used to whether the particular mode is available.
23349 + */
23350 +#define S3C_GPIO_PULL_NONE     ((__force s3c_gpio_pull_t)0x00)
23351 +#define S3C_GPIO_PULL_DOWN     ((__force s3c_gpio_pull_t)0x01)
23352 +#define S3C_GPIO_PULL_UP       ((__force s3c_gpio_pull_t)0x02)
23353 +
23354 +/**
23355 + * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
23356 + * @pin: The pin number to configure the pull resistor.
23357 + * @pull: The configuration for the pull resistor.
23358 + *
23359 + * This function sets the state of the pull-{up,down} resistor for the
23360 + * specified pin. It will return 0 if successfull, or a negative error
23361 + * code if the pin cannot support the requested pull setting.
23362 +*/
23363 +extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
23364 +
23365 +/**
23366 + * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
23367 + * @pin: The pin number to get the settings for
23368 + *
23369 + * Read the pull resistor value for the specified pin.
23370 +*/
23371 +extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
23372 +
23373 +#endif /* __PLAT_GPIO_CFG_H */
23374 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h
23375 ===================================================================
23376 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23377 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h      2009-01-02 00:01:56.000000000 +0100
23378 @@ -0,0 +1,176 @@
23379 +/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
23380 + *
23381 + * Copyright 2008 Openmoko, Inc.
23382 + * Copyright 2008 Simtec Electronics
23383 + *     http://armlinux.simtec.co.uk/
23384 + *     Ben Dooks <ben@simtec.co.uk>
23385 + *
23386 + * S3C Platform - GPIO pin configuration helper definitions
23387 + *
23388 + * This program is free software; you can redistribute it and/or modify
23389 + * it under the terms of the GNU General Public License version 2 as
23390 + * published by the Free Software Foundation.
23391 +*/
23392 +
23393 +/* This is meant for core cpu support, machine or other driver files
23394 + * should not be including this header.
23395 + */
23396 +
23397 +#ifndef __PLAT_GPIO_CFG_HELPERS_H
23398 +#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
23399 +
23400 +/* As a note, all gpio configuration functions are entered exclusively, either
23401 + * with the relevant lock held or the system prevented from doing anything else
23402 + * by disabling interrupts.
23403 +*/
23404 +
23405 +static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
23406 +                                    unsigned int off, unsigned int config)
23407 +{
23408 +       return (chip->config->set_config)(chip, off, config);
23409 +}
23410 +
23411 +static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
23412 +                                     unsigned int off, s3c_gpio_pull_t pull)
23413 +{
23414 +       return (chip->config->set_pull)(chip, off, pull);
23415 +}
23416 +
23417 +/**
23418 + * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
23419 + * @chip: The gpio chip that is being configured.
23420 + * @off: The offset for the GPIO being configured.
23421 + * @cfg: The configuration value to set.
23422 + *
23423 + * This helper deal with the GPIO cases where the control register
23424 + * has two bits of configuration per gpio, which have the following
23425 + * functions:
23426 + *     00 = input
23427 + *     01 = output
23428 + *     1x = special function
23429 +*/
23430 +extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
23431 +                                  unsigned int off, unsigned int cfg);
23432 +
23433 +/**
23434 + * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
23435 + * @chip: The gpio chip that is being configured.
23436 + * @off: The offset for the GPIO being configured.
23437 + * @cfg: The configuration value to set.
23438 + *
23439 + * This helper deal with the GPIO cases where the control register
23440 + * has one bit of configuration for the gpio, where setting the bit
23441 + * means the pin is in special function mode and unset means output.
23442 +*/
23443 +extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
23444 +                                    unsigned int off, unsigned int cfg);
23445 +
23446 +/**
23447 + * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
23448 + * @chip: The gpio chip that is being configured.
23449 + * @off: The offset for the GPIO being configured.
23450 + * @cfg: The configuration value to set.
23451 + *
23452 + * This helper deal with the GPIO cases where the control register has 4 bits
23453 + * of control per GPIO, generally in the form of:
23454 + *     0000 = Input
23455 + *     0001 = Output
23456 + *     others = Special functions (dependant on bank)
23457 + *
23458 + * Note, since the code to deal with the case where there are two control
23459 + * registers instead of one, we do not have a seperate set of functions for
23460 + * each case.
23461 +*/
23462 +extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
23463 +                                       unsigned int off, unsigned int cfg);
23464 +
23465 +
23466 +/* Pull-{up,down} resistor controls.
23467 + *
23468 + * S3C2410,S3C2440,S3C24A0 = Pull-UP,
23469 + * S3C2412,S3C2413 = Pull-Down
23470 + * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
23471 + * S3C2443 = Pull-Both [not same as S3C6400]
23472 + */
23473 +
23474 +/**
23475 + * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
23476 + * @chip: The gpio chip that is being configured.
23477 + * @off: The offset for the GPIO being configured.
23478 + * @param: pull: The pull mode being requested.
23479 + *
23480 + * This is a helper function for the case where we have GPIOs with one
23481 + * bit configuring the presence of a pull-up resistor.
23482 + */
23483 +extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
23484 +                               unsigned int off, s3c_gpio_pull_t pull);
23485 +
23486 +/**
23487 + * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
23488 + * @chip: The gpio chip that is being configured
23489 + * @off: The offset for the GPIO being configured
23490 + * @param: pull: The pull mode being requested
23491 + *
23492 + * This is a helper function for the case where we have GPIOs with one
23493 + * bit configuring the presence of a pull-down resistor.
23494 + */
23495 +extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
23496 +                                 unsigned int off, s3c_gpio_pull_t pull);
23497 +
23498 +/**
23499 + * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
23500 + * @chip: The gpio chip that is being configured.
23501 + * @off: The offset for the GPIO being configured.
23502 + * @param: pull: The pull mode being requested.
23503 + *
23504 + * This is a helper function for the case where we have GPIOs with two
23505 + * bits configuring the presence of a pull resistor, in the following
23506 + * order:
23507 + *     00 = No pull resistor connected
23508 + *     01 = Pull-up resistor connected
23509 + *     10 = Pull-down resistor connected
23510 + */
23511 +extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
23512 +                                  unsigned int off, s3c_gpio_pull_t pull);
23513 +
23514 +
23515 +/**
23516 + * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
23517 + * @chip: The gpio chip that the GPIO pin belongs to
23518 + * @off: The offset to the pin to get the configuration of.
23519 + *
23520 + * This helper function reads the state of the pull-{up,down} resistor for the
23521 + * given GPIO in the same case as s3c_gpio_setpull_upown.
23522 +*/
23523 +extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
23524 +                                              unsigned int off);
23525 +
23526 +/**
23527 + * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
23528 + * @chip: The gpio chip that is being configured.
23529 + * @off: The offset for the GPIO being configured.
23530 + * @param: pull: The pull mode being requested.
23531 + *
23532 + * This is a helper function for the case where we have GPIOs with two
23533 + * bits configuring the presence of a pull resistor, in the following
23534 + * order:
23535 + *     00 = Pull-up resistor connected
23536 + *     10 = Pull-down resistor connected
23537 + *     x1 = No pull up resistor
23538 + */
23539 +extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
23540 +                                   unsigned int off, s3c_gpio_pull_t pull);
23541 +
23542 +/**
23543 + * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
23544 + * @chip: The gpio chip that the GPIO pin belongs to.
23545 + * @off: The offset to the pin to get the configuration of.
23546 + *
23547 + * This helper function reads the state of the pull-{up,down} resistor for the
23548 + * given GPIO in the same case as s3c_gpio_setpull_upown.
23549 +*/
23550 +extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
23551 +                                               unsigned int off);
23552 +
23553 +#endif /* __PLAT_GPIO_CFG_HELPERS_H */
23554 +
23555 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-core.h
23556 ===================================================================
23557 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23558 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-core.h     2009-01-02 00:01:56.000000000 +0100
23559 @@ -0,0 +1,107 @@
23560 +/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
23561 + *
23562 + * Copyright 2008 Simtec Electronics
23563 + *     http://armlinux.simtec.co.uk/
23564 + *     Ben Dooks <ben@simtec.co.uk>
23565 + *
23566 + * S3C Platform - GPIO core
23567 + *
23568 + * This program is free software; you can redistribute it and/or modify
23569 + * it under the terms of the GNU General Public License version 2 as
23570 + * published by the Free Software Foundation.
23571 +*/
23572 +
23573 +/* Define the core gpiolib support functions that the s3c platforms may
23574 + * need to extend or change depending on the hardware and the s3c chip
23575 + * selected at build or found at run time.
23576 + *
23577 + * These definitions are not intended for driver inclusion, there is
23578 + * nothing here that should not live outside the platform and core
23579 + * specific code.
23580 +*/
23581 +
23582 +struct s3c_gpio_chip;
23583 +
23584 +/**
23585 + * struct s3c_gpio_pm - power management (suspend/resume) information
23586 + * @save: Routine to save the state of the GPIO block
23587 + * @resume: Routine to resume the GPIO block.
23588 + */
23589 +struct s3c_gpio_pm {
23590 +       void (*save)(struct s3c_gpio_chip *chip);
23591 +       void (*resume)(struct s3c_gpio_chip *chip);
23592 +};
23593 +
23594 +struct s3c_gpio_cfg;
23595 +
23596 +/**
23597 + * struct s3c_gpio_chip - wrapper for specific implementation of gpio
23598 + * @chip: The chip structure to be exported via gpiolib.
23599 + * @base: The base pointer to the gpio configuration registers.
23600 + * @config: special function and pull-resistor control information.
23601 + * @pm_save: Save information for suspend/resume support.
23602 + *
23603 + * This wrapper provides the necessary information for the Samsung
23604 + * specific gpios being registered with gpiolib.
23605 + */
23606 +struct s3c_gpio_chip {
23607 +       struct gpio_chip        chip;
23608 +       struct s3c_gpio_cfg     *config;
23609 +       struct s3c_gpio_pm      *pm;
23610 +       void __iomem            *base;
23611 +#ifdef CONFIG_PM
23612 +       u32                     pm_save[4];
23613 +#endif
23614 +};
23615 +
23616 +static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
23617 +{
23618 +       return container_of(gpc, struct s3c_gpio_chip, chip);
23619 +}
23620 +
23621 +/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
23622 + * @chip: The chip to register
23623 + *
23624 + * This is a wrapper to gpiochip_add() that takes our specific gpio chip
23625 + * information and makes the necessary alterations for the platform and
23626 + * notes the information for use with the configuration systems and any
23627 + * other parts of the system.
23628 + */
23629 +extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
23630 +
23631 +/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
23632 + * for use with the configuration calls, and other parts of the s3c gpiolib
23633 + * support code.
23634 + *
23635 + * Not all s3c support code will need this, as some configurations of cpu
23636 + * may only support one or two different configuration options and have an
23637 + * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
23638 + * the machine support file should provide its own s3c_gpiolib_getchip()
23639 + * and any other necessary functions.
23640 + */
23641 +
23642 +#ifdef CONFIG_S3C_GPIO_TRACK
23643 +extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
23644 +
23645 +static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
23646 +{
23647 +       return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
23648 +}
23649 +#else
23650 +/* machine specific code should provide s3c_gpiolib_getchip */
23651 +
23652 +static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
23653 +#endif
23654 +
23655 +#ifdef CONFIG_PM
23656 +extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
23657 +extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
23658 +extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
23659 +#define __gpio_pm(x) x
23660 +#else
23661 +#define s3c_gpio_pm_1bit NULL
23662 +#define s3c_gpio_pm_2bit NULL
23663 +#define s3c_gpio_pm_4bit NULL
23664 +#define __gpio_pm(x) NULL
23665 +
23666 +#endif /* CONFIG_PM */
23667 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/iic-core.h
23668 ===================================================================
23669 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23670 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/iic-core.h      2009-01-02 00:01:56.000000000 +0100
23671 @@ -0,0 +1,35 @@
23672 +/* arch/arm/mach-s3c2410/include/mach/iic-core.h
23673 + *
23674 + * Copyright 2008 Openmoko, Inc.
23675 + * Copyright 2008 Simtec Electronics
23676 + *     Ben Dooks <ben@simtec.co.uk>
23677 + *
23678 + * S3C - I2C Controller core functions
23679 + *
23680 + * This program is free software; you can redistribute it and/or modify
23681 + * it under the terms of the GNU General Public License version 2 as
23682 + * published by the Free Software Foundation.
23683 +*/
23684 +
23685 +#ifndef __ASM_ARCH_IIC_CORE_H
23686 +#define __ASM_ARCH_IIC_CORE_H __FILE__
23687 +
23688 +/* These functions are only for use with the core support code, such as
23689 + * the cpu specific initialisation code
23690 + */
23691 +
23692 +/* re-define device name depending on support. */
23693 +static inline void s3c_i2c0_setname(char *name)
23694 +{
23695 +       /* currently this device is always compiled in */
23696 +       s3c_device_i2c0.name = name;
23697 +}
23698 +
23699 +static inline void s3c_i2c1_setname(char *name)
23700 +{
23701 +#ifdef CONFIG_S3C_DEV_I2C1
23702 +       s3c_device_i2c1.name = name;
23703 +#endif
23704 +}
23705 +
23706 +#endif /* __ASM_ARCH_IIC_H */
23707 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/iic.h
23708 ===================================================================
23709 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23710 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/iic.h   2009-01-02 00:01:56.000000000 +0100
23711 @@ -0,0 +1,57 @@
23712 +/* arch/arm/mach-s3c2410/include/mach/iic.h
23713 + *
23714 + * Copyright (c) 2004 Simtec Electronics
23715 + *     Ben Dooks <ben@simtec.co.uk>
23716 + *
23717 + * S3C2410 - I2C Controller platfrom_device info
23718 + *
23719 + * This program is free software; you can redistribute it and/or modify
23720 + * it under the terms of the GNU General Public License version 2 as
23721 + * published by the Free Software Foundation.
23722 +*/
23723 +
23724 +#ifndef __ASM_ARCH_IIC_H
23725 +#define __ASM_ARCH_IIC_H __FILE__
23726 +
23727 +#define S3C_IICFLG_FILTER      (1<<0)  /* enable s3c2440 filter */
23728 +
23729 +/* Notes:
23730 + *     1) All frequencies are expressed in Hz
23731 + *     2) A value of zero is `do not care`
23732 +*/
23733 +
23734 +struct s3c2410_platform_i2c {
23735 +       int             bus_num;        /* bus number to use */
23736 +       unsigned int    flags;
23737 +       unsigned int    slave_addr;     /* slave address for controller */
23738 +       unsigned long   bus_freq;       /* standard bus frequency */
23739 +       unsigned long   max_freq;       /* max frequency for the bus */
23740 +       unsigned long   min_freq;       /* min frequency for the bus */
23741 +       unsigned int    sda_delay;      /* pclks (s3c2440 only) */
23742 +
23743 +       void    (*cfg_gpio)(struct platform_device *dev);
23744 +};
23745 +
23746 +/**
23747 + * s3c_i2c0_set_platdata - set platform data for i2c0 device
23748 + * @i2c: The platform data to set, or NULL for default data.
23749 + *
23750 + * Register the given platform data for use with the i2c0 device. This
23751 + * call copies the platform data, so the caller can use __initdata for
23752 + * their copy.
23753 + *
23754 + * This call will set cfg_gpio if is null to the default platform
23755 + * implementation.
23756 + *
23757 + * Any user of s3c_device_i2c0 should call this, even if it is with
23758 + * NULL to ensure that the device is given the default platform data
23759 + * as the driver will no longer carry defaults.
23760 + */
23761 +extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
23762 +extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
23763 +
23764 +/* defined by architecture to configure gpio */
23765 +extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
23766 +extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
23767 +
23768 +#endif /* __ASM_ARCH_IIC_H */
23769 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/map-base.h
23770 ===================================================================
23771 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23772 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/map-base.h      2009-01-02 00:01:56.000000000 +0100
23773 @@ -0,0 +1,40 @@
23774 +/* linux/include/asm-arm/plat-s3c/map.h
23775 + *
23776 + * Copyright 2003, 2007 Simtec Electronics
23777 + *     http://armlinux.simtec.co.uk/
23778 + *     Ben Dooks <ben@simtec.co.uk>
23779 + *
23780 + * S3C - Memory map definitions (virtual addresses)
23781 + *
23782 + * This program is free software; you can redistribute it and/or modify
23783 + * it under the terms of the GNU General Public License version 2 as
23784 + * published by the Free Software Foundation.
23785 +*/
23786 +
23787 +#ifndef __ASM_PLAT_MAP_H
23788 +#define __ASM_PLAT_MAP_H __FILE__
23789 +
23790 +/* Fit all our registers in at 0xF4000000 upwards, trying to use as
23791 + * little of the VA space as possible so vmalloc and friends have a
23792 + * better chance of getting memory.
23793 + *
23794 + * we try to ensure stuff like the IRQ registers are available for
23795 + * an single MOVS instruction (ie, only 8 bits of set data)
23796 + */
23797 +
23798 +#define S3C_ADDR_BASE  (0xF4000000)
23799 +
23800 +#ifndef __ASSEMBLY__
23801 +#define S3C_ADDR(x)    ((void __iomem __force *)S3C_ADDR_BASE + (x))
23802 +#else
23803 +#define S3C_ADDR(x)    (S3C_ADDR_BASE + (x))
23804 +#endif
23805 +
23806 +#define S3C_VA_IRQ     S3C_ADDR(0x00000000)    /* irq controller(s) */
23807 +#define S3C_VA_SYS     S3C_ADDR(0x00100000)    /* system control */
23808 +#define S3C_VA_MEM     S3C_ADDR(0x00200000)    /* system control */
23809 +#define S3C_VA_TIMER   S3C_ADDR(0x00300000)    /* timer block */
23810 +#define S3C_VA_WATCHDOG        S3C_ADDR(0x00400000)    /* watchdog */
23811 +#define S3C_VA_UART    S3C_ADDR(0x01000000)    /* UART */
23812 +
23813 +#endif /* __ASM_PLAT_MAP_H */
23814 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/map.h
23815 ===================================================================
23816 --- linux-2.6.28.orig/arch/arm/plat-s3c/include/plat/map.h      2008-12-25 00:26:37.000000000 +0100
23817 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
23818 @@ -1,40 +0,0 @@
23819 -/* linux/include/asm-arm/plat-s3c/map.h
23820 - *
23821 - * Copyright 2003, 2007 Simtec Electronics
23822 - *     http://armlinux.simtec.co.uk/
23823 - *     Ben Dooks <ben@simtec.co.uk>
23824 - *
23825 - * S3C - Memory map definitions (virtual addresses)
23826 - *
23827 - * This program is free software; you can redistribute it and/or modify
23828 - * it under the terms of the GNU General Public License version 2 as
23829 - * published by the Free Software Foundation.
23830 -*/
23831 -
23832 -#ifndef __ASM_PLAT_MAP_H
23833 -#define __ASM_PLAT_MAP_H __FILE__
23834 -
23835 -/* Fit all our registers in at 0xF4000000 upwards, trying to use as
23836 - * little of the VA space as possible so vmalloc and friends have a
23837 - * better chance of getting memory.
23838 - *
23839 - * we try to ensure stuff like the IRQ registers are available for
23840 - * an single MOVS instruction (ie, only 8 bits of set data)
23841 - */
23842 -
23843 -#define S3C_ADDR_BASE  (0xF4000000)
23844 -
23845 -#ifndef __ASSEMBLY__
23846 -#define S3C_ADDR(x)    ((void __iomem __force *)S3C_ADDR_BASE + (x))
23847 -#else
23848 -#define S3C_ADDR(x)    (S3C_ADDR_BASE + (x))
23849 -#endif
23850 -
23851 -#define S3C_VA_IRQ     S3C_ADDR(0x00000000)    /* irq controller(s) */
23852 -#define S3C_VA_SYS     S3C_ADDR(0x00100000)    /* system control */
23853 -#define S3C_VA_MEM     S3C_ADDR(0x00200000)    /* system control */
23854 -#define S3C_VA_TIMER   S3C_ADDR(0x00300000)    /* timer block */
23855 -#define S3C_VA_WATCHDOG        S3C_ADDR(0x00400000)    /* watchdog */
23856 -#define S3C_VA_UART    S3C_ADDR(0x01000000)    /* UART */
23857 -
23858 -#endif /* __ASM_PLAT_MAP_H */
23859 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/nand.h
23860 ===================================================================
23861 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23862 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/nand.h  2009-01-02 00:01:56.000000000 +0100
23863 @@ -0,0 +1,56 @@
23864 +/* arch/arm/mach-s3c2410/include/mach/nand.h
23865 + *
23866 + * Copyright (c) 2004 Simtec Electronics
23867 + *     Ben Dooks <ben@simtec.co.uk>
23868 + *
23869 + * S3C2410 - NAND device controller platfrom_device info
23870 + *
23871 + * This program is free software; you can redistribute it and/or modify
23872 + * it under the terms of the GNU General Public License version 2 as
23873 + * published by the Free Software Foundation.
23874 +*/
23875 +
23876 +/* struct s3c2410_nand_set
23877 + *
23878 + * define an set of one or more nand chips registered with an unique mtd
23879 + *
23880 + * nr_chips     = number of chips in this set
23881 + * nr_partitions = number of partitions pointed to be partitoons (or zero)
23882 + * name                 = name of set (optional)
23883 + * nr_map       = map for low-layer logical to physical chip numbers (option)
23884 + * partitions   = mtd partition list
23885 +*/
23886 +
23887 +#define S3C2410_NAND_BBT       0x0001
23888 +
23889 +struct s3c2410_nand_set {
23890 +       unsigned int            disable_ecc : 1;
23891 +
23892 +       int                     nr_chips;
23893 +       int                     nr_partitions;
23894 +       unsigned int            flags;
23895 +       char                    *name;
23896 +       int                     *nr_map;
23897 +       struct mtd_partition    *partitions;
23898 +       struct nand_ecclayout   *ecc_layout;
23899 +};
23900 +
23901 +struct s3c2410_platform_nand {
23902 +       /* timing information for controller, all times in nanoseconds */
23903 +
23904 +       int     tacls;  /* time for active CLE/ALE to nWE/nOE */
23905 +       int     twrph0; /* active time for nWE/nOE */
23906 +       int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
23907 +
23908 +       unsigned int    ignore_unset_ecc : 1;
23909 +
23910 +       int                     nr_sets;
23911 +       struct s3c2410_nand_set *sets;
23912 +
23913 +       /* force software_ecc at runtime */
23914 +       int     software_ecc;
23915 +
23916 +       void                    (*select_chip)(struct s3c2410_nand_set *,
23917 +                                              int chip);
23918 +};
23919 +
23920 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/pm.h
23921 ===================================================================
23922 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
23923 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/pm.h    2009-01-02 00:01:56.000000000 +0100
23924 @@ -0,0 +1,184 @@
23925 +/* linux/include/asm-arm/plat-s3c24xx/pm.h
23926 + *
23927 + * Copyright (c) 2004 Simtec Electronics
23928 + *     http://armlinux.simtec.co.uk/
23929 + *     Written by Ben Dooks, <ben@simtec.co.uk>
23930 + *
23931 + * This program is free software; you can redistribute it and/or modify
23932 + * it under the terms of the GNU General Public License version 2 as
23933 + * published by the Free Software Foundation.
23934 +*/
23935 +
23936 +#include <linux/sysdev.h>
23937 +
23938 +/* s3c_pm_init
23939 + *
23940 + * called from board at initialisation time to setup the power
23941 + * management
23942 +*/
23943 +
23944 +#ifdef CONFIG_PM
23945 +
23946 +extern __init int s3c_pm_init(void);
23947 +
23948 +#else
23949 +
23950 +static inline int s3c_pm_init(void)
23951 +{
23952 +       return 0;
23953 +}
23954 +#endif
23955 +
23956 +/* configuration for the IRQ mask over sleep */
23957 +extern unsigned long s3c_irqwake_intmask;
23958 +extern unsigned long s3c_irqwake_eintmask;
23959 +
23960 +/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
23961 +extern unsigned long s3c_irqwake_intallow;
23962 +extern unsigned long s3c_irqwake_eintallow;
23963 +
23964 +/* per-cpu sleep functions */
23965 +
23966 +extern void (*pm_cpu_prep)(void);
23967 +extern void (*pm_cpu_sleep)(void);
23968 +
23969 +/* Flags for PM Control */
23970 +
23971 +extern unsigned long s3c_pm_flags;
23972 +
23973 +extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
23974 +
23975 +/* from sleep.S */
23976 +
23977 +extern int  s3c_cpu_save(unsigned long *saveblk);
23978 +extern void s3c_cpu_resume(void);
23979 +
23980 +extern void s3c2410_cpu_suspend(void);
23981 +
23982 +extern unsigned long s3c_sleep_save_phys;
23983 +
23984 +/* sleep save info */
23985 +
23986 +/**
23987 + * struct sleep_save - save information for shared peripherals.
23988 + * @reg: Pointer to the register to save.
23989 + * @val: Holder for the value saved from reg.
23990 + *
23991 + * This describes a list of registers which is used by the pm core and
23992 + * other subsystem to save and restore register values over suspend.
23993 + */
23994 +struct sleep_save {
23995 +       void __iomem    *reg;
23996 +       unsigned long   val;
23997 +};
23998 +
23999 +#define SAVE_ITEM(x) \
24000 +       { .reg = (x) }
24001 +
24002 +/**
24003 + * struct pm_uart_save - save block for core UART
24004 + * @ulcon: Save value for S3C2410_ULCON
24005 + * @ucon: Save value for S3C2410_UCON
24006 + * @ufcon: Save value for S3C2410_UFCON
24007 + * @umcon: Save value for S3C2410_UMCON
24008 + * @ubrdiv: Save value for S3C2410_UBRDIV
24009 + *
24010 + * Save block for UART registers to be held over sleep and restored if they
24011 + * are needed (say by debug).
24012 +*/
24013 +struct pm_uart_save {
24014 +       u32     ulcon;
24015 +       u32     ucon;
24016 +       u32     ufcon;
24017 +       u32     umcon;
24018 +       u32     ubrdiv;
24019 +       u32     udivslot;
24020 +};
24021 +
24022 +/* helper functions to save/restore lists of registers. */
24023 +
24024 +extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
24025 +extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
24026 +extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
24027 +
24028 +#ifdef CONFIG_PM
24029 +extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
24030 +extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
24031 +extern int s3c24xx_irq_resume(struct sys_device *dev);
24032 +#else
24033 +#define s3c_irqext_wake NULL
24034 +#define s3c24xx_irq_suspend NULL
24035 +#define s3c24xx_irq_resume  NULL
24036 +#endif
24037 +
24038 +/* PM debug functions */
24039 +
24040 +#ifdef CONFIG_S3C2410_PM_DEBUG
24041 +/**
24042 + * s3c_pm_dbg() - low level debug function for use in suspend/resume.
24043 + * @msg: The message to print.
24044 + *
24045 + * This function is used mainly to debug the resume process before the system
24046 + * can rely on printk/console output. It uses the low-level debugging output
24047 + * routine printascii() to do its work.
24048 + */
24049 +extern void s3c_pm_dbg(const char *msg, ...);
24050 +
24051 +#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
24052 +#else
24053 +#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
24054 +#endif
24055 +
24056 +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
24057 +/**
24058 + * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
24059 + * @set: set bits for the state of the LEDs
24060 + * @clear: clear bits for the state of the LEDs.
24061 + */
24062 +extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
24063 +
24064 +#else
24065 +static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
24066 +#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
24067 +
24068 +/* suspend memory checking */
24069 +
24070 +#ifdef CONFIG_S3C2410_PM_CHECK
24071 +extern void s3c_pm_check_prepare(void);
24072 +extern void s3c_pm_check_restore(void);
24073 +extern void s3c_pm_check_cleanup(void);
24074 +extern void s3c_pm_check_store(void);
24075 +#else
24076 +#define s3c_pm_check_prepare() do { } while(0)
24077 +#define s3c_pm_check_restore() do { } while(0)
24078 +#define s3c_pm_check_cleanup() do { } while(0)
24079 +#define s3c_pm_check_store()   do { } while(0)
24080 +#endif
24081 +
24082 +/**
24083 + * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
24084 + *
24085 + * Setup all the necessary GPIO pins for waking the system on external
24086 + * interrupt.
24087 + */
24088 +extern void s3c_pm_configure_extint(void);
24089 +
24090 +/**
24091 + * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
24092 + *
24093 + * Restore the state of the GPIO pins after sleep, which may involve ensuring
24094 + * that we do not glitch the state of the pins from that the bootloader's
24095 + * resume code has done.
24096 +*/
24097 +extern void s3c_pm_restore_gpios(void);
24098 +
24099 +/**
24100 + * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
24101 + *
24102 + * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
24103 + */
24104 +extern void s3c_pm_save_gpios(void);
24105 +
24106 +extern void s3c_pm_save_core(void);
24107 +extern void s3c_pm_restore_core(void);
24108 +
24109 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-ac97.h
24110 ===================================================================
24111 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
24112 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-ac97.h     2009-01-02 00:01:56.000000000 +0100
24113 @@ -0,0 +1,67 @@
24114 +/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
24115 + *
24116 + * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
24117 + *             http://www.simtec.co.uk/products/SWLINUX/
24118 + *
24119 + * This program is free software; you can redistribute it and/or modify
24120 + * it under the terms of the GNU General Public License version 2 as
24121 + * published by the Free Software Foundation.
24122 + *
24123 + * S3C2440 AC97 Controller
24124 +*/
24125 +
24126 +#ifndef __ASM_ARCH_REGS_AC97_H
24127 +#define __ASM_ARCH_REGS_AC97_H __FILE__
24128 +
24129 +#define S3C_AC97_GLBCTRL                               (0x00)
24130 +
24131 +#define S3C_AC97_GLBCTRL_CODECREADYIE                  (1<<22)
24132 +#define S3C_AC97_GLBCTRL_PCMOUTURIE                    (1<<21)
24133 +#define S3C_AC97_GLBCTRL_PCMINORIE                     (1<<20)
24134 +#define S3C_AC97_GLBCTRL_MICINORIE                     (1<<19)
24135 +#define S3C_AC97_GLBCTRL_PCMOUTTIE                     (1<<18)
24136 +#define S3C_AC97_GLBCTRL_PCMINTIE                      (1<<17)
24137 +#define S3C_AC97_GLBCTRL_MICINTIE                      (1<<16)
24138 +#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                  (0<<12)
24139 +#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                  (1<<12)
24140 +#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                  (2<<12)
24141 +#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                 (3<<12)
24142 +#define S3C_AC97_GLBCTRL_PCMINTM_OFF                   (0<<10)
24143 +#define S3C_AC97_GLBCTRL_PCMINTM_PIO                   (1<<10)
24144 +#define S3C_AC97_GLBCTRL_PCMINTM_DMA                   (2<<10)
24145 +#define S3C_AC97_GLBCTRL_PCMINTM_MASK                  (3<<10)
24146 +#define S3C_AC97_GLBCTRL_MICINTM_OFF                   (0<<8)
24147 +#define S3C_AC97_GLBCTRL_MICINTM_PIO                   (1<<8)
24148 +#define S3C_AC97_GLBCTRL_MICINTM_DMA                   (2<<8)
24149 +#define S3C_AC97_GLBCTRL_MICINTM_MASK                  (3<<8)
24150 +#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE            (1<<3)
24151 +#define S3C_AC97_GLBCTRL_ACLINKON                      (1<<2)
24152 +#define S3C_AC97_GLBCTRL_WARMRESET                     (1<<1)
24153 +#define S3C_AC97_GLBCTRL_COLDRESET                     (1<<0)
24154 +
24155 +#define S3C_AC97_GLBSTAT                               (0x04)
24156 +
24157 +#define S3C_AC97_GLBSTAT_CODECREADY                    (1<<22)
24158 +#define S3C_AC97_GLBSTAT_PCMOUTUR                      (1<<21)
24159 +#define S3C_AC97_GLBSTAT_PCMINORI                      (1<<20)
24160 +#define S3C_AC97_GLBSTAT_MICINORI                      (1<<19)
24161 +#define S3C_AC97_GLBSTAT_PCMOUTTI                      (1<<18)
24162 +#define S3C_AC97_GLBSTAT_PCMINTI                       (1<<17)
24163 +#define S3C_AC97_GLBSTAT_MICINTI                       (1<<16)
24164 +#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                        (0<<0)
24165 +#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                        (1<<0)
24166 +#define S3C_AC97_GLBSTAT_MAINSTATE_READY               (2<<0)
24167 +#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE              (3<<0)
24168 +#define S3C_AC97_GLBSTAT_MAINSTATE_LP                  (4<<0)
24169 +#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                        (5<<0)
24170 +
24171 +#define S3C_AC97_CODEC_CMD                             (0x08)
24172 +
24173 +#define S3C_AC97_CODEC_CMD_READ                                (1<<23)
24174 +
24175 +#define S3C_AC97_STAT                                  (0x0c)
24176 +#define S3C_AC97_PCM_ADDR                              (0x10)
24177 +#define S3C_AC97_PCM_DATA                              (0x18)
24178 +#define S3C_AC97_MIC_DATA                              (0x1C)
24179 +
24180 +#endif /* __ASM_ARCH_REGS_AC97_H */
24181 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-fb.h
24182 ===================================================================
24183 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
24184 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-fb.h       2009-01-02 00:01:56.000000000 +0100
24185 @@ -0,0 +1,366 @@
24186 +/* arch/arm/plat-s3c/include/plat/regs-fb.h
24187 + *
24188 + * Copyright 2008 Openmoko, Inc.
24189 + * Copyright 2008 Simtec Electronics
24190 + *      http://armlinux.simtec.co.uk/
24191 + *      Ben Dooks <ben@simtec.co.uk>
24192 + *
24193 + * S3C Platform - new-style framebuffer register definitions
24194 + *
24195 + * This is the register set for the new style framebuffer interface
24196 + * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
24197 + * S3C64XX series such as the S3C6400 and S3C6410.
24198 + *
24199 + * The file does not contain the cpu specific items which are based on
24200 + * whichever architecture is selected, it only contains the core of the
24201 + * register set. See <mach/regs-fb.h> to get the specifics.
24202 + *
24203 + * Note, we changed to using regs-fb.h as it avoids any clashes with
24204 + * the original regs-lcd.h so out of the way of regs-lcd.h as well as
24205 + * indicating the newer block is much more than just an LCD interface.
24206 + *
24207 + * This program is free software; you can redistribute it and/or modify
24208 + * it under the terms of the GNU General Public License version 2 as
24209 + * published by the Free Software Foundation.
24210 +*/
24211 +
24212 +/* Please do not include this file directly, use <mach/regs-fb.h> to
24213 + * ensure all the localised SoC support is included as necessary.
24214 +*/
24215 +
24216 +/* VIDCON0 */
24217 +
24218 +#define VIDCON0                                        (0x00)
24219 +#define VIDCON0_INTERLACE                      (1 << 29)
24220 +#define VIDCON0_VIDOUT_MASK                    (0x3 << 26)
24221 +#define VIDCON0_VIDOUT_SHIFT                   (26)
24222 +#define VIDCON0_VIDOUT_RGB                     (0x0 << 26)
24223 +#define VIDCON0_VIDOUT_TV                      (0x1 << 26)
24224 +#define VIDCON0_VIDOUT_I80_LDI0                        (0x2 << 26)
24225 +#define VIDCON0_VIDOUT_I80_LDI1                        (0x3 << 26)
24226 +
24227 +#define VIDCON0_L1_DATA_MASK                   (0x7 << 23)
24228 +#define VIDCON0_L1_DATA_SHIFT                  (23)
24229 +#define VIDCON0_L1_DATA_16BPP                  (0x0 << 23)
24230 +#define VIDCON0_L1_DATA_18BPP16                        (0x1 << 23)
24231 +#define VIDCON0_L1_DATA_18BPP9                 (0x2 << 23)
24232 +#define VIDCON0_L1_DATA_24BPP                  (0x3 << 23)
24233 +#define VIDCON0_L1_DATA_18BPP                  (0x4 << 23)
24234 +#define VIDCON0_L1_DATA_16BPP8                 (0x5 << 23)
24235 +
24236 +#define VIDCON0_L0_DATA_MASK                   (0x7 << 20)
24237 +#define VIDCON0_L0_DATA_SHIFT                  (20)
24238 +#define VIDCON0_L0_DATA_16BPP                  (0x0 << 20)
24239 +#define VIDCON0_L0_DATA_18BPP16                        (0x1 << 20)
24240 +#define VIDCON0_L0_DATA_18BPP9                 (0x2 << 20)
24241 +#define VIDCON0_L0_DATA_24BPP                  (0x3 << 20)
24242 +#define VIDCON0_L0_DATA_18BPP                  (0x4 << 20)
24243 +#define VIDCON0_L0_DATA_16BPP8                 (0x5 << 20)
24244 +
24245 +#define VIDCON0_PNRMODE_MASK                   (0x3 << 17)
24246 +#define VIDCON0_PNRMODE_SHIFT                  (17)
24247 +#define VIDCON0_PNRMODE_RGB                    (0x0 << 17)
24248 +#define VIDCON0_PNRMODE_BGR                    (0x1 << 17)
24249 +#define VIDCON0_PNRMODE_SERIAL_RGB             (0x2 << 17)
24250 +#define VIDCON0_PNRMODE_SERIAL_BGR             (0x3 << 17)
24251 +
24252 +#define VIDCON0_CLKVALUP                       (1 << 16)
24253 +#define VIDCON0_CLKVAL_F_MASK                  (0xff << 6)
24254 +#define VIDCON0_CLKVAL_F_SHIFT                 (6)
24255 +#define VIDCON0_CLKVAL_F_LIMIT                 (0xff)
24256 +#define VIDCON0_CLKVAL_F(_x)                   ((_x) << 6)
24257 +#define VIDCON0_VLCKFREE                       (1 << 5)
24258 +#define VIDCON0_CLKDIR                         (1 << 4)
24259 +
24260 +#define VIDCON0_CLKSEL_MASK                    (0x3 << 2)
24261 +#define VIDCON0_CLKSEL_SHIFT                   (2)
24262 +#define VIDCON0_CLKSEL_HCLK                    (0x0 << 2)
24263 +#define VIDCON0_CLKSEL_LCD                     (0x1 << 2)
24264 +#define VIDCON0_CLKSEL_27M                     (0x3 << 2)
24265 +
24266 +#define VIDCON0_ENVID                          (1 << 1)
24267 +#define VIDCON0_ENVID_F                                (1 << 0)
24268 +
24269 +#define VIDCON1                                        (0x04)
24270 +#define VIDCON1_LINECNT_MASK                   (0x7ff << 16)
24271 +#define VIDCON1_LINECNT_SHIFT                  (16)
24272 +#define VIDCON1_LINECNT_GET(_v)                        (((_v) >> 16) & 0x7ff)
24273 +#define VIDCON1_VSTATUS_MASK                   (0x3 << 13)
24274 +#define VIDCON1_VSTATUS_SHIFT                  (13)
24275 +#define VIDCON1_VSTATUS_VSYNC                  (0x0 << 13)
24276 +#define VIDCON1_VSTATUS_BACKPORCH              (0x1 << 13)
24277 +#define VIDCON1_VSTATUS_ACTIVE                 (0x2 << 13)
24278 +#define VIDCON1_VSTATUS_FRONTPORCH             (0x0 << 13)
24279 +
24280 +#define VIDCON1_INV_VCLK                       (1 << 7)
24281 +#define VIDCON1_INV_HSYNC                      (1 << 6)
24282 +#define VIDCON1_INV_VSYNC                      (1 << 5)
24283 +#define VIDCON1_INV_VDEN                       (1 << 4)
24284 +
24285 +/* VIDCON2 */
24286 +
24287 +#define VIDCON2                                        (0x08)
24288 +#define VIDCON2_EN601                          (1 << 23)
24289 +#define VIDCON2_TVFMTSEL_SW                    (1 << 14)
24290 +
24291 +#define VIDCON2_TVFMTSEL1_MASK                 (0x3 << 12)
24292 +#define VIDCON2_TVFMTSEL1_SHIFT                        (12)
24293 +#define VIDCON2_TVFMTSEL1_RGB                  (0x0 << 12)
24294 +#define VIDCON2_TVFMTSEL1_YUV422               (0x1 << 12)
24295 +#define VIDCON2_TVFMTSEL1_YUV444               (0x2 << 12)
24296 +
24297 +#define VIDCON2_ORGYCbCr                       (1 << 8)
24298 +#define VIDCON2_YUVORDCrCb                     (1 << 7)
24299 +
24300 +/* VIDTCON0 */
24301 +
24302 +#define VIDTCON0_VBPDE_MASK                    (0xff << 24)
24303 +#define VIDTCON0_VBPDE_SHIFT                   (24)
24304 +#define VIDTCON0_VBPDE_LIMIT                   (0xff)
24305 +#define VIDTCON0_VBPDE(_x)                     ((_x) << 24)
24306 +
24307 +#define VIDTCON0_VBPD_MASK                     (0xff << 16)
24308 +#define VIDTCON0_VBPD_SHIFT                    (16)
24309 +#define VIDTCON0_VBPD_LIMIT                    (0xff)
24310 +#define VIDTCON0_VBPD(_x)                      ((_x) << 16)
24311 +
24312 +#define VIDTCON0_VFPD_MASK                     (0xff << 8)
24313 +#define VIDTCON0_VFPD_SHIFT                    (8)
24314 +#define VIDTCON0_VFPD_LIMIT                    (0xff)
24315 +#define VIDTCON0_VFPD(_x)                      ((_x) << 8)
24316 +
24317 +#define VIDTCON0_VSPW_MASK                     (0xff << 0)
24318 +#define VIDTCON0_VSPW_SHIFT                    (0)
24319 +#define VIDTCON0_VSPW_LIMIT                    (0xff)
24320 +#define VIDTCON0_VSPW(_x)                      ((_x) << 0)
24321 +
24322 +/* VIDTCON1 */
24323 +
24324 +#define VIDTCON1_VFPDE_MASK                    (0xff << 24)
24325 +#define VIDTCON1_VFPDE_SHIFT                   (24)
24326 +#define VIDTCON1_VFPDE_LIMIT                   (0xff)
24327 +#define VIDTCON1_VFPDE(_x)                     ((_x) << 24)
24328 +
24329 +#define VIDTCON1_HBPD_MASK                     (0xff << 16)
24330 +#define VIDTCON1_HBPD_SHIFT                    (16)
24331 +#define VIDTCON1_HBPD_LIMIT                    (0xff)
24332 +#define VIDTCON1_HBPD(_x)                      ((_x) << 16)
24333 +
24334 +#define VIDTCON1_HFPD_MASK                     (0xff << 8)
24335 +#define VIDTCON1_HFPD_SHIFT                    (8)
24336 +#define VIDTCON1_HFPD_LIMIT                    (0xff)
24337 +#define VIDTCON1_HFPD(_x)                      ((_x) << 8)
24338 +
24339 +#define VIDTCON1_HSPW_MASK                     (0xff << 0)
24340 +#define VIDTCON1_HSPW_SHIFT                    (0)
24341 +#define VIDTCON1_HSPW_LIMIT                    (0xff)
24342 +#define VIDTCON1_HSPW(_x)                      ((_x) << 0)
24343 +
24344 +#define VIDTCON2                               (0x18)
24345 +#define VIDTCON2_LINEVAL_MASK                  (0x7ff << 11)
24346 +#define VIDTCON2_LINEVAL_SHIFT                 (11)
24347 +#define VIDTCON2_LINEVAL_LIMIT                 (0x7ff)
24348 +#define VIDTCON2_LINEVAL(_x)                   ((_x) << 11)
24349 +
24350 +#define VIDTCON2_HOZVAL_MASK                   (0x7ff << 0)
24351 +#define VIDTCON2_HOZVAL_SHIFT                  (0)
24352 +#define VIDTCON2_HOZVAL_LIMIT                  (0x7ff)
24353 +#define VIDTCON2_HOZVAL(_x)                    ((_x) << 0)
24354 +
24355 +/* WINCONx */
24356 +
24357 +
24358 +#define WINCONx_BITSWP                         (1 << 18)
24359 +#define WINCONx_BYTSWP                         (1 << 17)
24360 +#define WINCONx_HAWSWP                         (1 << 16)
24361 +#define WINCONx_BURSTLEN_MASK                  (0x3 << 9)
24362 +#define WINCONx_BURSTLEN_SHIFT                 (9)
24363 +#define WINCONx_BURSTLEN_16WORD                        (0x0 << 9)
24364 +#define WINCONx_BURSTLEN_8WORD                 (0x1 << 9)
24365 +#define WINCONx_BURSTLEN_4WORD                 (0x2 << 9)
24366 +
24367 +#define WINCONx_ENWIN                          (1 << 0)
24368 +#define WINCON0_BPPMODE_MASK                   (0xf << 2)
24369 +#define WINCON0_BPPMODE_SHIFT                  (2)
24370 +#define WINCON0_BPPMODE_1BPP                   (0x0 << 2)
24371 +#define WINCON0_BPPMODE_2BPP                   (0x1 << 2)
24372 +#define WINCON0_BPPMODE_4BPP                   (0x2 << 2)
24373 +#define WINCON0_BPPMODE_8BPP_PALETTE           (0x3 << 2)
24374 +#define WINCON0_BPPMODE_16BPP_565              (0x5 << 2)
24375 +#define WINCON0_BPPMODE_16BPP_1555             (0x7 << 2)
24376 +#define WINCON0_BPPMODE_18BPP_666              (0x8 << 2)
24377 +#define WINCON0_BPPMODE_24BPP_888              (0xb << 2)
24378 +
24379 +#define WINCON1_BLD_PIX                                (1 << 6)
24380 +
24381 +#define WINCON1_ALPHA_SEL                      (1 << 1)
24382 +#define WINCON1_BPPMODE_MASK                   (0xf << 2)
24383 +#define WINCON1_BPPMODE_SHIFT                  (2)
24384 +#define WINCON1_BPPMODE_1BPP                   (0x0 << 2)
24385 +#define WINCON1_BPPMODE_2BPP                   (0x1 << 2)
24386 +#define WINCON1_BPPMODE_4BPP                   (0x2 << 2)
24387 +#define WINCON1_BPPMODE_8BPP_PALETTE           (0x3 << 2)
24388 +#define WINCON1_BPPMODE_8BPP_1232              (0x4 << 2)
24389 +#define WINCON1_BPPMODE_16BPP_565              (0x5 << 2)
24390 +#define WINCON1_BPPMODE_16BPP_A1555            (0x6 << 2)
24391 +#define WINCON1_BPPMODE_16BPP_I1555            (0x7 << 2)
24392 +#define WINCON1_BPPMODE_18BPP_666              (0x8 << 2)
24393 +#define WINCON1_BPPMODE_18BPP_A1665            (0x9 << 2)
24394 +#define WINCON1_BPPMODE_19BPP_A1666            (0xa << 2)
24395 +#define WINCON1_BPPMODE_24BPP_888              (0xb << 2)
24396 +#define WINCON1_BPPMODE_24BPP_A1887            (0xc << 2)
24397 +#define WINCON1_BPPMODE_25BPP_A1888            (0xd << 2)
24398 +#define WINCON1_BPPMODE_28BPP_A4888            (0xd << 2)
24399 +
24400 +
24401 +#define VIDOSDxA_TOPLEFT_X_MASK                        (0x7ff << 11)
24402 +#define VIDOSDxA_TOPLEFT_X_SHIFT               (11)
24403 +#define VIDOSDxA_TOPLEFT_X_LIMIT               (0x7ff)
24404 +#define VIDOSDxA_TOPLEFT_X(_x)                 ((_x) << 11)
24405 +
24406 +#define VIDOSDxA_TOPLEFT_Y_MASK                        (0x7ff << 0)
24407 +#define VIDOSDxA_TOPLEFT_Y_SHIFT               (0)
24408 +#define VIDOSDxA_TOPLEFT_Y_LIMIT               (0x7ff)
24409 +#define VIDOSDxA_TOPLEFT_Y(_x)                 ((_x) << 0)
24410 +
24411 +#define VIDOSDxB_BOTRIGHT_X_MASK               (0x7ff << 11)
24412 +#define VIDOSDxB_BOTRIGHT_X_SHIFT              (11)
24413 +#define VIDOSDxB_BOTRIGHT_X_LIMIT              (0x7ff)
24414 +#define VIDOSDxB_BOTRIGHT_X(_x)                        ((_x) << 11)
24415 +
24416 +#define VIDOSDxB_BOTRIGHT_Y_MASK               (0x7ff << 0)
24417 +#define VIDOSDxB_BOTRIGHT_Y_SHIFT              (0)
24418 +#define VIDOSDxB_BOTRIGHT_Y_LIMIT              (0x7ff)
24419 +#define VIDOSDxB_BOTRIGHT_Y(_x)                        ((_x) << 0)
24420 +
24421 +/* For VIDOSD[1..4]C */
24422 +#define VIDISD14C_ALPHA0_R(_x)                 ((_x) << 20)
24423 +#define VIDISD14C_ALPHA0_G_MASK                        (0xf << 16)
24424 +#define VIDISD14C_ALPHA0_G_SHIFT               (16)
24425 +#define VIDISD14C_ALPHA0_G_LIMIT               (0xf)
24426 +#define VIDISD14C_ALPHA0_G(_x)                 ((_x) << 16)
24427 +#define VIDISD14C_ALPHA0_B_MASK                        (0xf << 12)
24428 +#define VIDISD14C_ALPHA0_B_SHIFT               (12)
24429 +#define VIDISD14C_ALPHA0_B_LIMIT               (0xf)
24430 +#define VIDISD14C_ALPHA0_B(_x)                 ((_x) << 12)
24431 +#define VIDISD14C_ALPHA1_R_MASK                        (0xf << 8)
24432 +#define VIDISD14C_ALPHA1_R_SHIFT               (8)
24433 +#define VIDISD14C_ALPHA1_R_LIMIT               (0xf)
24434 +#define VIDISD14C_ALPHA1_R(_x)                 ((_x) << 8)
24435 +#define VIDISD14C_ALPHA1_G_MASK                        (0xf << 4)
24436 +#define VIDISD14C_ALPHA1_G_SHIFT               (4)
24437 +#define VIDISD14C_ALPHA1_G_LIMIT               (0xf)
24438 +#define VIDISD14C_ALPHA1_G(_x)                 ((_x) << 4)
24439 +#define VIDISD14C_ALPHA1_B_MASK                        (0xf << 0)
24440 +#define VIDISD14C_ALPHA1_B_SHIFT               (0)
24441 +#define VIDISD14C_ALPHA1_B_LIMIT               (0xf)
24442 +#define VIDISD14C_ALPHA1_B(_x)                 ((_x) << 0)
24443 +
24444 +/* Video buffer addresses */
24445 +#define VIDW_BUF_START(_buff)                  (0xA0 + ((_buff) * 8))
24446 +#define VIDW_BUF_START1(_buff)                 (0xA4 + ((_buff) * 8))
24447 +#define VIDW_BUF_END(_buff)                    (0xD0 + ((_buff) * 8))
24448 +#define VIDW_BUF_END1(_buff)                   (0xD4 + ((_buff) * 8))
24449 +#define VIDW_BUF_SIZE(_buff)                   (0x100 + ((_buff) * 4))
24450 +
24451 +#define VIDW_BUF_SIZE_OFFSET_MASK              (0x1fff << 13)
24452 +#define VIDW_BUF_SIZE_OFFSET_SHIFT             (13)
24453 +#define VIDW_BUF_SIZE_OFFSET_LIMIT             (0x1fff)
24454 +#define VIDW_BUF_SIZE_OFFSET(_x)               ((_x) << 13)
24455 +
24456 +#define VIDW_BUF_SIZE_PAGEWIDTH_MASK           (0x1fff << 0)
24457 +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT          (0)
24458 +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT          (0x1fff)
24459 +#define VIDW_BUF_SIZE_PAGEWIDTH(_x)            ((_x) << 0)
24460 +
24461 +/* Interrupt controls and status */
24462 +
24463 +#define VIDINTCON0_FIFOINTERVAL_MASK           (0x3f << 20)
24464 +#define VIDINTCON0_FIFOINTERVAL_SHIFT          (20)
24465 +#define VIDINTCON0_FIFOINTERVAL_LIMIT          (0x3f)
24466 +#define VIDINTCON0_FIFOINTERVAL(_x)            ((_x) << 20)
24467 +
24468 +#define VIDINTCON0_INT_SYSMAINCON              (1 << 19)
24469 +#define VIDINTCON0_INT_SYSSUBCON               (1 << 18)
24470 +#define VIDINTCON0_INT_I80IFDONE               (1 << 17)
24471 +
24472 +#define VIDINTCON0_FRAMESEL0_MASK              (0x3 << 15)
24473 +#define VIDINTCON0_FRAMESEL0_SHIFT             (15)
24474 +#define VIDINTCON0_FRAMESEL0_BACKPORCH         (0x0 << 15)
24475 +#define VIDINTCON0_FRAMESEL0_VSYNC             (0x1 << 15)
24476 +#define VIDINTCON0_FRAMESEL0_ACTIVE            (0x2 << 15)
24477 +#define VIDINTCON0_FRAMESEL0_FRONTPORCH                (0x3 << 15)
24478 +
24479 +#define VIDINTCON0_FRAMESEL1                   (1 << 14)
24480 +#define VIDINTCON0_FRAMESEL1_NONE              (0x0 << 14)
24481 +#define VIDINTCON0_FRAMESEL1_BACKPORCH         (0x1 << 14)
24482 +#define VIDINTCON0_FRAMESEL1_VSYNC             (0x2 << 14)
24483 +#define VIDINTCON0_FRAMESEL1_FRONTPORCH                (0x3 << 14)
24484 +
24485 +#define VIDINTCON0_INT_FRAME                   (1 << 12)
24486 +#define VIDINTCON0_FIFIOSEL_MASK               (0x7f << 5)
24487 +#define VIDINTCON0_FIFIOSEL_SHIFT              (5)
24488 +#define VIDINTCON0_FIFIOSEL_WINDOW0            (0x1 << 5)
24489 +#define VIDINTCON0_FIFIOSEL_WINDOW1            (0x2 << 5)
24490 +
24491 +#define VIDINTCON0_FIFOLEVEL_MASK              (0x7 << 2)
24492 +#define VIDINTCON0_FIFOLEVEL_SHIFT             (2)
24493 +#define VIDINTCON0_FIFOLEVEL_TO25PC            (0x0 << 2)
24494 +#define VIDINTCON0_FIFOLEVEL_TO50PC            (0x1 << 2)
24495 +#define VIDINTCON0_FIFOLEVEL_TO75PC            (0x2 << 2)
24496 +#define VIDINTCON0_FIFOLEVEL_EMPTY             (0x3 << 2)
24497 +#define VIDINTCON0_FIFOLEVEL_FULL              (0x4 << 2)
24498 +
24499 +#define VIDINTCON0_INT_FIFO_MASK               (0x3 << 0)
24500 +#define VIDINTCON0_INT_FIFO_SHIFT              (0)
24501 +#define VIDINTCON0_INT_ENABLE                  (1 << 0)
24502 +
24503 +#define VIDINTCON1                             (0x134)
24504 +#define VIDINTCON1_INT_I180                    (1 << 2)
24505 +#define VIDINTCON1_INT_FRAME                   (1 << 1)
24506 +#define VIDINTCON1_INT_FIFO                    (1 << 0)
24507 +
24508 +/* Window colour-key control registers */
24509 +
24510 +#define WxKEYCON0_KEYBL_EN                     (1 << 26)
24511 +#define WxKEYCON0_KEYEN_F                      (1 << 25)
24512 +#define WxKEYCON0_DIRCON                       (1 << 24)
24513 +#define WxKEYCON0_COMPKEY_MASK                 (0xffffff << 0)
24514 +#define WxKEYCON0_COMPKEY_SHIFT                        (0)
24515 +#define WxKEYCON0_COMPKEY_LIMIT                        (0xffffff)
24516 +#define WxKEYCON0_COMPKEY(_x)                  ((_x) << 0)
24517 +#define WxKEYCON1_COLVAL_MASK                  (0xffffff << 0)
24518 +#define WxKEYCON1_COLVAL_SHIFT                 (0)
24519 +#define WxKEYCON1_COLVAL_LIMIT                 (0xffffff)
24520 +#define WxKEYCON1_COLVAL(_x)                   ((_x) << 0)
24521 +
24522 +
24523 +/* Window blanking (MAP) */
24524 +
24525 +#define WINxMAP_MAP                            (1 << 24)
24526 +#define WINxMAP_MAP_COLOUR_MASK                        (0xffffff << 0)
24527 +#define WINxMAP_MAP_COLOUR_SHIFT               (0)
24528 +#define WINxMAP_MAP_COLOUR_LIMIT               (0xffffff)
24529 +#define WINxMAP_MAP_COLOUR(_x)                 ((_x) << 0)
24530 +
24531 +#define WPALCON_PAL_UPDATE                     (1 << 9)
24532 +#define WPALCON_W1PAL_MASK                     (0x7 << 3)
24533 +#define WPALCON_W1PAL_SHIFT                    (3)
24534 +#define WPALCON_W1PAL_25BPP_A888               (0x0 << 3)
24535 +#define WPALCON_W1PAL_24BPP                    (0x1 << 3)
24536 +#define WPALCON_W1PAL_19BPP_A666               (0x2 << 3)
24537 +#define WPALCON_W1PAL_18BPP_A665               (0x3 << 3)
24538 +#define WPALCON_W1PAL_18BPP                    (0x4 << 3)
24539 +#define WPALCON_W1PAL_16BPP_A555               (0x5 << 3)
24540 +#define WPALCON_W1PAL_16BPP_565                        (0x6 << 3)
24541 +
24542 +#define WPALCON_W0PAL_MASK                     (0x7 << 0)
24543 +#define WPALCON_W0PAL_SHIFT                    (0)
24544 +#define WPALCON_W0PAL_25BPP_A888               (0x0 << 0)
24545 +#define WPALCON_W0PAL_24BPP                    (0x1 << 0)
24546 +#define WPALCON_W0PAL_19BPP_A666               (0x2 << 0)
24547 +#define WPALCON_W0PAL_18BPP_A665               (0x3 << 0)
24548 +#define WPALCON_W0PAL_18BPP                    (0x4 << 0)
24549 +#define WPALCON_W0PAL_16BPP_A555               (0x5 << 0)
24550 +#define WPALCON_W0PAL_16BPP_565                        (0x6 << 0)
24551 +
24552 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-iic.h
24553 ===================================================================
24554 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
24555 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-iic.h      2009-01-02 00:01:56.000000000 +0100
24556 @@ -0,0 +1,56 @@
24557 +/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
24558 + *
24559 + * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
24560 + *             http://www.simtec.co.uk/products/SWLINUX/
24561 + *
24562 + * This program is free software; you can redistribute it and/or modify
24563 + * it under the terms of the GNU General Public License version 2 as
24564 + * published by the Free Software Foundation.
24565 + *
24566 + * S3C2410 I2C Controller
24567 +*/
24568 +
24569 +#ifndef __ASM_ARCH_REGS_IIC_H
24570 +#define __ASM_ARCH_REGS_IIC_H __FILE__
24571 +
24572 +/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
24573 +
24574 +#define S3C2410_IICREG(x) (x)
24575 +
24576 +#define S3C2410_IICCON    S3C2410_IICREG(0x00)
24577 +#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
24578 +#define S3C2410_IICADD    S3C2410_IICREG(0x08)
24579 +#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
24580 +#define S3C2440_IICLC    S3C2410_IICREG(0x10)
24581 +
24582 +#define S3C2410_IICCON_ACKEN           (1<<7)
24583 +#define S3C2410_IICCON_TXDIV_16                (0<<6)
24584 +#define S3C2410_IICCON_TXDIV_512       (1<<6)
24585 +#define S3C2410_IICCON_IRQEN           (1<<5)
24586 +#define S3C2410_IICCON_IRQPEND         (1<<4)
24587 +#define S3C2410_IICCON_SCALE(x)                ((x)&15)
24588 +#define S3C2410_IICCON_SCALEMASK       (0xf)
24589 +
24590 +#define S3C2410_IICSTAT_MASTER_RX      (2<<6)
24591 +#define S3C2410_IICSTAT_MASTER_TX      (3<<6)
24592 +#define S3C2410_IICSTAT_SLAVE_RX       (0<<6)
24593 +#define S3C2410_IICSTAT_SLAVE_TX       (1<<6)
24594 +#define S3C2410_IICSTAT_MODEMASK       (3<<6)
24595 +
24596 +#define S3C2410_IICSTAT_START          (1<<5)
24597 +#define S3C2410_IICSTAT_BUSBUSY                (1<<5)
24598 +#define S3C2410_IICSTAT_TXRXEN         (1<<4)
24599 +#define S3C2410_IICSTAT_ARBITR         (1<<3)
24600 +#define S3C2410_IICSTAT_ASSLAVE                (1<<2)
24601 +#define S3C2410_IICSTAT_ADDR0          (1<<1)
24602 +#define S3C2410_IICSTAT_LASTBIT                (1<<0)
24603 +
24604 +#define S3C2410_IICLC_SDA_DELAY0       (0 << 0)
24605 +#define S3C2410_IICLC_SDA_DELAY5       (1 << 0)
24606 +#define S3C2410_IICLC_SDA_DELAY10      (2 << 0)
24607 +#define S3C2410_IICLC_SDA_DELAY15      (3 << 0)
24608 +#define S3C2410_IICLC_SDA_DELAY_MASK   (3 << 0)
24609 +
24610 +#define S3C2410_IICLC_FILTER_ON                (1<<2)
24611 +
24612 +#endif /* __ASM_ARCH_REGS_IIC_H */
24613 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-irqtype.h
24614 ===================================================================
24615 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
24616 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-irqtype.h  2009-01-02 00:01:56.000000000 +0100
24617 @@ -0,0 +1,21 @@
24618 +/* arch/arm/plat-s3c/include/plat/regs-irqtype.h
24619 + *
24620 + * Copyright 2008 Simtec Electronics
24621 + *      Ben Dooks <ben@simtec.co.uk>
24622 + *      http://armlinux.simtec.co.uk/
24623 + *
24624 + * S3C - IRQ detection types.
24625 + *
24626 + * This program is free software; you can redistribute it and/or modify
24627 + * it under the terms of the GNU General Public License version 2 as
24628 + * published by the Free Software Foundation.
24629 + */
24630 +
24631 +/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
24632 + * the S3C64XX
24633 +*/
24634 +#define S3C2410_EXTINT_LOWLEV   (0x00)
24635 +#define S3C2410_EXTINT_HILEV    (0x01)
24636 +#define S3C2410_EXTINT_FALLEDGE         (0x02)
24637 +#define S3C2410_EXTINT_RISEEDGE         (0x04)
24638 +#define S3C2410_EXTINT_BOTHEDGE         (0x06)
24639 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-nand.h
24640 ===================================================================
24641 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
24642 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-nand.h     2009-01-02 00:01:56.000000000 +0100
24643 @@ -0,0 +1,123 @@
24644 +/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
24645 + *
24646 + * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
24647 + *                   http://www.simtec.co.uk/products/SWLINUX/
24648 + *
24649 + * This program is free software; you can redistribute it and/or modify
24650 + * it under the terms of the GNU General Public License version 2 as
24651 + * published by the Free Software Foundation.
24652 + *
24653 + * S3C2410 NAND register definitions
24654 +*/
24655 +
24656 +#ifndef __ASM_ARM_REGS_NAND
24657 +#define __ASM_ARM_REGS_NAND
24658 +
24659 +
24660 +#define S3C2410_NFREG(x) (x)
24661 +
24662 +#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
24663 +#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
24664 +#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
24665 +#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
24666 +#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
24667 +#define S3C2410_NFECC   S3C2410_NFREG(0x14)
24668 +
24669 +#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
24670 +#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
24671 +#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
24672 +#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
24673 +#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
24674 +#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
24675 +#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
24676 +#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
24677 +#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
24678 +#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
24679 +#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
24680 +#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
24681 +#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
24682 +#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
24683 +#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
24684 +
24685 +#define S3C2412_NFSBLK         S3C2410_NFREG(0x20)
24686 +#define S3C2412_NFEBLK         S3C2410_NFREG(0x24)
24687 +#define S3C2412_NFSTAT         S3C2410_NFREG(0x28)
24688 +#define S3C2412_NFMECC_ERR0    S3C2410_NFREG(0x2C)
24689 +#define S3C2412_NFMECC_ERR1    S3C2410_NFREG(0x30)
24690 +#define S3C2412_NFMECC0                S3C2410_NFREG(0x34)
24691 +#define S3C2412_NFMECC1                S3C2410_NFREG(0x38)
24692 +#define S3C2412_NFSECC         S3C2410_NFREG(0x3C)
24693 +
24694 +#define S3C2410_NFCONF_EN          (1<<15)
24695 +#define S3C2410_NFCONF_512BYTE     (1<<14)
24696 +#define S3C2410_NFCONF_4STEP       (1<<13)
24697 +#define S3C2410_NFCONF_INITECC     (1<<12)
24698 +#define S3C2410_NFCONF_nFCE        (1<<11)
24699 +#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
24700 +#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
24701 +#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
24702 +
24703 +#define S3C2410_NFSTAT_BUSY        (1<<0)
24704 +
24705 +#define S3C2440_NFCONF_BUSWIDTH_8      (0<<0)
24706 +#define S3C2440_NFCONF_BUSWIDTH_16     (1<<0)
24707 +#define S3C2440_NFCONF_ADVFLASH                (1<<3)
24708 +#define S3C2440_NFCONF_TACLS(x)                ((x)<<12)
24709 +#define S3C2440_NFCONF_TWRPH0(x)       ((x)<<8)
24710 +#define S3C2440_NFCONF_TWRPH1(x)       ((x)<<4)
24711 +
24712 +#define S3C2440_NFCONT_LOCKTIGHT       (1<<13)
24713 +#define S3C2440_NFCONT_SOFTLOCK                (1<<12)
24714 +#define S3C2440_NFCONT_ILLEGALACC_EN   (1<<10)
24715 +#define S3C2440_NFCONT_RNBINT_EN       (1<<9)
24716 +#define S3C2440_NFCONT_RN_FALLING      (1<<8)
24717 +#define S3C2440_NFCONT_SPARE_ECCLOCK   (1<<6)
24718 +#define S3C2440_NFCONT_MAIN_ECCLOCK    (1<<5)
24719 +#define S3C2440_NFCONT_INITECC         (1<<4)
24720 +#define S3C2440_NFCONT_nFCE            (1<<1)
24721 +#define S3C2440_NFCONT_ENABLE          (1<<0)
24722 +
24723 +#define S3C2440_NFSTAT_READY           (1<<0)
24724 +#define S3C2440_NFSTAT_nCE             (1<<1)
24725 +#define S3C2440_NFSTAT_RnB_CHANGE      (1<<2)
24726 +#define S3C2440_NFSTAT_ILLEGAL_ACCESS  (1<<3)
24727 +
24728 +#define S3C2412_NFCONF_NANDBOOT                (1<<31)
24729 +#define S3C2412_NFCONF_ECCCLKCON       (1<<30)
24730 +#define S3C2412_NFCONF_ECC_MLC         (1<<24)
24731 +#define S3C2412_NFCONF_TACLS_MASK      (7<<12) /* 1 extra bit of Tacls */
24732 +
24733 +#define S3C2412_NFCONT_ECC4_DIRWR      (1<<18)
24734 +#define S3C2412_NFCONT_LOCKTIGHT       (1<<17)
24735 +#define S3C2412_NFCONT_SOFTLOCK                (1<<16)
24736 +#define S3C2412_NFCONT_ECC4_ENCINT     (1<<13)
24737 +#define S3C2412_NFCONT_ECC4_DECINT     (1<<12)
24738 +#define S3C2412_NFCONT_MAIN_ECC_LOCK   (1<<7)
24739 +#define S3C2412_NFCONT_INIT_MAIN_ECC   (1<<5)
24740 +#define S3C2412_NFCONT_nFCE1           (1<<2)
24741 +#define S3C2412_NFCONT_nFCE0           (1<<1)
24742 +
24743 +#define S3C2412_NFSTAT_ECC_ENCDONE     (1<<7)
24744 +#define S3C2412_NFSTAT_ECC_DECDONE     (1<<6)
24745 +#define S3C2412_NFSTAT_ILLEGAL_ACCESS  (1<<5)
24746 +#define S3C2412_NFSTAT_RnB_CHANGE      (1<<4)
24747 +#define S3C2412_NFSTAT_nFCE1           (1<<3)
24748 +#define S3C2412_NFSTAT_nFCE0           (1<<2)
24749 +#define S3C2412_NFSTAT_Res1            (1<<1)
24750 +#define S3C2412_NFSTAT_READY           (1<<0)
24751 +
24752 +#define S3C2412_NFECCERR_SERRDATA(x)   (((x) >> 21) & 0xf)
24753 +#define S3C2412_NFECCERR_SERRBIT(x)    (((x) >> 18) & 0x7)
24754 +#define S3C2412_NFECCERR_MERRDATA(x)   (((x) >> 7) & 0x3ff)
24755 +#define S3C2412_NFECCERR_MERRBIT(x)    (((x) >> 4) & 0x7)
24756 +#define S3C2412_NFECCERR_SPARE_ERR(x)  (((x) >> 2) & 0x3)
24757 +#define S3C2412_NFECCERR_MAIN_ERR(x)   (((x) >> 2) & 0x3)
24758 +#define S3C2412_NFECCERR_NONE          (0)
24759 +#define S3C2412_NFECCERR_1BIT          (1)
24760 +#define S3C2412_NFECCERR_MULTIBIT      (2)
24761 +#define S3C2412_NFECCERR_ECCAREA       (3)
24762 +
24763 +
24764 +
24765 +#endif /* __ASM_ARM_REGS_NAND */
24766 +
24767 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-rtc.h
24768 ===================================================================
24769 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
24770 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-rtc.h      2009-01-02 00:01:56.000000000 +0100
24771 @@ -0,0 +1,61 @@
24772 +/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
24773 + *
24774 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
24775 + *                   http://www.simtec.co.uk/products/SWLINUX/
24776 + *
24777 + * This program is free software; you can redistribute it and/or modify
24778 + * it under the terms of the GNU General Public License version 2 as
24779 + * published by the Free Software Foundation.
24780 + *
24781 + * S3C2410 Internal RTC register definition
24782 +*/
24783 +
24784 +#ifndef __ASM_ARCH_REGS_RTC_H
24785 +#define __ASM_ARCH_REGS_RTC_H __FILE__
24786 +
24787 +#define S3C2410_RTCREG(x) (x)
24788 +
24789 +#define S3C2410_RTCCON       S3C2410_RTCREG(0x40)
24790 +#define S3C2410_RTCCON_RTCEN  (1<<0)
24791 +#define S3C2410_RTCCON_CLKSEL (1<<1)
24792 +#define S3C2410_RTCCON_CNTSEL (1<<2)
24793 +#define S3C2410_RTCCON_CLKRST (1<<3)
24794 +
24795 +#define S3C2410_TICNT        S3C2410_RTCREG(0x44)
24796 +#define S3C2410_TICNT_ENABLE  (1<<7)
24797 +
24798 +#define S3C2410_RTCALM       S3C2410_RTCREG(0x50)
24799 +#define S3C2410_RTCALM_ALMEN  (1<<6)
24800 +#define S3C2410_RTCALM_YEAREN (1<<5)
24801 +#define S3C2410_RTCALM_MONEN  (1<<4)
24802 +#define S3C2410_RTCALM_DAYEN  (1<<3)
24803 +#define S3C2410_RTCALM_HOUREN (1<<2)
24804 +#define S3C2410_RTCALM_MINEN  (1<<1)
24805 +#define S3C2410_RTCALM_SECEN  (1<<0)
24806 +
24807 +#define S3C2410_RTCALM_ALL \
24808 +  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
24809 +  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
24810 +  S3C2410_RTCALM_SECEN
24811 +
24812 +
24813 +#define S3C2410_ALMSEC       S3C2410_RTCREG(0x54)
24814 +#define S3C2410_ALMMIN       S3C2410_RTCREG(0x58)
24815 +#define S3C2410_ALMHOUR              S3C2410_RTCREG(0x5c)
24816 +
24817 +#define S3C2410_ALMDATE              S3C2410_RTCREG(0x60)
24818 +#define S3C2410_ALMMON       S3C2410_RTCREG(0x64)
24819 +#define S3C2410_ALMYEAR              S3C2410_RTCREG(0x68)
24820 +
24821 +#define S3C2410_RTCRST       S3C2410_RTCREG(0x6c)
24822 +
24823 +#define S3C2410_RTCSEC       S3C2410_RTCREG(0x70)
24824 +#define S3C2410_RTCMIN       S3C2410_RTCREG(0x74)
24825 +#define S3C2410_RTCHOUR              S3C2410_RTCREG(0x78)
24826 +#define S3C2410_RTCDATE              S3C2410_RTCREG(0x7c)
24827 +#define S3C2410_RTCDAY       S3C2410_RTCREG(0x80)
24828 +#define S3C2410_RTCMON       S3C2410_RTCREG(0x84)
24829 +#define S3C2410_RTCYEAR              S3C2410_RTCREG(0x88)
24830 +
24831 +
24832 +#endif /* __ASM_ARCH_REGS_RTC_H */
24833 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-sdhci.h
24834 ===================================================================
24835 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
24836 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-sdhci.h    2009-01-02 00:01:56.000000000 +0100
24837 @@ -0,0 +1,87 @@
24838 +/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
24839 + *
24840 + * Copyright 2008 Openmoko, Inc.
24841 + * Copyright 2008 Simtec Electronics
24842 + *     http://armlinux.simtec.co.uk/
24843 + *     Ben Dooks <ben@simtec.co.uk>
24844 + *
24845 + * S3C Platform - SDHCI (HSMMC) register definitions
24846 + *
24847 + * This program is free software; you can redistribute it and/or modify
24848 + * it under the terms of the GNU General Public License version 2 as
24849 + * published by the Free Software Foundation.
24850 +*/
24851 +
24852 +#ifndef __PLAT_S3C_SDHCI_REGS_H
24853 +#define __PLAT_S3C_SDHCI_REGS_H __FILE__
24854 +
24855 +#define S3C_SDHCI_CONTROL2                     (0x80)
24856 +#define S3C_SDHCI_CONTROL3                     (0x84)
24857 +#define S3C64XX_SDHCI_CONTROL4                 (0x8C)
24858 +
24859 +#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR      (1 << 31)
24860 +#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK                (1 << 30)
24861 +#define S3C_SDHCI_CTRL2_CDINVRXD3              (1 << 29)
24862 +#define S3C_SDHCI_CTRL2_SLCARDOUT              (1 << 28)
24863 +
24864 +#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK         (0xf << 24)
24865 +#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT                (24)
24866 +#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)          ((_x) << 24)
24867 +
24868 +#define S3C_SDHCI_CTRL2_LVLDAT_MASK            (0xff << 16)
24869 +#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT           (16)
24870 +#define S3C_SDHCI_CTRL2_LVLDAT(_x)             ((_x) << 16)
24871 +
24872 +#define S3C_SDHCI_CTRL2_ENFBCLKTX              (1 << 15)
24873 +#define S3C_SDHCI_CTRL2_ENFBCLKRX              (1 << 14)
24874 +#define S3C_SDHCI_CTRL2_SDCDSEL                        (1 << 13)
24875 +#define S3C_SDHCI_CTRL2_SDSIGPC                        (1 << 12)
24876 +#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART       (1 << 11)
24877 +
24878 +#define S3C_SDHCI_CTRL2_DFCNT_MASK             (0x3 << 9)
24879 +#define S3C_SDHCI_CTRL2_DFCNT_SHIFT            (9)
24880 +#define S3C_SDHCI_CTRL2_DFCNT_NONE             (0x0 << 9)
24881 +#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK           (0x1 << 9)
24882 +#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK          (0x2 << 9)
24883 +#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK          (0x3 << 9)
24884 +
24885 +#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD           (1 << 8)
24886 +#define S3C_SDHCI_CTRL2_RWAITMODE              (1 << 7)
24887 +#define S3C_SDHCI_CTRL2_DISBUFRD               (1 << 6)
24888 +#define S3C_SDHCI_CTRL2_SELBASECLK_MASK                (0x3 << 4)
24889 +#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT       (4)
24890 +#define S3C_SDHCI_CTRL2_PWRSYNC                        (1 << 3)
24891 +#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON         (1 << 1)
24892 +#define S3C_SDHCI_CTRL2_HWINITFIN              (1 << 0)
24893 +
24894 +#define S3C_SDHCI_CTRL3_FCSEL3                 (1 << 31)
24895 +#define S3C_SDHCI_CTRL3_FCSEL2                 (1 << 23)
24896 +#define S3C_SDHCI_CTRL3_FCSEL1                 (1 << 15)
24897 +#define S3C_SDHCI_CTRL3_FCSEL0                 (1 << 7)
24898 +
24899 +#define S3C_SDHCI_CTRL3_FIA3_MASK              (0x7f << 24)
24900 +#define S3C_SDHCI_CTRL3_FIA3_SHIFT             (24)
24901 +#define S3C_SDHCI_CTRL3_FIA3(_x)               ((_x) << 24)
24902 +
24903 +#define S3C_SDHCI_CTRL3_FIA2_MASK              (0x7f << 16)
24904 +#define S3C_SDHCI_CTRL3_FIA2_SHIFT             (16)
24905 +#define S3C_SDHCI_CTRL3_FIA2(_x)               ((_x) << 16)
24906 +
24907 +#define S3C_SDHCI_CTRL3_FIA1_MASK              (0x7f << 8)
24908 +#define S3C_SDHCI_CTRL3_FIA1_SHIFT             (8)
24909 +#define S3C_SDHCI_CTRL3_FIA1(_x)               ((_x) << 8)
24910 +
24911 +#define S3C_SDHCI_CTRL3_FIA0_MASK              (0x7f << 0)
24912 +#define S3C_SDHCI_CTRL3_FIA0_SHIFT             (0)
24913 +#define S3C_SDHCI_CTRL3_FIA0(_x)               ((_x) << 0)
24914 +
24915 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK      (0x3 << 16)
24916 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT     (16)
24917 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA       (0x0 << 16)
24918 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA       (0x1 << 16)
24919 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA       (0x2 << 16)
24920 +#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA       (0x3 << 16)
24921 +
24922 +#define S3C64XX_SDHCI_CONTROL4_BUSY            (1)
24923 +
24924 +#endif /* __PLAT_S3C_SDHCI_REGS_H */
24925 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-serial.h
24926 ===================================================================
24927 --- linux-2.6.28.orig/arch/arm/plat-s3c/include/plat/regs-serial.h      2008-12-25 00:26:37.000000000 +0100
24928 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-serial.h   2009-01-02 00:01:56.000000000 +0100
24929 @@ -77,6 +77,12 @@
24930  #define S3C2440_UCON_FCLK        (3<<10)
24931  #define S3C2443_UCON_EPLL        (3<<10)
24932
24933 +#define S3C6400_UCON_CLKMASK   (3<<10)
24934 +#define S3C6400_UCON_PCLK      (0<<10)
24935 +#define S3C6400_UCON_PCLK2     (2<<10)
24936 +#define S3C6400_UCON_UCLK0     (1<<10)
24937 +#define S3C6400_UCON_UCLK1     (3<<10)
24938 +
24939  #define S3C2440_UCON2_FCLK_EN    (1<<15)
24940  #define S3C2440_UCON0_DIVMASK    (15 << 12)
24941  #define S3C2440_UCON1_DIVMASK    (15 << 12)
24942 @@ -149,6 +155,14 @@
24943  #define S3C2410_UFSTAT_RXMASK    (15<<0)
24944  #define S3C2410_UFSTAT_RXSHIFT   (0)
24945
24946 +/* UFSTAT S3C24A0 */
24947 +#define S3C24A0_UFSTAT_TXFULL    (1 << 14)
24948 +#define S3C24A0_UFSTAT_RXFULL    (1 << 6)
24949 +#define S3C24A0_UFSTAT_TXMASK    (63 << 8)
24950 +#define S3C24A0_UFSTAT_TXSHIFT   (8)
24951 +#define S3C24A0_UFSTAT_RXMASK    (63)
24952 +#define S3C24A0_UFSTAT_RXSHIFT   (0)
24953 +
24954  /* UFSTAT S3C2443 same as S3C2440 */
24955  #define S3C2440_UFSTAT_TXFULL    (1<<14)
24956  #define S3C2440_UFSTAT_RXFULL    (1<<6)
24957 @@ -175,6 +189,11 @@
24958
24959  #define S3C2443_DIVSLOT                  (0x2C)
24960
24961 +/* S3C64XX interrupt registers. */
24962 +#define S3C64XX_UINTP          0x30
24963 +#define S3C64XX_UINTSP         0x34
24964 +#define S3C64XX_UINTM          0x38
24965 +
24966  #ifndef __ASSEMBLY__
24967
24968  /* struct s3c24xx_uart_clksrc
24969 @@ -224,7 +243,7 @@ struct s3c2410_uartcfg {
24970   * or platform_add_device() before the console_initcall()
24971  */
24972
24973 -extern struct platform_device *s3c24xx_uart_devs[3];
24974 +extern struct platform_device *s3c24xx_uart_devs[4];
24975
24976  #endif /* __ASSEMBLY__ */
24977
24978 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-timer.h
24979 ===================================================================
24980 --- linux-2.6.28.orig/arch/arm/plat-s3c/include/plat/regs-timer.h       2008-12-25 00:26:37.000000000 +0100
24981 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-timer.h    2009-01-02 00:01:56.000000000 +0100
24982 @@ -10,7 +10,6 @@
24983   * S3C2410 Timer configuration
24984  */
24985
24986 -
24987  #ifndef __ASM_ARCH_REGS_TIMER_H
24988  #define __ASM_ARCH_REGS_TIMER_H
24989
24990 @@ -21,6 +20,8 @@
24991  #define S3C2410_TCFG1        S3C_TIMERREG(0x04)
24992  #define S3C2410_TCON         S3C_TIMERREG(0x08)
24993
24994 +#define S3C64XX_TINT_CSTAT    S3C_TIMERREG(0x44)
24995 +
24996  #define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
24997  #define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
24998  #define S3C2410_TCFG_PRESCALER1_SHIFT (8)
24999 @@ -72,6 +73,14 @@
25000  #define S3C2410_TCFG1_MUX_TCLK    (4<<0)
25001  #define S3C2410_TCFG1_MUX_MASK   (15<<0)
25002
25003 +#define S3C64XX_TCFG1_MUX_DIV1   (0<<0)
25004 +#define S3C64XX_TCFG1_MUX_DIV2   (1<<0)
25005 +#define S3C64XX_TCFG1_MUX_DIV4   (2<<0)
25006 +#define S3C64XX_TCFG1_MUX_DIV8    (3<<0)
25007 +#define S3C64XX_TCFG1_MUX_DIV16   (4<<0)
25008 +#define S3C64XX_TCFG1_MUX_TCLK    (5<<0)  /* 3 sets of TCLK */
25009 +#define S3C64XX_TCFG1_MUX_MASK   (15<<0)
25010 +
25011  #define S3C2410_TCFG1_SHIFT(x)   ((x) * 4)
25012
25013  /* for each timer, we have an count buffer, an compare buffer and
25014 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-watchdog.h
25015 ===================================================================
25016 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
25017 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-watchdog.h 2009-01-02 00:01:56.000000000 +0100
25018 @@ -0,0 +1,41 @@
25019 +/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
25020 + *
25021 + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
25022 + *                   http://www.simtec.co.uk/products/SWLINUX/
25023 + *
25024 + * This program is free software; you can redistribute it and/or modify
25025 + * it under the terms of the GNU General Public License version 2 as
25026 + * published by the Free Software Foundation.
25027 + *
25028 + * S3C2410 Watchdog timer control
25029 +*/
25030 +
25031 +
25032 +#ifndef __ASM_ARCH_REGS_WATCHDOG_H
25033 +#define __ASM_ARCH_REGS_WATCHDOG_H
25034 +
25035 +#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
25036 +
25037 +#define S3C2410_WTCON     S3C_WDOGREG(0x00)
25038 +#define S3C2410_WTDAT     S3C_WDOGREG(0x04)
25039 +#define S3C2410_WTCNT     S3C_WDOGREG(0x08)
25040 +
25041 +/* the watchdog can either generate a reset pulse, or an
25042 + * interrupt.
25043 + */
25044 +
25045 +#define S3C2410_WTCON_RSTEN   (0x01)
25046 +#define S3C2410_WTCON_INTEN   (1<<2)
25047 +#define S3C2410_WTCON_ENABLE  (1<<5)
25048 +
25049 +#define S3C2410_WTCON_DIV16   (0<<3)
25050 +#define S3C2410_WTCON_DIV32   (1<<3)
25051 +#define S3C2410_WTCON_DIV64   (2<<3)
25052 +#define S3C2410_WTCON_DIV128  (3<<3)
25053 +
25054 +#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
25055 +#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
25056 +
25057 +#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
25058 +
25059 +
25060 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/sdhci.h
25061 ===================================================================
25062 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
25063 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/sdhci.h 2009-01-02 00:01:56.000000000 +0100
25064 @@ -0,0 +1,112 @@
25065 +/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
25066 + *
25067 + * Copyright 2008 Openmoko, Inc.
25068 + * Copyright 2008 Simtec Electronics
25069 + *     http://armlinux.simtec.co.uk/
25070 + *     Ben Dooks <ben@simtec.co.uk>
25071 + *
25072 + * S3C Platform - SDHCI (HSMMC) platform data definitions
25073 + *
25074 + * This program is free software; you can redistribute it and/or modify
25075 + * it under the terms of the GNU General Public License version 2 as
25076 + * published by the Free Software Foundation.
25077 +*/
25078 +
25079 +#ifndef __PLAT_S3C_SDHCI_H
25080 +#define __PLAT_S3C_SDHCI_H __FILE__
25081 +
25082 +struct platform_device;
25083 +struct mmc_host;
25084 +struct mmc_card;
25085 +struct mmc_ios;
25086 +
25087 +/**
25088 + * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
25089 + * @max_width: The maximum number of data bits supported.
25090 + * @host_caps: Standard MMC host capabilities bit field.
25091 + * @cfg_gpio: Configure the GPIO for a specific card bit-width
25092 + * @cfg_card: Configure the interface for a specific card and speed. This
25093 + *            is necessary the controllers and/or GPIO blocks require the
25094 + *           changing of driver-strength and other controls dependant on
25095 + *           the card and speed of operation.
25096 + * sdhci_host: Pointer kept during init, allows presence change notification
25097 + *
25098 + * Initialisation data specific to either the machine or the platform
25099 + * for the device driver to use or call-back when configuring gpio or
25100 + * card speed information.
25101 +*/
25102 +struct s3c_sdhci_platdata {
25103 +       unsigned int    max_width;
25104 +       unsigned int    host_caps;
25105 +
25106 +       char            **clocks;       /* set of clock sources */
25107 +
25108 +       void    (*cfg_gpio)(struct platform_device *dev, int width);
25109 +       void    (*cfg_card)(struct platform_device *dev,
25110 +                           void __iomem *regbase,
25111 +                           struct mmc_ios *ios,
25112 +                           struct mmc_card *card);
25113 +       struct sdhci_host * sdhci_host;
25114 +};
25115 +
25116 +extern void sdhci_s3c_force_presence_change(struct platform_device *pdev);
25117 +
25118 +/**
25119 + * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
25120 + * @pd: Platform data to register to device.
25121 + *
25122 + * Register the given platform data for use withe S3C SDHCI device.
25123 + * The call will copy the platform data, so the board definitions can
25124 + * make the structure itself __initdata.
25125 + */
25126 +extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
25127 +extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
25128 +
25129 +/* Default platform data, exported so that per-cpu initialisation can
25130 + * set the correct one when there are more than one cpu type selected.
25131 +*/
25132 +
25133 +extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
25134 +extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
25135 +
25136 +/* Helper function availablity */
25137 +
25138 +#ifdef CONFIG_S3C6410_SETUP_SDHCI
25139 +extern char *s3c6410_hsmmc_clksrcs[4];
25140 +
25141 +extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
25142 +extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
25143 +
25144 +extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
25145 +                                          void __iomem *r,
25146 +                                          struct mmc_ios *ios,
25147 +                                          struct mmc_card *card);
25148 +
25149 +#ifdef CONFIG_S3C_DEV_HSMMC
25150 +static inline void s3c6410_default_sdhci0(void)
25151 +{
25152 +       s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
25153 +       s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
25154 +       s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
25155 +}
25156 +#else
25157 +static inline void s3c6410_default_sdhci0(void) { }
25158 +#endif /* CONFIG_S3C_DEV_HSMMC */
25159 +
25160 +#ifdef CONFIG_S3C_DEV_HSMMC1
25161 +static inline void s3c6410_default_sdhci1(void)
25162 +{
25163 +       s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
25164 +       s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
25165 +       s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
25166 +}
25167 +#else
25168 +static inline void s3c6410_default_sdhci1(void) { }
25169 +#endif /* CONFIG_S3C_DEV_HSMMC1 */
25170 +
25171 +#else
25172 +static inline void s3c6410_default_sdhci0(void) { }
25173 +static inline void s3c6410_default_sdhci1(void) { }
25174 +#endif /* CONFIG_S3C6410_SETUP_SDHCI */
25175 +
25176 +#endif /* __PLAT_S3C_SDHCI_H */
25177 Index: linux-2.6.28/arch/arm/plat-s3c/include/plat/uncompress.h
25178 ===================================================================
25179 --- linux-2.6.28.orig/arch/arm/plat-s3c/include/plat/uncompress.h       2008-12-25 00:26:37.000000000 +0100
25180 +++ linux-2.6.28/arch/arm/plat-s3c/include/plat/uncompress.h    2009-01-02 00:01:56.000000000 +0100
25181 @@ -28,7 +28,7 @@ static void arch_detect_cpu(void);
25182  /* defines for UART registers */
25183
25184  #include <plat/regs-serial.h>
25185 -#include <asm/plat-s3c/regs-watchdog.h>
25186 +#include <plat/regs-watchdog.h>
25187
25188  /* working in physical space... */
25189  #undef S3C2410_WDOGREG
25190 @@ -37,7 +37,7 @@ static void arch_detect_cpu(void);
25191  /* how many bytes we allow into the FIFO at a time in FIFO mode */
25192  #define FIFO_MAX        (14)
25193
25194 -#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
25195 +#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
25196
25197  static __inline__ void
25198  uart_wr(unsigned int reg, unsigned int val)
25199 @@ -139,6 +139,28 @@ static void arch_decomp_error(const char
25200
25201  static void error(char *err);
25202
25203 +#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
25204 +static inline void arch_enable_uart_fifo(void)
25205 +{
25206 +       u32 fifocon = uart_rd(S3C2410_UFCON);
25207 +
25208 +       if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
25209 +               fifocon |= S3C2410_UFCON_RESETBOTH;
25210 +               uart_wr(S3C2410_UFCON, fifocon);
25211 +
25212 +               /* wait for fifo reset to complete */
25213 +               while (1) {
25214 +                       fifocon = uart_rd(S3C2410_UFCON);
25215 +                       if (!(fifocon & S3C2410_UFCON_RESETBOTH))
25216 +                               break;
25217 +               }
25218 +       }
25219 +}
25220 +#else
25221 +#define arch_enable_uart_fifo() do { } while(0)
25222 +#endif
25223 +
25224 +
25225  static void
25226  arch_decomp_setup(void)
25227  {
25228 @@ -149,6 +171,12 @@ arch_decomp_setup(void)
25229
25230         arch_detect_cpu();
25231         arch_decomp_wdog_start();
25232 +
25233 +       /* Enable the UART FIFOs if they where not enabled and our
25234 +        * configuration says we should turn them on.
25235 +        */
25236 +
25237 +       arch_enable_uart_fifo();
25238  }
25239
25240
25241 Index: linux-2.6.28/arch/arm/plat-s3c/init.c
25242 ===================================================================
25243 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
25244 +++ linux-2.6.28/arch/arm/plat-s3c/init.c       2009-01-02 00:01:56.000000000 +0100
25245 @@ -0,0 +1,161 @@
25246 +/* linux/arch/arm/plat-s3c/init.c
25247 + *
25248 + * Copyright (c) 2008 Simtec Electronics
25249 + *     Ben Dooks <ben@simtec.co.uk>
25250 + *     http://armlinux.simtec.co.uk/
25251 + *
25252 + * S3C series CPU initialisation
25253 + *
25254 + * This program is free software; you can redistribute it and/or modify
25255 + * it under the terms of the GNU General Public License version 2 as
25256 + * published by the Free Software Foundation.
25257 +*/
25258 +
25259 +#include <linux/init.h>
25260 +#include <linux/module.h>
25261 +#include <linux/interrupt.h>
25262 +#include <linux/ioport.h>
25263 +#include <linux/serial_core.h>
25264 +#include <linux/platform_device.h>
25265 +#include <linux/delay.h>
25266 +
25267 +#include <mach/hardware.h>
25268 +
25269 +#include <asm/mach/arch.h>
25270 +#include <asm/mach/map.h>
25271 +
25272 +#include <plat/cpu.h>
25273 +#include <plat/devs.h>
25274 +#include <plat/clock.h>
25275 +
25276 +#include <plat/regs-serial.h>
25277 +
25278 +static struct cpu_table *cpu;
25279 +
25280 +static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
25281 +                                               struct cpu_table *tab,
25282 +                                               unsigned int count)
25283 +{
25284 +       for (; count != 0; count--, tab++) {
25285 +               if ((idcode & tab->idmask) == tab->idcode)
25286 +                       return tab;
25287 +       }
25288 +
25289 +       return NULL;
25290 +}
25291 +
25292 +void __init s3c_init_cpu(unsigned long idcode,
25293 +                        struct cpu_table *cputab, unsigned int cputab_size)
25294 +{
25295 +       cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
25296 +
25297 +       if (cpu == NULL) {
25298 +               printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
25299 +               panic("Unknown S3C24XX CPU");
25300 +       }
25301 +
25302 +       printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
25303 +
25304 +       if (cpu->map_io == NULL || cpu->init == NULL) {
25305 +               printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
25306 +               panic("Unsupported Samsung CPU");
25307 +       }
25308 +
25309 +       cpu->map_io();
25310 +}
25311 +
25312 +/* s3c24xx_init_clocks
25313 + *
25314 + * Initialise the clock subsystem and associated information from the
25315 + * given master crystal value.
25316 + *
25317 + * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
25318 + *      != 0 -> PLL crystal value in Hz
25319 +*/
25320 +
25321 +void __init s3c24xx_init_clocks(int xtal)
25322 +{
25323 +       if (xtal == 0)
25324 +               xtal = 12*1000*1000;
25325 +
25326 +       if (cpu == NULL)
25327 +               panic("s3c24xx_init_clocks: no cpu setup?\n");
25328 +
25329 +       if (cpu->init_clocks == NULL)
25330 +               panic("s3c24xx_init_clocks: cpu has no clock init\n");
25331 +       else
25332 +               (cpu->init_clocks)(xtal);
25333 +}
25334 +
25335 +/* uart management */
25336 +
25337 +static int nr_uarts __initdata = 0;
25338 +
25339 +static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
25340 +
25341 +/* s3c24xx_init_uartdevs
25342 + *
25343 + * copy the specified platform data and configuration into our central
25344 + * set of devices, before the data is thrown away after the init process.
25345 + *
25346 + * This also fills in the array passed to the serial driver for the
25347 + * early initialisation of the console.
25348 +*/
25349 +
25350 +void __init s3c24xx_init_uartdevs(char *name,
25351 +                                 struct s3c24xx_uart_resources *res,
25352 +                                 struct s3c2410_uartcfg *cfg, int no)
25353 +{
25354 +       struct platform_device *platdev;
25355 +       struct s3c2410_uartcfg *cfgptr = uart_cfgs;
25356 +       struct s3c24xx_uart_resources *resp;
25357 +       int uart;
25358 +
25359 +       memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
25360 +
25361 +       for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
25362 +               platdev = s3c24xx_uart_src[cfgptr->hwport];
25363 +
25364 +               resp = res + cfgptr->hwport;
25365 +
25366 +               s3c24xx_uart_devs[uart] = platdev;
25367 +
25368 +               platdev->name = name;
25369 +               platdev->resource = resp->resources;
25370 +               platdev->num_resources = resp->nr_resources;
25371 +
25372 +               platdev->dev.platform_data = cfgptr;
25373 +       }
25374 +
25375 +       nr_uarts = no;
25376 +}
25377 +
25378 +void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
25379 +{
25380 +       if (cpu == NULL)
25381 +               return;
25382 +
25383 +       if (cpu->init_uarts == NULL) {
25384 +               printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
25385 +       } else
25386 +               (cpu->init_uarts)(cfg, no);
25387 +}
25388 +
25389 +static int __init s3c_arch_init(void)
25390 +{
25391 +       int ret;
25392 +
25393 +       // do the correct init for cpu
25394 +
25395 +       if (cpu == NULL)
25396 +               panic("s3c_arch_init: NULL cpu\n");
25397 +
25398 +       ret = (cpu->init)();
25399 +       if (ret != 0)
25400 +               return ret;
25401 +
25402 +       ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
25403 +       return ret;
25404 +}
25405 +
25406 +arch_initcall(s3c_arch_init);
25407 Index: linux-2.6.28/arch/arm/plat-s3c/Kconfig
25408 ===================================================================
25409 --- linux-2.6.28.orig/arch/arm/plat-s3c/Kconfig 2008-12-25 00:26:37.000000000 +0100
25410 +++ linux-2.6.28/arch/arm/plat-s3c/Kconfig      2009-01-02 00:01:56.000000000 +0100
25411 @@ -6,8 +6,8 @@
25412
25413  config PLAT_S3C
25414         bool
25415 -       depends on ARCH_S3C2410
25416 -       default y if ARCH_S3C2410
25417 +       depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
25418 +       default y
25419         select NO_IOPORT
25420         help
25421           Base platform code for any Samsung S3C device
25422 @@ -16,24 +16,24 @@ config PLAT_S3C
25423
25424  config CPU_LLSERIAL_S3C2410_ONLY
25425         bool
25426 -       depends on ARCH_S3C2410
25427 +       depends on PLAT_S3C
25428         default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
25429
25430  config CPU_LLSERIAL_S3C2440_ONLY
25431         bool
25432 -       depends on ARCH_S3C2410
25433 +       depends on PLAT_S3C
25434         default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
25435
25436  config CPU_LLSERIAL_S3C2410
25437         bool
25438 -       depends on ARCH_S3C2410
25439 +       depends on PLAT_S3C
25440         help
25441           Selected if there is an S3C2410 (or register compatible) serial
25442           low-level implementation needed
25443
25444  config CPU_LLSERIAL_S3C2440
25445         bool
25446 -       depends on ARCH_S3C2410
25447 +       depends on PLAT_S3C
25448         help
25449           Selected if there is an S3C2440 (or register compatible) serial
25450           low-level implementation needed
25451 @@ -57,6 +57,14 @@ config S3C_BOOT_ERROR_RESET
25452           Say y here to use the watchdog to reset the system if the
25453           kernel decompressor detects an error during decompression.
25454
25455 +config S3C_BOOT_UART_FORCE_FIFO
25456 +       bool "Force UART FIFO on during boot process"
25457 +       depends on PLAT_S3C
25458 +       default y
25459 +       help
25460 +         Say Y here to force the UART FIFOs on during the kernel
25461 +        uncompressor
25462 +
25463  comment "Power management"
25464
25465  config S3C2410_PM_DEBUG
25466 @@ -67,6 +75,15 @@ config S3C2410_PM_DEBUG
25467           Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
25468           for more information.
25469
25470 +config S3C_PM_DEBUG_LED_SMDK
25471 +       bool "SMDK LED suspend/resume debugging"
25472 +       depends on PM && (MACH_SMDK6410)
25473 +       help
25474 +         Say Y here to enable the use of the SMDK LEDs on the baseboard
25475 +        for debugging of the state of the suspend and resume process.
25476 +
25477 +        Note, this currently only works for S3C64XX based SMDK boards.
25478 +
25479  config S3C2410_PM_CHECK
25480         bool "S3C2410 PM Suspend Memory CRC"
25481         depends on PLAT_S3C && PM && CRC32
25482 @@ -102,3 +119,73 @@ config S3C_LOWLEVEL_UART_PORT
25483           such as the `Uncompressing...` at start time. The value of
25484           this configuration should be between zero and two. The port
25485           must have been initialised by the boot-loader before use.
25486 +
25487 +# options for gpiolib support
25488 +
25489 +config S3C_GPIO_SPACE
25490 +       int "Space between gpio banks"
25491 +       default 0
25492 +       help
25493 +         Add a number of spare GPIO entries between each bank for debugging
25494 +         purposes. This allows any problems where an counter overflows from
25495 +         one bank to another to be caught, at the expense of using a little
25496 +         more memory.
25497 +
25498 +config S3C_GPIO_TRACK
25499 +       bool
25500 +       help
25501 +         Internal configuration option to enable the s3c specific gpio
25502 +         chip tracking if the platform requires it.
25503 +
25504 +config S3C_GPIO_PULL_UPDOWN
25505 +       bool
25506 +       help
25507 +         Internal configuration to enable the correct GPIO pull helper
25508 +
25509 +config S3C_GPIO_PULL_DOWN
25510 +       bool
25511 +       help
25512 +         Internal configuration to enable the correct GPIO pull helper
25513 +
25514 +config S3C_GPIO_PULL_UP
25515 +       bool
25516 +       help
25517 +         Internal configuration to enable the correct GPIO pull helper
25518 +
25519 +config S3C_GPIO_CFG_S3C24XX
25520 +       bool
25521 +       help
25522 +         Internal configuration to enable S3C24XX style GPIO configuration
25523 +         functions.
25524 +
25525 +config S3C_GPIO_CFG_S3C64XX
25526 +       bool
25527 +       help
25528 +         Internal configuration to enable S3C64XX style GPIO configuration
25529 +         functions.
25530 +
25531 +# device definitions to compile in
25532 +
25533 +config S3C_DEV_HSMMC
25534 +       bool
25535 +       depends on PLAT_S3C
25536 +       help
25537 +         Compile in platform device definitions for HSMMC code
25538 +
25539 +config S3C_DEV_HSMMC1
25540 +       bool
25541 +       depends on PLAT_S3C
25542 +       help
25543 +         Compile in platform device definitions for HSMMC channel 1
25544 +
25545 +config S3C_DEV_I2C1
25546 +       bool
25547 +       depends on PLAT_S3C
25548 +       help
25549 +         Compile in platform device definitions for I2C channel 1
25550 +
25551 +config S3C_DEV_FB
25552 +       bool
25553 +       depends on PLAT_S3C
25554 +       help
25555 +         Compile in platform device definition for framebuffer
25556 Index: linux-2.6.28/arch/arm/plat-s3c/Makefile
25557 ===================================================================
25558 --- linux-2.6.28.orig/arch/arm/plat-s3c/Makefile        2008-12-25 00:26:37.000000000 +0100
25559 +++ linux-2.6.28/arch/arm/plat-s3c/Makefile     2009-01-02 00:01:56.000000000 +0100
25560 @@ -1,3 +1,33 @@
25561 -# dummy makefile, currently just including asm/arm/plat-s3c/include/plat
25562 +# arch/arm/plat-s3c/Makefile
25563 +#
25564 +# Copyright 2008 Simtec Electronics
25565 +#
25566 +# Licensed under GPLv2
25567
25568 -obj-n  := dummy.o
25569 +obj-y                          :=
25570 +obj-m                          :=
25571 +obj-n                          :=
25572 +obj-                           :=
25573 +
25574 +# Core support for all Samsung SoCs
25575 +
25576 +obj-y                          +=  init.o
25577 +obj-y                          += time.o
25578 +obj-y                          += clock.o
25579 +obj-y                          += pwm-clock.o
25580 +obj-y                          += gpio.o
25581 +obj-y                          += gpio-config.o
25582 +
25583 +# PM support
25584 +
25585 +obj-$(CONFIG_PM)               += pm.o
25586 +obj-$(CONFIG_PM)               += pm-gpio.o
25587 +obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
25588 +
25589 +# devices
25590 +
25591 +obj-$(CONFIG_S3C_DEV_HSMMC)    += dev-hsmmc.o
25592 +obj-$(CONFIG_S3C_DEV_HSMMC1)   += dev-hsmmc1.o
25593 +obj-y                          += dev-i2c0.o
25594 +obj-$(CONFIG_S3C_DEV_I2C1)     += dev-i2c1.o
25595 +obj-$(CONFIG_S3C_DEV_FB)       += dev-fb.o
25596 Index: linux-2.6.28/arch/arm/plat-s3c/pm.c
25597 ===================================================================
25598 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
25599 +++ linux-2.6.28/arch/arm/plat-s3c/pm.c 2009-01-02 00:01:56.000000000 +0100
25600 @@ -0,0 +1,387 @@
25601 +/* linux/arch/arm/plat-s3c/pm.c
25602 + *
25603 + * Copyright 2008 Openmoko, Inc.
25604 + * Copyright 2004,2006,2008 Simtec Electronics
25605 + *     Ben Dooks <ben@simtec.co.uk>
25606 + *     http://armlinux.simtec.co.uk/
25607 + *
25608 + * S3C common power management (suspend to ram) support.
25609 + *
25610 + * This program is free software; you can redistribute it and/or modify
25611 + * it under the terms of the GNU General Public License version 2 as
25612 + * published by the Free Software Foundation.
25613 +*/
25614 +
25615 +#include <linux/init.h>
25616 +#include <linux/suspend.h>
25617 +#include <linux/errno.h>
25618 +#include <linux/delay.h>
25619 +#include <linux/serial_core.h>
25620 +#include <linux/io.h>
25621 +#include <linux/regulator/machine.h>
25622 +
25623 +#include <asm/cacheflush.h>
25624 +#include <mach/hardware.h>
25625 +#include <mach/map.h>
25626 +
25627 +#include <plat/regs-serial.h>
25628 +#include <mach/regs-clock.h>
25629 +#include <mach/regs-irq.h>
25630 +#include <asm/irq.h>
25631 +
25632 +#include <plat/pm.h>
25633 +#include <plat/pm-core.h>
25634 +
25635 +/* for external use */
25636 +
25637 +unsigned long s3c_pm_flags;
25638 +
25639 +/* Debug code:
25640 + *
25641 + * This code supports debug output to the low level UARTs for use on
25642 + * resume before the console layer is available.
25643 +*/
25644 +
25645 +#ifdef CONFIG_S3C2410_PM_DEBUG
25646 +extern void printascii(const char *);
25647 +
25648 +void s3c_pm_dbg(const char *fmt, ...)
25649 +{
25650 +       va_list va;
25651 +       char buff[256];
25652 +
25653 +       va_start(va, fmt);
25654 +       vsprintf(buff, fmt, va);
25655 +       va_end(va);
25656 +
25657 +       printascii(buff);
25658 +}
25659 +
25660 +static inline void s3c_pm_debug_init(void)
25661 +{
25662 +       /* restart uart clocks so we can use them to output */
25663 +       s3c_pm_debug_init_uart();
25664 +}
25665 +
25666 +#else
25667 +#define s3c_pm_debug_init() do { } while(0)
25668 +
25669 +#endif /* CONFIG_S3C2410_PM_DEBUG */
25670 +
25671 +/* Save the UART configurations if we are configured for debug. */
25672 +
25673 +unsigned char pm_uart_udivslot;
25674 +
25675 +#ifdef CONFIG_S3C2410_PM_DEBUG
25676 +
25677 +struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
25678 +
25679 +static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
25680 +{
25681 +       void __iomem *regs = S3C_VA_UARTx(uart);
25682 +
25683 +       save->ulcon = __raw_readl(regs + S3C2410_ULCON);
25684 +       save->ucon = __raw_readl(regs + S3C2410_UCON);
25685 +       save->ufcon = __raw_readl(regs + S3C2410_UFCON);
25686 +       save->umcon = __raw_readl(regs + S3C2410_UMCON);
25687 +       save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
25688 +
25689 +       if (pm_uart_udivslot)
25690 +               save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
25691 +
25692 +       S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
25693 +                 uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
25694 +}
25695 +
25696 +static void s3c_pm_save_uarts(void)
25697 +{
25698 +       struct pm_uart_save *save = uart_save;
25699 +       unsigned int uart;
25700 +
25701 +       for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
25702 +               s3c_pm_save_uart(uart, save);
25703 +}
25704 +
25705 +static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
25706 +{
25707 +       void __iomem *regs = S3C_VA_UARTx(uart);
25708 +
25709 +       s3c_pm_arch_update_uart(regs, save);
25710 +
25711 +       __raw_writel(save->ulcon, regs + S3C2410_ULCON);
25712 +       __raw_writel(save->ucon,  regs + S3C2410_UCON);
25713 +       __raw_writel(save->ufcon, regs + S3C2410_UFCON);
25714 +       __raw_writel(save->umcon, regs + S3C2410_UMCON);
25715 +       __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
25716 +
25717 +       if (pm_uart_udivslot)
25718 +               __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
25719 +}
25720 +
25721 +static void s3c_pm_restore_uarts(void)
25722 +{
25723 +       struct pm_uart_save *save = uart_save;
25724 +       unsigned int uart;
25725 +
25726 +       for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
25727 +               s3c_pm_restore_uart(uart, save);
25728 +}
25729 +#else
25730 +static void s3c_pm_save_uarts(void) { }
25731 +static void s3c_pm_restore_uarts(void) { }
25732 +#endif
25733 +
25734 +/* The IRQ ext-int code goes here, it is too small to currently bother
25735 + * with its own file. */
25736 +
25737 +unsigned long s3c_irqwake_intmask      = 0xffffffffL;
25738 +unsigned long s3c_irqwake_eintmask     = 0xffffffffL;
25739 +
25740 +int s3c_irqext_wake(unsigned int irqno, unsigned int state)
25741 +{
25742 +       unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
25743 +
25744 +       if (!(s3c_irqwake_eintallow & bit))
25745 +               return -ENOENT;
25746 +
25747 +       printk(KERN_INFO "wake %s for irq %d\n",
25748 +              state ? "enabled" : "disabled", irqno);
25749 +
25750 +       if (!state)
25751 +               s3c_irqwake_eintmask |= bit;
25752 +       else
25753 +               s3c_irqwake_eintmask &= ~bit;
25754 +
25755 +       return 0;
25756 +}
25757 +
25758 +/* helper functions to save and restore register state */
25759 +
25760 +/**
25761 + * s3c_pm_do_save() - save a set of registers for restoration on resume.
25762 + * @ptr: Pointer to an array of registers.
25763 + * @count: Size of the ptr array.
25764 + *
25765 + * Run through the list of registers given, saving their contents in the
25766 + * array for later restoration when we wakeup.
25767 + */
25768 +void s3c_pm_do_save(struct sleep_save *ptr, int count)
25769 +{
25770 +       for (; count > 0; count--, ptr++) {
25771 +               ptr->val = __raw_readl(ptr->reg);
25772 +               S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
25773 +       }
25774 +}
25775 +
25776 +/**
25777 + * s3c_pm_do_restore() - restore register values from the save list.
25778 + * @ptr: Pointer to an array of registers.
25779 + * @count: Size of the ptr array.
25780 + *
25781 + * Restore the register values saved from s3c_pm_do_save().
25782 + *
25783 + * Note, we do not use S3C_PMDBG() in here, as the system may not have
25784 + * restore the UARTs state yet
25785 +*/
25786 +
25787 +void s3c_pm_do_restore(struct sleep_save *ptr, int count)
25788 +{
25789 +       for (; count > 0; count--, ptr++) {
25790 +               printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
25791 +                      ptr->reg, ptr->val, __raw_readl(ptr->reg));
25792 +
25793 +               __raw_writel(ptr->val, ptr->reg);
25794 +       }
25795 +}
25796 +
25797 +/**
25798 + * s3c_pm_do_restore_core() - early restore register values from save list.
25799 + *
25800 + * This is similar to s3c_pm_do_restore() except we try and minimise the
25801 + * side effects of the function in case registers that hardware might need
25802 + * to work has been restored.
25803 + *
25804 + * WARNING: Do not put any debug in here that may effect memory or use
25805 + * peripherals, as things may be changing!
25806 +*/
25807 +
25808 +void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
25809 +{
25810 +       for (; count > 0; count--, ptr++)
25811 +               __raw_writel(ptr->val, ptr->reg);
25812 +}
25813 +
25814 +/* s3c2410_pm_show_resume_irqs
25815 + *
25816 + * print any IRQs asserted at resume time (ie, we woke from)
25817 +*/
25818 +static void s3c_pm_show_resume_irqs(int start, unsigned long which,
25819 +                                   unsigned long mask)
25820 +{
25821 +       int i;
25822 +
25823 +       which &= ~mask;
25824 +
25825 +       for (i = 0; i <= 31; i++) {
25826 +               if (which & (1L<<i)) {
25827 +                       S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
25828 +               }
25829 +       }
25830 +}
25831 +
25832 +
25833 +void (*pm_cpu_prep)(void);
25834 +void (*pm_cpu_sleep)(void);
25835 +
25836 +#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
25837 +
25838 +/* s3c_pm_enter
25839 + *
25840 + * central control for sleep/resume process
25841 +*/
25842 +
25843 +static int s3c_pm_enter(suspend_state_t state)
25844 +{
25845 +       unsigned long regs_save[16];
25846 +
25847 +       /* ensure the debug is initialised (if enabled) */
25848 +
25849 +       s3c_pm_debug_init();
25850 +
25851 +       S3C_PMDBG("%s(%d)\n", __func__, state);
25852 +
25853 +       if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
25854 +               printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
25855 +               return -EINVAL;
25856 +       }
25857 +
25858 +       /* check if we have anything to wake-up with... bad things seem
25859 +        * to happen if you suspend with no wakeup (system will often
25860 +        * require a full power-cycle)
25861 +       */
25862 +
25863 +       if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
25864 +           !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
25865 +               printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
25866 +               printk(KERN_ERR "%s: Aborting sleep\n", __func__);
25867 +               return -EINVAL;
25868 +       }
25869 +
25870 +       /* store the physical address of the register recovery block */
25871 +
25872 +       s3c_sleep_save_phys = virt_to_phys(regs_save);
25873 +
25874 +       S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
25875 +
25876 +       /* save all necessary core registers not covered by the drivers */
25877 +
25878 +       s3c_pm_save_gpios();
25879 +       s3c_pm_save_uarts();
25880 +       s3c_pm_save_core();
25881 +
25882 +       /* set the irq configuration for wake */
25883 +
25884 +       s3c_pm_configure_extint();
25885 +
25886 +       S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
25887 +           s3c_irqwake_intmask, s3c_irqwake_eintmask);
25888 +
25889 +       s3c_pm_arch_prepare_irqs();
25890 +
25891 +       /* call cpu specific preparation */
25892 +
25893 +       pm_cpu_prep();
25894 +
25895 +       /* flush cache back to ram */
25896 +
25897 +       flush_cache_all();
25898 +
25899 +       s3c_pm_check_store();
25900 +
25901 +       /* send the cpu to sleep... */
25902 +
25903 +       s3c_pm_arch_stop_clocks();
25904 +
25905 +       /* s3c2410_cpu_save will also act as our return point from when
25906 +        * we resume as it saves its own register state, so use the return
25907 +        * code to differentiate return from save and return from sleep */
25908 +
25909 +       if (s3c_cpu_save(regs_save) == 0) {
25910 +               flush_cache_all();
25911 +               pm_cpu_sleep();
25912 +       }
25913 +
25914 +       /* restore the cpu state using the kernel's cpu init code. */
25915 +
25916 +       cpu_init();
25917 +
25918 +       /* restore the system state */
25919 +
25920 +       s3c_pm_restore_core();
25921 +       s3c_pm_restore_uarts();
25922 +       s3c_pm_restore_gpios();
25923 +
25924 +       s3c_pm_debug_init();
25925 +
25926 +       /* check what irq (if any) restored the system */
25927 +
25928 +       s3c_pm_arch_show_resume_irqs();
25929 +
25930 +       S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
25931 +
25932 +       s3c_pm_check_restore();
25933 +
25934 +       /* LEDs should now be 1110 */
25935 +       s3c_pm_debug_smdkled(1 << 1, 0);
25936 +
25937 +       /* ok, let's return from sleep */
25938 +
25939 +       S3C_PMDBG("S3C PM Resume (post-restore)\n");
25940 +       return 0;
25941 +}
25942 +
25943 +static int s3c_pm_prepare(void)
25944 +{
25945 +       /* prepare check area if configured */
25946 +
25947 +       s3c_pm_check_prepare();
25948 +       return 0;
25949 +}
25950 +
25951 +static void s3c_pm_finish(void)
25952 +{
25953 +       s3c_pm_check_cleanup();
25954 +}
25955 +
25956 +static int s3c_pm_begin(suspend_state_t state)
25957 +{
25958 +        int ret = 0;
25959 +
25960 +#ifdef CONFIG_REGULATOR
25961 +        ret = regulator_suspend_prepare(state);
25962 +#endif
25963 +        return ret;
25964 +}
25965 +
25966 +static struct platform_suspend_ops s3c_pm_ops = {
25967 +       .enter          = s3c_pm_enter,
25968 +       .prepare        = s3c_pm_prepare,
25969 +       .finish         = s3c_pm_finish,
25970 +       .valid          = suspend_valid_only_mem,
25971 +       .begin          = s3c_pm_begin,
25972 +};
25973 +
25974 +/* s3c_pm_init
25975 + *
25976 + * Attach the power management functions. This should be called
25977 + * from the board specific initialisation if the board supports
25978 + * it.
25979 +*/
25980 +
25981 +int __init s3c_pm_init(void)
25982 +{
25983 +       printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
25984 +
25985 +       suspend_set_ops(&s3c_pm_ops);
25986 +       return 0;
25987 +}
25988 Index: linux-2.6.28/arch/arm/plat-s3c/pm-check.c
25989 ===================================================================
25990 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
25991 +++ linux-2.6.28/arch/arm/plat-s3c/pm-check.c   2009-01-02 00:01:56.000000000 +0100
25992 @@ -0,0 +1,242 @@
25993 +/* linux/arch/arm/plat-s3c/pm-check.c
25994 + *  originally in linux/arch/arm/plat-s3c24xx/pm.c
25995 + *
25996 + * Copyright (c) 2004,2006,2008 Simtec Electronics
25997 + *     http://armlinux.simtec.co.uk
25998 + *     Ben Dooks <ben@simtec.co.uk>
25999 + *
26000 + * S3C Power Mangament - suspend/resume memory corruptiuon check.
26001 + *
26002 + * This program is free software; you can redistribute it and/or modify
26003 + * it under the terms of the GNU General Public License version 2 as
26004 + * published by the Free Software Foundation.
26005 +*/
26006 +
26007 +#include <linux/kernel.h>
26008 +#include <linux/suspend.h>
26009 +#include <linux/init.h>
26010 +#include <linux/crc32.h>
26011 +#include <linux/ioport.h>
26012 +
26013 +#include <plat/pm.h>
26014 +
26015 +#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1
26016 +#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value
26017 +#endif
26018 +
26019 +/* suspend checking code...
26020 + *
26021 + * this next area does a set of crc checks over all the installed
26022 + * memory, so the system can verify if the resume was ok.
26023 + *
26024 + * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
26025 + * increasing it will mean that the area corrupted will be less easy to spot,
26026 + * and reducing the size will cause the CRC save area to grow
26027 +*/
26028 +
26029 +#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
26030 +
26031 +static u32 crc_size;   /* size needed for the crc block */
26032 +static u32 *crcs;      /* allocated over suspend/resume */
26033 +
26034 +typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
26035 +
26036 +/* s3c_pm_run_res
26037 + *
26038 + * go through the given resource list, and look for system ram
26039 +*/
26040 +
26041 +static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
26042 +{
26043 +       while (ptr != NULL) {
26044 +               if (ptr->child != NULL)
26045 +                       s3c_pm_run_res(ptr->child, fn, arg);
26046 +
26047 +               if ((ptr->flags & IORESOURCE_MEM) &&
26048 +                   strcmp(ptr->name, "System RAM") == 0) {
26049 +                       S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
26050 +                                 (unsigned long)ptr->start,
26051 +                                 (unsigned long)ptr->end);
26052 +                       arg = (fn)(ptr, arg);
26053 +               }
26054 +
26055 +               ptr = ptr->sibling;
26056 +       }
26057 +}
26058 +
26059 +static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
26060 +{
26061 +       s3c_pm_run_res(&iomem_resource, fn, arg);
26062 +}
26063 +
26064 +static u32 *s3c_pm_countram(struct resource *res, u32 *val)
26065 +{
26066 +       u32 size = (u32)(res->end - res->start)+1;
26067 +
26068 +       size += CHECK_CHUNKSIZE-1;
26069 +       size /= CHECK_CHUNKSIZE;
26070 +
26071 +       S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
26072 +                 (unsigned long)res->start, (unsigned long)res->end, size);
26073 +
26074 +       *val += size * sizeof(u32);
26075 +       return val;
26076 +}
26077 +
26078 +/* s3c_pm_prepare_check
26079 + *
26080 + * prepare the necessary information for creating the CRCs. This
26081 + * must be done before the final save, as it will require memory
26082 + * allocating, and thus touching bits of the kernel we do not
26083 + * know about.
26084 +*/
26085 +
26086 +void s3c_pm_check_prepare(void)
26087 +{
26088 +       crc_size = 0;
26089 +
26090 +       s3c_pm_run_sysram(s3c_pm_countram, &crc_size);
26091 +
26092 +       S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);
26093 +
26094 +       crcs = kmalloc(crc_size+4, GFP_KERNEL);
26095 +       if (crcs == NULL)
26096 +               printk(KERN_ERR "Cannot allocated CRC save area\n");
26097 +}
26098 +
26099 +static u32 *s3c_pm_makecheck(struct resource *res, u32 *val)
26100 +{
26101 +       unsigned long addr, left;
26102 +
26103 +       for (addr = res->start; addr < res->end;
26104 +            addr += CHECK_CHUNKSIZE) {
26105 +               left = res->end - addr;
26106 +
26107 +               if (left > CHECK_CHUNKSIZE)
26108 +                       left = CHECK_CHUNKSIZE;
26109 +
26110 +               *val = crc32_le(~0, phys_to_virt(addr), left);
26111 +               val++;
26112 +       }
26113 +
26114 +       return val;
26115 +}
26116 +
26117 +/* s3c_pm_check_store
26118 + *
26119 + * compute the CRC values for the memory blocks before the final
26120 + * sleep.
26121 +*/
26122 +
26123 +void s3c_pm_check_store(void)
26124 +{
26125 +       if (crcs != NULL)
26126 +               s3c_pm_run_sysram(s3c_pm_makecheck, crcs);
26127 +}
26128 +
26129 +/* in_region
26130 + *
26131 + * return TRUE if the area defined by ptr..ptr+size contains the
26132 + * what..what+whatsz
26133 +*/
26134 +
26135 +static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
26136 +{
26137 +       if ((what+whatsz) < ptr)
26138 +               return 0;
26139 +
26140 +       if (what > (ptr+size))
26141 +               return 0;
26142 +
26143 +       return 1;
26144 +}
26145 +
26146 +/**
26147 + * s3c_pm_runcheck() - helper to check a resource on restore.
26148 + * @res: The resource to check
26149 + * @vak: Pointer to list of CRC32 values to check.
26150 + *
26151 + * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
26152 + * function runs the given memory resource checking it against the stored
26153 + * CRC to ensure that memory is restored. The function tries to skip as
26154 + * many of the areas used during the suspend process.
26155 + */
26156 +static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
26157 +{
26158 +       void *save_at = phys_to_virt(s3c_sleep_save_phys);
26159 +       unsigned long addr;
26160 +       unsigned long left;
26161 +       void *stkpage;
26162 +       void *ptr;
26163 +       u32 calc;
26164 +
26165 +       stkpage = (void *)((u32)&calc & ~PAGE_MASK);
26166 +
26167 +       for (addr = res->start; addr < res->end;
26168 +            addr += CHECK_CHUNKSIZE) {
26169 +               left = res->end - addr;
26170 +
26171 +               if (left > CHECK_CHUNKSIZE)
26172 +                       left = CHECK_CHUNKSIZE;
26173 +
26174 +               ptr = phys_to_virt(addr);
26175 +
26176 +               if (in_region(ptr, left, stkpage, 4096)) {
26177 +                       S3C_PMDBG("skipping %08lx, has stack in\n", addr);
26178 +                       goto skip_check;
26179 +               }
26180 +
26181 +               if (in_region(ptr, left, crcs, crc_size)) {
26182 +                       S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
26183 +                       goto skip_check;
26184 +               }
26185 +
26186 +               if (in_region(ptr, left, save_at, 32*4 )) {
26187 +                       S3C_PMDBG("skipping %08lx, has save block in\n", addr);
26188 +                       goto skip_check;
26189 +               }
26190 +
26191 +               /* calculate and check the checksum */
26192 +
26193 +               calc = crc32_le(~0, ptr, left);
26194 +               if (calc != *val) {
26195 +                       printk(KERN_ERR "Restore CRC error at "
26196 +                              "%08lx (%08x vs %08x)\n", addr, calc, *val);
26197 +
26198 +                       S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
26199 +                           addr, calc, *val);
26200 +               }
26201 +
26202 +       skip_check:
26203 +               val++;
26204 +       }
26205 +
26206 +       return val;
26207 +}
26208 +
26209 +/**
26210 + * s3c_pm_check_restore() - memory check called on resume
26211 + *
26212 + * check the CRCs after the restore event and free the memory used
26213 + * to hold them
26214 +*/
26215 +void s3c_pm_check_restore(void)
26216 +{
26217 +       if (crcs != NULL)
26218 +               s3c_pm_run_sysram(s3c_pm_runcheck, crcs);
26219 +}
26220 +
26221 +/**
26222 + * s3c_pm_check_cleanup() - free memory resources
26223 + *
26224 + * Free the resources that where allocated by the suspend
26225 + * memory check code. We do this separately from the
26226 + * s3c_pm_check_restore() function as we cannot call any
26227 + * functions that might sleep during that resume.
26228 + */
26229 +void s3c_pm_check_cleanup(void)
26230 +{
26231 +       kfree(crcs);
26232 +       crcs = NULL;
26233 +}
26234 +
26235 Index: linux-2.6.28/arch/arm/plat-s3c/pm-gpio.c
26236 ===================================================================
26237 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
26238 +++ linux-2.6.28/arch/arm/plat-s3c/pm-gpio.c    2009-01-02 00:01:56.000000000 +0100
26239 @@ -0,0 +1,378 @@
26240 +/* linux/arch/arm/plat-s3c/pm-gpio.c
26241 + *
26242 + * Copyright 2008 Openmoko, Inc.
26243 + * Copyright 2008 Simtec Electronics
26244 + *     Ben Dooks <ben@simtec.co.uk>
26245 + *     http://armlinux.simtec.co.uk/
26246 + *
26247 + * S3C series GPIO PM code
26248 + *
26249 + * This program is free software; you can redistribute it and/or modify
26250 + * it under the terms of the GNU General Public License version 2 as
26251 + * published by the Free Software Foundation.
26252 +*/
26253 +
26254 +#include <linux/kernel.h>
26255 +#include <linux/init.h>
26256 +#include <linux/io.h>
26257 +#include <linux/gpio.h>
26258 +
26259 +#include <mach/gpio-core.h>
26260 +#include <plat/pm.h>
26261 +
26262 +/* PM GPIO helpers */
26263 +
26264 +#define OFFS_CON       (0x00)
26265 +#define OFFS_DAT       (0X04)
26266 +#define OFFS_UP                (0X08)
26267 +
26268 +static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
26269 +{
26270 +       chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
26271 +       chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
26272 +}
26273 +
26274 +static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
26275 +{
26276 +       void __iomem *base = chip->base;
26277 +       u32 old_gpcon = __raw_readl(base + OFFS_CON);
26278 +       u32 old_gpdat = __raw_readl(base + OFFS_DAT);
26279 +       u32 gps_gpcon = chip->pm_save[0];
26280 +       u32 gps_gpdat = chip->pm_save[1];
26281 +       u32 gpcon;
26282 +
26283 +       /* GPACON only has one bit per control / data and no PULLUPs.
26284 +        * GPACON[x] = 0 => Output, 1 => SFN */
26285 +
26286 +       /* first set all SFN bits to SFN */
26287 +
26288 +       gpcon = old_gpcon | gps_gpcon;
26289 +       __raw_writel(gpcon, base + OFFS_CON);
26290 +
26291 +       /* now set all the other bits */
26292 +
26293 +       __raw_writel(gps_gpdat, base + OFFS_DAT);
26294 +       __raw_writel(gps_gpcon, base + OFFS_CON);
26295 +
26296 +       S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
26297 +                 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
26298 +}
26299 +
26300 +struct s3c_gpio_pm s3c_gpio_pm_1bit = {
26301 +       .save   = s3c_gpio_pm_1bit_save,
26302 +       .resume = s3c_gpio_pm_1bit_resume,
26303 +};
26304 +
26305 +static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
26306 +{
26307 +       chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
26308 +       chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
26309 +       chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
26310 +}
26311 +
26312 +/* Test whether the given masked+shifted bits of an GPIO configuration
26313 + * are one of the SFN (special function) modes. */
26314 +
26315 +static inline int is_sfn(unsigned long con)
26316 +{
26317 +       return con >= 2;
26318 +}
26319 +
26320 +/* Test if the given masked+shifted GPIO configuration is an input */
26321 +
26322 +static inline int is_in(unsigned long con)
26323 +{
26324 +       return con == 0;
26325 +}
26326 +
26327 +/* Test if the given masked+shifted GPIO configuration is an output */
26328 +
26329 +static inline int is_out(unsigned long con)
26330 +{
26331 +       return con == 1;
26332 +}
26333 +
26334 +/**
26335 + * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
26336 + * @chip: The chip information to resume.
26337 + *
26338 + * Restore one of the GPIO banks that was saved during suspend. This is
26339 + * not as simple as once thought, due to the possibility of glitches
26340 + * from the order that the CON and DAT registers are set in.
26341 + *
26342 + * The three states the pin can be are {IN,OUT,SFN} which gives us 9
26343 + * combinations of changes to check. Three of these, if the pin stays
26344 + * in the same configuration can be discounted. This leaves us with
26345 + * the following:
26346 + *
26347 + * { IN => OUT }  Change DAT first
26348 + * { IN => SFN }  Change CON first
26349 + * { OUT => SFN } Change CON first, so new data will not glitch
26350 + * { OUT => IN }  Change CON first, so new data will not glitch
26351 + * { SFN => IN }  Change CON first
26352 + * { SFN => OUT } Change DAT first, so new data will not glitch [1]
26353 + *
26354 + * We do not currently deal with the UP registers as these control
26355 + * weak resistors, so a small delay in change should not need to bring
26356 + * these into the calculations.
26357 + *
26358 + * [1] this assumes that writing to a pin DAT whilst in SFN will set the
26359 + *     state for when it is next output.
26360 + */
26361 +static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
26362 +{
26363 +       void __iomem *base = chip->base;
26364 +       u32 old_gpcon = __raw_readl(base + OFFS_CON);
26365 +       u32 old_gpdat = __raw_readl(base + OFFS_DAT);
26366 +       u32 gps_gpcon = chip->pm_save[0];
26367 +       u32 gps_gpdat = chip->pm_save[1];
26368 +       u32 gpcon, old, new, mask;
26369 +       u32 change_mask = 0x0;
26370 +       int nr;
26371 +
26372 +       /* restore GPIO pull-up settings */
26373 +       __raw_writel(chip->pm_save[2], base + OFFS_UP);
26374 +
26375 +       /* Create a change_mask of all the items that need to have
26376 +        * their CON value changed before their DAT value, so that
26377 +        * we minimise the work between the two settings.
26378 +        */
26379 +
26380 +       for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
26381 +               old = (old_gpcon & mask) >> nr;
26382 +               new = (gps_gpcon & mask) >> nr;
26383 +
26384 +               /* If there is no change, then skip */
26385 +
26386 +               if (old == new)
26387 +                       continue;
26388 +
26389 +               /* If both are special function, then skip */
26390 +
26391 +               if (is_sfn(old) && is_sfn(new))
26392 +                       continue;
26393 +
26394 +               /* Change is IN => OUT, do not change now */
26395 +
26396 +               if (is_in(old) && is_out(new))
26397 +                       continue;
26398 +
26399 +               /* Change is SFN => OUT, do not change now */
26400 +
26401 +               if (is_sfn(old) && is_out(new))
26402 +                       continue;
26403 +
26404 +               /* We should now be at the case of IN=>SFN,
26405 +                * OUT=>SFN, OUT=>IN, SFN=>IN. */
26406 +
26407 +               change_mask |= mask;
26408 +       }
26409 +
26410 +
26411 +       /* Write the new CON settings */
26412 +
26413 +       gpcon = old_gpcon & ~change_mask;
26414 +       gpcon |= gps_gpcon & change_mask;
26415 +
26416 +       __raw_writel(gpcon, base + OFFS_CON);
26417 +
26418 +       /* Now change any items that require DAT,CON */
26419 +
26420 +       __raw_writel(gps_gpdat, base + OFFS_DAT);
26421 +       __raw_writel(gps_gpcon, base + OFFS_CON);
26422 +
26423 +       S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
26424 +                 chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
26425 +}
26426 +
26427 +struct s3c_gpio_pm s3c_gpio_pm_2bit = {
26428 +       .save   = s3c_gpio_pm_2bit_save,
26429 +       .resume = s3c_gpio_pm_2bit_resume,
26430 +};
26431 +
26432 +#ifdef CONFIG_ARCH_S3C64XX
26433 +static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
26434 +{
26435 +       chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
26436 +       chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
26437 +       chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
26438 +
26439 +       if (chip->chip.ngpio > 8)
26440 +               chip->pm_save[0] = __raw_readl(chip->base - 4);
26441 +}
26442 +
26443 +static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
26444 +{
26445 +       u32 old, new, mask;
26446 +       u32 change_mask = 0x0;
26447 +       int nr;
26448 +
26449 +       for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
26450 +               old = (old_gpcon & mask) >> nr;
26451 +               new = (gps_gpcon & mask) >> nr;
26452 +
26453 +               /* If there is no change, then skip */
26454 +
26455 +               if (old == new)
26456 +                       continue;
26457 +
26458 +               /* If both are special function, then skip */
26459 +
26460 +               if (is_sfn(old) && is_sfn(new))
26461 +                       continue;
26462 +
26463 +               /* Change is IN => OUT, do not change now */
26464 +
26465 +               if (is_in(old) && is_out(new))
26466 +                       continue;
26467 +
26468 +               /* Change is SFN => OUT, do not change now */
26469 +
26470 +               if (is_sfn(old) && is_out(new))
26471 +                       continue;
26472 +
26473 +               /* We should now be at the case of IN=>SFN,
26474 +                * OUT=>SFN, OUT=>IN, SFN=>IN. */
26475 +
26476 +               change_mask |= mask;
26477 +       }
26478 +
26479 +       return change_mask;
26480 +}
26481 +
26482 +static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
26483 +{
26484 +       void __iomem *con = chip->base + (index * 4);
26485 +       u32 old_gpcon = __raw_readl(con);
26486 +       u32 gps_gpcon = chip->pm_save[index + 1];
26487 +       u32 gpcon, mask;
26488 +
26489 +       mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
26490 +
26491 +       gpcon = old_gpcon & ~mask;
26492 +       gpcon |= gps_gpcon & mask;
26493 +
26494 +       __raw_writel(gpcon, con);
26495 +}
26496 +
26497 +static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
26498 +{
26499 +       void __iomem *base = chip->base;
26500 +       u32 old_gpcon[2];
26501 +       u32 old_gpdat = __raw_readl(base + OFFS_DAT);
26502 +       u32 gps_gpdat = chip->pm_save[2];
26503 +
26504 +       /* First, modify the CON settings */
26505 +
26506 +       old_gpcon[0] = 0;
26507 +       old_gpcon[1] = __raw_readl(base + OFFS_CON);
26508 +
26509 +       s3c_gpio_pm_4bit_con(chip, 0);
26510 +       if (chip->chip.ngpio > 8) {
26511 +               old_gpcon[0] = __raw_readl(base - 4);
26512 +               s3c_gpio_pm_4bit_con(chip, -1);
26513 +       }
26514 +
26515 +       /* Now change the configurations that require DAT,CON */
26516 +
26517 +       __raw_writel(chip->pm_save[2], base + OFFS_DAT);
26518 +       __raw_writel(chip->pm_save[1], base + OFFS_CON);
26519 +       if (chip->chip.ngpio > 8)
26520 +               __raw_writel(chip->pm_save[0], base - 4);
26521 +
26522 +       __raw_writel(chip->pm_save[2], base + OFFS_DAT);
26523 +       __raw_writel(chip->pm_save[3], base + OFFS_UP);
26524 +
26525 +       if (chip->chip.ngpio > 8) {
26526 +               S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
26527 +                         chip->chip.label, old_gpcon[0], old_gpcon[1],
26528 +                         __raw_readl(base - 4),
26529 +                         __raw_readl(base + OFFS_CON),
26530 +                         old_gpdat, gps_gpdat);
26531 +       } else
26532 +               S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
26533 +                         chip->chip.label, old_gpcon[1],
26534 +                         __raw_readl(base + OFFS_CON),
26535 +                         old_gpdat, gps_gpdat);
26536 +}
26537 +
26538 +struct s3c_gpio_pm s3c_gpio_pm_4bit = {
26539 +       .save   = s3c_gpio_pm_4bit_save,
26540 +       .resume = s3c_gpio_pm_4bit_resume,
26541 +};
26542 +#endif /* CONFIG_ARCH_S3C64XX */
26543 +
26544 +/**
26545 + * s3c_pm_save_gpio() - save gpio chip data for suspend
26546 + * @ourchip: The chip for suspend.
26547 + */
26548 +static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
26549 +{
26550 +       struct s3c_gpio_pm *pm = ourchip->pm;
26551 +
26552 +       if (pm == NULL || pm->save == NULL)
26553 +               S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
26554 +       else
26555 +               pm->save(ourchip);
26556 +}
26557 +
26558 +/**
26559 + * s3c_pm_save_gpios() - Save the state of the GPIO banks.
26560 + *
26561 + * For all the GPIO banks, save the state of each one ready for going
26562 + * into a suspend mode.
26563 + */
26564 +void s3c_pm_save_gpios(void)
26565 +{
26566 +       struct s3c_gpio_chip *ourchip;
26567 +       unsigned int gpio_nr;
26568 +
26569 +       for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
26570 +               ourchip = s3c_gpiolib_getchip(gpio_nr);
26571 +               if (!ourchip)
26572 +                       continue;
26573 +
26574 +               s3c_pm_save_gpio(ourchip);
26575 +
26576 +               S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
26577 +                         ourchip->chip.label,
26578 +                         ourchip->pm_save[0],
26579 +                         ourchip->pm_save[1],
26580 +                         ourchip->pm_save[2],
26581 +                         ourchip->pm_save[3]);
26582 +
26583 +               gpio_nr += ourchip->chip.ngpio;
26584 +               gpio_nr += CONFIG_S3C_GPIO_SPACE;
26585 +       }
26586 +}
26587 +
26588 +/**
26589 + * s3c_pm_resume_gpio() - restore gpio chip data after suspend
26590 + * @ourchip: The suspended chip.
26591 + */
26592 +static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
26593 +{
26594 +       struct s3c_gpio_pm *pm = ourchip->pm;
26595 +
26596 +       if (pm == NULL || pm->resume == NULL)
26597 +               S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
26598 +       else
26599 +               pm->resume(ourchip);
26600 +}
26601 +
26602 +void s3c_pm_restore_gpios(void)
26603 +{
26604 +       struct s3c_gpio_chip *ourchip;
26605 +       unsigned int gpio_nr;
26606 +
26607 +       for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
26608 +               ourchip = s3c_gpiolib_getchip(gpio_nr);
26609 +               if (!ourchip)
26610 +                       continue;
26611 +
26612 +               s3c_pm_resume_gpio(ourchip);
26613 +
26614 +               gpio_nr += ourchip->chip.ngpio;
26615 +               gpio_nr += CONFIG_S3C_GPIO_SPACE;
26616 +       }
26617 +}
26618 Index: linux-2.6.28/arch/arm/plat-s3c/pwm-clock.c
26619 ===================================================================
26620 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
26621 +++ linux-2.6.28/arch/arm/plat-s3c/pwm-clock.c  2009-01-02 00:01:56.000000000 +0100
26622 @@ -0,0 +1,463 @@
26623 +/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
26624 + *
26625 + * Copyright (c) 2007 Simtec Electronics
26626 + * Copyright (c) 2007, 2008 Ben Dooks
26627 + *     Ben Dooks <ben-linux@fluff.org>
26628 + *
26629 + * This program is free software; you can redistribute it and/or modify
26630 + * it under the terms of the GNU General Public License as published by
26631 + * the Free Software Foundation; either version 2 of the License.
26632 +*/
26633 +
26634 +#include <linux/init.h>
26635 +#include <linux/module.h>
26636 +#include <linux/kernel.h>
26637 +#include <linux/list.h>
26638 +#include <linux/errno.h>
26639 +#include <linux/log2.h>
26640 +#include <linux/clk.h>
26641 +#include <linux/err.h>
26642 +#include <linux/io.h>
26643 +
26644 +#include <mach/hardware.h>
26645 +#include <mach/map.h>
26646 +#include <asm/irq.h>
26647 +
26648 +#include <plat/clock.h>
26649 +#include <plat/cpu.h>
26650 +
26651 +#include <plat/regs-timer.h>
26652 +#include <mach/pwm-clock.h>
26653 +
26654 +/* Each of the timers 0 through 5 go through the following
26655 + * clock tree, with the inputs depending on the timers.
26656 + *
26657 + * pclk ---- [ prescaler 0 ] -+---> timer 0
26658 + *                           +---> timer 1
26659 + *
26660 + * pclk ---- [ prescaler 1 ] -+---> timer 2
26661 + *                           +---> timer 3
26662 + *                           \---> timer 4
26663 + *
26664 + * Which are fed into the timers as so:
26665 + *
26666 + * prescaled 0 ---- [ div 2,4,8,16 ] ---\
26667 + *                                    [mux] -> timer 0
26668 + * tclk 0 ------------------------------/
26669 + *
26670 + * prescaled 0 ---- [ div 2,4,8,16 ] ---\
26671 + *                                    [mux] -> timer 1
26672 + * tclk 0 ------------------------------/
26673 + *
26674 + *
26675 + * prescaled 1 ---- [ div 2,4,8,16 ] ---\
26676 + *                                    [mux] -> timer 2
26677 + * tclk 1 ------------------------------/
26678 + *
26679 + * prescaled 1 ---- [ div 2,4,8,16 ] ---\
26680 + *                                    [mux] -> timer 3
26681 + * tclk 1 ------------------------------/
26682 + *
26683 + * prescaled 1 ---- [ div 2,4,8, 16 ] --\
26684 + *                                    [mux] -> timer 4
26685 + * tclk 1 ------------------------------/
26686 + *
26687 + * Since the mux and the divider are tied together in the
26688 + * same register space, it is impossible to set the parent
26689 + * and the rate at the same time. To avoid this, we add an
26690 + * intermediate 'prescaled-and-divided' clock to select
26691 + * as the parent for the timer input clock called tdiv.
26692 + *
26693 + * prescaled clk --> pwm-tdiv ---\
26694 + *                             [ mux ] --> timer X
26695 + * tclk -------------------------/
26696 +*/
26697 +
26698 +static struct clk clk_timer_scaler[];
26699 +
26700 +static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
26701 +{
26702 +       unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
26703 +
26704 +       if (clk == &clk_timer_scaler[1]) {
26705 +               tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
26706 +               tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
26707 +       } else {
26708 +               tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
26709 +       }
26710 +
26711 +       return clk_get_rate(clk->parent) / (tcfg0 + 1);
26712 +}
26713 +
26714 +static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
26715 +                                              unsigned long rate)
26716 +{
26717 +       unsigned long parent_rate = clk_get_rate(clk->parent);
26718 +       unsigned long divisor = parent_rate / rate;
26719 +
26720 +       if (divisor > 256)
26721 +               divisor = 256;
26722 +       else if (divisor < 2)
26723 +               divisor = 2;
26724 +
26725 +       return parent_rate / divisor;
26726 +}
26727 +
26728 +static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
26729 +{
26730 +       unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
26731 +       unsigned long tcfg0;
26732 +       unsigned long divisor;
26733 +       unsigned long flags;
26734 +
26735 +       divisor = clk_get_rate(clk->parent) / round;
26736 +       divisor--;
26737 +
26738 +       local_irq_save(flags);
26739 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
26740 +
26741 +       if (clk == &clk_timer_scaler[1]) {
26742 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
26743 +               tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
26744 +       } else {
26745 +               tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
26746 +               tcfg0 |= divisor;
26747 +       }
26748 +
26749 +       __raw_writel(tcfg0, S3C2410_TCFG0);
26750 +       local_irq_restore(flags);
26751 +
26752 +       return 0;
26753 +}
26754 +
26755 +static struct clk clk_timer_scaler[] = {
26756 +       [0]     = {
26757 +               .name           = "pwm-scaler0",
26758 +               .id             = -1,
26759 +               .get_rate       = clk_pwm_scaler_get_rate,
26760 +               .set_rate       = clk_pwm_scaler_set_rate,
26761 +               .round_rate     = clk_pwm_scaler_round_rate,
26762 +       },
26763 +       [1]     = {
26764 +               .name           = "pwm-scaler1",
26765 +               .id             = -1,
26766 +               .get_rate       = clk_pwm_scaler_get_rate,
26767 +               .set_rate       = clk_pwm_scaler_set_rate,
26768 +               .round_rate     = clk_pwm_scaler_round_rate,
26769 +       },
26770 +};
26771 +
26772 +static struct clk clk_timer_tclk[] = {
26773 +       [0]     = {
26774 +               .name           = "pwm-tclk0",
26775 +               .id             = -1,
26776 +       },
26777 +       [1]     = {
26778 +               .name           = "pwm-tclk1",
26779 +               .id             = -1,
26780 +       },
26781 +};
26782 +
26783 +struct pwm_tdiv_clk {
26784 +       struct clk      clk;
26785 +       unsigned int    divisor;
26786 +};
26787 +
26788 +static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
26789 +{
26790 +       return container_of(clk, struct pwm_tdiv_clk, clk);
26791 +}
26792 +
26793 +static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
26794 +{
26795 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26796 +       unsigned int divisor;
26797 +
26798 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
26799 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
26800 +
26801 +       if (pwm_cfg_src_is_tclk(tcfg1))
26802 +               divisor = to_tdiv(clk)->divisor;
26803 +       else
26804 +               divisor = tcfg_to_divisor(tcfg1);
26805 +
26806 +       return clk_get_rate(clk->parent) / divisor;
26807 +}
26808 +
26809 +static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
26810 +                                            unsigned long rate)
26811 +{
26812 +       unsigned long parent_rate;
26813 +       unsigned long divisor;
26814 +
26815 +       parent_rate = clk_get_rate(clk->parent);
26816 +       divisor = parent_rate / rate;
26817 +
26818 +       if (divisor <= 1 && pwm_tdiv_has_div1())
26819 +               divisor = 1;
26820 +       else if (divisor <= 2)
26821 +               divisor = 2;
26822 +       else if (divisor <= 4)
26823 +               divisor = 4;
26824 +       else if (divisor <= 8)
26825 +               divisor = 8;
26826 +       else
26827 +               divisor = 16;
26828 +
26829 +       return parent_rate / divisor;
26830 +}
26831 +
26832 +static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
26833 +{
26834 +       return pwm_tdiv_div_bits(divclk->divisor);
26835 +}
26836 +
26837 +static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
26838 +{
26839 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26840 +       unsigned long bits = clk_pwm_tdiv_bits(divclk);
26841 +       unsigned long flags;
26842 +       unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
26843 +
26844 +       local_irq_save(flags);
26845 +
26846 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
26847 +       tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
26848 +       tcfg1 |= bits << shift;
26849 +       __raw_writel(tcfg1, S3C2410_TCFG1);
26850 +
26851 +       local_irq_restore(flags);
26852 +}
26853 +
26854 +static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
26855 +{
26856 +       struct pwm_tdiv_clk *divclk = to_tdiv(clk);
26857 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26858 +       unsigned long parent_rate = clk_get_rate(clk->parent);
26859 +       unsigned long divisor;
26860 +
26861 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
26862 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
26863 +
26864 +       rate = clk_round_rate(clk, rate);
26865 +       divisor = parent_rate / rate;
26866 +
26867 +       if (divisor > 16)
26868 +               return -EINVAL;
26869 +
26870 +       divclk->divisor = divisor;
26871 +
26872 +       /* Update the current MUX settings if we are currently
26873 +        * selected as the clock source for this clock. */
26874 +
26875 +       if (!pwm_cfg_src_is_tclk(tcfg1))
26876 +               clk_pwm_tdiv_update(divclk);
26877 +
26878 +       return 0;
26879 +}
26880 +
26881 +static struct pwm_tdiv_clk clk_timer_tdiv[] = {
26882 +       [0]     = {
26883 +               .clk    = {
26884 +                       .name           = "pwm-tdiv",
26885 +                       .parent         = &clk_timer_scaler[0],
26886 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26887 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26888 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26889 +               },
26890 +       },
26891 +       [1]     = {
26892 +               .clk    = {
26893 +                       .name           = "pwm-tdiv",
26894 +                       .parent         = &clk_timer_scaler[0],
26895 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26896 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26897 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26898 +               }
26899 +       },
26900 +       [2]     = {
26901 +               .clk    = {
26902 +                       .name           = "pwm-tdiv",
26903 +                       .parent         = &clk_timer_scaler[1],
26904 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26905 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26906 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26907 +               },
26908 +       },
26909 +       [3]     = {
26910 +               .clk    = {
26911 +                       .name           = "pwm-tdiv",
26912 +                       .parent         = &clk_timer_scaler[1],
26913 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26914 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26915 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26916 +               },
26917 +       },
26918 +       [4]     = {
26919 +               .clk    = {
26920 +                       .name           = "pwm-tdiv",
26921 +                       .parent         = &clk_timer_scaler[1],
26922 +                       .get_rate       = clk_pwm_tdiv_get_rate,
26923 +                       .set_rate       = clk_pwm_tdiv_set_rate,
26924 +                       .round_rate     = clk_pwm_tdiv_round_rate,
26925 +               },
26926 +       },
26927 +};
26928 +
26929 +static int __init clk_pwm_tdiv_register(unsigned int id)
26930 +{
26931 +       struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
26932 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
26933 +
26934 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
26935 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
26936 +
26937 +       divclk->clk.id = id;
26938 +       divclk->divisor = tcfg_to_divisor(tcfg1);
26939 +
26940 +       return s3c24xx_register_clock(&divclk->clk);
26941 +}
26942 +
26943 +static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
26944 +{
26945 +       return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
26946 +}
26947 +
26948 +static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
26949 +{
26950 +       return &clk_timer_tdiv[id].clk;
26951 +}
26952 +
26953 +static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
26954 +{
26955 +       unsigned int id = clk->id;
26956 +       unsigned long tcfg1;
26957 +       unsigned long flags;
26958 +       unsigned long bits;
26959 +       unsigned long shift = S3C2410_TCFG1_SHIFT(id);
26960 +
26961 +       if (parent == s3c24xx_pwmclk_tclk(id))
26962 +               bits = S3C_TCFG1_MUX_TCLK << shift;
26963 +       else if (parent == s3c24xx_pwmclk_tdiv(id))
26964 +               bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
26965 +       else
26966 +               return -EINVAL;
26967 +
26968 +       clk->parent = parent;
26969 +
26970 +       local_irq_save(flags);
26971 +
26972 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
26973 +       tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
26974 +       __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
26975 +
26976 +       local_irq_restore(flags);
26977 +
26978 +       return 0;
26979 +}
26980 +
26981 +static struct clk clk_tin[] = {
26982 +       [0]     = {
26983 +               .name           = "pwm-tin",
26984 +               .id             = 0,
26985 +               .set_parent     = clk_pwm_tin_set_parent,
26986 +       },
26987 +       [1]     = {
26988 +               .name           = "pwm-tin",
26989 +               .id             = 1,
26990 +               .set_parent     = clk_pwm_tin_set_parent,
26991 +       },
26992 +       [2]     = {
26993 +               .name           = "pwm-tin",
26994 +               .id             = 2,
26995 +               .set_parent     = clk_pwm_tin_set_parent,
26996 +       },
26997 +       [3]     = {
26998 +               .name           = "pwm-tin",
26999 +               .id             = 3,
27000 +               .set_parent     = clk_pwm_tin_set_parent,
27001 +       },
27002 +       [4]     = {
27003 +               .name           = "pwm-tin",
27004 +               .id             = 4,
27005 +               .set_parent     = clk_pwm_tin_set_parent,
27006 +       },
27007 +};
27008 +
27009 +static __init int clk_pwm_tin_register(struct clk *pwm)
27010 +{
27011 +       unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
27012 +       unsigned int id = pwm->id;
27013 +
27014 +       struct clk *parent;
27015 +       int ret;
27016 +
27017 +       ret = s3c24xx_register_clock(pwm);
27018 +       if (ret < 0)
27019 +               return ret;
27020 +
27021 +       tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
27022 +       tcfg1 &= S3C2410_TCFG1_MUX_MASK;
27023 +
27024 +       if (pwm_cfg_src_is_tclk(tcfg1))
27025 +               parent = s3c24xx_pwmclk_tclk(id);
27026 +       else
27027 +               parent = s3c24xx_pwmclk_tdiv(id);
27028 +
27029 +       return clk_set_parent(pwm, parent);
27030 +}
27031 +
27032 +/**
27033 + * s3c_pwmclk_init() - initialise pwm clocks
27034 + *
27035 + * Initialise and register the clocks which provide the inputs for the
27036 + * pwm timer blocks.
27037 + *
27038 + * Note, this call is required by the time core, so must be called after
27039 + * the base clocks are added and before any of the initcalls are run.
27040 + */
27041 +__init void s3c_pwmclk_init(void)
27042 +{
27043 +       struct clk *clk_timers;
27044 +       unsigned int clk;
27045 +       int ret;
27046 +
27047 +       clk_timers = clk_get(NULL, "timers");
27048 +       if (IS_ERR(clk_timers)) {
27049 +               printk(KERN_ERR "%s: no parent clock\n", __func__);
27050 +               return;
27051 +       }
27052 +
27053 +       for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
27054 +               clk_timer_scaler[clk].parent = clk_timers;
27055 +               ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
27056 +               if (ret < 0) {
27057 +                       printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
27058 +                       return;
27059 +               }
27060 +       }
27061 +
27062 +       for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
27063 +               ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
27064 +               if (ret < 0) {
27065 +                       printk(KERN_ERR "error adding pww tclk%d\n", clk);
27066 +                       return;
27067 +               }
27068 +       }
27069 +
27070 +       for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
27071 +               ret = clk_pwm_tdiv_register(clk);
27072 +               if (ret < 0) {
27073 +                       printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
27074 +                       return;
27075 +               }
27076 +       }
27077 +
27078 +       for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
27079 +               ret = clk_pwm_tin_register(&clk_tin[clk]);
27080 +               if (ret < 0) {
27081 +                       printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
27082 +                       return;
27083 +               }
27084 +       }
27085 +}
27086 Index: linux-2.6.28/arch/arm/plat-s3c/time.c
27087 ===================================================================
27088 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
27089 +++ linux-2.6.28/arch/arm/plat-s3c/time.c       2009-01-02 00:01:56.000000000 +0100
27090 @@ -0,0 +1,285 @@
27091 +/* linux/arch/arm/plat-s3c24xx/time.c
27092 + *
27093 + * Copyright (C) 2003-2005 Simtec Electronics
27094 + *     Ben Dooks, <ben@simtec.co.uk>
27095 + *
27096 + * This program is free software; you can redistribute it and/or modify
27097 + * it under the terms of the GNU General Public License as published by
27098 + * the Free Software Foundation; either version 2 of the License, or
27099 + * (at your option) any later version.
27100 + *
27101 + * This program is distributed in the hope that it will be useful,
27102 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
27103 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
27104 + * GNU General Public License for more details.
27105 + *
27106 + * You should have received a copy of the GNU General Public License
27107 + * along with this program; if not, write to the Free Software
27108 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
27109 + */
27110 +
27111 +#include <linux/kernel.h>
27112 +#include <linux/sched.h>
27113 +#include <linux/init.h>
27114 +#include <linux/interrupt.h>
27115 +#include <linux/irq.h>
27116 +#include <linux/err.h>
27117 +#include <linux/clk.h>
27118 +#include <linux/io.h>
27119 +#include <linux/platform_device.h>
27120 +
27121 +#include <asm/system.h>
27122 +#include <asm/leds.h>
27123 +#include <asm/mach-types.h>
27124 +
27125 +#include <asm/irq.h>
27126 +#include <mach/map.h>
27127 +#include <plat/regs-timer.h>
27128 +#include <mach/regs-irq.h>
27129 +#include <asm/mach/time.h>
27130 +#include <mach/tick.h>
27131 +
27132 +#include <plat/clock.h>
27133 +#include <plat/cpu.h>
27134 +
27135 +static unsigned long timer_startval;
27136 +static unsigned long timer_usec_ticks;
27137 +
27138 +#ifndef TICK_MAX
27139 +#define TICK_MAX (0xffff)
27140 +#endif
27141 +
27142 +#define TIMER_USEC_SHIFT 16
27143 +
27144 +/* we use the shifted arithmetic to work out the ratio of timer ticks
27145 + * to usecs, as often the peripheral clock is not a nice even multiple
27146 + * of 1MHz.
27147 + *
27148 + * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
27149 + * for the current HZ value of 200 without producing overflows.
27150 + *
27151 + * Original patch by Dimitry Andric, updated by Ben Dooks
27152 +*/
27153 +
27154 +
27155 +/* timer_mask_usec_ticks
27156 + *
27157 + * given a clock and divisor, make the value to pass into timer_ticks_to_usec
27158 + * to scale the ticks into usecs
27159 +*/
27160 +
27161 +static inline unsigned long
27162 +timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
27163 +{
27164 +       unsigned long den = pclk / 1000;
27165 +
27166 +       return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
27167 +}
27168 +
27169 +/* timer_ticks_to_usec
27170 + *
27171 + * convert timer ticks to usec.
27172 +*/
27173 +
27174 +static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
27175 +{
27176 +       unsigned long res;
27177 +
27178 +       res = ticks * timer_usec_ticks;
27179 +       res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
27180 +
27181 +       return res >> TIMER_USEC_SHIFT;
27182 +}
27183 +
27184 +/***
27185 + * Returns microsecond  since last clock interrupt.  Note that interrupts
27186 + * will have been disabled by do_gettimeoffset()
27187 + * IRQs are disabled before entering here from do_gettimeofday()
27188 + */
27189 +
27190 +static unsigned long s3c2410_gettimeoffset (void)
27191 +{
27192 +       unsigned long tdone;
27193 +       unsigned long tval;
27194 +
27195 +       /* work out how many ticks have gone since last timer interrupt */
27196 +
27197 +       tval =  __raw_readl(S3C2410_TCNTO(4));
27198 +       tdone = timer_startval - tval;
27199 +
27200 +       /* check to see if there is an interrupt pending */
27201 +
27202 +       if (s3c24xx_ostimer_pending()) {
27203 +               /* re-read the timer, and try and fix up for the missed
27204 +                * interrupt. Note, the interrupt may go off before the
27205 +                * timer has re-loaded from wrapping.
27206 +                */
27207 +
27208 +               tval =  __raw_readl(S3C2410_TCNTO(4));
27209 +               tdone = timer_startval - tval;
27210 +
27211 +               if (tval != 0)
27212 +                       tdone += timer_startval;
27213 +       }
27214 +
27215 +       return timer_ticks_to_usec(tdone);
27216 +}
27217 +
27218 +
27219 +/*
27220 + * IRQ handler for the timer
27221 + */
27222 +static irqreturn_t
27223 +s3c2410_timer_interrupt(int irq, void *dev_id)
27224 +{
27225 +       timer_tick();
27226 +       return IRQ_HANDLED;
27227 +}
27228 +
27229 +static struct irqaction s3c2410_timer_irq = {
27230 +       .name           = "S3C2410 Timer Tick",
27231 +       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
27232 +       .handler        = s3c2410_timer_interrupt,
27233 +};
27234 +
27235 +#define use_tclk1_12() ( \
27236 +       machine_is_bast()       || \
27237 +       machine_is_vr1000()     || \
27238 +       machine_is_anubis()     || \
27239 +       machine_is_osiris())
27240 +
27241 +static struct clk *tin;
27242 +static struct clk *tdiv;
27243 +static struct clk *timerclk;
27244 +
27245 +/*
27246 + * Set up timer interrupt, and return the current time in seconds.
27247 + *
27248 + * Currently we only use timer4, as it is the only timer which has no
27249 + * other function that can be exploited externally
27250 + */
27251 +static void s3c2410_timer_setup (void)
27252 +{
27253 +       unsigned long tcon;
27254 +       unsigned long tcnt;
27255 +       unsigned long tcfg1;
27256 +       unsigned long tcfg0;
27257 +
27258 +       tcnt = TICK_MAX;  /* default value for tcnt */
27259 +
27260 +       /* configure the system for whichever machine is in use */
27261 +
27262 +       if (use_tclk1_12()) {
27263 +               /* timer is at 12MHz, scaler is 1 */
27264 +               timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
27265 +               tcnt = 12000000 / HZ;
27266 +
27267 +               tcfg1 = __raw_readl(S3C2410_TCFG1);
27268 +               tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
27269 +               tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
27270 +               __raw_writel(tcfg1, S3C2410_TCFG1);
27271 +       } else {
27272 +               unsigned long pclk;
27273 +               struct clk *tscaler;
27274 +
27275 +               /* for the h1940 (and others), we use the pclk from the core
27276 +                * to generate the timer values. since values around 50 to
27277 +                * 70MHz are not values we can directly generate the timer
27278 +                * value from, we need to pre-scale and divide before using it.
27279 +                *
27280 +                * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
27281 +                * (8.45 ticks per usec)
27282 +                */
27283 +
27284 +               pclk = clk_get_rate(timerclk);
27285 +
27286 +               /* configure clock tick */
27287 +
27288 +               timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
27289 +
27290 +               tscaler = clk_get_parent(tdiv);
27291 +
27292 +               clk_set_rate(tscaler, pclk / 3);
27293 +               clk_set_rate(tdiv, pclk / 6);
27294 +               clk_set_parent(tin, tdiv);
27295 +
27296 +               tcnt = clk_get_rate(tin) / HZ;
27297 +       }
27298 +
27299 +       tcon = __raw_readl(S3C2410_TCON);
27300 +       tcfg0 = __raw_readl(S3C2410_TCFG0);
27301 +       tcfg1 = __raw_readl(S3C2410_TCFG1);
27302 +
27303 +       /* timers reload after counting zero, so reduce the count by 1 */
27304 +
27305 +       tcnt--;
27306 +
27307 +       printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
27308 +              tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
27309 +
27310 +       /* check to see if timer is within 16bit range... */
27311 +       if (tcnt > TICK_MAX) {
27312 +               panic("setup_timer: HZ is too small, cannot configure timer!");
27313 +               return;
27314 +       }
27315 +
27316 +       __raw_writel(tcfg1, S3C2410_TCFG1);
27317 +       __raw_writel(tcfg0, S3C2410_TCFG0);
27318 +
27319 +       timer_startval = tcnt;
27320 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
27321 +
27322 +       /* ensure timer is stopped... */
27323 +
27324 +       tcon &= ~(7<<20);
27325 +       tcon |= S3C2410_TCON_T4RELOAD;
27326 +       tcon |= S3C2410_TCON_T4MANUALUPD;
27327 +
27328 +       __raw_writel(tcon, S3C2410_TCON);
27329 +       __raw_writel(tcnt, S3C2410_TCNTB(4));
27330 +       __raw_writel(tcnt, S3C2410_TCMPB(4));
27331 +
27332 +       /* start the timer running */
27333 +       tcon |= S3C2410_TCON_T4START;
27334 +       tcon &= ~S3C2410_TCON_T4MANUALUPD;
27335 +       __raw_writel(tcon, S3C2410_TCON);
27336 +}
27337 +
27338 +static void __init s3c2410_timer_resources(void)
27339 +{
27340 +       struct platform_device tmpdev;
27341 +
27342 +       tmpdev.dev.bus = &platform_bus_type;
27343 +       tmpdev.id = 4;
27344 +
27345 +       timerclk = clk_get(NULL, "timers");
27346 +       if (IS_ERR(timerclk))
27347 +               panic("failed to get clock for system timer");
27348 +
27349 +       clk_enable(timerclk);
27350 +
27351 +       if (!use_tclk1_12()) {
27352 +               tin = clk_get(&tmpdev.dev, "pwm-tin");
27353 +               if (IS_ERR(tin))
27354 +                       panic("failed to get pwm-tin clock for system timer");
27355 +
27356 +               tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
27357 +               if (IS_ERR(tdiv))
27358 +                       panic("failed to get pwm-tdiv clock for system timer");
27359 +       }
27360 +
27361 +       clk_enable(tin);
27362 +}
27363 +
27364 +static void __init s3c2410_timer_init(void)
27365 +{
27366 +       s3c2410_timer_resources();
27367 +       s3c2410_timer_setup();
27368 +       setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
27369 +}
27370 +
27371 +struct sys_timer s3c24xx_timer = {
27372 +       .init           = s3c2410_timer_init,
27373 +       .offset         = s3c2410_gettimeoffset,
27374 +       .resume         = s3c2410_timer_setup
27375 +};
27376 Index: linux-2.6.28/arch/arm/plat-s3c24xx/clock.c
27377 ===================================================================
27378 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/clock.c     2008-12-25 00:26:37.000000000 +0100
27379 +++ linux-2.6.28/arch/arm/plat-s3c24xx/clock.c  2009-01-02 00:01:56.000000000 +0100
27380 @@ -27,18 +27,8 @@
27381  */
27382
27383  #include <linux/init.h>
27384 -#include <linux/module.h>
27385  #include <linux/kernel.h>
27386 -#include <linux/list.h>
27387 -#include <linux/errno.h>
27388 -#include <linux/err.h>
27389 -#include <linux/platform_device.h>
27390 -#include <linux/sysdev.h>
27391 -#include <linux/interrupt.h>
27392 -#include <linux/ioport.h>
27393  #include <linux/clk.h>
27394 -#include <linux/mutex.h>
27395 -#include <linux/delay.h>
27396  #include <linux/io.h>
27397
27398  #include <mach/hardware.h>
27399 @@ -47,490 +37,23 @@
27400  #include <mach/regs-clock.h>
27401  #include <mach/regs-gpio.h>
27402
27403 +#include <plat/cpu-freq.h>
27404 +
27405  #include <plat/clock.h>
27406  #include <plat/cpu.h>
27407 -
27408 -/* clock information */
27409 -
27410 -static LIST_HEAD(clocks);
27411 -
27412 -DEFINE_MUTEX(clocks_mutex);
27413 -
27414 -/* enable and disable calls for use with the clk struct */
27415 -
27416 -static int clk_null_enable(struct clk *clk, int enable)
27417 -{
27418 -       return 0;
27419 -}
27420 -
27421 -/* Clock API calls */
27422 -
27423 -struct clk *clk_get(struct device *dev, const char *id)
27424 -{
27425 -       struct clk *p;
27426 -       struct clk *clk = ERR_PTR(-ENOENT);
27427 -       int idno;
27428 -
27429 -       if (dev == NULL || dev->bus != &platform_bus_type)
27430 -               idno = -1;
27431 -       else
27432 -               idno = to_platform_device(dev)->id;
27433 -
27434 -       mutex_lock(&clocks_mutex);
27435 -
27436 -       list_for_each_entry(p, &clocks, list) {
27437 -               if (p->id == idno &&
27438 -                   strcmp(id, p->name) == 0 &&
27439 -                   try_module_get(p->owner)) {
27440 -                       clk = p;
27441 -                       break;
27442 -               }
27443 -       }
27444 -
27445 -       /* check for the case where a device was supplied, but the
27446 -        * clock that was being searched for is not device specific */
27447 -
27448 -       if (IS_ERR(clk)) {
27449 -               list_for_each_entry(p, &clocks, list) {
27450 -                       if (p->id == -1 && strcmp(id, p->name) == 0 &&
27451 -                           try_module_get(p->owner)) {
27452 -                               clk = p;
27453 -                               break;
27454 -                       }
27455 -               }
27456 -       }
27457 -
27458 -       mutex_unlock(&clocks_mutex);
27459 -       return clk;
27460 -}
27461 -
27462 -void clk_put(struct clk *clk)
27463 -{
27464 -       module_put(clk->owner);
27465 -}
27466 -
27467 -int clk_enable(struct clk *clk)
27468 -{
27469 -       if (IS_ERR(clk) || clk == NULL)
27470 -               return -EINVAL;
27471 -
27472 -       clk_enable(clk->parent);
27473 -
27474 -       mutex_lock(&clocks_mutex);
27475 -
27476 -       if ((clk->usage++) == 0)
27477 -               (clk->enable)(clk, 1);
27478 -
27479 -       mutex_unlock(&clocks_mutex);
27480 -       return 0;
27481 -}
27482 -
27483 -void clk_disable(struct clk *clk)
27484 -{
27485 -       if (IS_ERR(clk) || clk == NULL)
27486 -               return;
27487 -
27488 -       mutex_lock(&clocks_mutex);
27489 -
27490 -       if ((--clk->usage) == 0)
27491 -               (clk->enable)(clk, 0);
27492 -
27493 -       mutex_unlock(&clocks_mutex);
27494 -       clk_disable(clk->parent);
27495 -}
27496 -
27497 -
27498 -unsigned long clk_get_rate(struct clk *clk)
27499 -{
27500 -       if (IS_ERR(clk))
27501 -               return 0;
27502 -
27503 -       if (clk->rate != 0)
27504 -               return clk->rate;
27505 -
27506 -       if (clk->get_rate != NULL)
27507 -               return (clk->get_rate)(clk);
27508 -
27509 -       if (clk->parent != NULL)
27510 -               return clk_get_rate(clk->parent);
27511 -
27512 -       return clk->rate;
27513 -}
27514 -
27515 -long clk_round_rate(struct clk *clk, unsigned long rate)
27516 -{
27517 -       if (!IS_ERR(clk) && clk->round_rate)
27518 -               return (clk->round_rate)(clk, rate);
27519 -
27520 -       return rate;
27521 -}
27522 -
27523 -int clk_set_rate(struct clk *clk, unsigned long rate)
27524 -{
27525 -       int ret;
27526 -
27527 -       if (IS_ERR(clk))
27528 -               return -EINVAL;
27529 -
27530 -       /* We do not default just do a clk->rate = rate as
27531 -        * the clock may have been made this way by choice.
27532 -        */
27533 -
27534 -       WARN_ON(clk->set_rate == NULL);
27535 -
27536 -       if (clk->set_rate == NULL)
27537 -               return -EINVAL;
27538 -
27539 -       mutex_lock(&clocks_mutex);
27540 -       ret = (clk->set_rate)(clk, rate);
27541 -       mutex_unlock(&clocks_mutex);
27542 -
27543 -       return ret;
27544 -}
27545 -
27546 -struct clk *clk_get_parent(struct clk *clk)
27547 -{
27548 -       return clk->parent;
27549 -}
27550 -
27551 -int clk_set_parent(struct clk *clk, struct clk *parent)
27552 -{
27553 -       int ret = 0;
27554 -
27555 -       if (IS_ERR(clk))
27556 -               return -EINVAL;
27557 -
27558 -       mutex_lock(&clocks_mutex);
27559 -
27560 -       if (clk->set_parent)
27561 -               ret = (clk->set_parent)(clk, parent);
27562 -
27563 -       mutex_unlock(&clocks_mutex);
27564 -
27565 -       return ret;
27566 -}
27567 -
27568 -EXPORT_SYMBOL(clk_get);
27569 -EXPORT_SYMBOL(clk_put);
27570 -EXPORT_SYMBOL(clk_enable);
27571 -EXPORT_SYMBOL(clk_disable);
27572 -EXPORT_SYMBOL(clk_get_rate);
27573 -EXPORT_SYMBOL(clk_round_rate);
27574 -EXPORT_SYMBOL(clk_set_rate);
27575 -EXPORT_SYMBOL(clk_get_parent);
27576 -EXPORT_SYMBOL(clk_set_parent);
27577 -
27578 -/* base clocks */
27579 -
27580 -static int clk_default_setrate(struct clk *clk, unsigned long rate)
27581 -{
27582 -       clk->rate = rate;
27583 -       return 0;
27584 -}
27585 -
27586 -struct clk clk_xtal = {
27587 -       .name           = "xtal",
27588 -       .id             = -1,
27589 -       .rate           = 0,
27590 -       .parent         = NULL,
27591 -       .ctrlbit        = 0,
27592 -};
27593 -
27594 -struct clk clk_mpll = {
27595 -       .name           = "mpll",
27596 -       .id             = -1,
27597 -       .set_rate       = clk_default_setrate,
27598 -};
27599 -
27600 -struct clk clk_upll = {
27601 -       .name           = "upll",
27602 -       .id             = -1,
27603 -       .parent         = NULL,
27604 -       .ctrlbit        = 0,
27605 -};
27606 -
27607 -struct clk clk_f = {
27608 -       .name           = "fclk",
27609 -       .id             = -1,
27610 -       .rate           = 0,
27611 -       .parent         = &clk_mpll,
27612 -       .ctrlbit        = 0,
27613 -       .set_rate       = clk_default_setrate,
27614 -};
27615 -
27616 -struct clk clk_h = {
27617 -       .name           = "hclk",
27618 -       .id             = -1,
27619 -       .rate           = 0,
27620 -       .parent         = NULL,
27621 -       .ctrlbit        = 0,
27622 -       .set_rate       = clk_default_setrate,
27623 -};
27624 -
27625 -struct clk clk_p = {
27626 -       .name           = "pclk",
27627 -       .id             = -1,
27628 -       .rate           = 0,
27629 -       .parent         = NULL,
27630 -       .ctrlbit        = 0,
27631 -       .set_rate       = clk_default_setrate,
27632 -};
27633 -
27634 -struct clk clk_usb_bus = {
27635 -       .name           = "usb-bus",
27636 -       .id             = -1,
27637 -       .rate           = 0,
27638 -       .parent         = &clk_upll,
27639 -};
27640 -
27641 -/* clocks that could be registered by external code */
27642 -
27643 -static int s3c24xx_dclk_enable(struct clk *clk, int enable)
27644 -{
27645 -       unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
27646 -
27647 -       if (enable)
27648 -               dclkcon |= clk->ctrlbit;
27649 -       else
27650 -               dclkcon &= ~clk->ctrlbit;
27651 -
27652 -       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27653 -
27654 -       return 0;
27655 -}
27656 -
27657 -static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
27658 -{
27659 -       unsigned long dclkcon;
27660 -       unsigned int uclk;
27661 -
27662 -       if (parent == &clk_upll)
27663 -               uclk = 1;
27664 -       else if (parent == &clk_p)
27665 -               uclk = 0;
27666 -       else
27667 -               return -EINVAL;
27668 -
27669 -       clk->parent = parent;
27670 -
27671 -       dclkcon = __raw_readl(S3C24XX_DCLKCON);
27672 -
27673 -       if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
27674 -               if (uclk)
27675 -                       dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
27676 -               else
27677 -                       dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
27678 -       } else {
27679 -               if (uclk)
27680 -                       dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
27681 -               else
27682 -                       dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
27683 -       }
27684 -
27685 -       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27686 -
27687 -       return 0;
27688 -}
27689 -
27690 -static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
27691 -{
27692 -       unsigned long div;
27693 -
27694 -       if ((rate == 0) || !clk->parent)
27695 -               return 0;
27696 -
27697 -       div = clk_get_rate(clk->parent) / rate;
27698 -       if (div < 2)
27699 -               div = 2;
27700 -       else if (div > 16)
27701 -               div = 16;
27702 -
27703 -       return div;
27704 -}
27705 -
27706 -static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
27707 -       unsigned long rate)
27708 -{
27709 -       unsigned long div = s3c24xx_calc_div(clk, rate);
27710 -
27711 -       if (div == 0)
27712 -               return 0;
27713 -
27714 -       return clk_get_rate(clk->parent) / div;
27715 -}
27716 -
27717 -static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
27718 -{
27719 -       unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
27720 -
27721 -       if (div == 0)
27722 -               return -EINVAL;
27723 -
27724 -       if (clk == &s3c24xx_dclk0) {
27725 -               mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
27726 -                       S3C2410_DCLKCON_DCLK0_CMP_MASK;
27727 -               data = S3C2410_DCLKCON_DCLK0_DIV(div) |
27728 -                       S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
27729 -       } else if (clk == &s3c24xx_dclk1) {
27730 -               mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
27731 -                       S3C2410_DCLKCON_DCLK1_CMP_MASK;
27732 -               data = S3C2410_DCLKCON_DCLK1_DIV(div) |
27733 -                       S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
27734 -       } else
27735 -               return -EINVAL;
27736 -
27737 -       clk->rate = clk_get_rate(clk->parent) / div;
27738 -       __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
27739 -               S3C24XX_DCLKCON);
27740 -       return clk->rate;
27741 -}
27742 -
27743 -static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
27744 -{
27745 -       unsigned long mask;
27746 -       unsigned long source;
27747 -
27748 -       /* calculate the MISCCR setting for the clock */
27749 -
27750 -       if (parent == &clk_xtal)
27751 -               source = S3C2410_MISCCR_CLK0_MPLL;
27752 -       else if (parent == &clk_upll)
27753 -               source = S3C2410_MISCCR_CLK0_UPLL;
27754 -       else if (parent == &clk_f)
27755 -               source = S3C2410_MISCCR_CLK0_FCLK;
27756 -       else if (parent == &clk_h)
27757 -               source = S3C2410_MISCCR_CLK0_HCLK;
27758 -       else if (parent == &clk_p)
27759 -               source = S3C2410_MISCCR_CLK0_PCLK;
27760 -       else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
27761 -               source = S3C2410_MISCCR_CLK0_DCLK0;
27762 -       else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
27763 -               source = S3C2410_MISCCR_CLK0_DCLK0;
27764 -       else
27765 -               return -EINVAL;
27766 -
27767 -       clk->parent = parent;
27768 -
27769 -       if (clk == &s3c24xx_clkout0)
27770 -               mask = S3C2410_MISCCR_CLK0_MASK;
27771 -       else {
27772 -               source <<= 4;
27773 -               mask = S3C2410_MISCCR_CLK1_MASK;
27774 -       }
27775 -
27776 -       s3c2410_modify_misccr(mask, source);
27777 -       return 0;
27778 -}
27779 -
27780 -/* external clock definitions */
27781 -
27782 -struct clk s3c24xx_dclk0 = {
27783 -       .name           = "dclk0",
27784 -       .id             = -1,
27785 -       .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
27786 -       .enable         = s3c24xx_dclk_enable,
27787 -       .set_parent     = s3c24xx_dclk_setparent,
27788 -       .set_rate       = s3c24xx_set_dclk_rate,
27789 -       .round_rate     = s3c24xx_round_dclk_rate,
27790 -};
27791 -
27792 -struct clk s3c24xx_dclk1 = {
27793 -       .name           = "dclk1",
27794 -       .id             = -1,
27795 -       .ctrlbit        = S3C2410_DCLKCON_DCLK1EN,
27796 -       .enable         = s3c24xx_dclk_enable,
27797 -       .set_parent     = s3c24xx_dclk_setparent,
27798 -       .set_rate       = s3c24xx_set_dclk_rate,
27799 -       .round_rate     = s3c24xx_round_dclk_rate,
27800 -};
27801 -
27802 -struct clk s3c24xx_clkout0 = {
27803 -       .name           = "clkout0",
27804 -       .id             = -1,
27805 -       .set_parent     = s3c24xx_clkout_setparent,
27806 -};
27807 -
27808 -struct clk s3c24xx_clkout1 = {
27809 -       .name           = "clkout1",
27810 -       .id             = -1,
27811 -       .set_parent     = s3c24xx_clkout_setparent,
27812 -};
27813 -
27814 -struct clk s3c24xx_uclk = {
27815 -       .name           = "uclk",
27816 -       .id             = -1,
27817 -};
27818 -
27819 -/* initialise the clock system */
27820 -
27821 -int s3c24xx_register_clock(struct clk *clk)
27822 -{
27823 -       clk->owner = THIS_MODULE;
27824 -
27825 -       if (clk->enable == NULL)
27826 -               clk->enable = clk_null_enable;
27827 -
27828 -       /* add to the list of available clocks */
27829 -
27830 -       mutex_lock(&clocks_mutex);
27831 -       list_add(&clk->list, &clocks);
27832 -       mutex_unlock(&clocks_mutex);
27833 -
27834 -       return 0;
27835 -}
27836 -
27837 -int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
27838 -{
27839 -       int fails = 0;
27840 -
27841 -       for (; nr_clks > 0; nr_clks--, clks++) {
27842 -               if (s3c24xx_register_clock(*clks) < 0)
27843 -                       fails++;
27844 -       }
27845 -
27846 -       return fails;
27847 -}
27848 +#include <plat/pll.h>
27849
27850  /* initalise all the clocks */
27851
27852 -int __init s3c24xx_setup_clocks(unsigned long xtal,
27853 -                               unsigned long fclk,
27854 -                               unsigned long hclk,
27855 -                               unsigned long pclk)
27856 +void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
27857 +                                          unsigned long hclk,
27858 +                                          unsigned long pclk)
27859  {
27860 -       printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
27861 -
27862 -       /* initialise the main system clocks */
27863 -
27864 -       clk_xtal.rate = xtal;
27865 -       clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
27866 +       clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
27867 +                                       clk_xtal.rate);
27868
27869         clk_mpll.rate = fclk;
27870         clk_h.rate = hclk;
27871         clk_p.rate = pclk;
27872         clk_f.rate = fclk;
27873 -
27874 -       /* assume uart clocks are correctly setup */
27875 -
27876 -       /* register our clocks */
27877 -
27878 -       if (s3c24xx_register_clock(&clk_xtal) < 0)
27879 -               printk(KERN_ERR "failed to register master xtal\n");
27880 -
27881 -       if (s3c24xx_register_clock(&clk_mpll) < 0)
27882 -               printk(KERN_ERR "failed to register mpll clock\n");
27883 -
27884 -       if (s3c24xx_register_clock(&clk_upll) < 0)
27885 -               printk(KERN_ERR "failed to register upll clock\n");
27886 -
27887 -       if (s3c24xx_register_clock(&clk_f) < 0)
27888 -               printk(KERN_ERR "failed to register cpu fclk\n");
27889 -
27890 -       if (s3c24xx_register_clock(&clk_h) < 0)
27891 -               printk(KERN_ERR "failed to register cpu hclk\n");
27892 -
27893 -       if (s3c24xx_register_clock(&clk_p) < 0)
27894 -               printk(KERN_ERR "failed to register cpu pclk\n");
27895 -
27896 -       return 0;
27897  }
27898 Index: linux-2.6.28/arch/arm/plat-s3c24xx/clock-dclk.c
27899 ===================================================================
27900 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
27901 +++ linux-2.6.28/arch/arm/plat-s3c24xx/clock-dclk.c     2009-01-02 00:01:56.000000000 +0100
27902 @@ -0,0 +1,194 @@
27903 +/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
27904 + *
27905 + * Copyright (c) 2004,2008 Simtec Electronics
27906 + *     Ben Dooks <ben@simtec.co.uk>
27907 + *     http://armlinux.simtec.co.uk/
27908 + *
27909 + * This program is free software; you can redistribute it and/or modify
27910 + * it under the terms of the GNU General Public License version 2 as
27911 + * published by the Free Software Foundation.
27912 + *
27913 + * S3C24XX - definitions for DCLK and CLKOUT registers
27914 + */
27915 +
27916 +#include <linux/kernel.h>
27917 +#include <linux/errno.h>
27918 +#include <linux/clk.h>
27919 +#include <linux/io.h>
27920 +
27921 +#include <mach/regs-clock.h>
27922 +#include <mach/regs-gpio.h>
27923 +
27924 +#include <plat/clock.h>
27925 +#include <plat/cpu.h>
27926 +
27927 +/* clocks that could be registered by external code */
27928 +
27929 +static int s3c24xx_dclk_enable(struct clk *clk, int enable)
27930 +{
27931 +       unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
27932 +
27933 +       if (enable)
27934 +               dclkcon |= clk->ctrlbit;
27935 +       else
27936 +               dclkcon &= ~clk->ctrlbit;
27937 +
27938 +       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27939 +
27940 +       return 0;
27941 +}
27942 +
27943 +static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
27944 +{
27945 +       unsigned long dclkcon;
27946 +       unsigned int uclk;
27947 +
27948 +       if (parent == &clk_upll)
27949 +               uclk = 1;
27950 +       else if (parent == &clk_p)
27951 +               uclk = 0;
27952 +       else
27953 +               return -EINVAL;
27954 +
27955 +       clk->parent = parent;
27956 +
27957 +       dclkcon = __raw_readl(S3C24XX_DCLKCON);
27958 +
27959 +       if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
27960 +               if (uclk)
27961 +                       dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
27962 +               else
27963 +                       dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
27964 +       } else {
27965 +               if (uclk)
27966 +                       dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
27967 +               else
27968 +                       dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
27969 +       }
27970 +
27971 +       __raw_writel(dclkcon, S3C24XX_DCLKCON);
27972 +
27973 +       return 0;
27974 +}
27975 +static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
27976 +{
27977 +       unsigned long div;
27978 +
27979 +       if ((rate == 0) || !clk->parent)
27980 +               return 0;
27981 +
27982 +       div = clk_get_rate(clk->parent) / rate;
27983 +       if (div < 2)
27984 +               div = 2;
27985 +       else if (div > 16)
27986 +               div = 16;
27987 +
27988 +       return div;
27989 +}
27990 +
27991 +static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
27992 +       unsigned long rate)
27993 +{
27994 +       unsigned long div = s3c24xx_calc_div(clk, rate);
27995 +
27996 +       if (div == 0)
27997 +               return 0;
27998 +
27999 +       return clk_get_rate(clk->parent) / div;
28000 +}
28001 +
28002 +static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
28003 +{
28004 +       unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
28005 +
28006 +       if (div == 0)
28007 +               return -EINVAL;
28008 +
28009 +       if (clk == &s3c24xx_dclk0) {
28010 +               mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
28011 +                       S3C2410_DCLKCON_DCLK0_CMP_MASK;
28012 +               data = S3C2410_DCLKCON_DCLK0_DIV(div) |
28013 +                       S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
28014 +       } else if (clk == &s3c24xx_dclk1) {
28015 +               mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
28016 +                       S3C2410_DCLKCON_DCLK1_CMP_MASK;
28017 +               data = S3C2410_DCLKCON_DCLK1_DIV(div) |
28018 +                       S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
28019 +       } else
28020 +               return -EINVAL;
28021 +
28022 +       clk->rate = clk_get_rate(clk->parent) / div;
28023 +       __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
28024 +               S3C24XX_DCLKCON);
28025 +       return clk->rate;
28026 +}
28027 +static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
28028 +{
28029 +       unsigned long mask;
28030 +       unsigned long source;
28031 +
28032 +       /* calculate the MISCCR setting for the clock */
28033 +
28034 +       if (parent == &clk_xtal)
28035 +               source = S3C2410_MISCCR_CLK0_MPLL;
28036 +       else if (parent == &clk_upll)
28037 +               source = S3C2410_MISCCR_CLK0_UPLL;
28038 +       else if (parent == &clk_f)
28039 +               source = S3C2410_MISCCR_CLK0_FCLK;
28040 +       else if (parent == &clk_h)
28041 +               source = S3C2410_MISCCR_CLK0_HCLK;
28042 +       else if (parent == &clk_p)
28043 +               source = S3C2410_MISCCR_CLK0_PCLK;
28044 +       else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
28045 +               source = S3C2410_MISCCR_CLK0_DCLK0;
28046 +       else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
28047 +               source = S3C2410_MISCCR_CLK0_DCLK0;
28048 +       else
28049 +               return -EINVAL;
28050 +
28051 +       clk->parent = parent;
28052 +
28053 +       if (clk == &s3c24xx_clkout0)
28054 +               mask = S3C2410_MISCCR_CLK0_MASK;
28055 +       else {
28056 +               source <<= 4;
28057 +               mask = S3C2410_MISCCR_CLK1_MASK;
28058 +       }
28059 +
28060 +       s3c2410_modify_misccr(mask, source);
28061 +       return 0;
28062 +}
28063 +
28064 +/* external clock definitions */
28065 +
28066 +struct clk s3c24xx_dclk0 = {
28067 +       .name           = "dclk0",
28068 +       .id             = -1,
28069 +       .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
28070 +       .enable         = s3c24xx_dclk_enable,
28071 +       .set_parent     = s3c24xx_dclk_setparent,
28072 +       .set_rate       = s3c24xx_set_dclk_rate,
28073 +       .round_rate     = s3c24xx_round_dclk_rate,
28074 +};
28075 +
28076 +struct clk s3c24xx_dclk1 = {
28077 +       .name           = "dclk1",
28078 +       .id             = -1,
28079 +       .ctrlbit        = S3C2410_DCLKCON_DCLK1EN,
28080 +       .enable         = s3c24xx_dclk_enable,
28081 +       .set_parent     = s3c24xx_dclk_setparent,
28082 +       .set_rate       = s3c24xx_set_dclk_rate,
28083 +       .round_rate     = s3c24xx_round_dclk_rate,
28084 +};
28085 +
28086 +struct clk s3c24xx_clkout0 = {
28087 +       .name           = "clkout0",
28088 +       .id             = -1,
28089 +       .set_parent     = s3c24xx_clkout_setparent,
28090 +};
28091 +
28092 +struct clk s3c24xx_clkout1 = {
28093 +       .name           = "clkout1",
28094 +       .id             = -1,
28095 +       .set_parent     = s3c24xx_clkout_setparent,
28096 +};
28097 Index: linux-2.6.28/arch/arm/plat-s3c24xx/common-smdk.c
28098 ===================================================================
28099 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/common-smdk.c       2008-12-25 00:26:37.000000000 +0100
28100 +++ linux-2.6.28/arch/arm/plat-s3c24xx/common-smdk.c    2009-01-02 00:01:56.000000000 +0100
28101 @@ -38,7 +38,7 @@
28102  #include <mach/regs-gpio.h>
28103  #include <mach/leds-gpio.h>
28104
28105 -#include <asm/plat-s3c/nand.h>
28106 +#include <plat/nand.h>
28107
28108  #include <plat/common-smdk.h>
28109  #include <plat/devs.h>
28110 @@ -201,5 +201,5 @@ void __init smdk_machine_init(void)
28111
28112         platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
28113
28114 -       s3c2410_pm_init();
28115 +       s3c_pm_init();
28116  }
28117 Index: linux-2.6.28/arch/arm/plat-s3c24xx/cpu.c
28118 ===================================================================
28119 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/cpu.c       2008-12-25 00:26:37.000000000 +0100
28120 +++ linux-2.6.28/arch/arm/plat-s3c24xx/cpu.c    2009-01-02 00:01:56.000000000 +0100
28121 @@ -55,16 +55,6 @@
28122  #include <plat/s3c2442.h>
28123  #include <plat/s3c2443.h>
28124
28125 -struct cpu_table {
28126 -       unsigned long   idcode;
28127 -       unsigned long   idmask;
28128 -       void            (*map_io)(struct map_desc *mach_desc, int size);
28129 -       void            (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
28130 -       void            (*init_clocks)(int xtal);
28131 -       int             (*init)(void);
28132 -       const char      *name;
28133 -};
28134 -
28135  /* table of supported CPUs */
28136
28137  static const char name_s3c2400[]  = "S3C2400";
28138 @@ -72,6 +62,7 @@ static const char name_s3c2410[]  = "S3C
28139  static const char name_s3c2412[]  = "S3C2412";
28140  static const char name_s3c2440[]  = "S3C2440";
28141  static const char name_s3c2442[]  = "S3C2442";
28142 +static const char name_s3c2442b[]  = "S3C2442B";
28143  static const char name_s3c2443[]  = "S3C2443";
28144  static const char name_s3c2410a[] = "S3C2410A";
28145  static const char name_s3c2440a[] = "S3C2440A";
28146 @@ -123,6 +114,15 @@ static struct cpu_table cpu_ids[] __init
28147                 .name           = name_s3c2442
28148         },
28149         {
28150 +               .idcode         = 0x32440aab,
28151 +               .idmask         = 0xffffffff,
28152 +               .map_io         = s3c244x_map_io,
28153 +               .init_clocks    = s3c244x_init_clocks,
28154 +               .init_uarts     = s3c244x_init_uarts,
28155 +               .init           = s3c2442_init,
28156 +               .name           = name_s3c2442b
28157 +       },
28158 +       {
28159                 .idcode         = 0x32412001,
28160                 .idmask         = 0xffffffff,
28161                 .map_io         = s3c2412_map_io,
28162 @@ -169,23 +169,7 @@ static struct map_desc s3c_iodesc[] __in
28163         IODESC_ENT(UART)
28164  };
28165
28166 -static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
28167 -{
28168 -       struct cpu_table *tab;
28169 -       int count;
28170 -
28171 -       tab = cpu_ids;
28172 -       for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
28173 -               if ((idcode & tab->idmask) == tab->idcode)
28174 -                       return tab;
28175 -       }
28176 -
28177 -       return NULL;
28178 -}
28179 -
28180 -/* cpu information */
28181 -
28182 -static struct cpu_table *cpu;
28183 +/* read cpu identificaiton code */
28184
28185  static unsigned long s3c24xx_read_idcode_v5(void)
28186  {
28187 @@ -231,6 +215,7 @@ void __init s3c24xx_init_io(struct map_d
28188         unsigned long idcode = 0x0;
28189
28190         /* initialise the io descriptors we need for initialisation */
28191 +       iotable_init(mach_desc, size);
28192         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
28193
28194         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
28195 @@ -239,117 +224,7 @@ void __init s3c24xx_init_io(struct map_d
28196                 idcode = s3c24xx_read_idcode_v4();
28197         }
28198
28199 -       cpu = s3c_lookup_cpu(idcode);
28200 -
28201 -       if (cpu == NULL) {
28202 -               printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
28203 -               panic("Unknown S3C24XX CPU");
28204 -       }
28205 -
28206 -       printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
28207 -
28208 -       if (cpu->map_io == NULL || cpu->init == NULL) {
28209 -               printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
28210 -               panic("Unsupported S3C24XX CPU");
28211 -       }
28212 -
28213         arm_pm_restart = s3c24xx_pm_restart;
28214
28215 -       (cpu->map_io)(mach_desc, size);
28216 -}
28217 -
28218 -/* s3c24xx_init_clocks
28219 - *
28220 - * Initialise the clock subsystem and associated information from the
28221 - * given master crystal value.
28222 - *
28223 - * xtal  = 0 -> use default PLL crystal value (normally 12MHz)
28224 - *      != 0 -> PLL crystal value in Hz
28225 -*/
28226 -
28227 -void __init s3c24xx_init_clocks(int xtal)
28228 -{
28229 -       if (xtal == 0)
28230 -               xtal = 12*1000*1000;
28231 -
28232 -       if (cpu == NULL)
28233 -               panic("s3c24xx_init_clocks: no cpu setup?\n");
28234 -
28235 -       if (cpu->init_clocks == NULL)
28236 -               panic("s3c24xx_init_clocks: cpu has no clock init\n");
28237 -       else
28238 -               (cpu->init_clocks)(xtal);
28239 +       s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
28240  }
28241 -
28242 -/* uart management */
28243 -
28244 -static int nr_uarts __initdata = 0;
28245 -
28246 -static struct s3c2410_uartcfg uart_cfgs[3];
28247 -
28248 -/* s3c24xx_init_uartdevs
28249 - *
28250 - * copy the specified platform data and configuration into our central
28251 - * set of devices, before the data is thrown away after the init process.
28252 - *
28253 - * This also fills in the array passed to the serial driver for the
28254 - * early initialisation of the console.
28255 -*/
28256 -
28257 -void __init s3c24xx_init_uartdevs(char *name,
28258 -                                 struct s3c24xx_uart_resources *res,
28259 -                                 struct s3c2410_uartcfg *cfg, int no)
28260 -{
28261 -       struct platform_device *platdev;
28262 -       struct s3c2410_uartcfg *cfgptr = uart_cfgs;
28263 -       struct s3c24xx_uart_resources *resp;
28264 -       int uart;
28265 -
28266 -       memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
28267 -
28268 -       for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
28269 -               platdev = s3c24xx_uart_src[cfgptr->hwport];
28270 -
28271 -               resp = res + cfgptr->hwport;
28272 -
28273 -               s3c24xx_uart_devs[uart] = platdev;
28274 -
28275 -               platdev->name = name;
28276 -               platdev->resource = resp->resources;
28277 -               platdev->num_resources = resp->nr_resources;
28278 -
28279 -               platdev->dev.platform_data = cfgptr;
28280 -       }
28281 -
28282 -       nr_uarts = no;
28283 -}
28284 -
28285 -void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28286 -{
28287 -       if (cpu == NULL)
28288 -               return;
28289 -
28290 -       if (cpu->init_uarts == NULL) {
28291 -               printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
28292 -       } else
28293 -               (cpu->init_uarts)(cfg, no);
28294 -}
28295 -
28296 -static int __init s3c_arch_init(void)
28297 -{
28298 -       int ret;
28299 -
28300 -       // do the correct init for cpu
28301 -
28302 -       if (cpu == NULL)
28303 -               panic("s3c_arch_init: NULL cpu\n");
28304 -
28305 -       ret = (cpu->init)();
28306 -       if (ret != 0)
28307 -               return ret;
28308 -
28309 -       ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
28310 -       return ret;
28311 -}
28312 -
28313 -arch_initcall(s3c_arch_init);
28314 Index: linux-2.6.28/arch/arm/plat-s3c24xx/devs.c
28315 ===================================================================
28316 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/devs.c      2008-12-25 00:26:37.000000000 +0100
28317 +++ linux-2.6.28/arch/arm/plat-s3c24xx/devs.c   2009-01-02 00:01:56.000000000 +0100
28318 @@ -26,14 +26,16 @@
28319  #include <asm/mach/irq.h>
28320  #include <mach/fb.h>
28321  #include <mach/hardware.h>
28322 +#include <mach/ts.h>
28323 +#include <asm/io.h>
28324  #include <asm/irq.h>
28325
28326  #include <plat/regs-serial.h>
28327 -#include <asm/plat-s3c24xx/udc.h>
28328 +#include <plat/udc.h>
28329
28330  #include <plat/devs.h>
28331  #include <plat/cpu.h>
28332 -#include <asm/plat-s3c24xx/regs-spi.h>
28333 +#include <plat/regs-spi.h>
28334
28335  /* Serial port registrations */
28336
28337 @@ -76,6 +78,19 @@ static struct resource s3c2410_uart2_res
28338         }
28339  };
28340
28341 +static struct resource s3c2410_uart3_resource[] = {
28342 +       [0] = {
28343 +               .start = S3C2443_PA_UART3,
28344 +               .end   = S3C2443_PA_UART3 + 0x3fff,
28345 +               .flags = IORESOURCE_MEM,
28346 +       },
28347 +       [1] = {
28348 +               .start = IRQ_S3CUART_RX3,
28349 +               .end   = IRQ_S3CUART_ERR3,
28350 +               .flags = IORESOURCE_IRQ,
28351 +       },
28352 +};
28353 +
28354  struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
28355         [0] = {
28356                 .resources      = s3c2410_uart0_resource,
28357 @@ -89,6 +104,10 @@ struct s3c24xx_uart_resources s3c2410_ua
28358                 .resources      = s3c2410_uart2_resource,
28359                 .nr_resources   = ARRAY_SIZE(s3c2410_uart2_resource),
28360         },
28361 +       [3] = {
28362 +               .resources      = s3c2410_uart3_resource,
28363 +               .nr_resources   = ARRAY_SIZE(s3c2410_uart3_resource),
28364 +       },
28365  };
28366
28367  /* yart devices */
28368 @@ -105,13 +124,18 @@ static struct platform_device s3c24xx_ua
28369         .id             = 2,
28370  };
28371
28372 -struct platform_device *s3c24xx_uart_src[3] = {
28373 +static struct platform_device s3c24xx_uart_device3 = {
28374 +       .id             = 3,
28375 +};
28376 +
28377 +struct platform_device *s3c24xx_uart_src[4] = {
28378         &s3c24xx_uart_device0,
28379         &s3c24xx_uart_device1,
28380         &s3c24xx_uart_device2,
28381 +       &s3c24xx_uart_device3,
28382  };
28383
28384 -struct platform_device *s3c24xx_uart_devs[3] = {
28385 +struct platform_device *s3c24xx_uart_devs[4] = {
28386  };
28387
28388  /* USB Host Controller */
28389 @@ -192,8 +216,8 @@ void __init s3c24xx_fb_set_platdata(stru
28390
28391  static struct resource s3c_nand_resource[] = {
28392         [0] = {
28393 -               .start = S3C2410_PA_NAND,
28394 -               .end   = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
28395 +               .start = S3C24XX_PA_NAND,
28396 +               .end   = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
28397                 .flags = IORESOURCE_MEM,
28398         }
28399  };
28400 @@ -207,6 +231,23 @@ struct platform_device s3c_device_nand =
28401
28402  EXPORT_SYMBOL(s3c_device_nand);
28403
28404 +/* Touchscreen */
28405 +struct platform_device s3c_device_ts = {
28406 +       .name             = "s3c2410-ts",
28407 +       .id               = -1,
28408 +};
28409 +
28410 +EXPORT_SYMBOL(s3c_device_ts);
28411 +
28412 +static struct s3c2410_ts_mach_info s3c2410ts_info;
28413 +
28414 +void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
28415 +{
28416 +       memcpy(&s3c2410ts_info,hard_s3c2410ts_info,sizeof(struct s3c2410_ts_mach_info));
28417 +       s3c_device_ts.dev.platform_data = &s3c2410ts_info;
28418 +}
28419 +EXPORT_SYMBOL(set_s3c2410ts_info);
28420 +
28421  /* USB Device (Gadget)*/
28422
28423  static struct resource s3c_usbgadget_resource[] = {
28424 @@ -271,31 +312,6 @@ struct platform_device s3c_device_wdt =
28425
28426  EXPORT_SYMBOL(s3c_device_wdt);
28427
28428 -/* I2C */
28429 -
28430 -static struct resource s3c_i2c_resource[] = {
28431 -       [0] = {
28432 -               .start = S3C24XX_PA_IIC,
28433 -               .end   = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
28434 -               .flags = IORESOURCE_MEM,
28435 -       },
28436 -       [1] = {
28437 -               .start = IRQ_IIC,
28438 -               .end   = IRQ_IIC,
28439 -               .flags = IORESOURCE_IRQ,
28440 -       }
28441 -
28442 -};
28443 -
28444 -struct platform_device s3c_device_i2c = {
28445 -       .name             = "s3c2410-i2c",
28446 -       .id               = -1,
28447 -       .num_resources    = ARRAY_SIZE(s3c_i2c_resource),
28448 -       .resource         = s3c_i2c_resource,
28449 -};
28450 -
28451 -EXPORT_SYMBOL(s3c_device_i2c);
28452 -
28453  /* IIS */
28454
28455  static struct resource s3c_iis_resource[] = {
28456 @@ -382,8 +398,8 @@ struct platform_device s3c_device_adc =
28457
28458  static struct resource s3c_sdi_resource[] = {
28459         [0] = {
28460 -               .start = S3C2410_PA_SDI,
28461 -               .end   = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
28462 +               .start = S3C24XX_PA_SDI,
28463 +               .end   = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
28464                 .flags = IORESOURCE_MEM,
28465         },
28466         [1] = {
28467 @@ -403,36 +419,6 @@ struct platform_device s3c_device_sdi =
28468
28469  EXPORT_SYMBOL(s3c_device_sdi);
28470
28471 -/* High-speed MMC/SD */
28472 -
28473 -static struct resource s3c_hsmmc_resource[] = {
28474 -       [0] = {
28475 -               .start = S3C2443_PA_HSMMC,
28476 -               .end   = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
28477 -               .flags = IORESOURCE_MEM,
28478 -       },
28479 -       [1] = {
28480 -               .start = IRQ_S3C2443_HSMMC,
28481 -               .end   = IRQ_S3C2443_HSMMC,
28482 -               .flags = IORESOURCE_IRQ,
28483 -       }
28484 -};
28485 -
28486 -static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
28487 -
28488 -struct platform_device s3c_device_hsmmc = {
28489 -       .name             = "s3c-sdhci",
28490 -       .id               = -1,
28491 -       .num_resources    = ARRAY_SIZE(s3c_hsmmc_resource),
28492 -       .resource         = s3c_hsmmc_resource,
28493 -       .dev              = {
28494 -               .dma_mask = &s3c_device_hsmmc_dmamask,
28495 -               .coherent_dma_mask = 0xffffffffUL
28496 -       }
28497 -};
28498 -
28499 -
28500 -
28501  /* SPI (0) */
28502
28503  static struct resource s3c_spi0_resource[] = {
28504 Index: linux-2.6.28/arch/arm/plat-s3c24xx/gpio.c
28505 ===================================================================
28506 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/gpio.c      2008-12-25 00:26:37.000000000 +0100
28507 +++ linux-2.6.28/arch/arm/plat-s3c24xx/gpio.c   2009-01-02 00:01:56.000000000 +0100
28508 @@ -32,6 +32,7 @@
28509  #include <asm/irq.h>
28510
28511  #include <mach/regs-gpio.h>
28512 +#include <mach/regs-gpioj.h>
28513
28514  void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
28515  {
28516 @@ -215,3 +216,423 @@ int s3c2410_gpio_irq2pin(unsigned int ir
28517  }
28518
28519  EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
28520 +
28521 +static void pretty_dump(u32 cfg, u32 state, u32 pull,
28522 +                       const char ** function_names_2,
28523 +                       const char ** function_names_3,
28524 +                       const char * prefix,
28525 +                       int count)
28526 +{
28527 +       int n;
28528 +       const char *tag_type = NULL,
28529 +                  *tag_state = NULL,
28530 +                  *tag_pulldown = NULL,
28531 +                  * level0 = "0",
28532 +                  * level1 = "1";
28533 +
28534 +       for (n = 0; n < count; n++) {
28535 +               switch ((cfg >> (2 * n)) & 3) {
28536 +               case 0:
28537 +                       tag_type = "input      ";
28538 +                       break;
28539 +               case 1:
28540 +                       tag_type = "OUTPUT     ";
28541 +                       break;
28542 +               case 2:
28543 +                       if (function_names_2) {
28544 +                               if (function_names_2[n])
28545 +                                       tag_type = function_names_2[n];
28546 +                               else
28547 +                                       tag_type = "*** ILLEGAL CFG (2) *** ";
28548 +                       } else
28549 +                               tag_type = "(function) ";
28550 +                       break;
28551 +               default:
28552 +                       if (function_names_3) {
28553 +                               if (function_names_3[n])
28554 +                                       tag_type = function_names_3[n];
28555 +                               else
28556 +                                       tag_type = "*** ILLEGAL CFG (3) *** ";
28557 +                       } else
28558 +                               tag_type = "(function) ";
28559 +                       break;
28560 +               }
28561 +               if ((state >> n) & 1)
28562 +                       tag_state = level1;
28563 +               else
28564 +                       tag_state = level0;
28565 +
28566 +               if (((pull >> n) & 1))
28567 +                       tag_pulldown = "";
28568 +               else
28569 +                       tag_pulldown = "(pulldown)";
28570 +
28571 +               printk(KERN_INFO"%s%02d: %s %s %s\n", prefix, n, tag_type,
28572 +                                                     tag_state, tag_pulldown);
28573 +       }
28574 +       printk(KERN_INFO"\n");
28575 +}
28576 +
28577 +static void pretty_dump_a(u32 cfg, u32 state,
28578 +                         const char ** function_names,
28579 +                         const char * prefix,
28580 +                         int count)
28581 +{
28582 +       int n;
28583 +       const char *tag_type = NULL,
28584 +                  *tag_state = NULL,
28585 +                  * level0 = "0",
28586 +                  * level1 = "1";
28587 +
28588 +       for (n = 0; n < count; n++) {
28589 +               switch ((cfg >> n) & 1) {
28590 +               case 0:
28591 +                       tag_type = "OUTPUT     ";
28592 +                       break;
28593 +               default:
28594 +                       if (function_names) {
28595 +                               if (function_names[n])
28596 +                                       tag_type = function_names[n];
28597 +                               else
28598 +                                       tag_type = "*** ILLEGAL CFG *** ";
28599 +                       } else
28600 +                               tag_type = "(function) ";
28601 +                       break;
28602 +               }
28603 +               if ((state >> n) & 1)
28604 +                       tag_state = level1;
28605 +               else
28606 +                       tag_state = level0;
28607 +
28608 +               printk(KERN_INFO"%s%02d: %s %s\n", prefix, n, tag_type,
28609 +                                                  tag_state);
28610 +       }
28611 +       printk(KERN_INFO"\n");
28612 +}
28613 +
28614 +static const char * funcs_a[] = {
28615 +       "ADDR0      ",
28616 +       "ADDR16     ",
28617 +       "ADDR17     ",
28618 +       "ADDR18     ",
28619 +       "ADDR19     ",
28620 +       "ADDR20     ",
28621 +       "ADDR21     ",
28622 +       "ADDR22     ",
28623 +       "ADDR23     ",
28624 +       "ADDR24     ",
28625 +       "ADDR25     ",
28626 +       "ADDR26     ",
28627 +       "nGCS[1]    ",
28628 +       "nGCS[2]    ",
28629 +       "nGCS[3]    ",
28630 +       "nGCS[4]    ",
28631 +       "nGCS[5]    ",
28632 +       "CLE        ",
28633 +       "ALE        ",
28634 +       "nFWE       ",
28635 +       "nFRE       ",
28636 +       "nRSTOUT    ",
28637 +       "nFCE       ",
28638 +       NULL,
28639 +       NULL
28640 +};
28641 +
28642 +
28643 +static const char * funcs_b2[] = {
28644 +       "TOUT0      ",
28645 +       "TOUT1      ",
28646 +       "TOUT2      ",
28647 +       "TOUT3      ",
28648 +       "TCLK[0]    ",
28649 +       "nXBACK     ",
28650 +       "nXBREQ     ",
28651 +       "nXDACK1    ",
28652 +       "nXDREQ1    ",
28653 +       "nXDACK0    ",
28654 +       "nXDREQ0    ",
28655 +};
28656 +static const char * funcs_b3[] = {
28657 +       NULL,
28658 +       NULL,
28659 +       NULL,
28660 +       NULL,
28661 +       NULL,
28662 +       NULL,
28663 +       NULL,
28664 +       NULL,
28665 +       NULL,
28666 +       NULL,
28667 +       NULL,
28668 +};
28669 +
28670 +static const char * funcs_c2[] = {
28671 +       "LEND       ",
28672 +       "VCLK       ",
28673 +       "VLINE      ",
28674 +       "VFRAME     ",
28675 +       "VM         ",
28676 +       "LCD_LPCOE  ",
28677 +       "LCD_LPCREV ",
28678 +       "LCD_LPCREVB",
28679 +       "VD[0]      ",
28680 +       "VD[1]      ",
28681 +       "VD[2]      ",
28682 +       "VD[3]      ",
28683 +       "VD[4]      ",
28684 +       "VD[5]      ",
28685 +       "VD[6]      ",
28686 +       "VD[7]      ",
28687 +};
28688 +static const char * funcs_c3[] = {
28689 +       NULL,
28690 +       NULL,
28691 +       NULL,
28692 +       NULL,
28693 +       "I2SSDI     ",
28694 +       NULL,
28695 +       NULL,
28696 +       NULL,
28697 +       NULL,
28698 +       NULL,
28699 +       NULL,
28700 +       NULL,
28701 +       NULL,
28702 +       NULL,
28703 +       NULL,
28704 +       NULL,
28705 +};
28706 +
28707 +static const char * funcs_d2[] = {
28708 +       "VD[8]      ",
28709 +       "VD[9]      ",
28710 +       "VD[10]     ",
28711 +       "VD[11]     ",
28712 +       "VD[12]     ",
28713 +       "VD[13]     ",
28714 +       "VD[14]     ",
28715 +       "VD[15]     ",
28716 +       "VD[16]     ",
28717 +       "VD[17]     ",
28718 +       "VD[18]     ",
28719 +       "VD[19]     ",
28720 +       "VD[20]     ",
28721 +       "VD[21]     ",
28722 +       "VD[22]     ",
28723 +       "VD[23]     ",
28724 +};
28725 +static const char * funcs_d3[] = {
28726 +       "nSPICS1    ",
28727 +       "SPICLK1    ",
28728 +       NULL,
28729 +       NULL,
28730 +       NULL,
28731 +       NULL,
28732 +       NULL,
28733 +       NULL,
28734 +       "SPIMISO1   ",
28735 +       "SPIMOSI1   ",
28736 +       "SPICLK1    ",
28737 +       NULL,
28738 +       NULL,
28739 +       NULL,
28740 +       "nSS1       ",
28741 +       "nSS0       ",
28742 +};
28743 +
28744 +static const char * funcs_e2[] = {
28745 +       "I2SLRCK    ",
28746 +       "I2SSCLK    ",
28747 +       "CDCLK      ",
28748 +       "I2SDI      ",
28749 +       "I2SDO      ",
28750 +       "SDCLK      ",
28751 +       "SDCMD      ",
28752 +       "SDDAT0     ",
28753 +       "SDDAT1     ",
28754 +       "SDDAT2     ",
28755 +       "SDDAT3     ",
28756 +       "SPIMISO0   ",
28757 +       "SPIMOSI0   ",
28758 +       "SPICLK0    ",
28759 +       "IICSCL     ",
28760 +       "IICSDA     ",
28761 +};
28762 +static const char * funcs_e3[] = {
28763 +       NULL,
28764 +       NULL,
28765 +       NULL,
28766 +       NULL,
28767 +       NULL,
28768 +       NULL,
28769 +       NULL,
28770 +       NULL,
28771 +       NULL,
28772 +       NULL,
28773 +       NULL,
28774 +       NULL,
28775 +       NULL,
28776 +       NULL,
28777 +       NULL,
28778 +       NULL,
28779 +};
28780 +
28781 +static const char * funcs_f2[] = {
28782 +       "EINT[0]    ",
28783 +       "EINT[1]    ",
28784 +       "EINT[2]    ",
28785 +       "EINT[3]    ",
28786 +       "EINT[4]    ",
28787 +       "EINT[5]    ",
28788 +       "EINT[6]    ",
28789 +       "EINT[7]    ",
28790 +};
28791 +static const char * funcs_f3[] = {
28792 +       NULL,
28793 +       NULL,
28794 +       NULL,
28795 +       NULL,
28796 +       NULL,
28797 +       NULL,
28798 +       NULL,
28799 +       NULL,
28800 +};
28801 +
28802 +
28803 +static const char * funcs_g2[] = {
28804 +       "EINT[8]    ",
28805 +       "EINT[9]    ",
28806 +       "EINT[10]   ",
28807 +       "EINT[11]   ",
28808 +       "EINT[12]   ",
28809 +       "EINT[13]   ",
28810 +       "EINT[14]   ",
28811 +       "EINT[15]   ",
28812 +       "EINT[16]   ",
28813 +       "EINT[17]   ",
28814 +       "EINT[18]   ",
28815 +       "EINT[19]   ",
28816 +       "EINT[20]   ",
28817 +       "EINT[21]   ",
28818 +       "EINT[22]   ",
28819 +       "EINT[23]   ",
28820 +};
28821 +static const char * funcs_g3[] = {
28822 +       NULL,
28823 +       NULL,
28824 +       "nSS0       ",
28825 +       "nSS1       ",
28826 +       "LCD_PWRDN  ",
28827 +       "SPIMISO1   ",
28828 +       "SPIMOSI1   ",
28829 +       "SPICLK1    ",
28830 +       NULL,
28831 +       "nRTS1      ",
28832 +       "nCTS1      ",
28833 +       "TCLK[1]    ",
28834 +       "nSPICS0    ",
28835 +       NULL,
28836 +       NULL,
28837 +       NULL,
28838 +};
28839 +
28840 +static const char * funcs_h2[] = {
28841 +       "nCTS0      ",
28842 +       "nRTS0      ",
28843 +       "TXD[0]     ",
28844 +       "RXD[0]     ",
28845 +       "TXD[1]     ",
28846 +       "RXD[1]     ",
28847 +       "TXD[2]     ",
28848 +       "RXD[2]     ",
28849 +       "UEXTCLK    ",
28850 +       "CLKOUT0    ",
28851 +       "CLKOUT1    ",
28852 +};
28853 +static const char * funcs_h3[] = {
28854 +       NULL,
28855 +       NULL,
28856 +       NULL,
28857 +       NULL,
28858 +       NULL,
28859 +       NULL,
28860 +       "nRTS1      ",
28861 +       "nCTS1      ",
28862 +       NULL,
28863 +       "nSPICS0    ",
28864 +       NULL,
28865 +};
28866 +
28867 +static const char * funcs_j2[] = {
28868 +       "CAMDATA[0] ",
28869 +       "CAMDATA[1] ",
28870 +       "CAMDATA[2] ",
28871 +       "CAMDATA[3] ",
28872 +       "CAMDATA[4] ",
28873 +       "CAMDATA[5] ",
28874 +       "CAMDATA[6] ",
28875 +       "CAMDATA[7] ",
28876 +       "CAMPCLK    ",
28877 +       "CAMVSYNC   ",
28878 +       "CAMHREF    ",
28879 +       "CAMCLKOUT  ",
28880 +       "CAMRESET   ",
28881 +};
28882 +static const char * funcs_j3[] = {
28883 +       NULL,
28884 +       NULL,
28885 +       NULL,
28886 +       NULL,
28887 +       NULL,
28888 +       NULL,
28889 +       NULL,
28890 +       NULL,
28891 +       NULL,
28892 +       NULL,
28893 +       NULL,
28894 +       NULL,
28895 +       NULL,
28896 +};
28897 +
28898 +/* used to dump GPIO states at suspend */
28899 +void s3c24xx_dump_gpio_states(void)
28900 +{
28901 +       pretty_dump_a(__raw_readl(S3C2410_GPACON),
28902 +                     __raw_readl(S3C2410_GPADAT),
28903 +                     funcs_a, "GPA", 25);
28904 +       pretty_dump(__raw_readl(S3C2410_GPBCON),
28905 +                   __raw_readl(S3C2410_GPBDAT),
28906 +                   __raw_readl(S3C2410_GPBUP),
28907 +                   funcs_b2, funcs_b3, "GPB", 11);
28908 +       pretty_dump(__raw_readl(S3C2410_GPCCON),
28909 +                   __raw_readl(S3C2410_GPCDAT),
28910 +                   __raw_readl(S3C2410_GPCUP),
28911 +                   funcs_c2, funcs_c3, "GPC", 16);
28912 +       pretty_dump(__raw_readl(S3C2410_GPDCON),
28913 +                   __raw_readl(S3C2410_GPDDAT),
28914 +                   __raw_readl(S3C2410_GPDUP),
28915 +                   funcs_d2, funcs_d3, "GPD", 16);
28916 +       pretty_dump(__raw_readl(S3C2410_GPECON),
28917 +                   __raw_readl(S3C2410_GPEDAT),
28918 +                   __raw_readl(S3C2410_GPEUP),
28919 +                   funcs_e2, funcs_e3, "GPE", 16);
28920 +       pretty_dump(__raw_readl(S3C2410_GPFCON),
28921 +                   __raw_readl(S3C2410_GPFDAT),
28922 +                   __raw_readl(S3C2410_GPFUP),
28923 +                   funcs_f2, funcs_f3, "GPF", 8);
28924 +       pretty_dump(__raw_readl(S3C2410_GPGCON),
28925 +                   __raw_readl(S3C2410_GPGDAT),
28926 +                   __raw_readl(S3C2410_GPGUP),
28927 +                   funcs_g2, funcs_g3, "GPG", 16);
28928 +       pretty_dump(__raw_readl(S3C2410_GPHCON),
28929 +                   __raw_readl(S3C2410_GPHDAT),
28930 +                   __raw_readl(S3C2410_GPHUP),
28931 +                   funcs_h2, funcs_h3, "GPH", 11);
28932 +       pretty_dump(__raw_readl(S3C2440_GPJCON),
28933 +                   __raw_readl(S3C2440_GPJDAT),
28934 +                   __raw_readl(S3C2440_GPJUP),
28935 +                   funcs_j2, funcs_j3, "GPJ", 13);
28936 +
28937 +}
28938 +EXPORT_SYMBOL(s3c24xx_dump_gpio_states);
28939 +
28940 Index: linux-2.6.28/arch/arm/plat-s3c24xx/gpiolib.c
28941 ===================================================================
28942 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/gpiolib.c   2008-12-25 00:26:37.000000000 +0100
28943 +++ linux-2.6.28/arch/arm/plat-s3c24xx/gpiolib.c        2009-01-02 00:01:56.000000000 +0100
28944 @@ -19,104 +19,13 @@
28945  #include <linux/io.h>
28946  #include <linux/gpio.h>
28947
28948 +#include <plat/gpio-core.h>
28949  #include <mach/hardware.h>
28950  #include <asm/irq.h>
28951 +#include <plat/pm.h>
28952
28953  #include <mach/regs-gpio.h>
28954
28955 -struct s3c24xx_gpio_chip {
28956 -       struct gpio_chip        chip;
28957 -       void __iomem            *base;
28958 -};
28959 -
28960 -static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
28961 -{
28962 -       return container_of(gpc, struct s3c24xx_gpio_chip, chip);
28963 -}
28964 -
28965 -/* these routines are exported for use by other parts of the platform
28966 - * and system support, but are not intended to be used directly by the
28967 - * drivers themsevles.
28968 - */
28969 -
28970 -static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
28971 -{
28972 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
28973 -       void __iomem *base = ourchip->base;
28974 -       unsigned long flags;
28975 -       unsigned long con;
28976 -
28977 -       local_irq_save(flags);
28978 -
28979 -       con = __raw_readl(base + 0x00);
28980 -       con &= ~(3 << (offset * 2));
28981 -       con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
28982 -
28983 -       __raw_writel(con, base + 0x00);
28984 -
28985 -       local_irq_restore(flags);
28986 -       return 0;
28987 -}
28988 -
28989 -static int s3c24xx_gpiolib_output(struct gpio_chip *chip,
28990 -                                 unsigned offset, int value)
28991 -{
28992 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
28993 -       void __iomem *base = ourchip->base;
28994 -       unsigned long flags;
28995 -       unsigned long dat;
28996 -       unsigned long con;
28997 -
28998 -       local_irq_save(flags);
28999 -
29000 -       dat = __raw_readl(base + 0x04);
29001 -       dat &= ~(1 << offset);
29002 -       if (value)
29003 -               dat |= 1 << offset;
29004 -       __raw_writel(dat, base + 0x04);
29005 -
29006 -       con = __raw_readl(base + 0x00);
29007 -       con &= ~(3 << (offset * 2));
29008 -       con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
29009 -
29010 -       __raw_writel(con, base + 0x00);
29011 -       __raw_writel(dat, base + 0x04);
29012 -
29013 -       local_irq_restore(flags);
29014 -       return 0;
29015 -}
29016 -
29017 -static void s3c24xx_gpiolib_set(struct gpio_chip *chip,
29018 -                               unsigned offset, int value)
29019 -{
29020 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
29021 -       void __iomem *base = ourchip->base;
29022 -       unsigned long flags;
29023 -       unsigned long dat;
29024 -
29025 -       local_irq_save(flags);
29026 -
29027 -       dat = __raw_readl(base + 0x04);
29028 -       dat &= ~(1 << offset);
29029 -       if (value)
29030 -               dat |= 1 << offset;
29031 -       __raw_writel(dat, base + 0x04);
29032 -
29033 -       local_irq_restore(flags);
29034 -}
29035 -
29036 -static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
29037 -{
29038 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
29039 -       unsigned long val;
29040 -
29041 -       val = __raw_readl(ourchip->base + 0x04);
29042 -       val >>= offset;
29043 -       val &= 1;
29044 -
29045 -       return val;
29046 -}
29047 -
29048  static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
29049  {
29050         return -EINVAL;
29051 @@ -125,7 +34,7 @@ static int s3c24xx_gpiolib_banka_input(s
29052  static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
29053                                         unsigned offset, int value)
29054  {
29055 -       struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
29056 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
29057         void __iomem *base = ourchip->base;
29058         unsigned long flags;
29059         unsigned long dat;
29060 @@ -151,9 +60,10 @@ static int s3c24xx_gpiolib_banka_output(
29061         return 0;
29062  }
29063
29064 -static struct s3c24xx_gpio_chip gpios[] = {
29065 +struct s3c_gpio_chip s3c24xx_gpios[] = {
29066         [0] = {
29067                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPA0),
29068 +               .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
29069                 .chip   = {
29070                         .base                   = S3C2410_GPA0,
29071                         .owner                  = THIS_MODULE,
29072 @@ -161,97 +71,87 @@ static struct s3c24xx_gpio_chip gpios[]
29073                         .ngpio                  = 24,
29074                         .direction_input        = s3c24xx_gpiolib_banka_input,
29075                         .direction_output       = s3c24xx_gpiolib_banka_output,
29076 -                       .set                    = s3c24xx_gpiolib_set,
29077 -                       .get                    = s3c24xx_gpiolib_get,
29078                 },
29079         },
29080         [1] = {
29081                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPB0),
29082 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
29083                 .chip   = {
29084                         .base                   = S3C2410_GPB0,
29085                         .owner                  = THIS_MODULE,
29086                         .label                  = "GPIOB",
29087                         .ngpio                  = 16,
29088 -                       .direction_input        = s3c24xx_gpiolib_input,
29089 -                       .direction_output       = s3c24xx_gpiolib_output,
29090 -                       .set                    = s3c24xx_gpiolib_set,
29091 -                       .get                    = s3c24xx_gpiolib_get,
29092                 },
29093         },
29094         [2] = {
29095                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPC0),
29096 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
29097                 .chip   = {
29098                         .base                   = S3C2410_GPC0,
29099                         .owner                  = THIS_MODULE,
29100                         .label                  = "GPIOC",
29101                         .ngpio                  = 16,
29102 -                       .direction_input        = s3c24xx_gpiolib_input,
29103 -                       .direction_output       = s3c24xx_gpiolib_output,
29104 -                       .set                    = s3c24xx_gpiolib_set,
29105 -                       .get                    = s3c24xx_gpiolib_get,
29106                 },
29107         },
29108         [3] = {
29109                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPD0),
29110 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
29111                 .chip   = {
29112                         .base                   = S3C2410_GPD0,
29113                         .owner                  = THIS_MODULE,
29114                         .label                  = "GPIOD",
29115                         .ngpio                  = 16,
29116 -                       .direction_input        = s3c24xx_gpiolib_input,
29117 -                       .direction_output       = s3c24xx_gpiolib_output,
29118 -                       .set                    = s3c24xx_gpiolib_set,
29119 -                       .get                    = s3c24xx_gpiolib_get,
29120                 },
29121         },
29122         [4] = {
29123                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPE0),
29124 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
29125                 .chip   = {
29126                         .base                   = S3C2410_GPE0,
29127                         .label                  = "GPIOE",
29128                         .owner                  = THIS_MODULE,
29129                         .ngpio                  = 16,
29130 -                       .direction_input        = s3c24xx_gpiolib_input,
29131 -                       .direction_output       = s3c24xx_gpiolib_output,
29132 -                       .set                    = s3c24xx_gpiolib_set,
29133 -                       .get                    = s3c24xx_gpiolib_get,
29134                 },
29135         },
29136         [5] = {
29137                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPF0),
29138 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
29139                 .chip   = {
29140                         .base                   = S3C2410_GPF0,
29141                         .owner                  = THIS_MODULE,
29142                         .label                  = "GPIOF",
29143                         .ngpio                  = 8,
29144 -                       .direction_input        = s3c24xx_gpiolib_input,
29145 -                       .direction_output       = s3c24xx_gpiolib_output,
29146 -                       .set                    = s3c24xx_gpiolib_set,
29147 -                       .get                    = s3c24xx_gpiolib_get,
29148                 },
29149         },
29150         [6] = {
29151                 .base   = S3C24XX_GPIO_BASE(S3C2410_GPG0),
29152 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
29153                 .chip   = {
29154                         .base                   = S3C2410_GPG0,
29155                         .owner                  = THIS_MODULE,
29156                         .label                  = "GPIOG",
29157 -                       .ngpio                  = 10,
29158 -                       .direction_input        = s3c24xx_gpiolib_input,
29159 -                       .direction_output       = s3c24xx_gpiolib_output,
29160 -                       .set                    = s3c24xx_gpiolib_set,
29161 -                       .get                    = s3c24xx_gpiolib_get,
29162 +                       .ngpio                  = 16,
29163 +               },
29164 +       },
29165 +       [7] = {
29166 +               .base   = S3C24XX_GPIO_BASE(S3C2410_GPH0),
29167 +               .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
29168 +               .chip   = {
29169 +                       .base                   = S3C2410_GPH0,
29170 +                       .owner                  = THIS_MODULE,
29171 +                       .label                  = "GPIOH",
29172 +                       .ngpio                  = 11,
29173                 },
29174         },
29175  };
29176
29177  static __init int s3c24xx_gpiolib_init(void)
29178  {
29179 -       struct s3c24xx_gpio_chip *chip = gpios;
29180 +       struct s3c_gpio_chip *chip = s3c24xx_gpios;
29181         int gpn;
29182
29183 -       for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
29184 -               gpiochip_add(&chip->chip);
29185 +       for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
29186 +               s3c_gpiolib_add(chip);
29187
29188         return 0;
29189  }
29190 Index: linux-2.6.28/arch/arm/plat-s3c24xx/gta02_pm_wlan.c
29191 ===================================================================
29192 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
29193 +++ linux-2.6.28/arch/arm/plat-s3c24xx/gta02_pm_wlan.c  2009-01-02 00:01:56.000000000 +0100
29194 @@ -0,0 +1,161 @@
29195 +/*
29196 + * GTA02 WLAN power management
29197 + *
29198 + * (C) 2008 by Openmoko Inc.
29199 + * Author: Andy Green <andy@openmoko.com>
29200 + * All rights reserved.
29201 + *
29202 + * This program is free software; you can redistribute it and/or modify
29203 + * it under the terms of the GNU General Public License version 2 as
29204 + * published by the Free Software Foundation
29205 + *
29206 + */
29207 +
29208 +#include <linux/module.h>
29209 +#include <linux/init.h>
29210 +#include <linux/kernel.h>
29211 +#include <linux/mutex.h>
29212 +#include <linux/platform_device.h>
29213 +
29214 +#include <mach/hardware.h>
29215 +#include <asm/mach-types.h>
29216 +#include <asm/plat-s3c24xx/neo1973.h>
29217 +
29218 +#include <mach/gta02.h>
29219 +#include <mach/gta02-pm-wlan.h>
29220 +#include <mach/regs-gpio.h>
29221 +#include <mach/regs-gpioj.h>
29222 +
29223 +#include <linux/delay.h>
29224 +
29225 +
29226 +static void __gta02_wlan_power(int on)
29227 +{
29228 +       if (!on) {
29229 +               s3c2410_gpio_setpin(GTA02_CHIP_PWD, 1);
29230 +               s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 0);
29231 +               return;
29232 +       }
29233 +
29234 +       /* power up sequencing */
29235 +
29236 +       s3c2410_gpio_setpin(GTA02_CHIP_PWD, 1);
29237 +       s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 0);
29238 +       msleep(100);
29239 +       s3c2410_gpio_setpin(GTA02_CHIP_PWD, 0);
29240 +       msleep(100);
29241 +       s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 1);
29242 +}
29243 +
29244 +void gta02_wlan_power(int on)
29245 +{
29246 +       static DEFINE_MUTEX(lock);
29247 +       static int is_on = -1; /* initial state is unknown */
29248 +
29249 +       on = !!on; /* normalize */
29250 +       mutex_lock(&lock);
29251 +       if (on != is_on)
29252 +               __gta02_wlan_power(on);
29253 +       is_on = on;
29254 +       mutex_unlock(&lock);
29255 +}
29256 +
29257 +static ssize_t gta02_wlan_read(struct device *dev,
29258 +                                      struct device_attribute *attr, char *buf)
29259 +{
29260 +       if (s3c2410_gpio_getpin(GTA02_CHIP_PWD))
29261 +               return strlcpy(buf, "0\n", 3);
29262 +
29263 +       return strlcpy(buf, "1\n", 3);
29264 +}
29265 +
29266 +static ssize_t gta02_wlan_write(struct device *dev,
29267 +                  struct device_attribute *attr, const char *buf, size_t count)
29268 +{
29269 +       unsigned long on = simple_strtoul(buf, NULL, 10) & 1;
29270 +
29271 +       gta02_wlan_power(on);
29272 +       return count;
29273 +}
29274 +
29275 +static DEVICE_ATTR(power_on, 0644, gta02_wlan_read, gta02_wlan_write);
29276 +
29277 +#ifdef CONFIG_PM
29278 +static int gta02_wlan_suspend(struct platform_device *pdev, pm_message_t state)
29279 +{
29280 +       dev_dbg(&pdev->dev, "suspending\n");
29281 +
29282 +       return 0;
29283 +}
29284 +
29285 +static int gta02_wlan_resume(struct platform_device *pdev)
29286 +{
29287 +       dev_dbg(&pdev->dev, "resuming\n");
29288 +
29289 +       return 0;
29290 +}
29291 +#else
29292 +#define gta02_wlan_suspend     NULL
29293 +#define gta02_wlan_resume              NULL
29294 +#endif
29295 +
29296 +static struct attribute *gta02_wlan_sysfs_entries[] = {
29297 +       &dev_attr_power_on.attr,
29298 +       NULL
29299 +};
29300 +
29301 +static struct attribute_group gta02_wlan_attr_group = {
29302 +       .name   = NULL,
29303 +       .attrs  = gta02_wlan_sysfs_entries,
29304 +};
29305 +
29306 +static int __init gta02_wlan_probe(struct platform_device *pdev)
29307 +{
29308 +       /* default-on for now */
29309 +       const int default_state = 1;
29310 +
29311 +       if (!machine_is_neo1973_gta02())
29312 +               return -EINVAL;
29313 +
29314 +       dev_info(&pdev->dev, "starting\n");
29315 +
29316 +       s3c2410_gpio_cfgpin(GTA02_CHIP_PWD, S3C2410_GPIO_OUTPUT);
29317 +       s3c2410_gpio_cfgpin(GTA02_GPIO_nWLAN_RESET, S3C2410_GPIO_OUTPUT);
29318 +       gta02_wlan_power(default_state);
29319 +
29320 +       return sysfs_create_group(&pdev->dev.kobj, &gta02_wlan_attr_group);
29321 +}
29322 +
29323 +static int gta02_wlan_remove(struct platform_device *pdev)
29324 +{
29325 +       sysfs_remove_group(&pdev->dev.kobj, &gta02_wlan_attr_group);
29326 +
29327 +       return 0;
29328 +}
29329 +
29330 +static struct platform_driver gta02_wlan_driver = {
29331 +       .probe          = gta02_wlan_probe,
29332 +       .remove         = gta02_wlan_remove,
29333 +       .suspend        = gta02_wlan_suspend,
29334 +       .resume         = gta02_wlan_resume,
29335 +       .driver         = {
29336 +               .name           = "gta02-pm-wlan",
29337 +       },
29338 +};
29339 +
29340 +static int __devinit gta02_wlan_init(void)
29341 +{
29342 +       return platform_driver_register(&gta02_wlan_driver);
29343 +}
29344 +
29345 +static void gta02_wlan_exit(void)
29346 +{
29347 +       platform_driver_unregister(&gta02_wlan_driver);
29348 +}
29349 +
29350 +module_init(gta02_wlan_init);
29351 +module_exit(gta02_wlan_exit);
29352 +
29353 +MODULE_LICENSE("GPL");
29354 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
29355 +MODULE_DESCRIPTION("Openmoko GTA02 WLAN power management");
29356 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
29357 ===================================================================
29358 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
29359 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h 2009-01-02 00:01:56.000000000 +0100
29360 @@ -0,0 +1,55 @@
29361 +/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
29362 + *
29363 + * Copyright 2008 Simtec Electronics
29364 + *      Ben Dooks <ben@simtec.co.uk>
29365 + *      http://armlinux.simtec.co.uk/
29366 + *
29367 + * S3C24xx - pwm clock and timer support
29368 + */
29369 +
29370 +/**
29371 + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
29372 + * @cfg: The timer TCFG1 register bits shifted down to 0.
29373 + *
29374 + * Return true if the given configuration from TCFG1 is a TCLK instead
29375 + * any of the TDIV clocks.
29376 + */
29377 +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
29378 +{
29379 +       return tcfg == S3C2410_TCFG1_MUX_TCLK;
29380 +}
29381 +
29382 +/**
29383 + * tcfg_to_divisor() - convert tcfg1 setting to a divisor
29384 + * @tcfg1: The tcfg1 setting, shifted down.
29385 + *
29386 + * Get the divisor value for the given tcfg1 setting. We assume the
29387 + * caller has already checked to see if this is not a TCLK source.
29388 + */
29389 +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
29390 +{
29391 +       return 1 << (1 + tcfg1);
29392 +}
29393 +
29394 +/**
29395 + * pwm_tdiv_has_div1() - does the tdiv setting have a /1
29396 + *
29397 + * Return true if we have a /1 in the tdiv setting.
29398 + */
29399 +static inline unsigned int pwm_tdiv_has_div1(void)
29400 +{
29401 +       return 0;
29402 +}
29403 +
29404 +/**
29405 + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
29406 + * @div: The divisor to calculate the bit information for.
29407 + *
29408 + * Turn a divisor into the necessary bit field for TCFG1.
29409 + */
29410 +static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
29411 +{
29412 +       return ilog2(div) - 1;
29413 +}
29414 +
29415 +#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
29416 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/clock.h
29417 ===================================================================
29418 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/clock.h        2008-12-25 00:26:37.000000000 +0100
29419 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
29420 @@ -1,64 +0,0 @@
29421 -/* linux/include/asm-arm/plat-s3c24xx/clock.h
29422 - * linux/arch/arm/mach-s3c2410/clock.h
29423 - *
29424 - * Copyright (c) 2004-2005 Simtec Electronics
29425 - *     http://www.simtec.co.uk/products/SWLINUX/
29426 - *     Written by Ben Dooks, <ben@simtec.co.uk>
29427 - *
29428 - * This program is free software; you can redistribute it and/or modify
29429 - * it under the terms of the GNU General Public License version 2 as
29430 - * published by the Free Software Foundation.
29431 -*/
29432 -
29433 -struct clk {
29434 -       struct list_head      list;
29435 -       struct module        *owner;
29436 -       struct clk           *parent;
29437 -       const char           *name;
29438 -       int                   id;
29439 -       int                   usage;
29440 -       unsigned long         rate;
29441 -       unsigned long         ctrlbit;
29442 -
29443 -       int                 (*enable)(struct clk *, int enable);
29444 -       int                 (*set_rate)(struct clk *c, unsigned long rate);
29445 -       unsigned long       (*get_rate)(struct clk *c);
29446 -       unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
29447 -       int                 (*set_parent)(struct clk *c, struct clk *parent);
29448 -};
29449 -
29450 -/* other clocks which may be registered by board support */
29451 -
29452 -extern struct clk s3c24xx_dclk0;
29453 -extern struct clk s3c24xx_dclk1;
29454 -extern struct clk s3c24xx_clkout0;
29455 -extern struct clk s3c24xx_clkout1;
29456 -extern struct clk s3c24xx_uclk;
29457 -
29458 -extern struct clk clk_usb_bus;
29459 -
29460 -/* core clock support */
29461 -
29462 -extern struct clk clk_f;
29463 -extern struct clk clk_h;
29464 -extern struct clk clk_p;
29465 -extern struct clk clk_mpll;
29466 -extern struct clk clk_upll;
29467 -extern struct clk clk_xtal;
29468 -
29469 -/* exports for arch/arm/mach-s3c2410
29470 - *
29471 - * Please DO NOT use these outside of arch/arm/mach-s3c2410
29472 -*/
29473 -
29474 -extern struct mutex clocks_mutex;
29475 -
29476 -extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
29477 -
29478 -extern int s3c24xx_register_clock(struct clk *clk);
29479 -extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
29480 -
29481 -extern int s3c24xx_setup_clocks(unsigned long xtal,
29482 -                               unsigned long fclk,
29483 -                               unsigned long hclk,
29484 -                               unsigned long pclk);
29485 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/cpu.h
29486 ===================================================================
29487 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/cpu.h  2008-12-25 00:26:37.000000000 +0100
29488 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
29489 @@ -1,54 +0,0 @@
29490 -/* linux/include/asm-arm/plat-s3c24xx/cpu.h
29491 - *
29492 - * Copyright (c) 2004-2005 Simtec Electronics
29493 - *     Ben Dooks <ben@simtec.co.uk>
29494 - *
29495 - * Header file for S3C24XX CPU support
29496 - *
29497 - * This program is free software; you can redistribute it and/or modify
29498 - * it under the terms of the GNU General Public License version 2 as
29499 - * published by the Free Software Foundation.
29500 -*/
29501 -
29502 -/* todo - fix when rmk changes iodescs to use `void __iomem *` */
29503 -
29504 -#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
29505 -
29506 -#ifndef MHZ
29507 -#define MHZ (1000*1000)
29508 -#endif
29509 -
29510 -#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
29511 -
29512 -/* forward declaration */
29513 -struct s3c24xx_uart_resources;
29514 -struct platform_device;
29515 -struct s3c2410_uartcfg;
29516 -struct map_desc;
29517 -
29518 -/* core initialisation functions */
29519 -
29520 -extern void s3c24xx_init_irq(void);
29521 -
29522 -extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
29523 -
29524 -extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29525 -
29526 -extern void s3c24xx_init_clocks(int xtal);
29527 -
29528 -extern void s3c24xx_init_uartdevs(char *name,
29529 -                                 struct s3c24xx_uart_resources *res,
29530 -                                 struct s3c2410_uartcfg *cfg, int no);
29531 -
29532 -/* timer for 2410/2440 */
29533 -
29534 -struct sys_timer;
29535 -extern struct sys_timer s3c24xx_timer;
29536 -
29537 -/* system device classes */
29538 -
29539 -extern struct sysdev_class s3c2410_sysclass;
29540 -extern struct sysdev_class s3c2412_sysclass;
29541 -extern struct sysdev_class s3c2440_sysclass;
29542 -extern struct sysdev_class s3c2442_sysclass;
29543 -extern struct sysdev_class s3c2443_sysclass;
29544 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/devs.h
29545 ===================================================================
29546 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/devs.h 2008-12-25 00:26:37.000000000 +0100
29547 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
29548 @@ -1,49 +0,0 @@
29549 -/* linux/include/asm-arm/plat-s3c24xx/devs.h
29550 - *
29551 - * Copyright (c) 2004 Simtec Electronics
29552 - * Ben Dooks <ben@simtec.co.uk>
29553 - *
29554 - * Header file for s3c2410 standard platform devices
29555 - *
29556 - * This program is free software; you can redistribute it and/or modify
29557 - * it under the terms of the GNU General Public License version 2 as
29558 - * published by the Free Software Foundation.
29559 -*/
29560 -#include <linux/platform_device.h>
29561 -
29562 -struct s3c24xx_uart_resources {
29563 -       struct resource         *resources;
29564 -       unsigned long            nr_resources;
29565 -};
29566 -
29567 -extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
29568 -
29569 -extern struct platform_device *s3c24xx_uart_devs[];
29570 -extern struct platform_device *s3c24xx_uart_src[];
29571 -
29572 -extern struct platform_device s3c_device_timer[];
29573 -
29574 -extern struct platform_device s3c_device_usb;
29575 -extern struct platform_device s3c_device_lcd;
29576 -extern struct platform_device s3c_device_wdt;
29577 -extern struct platform_device s3c_device_i2c;
29578 -extern struct platform_device s3c_device_iis;
29579 -extern struct platform_device s3c_device_rtc;
29580 -extern struct platform_device s3c_device_adc;
29581 -extern struct platform_device s3c_device_sdi;
29582 -extern struct platform_device s3c_device_hsmmc;
29583 -
29584 -extern struct platform_device s3c_device_spi0;
29585 -extern struct platform_device s3c_device_spi1;
29586 -
29587 -extern struct platform_device s3c_device_nand;
29588 -
29589 -extern struct platform_device s3c_device_usbgadget;
29590 -
29591 -/* s3c2440 specific devices */
29592 -
29593 -#ifdef CONFIG_CPU_S3C2440
29594 -
29595 -extern struct platform_device s3c_device_camif;
29596 -
29597 -#endif
29598 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/irq.h
29599 ===================================================================
29600 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/irq.h  2008-12-25 00:26:37.000000000 +0100
29601 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/irq.h       2009-01-02 00:01:56.000000000 +0100
29602 @@ -10,6 +10,12 @@
29603   * published by the Free Software Foundation.
29604  */
29605
29606 +#include <linux/io.h>
29607 +
29608 +#include <mach/hardware.h>
29609 +#include <mach/regs-irq.h>
29610 +#include <mach/regs-gpio.h>
29611 +
29612  #define irqdbf(x...)
29613  #define irqdbf2(x...)
29614
29615 @@ -25,8 +31,15 @@ s3c_irqsub_mask(unsigned int irqno, unsi
29616  {
29617         unsigned long mask;
29618         unsigned long submask;
29619 +#ifdef CONFIG_S3C2440_C_FIQ
29620 +       unsigned long flags;
29621 +#endif
29622
29623         submask = __raw_readl(S3C2410_INTSUBMSK);
29624 +#ifdef CONFIG_S3C2440_C_FIQ
29625 +       local_save_flags(flags);
29626 +       local_fiq_disable();
29627 +#endif
29628         mask = __raw_readl(S3C2410_INTMSK);
29629
29630         submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
29631 @@ -39,6 +52,9 @@ s3c_irqsub_mask(unsigned int irqno, unsi
29632
29633         /* write back masks */
29634         __raw_writel(submask, S3C2410_INTSUBMSK);
29635 +#ifdef CONFIG_S3C2440_C_FIQ
29636 +       local_irq_restore(flags);
29637 +#endif
29638
29639  }
29640
29641 @@ -47,8 +63,15 @@ s3c_irqsub_unmask(unsigned int irqno, un
29642  {
29643         unsigned long mask;
29644         unsigned long submask;
29645 +#ifdef CONFIG_S3C2440_C_FIQ
29646 +       unsigned long flags;
29647 +#endif
29648
29649         submask = __raw_readl(S3C2410_INTSUBMSK);
29650 +#ifdef CONFIG_S3C2440_C_FIQ
29651 +       local_save_flags(flags);
29652 +       local_fiq_disable();
29653 +#endif
29654         mask = __raw_readl(S3C2410_INTMSK);
29655
29656         submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
29657 @@ -57,6 +80,9 @@ s3c_irqsub_unmask(unsigned int irqno, un
29658         /* write back masks */
29659         __raw_writel(submask, S3C2410_INTSUBMSK);
29660         __raw_writel(mask, S3C2410_INTMSK);
29661 +#ifdef CONFIG_S3C2440_C_FIQ
29662 +       local_irq_restore(flags);
29663 +#endif
29664  }
29665
29666
29667 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/map.h
29668 ===================================================================
29669 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
29670 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/map.h       2009-01-02 00:01:56.000000000 +0100
29671 @@ -0,0 +1,101 @@
29672 +/* linux/include/asm-arm/plat-s3c24xx/map.h
29673 + *
29674 + * Copyright (c) 2008 Simtec Electronics
29675 + *     Ben Dooks <ben@simtec.co.uk>
29676 + *
29677 + * S3C24XX - Memory map definitions
29678 + *
29679 + * This program is free software; you can redistribute it and/or modify
29680 + * it under the terms of the GNU General Public License version 2 as
29681 + * published by the Free Software Foundation.
29682 +*/
29683 +
29684 +#ifndef __ASM_PLAT_S3C24XX_MAP_H
29685 +#define __ASM_PLAT_S3C24XX_MAP_H
29686 +
29687 +/* interrupt controller is the first thing we put in, to make
29688 + * the assembly code for the irq detection easier
29689 + */
29690 +#define S3C24XX_VA_IRQ    S3C_VA_IRQ
29691 +#define S3C2410_PA_IRQ    (0x4A000000)
29692 +#define S3C24XX_SZ_IRQ    SZ_1M
29693 +
29694 +/* memory controller registers */
29695 +#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
29696 +#define S3C2410_PA_MEMCTRL (0x48000000)
29697 +#define S3C24XX_SZ_MEMCTRL SZ_1M
29698 +
29699 +/* UARTs */
29700 +#define S3C24XX_VA_UART           S3C_VA_UART
29701 +#define S3C2410_PA_UART           (0x50000000)
29702 +#define S3C24XX_SZ_UART           SZ_1M
29703 +#define S3C_UART_OFFSET           (0x4000)
29704 +
29705 +#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
29706 +
29707 +/* Timers */
29708 +#define S3C24XX_VA_TIMER   S3C_VA_TIMER
29709 +#define S3C2410_PA_TIMER   (0x51000000)
29710 +#define S3C24XX_SZ_TIMER   SZ_1M
29711 +
29712 +/* Clock and Power management */
29713 +#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
29714 +#define S3C24XX_SZ_CLKPWR  SZ_1M
29715 +
29716 +/* USB Device port */
29717 +#define S3C2410_PA_USBDEV  (0x52000000)
29718 +#define S3C24XX_SZ_USBDEV  SZ_1M
29719 +
29720 +/* Watchdog */
29721 +#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
29722 +#define S3C2410_PA_WATCHDOG (0x53000000)
29723 +#define S3C24XX_SZ_WATCHDOG SZ_1M
29724 +
29725 +/* Standard size definitions for peripheral blocks. */
29726 +
29727 +#define S3C24XX_SZ_IIS         SZ_1M
29728 +#define S3C24XX_SZ_ADC         SZ_1M
29729 +#define S3C24XX_SZ_SPI         SZ_1M
29730 +#define S3C24XX_SZ_SDI         SZ_1M
29731 +#define S3C24XX_SZ_NAND                SZ_1M
29732 +#define S3C24XX_SZ_USBHOST     SZ_1M
29733 +
29734 +/* GPIO ports */
29735 +
29736 +/* the calculation for the VA of this must ensure that
29737 + * it is the same distance apart from the UART in the
29738 + * phsyical address space, as the initial mapping for the IO
29739 + * is done as a 1:1 maping. This puts it (currently) at
29740 + * 0xFA800000, which is not in the way of any current mapping
29741 + * by the base system.
29742 +*/
29743 +
29744 +#define S3C2410_PA_GPIO           (0x56000000)
29745 +#define S3C24XX_VA_GPIO           ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
29746 +#define S3C24XX_SZ_GPIO           SZ_1M
29747 +
29748 +
29749 +/* ISA style IO, for each machine to sort out mappings for, if it
29750 + * implements it. We reserve two 16M regions for ISA.
29751 + */
29752 +
29753 +#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
29754 +#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
29755 +
29756 +/* deal with the registers that move under the 2412/2413 */
29757 +
29758 +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
29759 +#ifndef __ASSEMBLY__
29760 +extern void __iomem *s3c24xx_va_gpio2;
29761 +#endif
29762 +#ifdef CONFIG_CPU_S3C2412_ONLY
29763 +#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
29764 +#else
29765 +#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
29766 +#endif
29767 +#else
29768 +#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
29769 +#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
29770 +#endif
29771 +
29772 +#endif /* __ASM_PLAT_S3C24XX_MAP_H */
29773 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/mci.h
29774 ===================================================================
29775 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
29776 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/mci.h       2009-01-02 00:01:56.000000000 +0100
29777 @@ -0,0 +1,15 @@
29778 +#ifndef _ARCH_MCI_H
29779 +#define _ARCH_MCI_H
29780 +
29781 +struct s3c24xx_mci_pdata {
29782 +       unsigned int    wprotect_invert : 1;
29783 +       unsigned int    detect_invert : 1;   /* set => detect active high. */
29784 +
29785 +       unsigned int    gpio_detect;
29786 +       unsigned int    gpio_wprotect;
29787 +       unsigned long   ocr_avail;
29788 +       void            (*set_power)(unsigned char power_mode,
29789 +                                    unsigned short vdd);
29790 +};
29791 +
29792 +#endif /* _ARCH_NCI_H */
29793 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/pll.h
29794 ===================================================================
29795 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
29796 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/pll.h       2009-01-02 00:01:56.000000000 +0100
29797 @@ -0,0 +1,37 @@
29798 +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
29799 + *
29800 + * Copyright 2008 Simtec Electronics
29801 + *      Ben Dooks <ben@simtec.co.uk>
29802 + *      http://armlinux.simtec.co.uk/
29803 + *
29804 + * S3C24xx - common pll registers and code
29805 + */
29806 +
29807 +#define S3C24XX_PLLCON_MDIVSHIFT       12
29808 +#define S3C24XX_PLLCON_PDIVSHIFT       4
29809 +#define S3C24XX_PLLCON_SDIVSHIFT       0
29810 +#define S3C24XX_PLLCON_MDIVMASK                ((1<<(1+(19-12)))-1)
29811 +#define S3C24XX_PLLCON_PDIVMASK                ((1<<5)-1)
29812 +#define S3C24XX_PLLCON_SDIVMASK                3
29813 +
29814 +#include <asm/div64.h>
29815 +
29816 +static inline unsigned int
29817 +s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
29818 +{
29819 +       unsigned int mdiv, pdiv, sdiv;
29820 +       uint64_t fvco;
29821 +
29822 +       mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
29823 +       pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
29824 +       sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
29825 +
29826 +       mdiv &= S3C24XX_PLLCON_MDIVMASK;
29827 +       pdiv &= S3C24XX_PLLCON_PDIVMASK;
29828 +       sdiv &= S3C24XX_PLLCON_SDIVMASK;
29829 +
29830 +       fvco = (uint64_t)baseclk * (mdiv + 8);
29831 +       do_div(fvco, (pdiv + 2) << sdiv);
29832 +
29833 +       return (unsigned int)fvco;
29834 +}
29835 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/pm-core.h
29836 ===================================================================
29837 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
29838 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/pm-core.h   2009-01-02 00:01:56.000000000 +0100
29839 @@ -0,0 +1,64 @@
29840 +/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
29841 + *
29842 + * Copyright 2008 Simtec Electronics
29843 + *      Ben Dooks <ben@simtec.co.uk>
29844 + *      http://armlinux.simtec.co.uk/
29845 + *
29846 + * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
29847 + *
29848 + * This program is free software; you can redistribute it and/or modify
29849 + * it under the terms of the GNU General Public License version 2 as
29850 + * published by the Free Software Foundation.
29851 + */
29852 +
29853 +static inline void s3c_pm_debug_init_uart(void)
29854 +{
29855 +       unsigned long tmp = __raw_readl(S3C2410_CLKCON);
29856 +
29857 +       /* re-start uart clocks */
29858 +       tmp |= S3C2410_CLKCON_UART0;
29859 +       tmp |= S3C2410_CLKCON_UART1;
29860 +       tmp |= S3C2410_CLKCON_UART2;
29861 +
29862 +       __raw_writel(tmp, S3C2410_CLKCON);
29863 +       udelay(10);
29864 +}
29865 +
29866 +static inline void s3c_pm_arch_prepare_irqs(void)
29867 +{
29868 +       __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
29869 +       __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
29870 +
29871 +       /* ack any outstanding external interrupts before we go to sleep */
29872 +
29873 +       __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
29874 +       __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
29875 +       __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
29876 +
29877 +}
29878 +
29879 +static inline void s3c_pm_arch_stop_clocks(void)
29880 +{
29881 +       __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
29882 +}
29883 +
29884 +static void s3c_pm_show_resume_irqs(int start, unsigned long which,
29885 +                                   unsigned long mask);
29886 +
29887 +static inline void s3c_pm_arch_show_resume_irqs(void)
29888 +{
29889 +       S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
29890 +                 __raw_readl(S3C2410_SRCPND),
29891 +                 __raw_readl(S3C2410_EINTPEND));
29892 +
29893 +       s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
29894 +                               s3c_irqwake_intmask);
29895 +
29896 +       s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
29897 +                               s3c_irqwake_eintmask);
29898 +}
29899 +
29900 +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
29901 +                                          struct pm_uart_save *save)
29902 +{
29903 +}
29904 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/pm.h
29905 ===================================================================
29906 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/pm.h   2008-12-25 00:26:37.000000000 +0100
29907 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
29908 @@ -1,73 +0,0 @@
29909 -/* linux/include/asm-arm/plat-s3c24xx/pm.h
29910 - *
29911 - * Copyright (c) 2004 Simtec Electronics
29912 - *     Written by Ben Dooks, <ben@simtec.co.uk>
29913 - *
29914 - * This program is free software; you can redistribute it and/or modify
29915 - * it under the terms of the GNU General Public License version 2 as
29916 - * published by the Free Software Foundation.
29917 -*/
29918 -
29919 -/* s3c2410_pm_init
29920 - *
29921 - * called from board at initialisation time to setup the power
29922 - * management
29923 -*/
29924 -
29925 -#ifdef CONFIG_PM
29926 -
29927 -extern __init int s3c2410_pm_init(void);
29928 -
29929 -#else
29930 -
29931 -static inline int s3c2410_pm_init(void)
29932 -{
29933 -       return 0;
29934 -}
29935 -#endif
29936 -
29937 -/* configuration for the IRQ mask over sleep */
29938 -extern unsigned long s3c_irqwake_intmask;
29939 -extern unsigned long s3c_irqwake_eintmask;
29940 -
29941 -/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
29942 -extern unsigned long s3c_irqwake_intallow;
29943 -extern unsigned long s3c_irqwake_eintallow;
29944 -
29945 -/* per-cpu sleep functions */
29946 -
29947 -extern void (*pm_cpu_prep)(void);
29948 -extern void (*pm_cpu_sleep)(void);
29949 -
29950 -/* Flags for PM Control */
29951 -
29952 -extern unsigned long s3c_pm_flags;
29953 -
29954 -/* from sleep.S */
29955 -
29956 -extern int  s3c2410_cpu_save(unsigned long *saveblk);
29957 -extern void s3c2410_cpu_suspend(void);
29958 -extern void s3c2410_cpu_resume(void);
29959 -
29960 -extern unsigned long s3c2410_sleep_save_phys;
29961 -
29962 -/* sleep save info */
29963 -
29964 -struct sleep_save {
29965 -       void __iomem    *reg;
29966 -       unsigned long   val;
29967 -};
29968 -
29969 -#define SAVE_ITEM(x) \
29970 -       { .reg = (x) }
29971 -
29972 -extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
29973 -extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
29974 -
29975 -#ifdef CONFIG_PM
29976 -extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
29977 -extern int s3c24xx_irq_resume(struct sys_device *dev);
29978 -#else
29979 -#define s3c24xx_irq_suspend NULL
29980 -#define s3c24xx_irq_resume  NULL
29981 -#endif
29982 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
29983 ===================================================================
29984 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
29985 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-spi.h  2009-01-02 00:01:56.000000000 +0100
29986 @@ -0,0 +1,82 @@
29987 +/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
29988 + *
29989 + * Copyright (c) 2004 Fetron GmbH
29990 + *
29991 + * This program is free software; you can redistribute it and/or modify
29992 + * it under the terms of the GNU General Public License version 2 as
29993 + * published by the Free Software Foundation.
29994 + *
29995 + * S3C2410 SPI register definition
29996 +*/
29997 +
29998 +#ifndef __ASM_ARCH_REGS_SPI_H
29999 +#define __ASM_ARCH_REGS_SPI_H
30000 +
30001 +#define S3C2410_SPI1   (0x20)
30002 +#define S3C2412_SPI1   (0x100)
30003 +
30004 +#define S3C2410_SPCON  (0x00)
30005 +
30006 +#define S3C2412_SPCON_RXFIFO_RB2       (0<<14)
30007 +#define S3C2412_SPCON_RXFIFO_RB4       (1<<14)
30008 +#define S3C2412_SPCON_RXFIFO_RB12      (2<<14)
30009 +#define S3C2412_SPCON_RXFIFO_RB14      (3<<14)
30010 +#define S3C2412_SPCON_TXFIFO_RB2       (0<<12)
30011 +#define S3C2412_SPCON_TXFIFO_RB4       (1<<12)
30012 +#define S3C2412_SPCON_TXFIFO_RB12      (2<<12)
30013 +#define S3C2412_SPCON_TXFIFO_RB14      (3<<12)
30014 +#define S3C2412_SPCON_RXFIFO_RESET     (1<<11) /* RxFIFO reset */
30015 +#define S3C2412_SPCON_TXFIFO_RESET     (1<<10) /* TxFIFO reset */
30016 +#define S3C2412_SPCON_RXFIFO_EN                (1<<9)  /* RxFIFO Enable */
30017 +#define S3C2412_SPCON_TXFIFO_EN                (1<<8)  /* TxFIFO Enable */
30018 +
30019 +#define S3C2412_SPCON_DIRC_RX    (1<<7)
30020 +
30021 +#define S3C2410_SPCON_SMOD_DMA   (2<<5)        /* DMA mode */
30022 +#define S3C2410_SPCON_SMOD_INT   (1<<5)        /* interrupt mode */
30023 +#define S3C2410_SPCON_SMOD_POLL   (0<<5)       /* polling mode */
30024 +#define S3C2410_SPCON_ENSCK      (1<<4)        /* Enable SCK */
30025 +#define S3C2410_SPCON_MSTR       (1<<3)        /* Master/Slave select
30026 +                                                  0: slave, 1: master */
30027 +#define S3C2410_SPCON_CPOL_HIGH          (1<<2)        /* Clock polarity select */
30028 +#define S3C2410_SPCON_CPOL_LOW   (0<<2)        /* Clock polarity select */
30029 +
30030 +#define S3C2410_SPCON_CPHA_FMTB          (1<<1)        /* Clock Phase Select */
30031 +#define S3C2410_SPCON_CPHA_FMTA          (0<<1)        /* Clock Phase Select */
30032 +
30033 +#define S3C2410_SPCON_TAGD       (1<<0)        /* Tx auto garbage data mode */
30034 +
30035 +
30036 +#define S3C2410_SPSTA   (0x04)
30037 +
30038 +#define S3C2412_SPSTA_RXFIFO_AE                (1<<11)
30039 +#define S3C2412_SPSTA_TXFIFO_AE                (1<<10)
30040 +#define S3C2412_SPSTA_RXFIFO_ERROR     (1<<9)
30041 +#define S3C2412_SPSTA_TXFIFO_ERROR     (1<<8)
30042 +#define S3C2412_SPSTA_RXFIFO_FIFO      (1<<7)
30043 +#define S3C2412_SPSTA_RXFIFO_EMPTY     (1<<6)
30044 +#define S3C2412_SPSTA_TXFIFO_NFULL     (1<<5)
30045 +#define S3C2412_SPSTA_TXFIFO_EMPTY     (1<<4)
30046 +
30047 +#define S3C2410_SPSTA_DCOL       (1<<2)        /* Data Collision Error */
30048 +#define S3C2410_SPSTA_MULD       (1<<1)        /* Multi Master Error */
30049 +#define S3C2410_SPSTA_READY      (1<<0)        /* Data Tx/Rx ready */
30050 +#define S3C2412_SPSTA_READY_ORG          (1<<3)
30051 +
30052 +#define S3C2410_SPPIN   (0x08)
30053 +
30054 +#define S3C2410_SPPIN_ENMUL      (1<<2)        /* Multi Master Error detect */
30055 +#define S3C2410_SPPIN_RESERVED   (1<<1)
30056 +#define S3C2400_SPPIN_nCS        (1<<1)        /* SPI Card Select */
30057 +#define S3C2410_SPPIN_KEEP       (1<<0)        /* Master Out keep */
30058 +
30059 +#define S3C2410_SPPRE   (0x0C)
30060 +#define S3C2410_SPTDAT  (0x10)
30061 +#define S3C2410_SPRDAT  (0x14)
30062 +
30063 +#define S3C2412_TXFIFO  (0x18)
30064 +#define S3C2412_RXFIFO  (0x18)
30065 +#define S3C2412_SPFIC   (0x24)
30066 +
30067 +
30068 +#endif /* __ASM_ARCH_REGS_SPI_H */
30069 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
30070 ===================================================================
30071 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
30072 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-udc.h  2009-01-02 00:01:56.000000000 +0100
30073 @@ -0,0 +1,153 @@
30074 +/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
30075 + *
30076 + * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
30077 + *
30078 + * This include file is free software; you can redistribute it and/or
30079 + * modify it under the terms of the GNU General Public License as
30080 + * published by the Free Software Foundation; either version 2 of
30081 + * the License, or (at your option) any later version.
30082 +*/
30083 +
30084 +#ifndef __ASM_ARCH_REGS_UDC_H
30085 +#define __ASM_ARCH_REGS_UDC_H
30086 +
30087 +#define S3C2410_USBDREG(x) (x)
30088 +
30089 +#define S3C2410_UDC_FUNC_ADDR_REG      S3C2410_USBDREG(0x0140)
30090 +#define S3C2410_UDC_PWR_REG            S3C2410_USBDREG(0x0144)
30091 +#define S3C2410_UDC_EP_INT_REG         S3C2410_USBDREG(0x0148)
30092 +
30093 +#define S3C2410_UDC_USB_INT_REG                S3C2410_USBDREG(0x0158)
30094 +#define S3C2410_UDC_EP_INT_EN_REG      S3C2410_USBDREG(0x015c)
30095 +
30096 +#define S3C2410_UDC_USB_INT_EN_REG     S3C2410_USBDREG(0x016c)
30097 +
30098 +#define S3C2410_UDC_FRAME_NUM1_REG     S3C2410_USBDREG(0x0170)
30099 +#define S3C2410_UDC_FRAME_NUM2_REG     S3C2410_USBDREG(0x0174)
30100 +
30101 +#define S3C2410_UDC_EP0_FIFO_REG       S3C2410_USBDREG(0x01c0)
30102 +#define S3C2410_UDC_EP1_FIFO_REG       S3C2410_USBDREG(0x01c4)
30103 +#define S3C2410_UDC_EP2_FIFO_REG       S3C2410_USBDREG(0x01c8)
30104 +#define S3C2410_UDC_EP3_FIFO_REG       S3C2410_USBDREG(0x01cc)
30105 +#define S3C2410_UDC_EP4_FIFO_REG       S3C2410_USBDREG(0x01d0)
30106 +
30107 +#define S3C2410_UDC_EP1_DMA_CON                S3C2410_USBDREG(0x0200)
30108 +#define S3C2410_UDC_EP1_DMA_UNIT       S3C2410_USBDREG(0x0204)
30109 +#define S3C2410_UDC_EP1_DMA_FIFO       S3C2410_USBDREG(0x0208)
30110 +#define S3C2410_UDC_EP1_DMA_TTC_L      S3C2410_USBDREG(0x020c)
30111 +#define S3C2410_UDC_EP1_DMA_TTC_M      S3C2410_USBDREG(0x0210)
30112 +#define S3C2410_UDC_EP1_DMA_TTC_H      S3C2410_USBDREG(0x0214)
30113 +
30114 +#define S3C2410_UDC_EP2_DMA_CON                S3C2410_USBDREG(0x0218)
30115 +#define S3C2410_UDC_EP2_DMA_UNIT       S3C2410_USBDREG(0x021c)
30116 +#define S3C2410_UDC_EP2_DMA_FIFO       S3C2410_USBDREG(0x0220)
30117 +#define S3C2410_UDC_EP2_DMA_TTC_L      S3C2410_USBDREG(0x0224)
30118 +#define S3C2410_UDC_EP2_DMA_TTC_M      S3C2410_USBDREG(0x0228)
30119 +#define S3C2410_UDC_EP2_DMA_TTC_H      S3C2410_USBDREG(0x022c)
30120 +
30121 +#define S3C2410_UDC_EP3_DMA_CON                S3C2410_USBDREG(0x0240)
30122 +#define S3C2410_UDC_EP3_DMA_UNIT       S3C2410_USBDREG(0x0244)
30123 +#define S3C2410_UDC_EP3_DMA_FIFO       S3C2410_USBDREG(0x0248)
30124 +#define S3C2410_UDC_EP3_DMA_TTC_L      S3C2410_USBDREG(0x024c)
30125 +#define S3C2410_UDC_EP3_DMA_TTC_M      S3C2410_USBDREG(0x0250)
30126 +#define S3C2410_UDC_EP3_DMA_TTC_H      S3C2410_USBDREG(0x0254)
30127 +
30128 +#define S3C2410_UDC_EP4_DMA_CON                S3C2410_USBDREG(0x0258)
30129 +#define S3C2410_UDC_EP4_DMA_UNIT       S3C2410_USBDREG(0x025c)
30130 +#define S3C2410_UDC_EP4_DMA_FIFO       S3C2410_USBDREG(0x0260)
30131 +#define S3C2410_UDC_EP4_DMA_TTC_L      S3C2410_USBDREG(0x0264)
30132 +#define S3C2410_UDC_EP4_DMA_TTC_M      S3C2410_USBDREG(0x0268)
30133 +#define S3C2410_UDC_EP4_DMA_TTC_H      S3C2410_USBDREG(0x026c)
30134 +
30135 +#define S3C2410_UDC_INDEX_REG          S3C2410_USBDREG(0x0178)
30136 +
30137 +/* indexed registers */
30138 +
30139 +#define S3C2410_UDC_MAXP_REG           S3C2410_USBDREG(0x0180)
30140 +
30141 +#define S3C2410_UDC_EP0_CSR_REG                S3C2410_USBDREG(0x0184)
30142 +
30143 +#define S3C2410_UDC_IN_CSR1_REG                S3C2410_USBDREG(0x0184)
30144 +#define S3C2410_UDC_IN_CSR2_REG                S3C2410_USBDREG(0x0188)
30145 +
30146 +#define S3C2410_UDC_OUT_CSR1_REG       S3C2410_USBDREG(0x0190)
30147 +#define S3C2410_UDC_OUT_CSR2_REG       S3C2410_USBDREG(0x0194)
30148 +#define S3C2410_UDC_OUT_FIFO_CNT1_REG  S3C2410_USBDREG(0x0198)
30149 +#define S3C2410_UDC_OUT_FIFO_CNT2_REG  S3C2410_USBDREG(0x019c)
30150 +
30151 +#define S3C2410_UDC_FUNCADDR_UPDATE    (1<<7)
30152 +
30153 +#define S3C2410_UDC_PWR_ISOUP          (1<<7) // R/W
30154 +#define S3C2410_UDC_PWR_RESET          (1<<3) // R
30155 +#define S3C2410_UDC_PWR_RESUME         (1<<2) // R/W
30156 +#define S3C2410_UDC_PWR_SUSPEND                (1<<1) // R
30157 +#define S3C2410_UDC_PWR_ENSUSPEND      (1<<0) // R/W
30158 +
30159 +#define S3C2410_UDC_PWR_DEFAULT                0x00
30160 +
30161 +#define S3C2410_UDC_INT_EP4            (1<<4) // R/W (clear only)
30162 +#define S3C2410_UDC_INT_EP3            (1<<3) // R/W (clear only)
30163 +#define S3C2410_UDC_INT_EP2            (1<<2) // R/W (clear only)
30164 +#define S3C2410_UDC_INT_EP1            (1<<1) // R/W (clear only)
30165 +#define S3C2410_UDC_INT_EP0            (1<<0) // R/W (clear only)
30166 +
30167 +#define S3C2410_UDC_USBINT_RESET       (1<<2) // R/W (clear only)
30168 +#define S3C2410_UDC_USBINT_RESUME      (1<<1) // R/W (clear only)
30169 +#define S3C2410_UDC_USBINT_SUSPEND     (1<<0) // R/W (clear only)
30170 +
30171 +#define S3C2410_UDC_INTE_EP4           (1<<4) // R/W
30172 +#define S3C2410_UDC_INTE_EP3           (1<<3) // R/W
30173 +#define S3C2410_UDC_INTE_EP2           (1<<2) // R/W
30174 +#define S3C2410_UDC_INTE_EP1           (1<<1) // R/W
30175 +#define S3C2410_UDC_INTE_EP0           (1<<0) // R/W
30176 +
30177 +#define S3C2410_UDC_USBINTE_RESET      (1<<2) // R/W
30178 +#define S3C2410_UDC_USBINTE_SUSPEND    (1<<0) // R/W
30179 +
30180 +
30181 +#define S3C2410_UDC_INDEX_EP0          (0x00)
30182 +#define S3C2410_UDC_INDEX_EP1          (0x01) // ??
30183 +#define S3C2410_UDC_INDEX_EP2          (0x02) // ??
30184 +#define S3C2410_UDC_INDEX_EP3          (0x03) // ??
30185 +#define S3C2410_UDC_INDEX_EP4          (0x04) // ??
30186 +
30187 +#define S3C2410_UDC_ICSR1_CLRDT                (1<<6) // R/W
30188 +#define S3C2410_UDC_ICSR1_SENTSTL      (1<<5) // R/W (clear only)
30189 +#define S3C2410_UDC_ICSR1_SENDSTL      (1<<4) // R/W
30190 +#define S3C2410_UDC_ICSR1_FFLUSH       (1<<3) // W   (set only)
30191 +#define S3C2410_UDC_ICSR1_UNDRUN       (1<<2) // R/W (clear only)
30192 +#define S3C2410_UDC_ICSR1_PKTRDY       (1<<0) // R/W (set only)
30193 +
30194 +#define S3C2410_UDC_ICSR2_AUTOSET      (1<<7) // R/W
30195 +#define S3C2410_UDC_ICSR2_ISO          (1<<6) // R/W
30196 +#define S3C2410_UDC_ICSR2_MODEIN       (1<<5) // R/W
30197 +#define S3C2410_UDC_ICSR2_DMAIEN       (1<<4) // R/W
30198 +
30199 +#define S3C2410_UDC_OCSR1_CLRDT                (1<<7) // R/W
30200 +#define S3C2410_UDC_OCSR1_SENTSTL      (1<<6) // R/W (clear only)
30201 +#define S3C2410_UDC_OCSR1_SENDSTL      (1<<5) // R/W
30202 +#define S3C2410_UDC_OCSR1_FFLUSH       (1<<4) // R/W
30203 +#define S3C2410_UDC_OCSR1_DERROR       (1<<3) // R
30204 +#define S3C2410_UDC_OCSR1_OVRRUN       (1<<2) // R/W (clear only)
30205 +#define S3C2410_UDC_OCSR1_PKTRDY       (1<<0) // R/W (clear only)
30206 +
30207 +#define S3C2410_UDC_OCSR2_AUTOCLR      (1<<7) // R/W
30208 +#define S3C2410_UDC_OCSR2_ISO          (1<<6) // R/W
30209 +#define S3C2410_UDC_OCSR2_DMAIEN       (1<<5) // R/W
30210 +
30211 +#define S3C2410_UDC_EP0_CSR_OPKRDY     (1<<0)
30212 +#define S3C2410_UDC_EP0_CSR_IPKRDY     (1<<1)
30213 +#define S3C2410_UDC_EP0_CSR_SENTSTL    (1<<2)
30214 +#define S3C2410_UDC_EP0_CSR_DE         (1<<3)
30215 +#define S3C2410_UDC_EP0_CSR_SE         (1<<4)
30216 +#define S3C2410_UDC_EP0_CSR_SENDSTL    (1<<5)
30217 +#define S3C2410_UDC_EP0_CSR_SOPKTRDY   (1<<6)
30218 +#define S3C2410_UDC_EP0_CSR_SSE        (1<<7)
30219 +
30220 +#define S3C2410_UDC_MAXP_8             (1<<0)
30221 +#define S3C2410_UDC_MAXP_16            (1<<1)
30222 +#define S3C2410_UDC_MAXP_32            (1<<2)
30223 +#define S3C2410_UDC_MAXP_64            (1<<3)
30224 +
30225 +
30226 +#endif
30227 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
30228 ===================================================================
30229 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/s3c2400.h      2008-12-25 00:26:37.000000000 +0100
30230 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2400.h   2009-01-02 00:01:56.000000000 +0100
30231 @@ -17,7 +17,7 @@
30232
30233  extern  int s3c2400_init(void);
30234
30235 -extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
30236 +extern void s3c2400_map_io(void);
30237
30238  extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
30239
30240 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
30241 ===================================================================
30242 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/s3c2410.h      2008-12-25 00:26:37.000000000 +0100
30243 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2410.h   2009-01-02 00:01:56.000000000 +0100
30244 @@ -15,7 +15,7 @@
30245
30246  extern  int s3c2410_init(void);
30247
30248 -extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
30249 +extern void s3c2410_map_io(void);
30250
30251  extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
30252
30253 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
30254 ===================================================================
30255 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/s3c2412.h      2008-12-25 00:26:37.000000000 +0100
30256 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2412.h   2009-01-02 00:01:56.000000000 +0100
30257 @@ -14,7 +14,7 @@
30258
30259  extern  int s3c2412_init(void);
30260
30261 -extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
30262 +extern void s3c2412_map_io(void);
30263
30264  extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
30265
30266 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
30267 ===================================================================
30268 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/include/plat/s3c2443.h      2008-12-25 00:26:37.000000000 +0100
30269 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2443.h   2009-01-02 00:01:56.000000000 +0100
30270 @@ -16,7 +16,7 @@ struct s3c2410_uartcfg;
30271
30272  extern  int s3c2443_init(void);
30273
30274 -extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
30275 +extern void s3c2443_map_io(void);
30276
30277  extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
30278
30279 Index: linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/udc.h
30280 ===================================================================
30281 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
30282 +++ linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/udc.h       2009-01-02 00:01:56.000000000 +0100
30283 @@ -0,0 +1,36 @@
30284 +/* arch/arm/mach-s3c2410/include/mach/udc.h
30285 + *
30286 + * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
30287 + *
30288 + *
30289 + * This program is free software; you can redistribute it and/or modify
30290 + * it under the terms of the GNU General Public License version 2 as
30291 + * published by the Free Software Foundation.
30292 + *
30293 + *
30294 + *  Changelog:
30295 + *     14-Mar-2005     RTP     Created file
30296 + *     02-Aug-2005     RTP     File rename
30297 + *     07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
30298 + *     18-Jan-2007     HMW     Add per-platform vbus_draw function
30299 +*/
30300 +
30301 +#ifndef __ASM_ARM_ARCH_UDC_H
30302 +#define __ASM_ARM_ARCH_UDC_H
30303 +
30304 +enum s3c2410_udc_cmd_e {
30305 +       S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
30306 +       S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
30307 +       S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
30308 +};
30309 +
30310 +struct s3c2410_udc_mach_info {
30311 +       void    (*udc_command)(enum s3c2410_udc_cmd_e);
30312 +       void    (*vbus_draw)(unsigned int ma);
30313 +       unsigned int vbus_pin;
30314 +       unsigned char vbus_pin_inverted;
30315 +};
30316 +
30317 +extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
30318 +
30319 +#endif /* __ASM_ARM_ARCH_UDC_H */
30320 Index: linux-2.6.28/arch/arm/plat-s3c24xx/irq.c
30321 ===================================================================
30322 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/irq.c       2008-12-25 00:26:37.000000000 +0100
30323 +++ linux-2.6.28/arch/arm/plat-s3c24xx/irq.c    2009-01-02 00:01:56.000000000 +0100
30324 @@ -1,6 +1,6 @@
30325  /* linux/arch/arm/plat-s3c24xx/irq.c
30326   *
30327 - * Copyright (c) 2003,2004 Simtec Electronics
30328 + * Copyright (c) 2003,2004 Simtec Electronics
30329   *     Ben Dooks <ben@simtec.co.uk>
30330   *
30331   * This program is free software; you can redistribute it and/or modify
30332 @@ -16,38 +16,6 @@
30333   * You should have received a copy of the GNU General Public License
30334   * along with this program; if not, write to the Free Software
30335   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
30336 - *
30337 - * Changelog:
30338 - *
30339 - *   22-Jul-2004  Ben Dooks <ben@simtec.co.uk>
30340 - *                Fixed compile warnings
30341 - *
30342 - *   22-Jul-2004  Roc Wu <cooloney@yahoo.com.cn>
30343 - *                Fixed s3c_extirq_type
30344 - *
30345 - *   21-Jul-2004  Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
30346 - *                Addition of ADC/TC demux
30347 - *
30348 - *   04-Oct-2004  Klaus Fetscher <k.fetscher@fetron.de>
30349 - *               Fix for set_irq_type() on low EINT numbers
30350 - *
30351 - *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
30352 - *               Tidy up KF's patch and sort out new release
30353 - *
30354 - *   05-Oct-2004  Ben Dooks <ben@simtec.co.uk>
30355 - *               Add support for power management controls
30356 - *
30357 - *   04-Nov-2004  Ben Dooks
30358 - *               Fix standard IRQ wake for EINT0..4 and RTC
30359 - *
30360 - *   22-Feb-2005  Ben Dooks
30361 - *               Fixed edge-triggering on ADC IRQ
30362 - *
30363 - *   28-Jun-2005  Ben Dooks
30364 - *               Mark IRQ_LCD valid
30365 - *
30366 - *   25-Jul-2005  Ben Dooks
30367 - *               Split the S3C2440 IRQ code to separate file
30368  */
30369
30370  #include <linux/init.h>
30371 @@ -55,90 +23,34 @@
30372  #include <linux/interrupt.h>
30373  #include <linux/ioport.h>
30374  #include <linux/sysdev.h>
30375 -#include <linux/io.h>
30376
30377 -#include <mach/hardware.h>
30378  #include <asm/irq.h>
30379 -
30380  #include <asm/mach/irq.h>
30381
30382 -#include <mach/regs-irq.h>
30383 -#include <mach/regs-gpio.h>
30384 +#include <plat/regs-irqtype.h>
30385
30386  #include <plat/cpu.h>
30387  #include <plat/pm.h>
30388  #include <plat/irq.h>
30389
30390 -/* wakeup irq control */
30391 -
30392 -#ifdef CONFIG_PM
30393 -
30394 -/* state for IRQs over sleep */
30395 -
30396 -/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
30397 - *
30398 - * set bit to 1 in allow bitfield to enable the wakeup settings on it
30399 -*/
30400 -
30401 -unsigned long s3c_irqwake_intallow     = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
30402 -unsigned long s3c_irqwake_intmask      = 0xffffffffL;
30403 -unsigned long s3c_irqwake_eintallow    = 0x0000fff0L;
30404 -unsigned long s3c_irqwake_eintmask     = 0xffffffffL;
30405 -
30406 -int
30407 -s3c_irq_wake(unsigned int irqno, unsigned int state)
30408 -{
30409 -       unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
30410 -
30411 -       if (!(s3c_irqwake_intallow & irqbit))
30412 -               return -ENOENT;
30413 -
30414 -       printk(KERN_INFO "wake %s for irq %d\n",
30415 -              state ? "enabled" : "disabled", irqno);
30416 -
30417 -       if (!state)
30418 -               s3c_irqwake_intmask |= irqbit;
30419 -       else
30420 -               s3c_irqwake_intmask &= ~irqbit;
30421 -
30422 -       return 0;
30423 -}
30424 -
30425 -static int
30426 -s3c_irqext_wake(unsigned int irqno, unsigned int state)
30427 -{
30428 -       unsigned long bit = 1L << (irqno - EXTINT_OFF);
30429 -
30430 -       if (!(s3c_irqwake_eintallow & bit))
30431 -               return -ENOENT;
30432 -
30433 -       printk(KERN_INFO "wake %s for irq %d\n",
30434 -              state ? "enabled" : "disabled", irqno);
30435 -
30436 -       if (!state)
30437 -               s3c_irqwake_eintmask |= bit;
30438 -       else
30439 -               s3c_irqwake_eintmask &= ~bit;
30440 -
30441 -       return 0;
30442 -}
30443 -
30444 -#else
30445 -#define s3c_irqext_wake NULL
30446 -#define s3c_irq_wake NULL
30447 -#endif
30448 -
30449 -
30450  static void
30451  s3c_irq_mask(unsigned int irqno)
30452  {
30453         unsigned long mask;
30454 -
30455 +#ifdef CONFIG_S3C2440_C_FIQ
30456 +       unsigned long flags;
30457 +#endif
30458         irqno -= IRQ_EINT0;
30459 -
30460 +#ifdef CONFIG_S3C2440_C_FIQ
30461 +       local_save_flags(flags);
30462 +       local_fiq_disable();
30463 +#endif
30464         mask = __raw_readl(S3C2410_INTMSK);
30465         mask |= 1UL << irqno;
30466         __raw_writel(mask, S3C2410_INTMSK);
30467 +#ifdef CONFIG_S3C2440_C_FIQ
30468 +       local_irq_restore(flags);
30469 +#endif
30470  }
30471
30472  static inline void
30473 @@ -155,9 +67,19 @@ s3c_irq_maskack(unsigned int irqno)
30474  {
30475         unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
30476         unsigned long mask;
30477 +#ifdef CONFIG_S3C2440_C_FIQ
30478 +       unsigned long flags;
30479 +#endif
30480
30481 +#ifdef CONFIG_S3C2440_C_FIQ
30482 +       local_save_flags(flags);
30483 +       local_fiq_disable();
30484 +#endif
30485         mask = __raw_readl(S3C2410_INTMSK);
30486         __raw_writel(mask|bitval, S3C2410_INTMSK);
30487 +#ifdef CONFIG_S3C2440_C_FIQ
30488 +       local_irq_restore(flags);
30489 +#endif
30490
30491         __raw_writel(bitval, S3C2410_SRCPND);
30492         __raw_writel(bitval, S3C2410_INTPND);
30493 @@ -168,15 +90,25 @@ static void
30494  s3c_irq_unmask(unsigned int irqno)
30495  {
30496         unsigned long mask;
30497 +#ifdef CONFIG_S3C2440_C_FIQ
30498 +       unsigned long flags;
30499 +#endif
30500
30501         if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
30502                 irqdbf2("s3c_irq_unmask %d\n", irqno);
30503
30504         irqno -= IRQ_EINT0;
30505
30506 +#ifdef CONFIG_S3C2440_C_FIQ
30507 +       local_save_flags(flags);
30508 +       local_fiq_disable();
30509 +#endif
30510         mask = __raw_readl(S3C2410_INTMSK);
30511         mask &= ~(1UL << irqno);
30512         __raw_writel(mask, S3C2410_INTMSK);
30513 +#ifdef CONFIG_S3C2440_C_FIQ
30514 +       local_irq_restore(flags);
30515 +#endif
30516  }
30517
30518  struct irq_chip s3c_irq_level_chip = {
30519 @@ -589,59 +521,6 @@ s3c_irq_demux_extint4t7(unsigned int irq
30520         }
30521  }
30522
30523 -#ifdef CONFIG_PM
30524 -
30525 -static struct sleep_save irq_save[] = {
30526 -       SAVE_ITEM(S3C2410_INTMSK),
30527 -       SAVE_ITEM(S3C2410_INTSUBMSK),
30528 -};
30529 -
30530 -/* the extint values move between the s3c2410/s3c2440 and the s3c2412
30531 - * so we use an array to hold them, and to calculate the address of
30532 - * the register at run-time
30533 -*/
30534 -
30535 -static unsigned long save_extint[3];
30536 -static unsigned long save_eintflt[4];
30537 -static unsigned long save_eintmask;
30538 -
30539 -int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
30540 -{
30541 -       unsigned int i;
30542 -
30543 -       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30544 -               save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
30545 -
30546 -       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30547 -               save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
30548 -
30549 -       s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
30550 -       save_eintmask = __raw_readl(S3C24XX_EINTMASK);
30551 -
30552 -       return 0;
30553 -}
30554 -
30555 -int s3c24xx_irq_resume(struct sys_device *dev)
30556 -{
30557 -       unsigned int i;
30558 -
30559 -       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30560 -               __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
30561 -
30562 -       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30563 -               __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
30564 -
30565 -       s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
30566 -       __raw_writel(save_eintmask, S3C24XX_EINTMASK);
30567 -
30568 -       return 0;
30569 -}
30570 -
30571 -#else
30572 -#define s3c24xx_irq_suspend NULL
30573 -#define s3c24xx_irq_resume  NULL
30574 -#endif
30575 -
30576  /* s3c24xx_init_irq
30577   *
30578   * Initialise S3C2410 IRQ system
30579 @@ -672,26 +551,26 @@ void __init s3c24xx_init_irq(void)
30580
30581         last = 0;
30582         for (i = 0; i < 4; i++) {
30583 -               pend = __raw_readl(S3C2410_INTPND);
30584 +               pend = __raw_readl(S3C2410_SUBSRCPND);
30585
30586                 if (pend == 0 || pend == last)
30587                         break;
30588
30589 -               __raw_writel(pend, S3C2410_SRCPND);
30590 -               __raw_writel(pend, S3C2410_INTPND);
30591 -               printk("irq: clearing pending status %08x\n", (int)pend);
30592 +               printk("irq: clearing subpending status %08x\n", (int)pend);
30593 +               __raw_writel(pend, S3C2410_SUBSRCPND);
30594                 last = pend;
30595         }
30596
30597         last = 0;
30598         for (i = 0; i < 4; i++) {
30599 -               pend = __raw_readl(S3C2410_SUBSRCPND);
30600 +               pend = __raw_readl(S3C2410_INTPND);
30601
30602                 if (pend == 0 || pend == last)
30603                         break;
30604
30605 -               printk("irq: clearing subpending status %08x\n", (int)pend);
30606 -               __raw_writel(pend, S3C2410_SUBSRCPND);
30607 +               __raw_writel(pend, S3C2410_SRCPND);
30608 +               __raw_writel(pend, S3C2410_INTPND);
30609 +               printk("irq: clearing pending status %08x\n", (int)pend);
30610                 last = pend;
30611         }
30612
30613 Index: linux-2.6.28/arch/arm/plat-s3c24xx/irq-pm.c
30614 ===================================================================
30615 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
30616 +++ linux-2.6.28/arch/arm/plat-s3c24xx/irq-pm.c 2009-01-02 00:01:56.000000000 +0100
30617 @@ -0,0 +1,118 @@
30618 +/* linux/arch/arm/plat-s3c24xx/irq-om.c
30619 + *
30620 + * Copyright (c) 2003,2004 Simtec Electronics
30621 + *     Ben Dooks <ben@simtec.co.uk>
30622 + *     http://armlinux.simtec.co.uk/
30623 + *
30624 + * S3C24XX - IRQ PM code
30625 + *
30626 + * This program is free software; you can redistribute it and/or modify
30627 + * it under the terms of the GNU General Public License version 2 as
30628 + * published by the Free Software Foundation.
30629 + */
30630 +
30631 +#include <linux/init.h>
30632 +#include <linux/module.h>
30633 +#include <linux/interrupt.h>
30634 +#include <linux/sysdev.h>
30635 +#include <linux/irq.h>
30636 +
30637 +#include <plat/cpu.h>
30638 +#include <plat/pm.h>
30639 +#include <plat/irq.h>
30640 +
30641 +/* state for IRQs over sleep */
30642 +
30643 +/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
30644 + *
30645 + * set bit to 1 in allow bitfield to enable the wakeup settings on it
30646 +*/
30647 +
30648 +unsigned long s3c_irqwake_intallow     = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
30649 +unsigned long s3c_irqwake_eintallow    = 0x0000fff0L;
30650 +
30651 +int s3c_irq_wake(unsigned int irqno, unsigned int state)
30652 +{
30653 +       unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
30654 +
30655 +       if (!(s3c_irqwake_intallow & irqbit))
30656 +               return -ENOENT;
30657 +
30658 +       printk(KERN_INFO "wake %s for irq %d\n",
30659 +              state ? "enabled" : "disabled", irqno);
30660 +
30661 +       if (!state)
30662 +               s3c_irqwake_intmask |= irqbit;
30663 +       else
30664 +               s3c_irqwake_intmask &= ~irqbit;
30665 +
30666 +       return 0;
30667 +}
30668 +
30669 +static struct sleep_save irq_save[] = {
30670 +       SAVE_ITEM(S3C2410_INTMSK),
30671 +       SAVE_ITEM(S3C2410_INTSUBMSK),
30672 +};
30673 +
30674 +/* the extint values move between the s3c2410/s3c2440 and the s3c2412
30675 + * so we use an array to hold them, and to calculate the address of
30676 + * the register at run-time
30677 +*/
30678 +
30679 +static unsigned long save_extint[3];
30680 +static unsigned long save_eintflt[4];
30681 +static unsigned long save_eintmask;
30682 +
30683 +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
30684 +{
30685 +       unsigned int i;
30686 +
30687 +       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30688 +               save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
30689 +
30690 +       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30691 +               save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
30692 +
30693 +       s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
30694 +       save_eintmask = __raw_readl(S3C24XX_EINTMASK);
30695 +
30696 +       return 0;
30697 +}
30698 +
30699 +int s3c24xx_irq_resume(struct sys_device *dev)
30700 +{
30701 +       unsigned int i, irq;
30702 +       unsigned long eintpnd;
30703 +       struct irq_desc *desc;
30704 +
30705 +       for (i = 0; i < ARRAY_SIZE(save_extint); i++)
30706 +               __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
30707 +
30708 +       for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
30709 +               __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
30710 +
30711 +       s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
30712 +       __raw_writel(save_eintmask, S3C24XX_EINTMASK);
30713 +
30714 +       /*
30715 +        * ACK those interrupts which are now masked and pending.
30716 +        * Level interrupts if not ACKed here, create an interrupt storm
30717 +        * because they are not handled at all.
30718 +        */
30719 +
30720 +       eintpnd = __raw_readl(S3C24XX_EINTPEND);
30721 +
30722 +       eintpnd &= save_eintmask;
30723 +       eintpnd &= ~0xff;       /* ignore lower irqs */
30724 +
30725 +       while (eintpnd) {
30726 +               irq = __ffs(eintpnd);
30727 +               eintpnd &= ~(1 << irq);
30728 +
30729 +               irq += (IRQ_EINT4 - 4);
30730 +               desc = irq_to_desc(irq);
30731 +               desc->chip->ack(irq);
30732 +       }
30733 +
30734 +       return 0;
30735 +}
30736 Index: linux-2.6.28/arch/arm/plat-s3c24xx/Kconfig
30737 ===================================================================
30738 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/Kconfig     2008-12-25 00:26:37.000000000 +0100
30739 +++ linux-2.6.28/arch/arm/plat-s3c24xx/Kconfig  2009-01-02 00:01:56.000000000 +0100
30740 @@ -6,18 +6,32 @@
30741
30742  config PLAT_S3C24XX
30743         bool
30744 -       depends on ARCH_S3C2410
30745 -       default y if ARCH_S3C2410
30746 +       depends on ARCH_S3C2410 || ARCH_S3C24A0
30747 +       default y
30748         select NO_IOPORT
30749         select ARCH_REQUIRE_GPIOLIB
30750 +       select S3C_GPIO_TRACK
30751         help
30752           Base platform code for any Samsung S3C24XX device
30753
30754  if PLAT_S3C24XX
30755
30756 +# code that is shared between a number of the s3c24xx implementations
30757 +
30758 +config S3C2410_CLOCK
30759 +       bool
30760 +       help
30761 +         Clock code for the S3C2410, and similar processors which
30762 +         is currently includes the S3C2410, S3C2440, S3C2442.
30763 +
30764 +config S3C24XX_DCLK
30765 +       bool
30766 +       help
30767 +         Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
30768 +
30769  config CPU_S3C244X
30770         bool
30771 -       depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
30772 +       default y if CPU_S3C2440 || CPU_S3C2442
30773         help
30774           Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
30775
30776 @@ -49,9 +63,31 @@ config S3C2410_DMA_DEBUG
30777           Enable debugging output for the DMA code. This option sends info
30778           to the kernel log, at priority KERN_DEBUG.
30779
30780 +# SPI default pin configuration code
30781 +
30782 +config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
30783 +       bool
30784 +       help
30785 +         SPI GPIO configuration code for BUS0 when connected to
30786 +         GPE11, GPE12 and GPE13.
30787 +
30788 +config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
30789 +       bool
30790 +       help
30791 +         SPI GPIO configuration code for BUS 1 when connected to
30792 +         GPG5, GPG6 and GPG7.
30793 +
30794 +# common code for s3c24xx based machines, such as the SMDKs.
30795 +
30796  config MACH_SMDK
30797         bool
30798         help
30799           Common machine code for SMDK2410 and SMDK2440
30800
30801 +config MACH_NEO1973
30802 +       bool
30803 +       select RFKILL
30804 +       help
30805 +         Common machine code for Neo1973 hardware
30806 +
30807  endif
30808 Index: linux-2.6.28/arch/arm/plat-s3c24xx/Makefile
30809 ===================================================================
30810 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/Makefile    2008-12-25 00:26:37.000000000 +0100
30811 +++ linux-2.6.28/arch/arm/plat-s3c24xx/Makefile 2009-01-02 00:01:56.000000000 +0100
30812 @@ -17,9 +17,8 @@ obj-y                         += irq.o
30813  obj-y                          += devs.o
30814  obj-y                          += gpio.o
30815  obj-y                          += gpiolib.o
30816 -obj-y                          += time.o
30817  obj-y                          += clock.o
30818 -obj-y                          += pwm-clock.o
30819 +obj-$(CONFIG_S3C24XX_DCLK)     += clock-dclk.o
30820
30821  # Architecture dependant builds
30822
30823 @@ -28,7 +27,26 @@ obj-$(CONFIG_CPU_S3C244X)    += s3c244x-irq
30824  obj-$(CONFIG_CPU_S3C244X)      += s3c244x-clock.o
30825  obj-$(CONFIG_PM_SIMTEC)                += pm-simtec.o
30826  obj-$(CONFIG_PM)               += pm.o
30827 +obj-$(CONFIG_PM)               += irq-pm.o
30828  obj-$(CONFIG_PM)               += sleep.o
30829  obj-$(CONFIG_HAVE_PWM)         += pwm.o
30830 +obj-$(CONFIG_S3C2410_CLOCK)    += s3c2410-clock.o
30831  obj-$(CONFIG_S3C2410_DMA)      += dma.o
30832 +
30833 +# device specific setup and/or initialisation
30834 +obj-$(CONFIG_ARCH_S3C2410)     += setup-i2c.o
30835 +
30836 +# SPI gpio central GPIO functions
30837 +
30838 +obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
30839 +obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7)    += spi-bus1-gpg5_6_7.o
30840 +
30841 +# machine common support
30842 +
30843  obj-$(CONFIG_MACH_SMDK)                += common-smdk.o
30844 +obj-$(CONFIG_MACH_NEO1973)     += \
30845 +                                   neo1973_pm_gsm.o \
30846 +                                   neo1973_pm_gps.o \
30847 +                                   neo1973_pm_bt.o  \
30848 +                                   gta02_pm_wlan.o  \
30849 +                                   neo1973_shadow.o
30850 Index: linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_bt.c
30851 ===================================================================
30852 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
30853 +++ linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_bt.c  2009-01-02 00:01:56.000000000 +0100
30854 @@ -0,0 +1,323 @@
30855 +/*
30856 + * Bluetooth PM code for the FIC Neo1973 GSM Phone
30857 + *
30858 + * (C) 2007 by Openmoko Inc.
30859 + * Author: Harald Welte <laforge@openmoko.org>
30860 + * All rights reserved.
30861 + *
30862 + * This program is free software; you can redistribute it and/or modify
30863 + * it under the terms of the GNU General Public License version 2 as
30864 + * published by the Free Software Foundation
30865 + *
30866 + */
30867 +
30868 +#include <linux/module.h>
30869 +#include <linux/init.h>
30870 +#include <linux/kernel.h>
30871 +#include <linux/platform_device.h>
30872 +#include <linux/rfkill.h>
30873 +#include <linux/err.h>
30874 +
30875 +#include <mach/hardware.h>
30876 +#include <asm/mach-types.h>
30877 +#include <asm/plat-s3c24xx/neo1973.h>
30878 +
30879 +/* For GTA01 */
30880 +#include <mach/gta01.h>
30881 +#include <linux/pcf50606.h>
30882 +
30883 +/* For GTA02 */
30884 +#include <mach/gta02.h>
30885 +#include <linux/mfd/pcf50633/gpio.h>
30886 +
30887 +#include <linux/regulator/consumer.h>
30888 +
30889 +#define DRVMSG "FIC Neo1973 Bluetooth Power Management"
30890 +
30891 +struct gta01_pm_bt_data {
30892 +       struct regulator *regulator;
30893 +       struct rfkill *rfkill;
30894 +       int pre_resume_state;
30895 +};
30896 +
30897 +static ssize_t bt_read(struct device *dev, struct device_attribute *attr,
30898 +                      char *buf)
30899 +{
30900 +       int ret = 0;
30901 +
30902 +       if (!strcmp(attr->attr.name, "power_on")) {
30903 +
30904 +               if (machine_is_neo1973_gta01()) {
30905 +                       if (pcf50606_onoff_get(pcf50606_global,
30906 +                                               PCF50606_REGULATOR_D1REG) &&
30907 +                           pcf50606_voltage_get(pcf50606_global,
30908 +                                                PCF50606_REGULATOR_D1REG) == 3100)
30909 +                               ret = 1;
30910 +               } else if (machine_is_neo1973_gta02()) {
30911 +                       if (s3c2410_gpio_getpin(GTA02_GPIO_BT_EN))
30912 +                               ret = 1;
30913 +               }
30914 +       } else if (!strcmp(attr->attr.name, "reset")) {
30915 +               if (machine_is_neo1973_gta01()) {
30916 +                       if (s3c2410_gpio_getpin(GTA01_GPIO_BT_EN) == 0)
30917 +                               ret = 1;
30918 +               } else if (machine_is_neo1973_gta02()) {
30919 +                       if (s3c2410_gpio_getpin(GTA02_GPIO_BT_EN) == 0)
30920 +                               ret = 1;
30921 +               }
30922 +       }
30923 +
30924 +       if (!ret) {
30925 +               return strlcpy(buf, "0\n", 3);
30926 +       } else {
30927 +               return strlcpy(buf, "1\n", 3);
30928 +       }
30929 +}
30930 +
30931 +static void __gta02_pm_bt_toggle_radio(struct device *dev, unsigned int on)
30932 +{
30933 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(dev);
30934 +
30935 +       dev_info(dev, "__gta02_pm_bt_toggle_radio %d\n", on);
30936 +
30937 +       if (machine_is_neo1973_gta02()) {
30938 +
30939 +               bt_data = dev_get_drvdata(dev);
30940 +
30941 +               neo1973_gpb_setpin(GTA02_GPIO_BT_EN, !on);
30942 +
30943 +               if (on) {
30944 +                       if (!regulator_is_enabled(bt_data->regulator))
30945 +                               regulator_enable(bt_data->regulator);
30946 +               } else {
30947 +                       if (regulator_is_enabled(bt_data->regulator))
30948 +                               regulator_disable(bt_data->regulator);
30949 +               }
30950 +
30951 +               neo1973_gpb_setpin(GTA02_GPIO_BT_EN, on);
30952 +       }
30953 +}
30954 +
30955 +
30956 +static int bt_rfkill_toggle_radio(void *data, enum rfkill_state state)
30957 +{
30958 +       struct device *dev = data;
30959 +       unsigned long on = (state == RFKILL_STATE_ON);
30960 +
30961 +       if (machine_is_neo1973_gta01()) {
30962 +               /* if we are powering up, assert reset, then power,
30963 +                * then release reset */
30964 +               if (on) {
30965 +                       neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
30966 +                       pcf50606_voltage_set(pcf50606_global,
30967 +                                            PCF50606_REGULATOR_D1REG,
30968 +                                            3100);
30969 +               }
30970 +               pcf50606_onoff_set(pcf50606_global,
30971 +                                  PCF50606_REGULATOR_D1REG, on);
30972 +               neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on);
30973 +       } else if (machine_is_neo1973_gta02())
30974 +               __gta02_pm_bt_toggle_radio(dev, on);
30975 +
30976 +       return 0;
30977 +}
30978 +
30979 +static ssize_t bt_write(struct device *dev, struct device_attribute *attr,
30980 +                       const char *buf, size_t count)
30981 +{
30982 +       unsigned long on = simple_strtoul(buf, NULL, 10);
30983 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(dev);
30984 +
30985 +       if (!strcmp(attr->attr.name, "power_on")) {
30986 +               enum rfkill_state state = on ? RFKILL_STATE_ON : RFKILL_STATE_OFF;
30987 +               bt_rfkill_toggle_radio(dev, state);
30988 +               bt_data->rfkill->state = state;
30989 +
30990 +               if (machine_is_neo1973_gta01()) {
30991 +                       /* if we are powering up, assert reset, then power,
30992 +                        * then release reset */
30993 +                       if (on) {
30994 +                               neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
30995 +                               pcf50606_voltage_set(pcf50606_global,
30996 +                                                    PCF50606_REGULATOR_D1REG,
30997 +                                                    3100);
30998 +                       }
30999 +                       pcf50606_onoff_set(pcf50606_global,
31000 +                                          PCF50606_REGULATOR_D1REG, on);
31001 +                       neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on);
31002 +               } else if (machine_is_neo1973_gta02())
31003 +                       __gta02_pm_bt_toggle_radio(dev, on);
31004 +
31005 +       } else if (!strcmp(attr->attr.name, "reset")) {
31006 +               /* reset is low-active, so we need to invert */
31007 +               if (machine_is_neo1973_gta01()) {
31008 +                       neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on ? 0 : 1);
31009 +               } else if (machine_is_neo1973_gta02()) {
31010 +                       neo1973_gpb_setpin(GTA02_GPIO_BT_EN, on ? 0 : 1);
31011 +               }
31012 +       }
31013 +
31014 +       return count;
31015 +}
31016 +
31017 +static DEVICE_ATTR(power_on, 0644, bt_read, bt_write);
31018 +static DEVICE_ATTR(reset, 0644, bt_read, bt_write);
31019 +
31020 +#ifdef CONFIG_PM
31021 +static int gta01_bt_suspend(struct platform_device *pdev, pm_message_t state)
31022 +{
31023 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
31024 +
31025 +       dev_dbg(&pdev->dev, DRVMSG ": suspending\n");
31026 +
31027 +       if (machine_is_neo1973_gta02()) {
31028 +               bt_data->pre_resume_state =
31029 +                                         s3c2410_gpio_getpin(GTA02_GPIO_BT_EN);
31030 +               __gta02_pm_bt_toggle_radio(&pdev->dev, 0);
31031 +       }
31032 +
31033 +       return 0;
31034 +}
31035 +
31036 +static int gta01_bt_resume(struct platform_device *pdev)
31037 +{
31038 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
31039 +       dev_dbg(&pdev->dev, DRVMSG ": resuming\n");
31040 +
31041 +       if (machine_is_neo1973_gta02()) {
31042 +               __gta02_pm_bt_toggle_radio(&pdev->dev,
31043 +                                                    bt_data->pre_resume_state);
31044 +       }
31045 +
31046 +       return 0;
31047 +}
31048 +#else
31049 +#define gta01_bt_suspend       NULL
31050 +#define gta01_bt_resume                NULL
31051 +#endif
31052 +
31053 +static struct attribute *gta01_bt_sysfs_entries[] = {
31054 +       &dev_attr_power_on.attr,
31055 +       &dev_attr_reset.attr,
31056 +       NULL
31057 +};
31058 +
31059 +static struct attribute_group gta01_bt_attr_group = {
31060 +       .name   = NULL,
31061 +       .attrs  = gta01_bt_sysfs_entries,
31062 +};
31063 +
31064 +static int __init gta01_bt_probe(struct platform_device *pdev)
31065 +{
31066 +       struct rfkill *rfkill;
31067 +       struct regulator *regulator;
31068 +       struct gta01_pm_bt_data *bt_data;
31069 +       int ret;
31070 +
31071 +       dev_info(&pdev->dev, DRVMSG ": starting\n");
31072 +
31073 +       bt_data = kzalloc(sizeof(*bt_data), GFP_KERNEL);
31074 +       dev_set_drvdata(&pdev->dev, bt_data);
31075 +
31076 +       if (machine_is_neo1973_gta01()) {
31077 +               /* we make sure that the voltage is off */
31078 +               pcf50606_onoff_set(pcf50606_global,
31079 +                                  PCF50606_REGULATOR_D1REG, 0);
31080 +               /* we pull reset to low to make sure that the chip doesn't
31081 +                * drain power through the reset line */
31082 +               neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
31083 +       } else if (machine_is_neo1973_gta02()) {
31084 +               regulator = regulator_get(&pdev->dev, "BT_3V2");
31085 +               if (IS_ERR(regulator))
31086 +                       return -ENODEV;
31087 +
31088 +               bt_data->regulator = regulator;
31089 +
31090 +               /* this tests the true physical state of the regulator... */
31091 +               if (regulator_is_enabled(regulator)) {
31092 +                       /*
31093 +                        * but these only operate on the logical state of the
31094 +                        * regulator... so we need to logicaly "adopt" it on
31095 +                        * to turn it off
31096 +                        */
31097 +                       regulator_enable(regulator);
31098 +                       regulator_disable(regulator);
31099 +               }
31100 +
31101 +               /* we pull reset to low to make sure that the chip doesn't
31102 +                * drain power through the reset line */
31103 +               neo1973_gpb_setpin(GTA02_GPIO_BT_EN, 0);
31104 +       }
31105 +
31106 +       rfkill = rfkill_allocate(&pdev->dev, RFKILL_TYPE_BLUETOOTH);
31107 +
31108 +       rfkill->name = pdev->name;
31109 +       rfkill->data = &pdev->dev;
31110 +       rfkill->state = RFKILL_STATE_OFF;
31111 +       rfkill->toggle_radio = bt_rfkill_toggle_radio;
31112 +
31113 +       ret = rfkill_register(rfkill);
31114 +       if (ret) {
31115 +               dev_err(&pdev->dev, "Failed to register rfkill\n");
31116 +               return ret;
31117 +       }
31118 +
31119 +       bt_data->rfkill = rfkill;
31120 +
31121 +       return sysfs_create_group(&pdev->dev.kobj, &gta01_bt_attr_group);
31122 +}
31123 +
31124 +static int gta01_bt_remove(struct platform_device *pdev)
31125 +{
31126 +       struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
31127 +       struct regulator *regulator;
31128 +
31129 +       sysfs_remove_group(&pdev->dev.kobj, &gta01_bt_attr_group);
31130 +
31131 +       if (bt_data->rfkill) {
31132 +               rfkill_unregister(bt_data->rfkill);
31133 +               rfkill_free(bt_data->rfkill);
31134 +       }
31135 +
31136 +       if (!bt_data || !bt_data->regulator)
31137 +               return 0;
31138 +
31139 +       regulator = bt_data->regulator;
31140 +
31141 +       /* Make sure regulator is disabled before calling regulator_put */
31142 +       if (regulator_is_enabled(regulator))
31143 +               regulator_disable(regulator);
31144 +
31145 +       regulator_put(regulator);
31146 +
31147 +       kfree(bt_data);
31148 +
31149 +       return 0;
31150 +}
31151 +
31152 +static struct platform_driver gta01_bt_driver = {
31153 +       .probe          = gta01_bt_probe,
31154 +       .remove         = gta01_bt_remove,
31155 +       .suspend        = gta01_bt_suspend,
31156 +       .resume         = gta01_bt_resume,
31157 +       .driver         = {
31158 +               .name           = "neo1973-pm-bt",
31159 +       },
31160 +};
31161 +
31162 +static int __devinit gta01_bt_init(void)
31163 +{
31164 +       return platform_driver_register(&gta01_bt_driver);
31165 +}
31166 +
31167 +static void gta01_bt_exit(void)
31168 +{
31169 +       platform_driver_unregister(&gta01_bt_driver);
31170 +}
31171 +
31172 +module_init(gta01_bt_init);
31173 +module_exit(gta01_bt_exit);
31174 +
31175 +MODULE_LICENSE("GPL");
31176 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
31177 +MODULE_DESCRIPTION(DRVMSG);
31178 Index: linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_gps.c
31179 ===================================================================
31180 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
31181 +++ linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_gps.c 2009-01-02 00:01:56.000000000 +0100
31182 @@ -0,0 +1,699 @@
31183 +/*
31184 + * GPS Power Management code for the FIC Neo1973 GSM Phone
31185 + *
31186 + * (C) 2007 by Openmoko Inc.
31187 + * Author: Harald Welte <laforge@openmoko.org>
31188 + * All rights reserved.
31189 + *
31190 + * This program is free software; you can redistribute it and/or modify
31191 + * it under the terms of the GNU General Public License version 2 as
31192 + * published by the Free Software Foundation
31193 + *
31194 + */
31195 +
31196 +#include <linux/module.h>
31197 +#include <linux/init.h>
31198 +#include <linux/kernel.h>
31199 +#include <linux/delay.h>
31200 +#include <linux/platform_device.h>
31201 +
31202 +#include <mach/hardware.h>
31203 +
31204 +#include <asm/mach-types.h>
31205 +
31206 +#include <asm/plat-s3c24xx/neo1973.h>
31207 +
31208 +/* For GTA01 */
31209 +#include <mach/gta01.h>
31210 +#include <linux/pcf50606.h>
31211 +
31212 +/* For GTA02 */
31213 +#include <mach/gta02.h>
31214 +
31215 +#include <linux/regulator/consumer.h>
31216 +
31217 +struct neo1973_pm_gps_data {
31218 +       int power_was_on;
31219 +       struct regulator *regulator;
31220 +};
31221 +
31222 +static struct neo1973_pm_gps_data neo1973_gps;
31223 +
31224 +int neo1973_pm_gps_is_on(void)
31225 +{
31226 +       return neo1973_gps.power_was_on;
31227 +}
31228 +EXPORT_SYMBOL_GPL(neo1973_pm_gps_is_on);
31229 +
31230 +#ifdef CONFIG_MACH_NEO1973_GTA01
31231 +
31232 +/* This is the 2.8V supply for the RTC crystal, the mail clock crystal and
31233 + * the input to VDD_RF */
31234 +static void gps_power_2v8_set(int on)
31235 +{
31236 +       switch (system_rev) {
31237 +       case GTA01v3_SYSTEM_REV:
31238 +       case GTA01v4_SYSTEM_REV:
31239 +               if (on)
31240 +                       pcf50606_voltage_set(pcf50606_global,
31241 +                                            PCF50606_REGULATOR_IOREG, 2800);
31242 +               pcf50606_onoff_set(pcf50606_global,
31243 +                                  PCF50606_REGULATOR_IOREG, on);
31244 +               break;
31245 +       case GTA01Bv2_SYSTEM_REV:
31246 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_2V8, on);
31247 +                       break;
31248 +       case GTA01Bv3_SYSTEM_REV:
31249 +       case GTA01Bv4_SYSTEM_REV:
31250 +               break;
31251 +       }
31252 +}
31253 +
31254 +static int gps_power_2v8_get(void)
31255 +{
31256 +       int ret = 0;
31257 +
31258 +       switch (system_rev) {
31259 +       case GTA01v3_SYSTEM_REV:
31260 +       case GTA01v4_SYSTEM_REV:
31261 +               if (pcf50606_onoff_get(pcf50606_global,
31262 +                                       PCF50606_REGULATOR_IOREG) &&
31263 +                   pcf50606_voltage_get(pcf50606_global,
31264 +                                        PCF50606_REGULATOR_IOREG) == 2800)
31265 +                       ret = 1;
31266 +               break;
31267 +       case GTA01Bv2_SYSTEM_REV:
31268 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_2V8))
31269 +                       ret = 1;
31270 +               break;
31271 +       case GTA01Bv3_SYSTEM_REV:
31272 +       case GTA01Bv4_SYSTEM_REV:
31273 +               break;
31274 +       }
31275 +
31276 +       return ret;
31277 +}
31278 +
31279 +/* This is the 3V supply (AVDD) for the external RF frontend (LNA bias) */
31280 +static void gps_power_3v_set(int on)
31281 +{
31282 +       switch (system_rev) {
31283 +       case GTA01v3_SYSTEM_REV:
31284 +       case GTA01v4_SYSTEM_REV:
31285 +               if (on)
31286 +                       pcf50606_voltage_set(pcf50606_global,
31287 +                                            PCF50606_REGULATOR_D1REG, 3000);
31288 +               pcf50606_onoff_set(pcf50606_global,
31289 +                                  PCF50606_REGULATOR_D1REG, on);
31290 +               break;
31291 +       case GTA01Bv2_SYSTEM_REV:
31292 +       case GTA01Bv3_SYSTEM_REV:
31293 +       case GTA01Bv4_SYSTEM_REV:
31294 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_3V, on);
31295 +               break;
31296 +       }
31297 +}
31298 +
31299 +static int gps_power_3v_get(void)
31300 +{
31301 +       int ret = 0;
31302 +
31303 +       switch (system_rev) {
31304 +       case GTA01v3_SYSTEM_REV:
31305 +       case GTA01v4_SYSTEM_REV:
31306 +               if (pcf50606_onoff_get(pcf50606_global,
31307 +                                      PCF50606_REGULATOR_D1REG) &&
31308 +                   pcf50606_voltage_get(pcf50606_global,
31309 +                                        PCF50606_REGULATOR_D1REG) == 3000)
31310 +                       ret = 1;
31311 +               break;
31312 +       case GTA01Bv2_SYSTEM_REV:
31313 +       case GTA01Bv3_SYSTEM_REV:
31314 +       case GTA01Bv4_SYSTEM_REV:
31315 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_3V))
31316 +                       ret = 1;
31317 +               break;
31318 +       }
31319 +
31320 +       return ret;
31321 +}
31322 +
31323 +/* This is the 3.3V supply for VDD_IO and VDD_LPREG input */
31324 +static void gps_power_3v3_set(int on)
31325 +{
31326 +       switch (system_rev) {
31327 +       case GTA01v3_SYSTEM_REV:
31328 +       case GTA01v4_SYSTEM_REV:
31329 +       case GTA01Bv2_SYSTEM_REV:
31330 +               if (on)
31331 +                       pcf50606_voltage_set(pcf50606_global,
31332 +                                            PCF50606_REGULATOR_DCD, 3300);
31333 +               pcf50606_onoff_set(pcf50606_global,
31334 +                                  PCF50606_REGULATOR_DCD, on);
31335 +               break;
31336 +       case GTA01Bv3_SYSTEM_REV:
31337 +       case GTA01Bv4_SYSTEM_REV:
31338 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_3V3, on);
31339 +               break;
31340 +       }
31341 +}
31342 +
31343 +static int gps_power_3v3_get(void)
31344 +{
31345 +       int ret = 0;
31346 +
31347 +       switch (system_rev) {
31348 +       case GTA01v3_SYSTEM_REV:
31349 +       case GTA01v4_SYSTEM_REV:
31350 +       case GTA01Bv2_SYSTEM_REV:
31351 +               if (pcf50606_onoff_get(pcf50606_global,
31352 +                                      PCF50606_REGULATOR_DCD) &&
31353 +                   pcf50606_voltage_get(pcf50606_global,
31354 +                                        PCF50606_REGULATOR_DCD) == 3300)
31355 +                       ret = 1;
31356 +               break;
31357 +       case GTA01Bv3_SYSTEM_REV:
31358 +       case GTA01Bv4_SYSTEM_REV:
31359 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_3V3))
31360 +                       ret = 1;
31361 +               break;
31362 +       }
31363 +
31364 +       return ret;
31365 +}
31366 +
31367 +/* This is the 2.5V supply for VDD_PLLREG and VDD_COREREG input */
31368 +static void gps_power_2v5_set(int on)
31369 +{
31370 +       switch (system_rev) {
31371 +       case GTA01v3_SYSTEM_REV:
31372 +               /* This is CORE_1V8 and cannot be disabled */
31373 +               break;
31374 +       case GTA01v4_SYSTEM_REV:
31375 +       case GTA01Bv2_SYSTEM_REV:
31376 +       case GTA01Bv3_SYSTEM_REV:
31377 +       case GTA01Bv4_SYSTEM_REV:
31378 +               if (on)
31379 +                       pcf50606_voltage_set(pcf50606_global,
31380 +                                            PCF50606_REGULATOR_D2REG, 2500);
31381 +               pcf50606_onoff_set(pcf50606_global,
31382 +                                  PCF50606_REGULATOR_D2REG, on);
31383 +               break;
31384 +       }
31385 +}
31386 +
31387 +static int gps_power_2v5_get(void)
31388 +{
31389 +       int ret = 0;
31390 +
31391 +       switch (system_rev) {
31392 +       case GTA01v3_SYSTEM_REV:
31393 +               /* This is CORE_1V8 and cannot be disabled */
31394 +               ret = 1;
31395 +               break;
31396 +       case GTA01v4_SYSTEM_REV:
31397 +       case GTA01Bv2_SYSTEM_REV:
31398 +       case GTA01Bv3_SYSTEM_REV:
31399 +       case GTA01Bv4_SYSTEM_REV:
31400 +               if (pcf50606_onoff_get(pcf50606_global,
31401 +                                      PCF50606_REGULATOR_D2REG) &&
31402 +                   pcf50606_voltage_get(pcf50606_global,
31403 +                                        PCF50606_REGULATOR_D2REG) == 2500)
31404 +                       ret = 1;
31405 +               break;
31406 +       }
31407 +
31408 +       return ret;
31409 +}
31410 +
31411 +/* This is the 1.5V supply for VDD_CORE */
31412 +static void gps_power_1v5_set(int on)
31413 +{
31414 +       switch (system_rev) {
31415 +       case GTA01v3_SYSTEM_REV:
31416 +       case GTA01v4_SYSTEM_REV:
31417 +       case GTA01Bv2_SYSTEM_REV:
31418 +               /* This is switched via 2v5 */
31419 +               break;
31420 +       case GTA01Bv3_SYSTEM_REV:
31421 +       case GTA01Bv4_SYSTEM_REV:
31422 +               if (on)
31423 +                       pcf50606_voltage_set(pcf50606_global,
31424 +                                            PCF50606_REGULATOR_DCD, 1500);
31425 +               pcf50606_onoff_set(pcf50606_global,
31426 +                                  PCF50606_REGULATOR_DCD, on);
31427 +               break;
31428 +       }
31429 +}
31430 +
31431 +static int gps_power_1v5_get(void)
31432 +{
31433 +       int ret = 0;
31434 +
31435 +       switch (system_rev) {
31436 +       case GTA01v3_SYSTEM_REV:
31437 +       case GTA01v4_SYSTEM_REV:
31438 +       case GTA01Bv2_SYSTEM_REV:
31439 +               /* This is switched via 2v5 */
31440 +               ret = 1;
31441 +               break;
31442 +       case GTA01Bv3_SYSTEM_REV:
31443 +       case GTA01Bv4_SYSTEM_REV:
31444 +               if (pcf50606_onoff_get(pcf50606_global,
31445 +                                      PCF50606_REGULATOR_DCD) &&
31446 +                   pcf50606_voltage_get(pcf50606_global,
31447 +                                        PCF50606_REGULATOR_DCD) == 1500)
31448 +                       ret = 1;
31449 +               break;
31450 +       }
31451 +
31452 +       return ret;
31453 +}
31454 +#endif
31455 +
31456 +/* This is the POWERON pin */
31457 +static void gps_pwron_set(int on)
31458 +{
31459 +
31460 +       if (machine_is_neo1973_gta01())
31461 +               neo1973_gpb_setpin(GTA01_GPIO_GPS_PWRON, on);
31462 +
31463 +       if (machine_is_neo1973_gta02()) {
31464 +               if (on) {
31465 +                       /* return UART pins to being UART pins */
31466 +                       s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_TXD1);
31467 +                       /* remove pulldown now it won't be floating any more */
31468 +                       s3c2410_gpio_pullup(S3C2410_GPH5, 0);
31469 +               } else {
31470 +                       /*
31471 +                        * take care not to power unpowered GPS from UART TX
31472 +                        * return them to GPIO and force low
31473 +                        */
31474 +                       s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_OUTP);
31475 +                       s3c2410_gpio_setpin(S3C2410_GPH4, 0);
31476 +                       /* don't let RX from unpowered GPS float */
31477 +                       s3c2410_gpio_pullup(S3C2410_GPH5, 1);
31478 +               }
31479 +               if ((on) && (!neo1973_gps.power_was_on))
31480 +                       regulator_enable(neo1973_gps.regulator);
31481 +
31482 +               if ((!on) && (neo1973_gps.power_was_on))
31483 +                       regulator_disable(neo1973_gps.regulator);
31484 +       }
31485 +
31486 +       neo1973_gps.power_was_on = !!on;
31487 +}
31488 +
31489 +static int gps_pwron_get(void)
31490 +{
31491 +       if (machine_is_neo1973_gta01())
31492 +               return !!s3c2410_gpio_getpin(GTA01_GPIO_GPS_PWRON);
31493 +
31494 +       if (machine_is_neo1973_gta02())
31495 +               return regulator_is_enabled(neo1973_gps.regulator);
31496 +       return -1;
31497 +}
31498 +
31499 +
31500 +#ifdef CONFIG_MACH_NEO1973_GTA01
31501 +static void gps_rst_set(int on);
31502 +static int gps_rst_get(void);
31503 +#endif
31504 +
31505 +static ssize_t power_gps_read(struct device *dev,
31506 +                             struct device_attribute *attr, char *buf)
31507 +{
31508 +       int ret = 0;
31509 +
31510 +       if (!strcmp(attr->attr.name, "pwron"))
31511 +#ifdef CONFIG_MACH_NEO1973_GTA01
31512 +       {
31513 +#endif
31514 +               ret = gps_pwron_get();
31515 +#ifdef CONFIG_MACH_NEO1973_GTA01
31516 +       } else if (!strcmp(attr->attr.name, "power_avdd_3v")) {
31517 +               ret = gps_power_3v_get();
31518 +       } else if (!strcmp(attr->attr.name, "power_tcxo_2v8")) {
31519 +               ret = gps_power_2v8_get();
31520 +       } else if (!strcmp(attr->attr.name, "reset")) {
31521 +               ret = gps_rst_get();
31522 +       } else if (!strcmp(attr->attr.name, "power_lp_io_3v3")) {
31523 +               ret = gps_power_3v3_get();
31524 +       } else if (!strcmp(attr->attr.name, "power_pll_core_2v5")) {
31525 +               ret = gps_power_2v5_get();
31526 +       } else if (!strcmp(attr->attr.name, "power_core_1v5") ||
31527 +                  !strcmp(attr->attr.name, "power_vdd_core_1v5")) {
31528 +               ret = gps_power_1v5_get();
31529 +       }
31530 +#endif
31531 +       if (ret)
31532 +               return strlcpy(buf, "1\n", 3);
31533 +       else
31534 +               return strlcpy(buf, "0\n", 3);
31535 +}
31536 +
31537 +static ssize_t power_gps_write(struct device *dev,
31538 +                              struct device_attribute *attr, const char *buf,
31539 +                              size_t count)
31540 +{
31541 +       unsigned long on = simple_strtoul(buf, NULL, 10);
31542 +
31543 +       if (!strcmp(attr->attr.name, "pwron"))
31544 +#ifdef CONFIG_MACH_NEO1973_GTA01
31545 +{
31546 +#endif
31547 +               gps_pwron_set(on);
31548 +#ifdef CONFIG_MACH_NEO1973_GTA01
31549 +       } else if (!strcmp(attr->attr.name, "power_avdd_3v")) {
31550 +               gps_power_3v_set(on);
31551 +       } else if (!strcmp(attr->attr.name, "power_tcxo_2v8")) {
31552 +               gps_power_2v8_set(on);
31553 +       } else if (!strcmp(attr->attr.name, "reset")) {
31554 +               gps_rst_set(on);
31555 +       } else if (!strcmp(attr->attr.name, "power_lp_io_3v3")) {
31556 +               gps_power_3v3_set(on);
31557 +       } else if (!strcmp(attr->attr.name, "power_pll_core_2v5")) {
31558 +               gps_power_2v5_set(on);
31559 +       } else if (!strcmp(attr->attr.name, "power_core_1v5") ||
31560 +                  !strcmp(attr->attr.name, "power_vdd_core_1v5")) {
31561 +               gps_power_1v5_set(on);
31562 +       }
31563 +#endif
31564 +       return count;
31565 +}
31566 +
31567 +
31568 +#ifdef CONFIG_MACH_NEO1973_GTA01
31569 +
31570 +/* This is the nRESET pin */
31571 +static void gps_rst_set(int on)
31572 +{
31573 +       switch (system_rev) {
31574 +       case GTA01v3_SYSTEM_REV:
31575 +               pcf50606_gpo0_set(pcf50606_global, on);
31576 +               break;
31577 +       case GTA01v4_SYSTEM_REV:
31578 +       case GTA01Bv2_SYSTEM_REV:
31579 +       case GTA01Bv3_SYSTEM_REV:
31580 +       case GTA01Bv4_SYSTEM_REV:
31581 +               s3c2410_gpio_setpin(GTA01_GPIO_GPS_RESET, on);
31582 +               break;
31583 +       }
31584 +}
31585 +
31586 +static int gps_rst_get(void)
31587 +{
31588 +       switch (system_rev) {
31589 +       case GTA01v3_SYSTEM_REV:
31590 +               if (pcf50606_gpo0_get(pcf50606_global))
31591 +                       return 1;
31592 +               break;
31593 +       case GTA01v4_SYSTEM_REV:
31594 +       case GTA01Bv2_SYSTEM_REV:
31595 +       case GTA01Bv3_SYSTEM_REV:
31596 +       case GTA01Bv4_SYSTEM_REV:
31597 +               if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_RESET))
31598 +                       return 1;
31599 +               break;
31600 +       }
31601 +
31602 +       return 0;
31603 +}
31604 +
31605 +
31606 +static void gps_power_sequence_up(void)
31607 +{
31608 +       /* According to PMB2520 Data Sheet, Rev. 2006-06-05,
31609 +        * Chapter 4.2.2 */
31610 +
31611 +       /* nRESET must be asserted low */
31612 +       gps_rst_set(0);
31613 +
31614 +       /* POWERON must be de-asserted (low) */
31615 +       gps_pwron_set(0);
31616 +
31617 +       /* Apply VDD_IO and VDD_LPREG_IN */
31618 +       gps_power_3v3_set(1);
31619 +
31620 +       /* VDD_COREREG_IN, VDD_PLLREG_IN */
31621 +       gps_power_1v5_set(1);
31622 +       gps_power_2v5_set(1);
31623 +
31624 +       /* and VDD_RF may be applied */
31625 +       gps_power_2v8_set(1);
31626 +
31627 +       /* We need to enable AVDD, since in GTA01Bv3 it is
31628 +        * shared with RFREG_IN */
31629 +       gps_power_3v_set(1);
31630 +
31631 +       msleep(3);      /* Is 3ms enough? */
31632 +
31633 +       /* De-asert nRESET */
31634 +       gps_rst_set(1);
31635 +
31636 +       /* Switch power on */
31637 +       gps_pwron_set(1);
31638 +
31639 +}
31640 +
31641 +static void gps_power_sequence_down(void)
31642 +{
31643 +       /* According to PMB2520 Data Sheet, Rev. 2006-06-05,
31644 +        * Chapter 4.2.3.1 */
31645 +       gps_pwron_set(0);
31646 +
31647 +       /* Don't disable AVDD before PWRON is cleared, since
31648 +        * in GTA01Bv3, AVDD and RFREG_IN are shared */
31649 +       gps_power_3v_set(0);
31650 +
31651 +       /* Remove VDD_COREREG_IN, VDD_PLLREG_IN and VDD_REFREG_IN */
31652 +       gps_power_1v5_set(0);
31653 +       gps_power_2v5_set(0);
31654 +       gps_power_2v8_set(0);
31655 +
31656 +       /* Remove VDD_LPREG_IN and VDD_IO */
31657 +       gps_power_3v3_set(0);
31658 +}
31659 +
31660 +
31661 +static ssize_t power_sequence_read(struct device *dev,
31662 +                                  struct device_attribute *attr,
31663 +                                  char *buf)
31664 +{
31665 +       return strlcpy(buf, "power_up power_down\n", PAGE_SIZE);
31666 +}
31667 +
31668 +static ssize_t power_sequence_write(struct device *dev,
31669 +                                   struct device_attribute *attr,
31670 +                                   const char *buf, size_t count)
31671 +{
31672 +       dev_dbg(dev, "wrote: '%s'\n", buf);
31673 +
31674 +       if (!strncmp(buf, "power_up", 8))
31675 +               gps_power_sequence_up();
31676 +       else if (!strncmp(buf, "power_down", 10))
31677 +               gps_power_sequence_down();
31678 +       else
31679 +               return -EINVAL;
31680 +
31681 +       return count;
31682 +}
31683 +
31684 +static DEVICE_ATTR(power_tcxo_2v8, 0644, power_gps_read, power_gps_write);
31685 +static DEVICE_ATTR(power_avdd_3v, 0644, power_gps_read, power_gps_write);
31686 +static DEVICE_ATTR(reset, 0644, power_gps_read, power_gps_write);
31687 +static DEVICE_ATTR(power_lp_io_3v3, 0644, power_gps_read, power_gps_write);
31688 +static DEVICE_ATTR(power_pll_core_2v5, 0644, power_gps_read, power_gps_write);
31689 +static DEVICE_ATTR(power_core_1v5, 0644, power_gps_read, power_gps_write);
31690 +static DEVICE_ATTR(power_vdd_core_1v5, 0644, power_gps_read, power_gps_write);
31691 +static DEVICE_ATTR(power_sequence, 0644, power_sequence_read,
31692 +                  power_sequence_write);
31693 +#endif
31694 +
31695 +#ifdef CONFIG_PM
31696 +static int gta01_pm_gps_suspend(struct platform_device *pdev,
31697 +                               pm_message_t state)
31698 +{
31699 +#ifdef CONFIG_MACH_NEO1973_GTA01
31700 +       if (machine_is_neo1973_gta01())
31701 +               /* FIXME */
31702 +               gps_power_sequence_down();
31703 +#endif
31704 +       if (machine_is_neo1973_gta02())
31705 +               gps_pwron_set(0);
31706 +
31707 +       return 0;
31708 +}
31709 +
31710 +static int gta01_pm_gps_resume(struct platform_device *pdev)
31711 +{
31712 +#ifdef CONFIG_MACH_NEO1973_GTA01
31713 +       if (machine_is_neo1973_gta01())
31714 +               if (neo1973_gps.power_was_on)
31715 +                       gps_power_sequence_up();
31716 +#endif
31717 +       if (machine_is_neo1973_gta02())
31718 +               if (neo1973_gps.power_was_on)
31719 +                   gps_pwron_set(1);
31720 +
31721 +       return 0;
31722 +}
31723 +#else
31724 +#define gta01_pm_gps_suspend   NULL
31725 +#define gta01_pm_gps_resume    NULL
31726 +#endif
31727 +
31728 +static DEVICE_ATTR(pwron, 0644, power_gps_read, power_gps_write);
31729 +
31730 +
31731 +static struct attribute *gta01_gps_sysfs_entries[] = {
31732 +       &dev_attr_pwron.attr,
31733 +#ifdef CONFIG_MACH_NEO1973_GTA01
31734 +       &dev_attr_power_avdd_3v.attr,
31735 +       &dev_attr_reset.attr,
31736 +       &dev_attr_power_lp_io_3v3.attr,
31737 +       &dev_attr_power_pll_core_2v5.attr,
31738 +       &dev_attr_power_sequence.attr,
31739 +       NULL,   /* power_core_1v5 */
31740 +       NULL,   /* power_vdd_core_1v5 */
31741 +#endif
31742 +       NULL    /* terminating entry */
31743 +};
31744 +
31745 +static struct attribute_group gta01_gps_attr_group = {
31746 +       .name   = NULL,
31747 +       .attrs  = gta01_gps_sysfs_entries,
31748 +};
31749 +
31750 +static struct attribute *gta02_gps_sysfs_entries[] = {
31751 +       &dev_attr_pwron.attr,
31752 +       NULL
31753 +};
31754 +
31755 +static struct attribute_group gta02_gps_attr_group = {
31756 +       .name   = NULL,
31757 +       .attrs  = gta02_gps_sysfs_entries,
31758 +};
31759 +
31760 +static int __init gta01_pm_gps_probe(struct platform_device *pdev)
31761 +{
31762 +       if (machine_is_neo1973_gta01()) {
31763 +               s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_PWRON, S3C2410_GPIO_OUTPUT);
31764 +
31765 +               switch (system_rev) {
31766 +               case GTA01v3_SYSTEM_REV:
31767 +                       break;
31768 +               case GTA01v4_SYSTEM_REV:
31769 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_RESET, S3C2410_GPIO_OUTPUT);
31770 +                       break;
31771 +               case GTA01Bv3_SYSTEM_REV:
31772 +               case GTA01Bv4_SYSTEM_REV:
31773 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_3V3, S3C2410_GPIO_OUTPUT);
31774 +                       /* fallthrough */
31775 +               case GTA01Bv2_SYSTEM_REV:
31776 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_2V8, S3C2410_GPIO_OUTPUT);
31777 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_3V, S3C2410_GPIO_OUTPUT);
31778 +                       s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_RESET, S3C2410_GPIO_OUTPUT);
31779 +                       break;
31780 +               default:
31781 +                       dev_warn(&pdev->dev, "Unknown GTA01 Revision 0x%x, "
31782 +                               "AGPS PM features not available!!!\n",
31783 +                               system_rev);
31784 +                       return -1;
31785 +                       break;
31786 +               }
31787 +
31788 +#ifdef CONFIG_MACH_NEO1973_GTA01
31789 +               gps_power_sequence_down();
31790 +
31791 +               switch (system_rev) {
31792 +               case GTA01v3_SYSTEM_REV:
31793 +               case GTA01v4_SYSTEM_REV:
31794 +               case GTA01Bv2_SYSTEM_REV:
31795 +                       gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-3] =
31796 +                                               &dev_attr_power_tcxo_2v8.attr;
31797 +                       break;
31798 +               case GTA01Bv3_SYSTEM_REV:
31799 +               case GTA01Bv4_SYSTEM_REV:
31800 +                       gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-3] =
31801 +                                               &dev_attr_power_core_1v5.attr;
31802 +                       gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-2] =
31803 +                                               &dev_attr_power_vdd_core_1v5.attr;
31804 +                       break;
31805 +               }
31806 +#endif
31807 +               return sysfs_create_group(&pdev->dev.kobj, &gta01_gps_attr_group);
31808 +       }
31809 +
31810 +       if (machine_is_neo1973_gta02()) {
31811 +               switch (system_rev) {
31812 +               case GTA02v2_SYSTEM_REV:
31813 +               case GTA02v3_SYSTEM_REV:
31814 +               case GTA02v4_SYSTEM_REV:
31815 +               case GTA02v5_SYSTEM_REV:
31816 +               case GTA02v6_SYSTEM_REV:
31817 +                       neo1973_gps.regulator = regulator_get(
31818 +                                                       &pdev->dev, "RF_3V");
31819 +                       if (IS_ERR(neo1973_gps.regulator)) {
31820 +                               dev_err(&pdev->dev, "probe failed %d\n",
31821 +                                                   (int)neo1973_gps.regulator);
31822 +                               return (int)neo1973_gps.regulator;
31823 +                       }
31824 +
31825 +                       dev_info(&pdev->dev, "FIC Neo1973 GPS Power Management:"
31826 +                                "starting\n");
31827 +                       break;
31828 +               default:
31829 +                       dev_warn(&pdev->dev, "Unknown GTA02 Revision 0x%x, "
31830 +                               "AGPS PM features not available!!!\n",
31831 +                               system_rev);
31832 +                       return -1;
31833 +                       break;
31834 +               }
31835 +               return sysfs_create_group(&pdev->dev.kobj, &gta02_gps_attr_group);
31836 +       }
31837 +       return -1;
31838 +}
31839 +
31840 +static int gta01_pm_gps_remove(struct platform_device *pdev)
31841 +{
31842 +       if (machine_is_neo1973_gta01()) {
31843 +#ifdef CONFIG_MACH_NEO1973_GTA01
31844 +               gps_power_sequence_down();
31845 +#endif
31846 +               sysfs_remove_group(&pdev->dev.kobj, &gta01_gps_attr_group);
31847 +       }
31848 +
31849 +       if (machine_is_neo1973_gta02()) {
31850 +               regulator_put(neo1973_gps.regulator);
31851 +               sysfs_remove_group(&pdev->dev.kobj, &gta02_gps_attr_group);
31852 +       }
31853 +       return 0;
31854 +}
31855 +
31856 +static struct platform_driver gta01_pm_gps_driver = {
31857 +       .probe          = gta01_pm_gps_probe,
31858 +       .remove         = gta01_pm_gps_remove,
31859 +       .suspend        = gta01_pm_gps_suspend,
31860 +       .resume         = gta01_pm_gps_resume,
31861 +       .driver         = {
31862 +               .name           = "neo1973-pm-gps",
31863 +       },
31864 +};
31865 +
31866 +static int __devinit gta01_pm_gps_init(void)
31867 +{
31868 +       return platform_driver_register(&gta01_pm_gps_driver);
31869 +}
31870 +
31871 +static void gta01_pm_gps_exit(void)
31872 +{
31873 +       platform_driver_unregister(&gta01_pm_gps_driver);
31874 +}
31875 +
31876 +module_init(gta01_pm_gps_init);
31877 +module_exit(gta01_pm_gps_exit);
31878 +
31879 +MODULE_LICENSE("GPL");
31880 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
31881 +MODULE_DESCRIPTION("FIC Neo1973 GPS Power Management");
31882 Index: linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_gps.h
31883 ===================================================================
31884 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
31885 +++ linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_gps.h 2009-01-02 00:01:56.000000000 +0100
31886 @@ -0,0 +1 @@
31887 +extern int neo1973_pm_gps_is_on(void);
31888 Index: linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_gsm.c
31889 ===================================================================
31890 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
31891 +++ linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_pm_gsm.c 2009-01-02 00:01:56.000000000 +0100
31892 @@ -0,0 +1,360 @@
31893 +/*
31894 + * GSM Management code for the FIC Neo1973 GSM Phone
31895 + *
31896 + * (C) 2007 by Openmoko Inc.
31897 + * Author: Harald Welte <laforge@openmoko.org>
31898 + * All rights reserved.
31899 + *
31900 + * This program is free software; you can redistribute it and/or modify
31901 + * it under the terms of the GNU General Public License version 2 as
31902 + * published by the Free Software Foundation
31903 + *
31904 + */
31905 +
31906 +#include <linux/module.h>
31907 +#include <linux/init.h>
31908 +#include <linux/kernel.h>
31909 +#include <linux/platform_device.h>
31910 +#include <linux/console.h>
31911 +#include <linux/errno.h>
31912 +#include <linux/interrupt.h>
31913 +
31914 +#include <mach/gpio.h>
31915 +#include <asm/mach-types.h>
31916 +#include <mach/gta01.h>
31917 +#include <asm/plat-s3c24xx/neo1973.h>
31918 +#include <mach/s3c24xx-serial.h>
31919 +
31920 +#include <mach/hardware.h>
31921 +
31922 +/* For GTA02 */
31923 +#include <mach/gta02.h>
31924 +#include <linux/mfd/pcf50633/gpio.h>
31925 +#include <mach/regs-gpio.h>
31926 +#include <mach/regs-gpioj.h>
31927 +
31928 +int gta_gsm_interrupts;
31929 +EXPORT_SYMBOL(gta_gsm_interrupts);
31930 +
31931 +extern void s3c24xx_serial_console_set_silence(int);
31932 +
31933 +struct gta01pm_priv {
31934 +       int gpio_ngsm_en;
31935 +        int gpio_ndl_gsm;
31936 +
31937 +       struct console *con;
31938 +};
31939 +
31940 +static struct gta01pm_priv gta01_gsm;
31941 +
31942 +static struct console *find_s3c24xx_console(void)
31943 +{
31944 +       struct console *con;
31945 +
31946 +       acquire_console_sem();
31947 +
31948 +       for (con = console_drivers; con; con = con->next) {
31949 +               if (!strcmp(con->name, "ttySAC"))
31950 +                       break;
31951 +       }
31952 +
31953 +       release_console_sem();
31954 +
31955 +       return con;
31956 +}
31957 +
31958 +static ssize_t gsm_read(struct device *dev, struct device_attribute *attr,
31959 +                       char *buf)
31960 +{
31961 +       if (!strcmp(attr->attr.name, "power_on")) {
31962 +               if (s3c2410_gpio_getpin(GTA01_GPIO_MODEM_ON))
31963 +                       goto out_1;
31964 +       } else if (!strcmp(attr->attr.name, "reset")) {
31965 +               if (machine_is_neo1973_gta01() && s3c2410_gpio_getpin(GTA01_GPIO_MODEM_RST))
31966 +                       goto out_1;
31967 +               else if (machine_is_neo1973_gta02() && s3c2410_gpio_getpin(GTA02_GPIO_MODEM_RST))
31968 +                       goto out_1;
31969 +       } else if (!strcmp(attr->attr.name, "download")) {
31970 +               if (machine_is_neo1973_gta01()) {
31971 +                       if (s3c2410_gpio_getpin(GTA01_GPIO_MODEM_DNLOAD))
31972 +                               goto out_1;
31973 +               } else if (machine_is_neo1973_gta02()) {
31974 +                       if (!s3c2410_gpio_getpin(GTA02_GPIO_nDL_GSM))
31975 +                               goto out_1;
31976 +               }
31977 +       } else if (!strcmp(attr->attr.name, "flowcontrolled")) {
31978 +               if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT)
31979 +                       goto out_1;
31980 +       }
31981 +
31982 +       return strlcpy(buf, "0\n", 3);
31983 +out_1:
31984 +       return strlcpy(buf, "1\n", 3);
31985 +}
31986 +
31987 +static ssize_t gsm_write(struct device *dev, struct device_attribute *attr,
31988 +                        const char *buf, size_t count)
31989 +{
31990 +       unsigned long on = simple_strtoul(buf, NULL, 10);
31991 +
31992 +       if (!strcmp(attr->attr.name, "power_on")) {
31993 +               if (on) {
31994 +                       if (gta01_gsm.con) {
31995 +                               dev_dbg(dev, "powering up GSM, thus "
31996 +                                        "disconnecting serial console\n");
31997 +
31998 +                               console_stop(gta01_gsm.con);
31999 +                               s3c24xx_serial_console_set_silence(1);
32000 +                       }
32001 +
32002 +                       if (gta01_gsm.gpio_ngsm_en)
32003 +                               s3c2410_gpio_setpin(gta01_gsm.gpio_ngsm_en, 0);
32004 +
32005 +                       if (machine_is_neo1973_gta02()) {
32006 +                               switch (system_rev) {
32007 +                               case GTA02v2_SYSTEM_REV:
32008 +                               case GTA02v3_SYSTEM_REV:
32009 +                               case GTA02v4_SYSTEM_REV:
32010 +                               case GTA02v5_SYSTEM_REV:
32011 +                               case GTA02v6_SYSTEM_REV:
32012 +                                       pcf50633_gpio_set(gta02_pcf_pdata.pcf,
32013 +                                                         PCF50633_GPIO2, 1);
32014 +                                       break;
32015 +                               }
32016 +                       }
32017 +
32018 +                       neo1973_gpb_setpin(GTA01_GPIO_MODEM_ON, 1);
32019 +               } else {
32020 +                       neo1973_gpb_setpin(GTA01_GPIO_MODEM_ON, 0);
32021 +
32022 +                       if (machine_is_neo1973_gta02()) {
32023 +                               switch (system_rev) {
32024 +                               case GTA02v2_SYSTEM_REV:
32025 +                               case GTA02v3_SYSTEM_REV:
32026 +                               case GTA02v4_SYSTEM_REV:
32027 +                               case GTA02v5_SYSTEM_REV:
32028 +                               case GTA02v6_SYSTEM_REV:
32029 +                                       pcf50633_gpio_set(gta02_pcf_pdata.pcf,
32030 +                                                         PCF50633_GPIO2, 0);
32031 +                                       break;
32032 +                               }
32033 +                       }
32034 +
32035 +                       if (gta01_gsm.gpio_ngsm_en)
32036 +                               s3c2410_gpio_setpin(gta01_gsm.gpio_ngsm_en, 1);
32037 +
32038 +                       if (gta01_gsm.con) {
32039 +                               s3c24xx_serial_console_set_silence(0);
32040 +                               console_start(gta01_gsm.con);
32041 +
32042 +                               dev_dbg(dev, "powered down GSM, thus enabling "
32043 +                                        "serial console\n");
32044 +                       }
32045 +               }
32046 +       } else if (!strcmp(attr->attr.name, "reset")) {
32047 +               if (machine_is_neo1973_gta01())
32048 +                       neo1973_gpb_setpin(GTA01_GPIO_MODEM_RST, on);
32049 +               else if (machine_is_neo1973_gta02())
32050 +                       neo1973_gpb_setpin(GTA02_GPIO_MODEM_RST, on);
32051 +       } else if (!strcmp(attr->attr.name, "download")) {
32052 +               if (machine_is_neo1973_gta01())
32053 +                       s3c2410_gpio_setpin(GTA01_GPIO_MODEM_DNLOAD, on);
32054 +
32055 +               if (machine_is_neo1973_gta02()) {
32056 +                       /*
32057 +                        * the keyboard / buttons driver requests and enables
32058 +                        * the JACK_INSERT IRQ.  We have to take care about
32059 +                        * not enabling and disabling the IRQ when it was
32060 +                        * already in that state or we get "unblanaced IRQ"
32061 +                        * kernel warnings and stack dumps.  So we use the
32062 +                        * copy of the ndl_gsm state to figure out if we should
32063 +                        * enable or disable the jack interrupt
32064 +                        */
32065 +                       if (on) {
32066 +                               if (gta01_gsm.gpio_ndl_gsm)
32067 +                                       disable_irq(gpio_to_irq(
32068 +                                                      GTA02_GPIO_JACK_INSERT));
32069 +                       } else {
32070 +                               if (!gta01_gsm.gpio_ndl_gsm)
32071 +                                       enable_irq(gpio_to_irq(
32072 +                                                      GTA02_GPIO_JACK_INSERT));
32073 +                       }
32074 +
32075 +                       gta01_gsm.gpio_ndl_gsm = !on;
32076 +                       s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, !on);
32077 +               }
32078 +       } else if (!strcmp(attr->attr.name, "flowcontrolled")) {
32079 +               if (on) {
32080 +                       gta_gsm_interrupts = 0;
32081 +                       s3c2410_gpio_setpin(S3C2410_GPH1, 1);
32082 +                       s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP);
32083 +               } else
32084 +                       s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_nRTS0);
32085 +       }
32086 +
32087 +       return count;
32088 +}
32089 +
32090 +static DEVICE_ATTR(power_on, 0644, gsm_read, gsm_write);
32091 +static DEVICE_ATTR(reset, 0644, gsm_read, gsm_write);
32092 +static DEVICE_ATTR(download, 0644, gsm_read, gsm_write);
32093 +static DEVICE_ATTR(flowcontrolled, 0644, gsm_read, gsm_write);
32094 +
32095 +#ifdef CONFIG_PM
32096 +
32097 +static int gta01_gsm_resume(struct platform_device *pdev);
32098 +static int gta01_gsm_suspend(struct platform_device *pdev, pm_message_t state)
32099 +{
32100 +       /* GPIO state is saved/restored by S3C2410 core GPIO driver, so we
32101 +        * don't need to do much here. */
32102 +
32103 +       /* If flowcontrol asserted, abort if GSM already interrupted */
32104 +       if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT) {
32105 +               if (gta_gsm_interrupts)
32106 +                       goto busy;
32107 +       }
32108 +
32109 +       /* disable DL GSM to prevent jack_insert becoming 'floating' */
32110 +       if (machine_is_neo1973_gta02())
32111 +               s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, 1);
32112 +       return 0;
32113 +
32114 +busy:
32115 +       return -EBUSY;
32116 +}
32117 +
32118 +static int
32119 +gta01_gsm_suspend_late(struct platform_device *pdev, pm_message_t state)
32120 +{
32121 +       /* Last chance: abort if GSM already interrupted */
32122 +       if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT) {
32123 +               if (gta_gsm_interrupts)
32124 +                       return -EBUSY;
32125 +       }
32126 +       return 0;
32127 +}
32128 +
32129 +static int gta01_gsm_resume(struct platform_device *pdev)
32130 +{
32131 +       /* GPIO state is saved/restored by S3C2410 core GPIO driver, so we
32132 +        * don't need to do much here. */
32133 +
32134 +       /* Make sure that the kernel console on the serial port is still
32135 +        * disabled. FIXME: resume ordering race with serial driver! */
32136 +       if (gta01_gsm.con && s3c2410_gpio_getpin(GTA01_GPIO_MODEM_ON))
32137 +               console_stop(gta01_gsm.con);
32138 +
32139 +       if (machine_is_neo1973_gta02())
32140 +               s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, gta01_gsm.gpio_ndl_gsm);
32141 +
32142 +       return 0;
32143 +}
32144 +#else
32145 +#define gta01_gsm_suspend      NULL
32146 +#define gta01_gsm_suspend_late NULL
32147 +#define gta01_gsm_resume       NULL
32148 +#endif /* CONFIG_PM */
32149 +
32150 +static struct attribute *gta01_gsm_sysfs_entries[] = {
32151 +       &dev_attr_power_on.attr,
32152 +       &dev_attr_reset.attr,
32153 +       &dev_attr_download.attr,
32154 +       &dev_attr_flowcontrolled.attr,
32155 +       NULL
32156 +};
32157 +
32158 +static struct attribute_group gta01_gsm_attr_group = {
32159 +       .name   = NULL,
32160 +       .attrs  = gta01_gsm_sysfs_entries,
32161 +};
32162 +
32163 +static int __init gta01_gsm_probe(struct platform_device *pdev)
32164 +{
32165 +       switch (system_rev) {
32166 +       case GTA01v3_SYSTEM_REV:
32167 +               gta01_gsm.gpio_ngsm_en = GTA01v3_GPIO_nGSM_EN;
32168 +               break;
32169 +       case GTA01v4_SYSTEM_REV:
32170 +               gta01_gsm.gpio_ngsm_en = 0;
32171 +               break;
32172 +       case GTA01Bv2_SYSTEM_REV:
32173 +       case GTA01Bv3_SYSTEM_REV:
32174 +       case GTA01Bv4_SYSTEM_REV:
32175 +               gta01_gsm.gpio_ngsm_en = GTA01Bv2_GPIO_nGSM_EN;
32176 +               s3c2410_gpio_setpin(GTA01v3_GPIO_nGSM_EN, 0);
32177 +               break;
32178 +       case GTA02v1_SYSTEM_REV:
32179 +       case GTA02v2_SYSTEM_REV:
32180 +       case GTA02v3_SYSTEM_REV:
32181 +       case GTA02v4_SYSTEM_REV:
32182 +       case GTA02v5_SYSTEM_REV:
32183 +       case GTA02v6_SYSTEM_REV:
32184 +               gta01_gsm.gpio_ngsm_en = 0;
32185 +               break;
32186 +       default:
32187 +               dev_warn(&pdev->dev, "Unknown Neo1973 Revision 0x%x, "
32188 +                        "some PM features not available!!!\n",
32189 +                        system_rev);
32190 +               break;
32191 +       }
32192 +
32193 +       switch (system_rev) {
32194 +       case GTA01v4_SYSTEM_REV:
32195 +       case GTA01Bv2_SYSTEM_REV:
32196 +               gta01_gsm_sysfs_entries[ARRAY_SIZE(gta01_gsm_sysfs_entries)-2] =
32197 +                                                       &dev_attr_download.attr;
32198 +               break;
32199 +       default:
32200 +               break;
32201 +       }
32202 +
32203 +       if (machine_is_neo1973_gta01()) {
32204 +               gta01_gsm.con = find_s3c24xx_console();
32205 +               if (!gta01_gsm.con)
32206 +                       dev_warn(&pdev->dev,
32207 +                                "cannot find S3C24xx console driver\n");
32208 +       } else
32209 +               gta01_gsm.con = NULL;
32210 +
32211 +       /* note that download initially disabled, and enforce that */
32212 +       gta01_gsm.gpio_ndl_gsm = 1;
32213 +       if (machine_is_neo1973_gta02())
32214 +               s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, 1);
32215 +
32216 +       return sysfs_create_group(&pdev->dev.kobj, &gta01_gsm_attr_group);
32217 +}
32218 +
32219 +static int gta01_gsm_remove(struct platform_device *pdev)
32220 +{
32221 +       sysfs_remove_group(&pdev->dev.kobj, &gta01_gsm_attr_group);
32222 +
32223 +       return 0;
32224 +}
32225 +
32226 +static struct platform_driver gta01_gsm_driver = {
32227 +       .probe          = gta01_gsm_probe,
32228 +       .remove         = gta01_gsm_remove,
32229 +       .suspend        = gta01_gsm_suspend,
32230 +       .suspend_late   = gta01_gsm_suspend_late,
32231 +       .resume         = gta01_gsm_resume,
32232 +       .driver         = {
32233 +               .name           = "neo1973-pm-gsm",
32234 +       },
32235 +};
32236 +
32237 +static int __devinit gta01_gsm_init(void)
32238 +{
32239 +       return platform_driver_register(&gta01_gsm_driver);
32240 +}
32241 +
32242 +static void gta01_gsm_exit(void)
32243 +{
32244 +       platform_driver_unregister(&gta01_gsm_driver);
32245 +}
32246 +
32247 +module_init(gta01_gsm_init);
32248 +module_exit(gta01_gsm_exit);
32249 +
32250 +MODULE_LICENSE("GPL");
32251 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
32252 +MODULE_DESCRIPTION("FIC Neo1973 GSM Power Management");
32253 Index: linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_shadow.c
32254 ===================================================================
32255 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
32256 +++ linux-2.6.28/arch/arm/plat-s3c24xx/neo1973_shadow.c 2009-01-02 00:01:56.000000000 +0100
32257 @@ -0,0 +1,88 @@
32258 +/*
32259 + * include/asm-arm/plat-s3c24xx/neo1973.h
32260 + *
32261 + * Common utility code for GTA01 and GTA02
32262 + *
32263 + * Copyright (C) 2008 by Openmoko, Inc.
32264 + * Author: Holger Hans Peter Freyther <freyther@openmoko.org>
32265 + * All rights reserved.
32266 + *
32267 + * This program is free software; you can redistribute it and/or
32268 + * modify it under the terms of the GNU General Public License as
32269 + * published by the Free Software Foundation; either version 2 of
32270 + * the License, or (at your option) any later version.
32271 + *
32272 + * This program is distributed in the hope that it will be useful,
32273 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
32274 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
32275 + * GNU General Public License for more details.
32276 + *
32277 + * You should have received a copy of the GNU General Public License
32278 + * along with this program; if not, write to the Free Software
32279 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32280 + * MA 02111-1307 USA
32281 + *
32282 + */
32283 +
32284 +#include <linux/module.h>
32285 +#include <linux/io.h>
32286 +#include <linux/irq.h>
32287 +
32288 +#include <asm/gpio.h>
32289 +#include <mach/regs-gpio.h>
32290 +#include <asm/plat-s3c24xx/neo1973.h>
32291 +
32292 +/**
32293 + * Shadow GPIO bank B handling. For the LEDs we need to keep track of the state
32294 + * in software. The s3c2410_gpio_setpin must not be used for GPIOs on bank B
32295 + */
32296 +static unsigned long gpb_mask;
32297 +static unsigned long gpb_state;
32298 +
32299 +void neo1973_gpb_add_shadow_gpio(unsigned int gpio)
32300 +{
32301 +       unsigned long offset = S3C2410_GPIO_OFFSET(gpio);
32302 +       unsigned long flags;
32303 +
32304 +       local_irq_save(flags);
32305 +       gpb_mask |= 1L << offset;
32306 +       local_irq_restore(flags);
32307 +}
32308 +EXPORT_SYMBOL(neo1973_gpb_add_shadow_gpio);
32309 +
32310 +static void set_shadow_gpio(unsigned long offset, unsigned int value)
32311 +{
32312 +       unsigned long state = value != 0;
32313 +
32314 +       gpb_state &= ~(1L << offset);
32315 +       gpb_state |= state << offset;
32316 +}
32317 +
32318 +void neo1973_gpb_setpin(unsigned int pin, unsigned to)
32319 +{
32320 +       void __iomem *base = S3C24XX_GPIO_BASE(S3C2410_GPB0);
32321 +       unsigned long offset = S3C2410_GPIO_OFFSET(pin);
32322 +       unsigned long flags;
32323 +       unsigned long dat;
32324 +
32325 +       BUG_ON(base != S3C24XX_GPIO_BASE(pin));
32326 +
32327 +       local_irq_save(flags);
32328 +       dat = __raw_readl(base + 0x04);
32329 +
32330 +       /* Add the shadow values */
32331 +       dat &= ~gpb_mask;
32332 +       dat |= gpb_state;
32333 +
32334 +       /* Do the operation like s3c2410_gpio_setpin */
32335 +       dat &= ~(1L << offset);
32336 +       dat |= to << offset;
32337 +
32338 +       /* Update the shadow state */
32339 +       if ((1L << offset) & gpb_mask)
32340 +               set_shadow_gpio(offset, to);
32341 +
32342 +       __raw_writel(dat, base + 0x04);
32343 +       local_irq_restore(flags);
32344 +}
32345 +EXPORT_SYMBOL(neo1973_gpb_setpin);
32346 Index: linux-2.6.28/arch/arm/plat-s3c24xx/pm.c
32347 ===================================================================
32348 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/pm.c        2008-12-25 00:26:37.000000000 +0100
32349 +++ linux-2.6.28/arch/arm/plat-s3c24xx/pm.c     2009-01-02 00:01:56.000000000 +0100
32350 @@ -31,14 +31,9 @@
32351  #include <linux/errno.h>
32352  #include <linux/time.h>
32353  #include <linux/interrupt.h>
32354 -#include <linux/crc32.h>
32355 -#include <linux/ioport.h>
32356 -#include <linux/delay.h>
32357  #include <linux/serial_core.h>
32358  #include <linux/io.h>
32359 -
32360 -#include <asm/cacheflush.h>
32361 -#include <mach/hardware.h>
32362 +#include <linux/regulator/machine.h>
32363
32364  #include <plat/regs-serial.h>
32365  #include <mach/regs-clock.h>
32366 @@ -50,10 +45,6 @@
32367
32368  #include <plat/pm.h>
32369
32370 -/* for external use */
32371 -
32372 -unsigned long s3c_pm_flags;
32373 -
32374  #define PFX "s3c24xx-pm: "
32375
32376  static struct sleep_save core_save[] = {
32377 @@ -76,371 +67,26 @@ static struct sleep_save core_save[] = {
32378         SAVE_ITEM(S3C2410_BANKCON4),
32379         SAVE_ITEM(S3C2410_BANKCON5),
32380
32381 +#ifndef CONFIG_CPU_FREQ
32382         SAVE_ITEM(S3C2410_CLKDIVN),
32383         SAVE_ITEM(S3C2410_MPLLCON),
32384 +       SAVE_ITEM(S3C2410_REFRESH),
32385 +#endif
32386         SAVE_ITEM(S3C2410_UPLLCON),
32387         SAVE_ITEM(S3C2410_CLKSLOW),
32388 -       SAVE_ITEM(S3C2410_REFRESH),
32389 -};
32390 -
32391 -static struct gpio_sleep {
32392 -       void __iomem    *base;
32393 -       unsigned int     gpcon;
32394 -       unsigned int     gpdat;
32395 -       unsigned int     gpup;
32396 -} gpio_save[] = {
32397 -       [0] = {
32398 -               .base   = S3C2410_GPACON,
32399 -       },
32400 -       [1] = {
32401 -               .base   = S3C2410_GPBCON,
32402 -       },
32403 -       [2] = {
32404 -               .base   = S3C2410_GPCCON,
32405 -       },
32406 -       [3] = {
32407 -               .base   = S3C2410_GPDCON,
32408 -       },
32409 -       [4] = {
32410 -               .base   = S3C2410_GPECON,
32411 -       },
32412 -       [5] = {
32413 -               .base   = S3C2410_GPFCON,
32414 -       },
32415 -       [6] = {
32416 -               .base   = S3C2410_GPGCON,
32417 -       },
32418 -       [7] = {
32419 -               .base   = S3C2410_GPHCON,
32420 -       },
32421  };
32422
32423  static struct sleep_save misc_save[] = {
32424         SAVE_ITEM(S3C2410_DCLKCON),
32425  };
32426
32427 -#ifdef CONFIG_S3C2410_PM_DEBUG
32428 -
32429 -#define SAVE_UART(va) \
32430 -       SAVE_ITEM((va) + S3C2410_ULCON), \
32431 -       SAVE_ITEM((va) + S3C2410_UCON), \
32432 -       SAVE_ITEM((va) + S3C2410_UFCON), \
32433 -       SAVE_ITEM((va) + S3C2410_UMCON), \
32434 -       SAVE_ITEM((va) + S3C2410_UBRDIV)
32435 -
32436 -static struct sleep_save uart_save[] = {
32437 -       SAVE_UART(S3C24XX_VA_UART0),
32438 -       SAVE_UART(S3C24XX_VA_UART1),
32439 -#ifndef CONFIG_CPU_S3C2400
32440 -       SAVE_UART(S3C24XX_VA_UART2),
32441 -#endif
32442 -};
32443 -
32444 -/* debug
32445 - *
32446 - * we send the debug to printascii() to allow it to be seen if the
32447 - * system never wakes up from the sleep
32448 -*/
32449 -
32450 -extern void printascii(const char *);
32451 -
32452 -void pm_dbg(const char *fmt, ...)
32453 -{
32454 -       va_list va;
32455 -       char buff[256];
32456 -
32457 -       va_start(va, fmt);
32458 -       vsprintf(buff, fmt, va);
32459 -       va_end(va);
32460 -
32461 -       printascii(buff);
32462 -}
32463 -
32464 -static void s3c2410_pm_debug_init(void)
32465 -{
32466 -       unsigned long tmp = __raw_readl(S3C2410_CLKCON);
32467 -
32468 -       /* re-start uart clocks */
32469 -       tmp |= S3C2410_CLKCON_UART0;
32470 -       tmp |= S3C2410_CLKCON_UART1;
32471 -       tmp |= S3C2410_CLKCON_UART2;
32472 -
32473 -       __raw_writel(tmp, S3C2410_CLKCON);
32474 -       udelay(10);
32475 -}
32476 -
32477 -#define DBG(fmt...) pm_dbg(fmt)
32478 -#else
32479 -#define DBG(fmt...) printk(KERN_DEBUG fmt)
32480 -
32481 -#define s3c2410_pm_debug_init() do { } while(0)
32482 -
32483 -static struct sleep_save uart_save[] = {};
32484 -#endif
32485 -
32486 -#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
32487 -
32488 -/* suspend checking code...
32489 - *
32490 - * this next area does a set of crc checks over all the installed
32491 - * memory, so the system can verify if the resume was ok.
32492 - *
32493 - * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
32494 - * increasing it will mean that the area corrupted will be less easy to spot,
32495 - * and reducing the size will cause the CRC save area to grow
32496 -*/
32497 -
32498 -#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
32499 -
32500 -static u32 crc_size;   /* size needed for the crc block */
32501 -static u32 *crcs;      /* allocated over suspend/resume */
32502 -
32503 -typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
32504 -
32505 -/* s3c2410_pm_run_res
32506 - *
32507 - * go thorugh the given resource list, and look for system ram
32508 -*/
32509 -
32510 -static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
32511 -{
32512 -       while (ptr != NULL) {
32513 -               if (ptr->child != NULL)
32514 -                       s3c2410_pm_run_res(ptr->child, fn, arg);
32515 -
32516 -               if ((ptr->flags & IORESOURCE_MEM) &&
32517 -                   strcmp(ptr->name, "System RAM") == 0) {
32518 -                       DBG("Found system RAM at %08lx..%08lx\n",
32519 -                           ptr->start, ptr->end);
32520 -                       arg = (fn)(ptr, arg);
32521 -               }
32522 -
32523 -               ptr = ptr->sibling;
32524 -       }
32525 -}
32526 -
32527 -static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
32528 -{
32529 -       s3c2410_pm_run_res(&iomem_resource, fn, arg);
32530 -}
32531 -
32532 -static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
32533 -{
32534 -       u32 size = (u32)(res->end - res->start)+1;
32535 -
32536 -       size += CHECK_CHUNKSIZE-1;
32537 -       size /= CHECK_CHUNKSIZE;
32538 -
32539 -       DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
32540 -
32541 -       *val += size * sizeof(u32);
32542 -       return val;
32543 -}
32544 -
32545 -/* s3c2410_pm_prepare_check
32546 - *
32547 - * prepare the necessary information for creating the CRCs. This
32548 - * must be done before the final save, as it will require memory
32549 - * allocating, and thus touching bits of the kernel we do not
32550 - * know about.
32551 -*/
32552 -
32553 -static void s3c2410_pm_check_prepare(void)
32554 -{
32555 -       crc_size = 0;
32556 -
32557 -       s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
32558 -
32559 -       DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
32560 -
32561 -       crcs = kmalloc(crc_size+4, GFP_KERNEL);
32562 -       if (crcs == NULL)
32563 -               printk(KERN_ERR "Cannot allocated CRC save area\n");
32564 -}
32565 -
32566 -static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
32567 -{
32568 -       unsigned long addr, left;
32569 -
32570 -       for (addr = res->start; addr < res->end;
32571 -            addr += CHECK_CHUNKSIZE) {
32572 -               left = res->end - addr;
32573 -
32574 -               if (left > CHECK_CHUNKSIZE)
32575 -                       left = CHECK_CHUNKSIZE;
32576 -
32577 -               *val = crc32_le(~0, phys_to_virt(addr), left);
32578 -               val++;
32579 -       }
32580 -
32581 -       return val;
32582 -}
32583 -
32584 -/* s3c2410_pm_check_store
32585 - *
32586 - * compute the CRC values for the memory blocks before the final
32587 - * sleep.
32588 -*/
32589 -
32590 -static void s3c2410_pm_check_store(void)
32591 -{
32592 -       if (crcs != NULL)
32593 -               s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
32594 -}
32595 -
32596 -/* in_region
32597 - *
32598 - * return TRUE if the area defined by ptr..ptr+size contatins the
32599 - * what..what+whatsz
32600 -*/
32601 -
32602 -static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
32603 -{
32604 -       if ((what+whatsz) < ptr)
32605 -               return 0;
32606 -
32607 -       if (what > (ptr+size))
32608 -               return 0;
32609 -
32610 -       return 1;
32611 -}
32612 -
32613 -static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
32614 -{
32615 -       void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
32616 -       unsigned long addr;
32617 -       unsigned long left;
32618 -       void *ptr;
32619 -       u32 calc;
32620 -
32621 -       for (addr = res->start; addr < res->end;
32622 -            addr += CHECK_CHUNKSIZE) {
32623 -               left = res->end - addr;
32624 -
32625 -               if (left > CHECK_CHUNKSIZE)
32626 -                       left = CHECK_CHUNKSIZE;
32627 -
32628 -               ptr = phys_to_virt(addr);
32629 -
32630 -               if (in_region(ptr, left, crcs, crc_size)) {
32631 -                       DBG("skipping %08lx, has crc block in\n", addr);
32632 -                       goto skip_check;
32633 -               }
32634 -
32635 -               if (in_region(ptr, left, save_at, 32*4 )) {
32636 -                       DBG("skipping %08lx, has save block in\n", addr);
32637 -                       goto skip_check;
32638 -               }
32639 -
32640 -               /* calculate and check the checksum */
32641 -
32642 -               calc = crc32_le(~0, ptr, left);
32643 -               if (calc != *val) {
32644 -                       printk(KERN_ERR PFX "Restore CRC error at "
32645 -                              "%08lx (%08x vs %08x)\n", addr, calc, *val);
32646 -
32647 -                       DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
32648 -                           addr, calc, *val);
32649 -               }
32650 -
32651 -       skip_check:
32652 -               val++;
32653 -       }
32654 -
32655 -       return val;
32656 -}
32657 -
32658 -/* s3c2410_pm_check_restore
32659 - *
32660 - * check the CRCs after the restore event and free the memory used
32661 - * to hold them
32662 -*/
32663 -
32664 -static void s3c2410_pm_check_restore(void)
32665 -{
32666 -       if (crcs != NULL) {
32667 -               s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
32668 -               kfree(crcs);
32669 -               crcs = NULL;
32670 -       }
32671 -}
32672 -
32673 -#else
32674 -
32675 -#define s3c2410_pm_check_prepare() do { } while(0)
32676 -#define s3c2410_pm_check_restore() do { } while(0)
32677 -#define s3c2410_pm_check_store()   do { } while(0)
32678 -#endif
32679 -
32680 -/* helper functions to save and restore register state */
32681 -
32682 -void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
32683 -{
32684 -       for (; count > 0; count--, ptr++) {
32685 -               ptr->val = __raw_readl(ptr->reg);
32686 -               DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
32687 -       }
32688 -}
32689 -
32690 -/* s3c2410_pm_do_restore
32691 - *
32692 - * restore the system from the given list of saved registers
32693 - *
32694 - * Note, we do not use DBG() in here, as the system may not have
32695 - * restore the UARTs state yet
32696 -*/
32697 -
32698 -void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
32699 -{
32700 -       for (; count > 0; count--, ptr++) {
32701 -               printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
32702 -                      ptr->reg, ptr->val, __raw_readl(ptr->reg));
32703 -
32704 -               __raw_writel(ptr->val, ptr->reg);
32705 -       }
32706 -}
32707 -
32708 -/* s3c2410_pm_do_restore_core
32709 - *
32710 - * similar to s3c2410_pm_do_restore_core
32711 - *
32712 - * WARNING: Do not put any debug in here that may effect memory or use
32713 - * peripherals, as things may be changing!
32714 -*/
32715 -
32716 -static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
32717 -{
32718 -       for (; count > 0; count--, ptr++) {
32719 -               __raw_writel(ptr->val, ptr->reg);
32720 -       }
32721 -}
32722 -
32723 -/* s3c2410_pm_show_resume_irqs
32724 - *
32725 - * print any IRQs asserted at resume time (ie, we woke from)
32726 -*/
32727 -
32728 -static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
32729 -                                       unsigned long mask)
32730 -{
32731 -       int i;
32732 -
32733 -       which &= ~mask;
32734 -
32735 -       for (i = 0; i <= 31; i++) {
32736 -               if ((which) & (1L<<i)) {
32737 -                       DBG("IRQ %d asserted at resume\n", start+i);
32738 -               }
32739 -       }
32740 -}
32741 -
32742 -/* s3c2410_pm_check_resume_pin
32743 +/* s3c_pm_check_resume_pin
32744   *
32745   * check to see if the pin is configured correctly for sleep mode, and
32746   * make any necessary adjustments if it is not
32747  */
32748
32749 -static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
32750 +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
32751  {
32752         unsigned long irqstate;
32753         unsigned long pinstate;
32754 @@ -455,21 +101,21 @@ static void s3c2410_pm_check_resume_pin(
32755
32756         if (!irqstate) {
32757                 if (pinstate == S3C2410_GPIO_IRQ)
32758 -                       DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
32759 +                       S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
32760         } else {
32761                 if (pinstate == S3C2410_GPIO_IRQ) {
32762 -                       DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
32763 +                       S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
32764                         s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
32765                 }
32766         }
32767  }
32768
32769 -/* s3c2410_pm_configure_extint
32770 +/* s3c_pm_configure_extint
32771   *
32772   * configure all external interrupt pins
32773  */
32774
32775 -static void s3c2410_pm_configure_extint(void)
32776 +void s3c_pm_configure_extint(void)
32777  {
32778         int pin;
32779
32780 @@ -479,336 +125,24 @@ static void s3c2410_pm_configure_extint(
32781         */
32782
32783         for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
32784 -               s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
32785 +               s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
32786         }
32787
32788         for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
32789 -               s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
32790 +               s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
32791         }
32792  }
32793
32794 -/* offsets for CON/DAT/UP registers */
32795 -
32796 -#define OFFS_CON       (S3C2410_GPACON - S3C2410_GPACON)
32797 -#define OFFS_DAT       (S3C2410_GPADAT - S3C2410_GPACON)
32798 -#define OFFS_UP                (S3C2410_GPBUP  - S3C2410_GPBCON)
32799 -
32800 -/* s3c2410_pm_save_gpios()
32801 - *
32802 - * Save the state of the GPIOs
32803 - */
32804
32805 -static void s3c2410_pm_save_gpios(void)
32806 +void s3c_pm_restore_core(void)
32807  {
32808 -       struct gpio_sleep *gps = gpio_save;
32809 -       unsigned int gpio;
32810 -
32811 -       for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
32812 -               void __iomem *base = gps->base;
32813 -
32814 -               gps->gpcon = __raw_readl(base + OFFS_CON);
32815 -               gps->gpdat = __raw_readl(base + OFFS_DAT);
32816 -
32817 -               if (gpio > 0)
32818 -                       gps->gpup = __raw_readl(base + OFFS_UP);
32819 -
32820 -       }
32821 -}
32822 -
32823 -/* Test whether the given masked+shifted bits of an GPIO configuration
32824 - * are one of the SFN (special function) modes. */
32825 -
32826 -static inline int is_sfn(unsigned long con)
32827 -{
32828 -       return (con == 2 || con == 3);
32829 -}
32830 -
32831 -/* Test if the given masked+shifted GPIO configuration is an input */
32832 -
32833 -static inline int is_in(unsigned long con)
32834 -{
32835 -       return con == 0;
32836 -}
32837 -
32838 -/* Test if the given masked+shifted GPIO configuration is an output */
32839 -
32840 -static inline int is_out(unsigned long con)
32841 -{
32842 -       return con == 1;
32843 +       s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
32844 +       s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
32845  }
32846
32847 -/* s3c2410_pm_restore_gpio()
32848 - *
32849 - * Restore one of the GPIO banks that was saved during suspend. This is
32850 - * not as simple as once thought, due to the possibility of glitches
32851 - * from the order that the CON and DAT registers are set in.
32852 - *
32853 - * The three states the pin can be are {IN,OUT,SFN} which gives us 9
32854 - * combinations of changes to check. Three of these, if the pin stays
32855 - * in the same configuration can be discounted. This leaves us with
32856 - * the following:
32857 - *
32858 - * { IN => OUT }  Change DAT first
32859 - * { IN => SFN }  Change CON first
32860 - * { OUT => SFN } Change CON first, so new data will not glitch
32861 - * { OUT => IN }  Change CON first, so new data will not glitch
32862 - * { SFN => IN }  Change CON first
32863 - * { SFN => OUT } Change DAT first, so new data will not glitch [1]
32864 - *
32865 - * We do not currently deal with the UP registers as these control
32866 - * weak resistors, so a small delay in change should not need to bring
32867 - * these into the calculations.
32868 - *
32869 - * [1] this assumes that writing to a pin DAT whilst in SFN will set the
32870 - *     state for when it is next output.
32871 - */
32872 -
32873 -static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
32874 +void s3c_pm_save_core(void)
32875  {
32876 -       void __iomem *base = gps->base;
32877 -       unsigned long gps_gpcon = gps->gpcon;
32878 -       unsigned long gps_gpdat = gps->gpdat;
32879 -       unsigned long old_gpcon;
32880 -       unsigned long old_gpdat;
32881 -       unsigned long old_gpup = 0x0;
32882 -       unsigned long gpcon;
32883 -       int nr;
32884 -
32885 -       old_gpcon = __raw_readl(base + OFFS_CON);
32886 -       old_gpdat = __raw_readl(base + OFFS_DAT);
32887 -
32888 -       if (base == S3C2410_GPACON) {
32889 -               /* GPACON only has one bit per control / data and no PULLUPs.
32890 -                * GPACON[x] = 0 => Output, 1 => SFN */
32891 -
32892 -               /* first set all SFN bits to SFN */
32893 -
32894 -               gpcon = old_gpcon | gps->gpcon;
32895 -               __raw_writel(gpcon, base + OFFS_CON);
32896 -
32897 -               /* now set all the other bits */
32898 -
32899 -               __raw_writel(gps_gpdat, base + OFFS_DAT);
32900 -               __raw_writel(gps_gpcon, base + OFFS_CON);
32901 -       } else {
32902 -               unsigned long old, new, mask;
32903 -               unsigned long change_mask = 0x0;
32904 -
32905 -               old_gpup = __raw_readl(base + OFFS_UP);
32906 -
32907 -               /* Create a change_mask of all the items that need to have
32908 -                * their CON value changed before their DAT value, so that
32909 -                * we minimise the work between the two settings.
32910 -                */
32911 -
32912 -               for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
32913 -                       old = (old_gpcon & mask) >> nr;
32914 -                       new = (gps_gpcon & mask) >> nr;
32915 -
32916 -                       /* If there is no change, then skip */
32917 -
32918 -                       if (old == new)
32919 -                               continue;
32920 -
32921 -                       /* If both are special function, then skip */
32922 -
32923 -                       if (is_sfn(old) && is_sfn(new))
32924 -                               continue;
32925 -
32926 -                       /* Change is IN => OUT, do not change now */
32927 -
32928 -                       if (is_in(old) && is_out(new))
32929 -                               continue;
32930 -
32931 -                       /* Change is SFN => OUT, do not change now */
32932 -
32933 -                       if (is_sfn(old) && is_out(new))
32934 -                               continue;
32935 -
32936 -                       /* We should now be at the case of IN=>SFN,
32937 -                        * OUT=>SFN, OUT=>IN, SFN=>IN. */
32938 -
32939 -                       change_mask |= mask;
32940 -               }
32941 -
32942 -               /* Write the new CON settings */
32943 -
32944 -               gpcon = old_gpcon & ~change_mask;
32945 -               gpcon |= gps_gpcon & change_mask;
32946 -
32947 -               __raw_writel(gpcon, base + OFFS_CON);
32948 -
32949 -               /* Now change any items that require DAT,CON */
32950 -
32951 -               __raw_writel(gps_gpdat, base + OFFS_DAT);
32952 -               __raw_writel(gps_gpcon, base + OFFS_CON);
32953 -               __raw_writel(gps->gpup, base + OFFS_UP);
32954 -       }
32955 -
32956 -       DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
32957 -           index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
32958 +       s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
32959 +       s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
32960  }
32961
32962 -
32963 -/** s3c2410_pm_restore_gpios()
32964 - *
32965 - * Restore the state of the GPIOs
32966 - */
32967 -
32968 -static void s3c2410_pm_restore_gpios(void)
32969 -{
32970 -       struct gpio_sleep *gps = gpio_save;
32971 -       int gpio;
32972 -
32973 -       for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
32974 -               s3c2410_pm_restore_gpio(gpio, gps);
32975 -       }
32976 -}
32977 -
32978 -void (*pm_cpu_prep)(void);
32979 -void (*pm_cpu_sleep)(void);
32980 -
32981 -#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
32982 -
32983 -/* s3c2410_pm_enter
32984 - *
32985 - * central control for sleep/resume process
32986 -*/
32987 -
32988 -static int s3c2410_pm_enter(suspend_state_t state)
32989 -{
32990 -       unsigned long regs_save[16];
32991 -
32992 -       /* ensure the debug is initialised (if enabled) */
32993 -
32994 -       s3c2410_pm_debug_init();
32995 -
32996 -       DBG("s3c2410_pm_enter(%d)\n", state);
32997 -
32998 -       if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
32999 -               printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
33000 -               return -EINVAL;
33001 -       }
33002 -
33003 -       /* check if we have anything to wake-up with... bad things seem
33004 -        * to happen if you suspend with no wakeup (system will often
33005 -        * require a full power-cycle)
33006 -       */
33007 -
33008 -       if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
33009 -           !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
33010 -               printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
33011 -               printk(KERN_ERR PFX "Aborting sleep\n");
33012 -               return -EINVAL;
33013 -       }
33014 -
33015 -       /* prepare check area if configured */
33016 -
33017 -       s3c2410_pm_check_prepare();
33018 -
33019 -       /* store the physical address of the register recovery block */
33020 -
33021 -       s3c2410_sleep_save_phys = virt_to_phys(regs_save);
33022 -
33023 -       DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
33024 -
33025 -       /* save all necessary core registers not covered by the drivers */
33026 -
33027 -       s3c2410_pm_save_gpios();
33028 -       s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
33029 -       s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
33030 -       s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
33031 -
33032 -       /* set the irq configuration for wake */
33033 -
33034 -       s3c2410_pm_configure_extint();
33035 -
33036 -       DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
33037 -           s3c_irqwake_intmask, s3c_irqwake_eintmask);
33038 -
33039 -       __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
33040 -       __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
33041 -
33042 -       /* ack any outstanding external interrupts before we go to sleep */
33043 -
33044 -       __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
33045 -       __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
33046 -       __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
33047 -
33048 -       /* call cpu specific preparation */
33049 -
33050 -       pm_cpu_prep();
33051 -
33052 -       /* flush cache back to ram */
33053 -
33054 -       flush_cache_all();
33055 -
33056 -       s3c2410_pm_check_store();
33057 -
33058 -       /* send the cpu to sleep... */
33059 -
33060 -       __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
33061 -
33062 -       /* s3c2410_cpu_save will also act as our return point from when
33063 -        * we resume as it saves its own register state, so use the return
33064 -        * code to differentiate return from save and return from sleep */
33065 -
33066 -       if (s3c2410_cpu_save(regs_save) == 0) {
33067 -               flush_cache_all();
33068 -               pm_cpu_sleep();
33069 -       }
33070 -
33071 -       /* restore the cpu state */
33072 -
33073 -       cpu_init();
33074 -
33075 -       /* restore the system state */
33076 -
33077 -       s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
33078 -       s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
33079 -       s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
33080 -       s3c2410_pm_restore_gpios();
33081 -
33082 -       s3c2410_pm_debug_init();
33083 -
33084 -       /* check what irq (if any) restored the system */
33085 -
33086 -       DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
33087 -           __raw_readl(S3C2410_SRCPND),
33088 -           __raw_readl(S3C2410_EINTPEND));
33089 -
33090 -       s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
33091 -                                   s3c_irqwake_intmask);
33092 -
33093 -       s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
33094 -                                   s3c_irqwake_eintmask);
33095 -
33096 -       DBG("post sleep, preparing to return\n");
33097 -
33098 -       s3c2410_pm_check_restore();
33099 -
33100 -       /* ok, let's return from sleep */
33101 -
33102 -       DBG("S3C2410 PM Resume (post-restore)\n");
33103 -       return 0;
33104 -}
33105 -
33106 -static struct platform_suspend_ops s3c2410_pm_ops = {
33107 -       .enter          = s3c2410_pm_enter,
33108 -       .valid          = suspend_valid_only_mem,
33109 -};
33110 -
33111 -/* s3c2410_pm_init
33112 - *
33113 - * Attach the power management functions. This should be called
33114 - * from the board specific initialisation if the board supports
33115 - * it.
33116 -*/
33117 -
33118 -int __init s3c2410_pm_init(void)
33119 -{
33120 -       printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
33121 -
33122 -       suspend_set_ops(&s3c2410_pm_ops);
33123 -       return 0;
33124 -}
33125 Index: linux-2.6.28/arch/arm/plat-s3c24xx/pm-simtec.c
33126 ===================================================================
33127 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/pm-simtec.c 2008-12-25 00:26:37.000000000 +0100
33128 +++ linux-2.6.28/arch/arm/plat-s3c24xx/pm-simtec.c      2009-01-02 00:01:56.000000000 +0100
33129 @@ -61,7 +61,7 @@ static __init int pm_simtec_init(void)
33130
33131         __raw_writel(gstatus4, S3C2410_GSTATUS4);
33132
33133 -       return s3c2410_pm_init();
33134 +       return s3c_pm_init();
33135  }
33136
33137  arch_initcall(pm_simtec_init);
33138 Index: linux-2.6.28/arch/arm/plat-s3c24xx/pwm-clock.c
33139 ===================================================================
33140 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/pwm-clock.c 2008-12-25 00:26:37.000000000 +0100
33141 +++ linux-2.6.28/arch/arm/plat-s3c24xx/pwm-clock.c      2009-01-02 00:01:56.000000000 +0100
33142 @@ -24,10 +24,10 @@
33143  #include <mach/regs-clock.h>
33144  #include <mach/regs-gpio.h>
33145
33146 -#include <plat/clock.h>
33147 -#include <plat/cpu.h>
33148 +#include <asm/plat-s3c24xx/clock.h>
33149 +#include <asm/plat-s3c24xx/cpu.h>
33150
33151 -#include <plat/regs-timer.h>
33152 +#include <asm/plat-s3c/regs-timer.h>
33153
33154  /* Each of the timers 0 through 5 go through the following
33155   * clock tree, with the inputs depending on the timers.
33156 Index: linux-2.6.28/arch/arm/plat-s3c24xx/s3c2410-clock.c
33157 ===================================================================
33158 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
33159 +++ linux-2.6.28/arch/arm/plat-s3c24xx/s3c2410-clock.c  2009-01-02 00:01:56.000000000 +0100
33160 @@ -0,0 +1,277 @@
33161 +/* linux/arch/arm/mach-s3c2410/clock.c
33162 + *
33163 + * Copyright (c) 2006 Simtec Electronics
33164 + *     Ben Dooks <ben@simtec.co.uk>
33165 + *
33166 + * S3C2410,S3C2440,S3C2442 Clock control support
33167 + *
33168 + * This program is free software; you can redistribute it and/or modify
33169 + * it under the terms of the GNU General Public License as published by
33170 + * the Free Software Foundation; either version 2 of the License, or
33171 + * (at your option) any later version.
33172 + *
33173 + * This program is distributed in the hope that it will be useful,
33174 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
33175 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
33176 + * GNU General Public License for more details.
33177 + *
33178 + * You should have received a copy of the GNU General Public License
33179 + * along with this program; if not, write to the Free Software
33180 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
33181 +*/
33182 +
33183 +#include <linux/init.h>
33184 +#include <linux/module.h>
33185 +#include <linux/kernel.h>
33186 +#include <linux/list.h>
33187 +#include <linux/errno.h>
33188 +#include <linux/err.h>
33189 +#include <linux/sysdev.h>
33190 +#include <linux/clk.h>
33191 +#include <linux/mutex.h>
33192 +#include <linux/delay.h>
33193 +#include <linux/serial_core.h>
33194 +#include <linux/io.h>
33195 +
33196 +#include <asm/mach/map.h>
33197 +
33198 +#include <mach/hardware.h>
33199 +
33200 +#include <plat/regs-serial.h>
33201 +#include <mach/regs-clock.h>
33202 +#include <mach/regs-gpio.h>
33203 +
33204 +#include <plat/s3c2410.h>
33205 +#include <plat/clock.h>
33206 +#include <plat/cpu.h>
33207 +
33208 +int s3c2410_clkcon_enable(struct clk *clk, int enable)
33209 +{
33210 +       unsigned int clocks = clk->ctrlbit;
33211 +       unsigned long clkcon;
33212 +
33213 +       clkcon = __raw_readl(S3C2410_CLKCON);
33214 +
33215 +       if (enable)
33216 +               clkcon |= clocks;
33217 +       else
33218 +               clkcon &= ~clocks;
33219 +
33220 +       /* ensure none of the special function bits set */
33221 +       clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
33222 +
33223 +       __raw_writel(clkcon, S3C2410_CLKCON);
33224 +
33225 +       return 0;
33226 +}
33227 +
33228 +static int s3c2410_upll_enable(struct clk *clk, int enable)
33229 +{
33230 +       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
33231 +       unsigned long orig = clkslow;
33232 +
33233 +       if (enable)
33234 +               clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
33235 +       else
33236 +               clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
33237 +
33238 +       __raw_writel(clkslow, S3C2410_CLKSLOW);
33239 +
33240 +       /* if we started the UPLL, then allow to settle */
33241 +
33242 +       if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
33243 +               udelay(200);
33244 +
33245 +       return 0;
33246 +}
33247 +
33248 +/* standard clock definitions */
33249 +
33250 +static struct clk init_clocks_disable[] = {
33251 +       {
33252 +               .name           = "nand",
33253 +               .id             = -1,
33254 +               .parent         = &clk_h,
33255 +               .enable         = s3c2410_clkcon_enable,
33256 +               .ctrlbit        = S3C2410_CLKCON_NAND,
33257 +       }, {
33258 +               .name           = "sdi",
33259 +               .id             = -1,
33260 +               .parent         = &clk_p,
33261 +               .enable         = s3c2410_clkcon_enable,
33262 +               .ctrlbit        = S3C2410_CLKCON_SDI,
33263 +       }, {
33264 +               .name           = "adc",
33265 +               .id             = -1,
33266 +               .parent         = &clk_p,
33267 +               .enable         = s3c2410_clkcon_enable,
33268 +               .ctrlbit        = S3C2410_CLKCON_ADC,
33269 +       }, {
33270 +               .name           = "i2c",
33271 +               .id             = -1,
33272 +               .parent         = &clk_p,
33273 +               .enable         = s3c2410_clkcon_enable,
33274 +               .ctrlbit        = S3C2410_CLKCON_IIC,
33275 +       }, {
33276 +               .name           = "iis",
33277 +               .id             = -1,
33278 +               .parent         = &clk_p,
33279 +               .enable         = s3c2410_clkcon_enable,
33280 +               .ctrlbit        = S3C2410_CLKCON_IIS,
33281 +       }, {
33282 +               .name           = "spi",
33283 +               .id             = -1,
33284 +               .parent         = &clk_p,
33285 +               .enable         = s3c2410_clkcon_enable,
33286 +               .ctrlbit        = S3C2410_CLKCON_SPI,
33287 +       }
33288 +};
33289 +
33290 +static struct clk init_clocks[] = {
33291 +       {
33292 +               .name           = "lcd",
33293 +               .id             = -1,
33294 +               .parent         = &clk_h,
33295 +               .enable         = s3c2410_clkcon_enable,
33296 +               .ctrlbit        = S3C2410_CLKCON_LCDC,
33297 +       }, {
33298 +               .name           = "gpio",
33299 +               .id             = -1,
33300 +               .parent         = &clk_p,
33301 +               .enable         = s3c2410_clkcon_enable,
33302 +               .ctrlbit        = S3C2410_CLKCON_GPIO,
33303 +       }, {
33304 +               .name           = "usb-host",
33305 +               .id             = -1,
33306 +               .parent         = &clk_h,
33307 +               .enable         = s3c2410_clkcon_enable,
33308 +               .ctrlbit        = S3C2410_CLKCON_USBH,
33309 +       }, {
33310 +               .name           = "usb-device",
33311 +               .id             = -1,
33312 +               .parent         = &clk_h,
33313 +               .enable         = s3c2410_clkcon_enable,
33314 +               .ctrlbit        = S3C2410_CLKCON_USBD,
33315 +       }, {
33316 +               .name           = "timers",
33317 +               .id             = -1,
33318 +               .parent         = &clk_p,
33319 +               .enable         = s3c2410_clkcon_enable,
33320 +               .ctrlbit        = S3C2410_CLKCON_PWMT,
33321 +       }, {
33322 +               .name           = "uart",
33323 +               .id             = 0,
33324 +               .parent         = &clk_p,
33325 +               .enable         = s3c2410_clkcon_enable,
33326 +               .ctrlbit        = S3C2410_CLKCON_UART0,
33327 +       }, {
33328 +               .name           = "uart",
33329 +               .id             = 1,
33330 +               .parent         = &clk_p,
33331 +               .enable         = s3c2410_clkcon_enable,
33332 +               .ctrlbit        = S3C2410_CLKCON_UART1,
33333 +       }, {
33334 +               .name           = "uart",
33335 +               .id             = 2,
33336 +               .parent         = &clk_p,
33337 +               .enable         = s3c2410_clkcon_enable,
33338 +               .ctrlbit        = S3C2410_CLKCON_UART2,
33339 +       }, {
33340 +               .name           = "rtc",
33341 +               .id             = -1,
33342 +               .parent         = &clk_p,
33343 +               .enable         = s3c2410_clkcon_enable,
33344 +               .ctrlbit        = S3C2410_CLKCON_RTC,
33345 +       }, {
33346 +               .name           = "watchdog",
33347 +               .id             = -1,
33348 +               .parent         = &clk_p,
33349 +               .ctrlbit        = 0,
33350 +       }, {
33351 +               .name           = "usb-bus-host",
33352 +               .id             = -1,
33353 +               .parent         = &clk_usb_bus,
33354 +       }, {
33355 +               .name           = "usb-bus-gadget",
33356 +               .id             = -1,
33357 +               .parent         = &clk_usb_bus,
33358 +       },
33359 +};
33360 +
33361 +/* s3c2410_baseclk_add()
33362 + *
33363 + * Add all the clocks used by the s3c2410 or compatible CPUs
33364 + * such as the S3C2440 and S3C2442.
33365 + *
33366 + * We cannot use a system device as we are needed before any
33367 + * of the init-calls that initialise the devices are actually
33368 + * done.
33369 +*/
33370 +
33371 +int __init s3c2410_baseclk_add(void)
33372 +{
33373 +       unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
33374 +       unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
33375 +       struct clk *clkp;
33376 +       struct clk *xtal;
33377 +       int ret;
33378 +       int ptr;
33379 +
33380 +       clk_upll.enable = s3c2410_upll_enable;
33381 +
33382 +       if (s3c24xx_register_clock(&clk_usb_bus) < 0)
33383 +               printk(KERN_ERR "failed to register usb bus clock\n");
33384 +
33385 +       /* register clocks from clock array */
33386 +
33387 +       clkp = init_clocks;
33388 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
33389 +               /* ensure that we note the clock state */
33390 +
33391 +               clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
33392 +
33393 +               ret = s3c24xx_register_clock(clkp);
33394 +               if (ret < 0) {
33395 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
33396 +                              clkp->name, ret);
33397 +               }
33398 +       }
33399 +
33400 +       /* We must be careful disabling the clocks we are not intending to
33401 +        * be using at boot time, as subsystems such as the LCD which do
33402 +        * their own DMA requests to the bus can cause the system to lockup
33403 +        * if they where in the middle of requesting bus access.
33404 +        *
33405 +        * Disabling the LCD clock if the LCD is active is very dangerous,
33406 +        * and therefore the bootloader should be careful to not enable
33407 +        * the LCD clock if it is not needed.
33408 +       */
33409 +
33410 +       /* install (and disable) the clocks we do not need immediately */
33411 +
33412 +       clkp = init_clocks_disable;
33413 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
33414 +
33415 +               ret = s3c24xx_register_clock(clkp);
33416 +               if (ret < 0) {
33417 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
33418 +                              clkp->name, ret);
33419 +               }
33420 +
33421 +               s3c2410_clkcon_enable(clkp, 0);
33422 +       }
33423 +
33424 +       /* show the clock-slow value */
33425 +
33426 +       xtal = clk_get(NULL, "xtal");
33427 +
33428 +       printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
33429 +              print_mhz(clk_get_rate(xtal) /
33430 +                        ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
33431 +              (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
33432 +              (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
33433 +              (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
33434 +
33435 +       s3c_pwmclk_init();
33436 +       return 0;
33437 +}
33438 Index: linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.c
33439 ===================================================================
33440 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/s3c244x.c   2008-12-25 00:26:37.000000000 +0100
33441 +++ linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.c        2009-01-02 00:01:56.000000000 +0100
33442 @@ -29,6 +29,8 @@
33443  #include <mach/hardware.h>
33444  #include <asm/irq.h>
33445
33446 +#include <plat/cpu-freq.h>
33447 +
33448  #include <mach/regs-clock.h>
33449  #include <plat/regs-serial.h>
33450  #include <mach/regs-gpio.h>
33451 @@ -42,6 +44,7 @@
33452  #include <plat/devs.h>
33453  #include <plat/cpu.h>
33454  #include <plat/pm.h>
33455 +#include <plat/pll.h>
33456
33457  static struct map_desc s3c244x_iodesc[] __initdata = {
33458         IODESC_ENT(CLKPWR),
33459 @@ -56,32 +59,37 @@ void __init s3c244x_init_uarts(struct s3
33460         s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
33461  }
33462
33463 -void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
33464 +extern struct platform_device s3c_device_ts;
33465 +
33466 +void __init s3c244x_map_io(void)
33467  {
33468         /* register our io-tables */
33469
33470         iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
33471 -       iotable_init(mach_desc, size);
33472
33473         /* rename any peripherals used differing from the s3c2410 */
33474
33475         s3c_device_sdi.name  = "s3c2440-sdi";
33476 -       s3c_device_i2c.name  = "s3c2440-i2c";
33477 +       s3c_device_i2c0.name  = "s3c2440-i2c";
33478         s3c_device_nand.name = "s3c2440-nand";
33479 +       s3c_device_ts.name = "s3c2440-ts";
33480         s3c_device_usbgadget.name = "s3c2440-usbgadget";
33481  }
33482
33483 -void __init s3c244x_init_clocks(int xtal)
33484 +void __init_or_cpufreq s3c244x_setup_clocks(void)
33485  {
33486 +       struct clk *xtal_clk;
33487         unsigned long clkdiv;
33488         unsigned long camdiv;
33489 +       unsigned long xtal;
33490         unsigned long hclk, fclk, pclk;
33491         int hdiv = 1;
33492
33493 -       /* now we've got our machine bits initialised, work out what
33494 -        * clocks we've got */
33495 +       xtal_clk = clk_get(NULL, "xtal");
33496 +       xtal = clk_get_rate(xtal_clk);
33497 +       clk_put(xtal_clk);
33498
33499 -       fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
33500 +       fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
33501
33502         clkdiv = __raw_readl(S3C2410_CLKDIVN);
33503         camdiv = __raw_readl(S3C2440_CAMDIVN);
33504 @@ -107,18 +115,24 @@ void __init s3c244x_init_clocks(int xtal
33505         }
33506
33507         hclk = fclk / hdiv;
33508 -       pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
33509 +       pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
33510
33511         /* print brief summary of clocks, etc */
33512
33513         printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
33514                print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
33515
33516 +       s3c24xx_setup_clocks(fclk, hclk, pclk);
33517 +}
33518 +
33519 +void __init s3c244x_init_clocks(int xtal)
33520 +{
33521         /* initialise the clocks here, to allow other things like the
33522          * console to use them, and to add new ones after the initialisation
33523          */
33524
33525 -       s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
33526 +       s3c24xx_register_baseclocks(xtal);
33527 +       s3c244x_setup_clocks();
33528         s3c2410_baseclk_add();
33529  }
33530
33531 @@ -134,13 +148,13 @@ static struct sleep_save s3c244x_sleep[]
33532
33533  static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
33534  {
33535 -       s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33536 +       s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33537         return 0;
33538  }
33539
33540  static int s3c244x_resume(struct sys_device *dev)
33541  {
33542 -       s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33543 +       s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
33544         return 0;
33545  }
33546
33547 Index: linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x-clock.c
33548 ===================================================================
33549 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/s3c244x-clock.c     2008-12-25 00:26:37.000000000 +0100
33550 +++ linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x-clock.c  2009-01-02 00:01:56.000000000 +0100
33551 @@ -31,7 +31,6 @@
33552  #include <linux/sysdev.h>
33553  #include <linux/interrupt.h>
33554  #include <linux/ioport.h>
33555 -#include <linux/mutex.h>
33556  #include <linux/clk.h>
33557  #include <linux/io.h>
33558
33559 @@ -102,13 +101,13 @@ static int s3c244x_clk_add(struct sys_de
33560         if (clk_get_rate(clock_upll) > (94 * MHZ)) {
33561                 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
33562
33563 -               mutex_lock(&clocks_mutex);
33564 +               spin_lock(&clocks_lock);
33565
33566                 clkdivn = __raw_readl(S3C2410_CLKDIVN);
33567                 clkdivn |= S3C2440_CLKDIVN_UCLK;
33568                 __raw_writel(clkdivn, S3C2410_CLKDIVN);
33569
33570 -               mutex_unlock(&clocks_mutex);
33571 +               spin_unlock(&clocks_lock);
33572         }
33573
33574         return 0;
33575 Index: linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.h
33576 ===================================================================
33577 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/s3c244x.h   2008-12-25 00:26:37.000000000 +0100
33578 +++ linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.h        2009-01-02 00:01:56.000000000 +0100
33579 @@ -12,7 +12,7 @@
33580
33581  #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
33582
33583 -extern void s3c244x_map_io(struct map_desc *mach_desc, int size);
33584 +extern void s3c244x_map_io(void);
33585
33586  extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
33587
33588 Index: linux-2.6.28/arch/arm/plat-s3c24xx/setup-i2c.c
33589 ===================================================================
33590 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
33591 +++ linux-2.6.28/arch/arm/plat-s3c24xx/setup-i2c.c      2009-01-02 00:01:56.000000000 +0100
33592 @@ -0,0 +1,25 @@
33593 +/* linux/arch/arm/plat-s3c24xx/setup-i2c.c
33594 + *
33595 + * Copyright 2008 Simtec Electronics
33596 + *     Ben Dooks <ben@simtec.co.uk>
33597 + *
33598 + * S3C24XX Base setup for i2c device
33599 + *
33600 + * This program is free software; you can redistribute it and/or modify
33601 + * it under the terms of the GNU General Public License version 2 as
33602 + * published by the Free Software Foundation.
33603 +*/
33604 +
33605 +#include <linux/kernel.h>
33606 +
33607 +struct platform_device;
33608 +
33609 +#include <plat/iic.h>
33610 +#include <mach/hardware.h>
33611 +#include <mach/regs-gpio.h>
33612 +
33613 +void s3c_i2c0_cfg_gpio(struct platform_device *dev)
33614 +{
33615 +       s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
33616 +       s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
33617 +}
33618 Index: linux-2.6.28/arch/arm/plat-s3c24xx/sleep.S
33619 ===================================================================
33620 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/sleep.S     2008-12-25 00:26:37.000000000 +0100
33621 +++ linux-2.6.28/arch/arm/plat-s3c24xx/sleep.S  2009-01-02 00:01:56.000000000 +0100
33622 @@ -41,7 +41,7 @@
33623
33624         .text
33625
33626 -       /* s3c2410_cpu_save
33627 +       /* s3c_cpu_save
33628          *
33629          * save enough of the CPU state to allow us to re-start
33630          * pm.c code. as we store items like the sp/lr, we will
33631 @@ -59,7 +59,7 @@
33632          *           1 => resumed from sleep
33633         */
33634
33635 -ENTRY(s3c2410_cpu_save)
33636 +ENTRY(s3c_cpu_save)
33637         stmfd   sp!, { r4 - r12, lr }
33638
33639         @@ store co-processor registers
33640 @@ -84,7 +84,7 @@ resume_with_mmu:
33641         .ltorg
33642
33643         @@ the next bits sit in the .data segment, even though they
33644 -       @@ happen to be code... the s3c2410_sleep_save_phys needs to be
33645 +       @@ happen to be code... the s3c_sleep_save_phys needs to be
33646         @@ accessed by the resume code before it can restore the MMU.
33647         @@ This means that the variable has to be close enough for the
33648         @@ code to read it... since the .text segment needs to be RO,
33649 @@ -92,19 +92,19 @@ resume_with_mmu:
33650
33651         .data
33652
33653 -       .global s3c2410_sleep_save_phys
33654 -s3c2410_sleep_save_phys:
33655 +       .global s3c_sleep_save_phys
33656 +s3c_sleep_save_phys:
33657         .word   0
33658
33659
33660         /* sleep magic, to allow the bootloader to check for an valid
33661          * image to resume to. Must be the first word before the
33662 -        * s3c2410_cpu_resume entry.
33663 +        * s3c_cpu_resume entry.
33664         */
33665
33666         .word   0x2bedf00d
33667
33668 -       /* s3c2410_cpu_resume
33669 +       /* s3c_cpu_resume
33670          *
33671          * resume code entry for bootloader to call
33672          *
33673 @@ -113,7 +113,7 @@ s3c2410_sleep_save_phys:
33674          * must not write to the code segment (code is read-only)
33675         */
33676
33677 -ENTRY(s3c2410_cpu_resume)
33678 +ENTRY(s3c_cpu_resume)
33679         mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
33680         msr     cpsr_c, r0
33681
33682 @@ -145,7 +145,7 @@ ENTRY(s3c2410_cpu_resume)
33683         mcr     p15, 0, r1, c8, c7, 0           @@ invalidate I & D TLBs
33684         mcr     p15, 0, r1, c7, c7, 0           @@ invalidate I & D caches
33685
33686 -       ldr     r0, s3c2410_sleep_save_phys     @ address of restore block
33687 +       ldr     r0, s3c_sleep_save_phys         @ address of restore block
33688         ldmia   r0, { r4 - r13 }
33689
33690         mcr     p15, 0, r4, c13, c0, 0          @ PID
33691 Index: linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
33692 ===================================================================
33693 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
33694 +++ linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c   2009-01-02 00:01:56.000000000 +0100
33695 @@ -0,0 +1,37 @@
33696 +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
33697 + *
33698 + * Copyright (c) 2008 Simtec Electronics
33699 + *     http://armlinux.simtec.co.uk/
33700 + *     Ben Dooks <ben@simtec.co.uk>
33701 + *
33702 + * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
33703 + *
33704 + * This program is free software; you can redistribute it and/or modify
33705 + * it under the terms of the GNU General Public License as published by
33706 + * the Free Software Foundation; either version 2 of the License.
33707 +*/
33708 +
33709 +#include <linux/kernel.h>
33710 +
33711 +#include <mach/hardware.h>
33712 +
33713 +#include <mach/spi.h>
33714 +#include <mach/regs-gpio.h>
33715 +
33716 +void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
33717 +                                         int enable)
33718 +{
33719 +       if (enable) {
33720 +               s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
33721 +               s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
33722 +               s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
33723 +               s3c2410_gpio_pullup(S3C2410_GPE11, 0);
33724 +               s3c2410_gpio_pullup(S3C2410_GPE13, 0);
33725 +       } else {
33726 +               s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
33727 +               s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
33728 +               s3c2410_gpio_pullup(S3C2410_GPE11, 1);
33729 +               s3c2410_gpio_pullup(S3C2410_GPE12, 1);
33730 +               s3c2410_gpio_pullup(S3C2410_GPE13, 1);
33731 +       }
33732 +}
33733 Index: linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
33734 ===================================================================
33735 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
33736 +++ linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c      2009-01-02 00:01:56.000000000 +0100
33737 @@ -0,0 +1,37 @@
33738 +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
33739 + *
33740 + * Copyright (c) 2008 Simtec Electronics
33741 + *     http://armlinux.simtec.co.uk/
33742 + *     Ben Dooks <ben@simtec.co.uk>
33743 + *
33744 + * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
33745 + *
33746 + * This program is free software; you can redistribute it and/or modify
33747 + * it under the terms of the GNU General Public License as published by
33748 + * the Free Software Foundation; either version 2 of the License.
33749 +*/
33750 +
33751 +#include <linux/kernel.h>
33752 +
33753 +#include <mach/hardware.h>
33754 +
33755 +#include <mach/spi.h>
33756 +#include <mach/regs-gpio.h>
33757 +
33758 +void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
33759 +                                      int enable)
33760 +{
33761 +       if (enable) {
33762 +               s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
33763 +               s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
33764 +               s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
33765 +               s3c2410_gpio_pullup(S3C2410_GPG5, 0);
33766 +               s3c2410_gpio_pullup(S3C2410_GPG6, 0);
33767 +       } else {
33768 +               s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
33769 +               s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
33770 +               s3c2410_gpio_pullup(S3C2410_GPG5, 1);
33771 +               s3c2410_gpio_pullup(S3C2410_GPG6, 1);
33772 +               s3c2410_gpio_pullup(S3C2410_GPG7, 1);
33773 +       }
33774 +}
33775 Index: linux-2.6.28/arch/arm/plat-s3c24xx/time.c
33776 ===================================================================
33777 --- linux-2.6.28.orig/arch/arm/plat-s3c24xx/time.c      2008-12-25 00:26:37.000000000 +0100
33778 +++ linux-2.6.28/arch/arm/plat-s3c24xx/time.c   2009-01-02 00:01:56.000000000 +0100
33779 @@ -3,6 +3,8 @@
33780   * Copyright (C) 2003-2005 Simtec Electronics
33781   *     Ben Dooks, <ben@simtec.co.uk>
33782   *
33783 + * dyn_tick support by Andrzej Zaborowski based on omap_dyn_tick_timer.
33784 + *
33785   * This program is free software; you can redistribute it and/or modify
33786   * it under the terms of the GNU General Public License as published by
33787   * the Free Software Foundation; either version 2 of the License, or
33788 @@ -25,23 +27,27 @@
33789  #include <linux/irq.h>
33790  #include <linux/err.h>
33791  #include <linux/clk.h>
33792 -#include <linux/io.h>
33793
33794  #include <asm/system.h>
33795  #include <asm/leds.h>
33796  #include <asm/mach-types.h>
33797
33798 +#include <asm/io.h>
33799  #include <asm/irq.h>
33800  #include <mach/map.h>
33801 -#include <plat/regs-timer.h>
33802 +#include <asm/plat-s3c/regs-timer.h>
33803  #include <mach/regs-irq.h>
33804  #include <asm/mach/time.h>
33805
33806 -#include <plat/clock.h>
33807 -#include <plat/cpu.h>
33808 +#include <asm/plat-s3c24xx/clock.h>
33809 +#include <asm/plat-s3c24xx/cpu.h>
33810
33811  static unsigned long timer_startval;
33812  static unsigned long timer_usec_ticks;
33813 +static struct work_struct resume_work;
33814 +
33815 +unsigned long pclk;
33816 +struct clk *clk;
33817
33818  #define TIMER_USEC_SHIFT 16
33819
33820 @@ -177,11 +183,7 @@ static void s3c2410_timer_setup (void)
33821                 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
33822                 tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
33823         } else {
33824 -               unsigned long pclk;
33825 -               struct clk *clk;
33826 -
33827 -               /* for the h1940 (and others), we use the pclk from the core
33828 -                * to generate the timer values. since values around 50 to
33829 +               /* since values around 50 to
33830                  * 70MHz are not values we can directly generate the timer
33831                  * value from, we need to pre-scale and divide before using it.
33832                  *
33833 @@ -189,19 +191,9 @@ static void s3c2410_timer_setup (void)
33834                  * (8.45 ticks per usec)
33835                  */
33836
33837 -               /* this is used as default if no other timer can be found */
33838 -
33839 -               clk = clk_get(NULL, "timers");
33840 -               if (IS_ERR(clk))
33841 -                       panic("failed to get clock for system timer");
33842 -
33843 -               clk_enable(clk);
33844 -
33845 -               pclk = clk_get_rate(clk);
33846 -
33847                 /* configure clock tick */
33848 -
33849                 timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
33850 +               printk("timer_usec_ticks = %lu\n", timer_usec_ticks);
33851
33852                 tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
33853                 tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
33854 @@ -245,16 +237,244 @@ static void s3c2410_timer_setup (void)
33855         tcon |= S3C2410_TCON_T4START;
33856         tcon &= ~S3C2410_TCON_T4MANUALUPD;
33857         __raw_writel(tcon, S3C2410_TCON);
33858 +
33859 +       __raw_writel(__raw_readl(S3C2410_INTMSK) & (~(1UL << 14)),
33860 +                    S3C2410_INTMSK);
33861 +
33862 +}
33863 +
33864 +struct sys_timer s3c24xx_timer;
33865 +static void timer_resume_work(struct work_struct *work)
33866 +{
33867 +       clk_enable(clk);
33868 +
33869 +#ifdef CONFIG_NO_IDLE_HZ
33870 +       if (s3c24xx_timer.dyn_tick->state & DYN_TICK_ENABLED)
33871 +               s3c24xx_timer.dyn_tick->enable();
33872 +       else
33873 +#endif
33874 +               s3c2410_timer_setup();
33875  }
33876
33877  static void __init s3c2410_timer_init (void)
33878  {
33879 +       if (!use_tclk1_12()) {
33880 +               /* for the h1940 (and others), we use the pclk from the core
33881 +                * to generate the timer values.
33882 +                */
33883 +
33884 +               /* this is used as default if no other timer can be found */
33885 +               clk = clk_get(NULL, "timers");
33886 +               if (IS_ERR(clk))
33887 +                       panic("failed to get clock for system timer");
33888 +
33889 +               clk_enable(clk);
33890 +
33891 +               pclk = clk_get_rate(clk);
33892 +               printk("pclk = %lu\n", pclk);
33893 +       }
33894 +
33895 +       INIT_WORK(&resume_work, timer_resume_work);
33896         s3c2410_timer_setup();
33897         setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
33898  }
33899
33900 +static void s3c2410_timer_resume_work(struct work_struct *work)
33901 +{
33902 +       s3c2410_timer_setup();
33903 +}
33904 +
33905 +static void s3c2410_timer_resume(void)
33906 +{
33907 +       static DECLARE_WORK(work, s3c2410_timer_resume_work);
33908 +       int res;
33909 +
33910 +       res = schedule_work(&work);
33911 +       if (!res)
33912 +               printk(KERN_ERR
33913 +                   "s3c2410_timer_resume_work already queued ???\n");
33914 +}
33915 +
33916 +#ifdef CONFIG_NO_IDLE_HZ
33917 +/*
33918 + * We'll set a constant prescaler so we don't have to bother setting it
33919 + * when reprogramming and so that we avoid costly divisions.
33920 + *
33921 + * (2 * HZ) << INPUT_FREQ_SHIFT is the desired frequency after prescaler.
33922 + * At HZ == 200, HZ * 1024 should work for PCLKs of up to ~53.5 MHz.
33923 + */
33924 +#define INPUT_FREQ_SHIFT       9
33925 +
33926 +static int ticks_last;
33927 +static int ticks_left;
33928 +static uint32_t tcnto_last;
33929 +
33930 +static inline int s3c24xx_timer_read(void)
33931 +{
33932 +       uint32_t tcnto = __raw_readl(S3C2410_TCNTO(4));
33933 +
33934 +       /*
33935 +        * WARNING: sometimes we get called before TCNTB has been
33936 +        * loaded into the counter and TCNTO then returns its previous
33937 +        * value and kill us, so don't do anything before counter is
33938 +        * reloaded.
33939 +        */
33940 +       if (unlikely(tcnto == tcnto_last))
33941 +               return ticks_last;
33942 +
33943 +       tcnto_last = -1;
33944 +       return tcnto <<
33945 +               ((__raw_readl(S3C2410_TCFG1) >> S3C2410_TCFG1_MUX4_SHIFT) & 3);
33946 +}
33947 +
33948 +static inline void s3c24xx_timer_program(int ticks)
33949 +{
33950 +       uint32_t tcon = __raw_readl(S3C2410_TCON) & ~(7 << 20);
33951 +       uint32_t tcfg1 = __raw_readl(S3C2410_TCFG1) & ~S3C2410_TCFG1_MUX4_MASK;
33952 +
33953 +       /* Just make sure the timer is stopped.  */
33954 +       __raw_writel(tcon, S3C2410_TCON);
33955 +
33956 +       /* TODO: add likely()ies / unlikely()ies */
33957 +       if (ticks >> 18) {
33958 +               ticks_last = min(ticks, 0xffff << 3);
33959 +               ticks_left = ticks - ticks_last;
33960 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV16, S3C2410_TCFG1);
33961 +               __raw_writel(ticks_last >> 3, S3C2410_TCNTB(4));
33962 +       } else if (ticks >> 17) {
33963 +               ticks_last = ticks;
33964 +               ticks_left = 0;
33965 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV8, S3C2410_TCFG1);
33966 +               __raw_writel(ticks_last >> 2, S3C2410_TCNTB(4));
33967 +       } else if (ticks >> 16) {
33968 +               ticks_last = ticks;
33969 +               ticks_left = 0;
33970 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV4, S3C2410_TCFG1);
33971 +               __raw_writel(ticks_last >> 1, S3C2410_TCNTB(4));
33972 +       } else {
33973 +               ticks_last = ticks;
33974 +               ticks_left = 0;
33975 +               __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV2, S3C2410_TCFG1);
33976 +               __raw_writel(ticks_last >> 0, S3C2410_TCNTB(4));
33977 +       }
33978 +
33979 +       tcnto_last = __raw_readl(S3C2410_TCNTO(4));
33980 +       __raw_writel(tcon | S3C2410_TCON_T4MANUALUPD,
33981 +                       S3C2410_TCON);
33982 +       __raw_writel(tcon | S3C2410_TCON_T4START,
33983 +                       S3C2410_TCON);
33984 +}
33985 +
33986 +/*
33987 + * If we have already waited all the time we were supposed to wait,
33988 + * kick the timer, setting the longest allowed timeout value just
33989 + * for time-keeping.
33990 + */
33991 +static inline void s3c24xx_timer_program_idle(void)
33992 +{
33993 +       s3c24xx_timer_program(0xffff << 3);
33994 +}
33995 +
33996 +static inline void s3c24xx_timer_update(int restart)
33997 +{
33998 +       int ticks_cur = s3c24xx_timer_read();
33999 +       int jiffies_elapsed = (ticks_last - ticks_cur) >> INPUT_FREQ_SHIFT;
34000 +       int subjiffy = ticks_last - (jiffies_elapsed << INPUT_FREQ_SHIFT);
34001 +
34002 +       if (restart) {
34003 +               if (ticks_left >= (1 << INPUT_FREQ_SHIFT))
34004 +                       s3c24xx_timer_program(ticks_left);
34005 +               else
34006 +                       s3c24xx_timer_program_idle();
34007 +               ticks_last += subjiffy;
34008 +       } else
34009 +               ticks_last = subjiffy;
34010 +
34011 +       while (jiffies_elapsed --)
34012 +               timer_tick();
34013 +}
34014 +
34015 +/* Called when the timer expires.  */
34016 +static irqreturn_t s3c24xx_timer_handler(int irq, void *dev_id)
34017 +{
34018 +       tcnto_last = -1;
34019 +       s3c24xx_timer_update(1);
34020 +
34021 +       return IRQ_HANDLED;
34022 +}
34023 +
34024 +/* Called to update jiffies with time elapsed.  */
34025 +static irqreturn_t s3c24xx_timer_handler_dyn_tick(int irq, void *dev_id)
34026 +{
34027 +       s3c24xx_timer_update(0);
34028 +
34029 +       return IRQ_HANDLED;
34030 +}
34031 +
34032 +/*
34033 + * Programs the next timer interrupt needed.  Called when dynamic tick is
34034 + * enabled, and to reprogram the ticks to skip from pm_idle.  The CPU goes
34035 + * to sleep directly after this.
34036 + */
34037 +static void s3c24xx_timer_reprogram_dyn_tick(unsigned long next_jiffies)
34038 +{
34039 +       int subjiffy_left = ticks_last - s3c24xx_timer_read();
34040 +
34041 +       s3c24xx_timer_program(max((int) next_jiffies, 1) << INPUT_FREQ_SHIFT);
34042 +       ticks_last += subjiffy_left;
34043 +}
34044 +
34045 +static unsigned long s3c24xx_timer_offset_dyn_tick(void)
34046 +{
34047 +       /* TODO */
34048 +       return 0;
34049 +}
34050 +
34051 +static int s3c24xx_timer_enable_dyn_tick(void)
34052 +{
34053 +       /* Set our constant prescaler.  */
34054 +       uint32_t tcfg0 = __raw_readl(S3C2410_TCFG0);
34055 +       int prescaler =
34056 +               max(min(256, (int) pclk / (HZ << (INPUT_FREQ_SHIFT + 1))), 1);
34057 +
34058 +       tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
34059 +       tcfg0 |= (prescaler - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
34060 +       __raw_writel(tcfg0, S3C2410_TCFG0);
34061 +
34062 +       /* Override handlers.  */
34063 +       s3c2410_timer_irq.handler = s3c24xx_timer_handler;
34064 +       s3c24xx_timer.offset = s3c24xx_timer_offset_dyn_tick;
34065 +
34066 +       printk(KERN_INFO "dyn_tick enabled on s3c24xx timer 4, "
34067 +                       "%li Hz pclk with prescaler %i\n", pclk, prescaler);
34068 +
34069 +       s3c24xx_timer_program_idle();
34070 +
34071 +       return 0;
34072 +}
34073 +
34074 +static int s3c24xx_timer_disable_dyn_tick(void)
34075 +{
34076 +       s3c2410_timer_irq.handler = s3c2410_timer_interrupt;
34077 +       s3c24xx_timer.offset = s3c2410_gettimeoffset;
34078 +       s3c2410_timer_setup();
34079 +
34080 +       return 0;
34081 +}
34082 +
34083 +static struct dyn_tick_timer s3c24xx_dyn_tick_timer = {
34084 +       .enable         = s3c24xx_timer_enable_dyn_tick,
34085 +       .disable        = s3c24xx_timer_disable_dyn_tick,
34086 +       .reprogram      = s3c24xx_timer_reprogram_dyn_tick,
34087 +       .handler        = s3c24xx_timer_handler_dyn_tick,
34088 +};
34089 +#endif /* CONFIG_NO_IDLE_HZ */
34090 +
34091  struct sys_timer s3c24xx_timer = {
34092         .init           = s3c2410_timer_init,
34093         .offset         = s3c2410_gettimeoffset,
34094 -       .resume         = s3c2410_timer_setup
34095 +       .resume         = s3c2410_timer_resume,
34096 +#ifdef CONFIG_NO_IDLE_HZ
34097 +       .dyn_tick       = &s3c24xx_dyn_tick_timer,
34098 +#endif
34099  };
34100 Index: linux-2.6.28/arch/arm/plat-s3c64xx/clock.c
34101 ===================================================================
34102 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
34103 +++ linux-2.6.28/arch/arm/plat-s3c64xx/clock.c  2009-01-02 00:01:56.000000000 +0100
34104 @@ -0,0 +1,282 @@
34105 +/* linux/arch/arm/plat-s3c64xx/clock.c
34106 + *
34107 + * Copyright 2008 Openmoko, Inc.
34108 + * Copyright 2008 Simtec Electronics
34109 + *     Ben Dooks <ben@simtec.co.uk>
34110 + *     http://armlinux.simtec.co.uk/
34111 + *
34112 + * S3C64XX Base clock support
34113 + *
34114 + * This program is free software; you can redistribute it and/or modify
34115 + * it under the terms of the GNU General Public License version 2 as
34116 + * published by the Free Software Foundation.
34117 +*/
34118 +
34119 +#include <linux/init.h>
34120 +#include <linux/module.h>
34121 +#include <linux/interrupt.h>
34122 +#include <linux/ioport.h>
34123 +#include <linux/delay.h>
34124 +#include <linux/io.h>
34125 +
34126 +#include <mach/hardware.h>
34127 +#include <mach/map.h>
34128 +
34129 +#include <plat/regs-sys.h>
34130 +#include <plat/regs-clock.h>
34131 +#include <plat/cpu.h>
34132 +#include <plat/devs.h>
34133 +#include <plat/clock.h>
34134 +
34135 +struct clk clk_27m = {
34136 +       .name           = "clk_27m",
34137 +       .id             = -1,
34138 +       .rate           = 27000000,
34139 +};
34140 +
34141 +static int clk_48m_ctrl(struct clk *clk, int enable)
34142 +{
34143 +       unsigned long flags;
34144 +       u32 val;
34145 +
34146 +       /* can't rely on clock lock, this register has other usages */
34147 +       local_irq_save(flags);
34148 +
34149 +       val = __raw_readl(S3C64XX_OTHERS);
34150 +       if (enable)
34151 +               val |= S3C64XX_OTHERS_USBMASK;
34152 +       else
34153 +               val &= ~S3C64XX_OTHERS_USBMASK;
34154 +
34155 +       __raw_writel(val, S3C64XX_OTHERS);
34156 +       local_irq_restore(flags);
34157 +
34158 +       return 0;
34159 +}
34160 +
34161 +struct clk clk_48m = {
34162 +       .name           = "clk_48m",
34163 +       .id             = -1,
34164 +       .rate           = 48000000,
34165 +       .enable         = clk_48m_ctrl,
34166 +};
34167 +
34168 +static int inline s3c64xx_gate(void __iomem *reg,
34169 +                               struct clk *clk,
34170 +                               int enable)
34171 +{
34172 +       unsigned int ctrlbit = clk->ctrlbit;
34173 +       u32 con;
34174 +
34175 +       con = __raw_readl(reg);
34176 +
34177 +       if (enable)
34178 +               con |= ctrlbit;
34179 +       else
34180 +               con &= ~ctrlbit;
34181 +
34182 +       __raw_writel(con, reg);
34183 +       return 0;
34184 +}
34185 +
34186 +static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
34187 +{
34188 +       return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
34189 +}
34190 +
34191 +static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
34192 +{
34193 +       return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
34194 +}
34195 +
34196 +int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
34197 +{
34198 +       return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
34199 +}
34200 +
34201 +static struct clk init_clocks_disable[] = {
34202 +       {
34203 +               .name           = "nand",
34204 +               .id             = -1,
34205 +               .parent         = &clk_h,
34206 +       }, {
34207 +               .name           = "adc",
34208 +               .id             = -1,
34209 +               .parent         = &clk_p,
34210 +               .enable         = s3c64xx_pclk_ctrl,
34211 +               .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
34212 +       }, {
34213 +               .name           = "i2c",
34214 +               .id             = -1,
34215 +               .parent         = &clk_p,
34216 +               .enable         = s3c64xx_pclk_ctrl,
34217 +               .ctrlbit        = S3C_CLKCON_PCLK_IIC,
34218 +       }, {
34219 +               .name           = "iis",
34220 +               .id             = 0,
34221 +               .parent         = &clk_p,
34222 +               .enable         = s3c64xx_pclk_ctrl,
34223 +               .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
34224 +       }, {
34225 +               .name           = "iis",
34226 +               .id             = 1,
34227 +               .parent         = &clk_p,
34228 +               .enable         = s3c64xx_pclk_ctrl,
34229 +               .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
34230 +       }, {
34231 +               .name           = "spi",
34232 +               .id             = 0,
34233 +               .parent         = &clk_p,
34234 +               .enable         = s3c64xx_pclk_ctrl,
34235 +               .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
34236 +       }, {
34237 +               .name           = "spi",
34238 +               .id             = 1,
34239 +               .parent         = &clk_p,
34240 +               .enable         = s3c64xx_pclk_ctrl,
34241 +               .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
34242 +       }, {
34243 +               .name           = "48m",
34244 +               .id             = 0,
34245 +               .parent         = &clk_48m,
34246 +               .enable         = s3c64xx_sclk_ctrl,
34247 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
34248 +       }, {
34249 +               .name           = "48m",
34250 +               .id             = 1,
34251 +               .parent         = &clk_48m,
34252 +               .enable         = s3c64xx_sclk_ctrl,
34253 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
34254 +       }, {
34255 +               .name           = "48m",
34256 +               .id             = 2,
34257 +               .parent         = &clk_48m,
34258 +               .enable         = s3c64xx_sclk_ctrl,
34259 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
34260 +       },
34261 +};
34262 +
34263 +static struct clk init_clocks[] = {
34264 +       {
34265 +               .name           = "lcd",
34266 +               .id             = -1,
34267 +               .parent         = &clk_h,
34268 +               .enable         = s3c64xx_hclk_ctrl,
34269 +               .ctrlbit        = S3C_CLKCON_HCLK_LCD,
34270 +       }, {
34271 +               .name           = "gpio",
34272 +               .id             = -1,
34273 +               .parent         = &clk_p,
34274 +               .enable         = s3c64xx_pclk_ctrl,
34275 +               .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
34276 +       }, {
34277 +               .name           = "usb-host",
34278 +               .id             = -1,
34279 +               .parent         = &clk_h,
34280 +               .enable         = s3c64xx_hclk_ctrl,
34281 +               .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
34282 +       }, {
34283 +               .name           = "hsmmc",
34284 +               .id             = 0,
34285 +               .parent         = &clk_h,
34286 +               .enable         = s3c64xx_hclk_ctrl,
34287 +               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
34288 +       }, {
34289 +               .name           = "hsmmc",
34290 +               .id             = 1,
34291 +               .parent         = &clk_h,
34292 +               .enable         = s3c64xx_hclk_ctrl,
34293 +               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
34294 +       }, {
34295 +               .name           = "hsmmc",
34296 +               .id             = 2,
34297 +               .parent         = &clk_h,
34298 +               .enable         = s3c64xx_hclk_ctrl,
34299 +               .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
34300 +       }, {
34301 +               .name           = "timers",
34302 +               .id             = -1,
34303 +               .parent         = &clk_p,
34304 +               .enable         = s3c64xx_pclk_ctrl,
34305 +               .ctrlbit        = S3C_CLKCON_PCLK_PWM,
34306 +       }, {
34307 +               .name           = "uart",
34308 +               .id             = 0,
34309 +               .parent         = &clk_p,
34310 +               .enable         = s3c64xx_pclk_ctrl,
34311 +               .ctrlbit        = S3C_CLKCON_PCLK_UART0,
34312 +       }, {
34313 +               .name           = "uart",
34314 +               .id             = 1,
34315 +               .parent         = &clk_p,
34316 +               .enable         = s3c64xx_pclk_ctrl,
34317 +               .ctrlbit        = S3C_CLKCON_PCLK_UART1,
34318 +       }, {
34319 +               .name           = "uart",
34320 +               .id             = 2,
34321 +               .parent         = &clk_p,
34322 +               .enable         = s3c64xx_pclk_ctrl,
34323 +               .ctrlbit        = S3C_CLKCON_PCLK_UART2,
34324 +       }, {
34325 +               .name           = "uart",
34326 +               .id             = 3,
34327 +               .parent         = &clk_p,
34328 +               .enable         = s3c64xx_pclk_ctrl,
34329 +               .ctrlbit        = S3C_CLKCON_PCLK_UART3,
34330 +       }, {
34331 +               .name           = "rtc",
34332 +               .id             = -1,
34333 +               .parent         = &clk_p,
34334 +               .enable         = s3c64xx_pclk_ctrl,
34335 +               .ctrlbit        = S3C_CLKCON_PCLK_RTC,
34336 +       }, {
34337 +               .name           = "watchdog",
34338 +               .id             = -1,
34339 +               .parent         = &clk_p,
34340 +               .ctrlbit        = S3C_CLKCON_PCLK_WDT,
34341 +       }, {
34342 +               .name           = "ac97",
34343 +               .id             = -1,
34344 +               .parent         = &clk_p,
34345 +               .ctrlbit        = S3C_CLKCON_PCLK_AC97,
34346 +       }
34347 +};
34348 +
34349 +static struct clk *clks[] __initdata = {
34350 +       &clk_ext,
34351 +       &clk_epll,
34352 +       &clk_27m,
34353 +       &clk_48m,
34354 +};
34355 +
34356 +void s3c64xx_register_clocks(void)
34357 +{
34358 +       struct clk *clkp;
34359 +       int ret;
34360 +       int ptr;
34361 +
34362 +       s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
34363 +
34364 +       clkp = init_clocks;
34365 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
34366 +               ret = s3c24xx_register_clock(clkp);
34367 +               if (ret < 0) {
34368 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
34369 +                              clkp->name, ret);
34370 +               }
34371 +       }
34372 +
34373 +       clkp = init_clocks_disable;
34374 +       for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
34375 +
34376 +               ret = s3c24xx_register_clock(clkp);
34377 +               if (ret < 0) {
34378 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
34379 +                              clkp->name, ret);
34380 +               }
34381 +
34382 +               (clkp->enable)(clkp, 0);
34383 +       }
34384 +
34385 +       s3c_pwmclk_init();
34386 +}
34387 Index: linux-2.6.28/arch/arm/plat-s3c64xx/cpu.c
34388 ===================================================================
34389 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
34390 +++ linux-2.6.28/arch/arm/plat-s3c64xx/cpu.c    2009-01-02 00:01:56.000000000 +0100
34391 @@ -0,0 +1,139 @@
34392 +/* linux/arch/arm/plat-s3c64xx/cpu.c
34393 + *
34394 + * Copyright 2008 Openmoko, Inc.
34395 + * Copyright 2008 Simtec Electronics
34396 + *     Ben Dooks <ben@simtec.co.uk>
34397 + *     http://armlinux.simtec.co.uk/
34398 + *
34399 + * S3C64XX CPU Support
34400 + *
34401 + * This program is free software; you can redistribute it and/or modify
34402 + * it under the terms of the GNU General Public License version 2 as
34403 + * published by the Free Software Foundation.
34404 +*/
34405 +
34406 +#include <linux/init.h>
34407 +#include <linux/module.h>
34408 +#include <linux/interrupt.h>
34409 +#include <linux/ioport.h>
34410 +#include <linux/sysdev.h>
34411 +#include <linux/serial_core.h>
34412 +#include <linux/platform_device.h>
34413 +#include <linux/delay.h>
34414 +#include <linux/io.h>
34415 +
34416 +#include <mach/hardware.h>
34417 +#include <mach/map.h>
34418 +
34419 +#include <asm/mach/arch.h>
34420 +#include <asm/mach/map.h>
34421 +
34422 +#include <plat/regs-serial.h>
34423 +
34424 +#include <plat/cpu.h>
34425 +#include <plat/devs.h>
34426 +#include <plat/clock.h>
34427 +
34428 +#include <plat/s3c6400.h>
34429 +#include <plat/s3c6410.h>
34430 +
34431 +/* table of supported CPUs */
34432 +
34433 +static const char name_s3c6400[] = "S3C6400";
34434 +static const char name_s3c6410[] = "S3C6410";
34435 +
34436 +static struct cpu_table cpu_ids[] __initdata = {
34437 +       {
34438 +               .idcode         = 0x36400000,
34439 +               .idmask         = 0xfffff000,
34440 +               .map_io         = s3c6400_map_io,
34441 +               .init_clocks    = s3c6400_init_clocks,
34442 +               .init_uarts     = s3c6400_init_uarts,
34443 +               .init           = s3c6400_init,
34444 +               .name           = name_s3c6400,
34445 +       }, {
34446 +               .idcode         = 0x36410100,
34447 +               .idmask         = 0xffffff00,
34448 +               .map_io         = s3c6410_map_io,
34449 +               .init_clocks    = s3c6410_init_clocks,
34450 +               .init_uarts     = s3c6410_init_uarts,
34451 +               .init           = s3c6410_init,
34452 +               .name           = name_s3c6410,
34453 +       },
34454 +};
34455 +
34456 +/* minimal IO mapping */
34457 +
34458 +/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
34459 +#define UART_OFFS (S3C_PA_UART & 0xfffff)
34460 +
34461 +static struct map_desc s3c_iodesc[] __initdata = {
34462 +       {
34463 +               .virtual        = (unsigned long)S3C_VA_SYS,
34464 +               .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
34465 +               .length         = SZ_4K,
34466 +               .type           = MT_DEVICE,
34467 +       }, {
34468 +               .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
34469 +               .pfn            = __phys_to_pfn(S3C_PA_UART),
34470 +               .length         = SZ_4K,
34471 +               .type           = MT_DEVICE,
34472 +       }, {
34473 +               .virtual        = (unsigned long)S3C_VA_VIC0,
34474 +               .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
34475 +               .length         = SZ_16K,
34476 +               .type           = MT_DEVICE,
34477 +       }, {
34478 +               .virtual        = (unsigned long)S3C_VA_VIC1,
34479 +               .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
34480 +               .length         = SZ_16K,
34481 +               .type           = MT_DEVICE,
34482 +       }, {
34483 +               .virtual        = (unsigned long)S3C_VA_TIMER,
34484 +               .pfn            = __phys_to_pfn(S3C_PA_TIMER),
34485 +               .length         = SZ_16K,
34486 +               .type           = MT_DEVICE,
34487 +       }, {
34488 +               .virtual        = (unsigned long)S3C64XX_VA_GPIO,
34489 +               .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
34490 +               .length         = SZ_4K,
34491 +               .type           = MT_DEVICE,
34492 +       }, {
34493 +               .virtual        = (unsigned long)S3C64XX_VA_MODEM,
34494 +               .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
34495 +               .length         = SZ_4K,
34496 +               .type           = MT_DEVICE,
34497 +       },
34498 +};
34499 +
34500 +
34501 +struct sysdev_class s3c64xx_sysclass = {
34502 +       .name   = "s3c64xx-core",
34503 +};
34504 +
34505 +static struct sys_device s3c64xx_sysdev = {
34506 +       .cls    = &s3c64xx_sysclass,
34507 +};
34508 +
34509 +
34510 +/* read cpu identification code */
34511 +
34512 +void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
34513 +{
34514 +       unsigned long idcode;
34515 +
34516 +       /* initialise the io descriptors we need for initialisation */
34517 +       iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
34518 +       iotable_init(mach_desc, size);
34519 +
34520 +       idcode = __raw_readl(S3C_VA_SYS + 0x118);
34521 +       s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
34522 +}
34523 +
34524 +static __init int s3c64xx_sysdev_init(void)
34525 +{
34526 +       sysdev_class_register(&s3c64xx_sysclass);
34527 +       return sysdev_register(&s3c64xx_sysdev);
34528 +}
34529 +
34530 +core_initcall(s3c64xx_sysdev_init);
34531 Index: linux-2.6.28/arch/arm/plat-s3c64xx/dev-uart.c
34532 ===================================================================
34533 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
34534 +++ linux-2.6.28/arch/arm/plat-s3c64xx/dev-uart.c       2009-01-02 00:01:56.000000000 +0100
34535 @@ -0,0 +1,176 @@
34536 +/* linux/arch/arm/plat-s3c64xx/dev-uart.c
34537 + *
34538 + * Copyright 2008 Openmoko, Inc.
34539 + * Copyright 2008 Simtec Electronics
34540 + *     Ben Dooks <ben@simtec.co.uk>
34541 + *     http://armlinux.simtec.co.uk/
34542 + *
34543 + * Base S3C64XX UART resource and device definitions
34544 + *
34545 + * This program is free software; you can redistribute it and/or modify
34546 + * it under the terms of the GNU General Public License version 2 as
34547 + * published by the Free Software Foundation.
34548 + *
34549 +*/
34550 +
34551 +#include <linux/kernel.h>
34552 +#include <linux/types.h>
34553 +#include <linux/interrupt.h>
34554 +#include <linux/list.h>
34555 +#include <linux/platform_device.h>
34556 +
34557 +#include <asm/mach/arch.h>
34558 +#include <asm/mach/irq.h>
34559 +#include <mach/hardware.h>
34560 +#include <mach/map.h>
34561 +
34562 +#include <plat/devs.h>
34563 +
34564 +/* Serial port registrations */
34565 +
34566 +/* 64xx uarts are closer together */
34567 +
34568 +static struct resource s3c64xx_uart0_resource[] = {
34569 +       [0] = {
34570 +               .start  = S3C_PA_UART0,
34571 +               .end    = S3C_PA_UART0 + 0x100,
34572 +               .flags  = IORESOURCE_MEM,
34573 +       },
34574 +       [1] = {
34575 +               .start  = IRQ_S3CUART_RX0,
34576 +               .end    = IRQ_S3CUART_RX0,
34577 +               .flags  = IORESOURCE_IRQ,
34578 +       },
34579 +       [2] = {
34580 +               .start  = IRQ_S3CUART_TX0,
34581 +               .end    = IRQ_S3CUART_TX0,
34582 +               .flags  = IORESOURCE_IRQ,
34583 +
34584 +       },
34585 +       [3] = {
34586 +               .start  = IRQ_S3CUART_ERR0,
34587 +               .end    = IRQ_S3CUART_ERR0,
34588 +               .flags  = IORESOURCE_IRQ,
34589 +       }
34590 +};
34591 +
34592 +static struct resource s3c64xx_uart1_resource[] = {
34593 +       [0] = {
34594 +               .start = S3C_PA_UART1,
34595 +               .end   = S3C_PA_UART1 + 0x100,
34596 +               .flags = IORESOURCE_MEM,
34597 +       },
34598 +       [1] = {
34599 +               .start  = IRQ_S3CUART_RX1,
34600 +               .end    = IRQ_S3CUART_RX1,
34601 +               .flags  = IORESOURCE_IRQ,
34602 +       },
34603 +       [2] = {
34604 +               .start  = IRQ_S3CUART_TX1,
34605 +               .end    = IRQ_S3CUART_TX1,
34606 +               .flags  = IORESOURCE_IRQ,
34607 +
34608 +       },
34609 +       [3] = {
34610 +               .start  = IRQ_S3CUART_ERR1,
34611 +               .end    = IRQ_S3CUART_ERR1,
34612 +               .flags  = IORESOURCE_IRQ,
34613 +       },
34614 +};
34615 +
34616 +static struct resource s3c6xx_uart2_resource[] = {
34617 +       [0] = {
34618 +               .start = S3C_PA_UART2,
34619 +               .end   = S3C_PA_UART2 + 0x100,
34620 +               .flags = IORESOURCE_MEM,
34621 +       },
34622 +       [1] = {
34623 +               .start  = IRQ_S3CUART_RX2,
34624 +               .end    = IRQ_S3CUART_RX2,
34625 +               .flags  = IORESOURCE_IRQ,
34626 +       },
34627 +       [2] = {
34628 +               .start  = IRQ_S3CUART_TX2,
34629 +               .end    = IRQ_S3CUART_TX2,
34630 +               .flags  = IORESOURCE_IRQ,
34631 +
34632 +       },
34633 +       [3] = {
34634 +               .start  = IRQ_S3CUART_ERR2,
34635 +               .end    = IRQ_S3CUART_ERR2,
34636 +               .flags  = IORESOURCE_IRQ,
34637 +       },
34638 +};
34639 +
34640 +static struct resource s3c64xx_uart3_resource[] = {
34641 +       [0] = {
34642 +               .start = S3C_PA_UART3,
34643 +               .end   = S3C_PA_UART3 + 0x100,
34644 +               .flags = IORESOURCE_MEM,
34645 +       },
34646 +       [1] = {
34647 +               .start  = IRQ_S3CUART_RX3,
34648 +               .end    = IRQ_S3CUART_RX3,
34649 +               .flags  = IORESOURCE_IRQ,
34650 +       },
34651 +       [2] = {
34652 +               .start  = IRQ_S3CUART_TX3,
34653 +               .end    = IRQ_S3CUART_TX3,
34654 +               .flags  = IORESOURCE_IRQ,
34655 +
34656 +       },
34657 +       [3] = {
34658 +               .start  = IRQ_S3CUART_ERR3,
34659 +               .end    = IRQ_S3CUART_ERR3,
34660 +               .flags  = IORESOURCE_IRQ,
34661 +       },
34662 +};
34663 +
34664 +
34665 +struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = {
34666 +       [0] = {
34667 +               .resources      = s3c64xx_uart0_resource,
34668 +               .nr_resources   = ARRAY_SIZE(s3c64xx_uart0_resource),
34669 +       },
34670 +       [1] = {
34671 +               .resources      = s3c64xx_uart1_resource,
34672 +               .nr_resources   = ARRAY_SIZE(s3c64xx_uart1_resource),
34673 +       },
34674 +       [2] = {
34675 +               .resources      = s3c6xx_uart2_resource,
34676 +               .nr_resources   = ARRAY_SIZE(s3c6xx_uart2_resource),
34677 +       },
34678 +       [3] = {
34679 +               .resources      = s3c64xx_uart3_resource,
34680 +               .nr_resources   = ARRAY_SIZE(s3c64xx_uart3_resource),
34681 +       },
34682 +};
34683 +
34684 +/* uart devices */
34685 +
34686 +static struct platform_device s3c24xx_uart_device0 = {
34687 +       .id             = 0,
34688 +};
34689 +
34690 +static struct platform_device s3c24xx_uart_device1 = {
34691 +       .id             = 1,
34692 +};
34693 +
34694 +static struct platform_device s3c24xx_uart_device2 = {
34695 +       .id             = 2,
34696 +};
34697 +
34698 +static struct platform_device s3c24xx_uart_device3 = {
34699 +       .id             = 3,
34700 +};
34701 +
34702 +struct platform_device *s3c24xx_uart_src[4] = {
34703 +       &s3c24xx_uart_device0,
34704 +       &s3c24xx_uart_device1,
34705 +       &s3c24xx_uart_device2,
34706 +       &s3c24xx_uart_device3,
34707 +};
34708 +
34709 +struct platform_device *s3c24xx_uart_devs[4] = {
34710 +};
34711 +
34712 Index: linux-2.6.28/arch/arm/plat-s3c64xx/gpiolib.c
34713 ===================================================================
34714 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
34715 +++ linux-2.6.28/arch/arm/plat-s3c64xx/gpiolib.c        2009-01-02 00:01:56.000000000 +0100
34716 @@ -0,0 +1,428 @@
34717 +/* arch/arm/plat-s3c64xx/gpiolib.c
34718 + *
34719 + * Copyright 2008 Openmoko, Inc.
34720 + * Copyright 2008 Simtec Electronics
34721 + *      Ben Dooks <ben@simtec.co.uk>
34722 + *      http://armlinux.simtec.co.uk/
34723 + *
34724 + * S3C64XX - GPIOlib support
34725 + *
34726 + * This program is free software; you can redistribute it and/or modify
34727 + * it under the terms of the GNU General Public License version 2 as
34728 + * published by the Free Software Foundation.
34729 + */
34730 +
34731 +#include <linux/kernel.h>
34732 +#include <linux/irq.h>
34733 +#include <linux/io.h>
34734 +
34735 +#include <mach/map.h>
34736 +#include <mach/gpio.h>
34737 +#include <mach/gpio-core.h>
34738 +
34739 +#include <plat/gpio-cfg.h>
34740 +#include <plat/gpio-cfg-helpers.h>
34741 +#include <plat/regs-gpio.h>
34742 +
34743 +/* GPIO bank summary:
34744 + *
34745 + * Bank        GPIOs   Style   SlpCon  ExtInt Group
34746 + * A   8       4Bit    Yes     1
34747 + * B   7       4Bit    Yes     1
34748 + * C   8       4Bit    Yes     2
34749 + * D   5       4Bit    Yes     3
34750 + * E   5       4Bit    Yes     None
34751 + * F   16      2Bit    Yes     4 [1]
34752 + * G   7       4Bit    Yes     5
34753 + * H   10      4Bit[2] Yes     6
34754 + * I   16      2Bit    Yes     None
34755 + * J   12      2Bit    Yes     None
34756 + * K   16      4Bit[2] No      None
34757 + * L   15      4Bit[2] No      None
34758 + * M   6       4Bit    No      IRQ_EINT
34759 + * N   16      2Bit    No      IRQ_EINT
34760 + * O   16      2Bit    Yes     7
34761 + * P   15      2Bit    Yes     8
34762 + * Q   9       2Bit    Yes     9
34763 + *
34764 + * [1] BANKF pins 14,15 do not form part of the external interrupt sources
34765 + * [2] BANK has two control registers, GPxCON0 and GPxCON1
34766 + */
34767 +
34768 +#define OFF_GPCON      (0x00)
34769 +#define OFF_GPDAT      (0x04)
34770 +
34771 +#define con_4bit_shift(__off) ((__off) * 4)
34772 +
34773 +#if 1
34774 +#define gpio_dbg(x...) do { } while(0)
34775 +#else
34776 +#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
34777 +#endif
34778 +
34779 +/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
34780 + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
34781 + * following example:
34782 + *
34783 + * base + 0x00: Control register, 4 bits per gpio
34784 + *             gpio n: 4 bits starting at (4*n)
34785 + *             0000 = input, 0001 = output, others mean special-function
34786 + * base + 0x04: Data register, 1 bit per gpio
34787 + *             bit n: data bit n
34788 + *
34789 + * Note, since the data register is one bit per gpio and is at base + 0x4
34790 + * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
34791 + * the output.
34792 +*/
34793 +
34794 +static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
34795 +{
34796 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34797 +       void __iomem *base = ourchip->base;
34798 +       unsigned long con;
34799 +
34800 +       con = __raw_readl(base + OFF_GPCON);
34801 +       con &= ~(0xf << con_4bit_shift(offset));
34802 +       __raw_writel(con, base + OFF_GPCON);
34803 +
34804 +       gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
34805 +
34806 +       return 0;
34807 +}
34808 +
34809 +static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
34810 +                                      unsigned offset, int value)
34811 +{
34812 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34813 +       void __iomem *base = ourchip->base;
34814 +       unsigned long con;
34815 +       unsigned long dat;
34816 +
34817 +       con = __raw_readl(base + OFF_GPCON);
34818 +       con &= ~(0xf << con_4bit_shift(offset));
34819 +       con |= 0x1 << con_4bit_shift(offset);
34820 +
34821 +       dat = __raw_readl(base + OFF_GPDAT);
34822 +       if (value)
34823 +               dat |= 1 << offset;
34824 +       else
34825 +               dat &= ~(1 << offset);
34826 +
34827 +       __raw_writel(dat, base + OFF_GPDAT);
34828 +       __raw_writel(con, base + OFF_GPCON);
34829 +       __raw_writel(dat, base + OFF_GPDAT);
34830 +
34831 +       gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
34832 +
34833 +       return 0;
34834 +}
34835 +
34836 +/* The next set of routines are for the case where the GPIO configuration
34837 + * registers are 4 bits per GPIO but there is more than one register (the
34838 + * bank has more than 8 GPIOs.
34839 + *
34840 + * This case is the similar to the 4 bit case, but the registers are as
34841 + * follows:
34842 + *
34843 + * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
34844 + *             gpio n: 4 bits starting at (4*n)
34845 + *             0000 = input, 0001 = output, others mean special-function
34846 + * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
34847 + *             gpio n: 4 bits starting at (4*n)
34848 + *             0000 = input, 0001 = output, others mean special-function
34849 + * base + 0x08: Data register, 1 bit per gpio
34850 + *             bit n: data bit n
34851 + *
34852 + * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
34853 + * store the 'base + 0x4' address so that these routines see the data
34854 + * register at ourchip->base + 0x04.
34855 +*/
34856 +
34857 +static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
34858 +{
34859 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34860 +       void __iomem *base = ourchip->base;
34861 +       void __iomem *regcon = base;
34862 +       unsigned long con;
34863 +
34864 +       if (offset > 7)
34865 +               offset -= 8;
34866 +       else
34867 +               regcon -= 4;
34868 +
34869 +       con = __raw_readl(regcon);
34870 +       con &= ~(0xf << con_4bit_shift(offset));
34871 +       __raw_writel(con, regcon);
34872 +
34873 +       gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
34874 +
34875 +       return 0;
34876 +
34877 +}
34878 +
34879 +static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
34880 +                                      unsigned offset, int value)
34881 +{
34882 +       struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
34883 +       void __iomem *base = ourchip->base;
34884 +       void __iomem *regcon = base;
34885 +       unsigned long con;
34886 +       unsigned long dat;
34887 +
34888 +       if (offset > 7)
34889 +               offset -= 8;
34890 +       else
34891 +               regcon -= 4;
34892 +
34893 +       con = __raw_readl(regcon);
34894 +       con &= ~(0xf << con_4bit_shift(offset));
34895 +       con |= 0x1 << con_4bit_shift(offset);
34896 +
34897 +       dat = __raw_readl(base + OFF_GPDAT);
34898 +       if (value)
34899 +               dat |= 1 << offset;
34900 +       else
34901 +               dat &= ~(1 << offset);
34902 +
34903 +       __raw_writel(dat, base + OFF_GPDAT);
34904 +       __raw_writel(con, regcon);
34905 +       __raw_writel(dat, base + OFF_GPDAT);
34906 +
34907 +       gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
34908 +
34909 +       return 0;
34910 +}
34911 +
34912 +static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
34913 +       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
34914 +       .set_pull       = s3c_gpio_setpull_updown,
34915 +       .get_pull       = s3c_gpio_getpull_updown,
34916 +};
34917 +
34918 +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
34919 +       .cfg_eint       = 7,
34920 +       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
34921 +       .set_pull       = s3c_gpio_setpull_updown,
34922 +       .get_pull       = s3c_gpio_getpull_updown,
34923 +};
34924 +
34925 +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
34926 +       .cfg_eint       = 3,
34927 +       .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
34928 +       .set_pull       = s3c_gpio_setpull_updown,
34929 +       .get_pull       = s3c_gpio_getpull_updown,
34930 +};
34931 +
34932 +static struct s3c_gpio_chip gpio_4bit[] = {
34933 +       {
34934 +               .base   = S3C64XX_GPA_BASE,
34935 +               .config = &gpio_4bit_cfg_eint0111,
34936 +               .chip   = {
34937 +                       .base   = S3C64XX_GPA(0),
34938 +                       .ngpio  = S3C64XX_GPIO_A_NR,
34939 +                       .label  = "GPA",
34940 +               },
34941 +       }, {
34942 +               .base   = S3C64XX_GPB_BASE,
34943 +               .config = &gpio_4bit_cfg_eint0111,
34944 +               .chip   = {
34945 +                       .base   = S3C64XX_GPB(0),
34946 +                       .ngpio  = S3C64XX_GPIO_B_NR,
34947 +                       .label  = "GPB",
34948 +               },
34949 +       }, {
34950 +               .base   = S3C64XX_GPC_BASE,
34951 +               .config = &gpio_4bit_cfg_eint0111,
34952 +               .chip   = {
34953 +                       .base   = S3C64XX_GPC(0),
34954 +                       .ngpio  = S3C64XX_GPIO_C_NR,
34955 +                       .label  = "GPC",
34956 +               },
34957 +       }, {
34958 +               .base   = S3C64XX_GPD_BASE,
34959 +               .config = &gpio_4bit_cfg_eint0111,
34960 +               .chip   = {
34961 +                       .base   = S3C64XX_GPD(0),
34962 +                       .ngpio  = S3C64XX_GPIO_D_NR,
34963 +                       .label  = "GPD",
34964 +               },
34965 +       }, {
34966 +               .base   = S3C64XX_GPE_BASE,
34967 +               .config = &gpio_4bit_cfg_noint,
34968 +               .chip   = {
34969 +                       .base   = S3C64XX_GPE(0),
34970 +                       .ngpio  = S3C64XX_GPIO_E_NR,
34971 +                       .label  = "GPE",
34972 +               },
34973 +       }, {
34974 +               .base   = S3C64XX_GPG_BASE,
34975 +               .config = &gpio_4bit_cfg_eint0111,
34976 +               .chip   = {
34977 +                       .base   = S3C64XX_GPG(0),
34978 +                       .ngpio  = S3C64XX_GPIO_G_NR,
34979 +                       .label  = "GPG",
34980 +               },
34981 +       }, {
34982 +               .base   = S3C64XX_GPM_BASE,
34983 +               .config = &gpio_4bit_cfg_eint0011,
34984 +               .chip   = {
34985 +                       .base   = S3C64XX_GPM(0),
34986 +                       .ngpio  = S3C64XX_GPIO_M_NR,
34987 +                       .label  = "GPM",
34988 +               },
34989 +       },
34990 +};
34991 +
34992 +static struct s3c_gpio_chip gpio_4bit2[] = {
34993 +       {
34994 +               .base   = S3C64XX_GPH_BASE + 0x4,
34995 +               .config = &gpio_4bit_cfg_eint0111,
34996 +               .chip   = {
34997 +                       .base   = S3C64XX_GPH(0),
34998 +                       .ngpio  = S3C64XX_GPIO_H_NR,
34999 +                       .label  = "GPH",
35000 +               },
35001 +       }, {
35002 +               .base   = S3C64XX_GPK_BASE + 0x4,
35003 +               .config = &gpio_4bit_cfg_noint,
35004 +               .chip   = {
35005 +                       .base   = S3C64XX_GPK(0),
35006 +                       .ngpio  = S3C64XX_GPIO_K_NR,
35007 +                       .label  = "GPK",
35008 +               },
35009 +       }, {
35010 +               .base   = S3C64XX_GPL_BASE + 0x4,
35011 +               .config = &gpio_4bit_cfg_eint0011,
35012 +               .chip   = {
35013 +                       .base   = S3C64XX_GPL(0),
35014 +                       .ngpio  = S3C64XX_GPIO_L_NR,
35015 +                       .label  = "GPL",
35016 +               },
35017 +       },
35018 +};
35019 +
35020 +static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
35021 +       .set_config     = s3c_gpio_setcfg_s3c24xx,
35022 +       .set_pull       = s3c_gpio_setpull_updown,
35023 +       .get_pull       = s3c_gpio_getpull_updown,
35024 +};
35025 +
35026 +static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
35027 +       .cfg_eint       = 2,
35028 +       .set_config     = s3c_gpio_setcfg_s3c24xx,
35029 +       .set_pull       = s3c_gpio_setpull_updown,
35030 +       .get_pull       = s3c_gpio_getpull_updown,
35031 +};
35032 +
35033 +static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
35034 +       .cfg_eint       = 3,
35035 +       .set_config     = s3c_gpio_setcfg_s3c24xx,
35036 +       .set_pull       = s3c_gpio_setpull_updown,
35037 +       .get_pull       = s3c_gpio_getpull_updown,
35038 +};
35039 +
35040 +static struct s3c_gpio_chip gpio_2bit[] = {
35041 +       {
35042 +               .base   = S3C64XX_GPF_BASE,
35043 +               .config = &gpio_2bit_cfg_eint11,
35044 +               .chip   = {
35045 +                       .base   = S3C64XX_GPF(0),
35046 +                       .ngpio  = S3C64XX_GPIO_F_NR,
35047 +                       .label  = "GPF",
35048 +               },
35049 +       }, {
35050 +               .base   = S3C64XX_GPI_BASE,
35051 +               .config = &gpio_2bit_cfg_noint,
35052 +               .chip   = {
35053 +                       .base   = S3C64XX_GPI(0),
35054 +                       .ngpio  = S3C64XX_GPIO_I_NR,
35055 +                       .label  = "GPI",
35056 +               },
35057 +       }, {
35058 +               .base   = S3C64XX_GPJ_BASE,
35059 +               .config = &gpio_2bit_cfg_noint,
35060 +               .chip   = {
35061 +                       .base   = S3C64XX_GPJ(0),
35062 +                       .ngpio  = S3C64XX_GPIO_J_NR,
35063 +                       .label  = "GPJ",
35064 +               },
35065 +       }, {
35066 +               .base   = S3C64XX_GPN_BASE,
35067 +               .config = &gpio_2bit_cfg_eint10,
35068 +               .chip   = {
35069 +                       .base   = S3C64XX_GPN(0),
35070 +                       .ngpio  = S3C64XX_GPIO_N_NR,
35071 +                       .label  = "GPN",
35072 +               },
35073 +       }, {
35074 +               .base   = S3C64XX_GPO_BASE,
35075 +               .config = &gpio_2bit_cfg_eint11,
35076 +               .chip   = {
35077 +                       .base   = S3C64XX_GPO(0),
35078 +                       .ngpio  = S3C64XX_GPIO_O_NR,
35079 +                       .label  = "GPO",
35080 +               },
35081 +       }, {
35082 +               .base   = S3C64XX_GPP_BASE,
35083 +               .config = &gpio_2bit_cfg_eint11,
35084 +               .chip   = {
35085 +                       .base   = S3C64XX_GPP(0),
35086 +                       .ngpio  = S3C64XX_GPIO_P_NR,
35087 +                       .label  = "GPP",
35088 +               },
35089 +       }, {
35090 +               .base   = S3C64XX_GPQ_BASE,
35091 +               .config = &gpio_2bit_cfg_eint11,
35092 +               .chip   = {
35093 +                       .base   = S3C64XX_GPQ(0),
35094 +                       .ngpio  = S3C64XX_GPIO_Q_NR,
35095 +                       .label  = "GPQ",
35096 +               },
35097 +       },
35098 +};
35099 +
35100 +static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
35101 +{
35102 +       chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
35103 +       chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
35104 +       chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
35105 +}
35106 +
35107 +static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
35108 +{
35109 +       chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
35110 +       chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
35111 +       chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
35112 +}
35113 +
35114 +static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
35115 +{
35116 +       chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
35117 +}
35118 +
35119 +static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
35120 +                                      int nr_chips,
35121 +                                      void (*fn)(struct s3c_gpio_chip *))
35122 +{
35123 +       for (; nr_chips > 0; nr_chips--, chips++) {
35124 +               if (fn)
35125 +                       (fn)(chips);
35126 +               s3c_gpiolib_add(chips);
35127 +       }
35128 +}
35129 +
35130 +static __init int s3c64xx_gpiolib_init(void)
35131 +{
35132 +       s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
35133 +                           s3c64xx_gpiolib_add_4bit);
35134 +
35135 +       s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
35136 +                           s3c64xx_gpiolib_add_4bit2);
35137 +
35138 +       s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
35139 +                           s3c64xx_gpiolib_add_2bit);
35140 +
35141 +       return 0;
35142 +}
35143 +
35144 +arch_initcall(s3c64xx_gpiolib_init);
35145 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
35146 ===================================================================
35147 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35148 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h       2009-01-02 00:01:56.000000000 +0100
35149 @@ -0,0 +1,48 @@
35150 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
35151 + *
35152 + * Copyright 2008 Openmoko, Inc.
35153 + * Copyright 2008 Simtec Electronics
35154 + *     Ben Dooks <ben@simtec.co.uk>
35155 + *     http://armlinux.simtec.co.uk/
35156 + *
35157 + * GPIO Bank A register and configuration definitions
35158 + *
35159 + * This program is free software; you can redistribute it and/or modify
35160 + * it under the terms of the GNU General Public License version 2 as
35161 + * published by the Free Software Foundation.
35162 +*/
35163 +
35164 +#define S3C64XX_GPACON                 (S3C64XX_GPA_BASE + 0x00)
35165 +#define S3C64XX_GPADAT                 (S3C64XX_GPA_BASE + 0x04)
35166 +#define S3C64XX_GPAPUD                 (S3C64XX_GPA_BASE + 0x08)
35167 +#define S3C64XX_GPACONSLP              (S3C64XX_GPA_BASE + 0x0c)
35168 +#define S3C64XX_GPAPUDSLP              (S3C64XX_GPA_BASE + 0x10)
35169 +
35170 +#define S3C64XX_GPA_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35171 +#define S3C64XX_GPA_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35172 +#define S3C64XX_GPA_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35173 +
35174 +#define S3C64XX_GPA0_UART_RXD0         (0x02 << 0)
35175 +#define S3C64XX_GPA0_EINT_G1_0         (0x07 << 0)
35176 +
35177 +#define S3C64XX_GPA1_UART_TXD0         (0x02 << 4)
35178 +#define S3C64XX_GPA1_EINT_G1_1         (0x07 << 4)
35179 +
35180 +#define S3C64XX_GPA2_UART_nCTS0                (0x02 << 8)
35181 +#define S3C64XX_GPA2_EINT_G1_2         (0x07 << 8)
35182 +
35183 +#define S3C64XX_GPA3_UART_nRTS0                (0x02 << 12)
35184 +#define S3C64XX_GPA3_EINT_G1_3         (0x07 << 12)
35185 +
35186 +#define S3C64XX_GPA4_UART_RXD1         (0x02 << 16)
35187 +#define S3C64XX_GPA4_EINT_G1_4         (0x07 << 16)
35188 +
35189 +#define S3C64XX_GPA5_UART_TXD1         (0x02 << 20)
35190 +#define S3C64XX_GPA5_EINT_G1_5         (0x07 << 20)
35191 +
35192 +#define S3C64XX_GPA6_UART_nCTS1                (0x02 << 24)
35193 +#define S3C64XX_GPA6_EINT_G1_6         (0x07 << 24)
35194 +
35195 +#define S3C64XX_GPA7_UART_nRTS1                (0x02 << 28)
35196 +#define S3C64XX_GPA7_EINT_G1_7         (0x07 << 28)
35197 +
35198 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
35199 ===================================================================
35200 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35201 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h       2009-01-02 00:01:56.000000000 +0100
35202 @@ -0,0 +1,60 @@
35203 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
35204 + *
35205 + * Copyright 2008 Openmoko, Inc.
35206 + * Copyright 2008 Simtec Electronics
35207 + *     Ben Dooks <ben@simtec.co.uk>
35208 + *     http://armlinux.simtec.co.uk/
35209 + *
35210 + * GPIO Bank B register and configuration definitions
35211 + *
35212 + * This program is free software; you can redistribute it and/or modify
35213 + * it under the terms of the GNU General Public License version 2 as
35214 + * published by the Free Software Foundation.
35215 +*/
35216 +
35217 +#define S3C64XX_GPBCON                 (S3C64XX_GPB_BASE + 0x00)
35218 +#define S3C64XX_GPBDAT                 (S3C64XX_GPB_BASE + 0x04)
35219 +#define S3C64XX_GPBPUD                 (S3C64XX_GPB_BASE + 0x08)
35220 +#define S3C64XX_GPBCONSLP              (S3C64XX_GPB_BASE + 0x0c)
35221 +#define S3C64XX_GPBPUDSLP              (S3C64XX_GPB_BASE + 0x10)
35222 +
35223 +#define S3C64XX_GPB_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35224 +#define S3C64XX_GPB_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35225 +#define S3C64XX_GPB_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35226 +
35227 +#define S3C64XX_GPB0_UART_RXD2         (0x02 << 0)
35228 +#define S3C64XX_GPB0_EXTDMA_REQ                (0x03 << 0)
35229 +#define S3C64XX_GPB0_IrDA_RXD          (0x04 << 0)
35230 +#define S3C64XX_GPB0_ADDR_CF0          (0x05 << 0)
35231 +#define S3C64XX_GPB0_EINT_G1_8         (0x07 << 0)
35232 +
35233 +#define S3C64XX_GPB1_UART_TXD2         (0x02 << 4)
35234 +#define S3C64XX_GPB1_EXTDMA_ACK                (0x03 << 4)
35235 +#define S3C64XX_GPB1_IrDA_TXD          (0x04 << 4)
35236 +#define S3C64XX_GPB1_ADDR_CF1          (0x05 << 4)
35237 +#define S3C64XX_GPB1_EINT_G1_9         (0x07 << 4)
35238 +
35239 +#define S3C64XX_GPB2_UART_RXD3         (0x02 << 8)
35240 +#define S3C64XX_GPB2_IrDA_RXD          (0x03 << 8)
35241 +#define S3C64XX_GPB2_EXTDMA_REQ                (0x04 << 8)
35242 +#define S3C64XX_GPB2_ADDR_CF2          (0x05 << 8)
35243 +#define S3C64XX_GPB2_I2C_SCL1          (0x06 << 8)
35244 +#define S3C64XX_GPB2_EINT_G1_10                (0x07 << 8)
35245 +
35246 +#define S3C64XX_GPB3_UART_TXD3         (0x02 << 12)
35247 +#define S3C64XX_GPB3_IrDA_TXD          (0x03 << 12)
35248 +#define S3C64XX_GPB3_EXTDMA_ACK                (0x04 << 12)
35249 +#define S3C64XX_GPB3_I2C_SDA1          (0x06 << 12)
35250 +#define S3C64XX_GPB3_EINT_G1_11                (0x07 << 12)
35251 +
35252 +#define S3C64XX_GPB4_IrDA_SDBW         (0x02 << 16)
35253 +#define S3C64XX_GPB4_CAM_FIELD         (0x03 << 16)
35254 +#define S3C64XX_GPB4_CF_DATA_DIR       (0x04 << 16)
35255 +#define S3C64XX_GPB4_EINT_G1_12                (0x07 << 16)
35256 +
35257 +#define S3C64XX_GPB5_I2C_SCL0          (0x02 << 20)
35258 +#define S3C64XX_GPB5_EINT_G1_13                (0x07 << 20)
35259 +
35260 +#define S3C64XX_GPB6_I2C_SDA0          (0x02 << 24)
35261 +#define S3C64XX_GPB6_EINT_G1_14                (0x07 << 24)
35262 +
35263 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
35264 ===================================================================
35265 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35266 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h       2009-01-02 00:01:56.000000000 +0100
35267 @@ -0,0 +1,53 @@
35268 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
35269 + *
35270 + * Copyright 2008 Openmoko, Inc.
35271 + * Copyright 2008 Simtec Electronics
35272 + *     Ben Dooks <ben@simtec.co.uk>
35273 + *     http://armlinux.simtec.co.uk/
35274 + *
35275 + * GPIO Bank C register and configuration definitions
35276 + *
35277 + * This program is free software; you can redistribute it and/or modify
35278 + * it under the terms of the GNU General Public License version 2 as
35279 + * published by the Free Software Foundation.
35280 +*/
35281 +
35282 +#define S3C64XX_GPCCON                 (S3C64XX_GPC_BASE + 0x00)
35283 +#define S3C64XX_GPCDAT                 (S3C64XX_GPC_BASE + 0x04)
35284 +#define S3C64XX_GPCPUD                 (S3C64XX_GPC_BASE + 0x08)
35285 +#define S3C64XX_GPCCONSLP              (S3C64XX_GPC_BASE + 0x0c)
35286 +#define S3C64XX_GPCPUDSLP              (S3C64XX_GPC_BASE + 0x10)
35287 +
35288 +#define S3C64XX_GPC_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35289 +#define S3C64XX_GPC_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35290 +#define S3C64XX_GPC_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35291 +
35292 +#define S3C64XX_GPC0_SPI_MISO0         (0x02 << 0)
35293 +#define S3C64XX_GPC0_EINT_G2_0         (0x07 << 0)
35294 +
35295 +#define S3C64XX_GPC1_SPI_CLKO          (0x02 << 4)
35296 +#define S3C64XX_GPC1_EINT_G2_1         (0x07 << 4)
35297 +
35298 +#define S3C64XX_GPC2_SPI_MOSIO         (0x02 << 8)
35299 +#define S3C64XX_GPC2_EINT_G2_2         (0x07 << 8)
35300 +
35301 +#define S3C64XX_GPC3_SPI_nCSO          (0x02 << 12)
35302 +#define S3C64XX_GPC3_EINT_G2_3         (0x07 << 12)
35303 +
35304 +#define S3C64XX_GPC4_SPI_MISO1         (0x02 << 16)
35305 +#define S3C64XX_GPC4_MMC2_CMD          (0x03 << 16)
35306 +#define S3C64XX_GPC4_I2S0_V40_DO       (0x05 << 16)
35307 +#define S3C64XX_GPC4_EINT_G2_4         (0x07 << 16)
35308 +
35309 +#define S3C64XX_GPC5_SPI_CLK1          (0x02 << 20)
35310 +#define S3C64XX_GPC5_MMC2_CLK          (0x03 << 20)
35311 +#define S3C64XX_GPC5_I2S1_V40_DO       (0x05 << 20)
35312 +#define S3C64XX_GPC5_EINT_G2_5         (0x07 << 20)
35313 +
35314 +#define S3C64XX_GPC6_SPI_MOSI1         (0x02 << 24)
35315 +#define S3C64XX_GPC6_EINT_G2_6         (0x07 << 24)
35316 +
35317 +#define S3C64XX_GPC7_SPI_nCS1          (0x02 << 28)
35318 +#define S3C64XX_GPC7_I2S2_V40_DO       (0x05 << 28)
35319 +#define S3C64XX_GPC7_EINT_G2_7         (0x07 << 28)
35320 +
35321 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
35322 ===================================================================
35323 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35324 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h       2009-01-02 00:01:56.000000000 +0100
35325 @@ -0,0 +1,49 @@
35326 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
35327 + *
35328 + * Copyright 2008 Openmoko, Inc.
35329 + * Copyright 2008 Simtec Electronics
35330 + *     Ben Dooks <ben@simtec.co.uk>
35331 + *     http://armlinux.simtec.co.uk/
35332 + *
35333 + * GPIO Bank D register and configuration definitions
35334 + *
35335 + * This program is free software; you can redistribute it and/or modify
35336 + * it under the terms of the GNU General Public License version 2 as
35337 + * published by the Free Software Foundation.
35338 +*/
35339 +
35340 +#define S3C64XX_GPDCON                 (S3C64XX_GPD_BASE + 0x00)
35341 +#define S3C64XX_GPDDAT                 (S3C64XX_GPD_BASE + 0x04)
35342 +#define S3C64XX_GPDPUD                 (S3C64XX_GPD_BASE + 0x08)
35343 +#define S3C64XX_GPDCONSLP              (S3C64XX_GPD_BASE + 0x0c)
35344 +#define S3C64XX_GPDPUDSLP              (S3C64XX_GPD_BASE + 0x10)
35345 +
35346 +#define S3C64XX_GPD_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35347 +#define S3C64XX_GPD_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35348 +#define S3C64XX_GPD_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35349 +
35350 +#define S3C64XX_GPD0_PCM0_SCLK         (0x02 << 0)
35351 +#define S3C64XX_GPD0_I2S0_CLK          (0x03 << 0)
35352 +#define S3C64XX_GPD0_AC97_BITCLK       (0x04 << 0)
35353 +#define S3C64XX_GPD0_EINT_G3_0         (0x07 << 0)
35354 +
35355 +#define S3C64XX_GPD1_PCM0_EXTCLK       (0x02 << 4)
35356 +#define S3C64XX_GPD1_I2S0_CDCLK                (0x03 << 4)
35357 +#define S3C64XX_GPD1_AC97_nRESET       (0x04 << 4)
35358 +#define S3C64XX_GPD1_EINT_G3_1         (0x07 << 4)
35359 +
35360 +#define S3C64XX_GPD2_PCM0_FSYNC                (0x02 << 8)
35361 +#define S3C64XX_GPD2_I2S0_LRCLK                (0x03 << 8)
35362 +#define S3C64XX_GPD2_AC97_SYNC         (0x04 << 8)
35363 +#define S3C64XX_GPD2_EINT_G3_2         (0x07 << 8)
35364 +
35365 +#define S3C64XX_GPD3_PCM0_SIN          (0x02 << 12)
35366 +#define S3C64XX_GPD3_I2S0_DI           (0x03 << 12)
35367 +#define S3C64XX_GPD3_AC97_SDI          (0x04 << 12)
35368 +#define S3C64XX_GPD3_EINT_G3_3         (0x07 << 12)
35369 +
35370 +#define S3C64XX_GPD4_PCM0_SOUT         (0x02 << 16)
35371 +#define S3C64XX_GPD4_I2S0_D0           (0x03 << 16)
35372 +#define S3C64XX_GPD4_AC97_SDO          (0x04 << 16)
35373 +#define S3C64XX_GPD4_EINT_G3_4         (0x07 << 16)
35374 +
35375 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
35376 ===================================================================
35377 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35378 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h       2009-01-02 00:01:56.000000000 +0100
35379 @@ -0,0 +1,44 @@
35380 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
35381 + *
35382 + * Copyright 2008 Openmoko, Inc.
35383 + * Copyright 2008 Simtec Electronics
35384 + *     Ben Dooks <ben@simtec.co.uk>
35385 + *     http://armlinux.simtec.co.uk/
35386 + *
35387 + * GPIO Bank E register and configuration definitions
35388 + *
35389 + * This program is free software; you can redistribute it and/or modify
35390 + * it under the terms of the GNU General Public License version 2 as
35391 + * published by the Free Software Foundation.
35392 +*/
35393 +
35394 +#define S3C64XX_GPECON                 (S3C64XX_GPE_BASE + 0x00)
35395 +#define S3C64XX_GPEDAT                 (S3C64XX_GPE_BASE + 0x04)
35396 +#define S3C64XX_GPEPUD                 (S3C64XX_GPE_BASE + 0x08)
35397 +#define S3C64XX_GPECONSLP              (S3C64XX_GPE_BASE + 0x0c)
35398 +#define S3C64XX_GPEPUDSLP              (S3C64XX_GPE_BASE + 0x10)
35399 +
35400 +#define S3C64XX_GPE_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35401 +#define S3C64XX_GPE_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35402 +#define S3C64XX_GPE_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35403 +
35404 +#define S3C64XX_GPE0_PCM1_SCLK         (0x02 << 0)
35405 +#define S3C64XX_GPE0_I2S1_CLK          (0x03 << 0)
35406 +#define S3C64XX_GPE0_AC97_BITCLK       (0x04 << 0)
35407 +
35408 +#define S3C64XX_GPE1_PCM1_EXTCLK       (0x02 << 4)
35409 +#define S3C64XX_GPE1_I2S1_CDCLK                (0x03 << 4)
35410 +#define S3C64XX_GPE1_AC97_nRESET       (0x04 << 4)
35411 +
35412 +#define S3C64XX_GPE2_PCM1_FSYNC                (0x02 << 8)
35413 +#define S3C64XX_GPE2_I2S1_LRCLK                (0x03 << 8)
35414 +#define S3C64XX_GPE2_AC97_SYNC         (0x04 << 8)
35415 +
35416 +#define S3C64XX_GPE3_PCM1_SIN          (0x02 << 12)
35417 +#define S3C64XX_GPE3_I2S1_DI           (0x03 << 12)
35418 +#define S3C64XX_GPE3_AC97_SDI          (0x04 << 12)
35419 +
35420 +#define S3C64XX_GPE4_PCM1_SOUT         (0x02 << 16)
35421 +#define S3C64XX_GPE4_I2S1_D0           (0x03 << 16)
35422 +#define S3C64XX_GPE4_AC97_SDO          (0x04 << 16)
35423 +
35424 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
35425 ===================================================================
35426 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35427 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h       2009-01-02 00:01:56.000000000 +0100
35428 @@ -0,0 +1,71 @@
35429 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
35430 + *
35431 + * Copyright 2008 Openmoko, Inc.
35432 + * Copyright 2008 Simtec Electronics
35433 + *     Ben Dooks <ben@simtec.co.uk>
35434 + *     http://armlinux.simtec.co.uk/
35435 + *
35436 + * GPIO Bank F register and configuration definitions
35437 + *
35438 + * This program is free software; you can redistribute it and/or modify
35439 + * it under the terms of the GNU General Public License version 2 as
35440 + * published by the Free Software Foundation.
35441 +*/
35442 +
35443 +#define S3C64XX_GPFCON                 (S3C64XX_GPF_BASE + 0x00)
35444 +#define S3C64XX_GPFDAT                 (S3C64XX_GPF_BASE + 0x04)
35445 +#define S3C64XX_GPFPUD                 (S3C64XX_GPF_BASE + 0x08)
35446 +#define S3C64XX_GPFCONSLP              (S3C64XX_GPF_BASE + 0x0c)
35447 +#define S3C64XX_GPFPUDSLP              (S3C64XX_GPF_BASE + 0x10)
35448 +
35449 +#define S3C64XX_GPF_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35450 +#define S3C64XX_GPF_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35451 +#define S3C64XX_GPF_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35452 +
35453 +#define S3C64XX_GPF0_CAMIF_CLK         (0x02 << 0)
35454 +#define S3C64XX_GPF0_EINT_G4_0         (0x03 << 0)
35455 +
35456 +#define S3C64XX_GPF1_CAMIF_HREF                (0x02 << 2)
35457 +#define S3C64XX_GPF1_EINT_G4_1         (0x03 << 2)
35458 +
35459 +#define S3C64XX_GPF2_CAMIF_PCLK                (0x02 << 4)
35460 +#define S3C64XX_GPF2_EINT_G4_2         (0x03 << 4)
35461 +
35462 +#define S3C64XX_GPF3_CAMIF_nRST                (0x02 << 6)
35463 +#define S3C64XX_GPF3_EINT_G4_3         (0x03 << 6)
35464 +
35465 +#define S3C64XX_GPF4_CAMIF_VSYNC       (0x02 << 8)
35466 +#define S3C64XX_GPF4_EINT_G4_4         (0x03 << 8)
35467 +
35468 +#define S3C64XX_GPF5_CAMIF_YDATA0      (0x02 << 10)
35469 +#define S3C64XX_GPF5_EINT_G4_5         (0x03 << 10)
35470 +
35471 +#define S3C64XX_GPF6_CAMIF_YDATA1      (0x02 << 12)
35472 +#define S3C64XX_GPF6_EINT_G4_6         (0x03 << 12)
35473 +
35474 +#define S3C64XX_GPF7_CAMIF_YDATA2      (0x02 << 14)
35475 +#define S3C64XX_GPF7_EINT_G4_7         (0x03 << 14)
35476 +
35477 +#define S3C64XX_GPF8_CAMIF_YDATA3      (0x02 << 16)
35478 +#define S3C64XX_GPF8_EINT_G4_8         (0x03 << 16)
35479 +
35480 +#define S3C64XX_GPF9_CAMIF_YDATA4      (0x02 << 18)
35481 +#define S3C64XX_GPF9_EINT_G4_9         (0x03 << 18)
35482 +
35483 +#define S3C64XX_GPF10_CAMIF_YDATA5     (0x02 << 20)
35484 +#define S3C64XX_GPF10_EINT_G4_10       (0x03 << 20)
35485 +
35486 +#define S3C64XX_GPF11_CAMIF_YDATA6     (0x02 << 22)
35487 +#define S3C64XX_GPF11_EINT_G4_11       (0x03 << 22)
35488 +
35489 +#define S3C64XX_GPF12_CAMIF_YDATA7     (0x02 << 24)
35490 +#define S3C64XX_GPF12_EINT_G4_12       (0x03 << 24)
35491 +
35492 +#define S3C64XX_GPF13_PWM_ECLK         (0x02 << 26)
35493 +#define S3C64XX_GPF13_EINT_G4_13       (0x03 << 26)
35494 +
35495 +#define S3C64XX_GPF14_PWM_TOUT0                (0x02 << 28)
35496 +#define S3C64XX_GPF14_CLKOUT0          (0x03 << 28)
35497 +
35498 +#define S3C64XX_GPF15_PWM_TOUT1                (0x02 << 30)
35499 +
35500 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
35501 ===================================================================
35502 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35503 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h       2009-01-02 00:01:56.000000000 +0100
35504 @@ -0,0 +1,42 @@
35505 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
35506 + *
35507 + * Copyright 2008 Openmoko, Inc.
35508 + * Copyright 2008 Simtec Electronics
35509 + *     Ben Dooks <ben@simtec.co.uk>
35510 + *     http://armlinux.simtec.co.uk/
35511 + *
35512 + * GPIO Bank G register and configuration definitions
35513 + *
35514 + * This program is free software; you can redistribute it and/or modify
35515 + * it under the terms of the GNU General Public License version 2 as
35516 + * published by the Free Software Foundation.
35517 +*/
35518 +
35519 +#define S3C64XX_GPGCON                 (S3C64XX_GPG_BASE + 0x00)
35520 +#define S3C64XX_GPGDAT                 (S3C64XX_GPG_BASE + 0x04)
35521 +#define S3C64XX_GPGPUD                 (S3C64XX_GPG_BASE + 0x08)
35522 +#define S3C64XX_GPGCONSLP              (S3C64XX_GPG_BASE + 0x0c)
35523 +#define S3C64XX_GPGPUDSLP              (S3C64XX_GPG_BASE + 0x10)
35524 +
35525 +#define S3C64XX_GPG_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35526 +#define S3C64XX_GPG_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35527 +#define S3C64XX_GPG_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35528 +
35529 +#define S3C64XX_GPG0_MMC0_CLK          (0x02 << 0)
35530 +#define S3C64XX_GPG0_EINT_G5_0         (0x07 << 0)
35531 +
35532 +#define S3C64XX_GPG1_MMC0_CMD          (0x02 << 4)
35533 +#define S3C64XX_GPG1_EINT_G5_1         (0x07 << 4)
35534 +
35535 +#define S3C64XX_GPG2_MMC0_DATA0                (0x02 << 8)
35536 +#define S3C64XX_GPG2_EINT_G5_2         (0x07 << 8)
35537 +
35538 +#define S3C64XX_GPG3_MMC0_DATA1                (0x02 << 12)
35539 +#define S3C64XX_GPG3_EINT_G5_3         (0x07 << 12)
35540 +
35541 +#define S3C64XX_GPG4_MMC0_DATA2                (0x02 << 16)
35542 +#define S3C64XX_GPG4_EINT_G5_4         (0x07 << 16)
35543 +
35544 +#define S3C64XX_GPG5_MMC0_DATA3                (0x02 << 20)
35545 +#define S3C64XX_GPG5_EINT_G5_5         (0x07 << 20)
35546 +
35547 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
35548 ===================================================================
35549 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35550 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h       2009-01-02 00:01:56.000000000 +0100
35551 @@ -0,0 +1,74 @@
35552 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
35553 + *
35554 + * Copyright 2008 Openmoko, Inc.
35555 + * Copyright 2008 Simtec Electronics
35556 + *     Ben Dooks <ben@simtec.co.uk>
35557 + *     http://armlinux.simtec.co.uk/
35558 + *
35559 + * GPIO Bank H register and configuration definitions
35560 + *
35561 + * This program is free software; you can redistribute it and/or modify
35562 + * it under the terms of the GNU General Public License version 2 as
35563 + * published by the Free Software Foundation.
35564 +*/
35565 +
35566 +#define S3C64XX_GPHCON0                        (S3C64XX_GPH_BASE + 0x00)
35567 +#define S3C64XX_GPHCON1                        (S3C64XX_GPH_BASE + 0x04)
35568 +#define S3C64XX_GPHDAT                 (S3C64XX_GPH_BASE + 0x08)
35569 +#define S3C64XX_GPHPUD                 (S3C64XX_GPH_BASE + 0x0c)
35570 +#define S3C64XX_GPHCONSLP              (S3C64XX_GPH_BASE + 0x10)
35571 +#define S3C64XX_GPHPUDSLP              (S3C64XX_GPH_BASE + 0x14)
35572 +
35573 +#define S3C64XX_GPH_CONMASK(__gpio)    (0xf << ((__gpio) * 4))
35574 +#define S3C64XX_GPH_INPUT(__gpio)      (0x0 << ((__gpio) * 4))
35575 +#define S3C64XX_GPH_OUTPUT(__gpio)     (0x1 << ((__gpio) * 4))
35576 +
35577 +#define S3C64XX_GPH0_MMC1_CLK          (0x02 << 0)
35578 +#define S3C64XX_GPH0_KP_COL0           (0x04 << 0)
35579 +#define S3C64XX_GPH0_EINT_G6_0         (0x07 << 0)
35580 +
35581 +#define S3C64XX_GPH1_MMC1_CMD          (0x02 << 4)
35582 +#define S3C64XX_GPH1_KP_COL1           (0x04 << 4)
35583 +#define S3C64XX_GPH1_EINT_G6_1         (0x07 << 4)
35584 +
35585 +#define S3C64XX_GPH2_MMC1_DATA0                (0x02 << 8)
35586 +#define S3C64XX_GPH2_KP_COL2           (0x04 << 8)
35587 +#define S3C64XX_GPH2_EINT_G6_2         (0x07 << 8)
35588 +
35589 +#define S3C64XX_GPH3_MMC1_DATA1                (0x02 << 12)
35590 +#define S3C64XX_GPH3_KP_COL3           (0x04 << 12)
35591 +#define S3C64XX_GPH3_EINT_G6_3         (0x07 << 12)
35592 +
35593 +#define S3C64XX_GPH4_MMC1_DATA2                (0x02 << 16)
35594 +#define S3C64XX_GPH4_KP_COL4           (0x04 << 16)
35595 +#define S3C64XX_GPH4_EINT_G6_4         (0x07 << 16)
35596 +
35597 +#define S3C64XX_GPH5_MMC1_DATA3                (0x02 << 20)
35598 +#define S3C64XX_GPH5_KP_COL5           (0x04 << 20)
35599 +#define S3C64XX_GPH5_EINT_G6_5         (0x07 << 20)
35600 +
35601 +#define S3C64XX_GPH6_MMC1_DATA4                (0x02 << 24)
35602 +#define S3C64XX_GPH6_MMC2_DATA0                (0x03 << 24)
35603 +#define S3C64XX_GPH6_KP_COL6           (0x04 << 24)
35604 +#define S3C64XX_GPH6_I2S_V40_BCLK      (0x05 << 24)
35605 +#define S3C64XX_GPH6_ADDR_CF0          (0x06 << 24)
35606 +#define S3C64XX_GPH6_EINT_G6_6         (0x07 << 24)
35607 +
35608 +#define S3C64XX_GPH7_MMC1_DATA5                (0x02 << 28)
35609 +#define S3C64XX_GPH7_MMC2_DATA1                (0x03 << 28)
35610 +#define S3C64XX_GPH7_KP_COL7           (0x04 << 28)
35611 +#define S3C64XX_GPH7_I2S_V40_CDCLK     (0x05 << 28)
35612 +#define S3C64XX_GPH7_ADDR_CF1          (0x06 << 28)
35613 +#define S3C64XX_GPH7_EINT_G6_7         (0x07 << 28)
35614 +
35615 +#define S3C64XX_GPH8_MMC1_DATA6                (0x02 << 32)
35616 +#define S3C64XX_GPH8_MMC2_DATA2                (0x03 << 32)
35617 +#define S3C64XX_GPH8_I2S_V40_LRCLK     (0x05 << 32)
35618 +#define S3C64XX_GPH8_ADDR_CF2          (0x06 << 32)
35619 +#define S3C64XX_GPH8_EINT_G6_8         (0x07 << 32)
35620 +
35621 +#define S3C64XX_GPH9_MMC1_DATA7                (0x02 << 36)
35622 +#define S3C64XX_GPH9_MMC2_DATA3                (0x03 << 36)
35623 +#define S3C64XX_GPH9_I2S_V40_DI                (0x05 << 36)
35624 +#define S3C64XX_GPH9_EINT_G6_9         (0x07 << 36)
35625 +
35626 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
35627 ===================================================================
35628 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35629 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h       2009-01-02 00:01:56.000000000 +0100
35630 @@ -0,0 +1,40 @@
35631 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
35632 + *
35633 + * Copyright 2008 Openmoko, Inc.
35634 + * Copyright 2008 Simtec Electronics
35635 + *     Ben Dooks <ben@simtec.co.uk>
35636 + *     http://armlinux.simtec.co.uk/
35637 + *
35638 + * GPIO Bank I register and configuration definitions
35639 + *
35640 + * This program is free software; you can redistribute it and/or modify
35641 + * it under the terms of the GNU General Public License version 2 as
35642 + * published by the Free Software Foundation.
35643 +*/
35644 +
35645 +#define S3C64XX_GPICON                 (S3C64XX_GPI_BASE + 0x00)
35646 +#define S3C64XX_GPIDAT                 (S3C64XX_GPI_BASE + 0x04)
35647 +#define S3C64XX_GPIPUD                 (S3C64XX_GPI_BASE + 0x08)
35648 +#define S3C64XX_GPICONSLP              (S3C64XX_GPI_BASE + 0x0c)
35649 +#define S3C64XX_GPIPUDSLP              (S3C64XX_GPI_BASE + 0x10)
35650 +
35651 +#define S3C64XX_GPI_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35652 +#define S3C64XX_GPI_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35653 +#define S3C64XX_GPI_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35654 +
35655 +#define S3C64XX_GPI0_VD0               (0x02 << 0)
35656 +#define S3C64XX_GPI1_VD1               (0x02 << 2)
35657 +#define S3C64XX_GPI2_VD2               (0x02 << 4)
35658 +#define S3C64XX_GPI3_VD3               (0x02 << 6)
35659 +#define S3C64XX_GPI4_VD4               (0x02 << 8)
35660 +#define S3C64XX_GPI5_VD5               (0x02 << 10)
35661 +#define S3C64XX_GPI6_VD6               (0x02 << 12)
35662 +#define S3C64XX_GPI7_VD7               (0x02 << 14)
35663 +#define S3C64XX_GPI8_VD8               (0x02 << 16)
35664 +#define S3C64XX_GPI9_VD9               (0x02 << 18)
35665 +#define S3C64XX_GPI10_VD10             (0x02 << 20)
35666 +#define S3C64XX_GPI11_VD11             (0x02 << 22)
35667 +#define S3C64XX_GPI12_VD12             (0x02 << 24)
35668 +#define S3C64XX_GPI13_VD13             (0x02 << 26)
35669 +#define S3C64XX_GPI14_VD14             (0x02 << 28)
35670 +#define S3C64XX_GPI15_VD15             (0x02 << 30)
35671 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
35672 ===================================================================
35673 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35674 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h       2009-01-02 00:01:56.000000000 +0100
35675 @@ -0,0 +1,36 @@
35676 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
35677 + *
35678 + * Copyright 2008 Openmoko, Inc.
35679 + * Copyright 2008 Simtec Electronics
35680 + *     Ben Dooks <ben@simtec.co.uk>
35681 + *     http://armlinux.simtec.co.uk/
35682 + *
35683 + * GPIO Bank J register and configuration definitions
35684 + *
35685 + * This program is free software; you can redistribute it and/or modify
35686 + * it under the terms of the GNU General Public License version 2 as
35687 + * published by the Free Software Foundation.
35688 +*/
35689 +
35690 +#define S3C64XX_GPJCON                 (S3C64XX_GPJ_BASE + 0x00)
35691 +#define S3C64XX_GPJDAT                 (S3C64XX_GPJ_BASE + 0x04)
35692 +#define S3C64XX_GPJPUD                 (S3C64XX_GPJ_BASE + 0x08)
35693 +#define S3C64XX_GPJCONSLP              (S3C64XX_GPJ_BASE + 0x0c)
35694 +#define S3C64XX_GPJPUDSLP              (S3C64XX_GPJ_BASE + 0x10)
35695 +
35696 +#define S3C64XX_GPJ_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35697 +#define S3C64XX_GPJ_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35698 +#define S3C64XX_GPJ_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35699 +
35700 +#define S3C64XX_GPJ0_VD16              (0x02 << 0)
35701 +#define S3C64XX_GPJ1_VD17              (0x02 << 2)
35702 +#define S3C64XX_GPJ2_VD18              (0x02 << 4)
35703 +#define S3C64XX_GPJ3_VD19              (0x02 << 6)
35704 +#define S3C64XX_GPJ4_VD20              (0x02 << 8)
35705 +#define S3C64XX_GPJ5_VD21              (0x02 << 10)
35706 +#define S3C64XX_GPJ6_VD22              (0x02 << 12)
35707 +#define S3C64XX_GPJ7_VD23              (0x02 << 14)
35708 +#define S3C64XX_GPJ8_LCD_HSYNC         (0x02 << 16)
35709 +#define S3C64XX_GPJ9_LCD_VSYNC         (0x02 << 18)
35710 +#define S3C64XX_GPJ10_LCD_VDEN         (0x02 << 20)
35711 +#define S3C64XX_GPJ11_LCD_VCLK         (0x02 << 22)
35712 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
35713 ===================================================================
35714 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35715 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h       2009-01-02 00:01:56.000000000 +0100
35716 @@ -0,0 +1,54 @@
35717 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
35718 + *
35719 + * Copyright 2008 Openmoko, Inc.
35720 + * Copyright 2008 Simtec Electronics
35721 + *     Ben Dooks <ben@simtec.co.uk>
35722 + *     http://armlinux.simtec.co.uk/
35723 + *
35724 + * GPIO Bank N register and configuration definitions
35725 + *
35726 + * This program is free software; you can redistribute it and/or modify
35727 + * it under the terms of the GNU General Public License version 2 as
35728 + * published by the Free Software Foundation.
35729 +*/
35730 +
35731 +#define S3C64XX_GPNCON                 (S3C64XX_GPN_BASE + 0x00)
35732 +#define S3C64XX_GPNDAT                 (S3C64XX_GPN_BASE + 0x04)
35733 +#define S3C64XX_GPNPUD                 (S3C64XX_GPN_BASE + 0x08)
35734 +
35735 +#define S3C64XX_GPN_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35736 +#define S3C64XX_GPN_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35737 +#define S3C64XX_GPN_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35738 +
35739 +#define S3C64XX_GPN0_EINT0             (0x02 << 0)
35740 +#define S3C64XX_GPN0_KP_ROW0           (0x03 << 0)
35741 +
35742 +#define S3C64XX_GPN1_EINT1             (0x02 << 2)
35743 +#define S3C64XX_GPN1_KP_ROW1           (0x03 << 2)
35744 +
35745 +#define S3C64XX_GPN2_EINT2             (0x02 << 4)
35746 +#define S3C64XX_GPN2_KP_ROW2           (0x03 << 4)
35747 +
35748 +#define S3C64XX_GPN3_EINT3             (0x02 << 6)
35749 +#define S3C64XX_GPN3_KP_ROW3           (0x03 << 6)
35750 +
35751 +#define S3C64XX_GPN4_EINT4             (0x02 << 8)
35752 +#define S3C64XX_GPN4_KP_ROW4           (0x03 << 8)
35753 +
35754 +#define S3C64XX_GPN5_EINT5             (0x02 << 10)
35755 +#define S3C64XX_GPN5_KP_ROW5           (0x03 << 10)
35756 +
35757 +#define S3C64XX_GPN6_EINT6             (0x02 << 12)
35758 +#define S3C64XX_GPN6_KP_ROW6           (0x03 << 12)
35759 +
35760 +#define S3C64XX_GPN7_EINT7             (0x02 << 14)
35761 +#define S3C64XX_GPN7_KP_ROW7           (0x03 << 14)
35762 +
35763 +#define S3C64XX_GPN8_EINT8             (0x02 << 16)
35764 +#define S3C64XX_GPN9_EINT9             (0x02 << 18)
35765 +#define S3C64XX_GPN10_EINT10           (0x02 << 20)
35766 +#define S3C64XX_GPN11_EINT11           (0x02 << 22)
35767 +#define S3C64XX_GPN12_EINT12           (0x02 << 24)
35768 +#define S3C64XX_GPN13_EINT13           (0x02 << 26)
35769 +#define S3C64XX_GPN14_EINT14           (0x02 << 28)
35770 +#define S3C64XX_GPN15_EINT15           (0x02 << 30)
35771 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
35772 ===================================================================
35773 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35774 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h       2009-01-02 00:01:56.000000000 +0100
35775 @@ -0,0 +1,70 @@
35776 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
35777 + *
35778 + * Copyright 2008 Openmoko, Inc.
35779 + * Copyright 2008 Simtec Electronics
35780 + *     Ben Dooks <ben@simtec.co.uk>
35781 + *     http://armlinux.simtec.co.uk/
35782 + *
35783 + * GPIO Bank O register and configuration definitions
35784 + *
35785 + * This program is free software; you can redistribute it and/or modify
35786 + * it under the terms of the GNU General Public License version 2 as
35787 + * published by the Free Software Foundation.
35788 +*/
35789 +
35790 +#define S3C64XX_GPOCON                 (S3C64XX_GPO_BASE + 0x00)
35791 +#define S3C64XX_GPODAT                 (S3C64XX_GPO_BASE + 0x04)
35792 +#define S3C64XX_GPOPUD                 (S3C64XX_GPO_BASE + 0x08)
35793 +#define S3C64XX_GPOCONSLP              (S3C64XX_GPO_BASE + 0x0c)
35794 +#define S3C64XX_GPOPUDSLP              (S3C64XX_GPO_BASE + 0x10)
35795 +
35796 +#define S3C64XX_GPO_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35797 +#define S3C64XX_GPO_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35798 +#define S3C64XX_GPO_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35799 +
35800 +#define S3C64XX_GPO0_MEM0_nCS2         (0x02 << 0)
35801 +#define S3C64XX_GPO0_EINT_G7_0         (0x03 << 0)
35802 +
35803 +#define S3C64XX_GPO1_MEM0_nCS3         (0x02 << 2)
35804 +#define S3C64XX_GPO1_EINT_G7_1         (0x03 << 2)
35805 +
35806 +#define S3C64XX_GPO2_MEM0_nCS4         (0x02 << 4)
35807 +#define S3C64XX_GPO2_EINT_G7_2         (0x03 << 4)
35808 +
35809 +#define S3C64XX_GPO3_MEM0_nCS5         (0x02 << 6)
35810 +#define S3C64XX_GPO3_EINT_G7_3         (0x03 << 6)
35811 +
35812 +#define S3C64XX_GPO4_EINT_G7_4         (0x03 << 8)
35813 +
35814 +#define S3C64XX_GPO5_EINT_G7_5         (0x03 << 10)
35815 +
35816 +#define S3C64XX_GPO6_MEM0_ADDR6                (0x02 << 12)
35817 +#define S3C64XX_GPO6_EINT_G7_6         (0x03 << 12)
35818 +
35819 +#define S3C64XX_GPO7_MEM0_ADDR7                (0x02 << 14)
35820 +#define S3C64XX_GPO7_EINT_G7_7         (0x03 << 14)
35821 +
35822 +#define S3C64XX_GPO8_MEM0_ADDR8                (0x02 << 16)
35823 +#define S3C64XX_GPO8_EINT_G7_8         (0x03 << 16)
35824 +
35825 +#define S3C64XX_GPO9_MEM0_ADDR9                (0x02 << 18)
35826 +#define S3C64XX_GPO9_EINT_G7_9         (0x03 << 18)
35827 +
35828 +#define S3C64XX_GPO10_MEM0_ADDR10      (0x02 << 20)
35829 +#define S3C64XX_GPO10_EINT_G7_10       (0x03 << 20)
35830 +
35831 +#define S3C64XX_GPO11_MEM0_ADDR11      (0x02 << 22)
35832 +#define S3C64XX_GPO11_EINT_G7_11       (0x03 << 22)
35833 +
35834 +#define S3C64XX_GPO12_MEM0_ADDR12      (0x02 << 24)
35835 +#define S3C64XX_GPO12_EINT_G7_12       (0x03 << 24)
35836 +
35837 +#define S3C64XX_GPO13_MEM0_ADDR13      (0x02 << 26)
35838 +#define S3C64XX_GPO13_EINT_G7_13       (0x03 << 26)
35839 +
35840 +#define S3C64XX_GPO14_MEM0_ADDR14      (0x02 << 28)
35841 +#define S3C64XX_GPO14_EINT_G7_14       (0x03 << 28)
35842 +
35843 +#define S3C64XX_GPO15_MEM0_ADDR15      (0x02 << 30)
35844 +#define S3C64XX_GPO15_EINT_G7_15       (0x03 << 30)
35845 +
35846 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
35847 ===================================================================
35848 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35849 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h       2009-01-02 00:01:56.000000000 +0100
35850 @@ -0,0 +1,69 @@
35851 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
35852 + *
35853 + * Copyright 2008 Openmoko, Inc.
35854 + * Copyright 2008 Simtec Electronics
35855 + *     Ben Dooks <ben@simtec.co.uk>
35856 + *     http://armlinux.simtec.co.uk/
35857 + *
35858 + * GPIO Bank P register and configuration definitions
35859 + *
35860 + * This program is free software; you can redistribute it and/or modify
35861 + * it under the terms of the GNU General Public License version 2 as
35862 + * published by the Free Software Foundation.
35863 +*/
35864 +
35865 +#define S3C64XX_GPPCON                 (S3C64XX_GPP_BASE + 0x00)
35866 +#define S3C64XX_GPPDAT                 (S3C64XX_GPP_BASE + 0x04)
35867 +#define S3C64XX_GPPPUD                 (S3C64XX_GPP_BASE + 0x08)
35868 +#define S3C64XX_GPPCONSLP              (S3C64XX_GPP_BASE + 0x0c)
35869 +#define S3C64XX_GPPPUDSLP              (S3C64XX_GPP_BASE + 0x10)
35870 +
35871 +#define S3C64XX_GPP_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35872 +#define S3C64XX_GPP_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35873 +#define S3C64XX_GPP_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35874 +
35875 +#define S3C64XX_GPP0_MEM0_ADDRV                (0x02 << 0)
35876 +#define S3C64XX_GPP0_EINT_G8_0         (0x03 << 0)
35877 +
35878 +#define S3C64XX_GPP1_MEM0_SMCLK                (0x02 << 2)
35879 +#define S3C64XX_GPP1_EINT_G8_1         (0x03 << 2)
35880 +
35881 +#define S3C64XX_GPP2_MEM0_nWAIT                (0x02 << 4)
35882 +#define S3C64XX_GPP2_EINT_G8_2         (0x03 << 4)
35883 +
35884 +#define S3C64XX_GPP3_MEM0_RDY0_ALE     (0x02 << 6)
35885 +#define S3C64XX_GPP3_EINT_G8_3         (0x03 << 6)
35886 +
35887 +#define S3C64XX_GPP4_MEM0_RDY1_CLE     (0x02 << 8)
35888 +#define S3C64XX_GPP4_EINT_G8_4         (0x03 << 8)
35889 +
35890 +#define S3C64XX_GPP5_MEM0_INTsm0_FWE   (0x02 << 10)
35891 +#define S3C64XX_GPP5_EINT_G8_5         (0x03 << 10)
35892 +
35893 +#define S3C64XX_GPP6_MEM0_(null)       (0x02 << 12)
35894 +#define S3C64XX_GPP6_EINT_G8_6         (0x03 << 12)
35895 +
35896 +#define S3C64XX_GPP7_MEM0_INTsm1_FRE   (0x02 << 14)
35897 +#define S3C64XX_GPP7_EINT_G8_7         (0x03 << 14)
35898 +
35899 +#define S3C64XX_GPP8_MEM0_RPn_RnB      (0x02 << 16)
35900 +#define S3C64XX_GPP8_EINT_G8_8         (0x03 << 16)
35901 +
35902 +#define S3C64XX_GPP9_MEM0_ATA_RESET    (0x02 << 18)
35903 +#define S3C64XX_GPP9_EINT_G8_9         (0x03 << 18)
35904 +
35905 +#define S3C64XX_GPP10_MEM0_ATA_INPACK  (0x02 << 20)
35906 +#define S3C64XX_GPP10_EINT_G8_10       (0x03 << 20)
35907 +
35908 +#define S3C64XX_GPP11_MEM0_ATA_REG     (0x02 << 22)
35909 +#define S3C64XX_GPP11_EINT_G8_11       (0x03 << 22)
35910 +
35911 +#define S3C64XX_GPP12_MEM0_ATA_WE      (0x02 << 24)
35912 +#define S3C64XX_GPP12_EINT_G8_12       (0x03 << 24)
35913 +
35914 +#define S3C64XX_GPP13_MEM0_ATA_OE      (0x02 << 26)
35915 +#define S3C64XX_GPP13_EINT_G8_13       (0x03 << 26)
35916 +
35917 +#define S3C64XX_GPP14_MEM0_ATA_CD      (0x02 << 28)
35918 +#define S3C64XX_GPP14_EINT_G8_14       (0x03 << 28)
35919 +
35920 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
35921 ===================================================================
35922 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35923 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h       2009-01-02 00:01:56.000000000 +0100
35924 @@ -0,0 +1,46 @@
35925 +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
35926 + *
35927 + * Copyright 2008 Openmoko, Inc.
35928 + * Copyright 2008 Simtec Electronics
35929 + *     Ben Dooks <ben@simtec.co.uk>
35930 + *     http://armlinux.simtec.co.uk/
35931 + *
35932 + * GPIO Bank Q register and configuration definitions
35933 + *
35934 + * This program is free software; you can redistribute it and/or modify
35935 + * it under the terms of the GNU General Public License version 2 as
35936 + * published by the Free Software Foundation.
35937 +*/
35938 +
35939 +#define S3C64XX_GPQCON                 (S3C64XX_GPQ_BASE + 0x00)
35940 +#define S3C64XX_GPQDAT                 (S3C64XX_GPQ_BASE + 0x04)
35941 +#define S3C64XX_GPQPUD                 (S3C64XX_GPQ_BASE + 0x08)
35942 +#define S3C64XX_GPQCONSLP              (S3C64XX_GPQ_BASE + 0x0c)
35943 +#define S3C64XX_GPQPUDSLP              (S3C64XX_GPQ_BASE + 0x10)
35944 +
35945 +#define S3C64XX_GPQ_CONMASK(__gpio)    (0x3 << ((__gpio) * 2))
35946 +#define S3C64XX_GPQ_INPUT(__gpio)      (0x0 << ((__gpio) * 2))
35947 +#define S3C64XX_GPQ_OUTPUT(__gpio)     (0x1 << ((__gpio) * 2))
35948 +
35949 +#define S3C64XX_GPQ0_MEM0_ADDR18_RAS   (0x02 << 0)
35950 +#define S3C64XX_GPQ0_EINT_G9_0         (0x03 << 0)
35951 +
35952 +#define S3C64XX_GPQ1_MEM0_ADDR19_CAS   (0x02 << 2)
35953 +#define S3C64XX_GPQ1_EINT_G9_1         (0x03 << 2)
35954 +
35955 +#define S3C64XX_GPQ2_EINT_G9_2         (0x03 << 4)
35956 +
35957 +#define S3C64XX_GPQ3_EINT_G9_3         (0x03 << 6)
35958 +
35959 +#define S3C64XX_GPQ4_EINT_G9_4         (0x03 << 8)
35960 +
35961 +#define S3C64XX_GPQ5_EINT_G9_5         (0x03 << 10)
35962 +
35963 +#define S3C64XX_GPQ6_EINT_G9_6         (0x03 << 12)
35964 +
35965 +#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC        (0x02 << 14)
35966 +#define S3C64XX_GPQ7_EINT_G9_7         (0x03 << 14)
35967 +
35968 +#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
35969 +#define S3C64XX_GPQ8_EINT_G9_8         (0x03 << 16)
35970 +
35971 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/irqs.h
35972 ===================================================================
35973 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
35974 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/irqs.h      2009-01-02 00:01:56.000000000 +0100
35975 @@ -0,0 +1,202 @@
35976 +/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
35977 + *
35978 + * Copyright 2008 Openmoko, Inc.
35979 + * Copyright 2008 Simtec Electronics
35980 + *      Ben Dooks <ben@simtec.co.uk>
35981 + *      http://armlinux.simtec.co.uk/
35982 + *
35983 + * S3C64XX - Common IRQ support
35984 + */
35985 +
35986 +#ifndef __ASM_PLAT_S3C64XX_IRQS_H
35987 +#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
35988 +
35989 +/* we keep the first set of CPU IRQs out of the range of
35990 + * the ISA space, so that the PC104 has them to itself
35991 + * and we don't end up having to do horrible things to the
35992 + * standard ISA drivers....
35993 + *
35994 + * note, since we're using the VICs, our start must be a
35995 + * mulitple of 32 to allow the common code to work
35996 + */
35997 +
35998 +#define S3C_IRQ_OFFSET (32)
35999 +
36000 +#define S3C_IRQ(x)     ((x) + S3C_IRQ_OFFSET)
36001 +
36002 +#define S3C_VIC0_BASE  S3C_IRQ(0)
36003 +#define S3C_VIC1_BASE  S3C_IRQ(32)
36004 +
36005 +/* UART interrupts, each UART has 4 intterupts per channel so
36006 + * use the space between the ISA and S3C main interrupts. Note, these
36007 + * are not in the same order as the S3C24XX series! */
36008 +
36009 +#define IRQ_S3CUART_BASE0      (16)
36010 +#define IRQ_S3CUART_BASE1      (20)
36011 +#define IRQ_S3CUART_BASE2      (24)
36012 +#define IRQ_S3CUART_BASE3      (28)
36013 +
36014 +#define UART_IRQ_RXD           (0)
36015 +#define UART_IRQ_ERR           (1)
36016 +#define UART_IRQ_TXD           (2)
36017 +#define UART_IRQ_MODEM         (3)
36018 +
36019 +#define IRQ_S3CUART_RX0                (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
36020 +#define IRQ_S3CUART_TX0                (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
36021 +#define IRQ_S3CUART_ERR0       (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
36022 +
36023 +#define IRQ_S3CUART_RX1                (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
36024 +#define IRQ_S3CUART_TX1                (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
36025 +#define IRQ_S3CUART_ERR1       (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
36026 +
36027 +#define IRQ_S3CUART_RX2                (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
36028 +#define IRQ_S3CUART_TX2                (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
36029 +#define IRQ_S3CUART_ERR2       (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
36030 +
36031 +#define IRQ_S3CUART_RX3                (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
36032 +#define IRQ_S3CUART_TX3                (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
36033 +#define IRQ_S3CUART_ERR3       (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
36034 +
36035 +/* VIC based IRQs */
36036 +
36037 +#define S3C64XX_IRQ_VIC0(x)    (S3C_VIC0_BASE + (x))
36038 +#define S3C64XX_IRQ_VIC1(x)    (S3C_VIC1_BASE + (x))
36039 +
36040 +/* VIC0 */
36041 +
36042 +#define IRQ_EINT0_3            S3C64XX_IRQ_VIC0(0)
36043 +#define IRQ_EINT4_11           S3C64XX_IRQ_VIC0(1)
36044 +#define IRQ_RTC_TIC            S3C64XX_IRQ_VIC0(2)
36045 +#define IRQ_CAMIF_C            S3C64XX_IRQ_VIC0(3)
36046 +#define IRQ_CAMIF_P            S3C64XX_IRQ_VIC0(4)
36047 +#define IRQ_CAMIF_MC           S3C64XX_IRQ_VIC0(5)
36048 +#define IRQ_S3C6410_IIC1       S3C64XX_IRQ_VIC0(5)
36049 +#define IRQ_S3C6410_IIS                S3C64XX_IRQ_VIC0(6)
36050 +#define IRQ_S3C6400_CAMIF_MP   S3C64XX_IRQ_VIC0(6)
36051 +#define IRQ_CAMIF_WE_C         S3C64XX_IRQ_VIC0(7)
36052 +#define IRQ_S3C6410_G3D                S3C64XX_IRQ_VIC0(8)
36053 +#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
36054 +#define IRQ_POST0              S3C64XX_IRQ_VIC0(9)
36055 +#define IRQ_ROTATOR            S3C64XX_IRQ_VIC0(10)
36056 +#define IRQ_2D                 S3C64XX_IRQ_VIC0(11)
36057 +#define IRQ_TVENC              S3C64XX_IRQ_VIC0(12)
36058 +#define IRQ_SCALER             S3C64XX_IRQ_VIC0(13)
36059 +#define IRQ_BATF               S3C64XX_IRQ_VIC0(14)
36060 +#define IRQ_JPEG               S3C64XX_IRQ_VIC0(15)
36061 +#define IRQ_MFC                        S3C64XX_IRQ_VIC0(16)
36062 +#define IRQ_SDMA0              S3C64XX_IRQ_VIC0(17)
36063 +#define IRQ_SDMA1              S3C64XX_IRQ_VIC0(18)
36064 +#define IRQ_ARM_DMAERR         S3C64XX_IRQ_VIC0(19)
36065 +#define IRQ_ARM_DMA            S3C64XX_IRQ_VIC0(20)
36066 +#define IRQ_ARM_DMAS           S3C64XX_IRQ_VIC0(21)
36067 +#define IRQ_KEYPAD             S3C64XX_IRQ_VIC0(22)
36068 +#define IRQ_TIMER0_VIC         S3C64XX_IRQ_VIC0(23)
36069 +#define IRQ_TIMER1_VIC         S3C64XX_IRQ_VIC0(24)
36070 +#define IRQ_TIMER2_VIC         S3C64XX_IRQ_VIC0(25)
36071 +#define IRQ_WDT                        S3C64XX_IRQ_VIC0(26)
36072 +#define IRQ_TIMER3_VIC         S3C64XX_IRQ_VIC0(27)
36073 +#define IRQ_TIMER4_VIC         S3C64XX_IRQ_VIC0(28)
36074 +#define IRQ_LCD_FIFO           S3C64XX_IRQ_VIC0(29)
36075 +#define IRQ_LCD_VSYNC          S3C64XX_IRQ_VIC0(30)
36076 +#define IRQ_LCD_SYSTEM         S3C64XX_IRQ_VIC0(31)
36077 +
36078 +/* VIC1 */
36079 +
36080 +#define IRQ_EINT12_19          S3C64XX_IRQ_VIC1(0)
36081 +#define IRQ_EINT20_27          S3C64XX_IRQ_VIC1(1)
36082 +#define IRQ_PCM0               S3C64XX_IRQ_VIC1(2)
36083 +#define IRQ_PCM1               S3C64XX_IRQ_VIC1(3)
36084 +#define IRQ_AC97               S3C64XX_IRQ_VIC1(4)
36085 +#define IRQ_UART0              S3C64XX_IRQ_VIC1(5)
36086 +#define IRQ_UART1              S3C64XX_IRQ_VIC1(6)
36087 +#define IRQ_UART2              S3C64XX_IRQ_VIC1(7)
36088 +#define IRQ_UART3              S3C64XX_IRQ_VIC1(8)
36089 +#define IRQ_DMA0               S3C64XX_IRQ_VIC1(9)
36090 +#define IRQ_DMA1               S3C64XX_IRQ_VIC1(10)
36091 +#define IRQ_ONENAND0           S3C64XX_IRQ_VIC1(11)
36092 +#define IRQ_ONENAND1           S3C64XX_IRQ_VIC1(12)
36093 +#define IRQ_NFC                        S3C64XX_IRQ_VIC1(13)
36094 +#define IRQ_CFCON              S3C64XX_IRQ_VIC1(14)
36095 +#define IRQ_UHOST              S3C64XX_IRQ_VIC1(15)
36096 +#define IRQ_SPI0               S3C64XX_IRQ_VIC1(16)
36097 +#define IRQ_SPI1               S3C64XX_IRQ_VIC1(17)
36098 +#define IRQ_IIC                        S3C64XX_IRQ_VIC1(18)
36099 +#define IRQ_HSItx              S3C64XX_IRQ_VIC1(19)
36100 +#define IRQ_HSIrx              S3C64XX_IRQ_VIC1(20)
36101 +#define IRQ_RESERVED           S3C64XX_IRQ_VIC1(21)
36102 +#define IRQ_MSM                        S3C64XX_IRQ_VIC1(22)
36103 +#define IRQ_HOSTIF             S3C64XX_IRQ_VIC1(23)
36104 +#define IRQ_HSMMC0             S3C64XX_IRQ_VIC1(24)
36105 +#define IRQ_HSMMC1             S3C64XX_IRQ_VIC1(25)
36106 +#define IRQ_HSMMC2             IRQ_SPI1        /* shared with SPI1 */
36107 +#define IRQ_OTG                        S3C64XX_IRQ_VIC1(26)
36108 +#define IRQ_IRDA               S3C64XX_IRQ_VIC1(27)
36109 +#define IRQ_RTC_ALARM          S3C64XX_IRQ_VIC1(28)
36110 +#define IRQ_SEC                        S3C64XX_IRQ_VIC1(29)
36111 +#define IRQ_PENDN              S3C64XX_IRQ_VIC1(30)
36112 +#define IRQ_TC                 IRQ_PENDN
36113 +#define IRQ_ADC                        S3C64XX_IRQ_VIC1(31)
36114 +
36115 +#define S3C64XX_TIMER_IRQ(x)   S3C_IRQ(64 + (x))
36116 +
36117 +#define IRQ_TIMER0             S3C64XX_TIMER_IRQ(0)
36118 +#define IRQ_TIMER1             S3C64XX_TIMER_IRQ(1)
36119 +#define IRQ_TIMER2             S3C64XX_TIMER_IRQ(2)
36120 +#define IRQ_TIMER3             S3C64XX_TIMER_IRQ(3)
36121 +#define IRQ_TIMER4             S3C64XX_TIMER_IRQ(4)
36122 +
36123 +/* compatibility for device defines */
36124 +
36125 +#define IRQ_IIC1               IRQ_S3C6410_IIC1
36126 +
36127 +/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
36128 + * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
36129 + * which we place after the pair of VICs. */
36130 +
36131 +#define S3C_IRQ_EINT_BASE      S3C_IRQ(64+5)
36132 +
36133 +#define S3C_EINT(x)            ((x) + S3C_IRQ_EINT_BASE)
36134 +#define IRQ_EINT(x)            S3C_EINT(x)
36135 +#define IRQ_EINT_BIT(x)                ((x) - S3C_EINT(0))
36136 +
36137 +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
36138 + * that they are sourced from the GPIO pins but with a different scheme for
36139 + * priority and source indication.
36140 + *
36141 + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
36142 + * interrupts, but for historical reasons they are kept apart from these
36143 + * next interrupts.
36144 + *
36145 + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
36146 + * machine specific support files.
36147 + */
36148 +
36149 +#define IRQ_EINT_GROUP1_NR     (15)
36150 +#define IRQ_EINT_GROUP2_NR     (8)
36151 +#define IRQ_EINT_GROUP3_NR     (5)
36152 +#define IRQ_EINT_GROUP4_NR     (14)
36153 +#define IRQ_EINT_GROUP5_NR     (7)
36154 +#define IRQ_EINT_GROUP6_NR     (10)
36155 +#define IRQ_EINT_GROUP7_NR     (16)
36156 +#define IRQ_EINT_GROUP8_NR     (15)
36157 +#define IRQ_EINT_GROUP9_NR     (9)
36158 +
36159 +#define IRQ_EINT_GROUP_BASE    S3C_EINT(28)
36160 +#define IRQ_EINT_GROUP1_BASE   (IRQ_EINT_GROUP_BASE + 0x00)
36161 +#define IRQ_EINT_GROUP2_BASE   (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
36162 +#define IRQ_EINT_GROUP3_BASE   (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
36163 +#define IRQ_EINT_GROUP4_BASE   (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
36164 +#define IRQ_EINT_GROUP5_BASE   (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
36165 +#define IRQ_EINT_GROUP6_BASE   (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
36166 +#define IRQ_EINT_GROUP7_BASE   (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
36167 +#define IRQ_EINT_GROUP8_BASE   (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
36168 +#define IRQ_EINT_GROUP9_BASE   (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
36169 +
36170 +#define IRQ_EINT_GROUP(group, no)      (IRQ_EINT_GROUP##group##__BASE + (x))
36171 +
36172 +/* Set the default NR_IRQS */
36173 +
36174 +#define NR_IRQS        (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
36175 +
36176 +#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
36177 +
36178 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pll.h
36179 ===================================================================
36180 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36181 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pll.h       2009-01-02 00:01:56.000000000 +0100
36182 @@ -0,0 +1,74 @@
36183 +/* arch/arm/plat-s3c64xx/include/plat/pll.h
36184 + *
36185 + * Copyright 2008 Openmoko, Inc.
36186 + * Copyright 2008 Simtec Electronics
36187 + *     Ben Dooks <ben@simtec.co.uk>
36188 + *     http://armlinux.simtec.co.uk/
36189 + *
36190 + * S3C64XX PLL code
36191 + *
36192 + * This program is free software; you can redistribute it and/or modify
36193 + * it under the terms of the GNU General Public License version 2 as
36194 + * published by the Free Software Foundation.
36195 +*/
36196 +
36197 +#define S3C6400_PLL_MDIV_MASK  ((1 << (25-16+1)) - 1)
36198 +#define S3C6400_PLL_PDIV_MASK  ((1 << (13-8+1)) - 1)
36199 +#define S3C6400_PLL_SDIV_MASK  ((1 << (2-0+1)) - 1)
36200 +#define S3C6400_PLL_MDIV_SHIFT (16)
36201 +#define S3C6400_PLL_PDIV_SHIFT (8)
36202 +#define S3C6400_PLL_SDIV_SHIFT (0)
36203 +
36204 +#include <asm/div64.h>
36205 +
36206 +static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
36207 +                                           u32 pllcon)
36208 +{
36209 +       u32 mdiv, pdiv, sdiv;
36210 +       u64 fvco = baseclk;
36211 +
36212 +       mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
36213 +       pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
36214 +       sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
36215 +
36216 +       fvco *= mdiv;
36217 +       do_div(fvco, (pdiv << sdiv));
36218 +
36219 +       return (unsigned long)fvco;
36220 +}
36221 +
36222 +#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
36223 +#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
36224 +#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
36225 +#define S3C6400_EPLL_MDIV_SHIFT        (16)
36226 +#define S3C6400_EPLL_PDIV_SHIFT        (8)
36227 +#define S3C6400_EPLL_SDIV_SHIFT        (0)
36228 +#define S3C6400_EPLL_KDIV_MASK  (0xffff)
36229 +
36230 +static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
36231 +{
36232 +       unsigned long result;
36233 +       u32 epll0 = __raw_readl(S3C_EPLL_CON0);
36234 +       u32 epll1 = __raw_readl(S3C_EPLL_CON1);
36235 +       u32 mdiv, pdiv, sdiv, kdiv;
36236 +       u64 tmp;
36237 +
36238 +       mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
36239 +       pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
36240 +       sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
36241 +       kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
36242 +
36243 +       /* We need to multiple baseclk by mdiv (the integer part) and kdiv
36244 +        * which is in 2^16ths, so shift mdiv up (does not overflow) and
36245 +        * add kdiv before multiplying. The use of tmp is to avoid any
36246 +        * overflows before shifting bac down into result when multipling
36247 +        * by the mdiv and kdiv pair.
36248 +        */
36249 +
36250 +       tmp = baseclk;
36251 +       tmp *= (mdiv << 16) + kdiv;
36252 +       do_div(tmp, (pdiv << sdiv));
36253 +       result = tmp >> 16;
36254 +
36255 +       return result;
36256 +}
36257 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pm-core.h
36258 ===================================================================
36259 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36260 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pm-core.h   2009-01-02 00:01:56.000000000 +0100
36261 @@ -0,0 +1,106 @@
36262 +/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
36263 + *
36264 + * Copyright 2008 Openmoko, Inc.
36265 + * Copyright 2008 Simtec Electronics
36266 + *      Ben Dooks <ben@simtec.co.uk>
36267 + *      http://armlinux.simtec.co.uk/
36268 + *
36269 + * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
36270 + *
36271 + * This program is free software; you can redistribute it and/or modify
36272 + * it under the terms of the GNU General Public License version 2 as
36273 + * published by the Free Software Foundation.
36274 + */
36275 +
36276 +#include <plat/regs-gpio.h>
36277 +
36278 +static inline void s3c_pm_debug_init_uart(void)
36279 +{
36280 +       u32 tmp = __raw_readl(S3C_PCLK_GATE);
36281 +
36282 +       /* As a note, since the S3C64XX UARTs generally have multiple
36283 +        * clock sources, we simply enable PCLK at the moment and hope
36284 +        * that the resume settings for the UART are suitable for the
36285 +        * use with PCLK.
36286 +        */
36287 +
36288 +       tmp |= S3C_CLKCON_PCLK_UART0;
36289 +       tmp |= S3C_CLKCON_PCLK_UART1;
36290 +       tmp |= S3C_CLKCON_PCLK_UART2;
36291 +       tmp |= S3C_CLKCON_PCLK_UART3;
36292 +
36293 +       __raw_writel(tmp, S3C_PCLK_GATE);
36294 +       udelay(10);
36295 +}
36296 +
36297 +static inline void s3c_pm_arch_clear_vic(void __iomem *base)
36298 +{
36299 +       __raw_writel(~0, base + VIC_INT_ENABLE_CLEAR);
36300 +       __raw_writel(~0, base + VIC_INT_SOFT_CLEAR);
36301 +}
36302 +
36303 +static inline void s3c_pm_arch_prepare_irqs(void)
36304 +{
36305 +       /* shutdown the VICs */
36306 +       s3c_pm_arch_clear_vic(S3C_VA_VIC0);
36307 +       s3c_pm_arch_clear_vic(S3C_VA_VIC1);
36308 +
36309 +       /* clear any pending EINT0 interrupts */
36310 +       __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
36311 +}
36312 +
36313 +static inline void s3c_pm_arch_stop_clocks(void)
36314 +{
36315 +}
36316 +
36317 +static inline void s3c_pm_arch_show_resume_irqs(void)
36318 +{
36319 +}
36320 +
36321 +/* make these defines, we currently do not have any need to change
36322 + * the IRQ wake controls depending on the CPU we are running on */
36323 +
36324 +#define s3c_irqwake_eintallow  ((1 << 28) - 1)
36325 +#define s3c_irqwake_intallow   (0)
36326 +
36327 +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
36328 +                                          struct pm_uart_save *save)
36329 +{
36330 +       u32 ucon = __raw_readl(regs + S3C2410_UCON);
36331 +       u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
36332 +       u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
36333 +       u32 new_ucon;
36334 +       u32 delta;
36335 +
36336 +       /* S3C64XX UART blocks only support level interrupts, so ensure that
36337 +        * when we restore unused UART blocks we force the level interrupt
36338 +        * settigs. */
36339 +       save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
36340 +
36341 +       /* We have a constraint on changing the clock type of the UART
36342 +        * between UCLKx and PCLK, so ensure that when we restore UCON
36343 +        * that the CLK field is correctly modified if the bootloader
36344 +        * has changed anything.
36345 +        */
36346 +       if (ucon_clk != save_clk) {
36347 +               new_ucon = save->ucon;
36348 +               delta = ucon_clk ^ save_clk;
36349 +
36350 +               /* change from UCLKx => wrong PCLK,
36351 +                * either UCLK can be tested for by a bit-test
36352 +                * with UCLK0 */
36353 +               if (ucon_clk & S3C6400_UCON_UCLK0 &&
36354 +                   !(save_clk & S3C6400_UCON_UCLK0) &&
36355 +                   delta & S3C6400_UCON_PCLK2) {
36356 +                       new_ucon &= ~S3C6400_UCON_UCLK0;
36357 +               } else if (delta == S3C6400_UCON_PCLK2) {
36358 +                       /* as an precaution, don't change from
36359 +                        * PCLK2 => PCLK or vice-versa */
36360 +                       new_ucon ^= S3C6400_UCON_PCLK2;
36361 +               }
36362 +
36363 +               S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
36364 +                         ucon, new_ucon, save->ucon);
36365 +               save->ucon = new_ucon;
36366 +       }
36367 +}
36368 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
36369 ===================================================================
36370 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36371 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-clock.h        2009-01-02 00:01:56.000000000 +0100
36372 @@ -0,0 +1,225 @@
36373 +/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
36374 + *
36375 + * Copyright 2008 Openmoko, Inc.
36376 + * Copyright 2008 Simtec Electronics
36377 + *     Ben Dooks <ben@simtec.co.uk>
36378 + *     http://armlinux.simtec.co.uk/
36379 + *
36380 + * S3C64XX clock register definitions
36381 + *
36382 + * This program is free software; you can redistribute it and/or modify
36383 + * it under the terms of the GNU General Public License version 2 as
36384 + * published by the Free Software Foundation.
36385 +*/
36386 +
36387 +#ifndef __PLAT_REGS_CLOCK_H
36388 +#define __PLAT_REGS_CLOCK_H __FILE__
36389 +
36390 +#define S3C_CLKREG(x)          (S3C_VA_SYS + (x))
36391 +
36392 +#define S3C_APLL_LOCK          S3C_CLKREG(0x00)
36393 +#define S3C_MPLL_LOCK          S3C_CLKREG(0x04)
36394 +#define S3C_EPLL_LOCK          S3C_CLKREG(0x08)
36395 +#define S3C_APLL_CON           S3C_CLKREG(0x0C)
36396 +#define S3C_MPLL_CON           S3C_CLKREG(0x10)
36397 +#define S3C_EPLL_CON0          S3C_CLKREG(0x14)
36398 +#define S3C_EPLL_CON1          S3C_CLKREG(0x18)
36399 +#define S3C_CLK_SRC            S3C_CLKREG(0x1C)
36400 +#define S3C_CLK_DIV0           S3C_CLKREG(0x20)
36401 +#define S3C_CLK_DIV1           S3C_CLKREG(0x24)
36402 +#define S3C_CLK_DIV2           S3C_CLKREG(0x28)
36403 +#define S3C_CLK_OUT            S3C_CLKREG(0x2C)
36404 +#define S3C_HCLK_GATE          S3C_CLKREG(0x30)
36405 +#define S3C_PCLK_GATE          S3C_CLKREG(0x34)
36406 +#define S3C_SCLK_GATE          S3C_CLKREG(0x38)
36407 +#define S3C_MEM0_GATE          S3C_CLKREG(0x3C)
36408 +
36409 +/* CLKDIV0 */
36410 +#define S3C6400_CLKDIV0_MFC_MASK       (0xf << 28)
36411 +#define S3C6400_CLKDIV0_MFC_SHIFT      (28)
36412 +#define S3C6400_CLKDIV0_JPEG_MASK      (0xf << 24)
36413 +#define S3C6400_CLKDIV0_JPEG_SHIFT     (24)
36414 +#define S3C6400_CLKDIV0_CAM_MASK       (0xf << 20)
36415 +#define S3C6400_CLKDIV0_CAM_SHIFT      (20)
36416 +#define S3C6400_CLKDIV0_SECURITY_MASK  (0x3 << 18)
36417 +#define S3C6400_CLKDIV0_SECURITY_SHIFT (18)
36418 +#define S3C6400_CLKDIV0_PCLK_MASK      (0xf << 12)
36419 +#define S3C6400_CLKDIV0_PCLK_SHIFT     (12)
36420 +#define S3C6400_CLKDIV0_HCLK2_MASK     (0x7 << 9)
36421 +#define S3C6400_CLKDIV0_HCLK2_SHIFT    (9)
36422 +#define S3C6400_CLKDIV0_HCLK_MASK      (0x1 << 8)
36423 +#define S3C6400_CLKDIV0_HCLK_SHIFT     (8)
36424 +#define S3C6400_CLKDIV0_MPLL_MASK      (0x1 << 4)
36425 +#define S3C6400_CLKDIV0_MPLL_SHIFT     (4)
36426 +#define S3C6400_CLKDIV0_ARM_MASK       (0x3 << 0)
36427 +#define S3C6410_CLKDIV0_ARM_MASK       (0x7 << 0)
36428 +#define S3C6400_CLKDIV0_ARM_SHIFT      (0)
36429 +
36430 +/* CLKDIV1 */
36431 +#define S3C6410_CLKDIV1_FIMC_MASK      (0xf << 24)
36432 +#define S3C6410_CLKDIV1_FIMC_SHIFT     (24)
36433 +#define S3C6400_CLKDIV1_UHOST_MASK     (0xf << 20)
36434 +#define S3C6400_CLKDIV1_UHOST_SHIFT    (20)
36435 +#define S3C6400_CLKDIV1_SCALER_MASK    (0xf << 16)
36436 +#define S3C6400_CLKDIV1_SCALER_SHIFT   (16)
36437 +#define S3C6400_CLKDIV1_LCD_MASK       (0xf << 12)
36438 +#define S3C6400_CLKDIV1_LCD_SHIFT      (12)
36439 +#define S3C6400_CLKDIV1_MMC2_MASK      (0xf << 8)
36440 +#define S3C6400_CLKDIV1_MMC2_SHIFT     (8)
36441 +#define S3C6400_CLKDIV1_MMC1_MASK      (0xf << 4)
36442 +#define S3C6400_CLKDIV1_MMC1_SHIFT     (4)
36443 +#define S3C6400_CLKDIV1_MMC0_MASK      (0xf << 0)
36444 +#define S3C6400_CLKDIV1_MMC0_SHIFT     (0)
36445 +
36446 +/* CLKDIV2 */
36447 +#define S3C6410_CLKDIV2_AUDIO2_MASK    (0xf << 24)
36448 +#define S3C6410_CLKDIV2_AUDIO2_SHIFT   (24)
36449 +#define S3C6400_CLKDIV2_IRDA_MASK      (0xf << 20)
36450 +#define S3C6400_CLKDIV2_IRDA_SHIFT     (20)
36451 +#define S3C6400_CLKDIV2_UART_MASK      (0xf << 16)
36452 +#define S3C6400_CLKDIV2_UART_SHIFT     (16)
36453 +#define S3C6400_CLKDIV2_AUDIO1_MASK    (0xf << 12)
36454 +#define S3C6400_CLKDIV2_AUDIO1_SHIFT   (12)
36455 +#define S3C6400_CLKDIV2_AUDIO0_MASK    (0xf << 8)
36456 +#define S3C6400_CLKDIV2_AUDIO0_SHIFT   (8)
36457 +#define S3C6400_CLKDIV2_SPI1_MASK      (0xf << 4)
36458 +#define S3C6400_CLKDIV2_SPI1_SHIFT     (4)
36459 +#define S3C6400_CLKDIV2_SPI0_MASK      (0xf << 0)
36460 +#define S3C6400_CLKDIV2_SPI0_SHIFT     (0)
36461 +
36462 +/* HCLK GATE Registers */
36463 +#define S3C_CLKCON_HCLK_BUS    (1<<30)
36464 +#define S3C_CLKCON_HCLK_SECUR  (1<<29)
36465 +#define S3C_CLKCON_HCLK_SDMA1  (1<<28)
36466 +#define S3C_CLKCON_HCLK_SDMA2  (1<<27)
36467 +#define S3C_CLKCON_HCLK_UHOST  (1<<26)
36468 +#define S3C_CLKCON_HCLK_IROM   (1<<25)
36469 +#define S3C_CLKCON_HCLK_DDR1   (1<<24)
36470 +#define S3C_CLKCON_HCLK_DDR0   (1<<23)
36471 +#define S3C_CLKCON_HCLK_MEM1   (1<<22)
36472 +#define S3C_CLKCON_HCLK_MEM0   (1<<21)
36473 +#define S3C_CLKCON_HCLK_USB    (1<<20)
36474 +#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
36475 +#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
36476 +#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
36477 +#define S3C_CLKCON_HCLK_MDP    (1<<16)
36478 +#define S3C_CLKCON_HCLK_DHOST  (1<<15)
36479 +#define S3C_CLKCON_HCLK_IHOST  (1<<14)
36480 +#define S3C_CLKCON_HCLK_DMA1   (1<<13)
36481 +#define S3C_CLKCON_HCLK_DMA0   (1<<12)
36482 +#define S3C_CLKCON_HCLK_JPEG   (1<<11)
36483 +#define S3C_CLKCON_HCLK_CAMIF  (1<<10)
36484 +#define S3C_CLKCON_HCLK_SCALER (1<<9)
36485 +#define S3C_CLKCON_HCLK_2D     (1<<8)
36486 +#define S3C_CLKCON_HCLK_TV     (1<<7)
36487 +#define S3C_CLKCON_HCLK_POST0  (1<<5)
36488 +#define S3C_CLKCON_HCLK_ROT    (1<<4)
36489 +#define S3C_CLKCON_HCLK_LCD    (1<<3)
36490 +#define S3C_CLKCON_HCLK_TZIC   (1<<2)
36491 +#define S3C_CLKCON_HCLK_INTC   (1<<1)
36492 +#define S3C_CLKCON_HCLK_MFC    (1<<0)
36493 +
36494 +/* PCLK GATE Registers */
36495 +#define S3C6410_CLKCON_PCLK_I2C1       (1<<27)
36496 +#define S3C6410_CLKCON_PCLK_IIS2       (1<<26)
36497 +#define S3C_CLKCON_PCLK_SKEY           (1<<24)
36498 +#define S3C_CLKCON_PCLK_CHIPID         (1<<23)
36499 +#define S3C_CLKCON_PCLK_SPI1           (1<<22)
36500 +#define S3C_CLKCON_PCLK_SPI0           (1<<21)
36501 +#define S3C_CLKCON_PCLK_HSIRX          (1<<20)
36502 +#define S3C_CLKCON_PCLK_HSITX          (1<<19)
36503 +#define S3C_CLKCON_PCLK_GPIO           (1<<18)
36504 +#define S3C_CLKCON_PCLK_IIC            (1<<17)
36505 +#define S3C_CLKCON_PCLK_IIS1           (1<<16)
36506 +#define S3C_CLKCON_PCLK_IIS0           (1<<15)
36507 +#define S3C_CLKCON_PCLK_AC97           (1<<14)
36508 +#define S3C_CLKCON_PCLK_TZPC           (1<<13)
36509 +#define S3C_CLKCON_PCLK_TSADC          (1<<12)
36510 +#define S3C_CLKCON_PCLK_KEYPAD         (1<<11)
36511 +#define S3C_CLKCON_PCLK_IRDA           (1<<10)
36512 +#define S3C_CLKCON_PCLK_PCM1           (1<<9)
36513 +#define S3C_CLKCON_PCLK_PCM0           (1<<8)
36514 +#define S3C_CLKCON_PCLK_PWM            (1<<7)
36515 +#define S3C_CLKCON_PCLK_RTC            (1<<6)
36516 +#define S3C_CLKCON_PCLK_WDT            (1<<5)
36517 +#define S3C_CLKCON_PCLK_UART3          (1<<4)
36518 +#define S3C_CLKCON_PCLK_UART2          (1<<3)
36519 +#define S3C_CLKCON_PCLK_UART1          (1<<2)
36520 +#define S3C_CLKCON_PCLK_UART0          (1<<1)
36521 +#define S3C_CLKCON_PCLK_MFC            (1<<0)
36522 +
36523 +/* SCLK GATE Registers */
36524 +#define S3C_CLKCON_SCLK_UHOST          (1<<30)
36525 +#define S3C_CLKCON_SCLK_MMC2_48                (1<<29)
36526 +#define S3C_CLKCON_SCLK_MMC1_48                (1<<28)
36527 +#define S3C_CLKCON_SCLK_MMC0_48                (1<<27)
36528 +#define S3C_CLKCON_SCLK_MMC2           (1<<26)
36529 +#define S3C_CLKCON_SCLK_MMC1           (1<<25)
36530 +#define S3C_CLKCON_SCLK_MMC0           (1<<24)
36531 +#define S3C_CLKCON_SCLK_SPI1_48        (1<<23)
36532 +#define S3C_CLKCON_SCLK_SPI0_48        (1<<22)
36533 +#define S3C_CLKCON_SCLK_SPI1           (1<<21)
36534 +#define S3C_CLKCON_SCLK_SPI0           (1<<20)
36535 +#define S3C_CLKCON_SCLK_DAC27          (1<<19)
36536 +#define S3C_CLKCON_SCLK_TV27           (1<<18)
36537 +#define S3C_CLKCON_SCLK_SCALER27       (1<<17)
36538 +#define S3C_CLKCON_SCLK_SCALER         (1<<16)
36539 +#define S3C_CLKCON_SCLK_LCD27          (1<<15)
36540 +#define S3C_CLKCON_SCLK_LCD            (1<<14)
36541 +#define S3C6400_CLKCON_SCLK_POST1_27   (1<<13)
36542 +#define S3C6410_CLKCON_FIMC            (1<<13)
36543 +#define S3C_CLKCON_SCLK_POST0_27       (1<<12)
36544 +#define S3C6400_CLKCON_SCLK_POST1      (1<<11)
36545 +#define S3C6410_CLKCON_SCLK_AUDIO2     (1<<11)
36546 +#define S3C_CLKCON_SCLK_POST0          (1<<10)
36547 +#define S3C_CLKCON_SCLK_AUDIO1         (1<<9)
36548 +#define S3C_CLKCON_SCLK_AUDIO0         (1<<8)
36549 +#define S3C_CLKCON_SCLK_SECUR          (1<<7)
36550 +#define S3C_CLKCON_SCLK_IRDA           (1<<6)
36551 +#define S3C_CLKCON_SCLK_UART           (1<<5)
36552 +#define S3C_CLKCON_SCLK_ONENAND        (1<<4)
36553 +#define S3C_CLKCON_SCLK_MFC            (1<<3)
36554 +#define S3C_CLKCON_SCLK_CAM            (1<<2)
36555 +#define S3C_CLKCON_SCLK_JPEG           (1<<1)
36556 +
36557 +/* CLKSRC */
36558 +
36559 +#define S3C6400_CLKSRC_APLL_MOUT       (1 << 0)
36560 +#define S3C6400_CLKSRC_MPLL_MOUT       (1 << 1)
36561 +#define S3C6400_CLKSRC_EPLL_MOUT       (1 << 2)
36562 +#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
36563 +#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
36564 +#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
36565 +#define S3C6400_CLKSRC_MFC             (1 << 4)
36566 +
36567 +#define S3C6410_CLKSRC_TV27_MASK       (0x1 << 31)
36568 +#define S3C6410_CLKSRC_TV27_SHIFT      (31)
36569 +#define S3C6410_CLKSRC_DAC27_MASK      (0x1 << 30)
36570 +#define S3C6410_CLKSRC_DAC27_SHIFT     (30)
36571 +#define S3C6400_CLKSRC_SCALER_MASK     (0x3 << 28)
36572 +#define S3C6400_CLKSRC_SCALER_SHIFT    (28)
36573 +#define S3C6400_CLKSRC_LCD_MASK                (0x3 << 26)
36574 +#define S3C6400_CLKSRC_LCD_SHIFT       (26)
36575 +#define S3C6400_CLKSRC_IRDA_MASK       (0x3 << 24)
36576 +#define S3C6400_CLKSRC_IRDA_SHIFT      (24)
36577 +#define S3C6400_CLKSRC_MMC2_MASK       (0x3 << 22)
36578 +#define S3C6400_CLKSRC_MMC2_SHIFT      (22)
36579 +#define S3C6400_CLKSRC_MMC1_MASK       (0x3 << 20)
36580 +#define S3C6400_CLKSRC_MMC1_SHIFT      (20)
36581 +#define S3C6400_CLKSRC_MMC0_MASK       (0x3 << 18)
36582 +#define S3C6400_CLKSRC_MMC0_SHIFT      (18)
36583 +#define S3C6400_CLKSRC_SPI1_MASK       (0x3 << 16)
36584 +#define S3C6400_CLKSRC_SPI1_SHIFT      (16)
36585 +#define S3C6400_CLKSRC_SPI0_MASK       (0x3 << 14)
36586 +#define S3C6400_CLKSRC_SPI0_SHIFT      (14)
36587 +#define S3C6400_CLKSRC_UART_MASK       (0x1 << 13)
36588 +#define S3C6400_CLKSRC_UART_SHIFT      (13)
36589 +#define S3C6400_CLKSRC_AUDIO1_MASK     (0x7 << 10)
36590 +#define S3C6400_CLKSRC_AUDIO1_SHIFT    (10)
36591 +#define S3C6400_CLKSRC_AUDIO0_MASK     (0x7 << 7)
36592 +#define S3C6400_CLKSRC_AUDIO0_SHIFT    (7)
36593 +#define S3C6400_CLKSRC_UHOST_MASK      (0x3 << 5)
36594 +#define S3C6400_CLKSRC_UHOST_SHIFT     (5)
36595 +
36596 +
36597 +#endif /* _PLAT_REGS_CLOCK_H */
36598 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
36599 ===================================================================
36600 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36601 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h 2009-01-02 00:01:56.000000000 +0100
36602 @@ -0,0 +1,187 @@
36603 +/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
36604 + *
36605 + * Copyright 2008 Openmoko, Inc.
36606 + * Copyright 2008 Simtec Electronics
36607 + *      Ben Dooks <ben@simtec.co.uk>
36608 + *      http://armlinux.simtec.co.uk/
36609 + *
36610 + * S3C64XX - GPIO register definitions
36611 + */
36612 +
36613 +#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
36614 +#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
36615 +
36616 +/* Base addresses for each of the banks */
36617 +
36618 +#define S3C64XX_GPIOREG(reg)   (S3C64XX_VA_GPIO + (reg))
36619 +
36620 +#define S3C64XX_GPA_BASE       S3C64XX_GPIOREG(0x0000)
36621 +#define S3C64XX_GPB_BASE       S3C64XX_GPIOREG(0x0020)
36622 +#define S3C64XX_GPC_BASE       S3C64XX_GPIOREG(0x0040)
36623 +#define S3C64XX_GPD_BASE       S3C64XX_GPIOREG(0x0060)
36624 +#define S3C64XX_GPE_BASE       S3C64XX_GPIOREG(0x0080)
36625 +#define S3C64XX_GPF_BASE       S3C64XX_GPIOREG(0x00A0)
36626 +#define S3C64XX_GPG_BASE       S3C64XX_GPIOREG(0x00C0)
36627 +#define S3C64XX_GPH_BASE       S3C64XX_GPIOREG(0x00E0)
36628 +#define S3C64XX_GPI_BASE       S3C64XX_GPIOREG(0x0100)
36629 +#define S3C64XX_GPJ_BASE       S3C64XX_GPIOREG(0x0120)
36630 +#define S3C64XX_GPK_BASE       S3C64XX_GPIOREG(0x0800)
36631 +#define S3C64XX_GPL_BASE       S3C64XX_GPIOREG(0x0810)
36632 +#define S3C64XX_GPM_BASE       S3C64XX_GPIOREG(0x0820)
36633 +#define S3C64XX_GPN_BASE       S3C64XX_GPIOREG(0x0830)
36634 +#define S3C64XX_GPO_BASE       S3C64XX_GPIOREG(0x0140)
36635 +#define S3C64XX_GPP_BASE       S3C64XX_GPIOREG(0x0160)
36636 +#define S3C64XX_GPQ_BASE       S3C64XX_GPIOREG(0x0180)
36637 +
36638 +/* SPCON */
36639 +
36640 +#define S3C64XX_SPCON          S3C64XX_GPIOREG(0x1A0)
36641 +
36642 +#define S3C64XX_SPCON_DRVCON_CAM_MASK          (0x3 << 30)
36643 +#define S3C64XX_SPCON_DRVCON_CAM_SHIFT         (30)
36644 +#define S3C64XX_SPCON_DRVCON_CAM_2mA           (0x0 << 30)
36645 +#define S3C64XX_SPCON_DRVCON_CAM_4mA           (0x1 << 30)
36646 +#define S3C64XX_SPCON_DRVCON_CAM_7mA           (0x2 << 30)
36647 +#define S3C64XX_SPCON_DRVCON_CAM_9mA           (0x3 << 30)
36648 +
36649 +#define S3C64XX_SPCON_DRVCON_HSSPI_MASK                (0x3 << 28)
36650 +#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT       (28)
36651 +#define S3C64XX_SPCON_DRVCON_HSSPI_2mA         (0x0 << 28)
36652 +#define S3C64XX_SPCON_DRVCON_HSSPI_4mA         (0x1 << 28)
36653 +#define S3C64XX_SPCON_DRVCON_HSSPI_7mA         (0x2 << 28)
36654 +#define S3C64XX_SPCON_DRVCON_HSSPI_9mA         (0x3 << 28)
36655 +
36656 +#define S3C64XX_SPCON_DRVCON_HSMMC_MASK                (0x3 << 26)
36657 +#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT       (26)
36658 +#define S3C64XX_SPCON_DRVCON_HSMMC_2mA         (0x0 << 26)
36659 +#define S3C64XX_SPCON_DRVCON_HSMMC_4mA         (0x1 << 26)
36660 +#define S3C64XX_SPCON_DRVCON_HSMMC_7mA         (0x2 << 26)
36661 +#define S3C64XX_SPCON_DRVCON_HSMMC_9mA         (0x3 << 26)
36662 +
36663 +#define S3C64XX_SPCON_DRVCON_LCD_MASK          (0x3 << 24)
36664 +#define S3C64XX_SPCON_DRVCON_LCD_SHIFT         (24)
36665 +#define S3C64XX_SPCON_DRVCON_LCD_2mA           (0x0 << 24)
36666 +#define S3C64XX_SPCON_DRVCON_LCD_4mA           (0x1 << 24)
36667 +#define S3C64XX_SPCON_DRVCON_LCD_7mA           (0x2 << 24)
36668 +#define S3C64XX_SPCON_DRVCON_LCD_9mA           (0x3 << 24)
36669 +
36670 +#define S3C64XX_SPCON_DRVCON_MODEM_MASK                (0x3 << 22)
36671 +#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT       (22)
36672 +#define S3C64XX_SPCON_DRVCON_MODEM_2mA         (0x0 << 22)
36673 +#define S3C64XX_SPCON_DRVCON_MODEM_4mA         (0x1 << 22)
36674 +#define S3C64XX_SPCON_DRVCON_MODEM_7mA         (0x2 << 22)
36675 +#define S3C64XX_SPCON_DRVCON_MODEM_9mA         (0x3 << 22)
36676 +
36677 +#define S3C64XX_SPCON_nRSTOUT_OEN              (1 << 21)
36678 +
36679 +#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK      (0x3 << 18)
36680 +#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT     (18)
36681 +#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA       (0x0 << 18)
36682 +#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA       (0x1 << 18)
36683 +#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA       (0x2 << 18)
36684 +#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA       (0x3 << 18)
36685 +
36686 +#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK                (0x3 << 16)
36687 +#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT       (16)
36688 +#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED    (0x0 << 16)
36689 +#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN                (0x1 << 16)
36690 +#define S3C64XX_SPCON_MEM1_DQS_PUD_UP          (0x2 << 16)
36691 +
36692 +#define S3C64XX_SPCON_MEM1_D_PUD1_MASK         (0x3 << 14)
36693 +#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT                (14)
36694 +#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED     (0x0 << 14)
36695 +#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN         (0x1 << 14)
36696 +#define S3C64XX_SPCON_MEM1_D_PUD1_UP           (0x2 << 14)
36697 +
36698 +#define S3C64XX_SPCON_MEM1_D_PUD0_MASK         (0x3 << 12)
36699 +#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT                (12)
36700 +#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED     (0x0 << 12)
36701 +#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN         (0x1 << 12)
36702 +#define S3C64XX_SPCON_MEM1_D_PUD0_UP           (0x2 << 12)
36703 +
36704 +#define S3C64XX_SPCON_MEM0_D_PUD_MASK          (0x3 << 8)
36705 +#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT         (8)
36706 +#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED      (0x0 << 8)
36707 +#define S3C64XX_SPCON_MEM0_D_PUD_DOWN          (0x1 << 8)
36708 +#define S3C64XX_SPCON_MEM0_D_PUD_UP            (0x2 << 8)
36709 +
36710 +#define S3C64XX_SPCON_USBH_DMPD                        (1 << 7)
36711 +#define S3C64XX_SPCON_USBH_DPPD                        (1 << 6)
36712 +#define S3C64XX_SPCON_USBH_PUSW2               (1 << 5)
36713 +#define S3C64XX_SPCON_USBH_PUSW1               (1 << 4)
36714 +#define S3C64XX_SPCON_USBH_SUSPND              (1 << 3)
36715 +
36716 +#define S3C64XX_SPCON_LCD_SEL_MASK             (0x3 << 0)
36717 +#define S3C64XX_SPCON_LCD_SEL_SHIFT            (0)
36718 +#define S3C64XX_SPCON_LCD_SEL_HOST             (0x0 << 0)
36719 +#define S3C64XX_SPCON_LCD_SEL_RGB              (0x1 << 0)
36720 +#define S3C64XX_SPCON_LCD_SEL_606_656          (0x2 << 0)
36721 +
36722 +
36723 +/* External interrupt registers */
36724 +
36725 +#define S3C64XX_EINT12CON      S3C64XX_GPIOREG(0x200)
36726 +#define S3C64XX_EINT34CON      S3C64XX_GPIOREG(0x204)
36727 +#define S3C64XX_EINT56CON      S3C64XX_GPIOREG(0x208)
36728 +#define S3C64XX_EINT78CON      S3C64XX_GPIOREG(0x20C)
36729 +#define S3C64XX_EINT9CON       S3C64XX_GPIOREG(0x210)
36730 +
36731 +#define S3C64XX_EINT12FLTCON   S3C64XX_GPIOREG(0x220)
36732 +#define S3C64XX_EINT34FLTCON   S3C64XX_GPIOREG(0x224)
36733 +#define S3C64XX_EINT56FLTCON   S3C64XX_GPIOREG(0x228)
36734 +#define S3C64XX_EINT78FLTCON   S3C64XX_GPIOREG(0x22C)
36735 +#define S3C64XX_EINT9FLTCON    S3C64XX_GPIOREG(0x230)
36736 +
36737 +#define S3C64XX_EINT12MASK     S3C64XX_GPIOREG(0x240)
36738 +#define S3C64XX_EINT34MASK     S3C64XX_GPIOREG(0x244)
36739 +#define S3C64XX_EINT56MASK     S3C64XX_GPIOREG(0x248)
36740 +#define S3C64XX_EINT78MASK     S3C64XX_GPIOREG(0x24C)
36741 +#define S3C64XX_EINT9MASK      S3C64XX_GPIOREG(0x250)
36742 +
36743 +#define S3C64XX_EINT12PEND     S3C64XX_GPIOREG(0x260)
36744 +#define S3C64XX_EINT34PEND     S3C64XX_GPIOREG(0x264)
36745 +#define S3C64XX_EINT56PEND     S3C64XX_GPIOREG(0x268)
36746 +#define S3C64XX_EINT78PEND     S3C64XX_GPIOREG(0x26C)
36747 +#define S3C64XX_EINT9PEND      S3C64XX_GPIOREG(0x270)
36748 +
36749 +#define S3C64XX_PRIORITY       S3C64XX_GPIOREG(0x280)
36750 +#define S3C64XX_PRIORITY_ARB(x)        (1 << (x))
36751 +
36752 +#define S3C64XX_SERVICE                S3C64XX_GPIOREG(0x284)
36753 +#define S3C64XX_SERVICEPEND    S3C64XX_GPIOREG(0x288)
36754 +
36755 +#define S3C64XX_EINT0CON0      S3C64XX_GPIOREG(0x900)
36756 +#define S3C64XX_EINT0CON1      S3C64XX_GPIOREG(0x904)
36757 +#define S3C64XX_EINT0FLTCON0   S3C64XX_GPIOREG(0x910)
36758 +#define S3C64XX_EINT0FLTCON1   S3C64XX_GPIOREG(0x914)
36759 +#define S3C64XX_EINT0FLTCON2   S3C64XX_GPIOREG(0x918)
36760 +#define S3C64XX_EINT0FLTCON3   S3C64XX_GPIOREG(0x91C)
36761 +
36762 +#define S3C64XX_EINT0MASK      S3C64XX_GPIOREG(0x920)
36763 +#define S3C64XX_EINT0PEND      S3C64XX_GPIOREG(0x924)
36764 +
36765 +/* GPIO sleep configuration */
36766 +
36767 +#define S3C64XX_SPCONSLP       S3C64XX_GPIOREG(0x880)
36768 +
36769 +#define S3C64XX_SPCONSLP_TDO_PULLDOWN  (1 << 14)
36770 +#define S3C64XX_SPCONSLP_CKE1INIT      (1 << 5)
36771 +
36772 +#define S3C64XX_SPCONSLP_RSTOUT_MASK   (0x3 << 12)
36773 +#define S3C64XX_SPCONSLP_RSTOUT_OUT0   (0x0 << 12)
36774 +#define S3C64XX_SPCONSLP_RSTOUT_OUT1   (0x1 << 12)
36775 +#define S3C64XX_SPCONSLP_RSTOUT_HIZ    (0x2 << 12)
36776 +
36777 +#define S3C64XX_SPCONSLP_KPCOL_MASK    (0x3 << 0)
36778 +#define S3C64XX_SPCONSLP_KPCOL_OUT0    (0x0 << 0)
36779 +#define S3C64XX_SPCONSLP_KPCOL_OUT1    (0x1 << 0)
36780 +#define S3C64XX_SPCONSLP_KPCOL_INP     (0x2 << 0)
36781 +
36782 +
36783 +#define S3C64XX_SLPEN          S3C64XX_GPIOREG(0x930)
36784 +
36785 +#define S3C64XX_SLPEN_USE_xSLP         (1 << 0)
36786 +#define S3C64XX_SLPEN_CFG_BYSLPEN      (1 << 1)
36787 +
36788 +#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
36789 +
36790 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
36791 ===================================================================
36792 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36793 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h 2009-01-02 00:01:56.000000000 +0100
36794 @@ -0,0 +1,25 @@
36795 +/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
36796 + *
36797 + * Copyright 2008 Openmoko, Inc.
36798 + * Copyright 2008 Simtec Electronics
36799 + *      Ben Dooks <ben@simtec.co.uk>
36800 + *      http://armlinux.simtec.co.uk/
36801 + *
36802 + * S3C64XX - GPIO memory port register definitions
36803 + */
36804 +
36805 +#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
36806 +#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
36807 +
36808 +#define S3C64XX_MEM0CONSTOP    S3C64XX_GPIOREG(0x1B0)
36809 +#define S3C64XX_MEM1CONSTOP    S3C64XX_GPIOREG(0x1B4)
36810 +
36811 +#define S3C64XX_MEM0CONSLP0    S3C64XX_GPIOREG(0x1C0)
36812 +#define S3C64XX_MEM0CONSLP1    S3C64XX_GPIOREG(0x1C4)
36813 +#define S3C64XX_MEM1CONSLP     S3C64XX_GPIOREG(0x1C8)
36814 +
36815 +#define S3C64XX_MEM0DRVCON     S3C64XX_GPIOREG(0x1D0)
36816 +#define S3C64XX_MEM1DRVCON     S3C64XX_GPIOREG(0x1D4)
36817 +
36818 +#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
36819 +
36820 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
36821 ===================================================================
36822 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36823 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-modem.h        2009-01-02 00:01:56.000000000 +0100
36824 @@ -0,0 +1,31 @@
36825 +/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
36826 + *
36827 + * Copyright 2008 Openmoko, Inc.
36828 + * Copyright 2008 Simtec Electronics
36829 + *      http://armlinux.simtec.co.uk/
36830 + *      Ben Dooks <ben@simtec.co.uk>
36831 + *
36832 + * S3C64XX - modem block registers
36833 + *
36834 + * This program is free software; you can redistribute it and/or modify
36835 + * it under the terms of the GNU General Public License version 2 as
36836 + * published by the Free Software Foundation.
36837 +*/
36838 +
36839 +#ifndef __PLAT_S3C64XX_REGS_MODEM_H
36840 +#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
36841 +
36842 +#define S3C64XX_MODEMREG(x)    (S3C64XX_VA_MODEM + (x))
36843 +
36844 +#define S3C64XX_MODEM_INT2AP                   S3C64XX_MODEMREG(0x0)
36845 +#define S3C64XX_MODEM_INT2MODEM                        S3C64XX_MODEMREG(0x4)
36846 +#define S3C64XX_MODEM_MIFCON                   S3C64XX_MODEMREG(0x8)
36847 +#define S3C64XX_MODEM_MIFPCON                  S3C64XX_MODEMREG(0xC)
36848 +#define S3C64XX_MODEM_INTCLR                   S3C64XX_MODEMREG(0x10)
36849 +#define S3C64XX_MODEM_DMA_TXADDR               S3C64XX_MODEMREG(0x14)
36850 +#define S3C64XX_MODEM_DMA_RXADDR               S3C64XX_MODEMREG(0x18)
36851 +
36852 +#define MIFPCON_INT2M_LEVEL                    (1 << 4)
36853 +#define MIFPCON_LCD_BYPASS                     (1 << 3)
36854 +
36855 +#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
36856 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
36857 ===================================================================
36858 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36859 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h 2009-01-02 00:01:56.000000000 +0100
36860 @@ -0,0 +1,116 @@
36861 +/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
36862 + *
36863 + * Copyright 2008 Openmoko, Inc.
36864 + * Copyright 2008 Simtec Electronics
36865 + *      http://armlinux.simtec.co.uk/
36866 + *      Ben Dooks <ben@simtec.co.uk>
36867 + *
36868 + * S3C64XX - syscon power and sleep control registers
36869 + *
36870 + * This program is free software; you can redistribute it and/or modify
36871 + * it under the terms of the GNU General Public License version 2 as
36872 + * published by the Free Software Foundation.
36873 +*/
36874 +
36875 +#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
36876 +#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
36877 +
36878 +#define S3C64XX_PWR_CFG                                S3C_SYSREG(0x804)
36879 +
36880 +#define S3C64XX_PWRCFG_OSC_OTG_DISABLE         (1 << 17)
36881 +#define S3C64XX_PWRCFG_MMC2_DISABLE            (1 << 16)
36882 +#define S3C64XX_PWRCFG_MMC1_DISABLE            (1 << 15)
36883 +#define S3C64XX_PWRCFG_MMC0_DISABLE            (1 << 14)
36884 +#define S3C64XX_PWRCFG_HSI_DISABLE             (1 << 13)
36885 +#define S3C64XX_PWRCFG_TS_DISABLE              (1 << 12)
36886 +#define S3C64XX_PWRCFG_RTC_TICK_DISABLE                (1 << 11)
36887 +#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE       (1 << 10)
36888 +#define S3C64XX_PWRCFG_MSM_DISABLE             (1 << 9)
36889 +#define S3C64XX_PWRCFG_KEY_DISABLE             (1 << 8)
36890 +#define S3C64XX_PWRCFG_BATF_DISABLE            (1 << 7)
36891 +
36892 +#define S3C64XX_PWRCFG_CFG_WFI_MASK            (0x3 << 5)
36893 +#define S3C64XX_PWRCFG_CFG_WFI_SHIFT           (5)
36894 +#define S3C64XX_PWRCFG_CFG_WFI_IGNORE          (0x0 << 5)
36895 +#define S3C64XX_PWRCFG_CFG_WFI_IDLE            (0x1 << 5)
36896 +#define S3C64XX_PWRCFG_CFG_WFI_STOP            (0x2 << 5)
36897 +#define S3C64XX_PWRCFG_CFG_WFI_SLEEP           (0x3 << 5)
36898 +
36899 +#define S3C64XX_PWRCFG_CFG_BATFLT_MASK         (0x3 << 3)
36900 +#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT                (3)
36901 +#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE       (0x0 << 3)
36902 +#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ          (0x1 << 3)
36903 +#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP                (0x3 << 3)
36904 +
36905 +#define S3C64XX_PWRCFG_CFG_BAT_WAKE            (1 << 2)
36906 +#define S3C64XX_PWRCFG_OSC27_EN                        (1 << 0)
36907 +
36908 +#define S3C64XX_EINT_MASK                      S3C_SYSREG(0x808)
36909 +
36910 +#define S3C64XX_NORMAL_CFG                     S3C_SYSREG(0x810)
36911 +
36912 +#define S3C64XX_NORMALCFG_IROM_ON              (1 << 30)
36913 +#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON                (1 << 16)
36914 +#define S3C64XX_NORMALCFG_DOMAIN_S_ON          (1 << 15)
36915 +#define S3C64XX_NORMALCFG_DOMAIN_F_ON          (1 << 14)
36916 +#define S3C64XX_NORMALCFG_DOMAIN_P_ON          (1 << 13)
36917 +#define S3C64XX_NORMALCFG_DOMAIN_I_ON          (1 << 12)
36918 +#define S3C64XX_NORMALCFG_DOMAIN_G_ON          (1 << 10)
36919 +#define S3C64XX_NORMALCFG_DOMAIN_V_ON          (1 << 9)
36920 +
36921 +#define S3C64XX_STOP_CFG                       S3C_SYSREG(0x814)
36922 +
36923 +#define S3C64XX_STOPCFG_MEMORY_ARM_ON          (1 << 29)
36924 +#define S3C64XX_STOPCFG_TOP_MEMORY_ON          (1 << 20)
36925 +#define S3C64XX_STOPCFG_ARM_LOGIC_ON           (1 << 17)
36926 +#define S3C64XX_STOPCFG_TOP_LOGIC_ON           (1 << 8)
36927 +#define S3C64XX_STOPCFG_OSC_EN                 (1 << 0)
36928 +
36929 +#define S3C64XX_SLEEP_CFG                      S3C_SYSREG(0x818)
36930 +
36931 +#define S3C64XX_SLEEPCFG_OSC_EN                        (1 << 0)
36932 +
36933 +#define S3C64XX_STOP_MEM_CFG                   S3C_SYSREG(0x81c)
36934 +
36935 +#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN      (1 << 6)
36936 +#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN       (1 << 5)
36937 +#define S3C64XX_STOPMEMCFG_OTG_RETAIN          (1 << 4)
36938 +#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN                (1 << 3)
36939 +#define S3C64XX_STOPMEMCFG_IROM_RETAIN         (1 << 2)
36940 +#define S3C64XX_STOPMEMCFG_IRDA_RETAIN         (1 << 1)
36941 +#define S3C64XX_STOPMEMCFG_NFCON_RETAIN                (1 << 0)
36942 +
36943 +#define S3C64XX_OSC_STABLE                     S3C_SYSREG(0x824)
36944 +#define S3C64XX_PWR_STABLE                     S3C_SYSREG(0x828)
36945 +
36946 +#define S3C64XX_WAKEUP_STAT                    S3C_SYSREG(0x908)
36947 +
36948 +#define S3C64XX_WAKEUPSTAT_MMC2                        (1 << 11)
36949 +#define S3C64XX_WAKEUPSTAT_MMC1                        (1 << 10)
36950 +#define S3C64XX_WAKEUPSTAT_MMC0                        (1 << 9)
36951 +#define S3C64XX_WAKEUPSTAT_HSI                 (1 << 8)
36952 +#define S3C64XX_WAKEUPSTAT_BATFLT              (1 << 6)
36953 +#define S3C64XX_WAKEUPSTAT_MSM                 (1 << 5)
36954 +#define S3C64XX_WAKEUPSTAT_KEY                 (1 << 4)
36955 +#define S3C64XX_WAKEUPSTAT_TS                  (1 << 3)
36956 +#define S3C64XX_WAKEUPSTAT_RTC_TICK            (1 << 2)
36957 +#define S3C64XX_WAKEUPSTAT_RTC_ALARM           (1 << 1)
36958 +#define S3C64XX_WAKEUPSTAT_EINT                        (1 << 0)
36959 +
36960 +#define S3C64XX_BLK_PWR_STAT                   S3C_SYSREG(0x90c)
36961 +
36962 +#define S3C64XX_BLKPWRSTAT_G                   (1 << 7)
36963 +#define S3C64XX_BLKPWRSTAT_ETM                 (1 << 6)
36964 +#define S3C64XX_BLKPWRSTAT_S                   (1 << 5)
36965 +#define S3C64XX_BLKPWRSTAT_F                   (1 << 4)
36966 +#define S3C64XX_BLKPWRSTAT_P                   (1 << 3)
36967 +#define S3C64XX_BLKPWRSTAT_I                   (1 << 2)
36968 +#define S3C64XX_BLKPWRSTAT_V                   (1 << 1)
36969 +#define S3C64XX_BLKPWRSTAT_TOP                 (1 << 0)
36970 +
36971 +#define S3C64XX_INFORM0                                S3C_SYSREG(0xA00)
36972 +#define S3C64XX_INFORM1                                S3C_SYSREG(0xA04)
36973 +#define S3C64XX_INFORM2                                S3C_SYSREG(0xA08)
36974 +#define S3C64XX_INFORM3                                S3C_SYSREG(0xA0C)
36975 +
36976 +#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
36977 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
36978 ===================================================================
36979 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
36980 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-sys.h  2009-01-02 00:01:56.000000000 +0100
36981 @@ -0,0 +1,28 @@
36982 +/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
36983 + *
36984 + * Copyright 2008 Openmoko, Inc.
36985 + * Copyright 2008 Simtec Electronics
36986 + *     Ben Dooks <ben@simtec.co.uk>
36987 + *     http://armlinux.simtec.co.uk/
36988 + *
36989 + * S3C64XX system register definitions
36990 + *
36991 + * This program is free software; you can redistribute it and/or modify
36992 + * it under the terms of the GNU General Public License version 2 as
36993 + * published by the Free Software Foundation.
36994 +*/
36995 +
36996 +#ifndef __PLAT_REGS_SYS_H
36997 +#define __PLAT_REGS_SYS_H __FILE__
36998 +
36999 +#define S3C_SYSREG(x)          (S3C_VA_SYS + (x))
37000 +
37001 +#define S3C64XX_AHB_CON0       S3C_SYSREG(0x100)
37002 +#define S3C64XX_AHB_CON1       S3C_SYSREG(0x104)
37003 +#define S3C64XX_AHB_CON2       S3C_SYSREG(0x108)
37004 +
37005 +#define S3C64XX_OTHERS         S3C_SYSREG(0x900)
37006 +
37007 +#define S3C64XX_OTHERS_USBMASK (1 << 16)
37008 +
37009 +#endif /* _PLAT_REGS_SYS_H */
37010 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
37011 ===================================================================
37012 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37013 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6400.h   2009-01-02 00:01:56.000000000 +0100
37014 @@ -0,0 +1,35 @@
37015 +/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h
37016 + *
37017 + * Copyright 2008 Openmoko, Inc.
37018 + * Copyright 2008 Simtec Electronics
37019 + *     Ben Dooks <ben@simtec.co.uk>
37020 + *     http://armlinux.simtec.co.uk/
37021 + *
37022 + * Header file for s3c6400 cpu support
37023 + *
37024 + * This program is free software; you can redistribute it and/or modify
37025 + * it under the terms of the GNU General Public License version 2 as
37026 + * published by the Free Software Foundation.
37027 +*/
37028 +
37029 +/* Common init code for S3C6400 related SoCs */
37030 +
37031 +extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
37032 +extern void s3c6400_register_clocks(void);
37033 +extern void s3c6400_setup_clocks(void);
37034 +
37035 +#ifdef CONFIG_CPU_S3C6400
37036 +
37037 +extern  int s3c6400_init(void);
37038 +extern void s3c6400_map_io(void);
37039 +extern void s3c6400_init_clocks(int xtal);
37040 +
37041 +#define s3c6400_init_uarts s3c6400_common_init_uarts
37042 +
37043 +#else
37044 +#define s3c6400_init_clocks NULL
37045 +#define s3c6400_init_uarts NULL
37046 +#define s3c6400_map_io NULL
37047 +#define s3c6400_init NULL
37048 +#endif
37049 +
37050 Index: linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6410.h
37051 ===================================================================
37052 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37053 +++ linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6410.h   2009-01-02 00:01:56.000000000 +0100
37054 @@ -0,0 +1,29 @@
37055 +/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h
37056 + *
37057 + * Copyright 2008 Openmoko,  Inc.
37058 + * Copyright 2008 Simtec Electronics
37059 + *     Ben Dooks <ben@simtec.co.uk>
37060 + *     http://armlinux.simtec.co.uk/
37061 + *
37062 + * Header file for s3c6410 cpu support
37063 + *
37064 + * This program is free software; you can redistribute it and/or modify
37065 + * it under the terms of the GNU General Public License version 2 as
37066 + * published by the Free Software Foundation.
37067 +*/
37068 +
37069 +#ifdef CONFIG_CPU_S3C6410
37070 +
37071 +extern  int s3c6410_init(void);
37072 +extern void s3c6410_init_irq(void);
37073 +extern void s3c6410_map_io(void);
37074 +extern void s3c6410_init_clocks(int xtal);
37075 +
37076 +#define s3c6410_init_uarts s3c6400_common_init_uarts
37077 +
37078 +#else
37079 +#define s3c6410_init_clocks NULL
37080 +#define s3c6410_init_uarts NULL
37081 +#define s3c6410_map_io NULL
37082 +#define s3c6410_init NULL
37083 +#endif
37084 Index: linux-2.6.28/arch/arm/plat-s3c64xx/irq.c
37085 ===================================================================
37086 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37087 +++ linux-2.6.28/arch/arm/plat-s3c64xx/irq.c    2009-01-02 00:01:56.000000000 +0100
37088 @@ -0,0 +1,256 @@
37089 +/* arch/arm/plat-s3c64xx/irq.c
37090 + *
37091 + * Copyright 2008 Openmoko, Inc.
37092 + * Copyright 2008 Simtec Electronics
37093 + *      Ben Dooks <ben@simtec.co.uk>
37094 + *      http://armlinux.simtec.co.uk/
37095 + *
37096 + * S3C64XX - Interrupt handling
37097 + *
37098 + * This program is free software; you can redistribute it and/or modify
37099 + * it under the terms of the GNU General Public License version 2 as
37100 + * published by the Free Software Foundation.
37101 + */
37102 +
37103 +#include <linux/kernel.h>
37104 +#include <linux/interrupt.h>
37105 +#include <linux/serial_core.h>
37106 +#include <linux/irq.h>
37107 +#include <linux/io.h>
37108 +
37109 +#include <asm/hardware/vic.h>
37110 +
37111 +#include <mach/map.h>
37112 +#include <plat/regs-serial.h>
37113 +#include <plat/regs-timer.h>
37114 +#include <plat/cpu.h>
37115 +
37116 +/* Timer interrupt handling */
37117 +
37118 +static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
37119 +{
37120 +       generic_handle_irq(sub_irq);
37121 +}
37122 +
37123 +static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
37124 +{
37125 +       s3c_irq_demux_timer(irq, IRQ_TIMER0);
37126 +}
37127 +
37128 +static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
37129 +{
37130 +       s3c_irq_demux_timer(irq, IRQ_TIMER1);
37131 +}
37132 +
37133 +static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
37134 +{
37135 +       s3c_irq_demux_timer(irq, IRQ_TIMER2);
37136 +}
37137 +
37138 +static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
37139 +{
37140 +       s3c_irq_demux_timer(irq, IRQ_TIMER3);
37141 +}
37142 +
37143 +static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
37144 +{
37145 +       s3c_irq_demux_timer(irq, IRQ_TIMER4);
37146 +}
37147 +
37148 +/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
37149 +
37150 +static void s3c_irq_timer_mask(unsigned int irq)
37151 +{
37152 +       u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
37153 +
37154 +       reg &= 0x1f;  /* mask out pending interrupts */
37155 +       reg &= ~(1 << (irq - IRQ_TIMER0));
37156 +       __raw_writel(reg, S3C64XX_TINT_CSTAT);
37157 +}
37158 +
37159 +static void s3c_irq_timer_unmask(unsigned int irq)
37160 +{
37161 +       u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
37162 +
37163 +       reg &= 0x1f;  /* mask out pending interrupts */
37164 +       reg |= 1 << (irq - IRQ_TIMER0);
37165 +       __raw_writel(reg, S3C64XX_TINT_CSTAT);
37166 +}
37167 +
37168 +static void s3c_irq_timer_ack(unsigned int irq)
37169 +{
37170 +       u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
37171 +
37172 +       reg &= 0x1f;
37173 +       reg |= (1 << 5) << (irq - IRQ_TIMER0);
37174 +       __raw_writel(reg, S3C64XX_TINT_CSTAT);
37175 +}
37176 +
37177 +static struct irq_chip s3c_irq_timer = {
37178 +       .name           = "s3c-timer",
37179 +       .mask           = s3c_irq_timer_mask,
37180 +       .unmask         = s3c_irq_timer_unmask,
37181 +       .ack            = s3c_irq_timer_ack,
37182 +};
37183 +
37184 +struct uart_irq {
37185 +       void __iomem    *regs;
37186 +       unsigned int     base_irq;
37187 +       unsigned int     parent_irq;
37188 +};
37189 +
37190 +/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
37191 + * are consecutive when looking up the interrupt in the demux routines.
37192 + */
37193 +static struct uart_irq uart_irqs[] = {
37194 +       [0] = {
37195 +               .regs           = S3C_VA_UART0,
37196 +               .base_irq       = IRQ_S3CUART_BASE0,
37197 +               .parent_irq     = IRQ_UART0,
37198 +       },
37199 +       [1] = {
37200 +               .regs           = S3C_VA_UART1,
37201 +               .base_irq       = IRQ_S3CUART_BASE1,
37202 +               .parent_irq     = IRQ_UART1,
37203 +       },
37204 +       [2] = {
37205 +               .regs           = S3C_VA_UART2,
37206 +               .base_irq       = IRQ_S3CUART_BASE2,
37207 +               .parent_irq     = IRQ_UART2,
37208 +       },
37209 +       [3] = {
37210 +               .regs           = S3C_VA_UART3,
37211 +               .base_irq       = IRQ_S3CUART_BASE3,
37212 +               .parent_irq     = IRQ_UART3,
37213 +       },
37214 +};
37215 +
37216 +static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
37217 +{
37218 +       struct uart_irq *uirq = get_irq_chip_data(irq);
37219 +       return uirq->regs;
37220 +}
37221 +
37222 +static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
37223 +{
37224 +       return irq & 3;
37225 +}
37226 +
37227 +/* UART interrupt registers, not worth adding to seperate include header */
37228 +
37229 +static void s3c_irq_uart_mask(unsigned int irq)
37230 +{
37231 +       void __iomem *regs = s3c_irq_uart_base(irq);
37232 +       unsigned int bit = s3c_irq_uart_bit(irq);
37233 +       u32 reg;
37234 +
37235 +       reg = __raw_readl(regs + S3C64XX_UINTM);
37236 +       reg |= (1 << bit);
37237 +       __raw_writel(reg, regs + S3C64XX_UINTM);
37238 +}
37239 +
37240 +static void s3c_irq_uart_maskack(unsigned int irq)
37241 +{
37242 +       void __iomem *regs = s3c_irq_uart_base(irq);
37243 +       unsigned int bit = s3c_irq_uart_bit(irq);
37244 +       u32 reg;
37245 +
37246 +       reg = __raw_readl(regs + S3C64XX_UINTM);
37247 +       reg |= (1 << bit);
37248 +       __raw_writel(reg, regs + S3C64XX_UINTM);
37249 +       __raw_writel(1 << bit, regs + S3C64XX_UINTP);
37250 +}
37251 +
37252 +static void s3c_irq_uart_unmask(unsigned int irq)
37253 +{
37254 +       void __iomem *regs = s3c_irq_uart_base(irq);
37255 +       unsigned int bit = s3c_irq_uart_bit(irq);
37256 +       u32 reg;
37257 +
37258 +       reg = __raw_readl(regs + S3C64XX_UINTM);
37259 +       reg &= ~(1 << bit);
37260 +       __raw_writel(reg, regs + S3C64XX_UINTM);
37261 +}
37262 +
37263 +static void s3c_irq_uart_ack(unsigned int irq)
37264 +{
37265 +       void __iomem *regs = s3c_irq_uart_base(irq);
37266 +       unsigned int bit = s3c_irq_uart_bit(irq);
37267 +
37268 +       __raw_writel(1 << bit, regs + S3C64XX_UINTP);
37269 +}
37270 +
37271 +static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
37272 +{
37273 +       struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
37274 +       u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
37275 +       int base = uirq->base_irq;
37276 +
37277 +       if (pend & (1 << 0))
37278 +               generic_handle_irq(base);
37279 +       if (pend & (1 << 1))
37280 +               generic_handle_irq(base + 1);
37281 +       if (pend & (1 << 2))
37282 +               generic_handle_irq(base + 2);
37283 +       if (pend & (1 << 3))
37284 +               generic_handle_irq(base + 3);
37285 +}
37286 +
37287 +static struct irq_chip s3c_irq_uart = {
37288 +       .name           = "s3c-uart",
37289 +       .mask           = s3c_irq_uart_mask,
37290 +       .unmask         = s3c_irq_uart_unmask,
37291 +       .mask_ack       = s3c_irq_uart_maskack,
37292 +       .ack            = s3c_irq_uart_ack,
37293 +};
37294 +
37295 +static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
37296 +{
37297 +       void *reg_base = uirq->regs;
37298 +       unsigned int irq;
37299 +       int offs;
37300 +
37301 +       /* mask all interrupts at the start. */
37302 +       __raw_writel(0xf, reg_base + S3C64XX_UINTM);
37303 +
37304 +       for (offs = 0; offs < 3; offs++) {
37305 +               irq = uirq->base_irq + offs;
37306 +
37307 +               set_irq_chip(irq, &s3c_irq_uart);
37308 +               set_irq_chip_data(irq, uirq);
37309 +               set_irq_handler(irq, handle_level_irq);
37310 +               set_irq_flags(irq, IRQF_VALID);
37311 +       }
37312 +
37313 +       set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
37314 +}
37315 +
37316 +void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
37317 +{
37318 +       int uart, irq;
37319 +
37320 +       printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
37321 +
37322 +       /* initialise the pair of VICs */
37323 +       vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
37324 +       vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
37325 +
37326 +       /* add the timer sub-irqs */
37327 +
37328 +       set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
37329 +       set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
37330 +       set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
37331 +       set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
37332 +       set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
37333 +
37334 +       for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
37335 +               set_irq_chip(irq, &s3c_irq_timer);
37336 +               set_irq_handler(irq, handle_level_irq);
37337 +               set_irq_flags(irq, IRQF_VALID);
37338 +       }
37339 +
37340 +       for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
37341 +               s3c64xx_uart_irq(&uart_irqs[uart]);
37342 +}
37343 +
37344 +
37345 Index: linux-2.6.28/arch/arm/plat-s3c64xx/irq-eint.c
37346 ===================================================================
37347 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37348 +++ linux-2.6.28/arch/arm/plat-s3c64xx/irq-eint.c       2009-01-02 00:01:56.000000000 +0100
37349 @@ -0,0 +1,204 @@
37350 +/* arch/arm/plat-s3c64xx/irq-eint.c
37351 + *
37352 + * Copyright 2008 Openmoko, Inc.
37353 + * Copyright 2008 Simtec Electronics
37354 + *      Ben Dooks <ben@simtec.co.uk>
37355 + *      http://armlinux.simtec.co.uk/
37356 + *
37357 + * S3C64XX - Interrupt handling for IRQ_EINT(x)
37358 + *
37359 + * This program is free software; you can redistribute it and/or modify
37360 + * it under the terms of the GNU General Public License version 2 as
37361 + * published by the Free Software Foundation.
37362 + */
37363 +
37364 +#include <linux/kernel.h>
37365 +#include <linux/interrupt.h>
37366 +#include <linux/gpio.h>
37367 +#include <linux/irq.h>
37368 +#include <linux/io.h>
37369 +#include <linux/gpio.h>
37370 +
37371 +#include <asm/hardware/vic.h>
37372 +
37373 +#include <plat/regs-irqtype.h>
37374 +#include <plat/regs-gpio.h>
37375 +#include <plat/gpio-cfg.h>
37376 +
37377 +#include <mach/map.h>
37378 +#include <plat/cpu.h>
37379 +#include <plat/pm.h>
37380 +
37381 +#define eint_offset(irq)       ((irq) - IRQ_EINT(0))
37382 +#define eint_irq_to_bit(irq)   (1 << eint_offset(irq))
37383 +
37384 +static inline void s3c_irq_eint_mask(unsigned int irq)
37385 +{
37386 +       u32 mask;
37387 +
37388 +       mask = __raw_readl(S3C64XX_EINT0MASK);
37389 +       mask |= eint_irq_to_bit(irq);
37390 +       __raw_writel(mask, S3C64XX_EINT0MASK);
37391 +}
37392 +
37393 +static void s3c_irq_eint_unmask(unsigned int irq)
37394 +{
37395 +       u32 mask;
37396 +
37397 +       mask = __raw_readl(S3C64XX_EINT0MASK);
37398 +       mask &= ~eint_irq_to_bit(irq);
37399 +       __raw_writel(mask, S3C64XX_EINT0MASK);
37400 +}
37401 +
37402 +static inline void s3c_irq_eint_ack(unsigned int irq)
37403 +{
37404 +       __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
37405 +}
37406 +
37407 +static void s3c_irq_eint_maskack(unsigned int irq)
37408 +{
37409 +       /* compiler should in-line these */
37410 +       s3c_irq_eint_mask(irq);
37411 +       s3c_irq_eint_ack(irq);
37412 +}
37413 +
37414 +static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
37415 +{
37416 +       int offs = eint_offset(irq);
37417 +       int pin;
37418 +       int shift;
37419 +       u32 ctrl, mask;
37420 +       u32 newvalue = 0;
37421 +       void __iomem *reg;
37422 +
37423 +       if (offs > 27)
37424 +               return -EINVAL;
37425 +
37426 +       if (offs <= 15)
37427 +               reg = S3C64XX_EINT0CON0;
37428 +       else
37429 +               reg = S3C64XX_EINT0CON1;
37430 +
37431 +       switch (type) {
37432 +       case IRQ_TYPE_NONE:
37433 +               printk(KERN_WARNING "No edge setting!\n");
37434 +               break;
37435 +
37436 +       case IRQ_TYPE_EDGE_RISING:
37437 +               newvalue = S3C2410_EXTINT_RISEEDGE;
37438 +               break;
37439 +
37440 +       case IRQ_TYPE_EDGE_FALLING:
37441 +               newvalue = S3C2410_EXTINT_FALLEDGE;
37442 +               break;
37443 +
37444 +       case IRQ_TYPE_EDGE_BOTH:
37445 +               newvalue = S3C2410_EXTINT_BOTHEDGE;
37446 +               break;
37447 +
37448 +       case IRQ_TYPE_LEVEL_LOW:
37449 +               newvalue = S3C2410_EXTINT_LOWLEV;
37450 +               break;
37451 +
37452 +       case IRQ_TYPE_LEVEL_HIGH:
37453 +               newvalue = S3C2410_EXTINT_HILEV;
37454 +               break;
37455 +
37456 +       default:
37457 +               printk(KERN_ERR "No such irq type %d", type);
37458 +               return -1;
37459 +       }
37460 +
37461 +       shift = (offs / 2) * 4;
37462 +       mask = 0x7 << shift;
37463 +
37464 +       ctrl = __raw_readl(reg);
37465 +       ctrl &= ~mask;
37466 +       ctrl |= newvalue << shift;
37467 +       __raw_writel(ctrl, reg);
37468 +
37469 +       /* set the GPIO pin appropriately */
37470 +
37471 +       if (offs < 23)
37472 +               pin = S3C64XX_GPN(offs);
37473 +       else
37474 +               pin = S3C64XX_GPM(offs - 23);
37475 +
37476 +       s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
37477 +
37478 +       return 0;
37479 +}
37480 +
37481 +static struct irq_chip s3c_irq_eint = {
37482 +       .name           = "s3c-eint",
37483 +       .mask           = s3c_irq_eint_mask,
37484 +       .unmask         = s3c_irq_eint_unmask,
37485 +       .mask_ack       = s3c_irq_eint_maskack,
37486 +       .ack            = s3c_irq_eint_ack,
37487 +       .set_type       = s3c_irq_eint_set_type,
37488 +       .set_wake       = s3c_irqext_wake,
37489 +};
37490 +
37491 +/* s3c_irq_demux_eint
37492 + *
37493 + * This function demuxes the IRQ from the group0 external interrupts,
37494 + * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
37495 + * the specific handlers s3c_irq_demux_eintX_Y.
37496 + */
37497 +static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
37498 +{
37499 +       u32 status = __raw_readl(S3C64XX_EINT0PEND);
37500 +       u32 mask = __raw_readl(S3C64XX_EINT0MASK);
37501 +       unsigned int irq;
37502 +
37503 +       status &= ~mask;
37504 +       status >>= start;
37505 +       status &= (1 << (end - start + 1)) - 1;
37506 +
37507 +       for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
37508 +               if (status & 1)
37509 +                       generic_handle_irq(irq);
37510 +
37511 +               status >>= 1;
37512 +       }
37513 +}
37514 +
37515 +static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
37516 +{
37517 +       s3c_irq_demux_eint(0, 3);
37518 +}
37519 +
37520 +static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
37521 +{
37522 +       s3c_irq_demux_eint(4, 11);
37523 +}
37524 +
37525 +static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
37526 +{
37527 +       s3c_irq_demux_eint(12, 19);
37528 +}
37529 +
37530 +static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
37531 +{
37532 +       s3c_irq_demux_eint(20, 27);
37533 +}
37534 +
37535 +int __init s3c64xx_init_irq_eint(void)
37536 +{
37537 +       int irq;
37538 +
37539 +       for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
37540 +               set_irq_chip(irq, &s3c_irq_eint);
37541 +               set_irq_handler(irq, handle_level_irq);
37542 +               set_irq_flags(irq, IRQF_VALID);
37543 +       }
37544 +
37545 +       set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
37546 +       set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
37547 +       set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
37548 +       set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
37549 +
37550 +       return 0;
37551 +}
37552 +
37553 +arch_initcall(s3c64xx_init_irq_eint);
37554 Index: linux-2.6.28/arch/arm/plat-s3c64xx/irq-pm.c
37555 ===================================================================
37556 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37557 +++ linux-2.6.28/arch/arm/plat-s3c64xx/irq-pm.c 2009-01-02 00:01:56.000000000 +0100
37558 @@ -0,0 +1,173 @@
37559 +/* arch/arm/plat-s3c64xx/irq-pm.c
37560 + *
37561 + * Copyright 2008 Openmoko, Inc.
37562 + * Copyright 2008 Simtec Electronics
37563 + *      Ben Dooks <ben@simtec.co.uk>
37564 + *      http://armlinux.simtec.co.uk/
37565 + *
37566 + * S3C64XX - Interrupt handling Power Management
37567 + *
37568 + * This program is free software; you can redistribute it and/or modify
37569 + * it under the terms of the GNU General Public License version 2 as
37570 + * published by the Free Software Foundation.
37571 + */
37572 +
37573 +#include <linux/kernel.h>
37574 +#include <linux/sysdev.h>
37575 +#include <linux/interrupt.h>
37576 +#include <linux/serial_core.h>
37577 +#include <linux/irq.h>
37578 +#include <linux/io.h>
37579 +
37580 +#include <asm/hardware/vic.h>
37581 +
37582 +#include <mach/map.h>
37583 +
37584 +#include <plat/regs-serial.h>
37585 +#include <plat/regs-timer.h>
37586 +#include <plat/regs-gpio.h>
37587 +#include <plat/cpu.h>
37588 +#include <plat/pm.h>
37589 +
37590 +/* We handled all the IRQ types in this code, to save having to make several
37591 + * small files to handle each different type separately. Having the EINT_GRP
37592 + * code here shouldn't be as much bloat as the IRQ table space needed when
37593 + * they are enabled. The added benefit is we ensure that these registers are
37594 + * in the same state as we suspended.
37595 + */
37596 +
37597 +static struct sleep_save irq_save[] = {
37598 +       SAVE_ITEM(S3C64XX_PRIORITY),
37599 +       SAVE_ITEM(S3C64XX_EINT0CON0),
37600 +       SAVE_ITEM(S3C64XX_EINT0CON1),
37601 +       SAVE_ITEM(S3C64XX_EINT0FLTCON0),
37602 +       SAVE_ITEM(S3C64XX_EINT0FLTCON1),
37603 +       SAVE_ITEM(S3C64XX_EINT0FLTCON2),
37604 +       SAVE_ITEM(S3C64XX_EINT0FLTCON3),
37605 +       SAVE_ITEM(S3C64XX_EINT0MASK),
37606 +       SAVE_ITEM(S3C64XX_TINT_CSTAT),
37607 +};
37608 +
37609 +static struct irq_grp_save {
37610 +       u32     fltcon;
37611 +       u32     con;
37612 +       u32     mask;
37613 +} eint_grp_save[5];
37614 +
37615 +struct irq_vic_save {
37616 +       u32     int_select;
37617 +       u32     int_enable;
37618 +       u32     soft_int;
37619 +       u32     protect;
37620 +       u32     vect_addr[32];
37621 +       u32     vect_cntl[32];
37622 +};
37623 +
37624 +static struct irq_vic_save irq_pm_vic0_save;
37625 +static struct irq_vic_save irq_pm_vic1_save;
37626 +
37627 +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
37628 +
37629 +static void s3c64xx_vic_save(void __iomem *base, struct irq_vic_save *save)
37630 +{
37631 +       int v;
37632 +
37633 +       save->int_select = readl(base + VIC_INT_SELECT);
37634 +       save->int_enable = readl(base + VIC_INT_ENABLE);
37635 +       save->soft_int = readl(base + VIC_INT_SOFT);
37636 +       save->protect = readl(base + VIC_PROTECT);
37637 +
37638 +       S3C_PMDBG("%s: select=%08x, enable=%08x, protect=%08x\n", __func__,
37639 +                 save->int_select, save->int_enable, save->protect);
37640 +
37641 +       for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
37642 +               save->vect_addr[v] = readl(base + VIC_VECT_ADDR0 + (v * 4));
37643 +               save->vect_cntl[v] = readl(base + VIC_VECT_CNTL0 + (v * 4));
37644 +       }
37645 +}
37646 +
37647 +static void s3c64xx_vic_restore(void __iomem *base, struct irq_vic_save *save)
37648 +{
37649 +       int v;
37650 +
37651 +       writel(save->int_select, base + VIC_INT_SELECT);
37652 +       writel(save->protect, base + VIC_PROTECT);
37653 +
37654 +       /* set the enabled ints and then clear the non-enabled */
37655 +       writel(save->int_enable, base + VIC_INT_ENABLE);
37656 +       writel(~save->int_enable, base + VIC_INT_ENABLE_CLEAR);
37657 +
37658 +       /* and the same for the soft-int register */
37659 +
37660 +       writel(save->soft_int, base + VIC_INT_SOFT);
37661 +       writel(~save->soft_int, base + VIC_INT_SOFT_CLEAR);
37662 +
37663 +       S3C_PMDBG("%s: vic int_enable=%08x\n", __func__, readl(base + VIC_INT_ENABLE));
37664 +
37665 +       for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
37666 +               writel(save->vect_addr[v], base + VIC_VECT_ADDR0 + (v * 4));
37667 +               writel(save->vect_cntl[v], base + VIC_VECT_CNTL0 + (v * 4));
37668 +       }
37669 +}
37670 +
37671 +static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
37672 +{
37673 +       struct irq_grp_save *grp = eint_grp_save;
37674 +       int i;
37675 +
37676 +       S3C_PMDBG("%s: suspending IRQs\n", __func__);
37677 +
37678 +       s3c64xx_vic_save(S3C_VA_VIC0, &irq_pm_vic0_save);
37679 +       s3c64xx_vic_save(S3C_VA_VIC1, &irq_pm_vic1_save);
37680 +
37681 +       s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
37682 +
37683 +       for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
37684 +               irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
37685 +
37686 +       for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
37687 +               grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
37688 +               grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
37689 +               grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
37690 +       }
37691 +
37692 +       return 0;
37693 +}
37694 +
37695 +static int s3c64xx_irq_pm_resume(struct sys_device *dev)
37696 +{
37697 +       struct irq_grp_save *grp = eint_grp_save;
37698 +       int i;
37699 +
37700 +       S3C_PMDBG("%s: resuming IRQs\n", __func__);
37701 +
37702 +       s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
37703 +
37704 +       s3c64xx_vic_restore(S3C_VA_VIC0, &irq_pm_vic0_save);
37705 +       s3c64xx_vic_restore(S3C_VA_VIC1, &irq_pm_vic1_save);
37706 +
37707 +       for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
37708 +               __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
37709 +
37710 +       for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
37711 +               __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
37712 +               __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
37713 +               __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
37714 +       }
37715 +
37716 +       S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
37717 +       return 0;
37718 +}
37719 +
37720 +static struct sysdev_driver s3c64xx_irq_driver = {
37721 +       .suspend = s3c64xx_irq_pm_suspend,
37722 +       .resume  = s3c64xx_irq_pm_resume,
37723 +};
37724 +
37725 +static int __init s3c64xx_irq_pm_init(void)
37726 +{
37727 +       return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
37728 +}
37729 +
37730 +arch_initcall(s3c64xx_irq_pm_init);
37731 +
37732 Index: linux-2.6.28/arch/arm/plat-s3c64xx/Kconfig
37733 ===================================================================
37734 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37735 +++ linux-2.6.28/arch/arm/plat-s3c64xx/Kconfig  2009-01-02 00:01:56.000000000 +0100
37736 @@ -0,0 +1,61 @@
37737 +# arch/arm/plat-s3c64xx/Kconfig
37738 +#
37739 +# Copyright 2008 Openmoko, Inc.
37740 +# Copyright 2008 Simtec Electronics
37741 +#      Ben Dooks <ben@simtec.co.uk>
37742 +#
37743 +# Licensed under GPLv2
37744 +
37745 +config PLAT_S3C64XX
37746 +       bool
37747 +       depends on ARCH_S3C64XX
37748 +       select PLAT_S3C
37749 +       select ARM_VIC
37750 +       default y
37751 +       select NO_IOPORT
37752 +       select ARCH_REQUIRE_GPIOLIB
37753 +       select S3C_GPIO_TRACK
37754 +       select S3C_GPIO_PULL_UPDOWN
37755 +       select S3C_GPIO_CFG_S3C24XX
37756 +       select S3C_GPIO_CFG_S3C64XX
37757 +       help
37758 +         Base platform code for any Samsung S3C64XX device
37759 +
37760 +if PLAT_S3C64XX
37761 +
37762 +# Configuration options shared by all S3C64XX implementations
37763 +
37764 +config CPU_S3C6400_INIT
37765 +       bool
37766 +       help
37767 +         Common initialisation code for the S3C6400 that is shared
37768 +         by other CPUs in the series, such as the S3C6410.
37769 +
37770 +config CPU_S3C6400_CLOCK
37771 +       bool
37772 +       help
37773 +         Common clock support code for the S3C6400 that is shared
37774 +         by other CPUs in the series, such as the S3C6410.
37775 +
37776 +# platform specific device setup
37777 +
37778 +config S3C64XX_SETUP_I2C0
37779 +       bool
37780 +       default y
37781 +       help
37782 +         Common setup code for i2c bus 0.
37783 +
37784 +         Note, currently since i2c0 is always compiled, this setup helper
37785 +         is always compiled with it.
37786 +
37787 +config S3C64XX_SETUP_I2C1
37788 +       bool
37789 +       help
37790 +         Common setup code for i2c bus 1.
37791 +
37792 +config S3C64XX_SETUP_FB_24BPP
37793 +       bool
37794 +       help
37795 +         Common setup code for S3C64XX with an 24bpp RGB display helper.
37796 +
37797 +endif
37798 Index: linux-2.6.28/arch/arm/plat-s3c64xx/Makefile
37799 ===================================================================
37800 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37801 +++ linux-2.6.28/arch/arm/plat-s3c64xx/Makefile 2009-01-02 00:01:56.000000000 +0100
37802 @@ -0,0 +1,37 @@
37803 +# arch/arm/plat-s3c64xx/Makefile
37804 +#
37805 +# Copyright 2008 Openmoko, Inc.
37806 +# Copyright 2008 Simtec Electronics
37807 +#
37808 +# Licensed under GPLv2
37809 +
37810 +obj-y                          :=
37811 +obj-m                          :=
37812 +obj-n                          := dummy.o
37813 +obj-                           :=
37814 +
37815 +# Core files
37816 +
37817 +obj-y                          += dev-uart.o
37818 +obj-y                          += cpu.o
37819 +obj-y                          += irq.o
37820 +obj-y                          += irq-eint.o
37821 +obj-y                          += clock.o
37822 +obj-y                          += gpiolib.o
37823 +
37824 +# CPU support
37825 +
37826 +obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
37827 +obj-$(CONFIG_CPU_S3C6400_CLOCK)        += s3c6400-clock.o
37828 +
37829 +# PM support
37830 +
37831 +obj-$(CONFIG_PM)               += pm.o
37832 +obj-$(CONFIG_PM)               += sleep.o
37833 +obj-$(CONFIG_PM)               += irq-pm.o
37834 +
37835 +# Device setup
37836 +
37837 +obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
37838 +obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
37839 +obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
37840 Index: linux-2.6.28/arch/arm/plat-s3c64xx/pm.c
37841 ===================================================================
37842 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
37843 +++ linux-2.6.28/arch/arm/plat-s3c64xx/pm.c     2009-01-02 00:01:56.000000000 +0100
37844 @@ -0,0 +1,177 @@
37845 +/* linux/arch/arm/plat-s3c64xx/pm.c
37846 + *
37847 + * Copyright 2008 Openmoko, Inc.
37848 + * Copyright 2008 Simtec Electronics
37849 + *     Ben Dooks <ben@simtec.co.uk>
37850 + *     http://armlinux.simtec.co.uk/
37851 + *
37852 + * S3C64XX CPU PM support.
37853 + *
37854 + * This program is free software; you can redistribute it and/or modify
37855 + * it under the terms of the GNU General Public License version 2 as
37856 + * published by the Free Software Foundation.
37857 +*/
37858 +
37859 +#include <linux/init.h>
37860 +#include <linux/suspend.h>
37861 +#include <linux/serial_core.h>
37862 +#include <linux/io.h>
37863 +
37864 +#include <mach/map.h>
37865 +
37866 +#include <plat/pm.h>
37867 +#include <plat/regs-sys.h>
37868 +#include <plat/regs-gpio.h>
37869 +#include <plat/regs-clock.h>
37870 +#include <plat/regs-modem.h>
37871 +#include <plat/regs-syscon-power.h>
37872 +#include <plat/regs-gpio-memport.h>
37873 +
37874 +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
37875 +#include <plat/gpio-bank-n.h>
37876 +
37877 +void s3c_pm_debug_smdkled(u32 set, u32 clear)
37878 +{
37879 +       unsigned long flags;
37880 +       u32 reg;
37881 +
37882 +       local_irq_save(flags);
37883 +       reg = __raw_readl(S3C64XX_GPNCON);
37884 +       reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
37885 +                S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
37886 +       reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
37887 +              S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
37888 +       __raw_writel(reg, S3C64XX_GPNCON);
37889 +
37890 +       reg = __raw_readl(S3C64XX_GPNDAT);
37891 +       reg &= ~(clear << 12);
37892 +       reg |= set << 12;
37893 +       __raw_writel(reg, S3C64XX_GPNDAT);
37894 +
37895 +       local_irq_restore(flags);
37896 +}
37897 +#endif
37898 +
37899 +static struct sleep_save core_save[] = {
37900 +       SAVE_ITEM(S3C_APLL_LOCK),
37901 +       SAVE_ITEM(S3C_MPLL_LOCK),
37902 +       SAVE_ITEM(S3C_EPLL_LOCK),
37903 +       SAVE_ITEM(S3C_CLK_SRC),
37904 +       SAVE_ITEM(S3C_CLK_DIV0),
37905 +       SAVE_ITEM(S3C_CLK_DIV1),
37906 +       SAVE_ITEM(S3C_CLK_DIV2),
37907 +       SAVE_ITEM(S3C_CLK_OUT),
37908 +       SAVE_ITEM(S3C_HCLK_GATE),
37909 +       SAVE_ITEM(S3C_PCLK_GATE),
37910 +       SAVE_ITEM(S3C_SCLK_GATE),
37911 +       SAVE_ITEM(S3C_MEM0_GATE),
37912 +
37913 +       SAVE_ITEM(S3C_EPLL_CON1),
37914 +       SAVE_ITEM(S3C_EPLL_CON0),
37915 +
37916 +       SAVE_ITEM(S3C64XX_MEM0DRVCON),
37917 +       SAVE_ITEM(S3C64XX_MEM1DRVCON),
37918 +
37919 +#ifndef CONFIG_CPU_FREQ
37920 +       SAVE_ITEM(S3C_APLL_CON),
37921 +       SAVE_ITEM(S3C_MPLL_CON),
37922 +#endif
37923 +};
37924 +
37925 +static struct sleep_save misc_save[] = {
37926 +       SAVE_ITEM(S3C64XX_AHB_CON0),
37927 +       SAVE_ITEM(S3C64XX_AHB_CON1),
37928 +       SAVE_ITEM(S3C64XX_AHB_CON2),
37929 +
37930 +       SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
37931 +       SAVE_ITEM(S3C64XX_SPCON),
37932 +
37933 +       SAVE_ITEM(S3C64XX_MEM0CONSTOP),
37934 +       SAVE_ITEM(S3C64XX_MEM1CONSTOP),
37935 +       SAVE_ITEM(S3C64XX_MEM0CONSLP0),
37936 +       SAVE_ITEM(S3C64XX_MEM0CONSLP1),
37937 +       SAVE_ITEM(S3C64XX_MEM1CONSLP),
37938 +};
37939 +
37940 +void s3c_pm_configure_extint(void)
37941 +{
37942 +       __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
37943 +}
37944 +
37945 +void s3c_pm_restore_core(void)
37946 +{
37947 +       __raw_writel(0, S3C64XX_EINT_MASK);
37948 +
37949 +       s3c_pm_debug_smdkled(1 << 2, 0);
37950 +
37951 +       s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
37952 +       s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
37953 +}
37954 +
37955 +void s3c_pm_save_core(void)
37956 +{
37957 +       s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
37958 +       s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
37959 +}
37960 +
37961 +/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
37962 + * put the per-cpu code in here until any new cpu comes along and changes
37963 + * this.
37964 + */
37965 +
37966 +#include <plat/regs-gpio.h>
37967 +
37968 +static void s3c64xx_cpu_suspend(void)
37969 +{
37970 +       unsigned long tmp;
37971 +
37972 +       /* set our standby method to sleep */
37973 +
37974 +       tmp = __raw_readl(S3C64XX_PWR_CFG);
37975 +       tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
37976 +       tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
37977 +       __raw_writel(tmp, S3C64XX_PWR_CFG);
37978 +
37979 +       /* clear any old wakeup */
37980 +
37981 +       __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
37982 +                    S3C64XX_WAKEUP_STAT);
37983 +
37984 +       /* set the LED state to 0110 over sleep */
37985 +       s3c_pm_debug_smdkled(3 << 1, 0xf);
37986 +
37987 +       /* issue the standby signal into the pm unit. Note, we
37988 +        * issue a write-buffer drain just in case */
37989 +
37990 +       tmp = 0;
37991 +
37992 +       asm("b 1f\n\t"
37993 +           ".align 5\n\t"
37994 +           "1:\n\t"
37995 +           "mcr p15, 0, %0, c7, c10, 5\n\t"
37996 +           "mcr p15, 0, %0, c7, c10, 4\n\t"
37997 +           "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
37998 +
37999 +       /* we should never get past here */
38000 +
38001 +       panic("sleep resumed to originator?");
38002 +}
38003 +
38004 +static void s3c64xx_pm_prepare(void)
38005 +{
38006 +       /* store address of resume. */
38007 +       __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
38008 +
38009 +       /* ensure previous wakeup state is cleared before sleeping */
38010 +       __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
38011 +}
38012 +
38013 +static int s3c64xx_pm_init(void)
38014 +{
38015 +       pm_cpu_prep = s3c64xx_pm_prepare;
38016 +       pm_cpu_sleep = s3c64xx_cpu_suspend;
38017 +       pm_uart_udivslot = 1;
38018 +       return 0;
38019 +}
38020 +
38021 +arch_initcall(s3c64xx_pm_init);
38022 Index: linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-clock.c
38023 ===================================================================
38024 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
38025 +++ linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-clock.c  2009-01-02 00:01:56.000000000 +0100
38026 @@ -0,0 +1,654 @@
38027 +/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
38028 + *
38029 + * Copyright 2008 Openmoko, Inc.
38030 + * Copyright 2008 Simtec Electronics
38031 + *     Ben Dooks <ben@simtec.co.uk>
38032 + *     http://armlinux.simtec.co.uk/
38033 + *
38034 + * S3C6400 based common clock support
38035 + *
38036 + * This program is free software; you can redistribute it and/or modify
38037 + * it under the terms of the GNU General Public License version 2 as
38038 + * published by the Free Software Foundation.
38039 +*/
38040 +
38041 +#include <linux/init.h>
38042 +#include <linux/module.h>
38043 +#include <linux/kernel.h>
38044 +#include <linux/list.h>
38045 +#include <linux/errno.h>
38046 +#include <linux/err.h>
38047 +#include <linux/clk.h>
38048 +#include <linux/sysdev.h>
38049 +#include <linux/io.h>
38050 +
38051 +#include <mach/hardware.h>
38052 +#include <mach/map.h>
38053 +
38054 +#include <plat/cpu-freq.h>
38055 +
38056 +#include <plat/regs-clock.h>
38057 +#include <plat/clock.h>
38058 +#include <plat/cpu.h>
38059 +#include <plat/pll.h>
38060 +
38061 +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
38062 + * ext_xtal_mux for want of an actual name from the manual.
38063 +*/
38064 +
38065 +struct clk clk_ext_xtal_mux = {
38066 +       .name           = "ext_xtal",
38067 +       .id             = -1,
38068 +};
38069 +
38070 +#define clk_fin_apll clk_ext_xtal_mux
38071 +#define clk_fin_mpll clk_ext_xtal_mux
38072 +#define clk_fin_epll clk_ext_xtal_mux
38073 +
38074 +#define clk_fout_mpll  clk_mpll
38075 +
38076 +struct clk_sources {
38077 +       unsigned int    nr_sources;
38078 +       struct clk      **sources;
38079 +};
38080 +
38081 +struct clksrc_clk {
38082 +       struct clk              clk;
38083 +       unsigned int            mask;
38084 +       unsigned int            shift;
38085 +
38086 +       struct clk_sources      *sources;
38087 +
38088 +       unsigned int            divider_shift;
38089 +       void __iomem            *reg_divider;
38090 +};
38091 +
38092 +struct clk clk_fout_apll = {
38093 +       .name           = "fout_apll",
38094 +       .id             = -1,
38095 +};
38096 +
38097 +static struct clk *clk_src_apll_list[] = {
38098 +       [0] = &clk_fin_apll,
38099 +       [1] = &clk_fout_apll,
38100 +};
38101 +
38102 +static struct clk_sources clk_src_apll = {
38103 +       .sources        = clk_src_apll_list,
38104 +       .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
38105 +};
38106 +
38107 +struct clksrc_clk clk_mout_apll = {
38108 +       .clk    = {
38109 +               .name           = "mout_apll",
38110 +               .id             = -1,
38111 +       },
38112 +       .shift          = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
38113 +       .mask           = S3C6400_CLKSRC_APLL_MOUT,
38114 +       .sources        = &clk_src_apll,
38115 +};
38116 +
38117 +struct clk clk_fout_epll = {
38118 +       .name           = "fout_epll",
38119 +       .id             = -1,
38120 +};
38121 +
38122 +static struct clk *clk_src_epll_list[] = {
38123 +       [0] = &clk_fin_epll,
38124 +       [1] = &clk_fout_epll,
38125 +};
38126 +
38127 +static struct clk_sources clk_src_epll = {
38128 +       .sources        = clk_src_epll_list,
38129 +       .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
38130 +};
38131 +
38132 +struct clksrc_clk clk_mout_epll = {
38133 +       .clk    = {
38134 +               .name           = "mout_epll",
38135 +               .id             = -1,
38136 +       },
38137 +       .shift          = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
38138 +       .mask           = S3C6400_CLKSRC_EPLL_MOUT,
38139 +       .sources        = &clk_src_epll,
38140 +};
38141 +
38142 +static struct clk *clk_src_mpll_list[] = {
38143 +       [0] = &clk_fin_mpll,
38144 +       [1] = &clk_fout_mpll,
38145 +};
38146 +
38147 +static struct clk_sources clk_src_mpll = {
38148 +       .sources        = clk_src_mpll_list,
38149 +       .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
38150 +};
38151 +
38152 +struct clksrc_clk clk_mout_mpll = {
38153 +       .clk = {
38154 +               .name           = "mout_mpll",
38155 +               .id             = -1,
38156 +       },
38157 +       .shift          = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
38158 +       .mask           = S3C6400_CLKSRC_MPLL_MOUT,
38159 +       .sources        = &clk_src_mpll,
38160 +};
38161 +
38162 +static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
38163 +{
38164 +       unsigned long rate = clk_get_rate(clk->parent);
38165 +
38166 +       printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
38167 +
38168 +       if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
38169 +               rate /= 2;
38170 +
38171 +       return rate;
38172 +}
38173 +
38174 +struct clk clk_dout_mpll = {
38175 +       .name           = "dout_mpll",
38176 +       .id             = -1,
38177 +       .parent         = &clk_mout_mpll.clk,
38178 +       .get_rate       = s3c64xx_clk_doutmpll_get_rate,
38179 +};
38180 +
38181 +static struct clk *clkset_spi_mmc_list[] = {
38182 +       &clk_mout_epll.clk,
38183 +       &clk_dout_mpll,
38184 +       &clk_fin_epll,
38185 +       &clk_27m,
38186 +};
38187 +
38188 +static struct clk_sources clkset_spi_mmc = {
38189 +       .sources        = clkset_spi_mmc_list,
38190 +       .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
38191 +};
38192 +
38193 +static struct clk *clkset_irda_list[] = {
38194 +       &clk_mout_epll.clk,
38195 +       &clk_dout_mpll,
38196 +       NULL,
38197 +       &clk_27m,
38198 +};
38199 +
38200 +static struct clk_sources clkset_irda = {
38201 +       .sources        = clkset_irda_list,
38202 +       .nr_sources     = ARRAY_SIZE(clkset_irda_list),
38203 +};
38204 +
38205 +static struct clk *clkset_uart_list[] = {
38206 +       &clk_mout_epll.clk,
38207 +       &clk_dout_mpll,
38208 +       NULL,
38209 +       NULL
38210 +};
38211 +
38212 +static struct clk_sources clkset_uart = {
38213 +       .sources        = clkset_uart_list,
38214 +       .nr_sources     = ARRAY_SIZE(clkset_uart_list),
38215 +};
38216 +
38217 +static struct clk *clkset_uhost_list[] = {
38218 +       &clk_mout_epll.clk,
38219 +       &clk_dout_mpll,
38220 +       &clk_fin_epll,
38221 +       &clk_48m,
38222 +};
38223 +
38224 +static struct clk_sources clkset_uhost = {
38225 +       .sources        = clkset_uhost_list,
38226 +       .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
38227 +};
38228 +
38229 +
38230 +/* The peripheral clocks are all controlled via clocksource followed
38231 + * by an optional divider and gate stage. We currently roll this into
38232 + * one clock which hides the intermediate clock from the mux.
38233 + *
38234 + * Note, the JPEG clock can only be an even divider...
38235 + *
38236 + * The scaler and LCD clocks depend on the S3C64XX version, and also
38237 + * have a common parent divisor so are not included here.
38238 + */
38239 +
38240 +static inline struct clksrc_clk *to_clksrc(struct clk *clk)
38241 +{
38242 +       return container_of(clk, struct clksrc_clk, clk);
38243 +}
38244 +
38245 +static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
38246 +{
38247 +       struct clksrc_clk *sclk = to_clksrc(clk);
38248 +       unsigned long rate = clk_get_rate(clk->parent);
38249 +       u32 clkdiv = __raw_readl(sclk->reg_divider);
38250 +
38251 +       clkdiv >>= sclk->divider_shift;
38252 +       clkdiv &= 0xf;
38253 +       clkdiv++;
38254 +
38255 +       rate /= clkdiv;
38256 +       return rate;
38257 +}
38258 +
38259 +static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
38260 +{
38261 +       struct clksrc_clk *sclk = to_clksrc(clk);
38262 +       void __iomem *reg = sclk->reg_divider;
38263 +       unsigned int div;
38264 +       u32 val;
38265 +
38266 +       rate = clk_round_rate(clk, rate);
38267 +       div = clk_get_rate(clk->parent) / rate;
38268 +
38269 +       val = __raw_readl(reg);
38270 +       val &= ~sclk->mask;
38271 +       val |= (rate - 1) << sclk->shift;
38272 +       __raw_writel(val, reg);
38273 +
38274 +       return 0;
38275 +}
38276 +
38277 +static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
38278 +{
38279 +       struct clksrc_clk *sclk = to_clksrc(clk);
38280 +       struct clk_sources *srcs = sclk->sources;
38281 +       u32 clksrc = __raw_readl(S3C_CLK_SRC);
38282 +       int src_nr = -1;
38283 +       int ptr;
38284 +
38285 +       for (ptr = 0; ptr < srcs->nr_sources; ptr++)
38286 +               if (srcs->sources[ptr] == parent) {
38287 +                       src_nr = ptr;
38288 +                       break;
38289 +               }
38290 +
38291 +       if (src_nr >= 0) {
38292 +               clksrc &= ~sclk->mask;
38293 +               clksrc |= src_nr << sclk->shift;
38294 +
38295 +               __raw_writel(clksrc, S3C_CLK_SRC);
38296 +               return 0;
38297 +       }
38298 +
38299 +       return -EINVAL;
38300 +}
38301 +
38302 +static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
38303 +                                             unsigned long rate)
38304 +{
38305 +       unsigned long parent_rate = clk_get_rate(clk->parent);
38306 +       int div;
38307 +
38308 +       if (rate > parent_rate)
38309 +               rate = parent_rate;
38310 +       else {
38311 +               div = rate / parent_rate;
38312 +
38313 +               if (div == 0)
38314 +                       div = 1;
38315 +               if (div > 16)
38316 +                       div = 16;
38317 +
38318 +               rate = parent_rate / div;
38319 +       }
38320 +
38321 +       return rate;
38322 +}
38323 +
38324 +static struct clksrc_clk clk_mmc0 = {
38325 +       .clk    = {
38326 +               .name           = "mmc_bus",
38327 +               .id             = 0,
38328 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
38329 +               .enable         = s3c64xx_sclk_ctrl,
38330 +               .set_parent     = s3c64xx_setparent_clksrc,
38331 +               .get_rate       = s3c64xx_getrate_clksrc,
38332 +               .set_rate       = s3c64xx_setrate_clksrc,
38333 +               .round_rate     = s3c64xx_roundrate_clksrc,
38334 +       },
38335 +       .shift          = S3C6400_CLKSRC_MMC0_SHIFT,
38336 +       .mask           = S3C6400_CLKSRC_MMC0_MASK,
38337 +       .sources        = &clkset_spi_mmc,
38338 +       .divider_shift  = S3C6400_CLKDIV1_MMC0_SHIFT,
38339 +       .reg_divider    = S3C_CLK_DIV1,
38340 +};
38341 +
38342 +static struct clksrc_clk clk_mmc1 = {
38343 +       .clk    = {
38344 +               .name           = "mmc_bus",
38345 +               .id             = 1,
38346 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
38347 +               .enable         = s3c64xx_sclk_ctrl,
38348 +               .get_rate       = s3c64xx_getrate_clksrc,
38349 +               .set_rate       = s3c64xx_setrate_clksrc,
38350 +               .set_parent     = s3c64xx_setparent_clksrc,
38351 +               .round_rate     = s3c64xx_roundrate_clksrc,
38352 +       },
38353 +       .shift          = S3C6400_CLKSRC_MMC1_SHIFT,
38354 +       .mask           = S3C6400_CLKSRC_MMC1_MASK,
38355 +       .sources        = &clkset_spi_mmc,
38356 +       .divider_shift  = S3C6400_CLKDIV1_MMC1_SHIFT,
38357 +       .reg_divider    = S3C_CLK_DIV1,
38358 +};
38359 +
38360 +static struct clksrc_clk clk_mmc2 = {
38361 +       .clk    = {
38362 +               .name           = "mmc_bus",
38363 +               .id             = 2,
38364 +               .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
38365 +               .enable         = s3c64xx_sclk_ctrl,
38366 +               .get_rate       = s3c64xx_getrate_clksrc,
38367 +               .set_rate       = s3c64xx_setrate_clksrc,
38368 +               .set_parent     = s3c64xx_setparent_clksrc,
38369 +               .round_rate     = s3c64xx_roundrate_clksrc,
38370 +       },
38371 +       .shift          = S3C6400_CLKSRC_MMC2_SHIFT,
38372 +       .mask           = S3C6400_CLKSRC_MMC2_MASK,
38373 +       .sources        = &clkset_spi_mmc,
38374 +       .divider_shift  = S3C6400_CLKDIV1_MMC2_SHIFT,
38375 +       .reg_divider    = S3C_CLK_DIV1,
38376 +};
38377 +
38378 +static struct clksrc_clk clk_usbhost = {
38379 +       .clk    = {
38380 +               .name           = "usb-host-bus",
38381 +               .id             = -1,
38382 +               .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
38383 +               .enable         = s3c64xx_sclk_ctrl,
38384 +               .set_parent     = s3c64xx_setparent_clksrc,
38385 +               .get_rate       = s3c64xx_getrate_clksrc,
38386 +               .set_rate       = s3c64xx_setrate_clksrc,
38387 +               .round_rate     = s3c64xx_roundrate_clksrc,
38388 +       },
38389 +       .shift          = S3C6400_CLKSRC_UHOST_SHIFT,
38390 +       .mask           = S3C6400_CLKSRC_UHOST_MASK,
38391 +       .sources        = &clkset_uhost,
38392 +       .divider_shift  = S3C6400_CLKDIV1_UHOST_SHIFT,
38393 +       .reg_divider    = S3C_CLK_DIV1,
38394 +};
38395 +
38396 +static struct clksrc_clk clk_uart_uclk1 = {
38397 +       .clk    = {
38398 +               .name           = "uclk1",
38399 +               .id             = -1,
38400 +               .ctrlbit        = S3C_CLKCON_SCLK_UART,
38401 +               .enable         = s3c64xx_sclk_ctrl,
38402 +               .set_parent     = s3c64xx_setparent_clksrc,
38403 +               .get_rate       = s3c64xx_getrate_clksrc,
38404 +               .set_rate       = s3c64xx_setrate_clksrc,
38405 +               .round_rate     = s3c64xx_roundrate_clksrc,
38406 +       },
38407 +       .shift          = S3C6400_CLKSRC_UART_SHIFT,
38408 +       .mask           = S3C6400_CLKSRC_UART_MASK,
38409 +       .sources        = &clkset_uart,
38410 +       .divider_shift  = S3C6400_CLKDIV2_UART_SHIFT,
38411 +       .reg_divider    = S3C_CLK_DIV2,
38412 +};
38413 +
38414 +/* Where does UCLK0 come from? */
38415 +
38416 +static struct clksrc_clk clk_spi0 = {
38417 +       .clk    = {
38418 +               .name           = "spi-bus",
38419 +               .id             = 0,
38420 +               .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
38421 +               .enable         = s3c64xx_sclk_ctrl,
38422 +               .set_parent     = s3c64xx_setparent_clksrc,
38423 +               .get_rate       = s3c64xx_getrate_clksrc,
38424 +               .set_rate       = s3c64xx_setrate_clksrc,
38425 +               .round_rate     = s3c64xx_roundrate_clksrc,
38426 +       },
38427 +       .shift          = S3C6400_CLKSRC_SPI0_SHIFT,
38428 +       .mask           = S3C6400_CLKSRC_SPI0_MASK,
38429 +       .sources        = &clkset_spi_mmc,
38430 +       .divider_shift  = S3C6400_CLKDIV2_SPI0_SHIFT,
38431 +       .reg_divider    = S3C_CLK_DIV2,
38432 +};
38433 +
38434 +static struct clksrc_clk clk_spi1 = {
38435 +       .clk    = {
38436 +               .name           = "spi-bus",
38437 +               .id             = 1,
38438 +               .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
38439 +               .enable         = s3c64xx_sclk_ctrl,
38440 +               .set_parent     = s3c64xx_setparent_clksrc,
38441 +               .get_rate       = s3c64xx_getrate_clksrc,
38442 +               .set_rate       = s3c64xx_setrate_clksrc,
38443 +               .round_rate     = s3c64xx_roundrate_clksrc,
38444 +       },
38445 +       .shift          = S3C6400_CLKSRC_SPI1_SHIFT,
38446 +       .mask           = S3C6400_CLKSRC_SPI1_MASK,
38447 +       .sources        = &clkset_spi_mmc,
38448 +       .divider_shift  = S3C6400_CLKDIV2_SPI1_SHIFT,
38449 +       .reg_divider    = S3C_CLK_DIV2,
38450 +};
38451 +
38452 +static struct clk clk_iis_cd0 = {
38453 +       .name           = "iis_cdclk0",
38454 +       .id             = -1,
38455 +};
38456 +
38457 +static struct clk clk_iis_cd1 = {
38458 +       .name           = "iis_cdclk1",
38459 +       .id             = -1,
38460 +};
38461 +
38462 +static struct clk clk_pcm_cd = {
38463 +       .name           = "pcm_cdclk",
38464 +       .id             = -1,
38465 +};
38466 +
38467 +static struct clk *clkset_audio0_list[] = {
38468 +       [0] = &clk_mout_epll.clk,
38469 +       [1] = &clk_dout_mpll,
38470 +       [2] = &clk_fin_epll,
38471 +       [3] = &clk_iis_cd0,
38472 +       [4] = &clk_pcm_cd,
38473 +};
38474 +
38475 +static struct clk_sources clkset_audio0 = {
38476 +       .sources        = clkset_audio0_list,
38477 +       .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
38478 +};
38479 +
38480 +static struct clksrc_clk clk_audio0 = {
38481 +       .clk    = {
38482 +               .name           = "audio-bus",
38483 +               .id             = 0,
38484 +               .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
38485 +               .enable         = s3c64xx_sclk_ctrl,
38486 +               .set_parent     = s3c64xx_setparent_clksrc,
38487 +               .get_rate       = s3c64xx_getrate_clksrc,
38488 +               .set_rate       = s3c64xx_setrate_clksrc,
38489 +               .round_rate     = s3c64xx_roundrate_clksrc,
38490 +       },
38491 +       .shift          = S3C6400_CLKSRC_AUDIO0_SHIFT,
38492 +       .mask           = S3C6400_CLKSRC_AUDIO0_MASK,
38493 +       .sources        = &clkset_audio0,
38494 +       .divider_shift  = S3C6400_CLKDIV2_AUDIO0_SHIFT,
38495 +       .reg_divider    = S3C_CLK_DIV2,
38496 +};
38497 +
38498 +static struct clk *clkset_audio1_list[] = {
38499 +       [0] = &clk_mout_epll.clk,
38500 +       [1] = &clk_dout_mpll,
38501 +       [2] = &clk_fin_epll,
38502 +       [3] = &clk_iis_cd1,
38503 +       [4] = &clk_pcm_cd,
38504 +};
38505 +
38506 +static struct clk_sources clkset_audio1 = {
38507 +       .sources        = clkset_audio1_list,
38508 +       .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
38509 +};
38510 +
38511 +static struct clksrc_clk clk_audio1 = {
38512 +       .clk    = {
38513 +               .name           = "audio-bus",
38514 +               .id             = 1,
38515 +               .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
38516 +               .enable         = s3c64xx_sclk_ctrl,
38517 +               .set_parent     = s3c64xx_setparent_clksrc,
38518 +               .get_rate       = s3c64xx_getrate_clksrc,
38519 +               .set_rate       = s3c64xx_setrate_clksrc,
38520 +               .round_rate     = s3c64xx_roundrate_clksrc,
38521 +       },
38522 +       .shift          = S3C6400_CLKSRC_AUDIO1_SHIFT,
38523 +       .mask           = S3C6400_CLKSRC_AUDIO1_MASK,
38524 +       .sources        = &clkset_audio1,
38525 +       .divider_shift  = S3C6400_CLKDIV2_AUDIO1_SHIFT,
38526 +       .reg_divider    = S3C_CLK_DIV2,
38527 +};
38528 +
38529 +static struct clksrc_clk clk_irda = {
38530 +       .clk    = {
38531 +               .name           = "irda-bus",
38532 +               .id             = 0,
38533 +               .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
38534 +               .enable         = s3c64xx_sclk_ctrl,
38535 +               .set_parent     = s3c64xx_setparent_clksrc,
38536 +               .get_rate       = s3c64xx_getrate_clksrc,
38537 +               .set_rate       = s3c64xx_setrate_clksrc,
38538 +               .round_rate     = s3c64xx_roundrate_clksrc,
38539 +       },
38540 +       .shift          = S3C6400_CLKSRC_IRDA_SHIFT,
38541 +       .mask           = S3C6400_CLKSRC_IRDA_MASK,
38542 +       .sources        = &clkset_irda,
38543 +       .divider_shift  = S3C6400_CLKDIV2_IRDA_SHIFT,
38544 +       .reg_divider    = S3C_CLK_DIV2,
38545 +};
38546 +
38547 +/* Clock initialisation code */
38548 +
38549 +static struct clksrc_clk *init_parents[] = {
38550 +       &clk_mout_apll,
38551 +       &clk_mout_epll,
38552 +       &clk_mout_mpll,
38553 +       &clk_mmc0,
38554 +       &clk_mmc1,
38555 +       &clk_mmc2,
38556 +       &clk_usbhost,
38557 +       &clk_uart_uclk1,
38558 +       &clk_spi0,
38559 +       &clk_spi1,
38560 +       &clk_audio0,
38561 +       &clk_audio1,
38562 +       &clk_irda,
38563 +};
38564 +
38565 +static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
38566 +{
38567 +       struct clk_sources *srcs = clk->sources;
38568 +       u32 clksrc = __raw_readl(S3C_CLK_SRC);
38569 +
38570 +       clksrc &= clk->mask;
38571 +       clksrc >>= clk->shift;
38572 +
38573 +       if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
38574 +               printk(KERN_ERR "%s: bad source %d\n",
38575 +                      clk->clk.name, clksrc);
38576 +               return;
38577 +       }
38578 +
38579 +       clk->clk.parent = srcs->sources[clksrc];
38580 +
38581 +       printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
38582 +              clk->clk.name, clk->clk.parent->name, clksrc,
38583 +              clk_get_rate(&clk->clk));
38584 +}
38585 +
38586 +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
38587 +
38588 +void __init_or_cpufreq s3c6400_setup_clocks(void)
38589 +{
38590 +       struct clk *xtal_clk;
38591 +       unsigned long xtal;
38592 +       unsigned long fclk;
38593 +       unsigned long hclk;
38594 +       unsigned long hclk2;
38595 +       unsigned long pclk;
38596 +       unsigned long epll;
38597 +       unsigned long apll;
38598 +       unsigned long mpll;
38599 +       unsigned int ptr;
38600 +       u32 clkdiv0;
38601 +
38602 +       printk(KERN_DEBUG "%s: registering clocks\n", __func__);
38603 +
38604 +       clkdiv0 = __raw_readl(S3C_CLK_DIV0);
38605 +       printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
38606 +
38607 +       xtal_clk = clk_get(NULL, "xtal");
38608 +       BUG_ON(IS_ERR(xtal_clk));
38609 +
38610 +       xtal = clk_get_rate(xtal_clk);
38611 +       clk_put(xtal_clk);
38612 +
38613 +       printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
38614 +
38615 +       epll = s3c6400_get_epll(xtal);
38616 +       mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
38617 +       apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
38618 +
38619 +       fclk = mpll;
38620 +
38621 +       printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
38622 +              apll, mpll, epll);
38623 +
38624 +       hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
38625 +       hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
38626 +       pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
38627 +
38628 +       printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
38629 +              hclk2, hclk, pclk);
38630 +
38631 +       clk_fout_mpll.rate = mpll;
38632 +       clk_fout_epll.rate = epll;
38633 +       clk_fout_apll.rate = apll;
38634 +
38635 +       clk_h.rate = hclk;
38636 +       clk_p.rate = pclk;
38637 +       clk_f.rate = fclk;
38638 +
38639 +       for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
38640 +               s3c6400_set_clksrc(init_parents[ptr]);
38641 +}
38642 +
38643 +static struct clk *clks[] __initdata = {
38644 +       &clk_ext_xtal_mux,
38645 +       &clk_iis_cd0,
38646 +       &clk_iis_cd1,
38647 +       &clk_pcm_cd,
38648 +       &clk_mout_epll.clk,
38649 +       &clk_fout_epll,
38650 +       &clk_mout_mpll.clk,
38651 +       &clk_dout_mpll,
38652 +       &clk_mmc0.clk,
38653 +       &clk_mmc1.clk,
38654 +       &clk_mmc2.clk,
38655 +       &clk_usbhost.clk,
38656 +       &clk_uart_uclk1.clk,
38657 +       &clk_spi0.clk,
38658 +       &clk_spi1.clk,
38659 +       &clk_audio0.clk,
38660 +       &clk_audio1.clk,
38661 +       &clk_irda.clk,
38662 +};
38663 +
38664 +void __init s3c6400_register_clocks(void)
38665 +{
38666 +       struct clk *clkp;
38667 +       int ret;
38668 +       int ptr;
38669 +
38670 +       for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
38671 +               clkp = clks[ptr];
38672 +               ret = s3c24xx_register_clock(clkp);
38673 +               if (ret < 0) {
38674 +                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
38675 +                              clkp->name, ret);
38676 +               }
38677 +       }
38678 +
38679 +       clk_epll.parent = &clk_mout_epll.clk;
38680 +}
38681 Index: linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-init.c
38682 ===================================================================
38683 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
38684 +++ linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-init.c   2009-01-02 00:01:56.000000000 +0100
38685 @@ -0,0 +1,29 @@
38686 +/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c
38687 + *
38688 + * Copyright 2008 Openmoko, Inc.
38689 + * Copyright 2008 Simtec Electronics
38690 + *      Ben Dooks <ben@simtec.co.uk>
38691 + *      http://armlinux.simtec.co.uk/
38692 + *
38693 + * S3C6400 - CPU initialisation (common with other S3C64XX chips)
38694 + *
38695 + * This program is free software; you can redistribute it and/or modify
38696 + * it under the terms of the GNU General Public License version 2 as
38697 + * published by the Free Software Foundation.
38698 + */
38699 +
38700 +#include <linux/kernel.h>
38701 +#include <linux/types.h>
38702 +#include <linux/init.h>
38703 +
38704 +#include <plat/cpu.h>
38705 +#include <plat/devs.h>
38706 +#include <plat/s3c6400.h>
38707 +#include <plat/s3c6410.h>
38708 +
38709 +/* uart registration process */
38710 +
38711 +void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
38712 +{
38713 +       s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
38714 +}
38715 Index: linux-2.6.28/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
38716 ===================================================================
38717 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
38718 +++ linux-2.6.28/arch/arm/plat-s3c64xx/setup-fb-24bpp.c 2009-01-02 00:01:56.000000000 +0100
38719 @@ -0,0 +1,37 @@
38720 +/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
38721 + *
38722 + * Copyright 2008 Openmoko, Inc.
38723 + * Copyright 2008 Simtec Electronics
38724 + *     Ben Dooks <ben@simtec.co.uk>
38725 + *     http://armlinux.simtec.co.uk/
38726 + *
38727 + * Base S3C64XX setup information for 24bpp LCD framebuffer
38728 + *
38729 + * This program is free software; you can redistribute it and/or modify
38730 + * it under the terms of the GNU General Public License version 2 as
38731 + * published by the Free Software Foundation.
38732 +*/
38733 +
38734 +#include <linux/kernel.h>
38735 +#include <linux/types.h>
38736 +#include <linux/fb.h>
38737 +
38738 +#include <mach/regs-fb.h>
38739 +#include <mach/gpio.h>
38740 +#include <plat/fb.h>
38741 +#include <plat/gpio-cfg.h>
38742 +
38743 +extern void s3c64xx_fb_gpio_setup_24bpp(void)
38744 +{
38745 +       unsigned int gpio;
38746 +
38747 +       for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
38748 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
38749 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
38750 +       }
38751 +
38752 +       for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
38753 +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
38754 +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
38755 +       }
38756 +}
38757 Index: linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c0.c
38758 ===================================================================
38759 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
38760 +++ linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c0.c     2009-01-02 00:01:56.000000000 +0100
38761 @@ -0,0 +1,31 @@
38762 +/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c
38763 + *
38764 + * Copyright 2008 Openmoko, Inc.
38765 + * Copyright 2008 Simtec Electronics
38766 + *     Ben Dooks <ben@simtec.co.uk>
38767 + *     http://armlinux.simtec.co.uk/
38768 + *
38769 + * Base S3C64XX I2C bus 0 gpio configuration
38770 + *
38771 + * This program is free software; you can redistribute it and/or modify
38772 + * it under the terms of the GNU General Public License version 2 as
38773 + * published by the Free Software Foundation.
38774 +*/
38775 +
38776 +#include <linux/kernel.h>
38777 +#include <linux/types.h>
38778 +
38779 +struct platform_device; /* don't need the contents */
38780 +
38781 +#include <mach/gpio.h>
38782 +#include <plat/iic.h>
38783 +#include <plat/gpio-bank-b.h>
38784 +#include <plat/gpio-cfg.h>
38785 +
38786 +void s3c_i2c0_cfg_gpio(struct platform_device *dev)
38787 +{
38788 +       s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
38789 +       s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
38790 +       s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
38791 +       s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
38792 +}
38793 Index: linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c1.c
38794 ===================================================================
38795 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
38796 +++ linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c1.c     2009-01-02 00:01:56.000000000 +0100
38797 @@ -0,0 +1,31 @@
38798 +/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
38799 + *
38800 + * Copyright 2008 Openmoko, Inc.
38801 + * Copyright 2008 Simtec Electronics
38802 + *     Ben Dooks <ben@simtec.co.uk>
38803 + *     http://armlinux.simtec.co.uk/
38804 + *
38805 + * Base S3C64XX I2C bus 1 gpio configuration
38806 + *
38807 + * This program is free software; you can redistribute it and/or modify
38808 + * it under the terms of the GNU General Public License version 2 as
38809 + * published by the Free Software Foundation.
38810 +*/
38811 +
38812 +#include <linux/kernel.h>
38813 +#include <linux/types.h>
38814 +
38815 +struct platform_device; /* don't need the contents */
38816 +
38817 +#include <mach/gpio.h>
38818 +#include <plat/iic.h>
38819 +#include <plat/gpio-bank-b.h>
38820 +#include <plat/gpio-cfg.h>
38821 +
38822 +void s3c_i2c1_cfg_gpio(struct platform_device *dev)
38823 +{
38824 +       s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
38825 +       s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
38826 +       s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
38827 +       s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
38828 +}
38829 Index: linux-2.6.28/arch/arm/plat-s3c64xx/sleep.S
38830 ===================================================================
38831 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
38832 +++ linux-2.6.28/arch/arm/plat-s3c64xx/sleep.S  2009-01-02 00:01:56.000000000 +0100
38833 @@ -0,0 +1,143 @@
38834 +/* linux/0arch/arm/plat-s3c64xx/sleep.S
38835 + *
38836 + * Copyright 2008 Openmoko, Inc.
38837 + * Copyright 2008 Simtec Electronics
38838 + *     Ben Dooks <ben@simtec.co.uk>
38839 + *     http://armlinux.simtec.co.uk/
38840 + *
38841 + * S3C64XX CPU sleep code
38842 + *
38843 + * This program is free software; you can redistribute it and/or modify
38844 + * it under the terms of the GNU General Public License version 2 as
38845 + * published by the Free Software Foundation.
38846 +*/
38847 +
38848 +#include <linux/linkage.h>
38849 +#include <asm/assembler.h>
38850 +#include <mach/map.h>
38851 +
38852 +#undef S3C64XX_VA_GPIO
38853 +#define S3C64XX_VA_GPIO (0x0)
38854 +
38855 +#include <plat/regs-gpio.h>
38856 +#include <plat/gpio-bank-n.h>
38857 +
38858 +#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
38859 +
38860 +       .text
38861 +
38862 +       /* s3c_cpu_save
38863 +        *
38864 +        * Save enough processor state to allow the restart of the pm.c
38865 +        * code after resume.
38866 +        *
38867 +        * entry:
38868 +        *      r0 = pointer to the save block
38869 +        * exit:
38870 +        *      r0 = exit code: 1 => stored data
38871 +        *                      0 => resumed from sleep
38872 +       */
38873 +
38874 +ENTRY(s3c_cpu_save)
38875 +       stmfd   sp!, { r4 - r12, lr }
38876 +
38877 +       mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
38878 +       mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
38879 +       mrc     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
38880 +       mrc     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
38881 +       mrc     p15, 0, r8, c2, c0, 2   @ Translation Table Control
38882 +       mrc     p15, 0, r9, c1, c0, 0   @ Control register
38883 +       mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
38884 +       mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
38885 +
38886 +       stmia   r0, { r4 - r13 }        @ Save CP registers and SP
38887 +       mov     r0, #0
38888 +       ldmfd   sp, { r4 - r12, pc }    @ return, not disturbing SP
38889 +
38890 +       @@ return to the caller, after the MMU is turned on.
38891 +       @@ restore the last bits of the stack and return.
38892 +resume_with_mmu:
38893 +       mov     r0, #1
38894 +       ldmfd   sp!, { r4 - r12, pc }   @ return, from sp from s3c_cpu_save
38895 +
38896 +       .data
38897 +
38898 +       /* the next bit is code, but it requires easy access to the
38899 +        * s3c_sleep_save_phys data before the MMU is switched on, so
38900 +        * we store the code that needs this variable in the .data where
38901 +        * the value can be written to (the .text segment is RO).
38902 +       */
38903 +
38904 +       .global s3c_sleep_save_phys
38905 +s3c_sleep_save_phys:
38906 +       .word   0
38907 +
38908 +       /* Sleep magic, the word before the resume entry point so that the
38909 +        * bootloader can check for a resumeable image. */
38910 +
38911 +       .word   0x2bedf00d
38912 +
38913 +       /* s3c_cpu_reusme
38914 +        *
38915 +        * This is the entry point, stored by whatever method the bootloader
38916 +        * requires to get the kernel runnign again. This code expects to be
38917 +        * entered with no caches live and the MMU disabled. It will then
38918 +        * restore the MMU and other basic CP registers saved and restart
38919 +        * the kernel C code to finish the resume code.
38920 +       */
38921 +
38922 +ENTRY(s3c_cpu_resume)
38923 +       msr     cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
38924 +       ldr     r2, =LL_UART            /* for debug */
38925 +
38926 +#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
38927 +       /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
38928 +        * as the uboot version supplied resets these to inputs during the
38929 +        * resume checks.
38930 +       */
38931 +
38932 +       ldr     r3, =S3C64XX_PA_GPIO
38933 +       ldr     r0, [ r3, #S3C64XX_GPNCON ]
38934 +       bic     r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
38935 +                         S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
38936 +       orr     r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
38937 +                         S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
38938 +       str     r0, [ r3, #S3C64XX_GPNCON ]
38939 +
38940 +       ldr     r0, [ r3, #S3C64XX_GPNDAT ]
38941 +       bic     r0, r0, #0xf << 12                      @ GPN12..15
38942 +       orr     r0, r0, #1 << 15                        @ GPN15
38943 +       str     r0, [ r3, #S3C64XX_GPNDAT ]
38944 +#endif
38945 +
38946 +       /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
38947 +        * are thoroughly cleaned just in case the bootloader didn't do it
38948 +        * for us. */
38949 +       mov     r0, #0
38950 +       mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
38951 +       mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
38952 +       mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
38953 +       mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
38954 +       @@mcr   p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
38955 +       @@mcr   p15, 0, r0, c7, c7, 0           @ Invalidate I + D caches
38956 +
38957 +       ldr     r0, s3c_sleep_save_phys
38958 +       ldmia   r0, { r4 - r13 }
38959 +
38960 +       mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
38961 +       mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
38962 +       mcr     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
38963 +       mcr     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
38964 +       mcr     p15, 0, r8, c2, c0, 2   @ Translation Table Control
38965 +       mcr     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
38966 +
38967 +       mov     r0, #0                  @ restore copro access controls
38968 +       mcr     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
38969 +       mcr     p15, 0, r0, c7, c5, 4
38970 +
38971 +       ldr     r2, =resume_with_mmu
38972 +       mcr     p15, 0, r9, c1, c0, 0           /* turn mmu back on */
38973 +       nop
38974 +       mov     pc, r2                          /* jump back */
38975 +
38976 +       .end
38977 Index: linux-2.6.28/dfu-kern
38978 ===================================================================
38979 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
38980 +++ linux-2.6.28/dfu-kern       2009-01-02 00:01:56.000000000 +0100
38981 @@ -0,0 +1,14 @@
38982 +#!/bin/bash
38983 +
38984 +if [ -z "$1" ] ; then
38985 +       echo "Usage: $0 <DEVICE>    eg, $0 GTA02"
38986 +       exit 1
38987 +fi
38988 +
38989 +../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5119 -D uImage-$1.bin
38990 +if [ $? -eq 1 ] ; then
38991 +../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5120 -D uImage-$1.bin
38992 +../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5119 -D uImage-$1.bin
38993 +fi
38994 +
38995 +
38996 Index: linux-2.6.28/Documentation/arm/Samsung-S3C24XX/Suspend.txt
38997 ===================================================================
38998 --- linux-2.6.28.orig/Documentation/arm/Samsung-S3C24XX/Suspend.txt     2008-12-25 00:26:37.000000000 +0100
38999 +++ linux-2.6.28/Documentation/arm/Samsung-S3C24XX/Suspend.txt  2009-01-02 00:01:56.000000000 +0100
39000 @@ -40,13 +40,13 @@ Resuming
39001  Machine Support
39002  ---------------
39003
39004 -  The machine specific functions must call the s3c2410_pm_init() function
39005 +  The machine specific functions must call the s3c_pm_init() function
39006    to say that its bootloader is capable of resuming. This can be as
39007    simple as adding the following to the machine's definition:
39008
39009 -  INITMACHINE(s3c2410_pm_init)
39010 +  INITMACHINE(s3c_pm_init)
39011
39012 -  A board can do its own setup before calling s3c2410_pm_init, if it
39013 +  A board can do its own setup before calling s3c_pm_init, if it
39014    needs to setup anything else for power management support.
39015
39016    There is currently no support for over-riding the default method of
39017 @@ -74,7 +74,7 @@ statuc void __init machine_init(void)
39018
39019         enable_irq_wake(IRQ_EINT0);
39020
39021 -       s3c2410_pm_init();
39022 +       s3c_pm_init();
39023  }
39024
39025
39026 Index: linux-2.6.28/drivers/android/alarm.c
39027 ===================================================================
39028 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
39029 +++ linux-2.6.28/drivers/android/alarm.c        2009-01-02 00:01:56.000000000 +0100
39030 @@ -0,0 +1,542 @@
39031 +/* drivers/android/alarm.c
39032 + *
39033 + * Copyright (C) 2007 Google, Inc.
39034 + *
39035 + * This software is licensed under the terms of the GNU General Public
39036 + * License version 2, as published by the Free Software Foundation, and
39037 + * may be copied, distributed, and modified under those terms.
39038 + *
39039 + * This program is distributed in the hope that it will be useful,
39040 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
39041 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
39042 + * GNU General Public License for more details.
39043 + *
39044 + */
39045 +
39046 +#include <asm/mach/time.h>
39047 +#include <linux/android_alarm.h>
39048 +#include <linux/android_power.h>
39049 +#include <linux/device.h>
39050 +#include <linux/miscdevice.h>
39051 +#include <linux/platform_device.h>
39052 +#include <linux/rtc.h>
39053 +#include <linux/spinlock.h>
39054 +#include <linux/sysdev.h>
39055 +
39056 +#define ANDROID_ALARM_PRINT_ERRORS (1U << 0)
39057 +#define ANDROID_ALARM_PRINT_INIT_STATUS (1U << 1)
39058 +#define ANDROID_ALARM_PRINT_INFO (1U << 2)
39059 +#define ANDROID_ALARM_PRINT_IO (1U << 3)
39060 +#define ANDROID_ALARM_PRINT_INT (1U << 4)
39061 +#define ANDROID_ALARM_PRINT_FLOW (1U << 5)
39062 +
39063 +#if 0
39064 +#define ANDROID_ALARM_DPRINTF_MASK (~0)
39065 +#define ANDROID_ALARM_DPRINTF(debug_level_mask, args...) \
39066 +       do { \
39067 +               if(ANDROID_ALARM_DPRINTF_MASK & debug_level_mask) { \
39068 +                       printk(args); \
39069 +               } \
39070 +       } while(0)
39071 +#else
39072 +#define ANDROID_ALARM_DPRINTF(args...)
39073 +#endif
39074 +
39075 +// support old usespace code
39076 +#define ANDROID_ALARM_SET_OLD               _IOW('a', 2, time_t) // set alarm
39077 +#define ANDROID_ALARM_SET_AND_WAIT_OLD      _IOW('a', 3, time_t)
39078 +
39079 +static struct rtc_device *alarm_rtc_dev;
39080 +static int alarm_opened;
39081 +static DEFINE_SPINLOCK(alarm_slock);
39082 +static DEFINE_MUTEX(alarm_setrtc_mutex);
39083 +static android_suspend_lock_t alarm_suspend_lock = {
39084 +       .name = "android_alarm"
39085 +};
39086 +static android_suspend_lock_t alarm_rtc_suspend_lock = {
39087 +       .name = "android_alarm_rtc"
39088 +};
39089 +static DECLARE_WAIT_QUEUE_HEAD(alarm_wait_queue);
39090 +static uint32_t alarm_pending;
39091 +static uint32_t alarm_enabled;
39092 +static uint32_t wait_pending;
39093 +static struct platform_device *alarm_platform_dev;
39094 +static struct hrtimer alarm_timer[ANDROID_ALARM_TYPE_COUNT];
39095 +static struct timespec alarm_time[ANDROID_ALARM_TYPE_COUNT];
39096 +static struct timespec elapsed_rtc_delta;
39097 +
39098 +static void alarm_start_hrtimer(android_alarm_type_t alarm_type)
39099 +{
39100 +       struct timespec hr_alarm_time;
39101 +       if(!(alarm_enabled & (1U << alarm_type)))
39102 +               return;
39103 +       hr_alarm_time = alarm_time[alarm_type];
39104 +       if(alarm_type == ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP || alarm_type == ANDROID_ALARM_ELAPSED_REALTIME)
39105 +               set_normalized_timespec(&hr_alarm_time, hr_alarm_time.tv_sec + elapsed_rtc_delta.tv_sec,
39106 +                                       hr_alarm_time.tv_nsec + elapsed_rtc_delta.tv_nsec);
39107 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm start hrtimer %d at %ld.%09ld\n", alarm_type, hr_alarm_time.tv_sec, hr_alarm_time.tv_nsec);
39108 +       hrtimer_start(&alarm_timer[alarm_type], timespec_to_ktime(hr_alarm_time), HRTIMER_MODE_ABS);
39109 +}
39110 +
39111 +static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
39112 +{
39113 +       int rv = 0;
39114 +       unsigned long flags;
39115 +       int i;
39116 +       struct timespec new_alarm_time;
39117 +       struct timespec new_rtc_time;
39118 +       struct timespec tmp_time;
39119 +       struct rtc_time rtc_new_rtc_time;
39120 +       android_alarm_type_t alarm_type = ANDROID_ALARM_IOCTL_TO_TYPE(cmd);
39121 +       uint32_t alarm_type_mask = 1U << alarm_type;
39122 +
39123 +       if(alarm_type >= ANDROID_ALARM_TYPE_COUNT)
39124 +               return -EINVAL;
39125 +
39126 +       if(ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_GET_TIME(0)) {
39127 +               if ((file->f_flags & O_ACCMODE) == O_RDONLY)
39128 +                       return -EPERM;
39129 +               if(file->private_data == NULL && cmd != ANDROID_ALARM_SET_RTC) {
39130 +                       spin_lock_irqsave(&alarm_slock, flags);
39131 +                       if(alarm_opened) {
39132 +                               spin_unlock_irqrestore(&alarm_slock, flags);
39133 +                               return -EBUSY;
39134 +                       }
39135 +                       alarm_opened = 1;
39136 +                       file->private_data = (void *)1;
39137 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39138 +               }
39139 +       }
39140 +
39141 +       switch(ANDROID_ALARM_BASE_CMD(cmd)) {
39142 +               //case ANDROID_ALARM_CLEAR_OLD: // same as ANDROID_ALARM_CLEAR(0)
39143 +               case ANDROID_ALARM_CLEAR(0):
39144 +                       spin_lock_irqsave(&alarm_slock, flags);
39145 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm %d clear\n", alarm_type);
39146 +                       hrtimer_try_to_cancel(&alarm_timer[alarm_type]);
39147 +                       if(alarm_pending) {
39148 +                               alarm_pending &= ~alarm_type_mask;
39149 +                               if(!alarm_pending && !wait_pending) {
39150 +                                       android_unlock_suspend(&alarm_suspend_lock);
39151 +                               }
39152 +                       }
39153 +                       alarm_enabled &= ~alarm_type_mask;
39154 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39155 +                       break;
39156 +
39157 +               case ANDROID_ALARM_SET_OLD:
39158 +               case ANDROID_ALARM_SET_AND_WAIT_OLD:
39159 +                       if(get_user(new_alarm_time.tv_sec, (int __user *)arg)) {
39160 +                               rv = -EFAULT;
39161 +                               goto err1;
39162 +                       }
39163 +                       new_alarm_time.tv_nsec = 0;
39164 +                       goto from_old_alarm_set;
39165 +
39166 +               case ANDROID_ALARM_SET_AND_WAIT(0):
39167 +               case ANDROID_ALARM_SET(0):
39168 +                       if(copy_from_user(&new_alarm_time, (void __user *)arg, sizeof(new_alarm_time))) {
39169 +                               rv = -EFAULT;
39170 +                               goto err1;
39171 +                       }
39172 +from_old_alarm_set:
39173 +                       spin_lock_irqsave(&alarm_slock, flags);
39174 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm %d set %ld.%09ld\n", alarm_type, new_alarm_time.tv_sec, new_alarm_time.tv_nsec);
39175 +                       alarm_time[alarm_type] = new_alarm_time;
39176 +                       alarm_enabled |= alarm_type_mask;
39177 +                       alarm_start_hrtimer(alarm_type);
39178 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39179 +                       if(ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_SET_AND_WAIT(0) && cmd != ANDROID_ALARM_SET_AND_WAIT_OLD)
39180 +                               break;
39181 +                       // fall though
39182 +               case ANDROID_ALARM_WAIT:
39183 +                       spin_lock_irqsave(&alarm_slock, flags);
39184 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm wait\n");
39185 +                       if(!alarm_pending && wait_pending) {
39186 +                               android_unlock_suspend(&alarm_suspend_lock);
39187 +                               wait_pending = 0;
39188 +                       }
39189 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39190 +                       rv = wait_event_interruptible(alarm_wait_queue, alarm_pending);
39191 +                       if(rv)
39192 +                               goto err1;
39193 +                       spin_lock_irqsave(&alarm_slock, flags);
39194 +                       rv = alarm_pending;
39195 +                       wait_pending = 1;
39196 +                       alarm_pending = 0;
39197 +                       if(rv & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
39198 +                               android_unlock_suspend(&alarm_rtc_suspend_lock);
39199 +                       }
39200 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39201 +                       break;
39202 +               case ANDROID_ALARM_SET_RTC:
39203 +                       if(copy_from_user(&new_rtc_time, (void __user *)arg, sizeof(new_rtc_time))) {
39204 +                               rv = -EFAULT;
39205 +                               goto err1;
39206 +                       }
39207 +                       rtc_time_to_tm(new_rtc_time.tv_sec, &rtc_new_rtc_time);
39208 +
39209 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO,
39210 +                               "set rtc %ld %ld - rtc %02d:%02d:%02d %02d/%02d/%04d\n",
39211 +                               new_rtc_time.tv_sec, new_rtc_time.tv_nsec,
39212 +                               rtc_new_rtc_time.tm_hour, rtc_new_rtc_time.tm_min,
39213 +                               rtc_new_rtc_time.tm_sec, rtc_new_rtc_time.tm_mon + 1,
39214 +                               rtc_new_rtc_time.tm_mday, rtc_new_rtc_time.tm_year + 1900);
39215 +
39216 +                       mutex_lock(&alarm_setrtc_mutex);
39217 +                       spin_lock_irqsave(&alarm_slock, flags);
39218 +                       for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++)
39219 +                               hrtimer_try_to_cancel(&alarm_timer[i]);
39220 +                       getnstimeofday(&tmp_time);
39221 +                       elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, timespec_sub(tmp_time, new_rtc_time));
39222 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39223 +                       rv = do_settimeofday(&new_rtc_time);
39224 +                       spin_lock_irqsave(&alarm_slock, flags);
39225 +                       for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++)
39226 +                               alarm_start_hrtimer(i);
39227 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39228 +                       if(rv < 0) {
39229 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, "Failed to set time\n");
39230 +                               mutex_unlock(&alarm_setrtc_mutex);
39231 +                               goto err1;
39232 +                       }
39233 +                       rv = rtc_set_time(alarm_rtc_dev, &rtc_new_rtc_time);
39234 +                       spin_lock_irqsave(&alarm_slock, flags);
39235 +                       alarm_pending |= ANDROID_ALARM_TIME_CHANGE_MASK;
39236 +                       wake_up(&alarm_wait_queue);
39237 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39238 +                       mutex_unlock(&alarm_setrtc_mutex);
39239 +                       if(rv < 0) {
39240 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, "Failed to set RTC, time will be lost on reboot\n");
39241 +                               goto err1;
39242 +                       }
39243 +                       break;
39244 +               case ANDROID_ALARM_GET_TIME(0):
39245 +                       mutex_lock(&alarm_setrtc_mutex);
39246 +                       spin_lock_irqsave(&alarm_slock, flags);
39247 +                       if(alarm_type != ANDROID_ALARM_SYSTEMTIME) {
39248 +                               getnstimeofday(&tmp_time);
39249 +                               if(alarm_type >= ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP) {
39250 +                                       tmp_time = timespec_sub(tmp_time, elapsed_rtc_delta);
39251 +                               }
39252 +                       }
39253 +                       else
39254 +                               ktime_get_ts(&tmp_time);
39255 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39256 +                       mutex_unlock(&alarm_setrtc_mutex);
39257 +                       if(copy_to_user((void __user *)arg, &tmp_time, sizeof(tmp_time))) {
39258 +                               rv = -EFAULT;
39259 +                               goto err1;
39260 +                       }
39261 +                       break;
39262 +
39263 +               default:
39264 +                       rv = -EINVAL;
39265 +                       goto err1;
39266 +       }
39267 +err1:
39268 +       return rv;
39269 +}
39270 +
39271 +static int alarm_open(struct inode *inode, struct file *file)
39272 +{
39273 +       file->private_data = NULL;
39274 +       return 0;
39275 +}
39276 +
39277 +static int alarm_release(struct inode *inode, struct file *file)
39278 +{
39279 +       int i;
39280 +       unsigned long flags;
39281 +
39282 +       spin_lock_irqsave(&alarm_slock, flags);
39283 +       if(file->private_data != 0) {
39284 +               for(i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++) {
39285 +                       uint32_t alarm_type_mask = 1U << i;
39286 +                       if(alarm_enabled & alarm_type_mask) {
39287 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm_release: clear alarm, pending %d\n", !!(alarm_pending & alarm_type_mask));
39288 +                               alarm_enabled &= ~alarm_type_mask;
39289 +                       }
39290 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39291 +                       hrtimer_cancel(&alarm_timer[i]);
39292 +                       spin_lock_irqsave(&alarm_slock, flags);
39293 +               }
39294 +               if(alarm_pending | wait_pending) {
39295 +                       if(alarm_pending)
39296 +                               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm_release: clear pending alarms %x\n", alarm_pending);
39297 +                       android_unlock_suspend(&alarm_suspend_lock);
39298 +                       wait_pending = 0;
39299 +                       alarm_pending = 0;
39300 +               }
39301 +               alarm_opened = 0;
39302 +       }
39303 +       spin_unlock_irqrestore(&alarm_slock, flags);
39304 +       return 0;
39305 +}
39306 +
39307 +static enum hrtimer_restart alarm_timer_triggered(struct hrtimer *timer)
39308 +{
39309 +       unsigned long flags;
39310 +       android_alarm_type_t alarm_type = (timer - alarm_timer);
39311 +       uint32_t alarm_type_mask = 1U << alarm_type;
39312 +
39313 +
39314 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, "alarm_timer_triggered type %d\n", alarm_type);
39315 +       spin_lock_irqsave(&alarm_slock, flags);
39316 +       if (alarm_enabled & alarm_type_mask) {
39317 +               android_lock_suspend_auto_expire(&alarm_suspend_lock, 5 * HZ);
39318 +               alarm_enabled &= ~alarm_type_mask;
39319 +               alarm_pending |= alarm_type_mask;
39320 +               wake_up(&alarm_wait_queue);
39321 +       }
39322 +       spin_unlock_irqrestore(&alarm_slock, flags);
39323 +       return HRTIMER_NORESTART;
39324 +}
39325 +
39326 +static void alarm_triggered_func(void *p)
39327 +{
39328 +//     unsigned long flags;
39329 +
39330 +       struct rtc_device *rtc = alarm_rtc_dev;
39331 +       if(rtc->irq_data & RTC_AF) {
39332 +               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, "alarm_triggered_func:\n");
39333 +               android_lock_suspend_auto_expire(&alarm_rtc_suspend_lock, 1 * HZ);
39334 +       }
39335 +}
39336 +
39337 +int alarm_suspend(struct platform_device *pdev, pm_message_t state)
39338 +{
39339 +       int                 err = 0;
39340 +       unsigned long       flags;
39341 +       struct rtc_wkalrm   rtc_alarm;
39342 +       struct rtc_time     rtc_current_rtc_time;
39343 +       unsigned long       rtc_current_time;
39344 +       unsigned long       rtc_alarm_time;
39345 +       struct timespec     rtc_current_timespec;
39346 +       struct timespec     rtc_delta;
39347 +       struct timespec     elapsed_realtime_alarm_time;
39348 +
39349 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm_suspend(%p, %d)\n", pdev, state.event);
39350 +       spin_lock_irqsave(&alarm_slock, flags);
39351 +       if(alarm_pending && (alarm_suspend_lock.flags & ANDROID_SUSPEND_LOCK_AUTO_EXPIRE)) {
39352 +               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm pending\n");
39353 +               err = -EBUSY;
39354 +               goto err1;
39355 +       }
39356 +       if(alarm_enabled & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
39357 +               spin_unlock_irqrestore(&alarm_slock, flags);
39358 +               if(alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK)
39359 +                       hrtimer_cancel(&alarm_timer[ANDROID_ALARM_RTC_WAKEUP]);
39360 +               if(alarm_enabled & ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
39361 +                       hrtimer_cancel(&alarm_timer[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP]);
39362 +
39363 +               rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
39364 +               rtc_current_timespec.tv_nsec = 0;
39365 +               rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_timespec.tv_sec);
39366 +               save_time_delta(&rtc_delta, &rtc_current_timespec);
39367 +               set_normalized_timespec(&elapsed_realtime_alarm_time,
39368 +                       alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].tv_sec + elapsed_rtc_delta.tv_sec,
39369 +                       alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].tv_nsec + elapsed_rtc_delta.tv_nsec);
39370 +               if((alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK) &&
39371 +                  (!(alarm_enabled & ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
39372 +                  || timespec_compare(&alarm_time[ANDROID_ALARM_RTC_WAKEUP], &elapsed_realtime_alarm_time) < 0))
39373 +                       rtc_alarm_time = timespec_sub(alarm_time[ANDROID_ALARM_RTC_WAKEUP], rtc_delta).tv_sec;
39374 +               else {
39375 +                       rtc_alarm_time = timespec_sub(elapsed_realtime_alarm_time, rtc_delta).tv_sec;
39376 +               }
39377 +               rtc_time_to_tm(rtc_alarm_time, &rtc_alarm.time);
39378 +               rtc_alarm.enabled = 1;
39379 +               rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
39380 +               rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
39381 +               rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_time);
39382 +               ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO,
39383 +                       "rtc alarm set at %ld, now %ld, rtc delta %ld.%09ld\n",
39384 +                       rtc_alarm_time, rtc_current_time,
39385 +                       rtc_delta.tv_sec, rtc_delta.tv_nsec);
39386 +               if(rtc_current_time + 1 >= rtc_alarm_time) {
39387 +                       //spin_lock_irqsave(&alarm_slock, flags);
39388 +                       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm about to go off\n");
39389 +                       memset(&rtc_alarm, 0, sizeof(rtc_alarm));
39390 +                       rtc_alarm.enabled = 0;
39391 +                       rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
39392 +
39393 +                       spin_lock_irqsave(&alarm_slock, flags);
39394 +                       android_lock_suspend_auto_expire(&alarm_rtc_suspend_lock, 2 * HZ); // trigger a wakeup
39395 +                       alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP);
39396 +                       alarm_start_hrtimer(ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP);
39397 +                       err = -EBUSY;
39398 +                       spin_unlock_irqrestore(&alarm_slock, flags);
39399 +               }
39400 +       }
39401 +       else {
39402 +err1:
39403 +               spin_unlock_irqrestore(&alarm_slock, flags);
39404 +       }
39405 +       return err;
39406 +}
39407 +
39408 +int alarm_resume(struct platform_device *pdev)
39409 +{
39410 +       struct rtc_wkalrm alarm;
39411 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm_resume(%p)\n", pdev);
39412 +       if(alarm_enabled & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
39413 +               memset(&alarm, 0, sizeof(alarm));
39414 +               alarm.enabled = 0;
39415 +               rtc_set_alarm(alarm_rtc_dev, &alarm);
39416 +               alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP);
39417 +               alarm_start_hrtimer(ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP);
39418 +       }
39419 +       return 0;
39420 +}
39421 +
39422 +static struct rtc_task alarm_rtc_task = {
39423 +       .func = alarm_triggered_func
39424 +};
39425 +
39426 +static struct file_operations alarm_fops = {
39427 +       .owner = THIS_MODULE,
39428 +       .unlocked_ioctl = alarm_ioctl,
39429 +       .open = alarm_open,
39430 +       .release = alarm_release,
39431 +};
39432 +
39433 +static struct miscdevice alarm_device = {
39434 +       .minor = MISC_DYNAMIC_MINOR,
39435 +       .name = "alarm",
39436 +       .fops = &alarm_fops,
39437 +};
39438 +
39439 +static int rtc_alarm_add_device(struct device *dev,
39440 +                               struct class_interface *class_intf)
39441 +{
39442 +       int err;
39443 +       struct rtc_device *rtc = to_rtc_device(dev);
39444 +
39445 +       mutex_lock(&alarm_setrtc_mutex);
39446 +
39447 +       if(alarm_rtc_dev) {
39448 +               err = -EBUSY;
39449 +               goto err1;
39450 +       }
39451 +
39452 +       err = misc_register(&alarm_device);
39453 +       if(err)
39454 +               goto err1;
39455 +       alarm_platform_dev = platform_device_register_simple("alarm", -1, NULL, 0);
39456 +       if(IS_ERR(alarm_platform_dev)) {
39457 +               err = PTR_ERR(alarm_platform_dev);
39458 +               goto err2;
39459 +       }
39460 +       err = rtc_irq_register(rtc, &alarm_rtc_task);
39461 +       if(err)
39462 +               goto err3;
39463 +       alarm_rtc_dev = rtc;
39464 +       mutex_unlock(&alarm_setrtc_mutex);
39465 +
39466 +       //device_pm_set_parent(&alarm_platform_dev->dev, dev); // currently useless, drivers are suspended in reverse creation order
39467 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm: parent %p\n", alarm_platform_dev->dev.power.pm_parent);
39468 +       return 0;
39469 +
39470 +err3:
39471 +       platform_device_unregister(alarm_platform_dev);
39472 +err2:
39473 +       misc_deregister(&alarm_device);
39474 +err1:
39475 +       mutex_unlock(&alarm_setrtc_mutex);
39476 +       return err;
39477 +}
39478 +
39479 +static void rtc_alarm_remove_device(struct device *dev,
39480 +                                    struct class_interface *class_intf)
39481 +{
39482 +       if(dev == &alarm_rtc_dev->dev) {
39483 +               rtc_irq_unregister(alarm_rtc_dev, &alarm_rtc_task);
39484 +               platform_device_unregister(alarm_platform_dev);
39485 +               misc_deregister(&alarm_device);
39486 +               alarm_rtc_dev = NULL;
39487 +       }
39488 +}
39489 +
39490 +static struct class_interface rtc_alarm_interface = {
39491 +       .add_dev = &rtc_alarm_add_device,
39492 +       .remove_dev = &rtc_alarm_remove_device,
39493 +};
39494 +
39495 +static struct platform_driver alarm_driver = {
39496 +       .suspend = alarm_suspend,
39497 +       .resume = alarm_resume,
39498 +       .driver = {
39499 +               .name = "alarm"
39500 +       }
39501 +};
39502 +
39503 +static int __init alarm_late_init(void)
39504 +{
39505 +       unsigned long   flags;
39506 +       struct timespec system_time;
39507 +
39508 +       // this needs to run after the rtc is read at boot
39509 +       spin_lock_irqsave(&alarm_slock, flags);
39510 +       // We read the current rtc and system time so we can later calulate
39511 +       // elasped realtime to be (boot_systemtime + rtc - boot_rtc) ==
39512 +       // (rtc - (boot_rtc - boot_systemtime))
39513 +       getnstimeofday(&elapsed_rtc_delta);
39514 +       ktime_get_ts(&system_time);
39515 +       elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, system_time);
39516 +       spin_unlock_irqrestore(&alarm_slock, flags);
39517 +
39518 +       ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO,
39519 +               "alarm_late_init: rtc to elapsed realtime delta %ld.%09ld\n",
39520 +               elapsed_rtc_delta.tv_sec, elapsed_rtc_delta.tv_nsec);
39521 +       return 0;
39522 +}
39523 +
39524 +static int __init alarm_init(void)
39525 +{
39526 +       int err;
39527 +       int i;
39528 +
39529 +       for(i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) {
39530 +               hrtimer_init(&alarm_timer[i], CLOCK_REALTIME, HRTIMER_MODE_ABS);
39531 +               alarm_timer[i].function = alarm_timer_triggered;
39532 +       }
39533 +       hrtimer_init(&alarm_timer[ANDROID_ALARM_SYSTEMTIME], CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
39534 +       alarm_timer[ANDROID_ALARM_SYSTEMTIME].function = alarm_timer_triggered;
39535 +       err = platform_driver_register(&alarm_driver);
39536 +       if(err < 0)
39537 +               goto err1;
39538 +       err = android_init_suspend_lock(&alarm_suspend_lock);
39539 +       if(err < 0)
39540 +               goto err2;
39541 +       err = android_init_suspend_lock(&alarm_rtc_suspend_lock);
39542 +       if(err < 0)
39543 +               goto err3;
39544 +       rtc_alarm_interface.class = rtc_class;
39545 +       err = class_interface_register(&rtc_alarm_interface);
39546 +       if(err < 0)
39547 +               goto err4;
39548 +
39549 +       return 0;
39550 +
39551 +err4:
39552 +       android_uninit_suspend_lock(&alarm_rtc_suspend_lock);
39553 +err3:
39554 +       android_uninit_suspend_lock(&alarm_suspend_lock);
39555 +err2:
39556 +       platform_driver_unregister(&alarm_driver);
39557 +err1:
39558 +       return err;
39559 +}
39560 +
39561 +static void  __exit alarm_exit(void)
39562 +{
39563 +       class_interface_unregister(&rtc_alarm_interface);
39564 +       android_uninit_suspend_lock(&alarm_rtc_suspend_lock);
39565 +       android_uninit_suspend_lock(&alarm_suspend_lock);
39566 +       platform_driver_unregister(&alarm_driver);
39567 +}
39568 +
39569 +late_initcall(alarm_late_init);
39570 +module_init(alarm_init);
39571 +module_exit(alarm_exit);
39572 +
39573 Index: linux-2.6.28/drivers/android/binder.c
39574 ===================================================================
39575 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
39576 +++ linux-2.6.28/drivers/android/binder.c       2009-01-02 00:01:56.000000000 +0100
39577 @@ -0,0 +1,3495 @@
39578 +/* drivers/android/binder.c
39579 + *
39580 + * Android IPC Subsystem
39581 + *
39582 + * Copyright (C) 2007-2008 Google, Inc.
39583 + *
39584 + * This software is licensed under the terms of the GNU General Public
39585 + * License version 2, as published by the Free Software Foundation, and
39586 + * may be copied, distributed, and modified under those terms.
39587 + *
39588 + * This program is distributed in the hope that it will be useful,
39589 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
39590 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
39591 + * GNU General Public License for more details.
39592 + *
39593 + */
39594 +
39595 +#include <asm/cacheflush.h>
39596 +#include <linux/binder.h>
39597 +#include <linux/fdtable.h>
39598 +#include <linux/file.h>
39599 +#include <linux/fs.h>
39600 +#include <linux/list.h>
39601 +#include <linux/miscdevice.h>
39602 +#include <linux/mm.h>
39603 +#include <linux/module.h>
39604 +#include <linux/mutex.h>
39605 +#include <linux/nsproxy.h>
39606 +#include <linux/poll.h>
39607 +#include <linux/proc_fs.h>
39608 +#include <linux/rbtree.h>
39609 +#include <linux/sched.h>
39610 +#include <linux/uaccess.h>
39611 +#include <linux/vmalloc.h>
39612 +
39613 +static DEFINE_MUTEX(binder_lock);
39614 +static HLIST_HEAD(binder_procs);
39615 +static struct binder_node *binder_context_mgr_node;
39616 +static uid_t binder_context_mgr_uid = -1;
39617 +static int binder_last_id;
39618 +static struct proc_dir_entry *binder_proc_dir_entry_root;
39619 +static struct proc_dir_entry *binder_proc_dir_entry_proc;
39620 +static struct hlist_head binder_dead_nodes;
39621 +
39622 +static int binder_read_proc_proc(
39623 +       char *page, char **start, off_t off, int count, int *eof, void *data);
39624 +
39625 +/* This is only defined in include/asm-arm/sizes.h */
39626 +#ifndef SZ_1K
39627 +#define SZ_1K                               0x400
39628 +#endif
39629 +
39630 +#ifndef SZ_4M
39631 +#define SZ_4M                               0x400000
39632 +#endif
39633 +
39634 +#define FORBIDDEN_MMAP_FLAGS                (VM_WRITE)
39635 +
39636 +#define BINDER_SMALL_BUF_SIZE (PAGE_SIZE * 64)
39637 +
39638 +enum {
39639 +       BINDER_DEBUG_USER_ERROR             = 1U << 0,
39640 +       BINDER_DEBUG_FAILED_TRANSACTION     = 1U << 1,
39641 +       BINDER_DEBUG_DEAD_TRANSACTION       = 1U << 2,
39642 +       BINDER_DEBUG_OPEN_CLOSE             = 1U << 3,
39643 +       BINDER_DEBUG_DEAD_BINDER            = 1U << 4,
39644 +       BINDER_DEBUG_DEATH_NOTIFICATION     = 1U << 5,
39645 +       BINDER_DEBUG_READ_WRITE             = 1U << 6,
39646 +       BINDER_DEBUG_USER_REFS              = 1U << 7,
39647 +       BINDER_DEBUG_THREADS                = 1U << 8,
39648 +       BINDER_DEBUG_TRANSACTION            = 1U << 9,
39649 +       BINDER_DEBUG_TRANSACTION_COMPLETE   = 1U << 10,
39650 +       BINDER_DEBUG_FREE_BUFFER            = 1U << 11,
39651 +       BINDER_DEBUG_INTERNAL_REFS          = 1U << 12,
39652 +       BINDER_DEBUG_BUFFER_ALLOC           = 1U << 13,
39653 +       BINDER_DEBUG_PRIORITY_CAP           = 1U << 14,
39654 +       BINDER_DEBUG_BUFFER_ALLOC_ASYNC     = 1U << 15,
39655 +};
39656 +static uint32_t binder_debug_mask = BINDER_DEBUG_USER_ERROR |
39657 +       BINDER_DEBUG_FAILED_TRANSACTION | BINDER_DEBUG_DEAD_TRANSACTION;
39658 +module_param_named(debug_mask, binder_debug_mask, uint, S_IWUSR | S_IRUGO)
39659 +static int binder_debug_no_lock;
39660 +module_param_named(proc_no_lock, binder_debug_no_lock, bool, S_IWUSR | S_IRUGO)
39661 +static DECLARE_WAIT_QUEUE_HEAD(binder_user_error_wait);
39662 +static int binder_stop_on_user_error;
39663 +static int binder_set_stop_on_user_error(
39664 +       const char *val, struct kernel_param *kp)
39665 +{
39666 +       int ret;
39667 +       ret = param_set_int(val, kp);
39668 +       if (binder_stop_on_user_error < 2)
39669 +               wake_up(&binder_user_error_wait);
39670 +       return ret;
39671 +}
39672 +module_param_call(stop_on_user_error, binder_set_stop_on_user_error,
39673 +       param_get_int, &binder_stop_on_user_error, S_IWUSR | S_IRUGO);
39674 +
39675 +#define binder_user_error(x...) \
39676 +       do { \
39677 +               if (binder_debug_mask & BINDER_DEBUG_USER_ERROR) \
39678 +                       printk(KERN_INFO x); \
39679 +               if (binder_stop_on_user_error) \
39680 +                       binder_stop_on_user_error = 2; \
39681 +       } while (0)
39682 +
39683 +enum {
39684 +       BINDER_STAT_PROC,
39685 +       BINDER_STAT_THREAD,
39686 +       BINDER_STAT_NODE,
39687 +       BINDER_STAT_REF,
39688 +       BINDER_STAT_DEATH,
39689 +       BINDER_STAT_TRANSACTION,
39690 +       BINDER_STAT_TRANSACTION_COMPLETE,
39691 +       BINDER_STAT_COUNT
39692 +};
39693 +
39694 +struct binder_stats {
39695 +       int br[_IOC_NR(BR_FAILED_REPLY) + 1];
39696 +       int bc[_IOC_NR(BC_DEAD_BINDER_DONE) + 1];
39697 +       int obj_created[BINDER_STAT_COUNT];
39698 +       int obj_deleted[BINDER_STAT_COUNT];
39699 +};
39700 +
39701 +static struct binder_stats binder_stats;
39702 +
39703 +struct binder_transaction_log_entry {
39704 +       int debug_id;
39705 +       int call_type;
39706 +       int from_proc;
39707 +       int from_thread;
39708 +       int target_handle;
39709 +       int to_proc;
39710 +       int to_thread;
39711 +       int to_node;
39712 +       int data_size;
39713 +       int offsets_size;
39714 +};
39715 +struct binder_transaction_log {
39716 +       int next;
39717 +       int full;
39718 +       struct binder_transaction_log_entry entry[32];
39719 +};
39720 +struct binder_transaction_log binder_transaction_log;
39721 +struct binder_transaction_log binder_transaction_log_failed;
39722 +
39723 +static struct binder_transaction_log_entry *binder_transaction_log_add(
39724 +       struct binder_transaction_log *log)
39725 +{
39726 +       struct binder_transaction_log_entry *e;
39727 +       e = &log->entry[log->next];
39728 +       memset(e, 0, sizeof(*e));
39729 +       log->next++;
39730 +       if (log->next == ARRAY_SIZE(log->entry)) {
39731 +               log->next = 0;
39732 +               log->full = 1;
39733 +       }
39734 +       return e;
39735 +}
39736 +
39737 +struct binder_work {
39738 +       struct list_head entry;
39739 +       enum {
39740 +               BINDER_WORK_TRANSACTION = 1,
39741 +               BINDER_WORK_TRANSACTION_COMPLETE,
39742 +               BINDER_WORK_NODE,
39743 +               BINDER_WORK_DEAD_BINDER,
39744 +               BINDER_WORK_DEAD_BINDER_AND_CLEAR,
39745 +               BINDER_WORK_CLEAR_DEATH_NOTIFICATION,
39746 +       } type;
39747 +};
39748 +
39749 +struct binder_node {
39750 +       int debug_id;
39751 +       struct binder_work work;
39752 +       union {
39753 +               struct rb_node rb_node;
39754 +               struct hlist_node dead_node;
39755 +       };
39756 +       struct binder_proc *proc;
39757 +       struct hlist_head refs;
39758 +       int internal_strong_refs;
39759 +       int local_weak_refs;
39760 +       int local_strong_refs;
39761 +       void __user *ptr;
39762 +       void __user *cookie;
39763 +       unsigned has_strong_ref : 1;
39764 +       unsigned pending_strong_ref : 1;
39765 +       unsigned has_weak_ref : 1;
39766 +       unsigned pending_weak_ref : 1;
39767 +       unsigned has_async_transaction : 1;
39768 +       unsigned accept_fds : 1;
39769 +       int min_priority : 8;
39770 +       struct list_head async_todo;
39771 +};
39772 +
39773 +struct binder_ref_death {
39774 +       struct binder_work work;
39775 +       void __user *cookie;
39776 +};
39777 +
39778 +struct binder_ref {
39779 +       /* Lookups needed: */
39780 +       /*   node + proc => ref (transaction) */
39781 +       /*   desc + proc => ref (transaction, inc/dec ref) */
39782 +       /*   node => refs + procs (proc exit) */
39783 +       int debug_id;
39784 +       struct rb_node rb_node_desc;
39785 +       struct rb_node rb_node_node;
39786 +       struct hlist_node node_entry;
39787 +       struct binder_proc *proc;
39788 +       struct binder_node *node;
39789 +       uint32_t desc;
39790 +       int strong;
39791 +       int weak;
39792 +       struct binder_ref_death *death;
39793 +};
39794 +
39795 +struct binder_buffer {
39796 +       struct list_head entry; /* free and allocated entries by addesss */
39797 +       struct rb_node rb_node; /* free entry by size or allocated entry */
39798 +                               /* by address */
39799 +       unsigned free : 1;
39800 +       unsigned allow_user_free : 1;
39801 +       unsigned async_transaction : 1;
39802 +       unsigned debug_id : 29;
39803 +
39804 +       struct binder_transaction *transaction;
39805 +
39806 +       struct binder_node *target_node;
39807 +       size_t data_size;
39808 +       size_t offsets_size;
39809 +       uint8_t data[0];
39810 +};
39811 +
39812 +struct binder_proc {
39813 +       struct hlist_node proc_node;
39814 +       struct rb_root threads;
39815 +       struct rb_root nodes;
39816 +       struct rb_root refs_by_desc;
39817 +       struct rb_root refs_by_node;
39818 +       int pid;
39819 +       struct vm_area_struct *vma;
39820 +       struct task_struct *tsk;
39821 +       void *buffer;
39822 +       size_t user_buffer_offset;
39823 +
39824 +       struct list_head buffers;
39825 +       struct rb_root free_buffers;
39826 +       struct rb_root allocated_buffers;
39827 +       size_t free_async_space;
39828 +
39829 +       struct page **pages;
39830 +       size_t buffer_size;
39831 +       uint32_t buffer_free;
39832 +       struct list_head todo;
39833 +       wait_queue_head_t wait;
39834 +       struct binder_stats stats;
39835 +       struct list_head delivered_death;
39836 +       int max_threads;
39837 +       int requested_threads;
39838 +       int requested_threads_started;
39839 +       int ready_threads;
39840 +       long default_priority;
39841 +};
39842 +
39843 +enum {
39844 +       BINDER_LOOPER_STATE_REGISTERED  = 0x01,
39845 +       BINDER_LOOPER_STATE_ENTERED     = 0x02,
39846 +       BINDER_LOOPER_STATE_EXITED      = 0x04,
39847 +       BINDER_LOOPER_STATE_INVALID     = 0x08,
39848 +       BINDER_LOOPER_STATE_WAITING     = 0x10,
39849 +       BINDER_LOOPER_STATE_NEED_RETURN = 0x20
39850 +};
39851 +
39852 +struct binder_thread {
39853 +       struct binder_proc *proc;
39854 +       struct rb_node rb_node;
39855 +       int pid;
39856 +       int looper;
39857 +       struct binder_transaction *transaction_stack;
39858 +       struct list_head todo;
39859 +       uint32_t return_error; /* Write failed, return error code in read buf */
39860 +       uint32_t return_error2; /* Write failed, return error code in read */
39861 +               /* buffer. Used when sending a reply to a dead process that */
39862 +               /* we are also waiting on */
39863 +       wait_queue_head_t wait;
39864 +       struct binder_stats stats;
39865 +};
39866 +
39867 +struct binder_transaction {
39868 +       int debug_id;
39869 +       struct binder_work work;
39870 +       struct binder_thread *from;
39871 +       struct binder_transaction *from_parent;
39872 +       struct binder_proc *to_proc;
39873 +       struct binder_thread *to_thread;
39874 +       struct binder_transaction *to_parent;
39875 +       unsigned need_reply : 1;
39876 +       /*unsigned is_dead : 1;*/ /* not used at the moment */
39877 +
39878 +       struct binder_buffer *buffer;
39879 +       unsigned int    code;
39880 +       unsigned int    flags;
39881 +       long    priority;
39882 +       long    saved_priority;
39883 +       uid_t   sender_euid;
39884 +};
39885 +
39886 +/*
39887 + * copied from get_unused_fd_flags
39888 + */
39889 +int task_get_unused_fd_flags(struct task_struct *tsk, int flags)
39890 +{
39891 +       struct files_struct *files = get_files_struct(tsk);
39892 +       int fd, error;
39893 +       struct fdtable *fdt;
39894 +       unsigned long rlim_cur;
39895 +
39896 +       if (files == NULL)
39897 +               return -ESRCH;
39898 +
39899 +       error = -EMFILE;
39900 +       spin_lock(&files->file_lock);
39901 +
39902 +repeat:
39903 +       fdt = files_fdtable(files);
39904 +       fd = find_next_zero_bit(fdt->open_fds->fds_bits, fdt->max_fds,
39905 +                               files->next_fd);
39906 +
39907 +       /*
39908 +        * N.B. For clone tasks sharing a files structure, this test
39909 +        * will limit the total number of files that can be opened.
39910 +        */
39911 +       rcu_read_lock();
39912 +       if (tsk->signal)
39913 +               rlim_cur = tsk->signal->rlim[RLIMIT_NOFILE].rlim_cur;
39914 +       else
39915 +               rlim_cur = 0;
39916 +       rcu_read_unlock();
39917 +       if (fd >= rlim_cur)
39918 +               goto out;
39919 +
39920 +       /* Do we need to expand the fd array or fd set?  */
39921 +       error = expand_files(files, fd);
39922 +       if (error < 0)
39923 +               goto out;
39924 +
39925 +       if (error) {
39926 +               /*
39927 +                * If we needed to expand the fs array we
39928 +                * might have blocked - try again.
39929 +                */
39930 +               error = -EMFILE;
39931 +               goto repeat;
39932 +       }
39933 +
39934 +       FD_SET(fd, fdt->open_fds);
39935 +       if (flags & O_CLOEXEC)
39936 +               FD_SET(fd, fdt->close_on_exec);
39937 +       else
39938 +               FD_CLR(fd, fdt->close_on_exec);
39939 +       files->next_fd = fd + 1;
39940 +#if 1
39941 +       /* Sanity check */
39942 +       if (fdt->fd[fd] != NULL) {
39943 +               printk(KERN_WARNING "get_unused_fd: slot %d not NULL!\n", fd);
39944 +               fdt->fd[fd] = NULL;
39945 +       }
39946 +#endif
39947 +       error = fd;
39948 +
39949 +out:
39950 +       spin_unlock(&files->file_lock);
39951 +       put_files_struct(files);
39952 +       return error;
39953 +}
39954 +
39955 +/*
39956 + * copied from fd_install
39957 + */
39958 +static void task_fd_install(
39959 +       struct task_struct *tsk, unsigned int fd, struct file *file)
39960 +{
39961 +       struct files_struct *files = get_files_struct(tsk);
39962 +       struct fdtable *fdt;
39963 +
39964 +       if (files == NULL)
39965 +               return;
39966 +
39967 +       spin_lock(&files->file_lock);
39968 +       fdt = files_fdtable(files);
39969 +       BUG_ON(fdt->fd[fd] != NULL);
39970 +       rcu_assign_pointer(fdt->fd[fd], file);
39971 +       spin_unlock(&files->file_lock);
39972 +       put_files_struct(files);
39973 +}
39974 +
39975 +/*
39976 + * copied from __put_unused_fd in open.c
39977 + */
39978 +static void __put_unused_fd(struct files_struct *files, unsigned int fd)
39979 +{
39980 +       struct fdtable *fdt = files_fdtable(files);
39981 +       __FD_CLR(fd, fdt->open_fds);
39982 +       if (fd < files->next_fd)
39983 +               files->next_fd = fd;
39984 +}
39985 +
39986 +/*
39987 + * copied from sys_close
39988 + */
39989 +static long task_close_fd(struct task_struct *tsk, unsigned int fd)
39990 +{
39991 +       struct file *filp;
39992 +       struct files_struct *files = get_files_struct(tsk);
39993 +       struct fdtable *fdt;
39994 +       int retval;
39995 +
39996 +       if (files == NULL)
39997 +               return -ESRCH;
39998 +
39999 +       spin_lock(&files->file_lock);
40000 +       fdt = files_fdtable(files);
40001 +       if (fd >= fdt->max_fds)
40002 +               goto out_unlock;
40003 +       filp = fdt->fd[fd];
40004 +       if (!filp)
40005 +               goto out_unlock;
40006 +       rcu_assign_pointer(fdt->fd[fd], NULL);
40007 +       FD_CLR(fd, fdt->close_on_exec);
40008 +       __put_unused_fd(files, fd);
40009 +       spin_unlock(&files->file_lock);
40010 +       retval = filp_close(filp, files);
40011 +
40012 +       /* can't restart close syscall because file table entry was cleared */
40013 +       if (unlikely(retval == -ERESTARTSYS ||
40014 +                    retval == -ERESTARTNOINTR ||
40015 +                    retval == -ERESTARTNOHAND ||
40016 +                    retval == -ERESTART_RESTARTBLOCK))
40017 +               retval = -EINTR;
40018 +
40019 +       put_files_struct(files);
40020 +       return retval;
40021 +
40022 +out_unlock:
40023 +       spin_unlock(&files->file_lock);
40024 +       put_files_struct(files);
40025 +       return -EBADF;
40026 +}
40027 +
40028 +static void binder_set_nice(long nice)
40029 +{
40030 +       long min_nice;
40031 +       if (can_nice(current, nice)) {
40032 +               set_user_nice(current, nice);
40033 +               return;
40034 +       }
40035 +       min_nice = 20 - current->signal->rlim[RLIMIT_NICE].rlim_cur;
40036 +       if (binder_debug_mask & BINDER_DEBUG_PRIORITY_CAP)
40037 +               printk(KERN_INFO "binder: %d: nice value %ld not allowed use "
40038 +                      "%ld instead\n", current->pid, nice, min_nice);
40039 +       set_user_nice(current, min_nice);
40040 +       if (min_nice < 20)
40041 +               return;
40042 +       binder_user_error("binder: %d RLIMIT_NICE not set\n", current->pid);
40043 +}
40044 +
40045 +static size_t binder_buffer_size(
40046 +       struct binder_proc *proc, struct binder_buffer *buffer)
40047 +{
40048 +       if (list_is_last(&buffer->entry, &proc->buffers))
40049 +               return proc->buffer + proc->buffer_size - (void *)buffer->data;
40050 +       else
40051 +               return (size_t)list_entry(buffer->entry.next,
40052 +                       struct binder_buffer, entry) - (size_t)buffer->data;
40053 +}
40054 +
40055 +static void binder_insert_free_buffer(
40056 +       struct binder_proc *proc, struct binder_buffer *new_buffer)
40057 +{
40058 +       struct rb_node **p = &proc->free_buffers.rb_node;
40059 +       struct rb_node *parent = NULL;
40060 +       struct binder_buffer *buffer;
40061 +       size_t buffer_size;
40062 +       size_t new_buffer_size;
40063 +
40064 +       BUG_ON(!new_buffer->free);
40065 +
40066 +       new_buffer_size = binder_buffer_size(proc, new_buffer);
40067 +
40068 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40069 +               printk(KERN_INFO "binder: %d: add free buffer, size %d, "
40070 +                      "at %p\n", proc->pid, new_buffer_size, new_buffer);
40071 +
40072 +       while (*p) {
40073 +               parent = *p;
40074 +               buffer = rb_entry(parent, struct binder_buffer, rb_node);
40075 +               BUG_ON(!buffer->free);
40076 +
40077 +               buffer_size = binder_buffer_size(proc, buffer);
40078 +
40079 +               if (new_buffer_size < buffer_size)
40080 +                       p = &parent->rb_left;
40081 +               else
40082 +                       p = &parent->rb_right;
40083 +       }
40084 +       rb_link_node(&new_buffer->rb_node, parent, p);
40085 +       rb_insert_color(&new_buffer->rb_node, &proc->free_buffers);
40086 +}
40087 +
40088 +static void binder_insert_allocated_buffer(
40089 +       struct binder_proc *proc, struct binder_buffer *new_buffer)
40090 +{
40091 +       struct rb_node **p = &proc->allocated_buffers.rb_node;
40092 +       struct rb_node *parent = NULL;
40093 +       struct binder_buffer *buffer;
40094 +
40095 +       BUG_ON(new_buffer->free);
40096 +
40097 +       while (*p) {
40098 +               parent = *p;
40099 +               buffer = rb_entry(parent, struct binder_buffer, rb_node);
40100 +               BUG_ON(buffer->free);
40101 +
40102 +               if (new_buffer < buffer)
40103 +                       p = &parent->rb_left;
40104 +               else if (new_buffer > buffer)
40105 +                       p = &parent->rb_right;
40106 +               else
40107 +                       BUG();
40108 +       }
40109 +       rb_link_node(&new_buffer->rb_node, parent, p);
40110 +       rb_insert_color(&new_buffer->rb_node, &proc->allocated_buffers);
40111 +}
40112 +
40113 +static struct binder_buffer *binder_buffer_lookup(
40114 +       struct binder_proc *proc, void __user *user_ptr)
40115 +{
40116 +       struct rb_node *n = proc->allocated_buffers.rb_node;
40117 +       struct binder_buffer *buffer;
40118 +       struct binder_buffer *kern_ptr;
40119 +
40120 +       kern_ptr = user_ptr - proc->user_buffer_offset
40121 +               - offsetof(struct binder_buffer, data);
40122 +
40123 +       while (n) {
40124 +               buffer = rb_entry(n, struct binder_buffer, rb_node);
40125 +               BUG_ON(buffer->free);
40126 +
40127 +               if (kern_ptr < buffer)
40128 +                       n = n->rb_left;
40129 +               else if (kern_ptr > buffer)
40130 +                       n = n->rb_right;
40131 +               else
40132 +                       return buffer;
40133 +       }
40134 +       return NULL;
40135 +}
40136 +
40137 +static int binder_update_page_range(struct binder_proc *proc, int allocate,
40138 +       void *start, void *end, struct vm_area_struct *vma)
40139 +{
40140 +       void *page_addr;
40141 +       unsigned long user_page_addr;
40142 +       struct vm_struct tmp_area;
40143 +       struct page **page;
40144 +       struct mm_struct *mm;
40145 +
40146 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40147 +               printk(KERN_INFO "binder: %d: %s pages %p-%p\n",
40148 +                      proc->pid, allocate ? "allocate" : "free", start, end);
40149 +
40150 +       if (end <= start)
40151 +               return 0;
40152 +
40153 +       if (vma)
40154 +               mm = NULL;
40155 +       else
40156 +               mm = get_task_mm(proc->tsk);
40157 +
40158 +       if (mm) {
40159 +               down_write(&mm->mmap_sem);
40160 +               vma = proc->vma;
40161 +       }
40162 +
40163 +       if (allocate == 0)
40164 +               goto free_range;
40165 +
40166 +       if (vma == NULL) {
40167 +               printk(KERN_ERR "binder: %d: binder_alloc_buf failed to "
40168 +                      "map pages in userspace, no vma\n", proc->pid);
40169 +               goto err_no_vma;
40170 +       }
40171 +
40172 +       for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) {
40173 +               int ret;
40174 +               struct page **page_array_ptr;
40175 +               page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
40176 +
40177 +               BUG_ON(*page);
40178 +               *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
40179 +               if (*page == NULL) {
40180 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
40181 +                              "for page at %p\n", proc->pid, page_addr);
40182 +                       goto err_alloc_page_failed;
40183 +               }
40184 +               tmp_area.addr = page_addr;
40185 +               tmp_area.size = PAGE_SIZE + PAGE_SIZE /* guard page? */;
40186 +               page_array_ptr = page;
40187 +               ret = map_vm_area(&tmp_area, PAGE_KERNEL, &page_array_ptr);
40188 +               if (ret) {
40189 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
40190 +                              "to map page at %p in kernel\n",
40191 +                              proc->pid, page_addr);
40192 +                       goto err_map_kernel_failed;
40193 +               }
40194 +               user_page_addr = (size_t)page_addr + proc->user_buffer_offset;
40195 +               ret = vm_insert_page(vma, user_page_addr, page[0]);
40196 +               if (ret) {
40197 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
40198 +                              "to map page at %lx in userspace\n",
40199 +                              proc->pid, user_page_addr);
40200 +                       goto err_vm_insert_page_failed;
40201 +               }
40202 +               /* vm_insert_page does not seem to increment the refcount */
40203 +       }
40204 +       if (mm) {
40205 +               up_write(&mm->mmap_sem);
40206 +               mmput(mm);
40207 +       }
40208 +       return 0;
40209 +
40210 +free_range:
40211 +       for (page_addr = end - PAGE_SIZE; page_addr >= start;
40212 +            page_addr -= PAGE_SIZE) {
40213 +               page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
40214 +               if (vma)
40215 +                       zap_page_range(vma, (size_t)page_addr +
40216 +                               proc->user_buffer_offset, PAGE_SIZE, NULL);
40217 +err_vm_insert_page_failed:
40218 +               unmap_kernel_range((unsigned long)page_addr, PAGE_SIZE);
40219 +err_map_kernel_failed:
40220 +               __free_page(*page);
40221 +               *page = NULL;
40222 +err_alloc_page_failed:
40223 +               ;
40224 +       }
40225 +err_no_vma:
40226 +       if (mm) {
40227 +               up_write(&mm->mmap_sem);
40228 +               mmput(mm);
40229 +       }
40230 +       return -ENOMEM;
40231 +}
40232 +
40233 +static struct binder_buffer *binder_alloc_buf(struct binder_proc *proc,
40234 +       size_t data_size, size_t offsets_size, int is_async)
40235 +{
40236 +       struct rb_node *n = proc->free_buffers.rb_node;
40237 +       struct binder_buffer *buffer;
40238 +       size_t buffer_size;
40239 +       struct rb_node *best_fit = NULL;
40240 +       void *has_page_addr;
40241 +       void *end_page_addr;
40242 +       size_t size;
40243 +
40244 +       if (proc->vma == NULL) {
40245 +               printk(KERN_ERR "binder: %d: binder_alloc_buf, no vma\n",
40246 +                      proc->pid);
40247 +               return NULL;
40248 +       }
40249 +
40250 +       size = ALIGN(data_size, sizeof(void *)) +
40251 +               ALIGN(offsets_size, sizeof(void *));
40252 +
40253 +       if (size < data_size || size < offsets_size) {
40254 +               binder_user_error("binder: %d: got transaction with invalid "
40255 +                       "size %d-%d\n", proc->pid, data_size, offsets_size);
40256 +               return NULL;
40257 +       }
40258 +
40259 +       if (is_async &&
40260 +           proc->free_async_space < size + sizeof(struct binder_buffer)) {
40261 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40262 +                       printk(KERN_ERR "binder: %d: binder_alloc_buf size %d f"
40263 +                              "ailed, no async space left\n", proc->pid, size);
40264 +               return NULL;
40265 +       }
40266 +
40267 +       while (n) {
40268 +               buffer = rb_entry(n, struct binder_buffer, rb_node);
40269 +               BUG_ON(!buffer->free);
40270 +               buffer_size = binder_buffer_size(proc, buffer);
40271 +
40272 +               if (size < buffer_size) {
40273 +                       best_fit = n;
40274 +                       n = n->rb_left;
40275 +               } else if (size > buffer_size)
40276 +                       n = n->rb_right;
40277 +               else {
40278 +                       best_fit = n;
40279 +                       break;
40280 +               }
40281 +       }
40282 +       if (best_fit == NULL) {
40283 +               printk(KERN_ERR "binder: %d: binder_alloc_buf size %d failed, "
40284 +                      "no address space\n", proc->pid, size);
40285 +               return NULL;
40286 +       }
40287 +       if (n == NULL) {
40288 +               buffer = rb_entry(best_fit, struct binder_buffer, rb_node);
40289 +               buffer_size = binder_buffer_size(proc, buffer);
40290 +       }
40291 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40292 +               printk(KERN_INFO "binder: %d: binder_alloc_buf size %d got buff"
40293 +                      "er %p size %d\n", proc->pid, size, buffer, buffer_size);
40294 +
40295 +       has_page_addr =
40296 +               (void *)(((size_t)buffer->data + buffer_size) & PAGE_MASK);
40297 +       if (n == NULL) {
40298 +               if (size + sizeof(struct binder_buffer) + 4 >= buffer_size)
40299 +                       buffer_size = size; /* no room for other buffers */
40300 +               else
40301 +                       buffer_size = size + sizeof(struct binder_buffer);
40302 +       }
40303 +       end_page_addr = (void *)PAGE_ALIGN((size_t)buffer->data + buffer_size);
40304 +       if (end_page_addr > has_page_addr)
40305 +               end_page_addr = has_page_addr;
40306 +       if (binder_update_page_range(proc, 1,
40307 +           (void *)PAGE_ALIGN((size_t)buffer->data), end_page_addr, NULL))
40308 +               return NULL;
40309 +
40310 +       rb_erase(best_fit, &proc->free_buffers);
40311 +       buffer->free = 0;
40312 +       binder_insert_allocated_buffer(proc, buffer);
40313 +       if (buffer_size != size) {
40314 +               struct binder_buffer *new_buffer = (void *)buffer->data + size;
40315 +               list_add(&new_buffer->entry, &buffer->entry);
40316 +               new_buffer->free = 1;
40317 +               binder_insert_free_buffer(proc, new_buffer);
40318 +       }
40319 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40320 +               printk(KERN_INFO "binder: %d: binder_alloc_buf size %d got "
40321 +                      "%p\n", proc->pid, size, buffer);
40322 +       buffer->data_size = data_size;
40323 +       buffer->offsets_size = offsets_size;
40324 +       buffer->async_transaction = is_async;
40325 +       if (is_async) {
40326 +               proc->free_async_space -= size + sizeof(struct binder_buffer);
40327 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC_ASYNC)
40328 +                       printk(KERN_INFO "binder: %d: binder_alloc_buf size %d "
40329 +                              "async free %d\n", proc->pid, size,
40330 +                              proc->free_async_space);
40331 +       }
40332 +
40333 +       return buffer;
40334 +}
40335 +
40336 +static void *buffer_start_page(struct binder_buffer *buffer)
40337 +{
40338 +       return (void *)((size_t)buffer & PAGE_MASK);
40339 +}
40340 +
40341 +static void *buffer_end_page(struct binder_buffer *buffer)
40342 +{
40343 +       return (void *)(((size_t)(buffer + 1) - 1) & PAGE_MASK);
40344 +}
40345 +
40346 +static void binder_delete_free_buffer(
40347 +       struct binder_proc *proc, struct binder_buffer *buffer)
40348 +{
40349 +       struct binder_buffer *prev, *next = NULL;
40350 +       int free_page_end = 1;
40351 +       int free_page_start = 1;
40352 +
40353 +       BUG_ON(proc->buffers.next == &buffer->entry);
40354 +       prev = list_entry(buffer->entry.prev, struct binder_buffer, entry);
40355 +       BUG_ON(!prev->free);
40356 +       if (buffer_end_page(prev) == buffer_start_page(buffer)) {
40357 +               free_page_start = 0;
40358 +               if (buffer_end_page(prev) == buffer_end_page(buffer))
40359 +                       free_page_end = 0;
40360 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40361 +                       printk(KERN_INFO "binder: %d: merge free, buffer %p "
40362 +                              "share page with %p\n", proc->pid, buffer, prev);
40363 +       }
40364 +
40365 +       if (!list_is_last(&buffer->entry, &proc->buffers)) {
40366 +               next = list_entry(buffer->entry.next,
40367 +                                 struct binder_buffer, entry);
40368 +               if (buffer_start_page(next) == buffer_end_page(buffer)) {
40369 +                       free_page_end = 0;
40370 +                       if (buffer_start_page(next) ==
40371 +                           buffer_start_page(buffer))
40372 +                               free_page_start = 0;
40373 +                       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40374 +                               printk(KERN_INFO "binder: %d: merge free, "
40375 +                                      "buffer %p share page with %p\n",
40376 +                                      proc->pid, buffer, prev);
40377 +               }
40378 +       }
40379 +       list_del(&buffer->entry);
40380 +       if (free_page_start || free_page_end) {
40381 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40382 +                       printk(KERN_INFO "binder: %d: merge free, buffer %p do "
40383 +                              "not share page%s%s with with %p or %p\n",
40384 +                              proc->pid, buffer, free_page_start ? "" : " end",
40385 +                              free_page_end ? "" : " start", prev, next);
40386 +               binder_update_page_range(proc, 0, free_page_start ?
40387 +                       buffer_start_page(buffer) : buffer_end_page(buffer),
40388 +                       (free_page_end ? buffer_end_page(buffer) :
40389 +                       buffer_start_page(buffer)) + PAGE_SIZE, NULL);
40390 +       }
40391 +}
40392 +
40393 +static void binder_free_buf(
40394 +       struct binder_proc *proc, struct binder_buffer *buffer)
40395 +{
40396 +       size_t size, buffer_size;
40397 +
40398 +       buffer_size = binder_buffer_size(proc, buffer);
40399 +
40400 +       size = ALIGN(buffer->data_size, sizeof(void *)) +
40401 +               ALIGN(buffer->offsets_size, sizeof(void *));
40402 +       if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
40403 +               printk(KERN_INFO "binder: %d: binder_free_buf %p size %d buffer"
40404 +                      "_size %d\n", proc->pid, buffer, size, buffer_size);
40405 +
40406 +       BUG_ON(buffer->free);
40407 +       BUG_ON(size > buffer_size);
40408 +       BUG_ON(buffer->transaction != NULL);
40409 +       BUG_ON((void *)buffer < proc->buffer);
40410 +       BUG_ON((void *)buffer > proc->buffer + proc->buffer_size);
40411 +
40412 +       if (buffer->async_transaction) {
40413 +               proc->free_async_space += size + sizeof(struct binder_buffer);
40414 +               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC_ASYNC)
40415 +                       printk(KERN_INFO "binder: %d: binder_free_buf size %d "
40416 +                              "async free %d\n", proc->pid, size,
40417 +                              proc->free_async_space);
40418 +       }
40419 +
40420 +       binder_update_page_range(proc, 0,
40421 +               (void *)PAGE_ALIGN((size_t)buffer->data),
40422 +               (void *)(((size_t)buffer->data + buffer_size) & PAGE_MASK),
40423 +               NULL);
40424 +       rb_erase(&buffer->rb_node, &proc->allocated_buffers);
40425 +       buffer->free = 1;
40426 +       if (!list_is_last(&buffer->entry, &proc->buffers)) {
40427 +               struct binder_buffer *next = list_entry(buffer->entry.next,
40428 +                                               struct binder_buffer, entry);
40429 +               if (next->free) {
40430 +                       rb_erase(&next->rb_node, &proc->free_buffers);
40431 +                       binder_delete_free_buffer(proc, next);
40432 +               }
40433 +       }
40434 +       if (proc->buffers.next != &buffer->entry) {
40435 +               struct binder_buffer *prev = list_entry(buffer->entry.prev,
40436 +                                               struct binder_buffer, entry);
40437 +               if (prev->free) {
40438 +                       binder_delete_free_buffer(proc, buffer);
40439 +                       rb_erase(&prev->rb_node, &proc->free_buffers);
40440 +                       buffer = prev;
40441 +               }
40442 +       }
40443 +       binder_insert_free_buffer(proc, buffer);
40444 +}
40445 +
40446 +static struct binder_node *
40447 +binder_get_node(struct binder_proc *proc, void __user *ptr)
40448 +{
40449 +       struct rb_node *n = proc->nodes.rb_node;
40450 +       struct binder_node *node;
40451 +
40452 +       while (n) {
40453 +               node = rb_entry(n, struct binder_node, rb_node);
40454 +
40455 +               if (ptr < node->ptr)
40456 +                       n = n->rb_left;
40457 +               else if (ptr > node->ptr)
40458 +                       n = n->rb_right;
40459 +               else
40460 +                       return node;
40461 +       }
40462 +       return NULL;
40463 +}
40464 +
40465 +static struct binder_node *
40466 +binder_new_node(struct binder_proc *proc, void __user *ptr, void __user *cookie)
40467 +{
40468 +       struct rb_node **p = &proc->nodes.rb_node;
40469 +       struct rb_node *parent = NULL;
40470 +       struct binder_node *node;
40471 +
40472 +       while (*p) {
40473 +               parent = *p;
40474 +               node = rb_entry(parent, struct binder_node, rb_node);
40475 +
40476 +               if (ptr < node->ptr)
40477 +                       p = &(*p)->rb_left;
40478 +               else if (ptr > node->ptr)
40479 +                       p = &(*p)->rb_right;
40480 +               else
40481 +                       return NULL;
40482 +       }
40483 +
40484 +       node = kzalloc(sizeof(*node), GFP_KERNEL);
40485 +       if (node == NULL)
40486 +               return NULL;
40487 +       binder_stats.obj_created[BINDER_STAT_NODE]++;
40488 +       rb_link_node(&node->rb_node, parent, p);
40489 +       rb_insert_color(&node->rb_node, &proc->nodes);
40490 +       node->debug_id = ++binder_last_id;
40491 +       node->proc = proc;
40492 +       node->ptr = ptr;
40493 +       node->cookie = cookie;
40494 +       node->work.type = BINDER_WORK_NODE;
40495 +       INIT_LIST_HEAD(&node->work.entry);
40496 +       INIT_LIST_HEAD(&node->async_todo);
40497 +       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40498 +               printk(KERN_INFO "binder: %d:%d node %d u%p c%p created\n",
40499 +                      proc->pid, current->pid, node->debug_id,
40500 +                      node->ptr, node->cookie);
40501 +       return node;
40502 +}
40503 +
40504 +static int
40505 +binder_inc_node(struct binder_node *node, int strong, int internal,
40506 +               struct list_head *target_list)
40507 +{
40508 +       if (strong) {
40509 +               if (internal) {
40510 +                       if (target_list == NULL &&
40511 +                           node->internal_strong_refs == 0 &&
40512 +                           !(node == binder_context_mgr_node &&
40513 +                           node->has_strong_ref)) {
40514 +                               printk(KERN_ERR "binder: invalid inc strong "
40515 +                                       "node for %d\n", node->debug_id);
40516 +                               return -EINVAL;
40517 +                       }
40518 +                       node->internal_strong_refs++;
40519 +               } else
40520 +                       node->local_strong_refs++;
40521 +               if (!node->has_strong_ref && target_list) {
40522 +                       list_del_init(&node->work.entry);
40523 +                       list_add_tail(&node->work.entry, target_list);
40524 +               }
40525 +       } else {
40526 +               if (!internal)
40527 +                       node->local_weak_refs++;
40528 +               if (!node->has_weak_ref && list_empty(&node->work.entry)) {
40529 +                       if (target_list == NULL) {
40530 +                               printk(KERN_ERR "binder: invalid inc weak node "
40531 +                                       "for %d\n", node->debug_id);
40532 +                               return -EINVAL;
40533 +                       }
40534 +                       list_add_tail(&node->work.entry, target_list);
40535 +               }
40536 +       }
40537 +       return 0;
40538 +}
40539 +
40540 +static int
40541 +binder_dec_node(struct binder_node *node, int strong, int internal)
40542 +{
40543 +       if (strong) {
40544 +               if (internal)
40545 +                       node->internal_strong_refs--;
40546 +               else
40547 +                       node->local_strong_refs--;
40548 +               if (node->local_strong_refs || node->internal_strong_refs)
40549 +                       return 0;
40550 +       } else {
40551 +               if (!internal)
40552 +                       node->local_weak_refs--;
40553 +               if (node->local_weak_refs || !hlist_empty(&node->refs))
40554 +                       return 0;
40555 +       }
40556 +       if (node->proc && (node->has_strong_ref || node->has_weak_ref)) {
40557 +               if (list_empty(&node->work.entry)) {
40558 +                       list_add_tail(&node->work.entry, &node->proc->todo);
40559 +                       wake_up_interruptible(&node->proc->wait);
40560 +               }
40561 +       } else {
40562 +               if (hlist_empty(&node->refs) && !node->local_strong_refs &&
40563 +                   !node->local_weak_refs) {
40564 +                       list_del_init(&node->work.entry);
40565 +                       if (node->proc) {
40566 +                               rb_erase(&node->rb_node, &node->proc->nodes);
40567 +                               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40568 +                                       printk(KERN_INFO "binder: refless node %d deleted\n", node->debug_id);
40569 +                       } else {
40570 +                               hlist_del(&node->dead_node);
40571 +                               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40572 +                                       printk(KERN_INFO "binder: dead node %d deleted\n", node->debug_id);
40573 +                       }
40574 +                       kfree(node);
40575 +                       binder_stats.obj_deleted[BINDER_STAT_NODE]++;
40576 +               }
40577 +       }
40578 +
40579 +       return 0;
40580 +}
40581 +
40582 +
40583 +static struct binder_ref *
40584 +binder_get_ref(struct binder_proc *proc, uint32_t desc)
40585 +{
40586 +       struct rb_node *n = proc->refs_by_desc.rb_node;
40587 +       struct binder_ref *ref;
40588 +
40589 +       while (n) {
40590 +               ref = rb_entry(n, struct binder_ref, rb_node_desc);
40591 +
40592 +               if (desc < ref->desc)
40593 +                       n = n->rb_left;
40594 +               else if (desc > ref->desc)
40595 +                       n = n->rb_right;
40596 +               else
40597 +                       return ref;
40598 +       }
40599 +       return NULL;
40600 +}
40601 +
40602 +static struct binder_ref *
40603 +binder_get_ref_for_node(struct binder_proc *proc, struct binder_node *node)
40604 +{
40605 +       struct rb_node *n;
40606 +       struct rb_node **p = &proc->refs_by_node.rb_node;
40607 +       struct rb_node *parent = NULL;
40608 +       struct binder_ref *ref, *new_ref;
40609 +
40610 +       while (*p) {
40611 +               parent = *p;
40612 +               ref = rb_entry(parent, struct binder_ref, rb_node_node);
40613 +
40614 +               if (node < ref->node)
40615 +                       p = &(*p)->rb_left;
40616 +               else if (node > ref->node)
40617 +                       p = &(*p)->rb_right;
40618 +               else
40619 +                       return ref;
40620 +       }
40621 +       new_ref = kzalloc(sizeof(*ref), GFP_KERNEL);
40622 +       if (new_ref == NULL)
40623 +               return NULL;
40624 +       binder_stats.obj_created[BINDER_STAT_REF]++;
40625 +       new_ref->debug_id = ++binder_last_id;
40626 +       new_ref->proc = proc;
40627 +       new_ref->node = node;
40628 +       rb_link_node(&new_ref->rb_node_node, parent, p);
40629 +       rb_insert_color(&new_ref->rb_node_node, &proc->refs_by_node);
40630 +
40631 +       new_ref->desc = (node == binder_context_mgr_node) ? 0 : 1;
40632 +       for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
40633 +               ref = rb_entry(n, struct binder_ref, rb_node_desc);
40634 +               if (ref->desc > new_ref->desc)
40635 +                       break;
40636 +               new_ref->desc = ref->desc + 1;
40637 +       }
40638 +
40639 +       p = &proc->refs_by_desc.rb_node;
40640 +       while (*p) {
40641 +               parent = *p;
40642 +               ref = rb_entry(parent, struct binder_ref, rb_node_desc);
40643 +
40644 +               if (new_ref->desc < ref->desc)
40645 +                       p = &(*p)->rb_left;
40646 +               else if (new_ref->desc > ref->desc)
40647 +                       p = &(*p)->rb_right;
40648 +               else
40649 +                       BUG();
40650 +       }
40651 +       rb_link_node(&new_ref->rb_node_desc, parent, p);
40652 +       rb_insert_color(&new_ref->rb_node_desc, &proc->refs_by_desc);
40653 +       if (node) {
40654 +               hlist_add_head(&new_ref->node_entry, &node->refs);
40655 +               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40656 +                       printk(KERN_INFO "binder: %d new ref %d desc %d for "
40657 +                               "node %d\n", proc->pid, new_ref->debug_id,
40658 +                               new_ref->desc, node->debug_id);
40659 +       } else {
40660 +               if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40661 +                       printk(KERN_INFO "binder: %d new ref %d desc %d for "
40662 +                               "dead node\n", proc->pid, new_ref->debug_id,
40663 +                               new_ref->desc);
40664 +       }
40665 +       return new_ref;
40666 +}
40667 +
40668 +static void
40669 +binder_delete_ref(struct binder_ref *ref)
40670 +{
40671 +       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
40672 +               printk(KERN_INFO "binder: %d delete ref %d desc %d for "
40673 +                       "node %d\n", ref->proc->pid, ref->debug_id,
40674 +                       ref->desc, ref->node->debug_id);
40675 +       rb_erase(&ref->rb_node_desc, &ref->proc->refs_by_desc);
40676 +       rb_erase(&ref->rb_node_node, &ref->proc->refs_by_node);
40677 +       if (ref->strong)
40678 +               binder_dec_node(ref->node, 1, 1);
40679 +       hlist_del(&ref->node_entry);
40680 +       binder_dec_node(ref->node, 0, 1);
40681 +       if (ref->death) {
40682 +               if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
40683 +                       printk(KERN_INFO "binder: %d delete ref %d desc %d "
40684 +                               "has death notification\n", ref->proc->pid,
40685 +                               ref->debug_id, ref->desc);
40686 +               list_del(&ref->death->work.entry);
40687 +               kfree(ref->death);
40688 +               binder_stats.obj_deleted[BINDER_STAT_DEATH]++;
40689 +       }
40690 +       kfree(ref);
40691 +       binder_stats.obj_deleted[BINDER_STAT_REF]++;
40692 +}
40693 +
40694 +static int
40695 +binder_inc_ref(
40696 +       struct binder_ref *ref, int strong, struct list_head *target_list)
40697 +{
40698 +       int ret;
40699 +       if (strong) {
40700 +               if (ref->strong == 0) {
40701 +                       ret = binder_inc_node(ref->node, 1, 1, target_list);
40702 +                       if (ret)
40703 +                               return ret;
40704 +               }
40705 +               ref->strong++;
40706 +       } else {
40707 +               if (ref->weak == 0) {
40708 +                       ret = binder_inc_node(ref->node, 0, 1, target_list);
40709 +                       if (ret)
40710 +                               return ret;
40711 +               }
40712 +               ref->weak++;
40713 +       }
40714 +       return 0;
40715 +}
40716 +
40717 +
40718 +static int
40719 +binder_dec_ref(struct binder_ref *ref, int strong)
40720 +{
40721 +       if (strong) {
40722 +               if (ref->strong == 0) {
40723 +                       binder_user_error("binder: %d invalid dec strong, "
40724 +                                         "ref %d desc %d s %d w %d\n",
40725 +                                         ref->proc->pid, ref->debug_id,
40726 +                                         ref->desc, ref->strong, ref->weak);
40727 +                       return -EINVAL;
40728 +               }
40729 +               ref->strong--;
40730 +               if (ref->strong == 0) {
40731 +                       int ret;
40732 +                       ret = binder_dec_node(ref->node, strong, 1);
40733 +                       if (ret)
40734 +                               return ret;
40735 +               }
40736 +       } else {
40737 +               if (ref->weak == 0) {
40738 +                       binder_user_error("binder: %d invalid dec weak, "
40739 +                                         "ref %d desc %d s %d w %d\n",
40740 +                                         ref->proc->pid, ref->debug_id,
40741 +                                         ref->desc, ref->strong, ref->weak);
40742 +                       return -EINVAL;
40743 +               }
40744 +               ref->weak--;
40745 +       }
40746 +       if (ref->strong == 0 && ref->weak == 0)
40747 +               binder_delete_ref(ref);
40748 +       return 0;
40749 +}
40750 +
40751 +static void
40752 +binder_pop_transaction(
40753 +       struct binder_thread *target_thread, struct binder_transaction *t)
40754 +{
40755 +       if (target_thread) {
40756 +               BUG_ON(target_thread->transaction_stack != t);
40757 +               BUG_ON(target_thread->transaction_stack->from != target_thread);
40758 +               target_thread->transaction_stack =
40759 +                       target_thread->transaction_stack->from_parent;
40760 +               t->from = NULL;
40761 +       }
40762 +       t->need_reply = 0;
40763 +       if (t->buffer)
40764 +               t->buffer->transaction = NULL;
40765 +       kfree(t);
40766 +       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
40767 +}
40768 +
40769 +static void
40770 +binder_send_failed_reply(struct binder_transaction *t, uint32_t error_code)
40771 +{
40772 +       struct binder_thread *target_thread;
40773 +       BUG_ON(t->flags & TF_ONE_WAY);
40774 +       while (1) {
40775 +               target_thread = t->from;
40776 +               if (target_thread) {
40777 +                       if (target_thread->return_error != BR_OK &&
40778 +                          target_thread->return_error2 == BR_OK) {
40779 +                               target_thread->return_error2 =
40780 +                                       target_thread->return_error;
40781 +                               target_thread->return_error = BR_OK;
40782 +                       }
40783 +                       if (target_thread->return_error == BR_OK) {
40784 +                               if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
40785 +                                       printk(KERN_INFO "binder: send failed reply for transaction %d to %d:%d\n",
40786 +                                              t->debug_id, target_thread->proc->pid, target_thread->pid);
40787 +
40788 +                               binder_pop_transaction(target_thread, t);
40789 +                               target_thread->return_error = error_code;
40790 +                               wake_up_interruptible(&target_thread->wait);
40791 +                       } else {
40792 +                               printk(KERN_ERR "binder: reply failed, target "
40793 +                                       "thread, %d:%d, has error code %d "
40794 +                                       "already\n", target_thread->proc->pid,
40795 +                                       target_thread->pid,
40796 +                                       target_thread->return_error);
40797 +                       }
40798 +                       return;
40799 +               } else {
40800 +                       struct binder_transaction *next = t->from_parent;
40801 +
40802 +                       if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
40803 +                               printk(KERN_INFO "binder: send failed reply "
40804 +                                       "for transaction %d, target dead\n",
40805 +                                       t->debug_id);
40806 +
40807 +                       binder_pop_transaction(target_thread, t);
40808 +                       if (next == NULL) {
40809 +                               if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
40810 +                                       printk(KERN_INFO "binder: reply failed,"
40811 +                                               " no target thread at root\n");
40812 +                               return;
40813 +                       }
40814 +                       t = next;
40815 +                       if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
40816 +                               printk(KERN_INFO "binder: reply failed, no targ"
40817 +                                       "et thread -- retry %d\n", t->debug_id);
40818 +               }
40819 +       }
40820 +}
40821 +
40822 +static void
40823 +binder_transaction_buffer_release(struct binder_proc *proc,
40824 +                       struct binder_buffer *buffer, size_t *failed_at);
40825 +
40826 +static void
40827 +binder_transaction(struct binder_proc *proc, struct binder_thread *thread,
40828 +       struct binder_transaction_data *tr, int reply)
40829 +{
40830 +       struct binder_transaction *t;
40831 +       struct binder_work *tcomplete;
40832 +       size_t *offp, *off_end;
40833 +       struct binder_proc *target_proc;
40834 +       struct binder_thread *target_thread = NULL;
40835 +       struct binder_node *target_node = NULL;
40836 +       struct list_head *target_list;
40837 +       wait_queue_head_t *target_wait;
40838 +       struct binder_transaction *in_reply_to = NULL;
40839 +       struct binder_transaction_log_entry *e;
40840 +       uint32_t return_error;
40841 +
40842 +       e = binder_transaction_log_add(&binder_transaction_log);
40843 +       e->call_type = reply ? 2 : !!(tr->flags & TF_ONE_WAY);
40844 +       e->from_proc = proc->pid;
40845 +       e->from_thread = thread->pid;
40846 +       e->target_handle = tr->target.handle;
40847 +       e->data_size = tr->data_size;
40848 +       e->offsets_size = tr->offsets_size;
40849 +
40850 +       if (reply) {
40851 +               in_reply_to = thread->transaction_stack;
40852 +               if (in_reply_to == NULL) {
40853 +                       binder_user_error("binder: %d:%d got reply transaction "
40854 +                                         "with no transaction stack\n",
40855 +                                         proc->pid, thread->pid);
40856 +                       return_error = BR_FAILED_REPLY;
40857 +                       goto err_empty_call_stack;
40858 +               }
40859 +               binder_set_nice(in_reply_to->saved_priority);
40860 +               if (in_reply_to->to_thread != thread) {
40861 +                       binder_user_error("binder: %d:%d got reply transaction "
40862 +                               "with bad transaction stack,"
40863 +                               " transaction %d has target %d:%d\n",
40864 +                               proc->pid, thread->pid, in_reply_to->debug_id,
40865 +                               in_reply_to->to_proc ?
40866 +                               in_reply_to->to_proc->pid : 0,
40867 +                               in_reply_to->to_thread ?
40868 +                               in_reply_to->to_thread->pid : 0);
40869 +                       return_error = BR_FAILED_REPLY;
40870 +                       in_reply_to = NULL;
40871 +                       goto err_bad_call_stack;
40872 +               }
40873 +               thread->transaction_stack = in_reply_to->to_parent;
40874 +               target_thread = in_reply_to->from;
40875 +               if (target_thread == NULL) {
40876 +                       return_error = BR_DEAD_REPLY;
40877 +                       goto err_dead_binder;
40878 +               }
40879 +               if (target_thread->transaction_stack != in_reply_to) {
40880 +                       binder_user_error("binder: %d:%d got reply transaction "
40881 +                               "with bad target transaction stack %d, "
40882 +                               "expected %d\n",
40883 +                               proc->pid, thread->pid,
40884 +                               target_thread->transaction_stack ?
40885 +                               target_thread->transaction_stack->debug_id : 0,
40886 +                               in_reply_to->debug_id);
40887 +                       return_error = BR_FAILED_REPLY;
40888 +                       in_reply_to = NULL;
40889 +                       target_thread = NULL;
40890 +                       goto err_dead_binder;
40891 +               }
40892 +               target_proc = target_thread->proc;
40893 +       } else {
40894 +               if (tr->target.handle) {
40895 +                       struct binder_ref *ref;
40896 +                       ref = binder_get_ref(proc, tr->target.handle);
40897 +                       if (ref == NULL) {
40898 +                               binder_user_error("binder: %d:%d got "
40899 +                                       "transaction to invalid handle\n",
40900 +                                       proc->pid, thread->pid);
40901 +                               return_error = BR_FAILED_REPLY;
40902 +                               goto err_invalid_target_handle;
40903 +                       }
40904 +                       target_node = ref->node;
40905 +               } else {
40906 +                       target_node = binder_context_mgr_node;
40907 +                       if (target_node == NULL) {
40908 +                               return_error = BR_DEAD_REPLY;
40909 +                               goto err_no_context_mgr_node;
40910 +                       }
40911 +               }
40912 +               e->to_node = target_node->debug_id;
40913 +               target_proc = target_node->proc;
40914 +               if (target_proc == NULL) {
40915 +                       return_error = BR_DEAD_REPLY;
40916 +                       goto err_dead_binder;
40917 +               }
40918 +               if (!(tr->flags & TF_ONE_WAY) && thread->transaction_stack) {
40919 +                       struct binder_transaction *tmp;
40920 +                       tmp = thread->transaction_stack;
40921 +                       while (tmp) {
40922 +                               if (tmp->from && tmp->from->proc == target_proc)
40923 +                                       target_thread = tmp->from;
40924 +                               tmp = tmp->from_parent;
40925 +                       }
40926 +               }
40927 +       }
40928 +       if (target_thread) {
40929 +               e->to_thread = target_thread->pid;
40930 +               target_list = &target_thread->todo;
40931 +               target_wait = &target_thread->wait;
40932 +       } else {
40933 +               target_list = &target_proc->todo;
40934 +               target_wait = &target_proc->wait;
40935 +       }
40936 +       e->to_proc = target_proc->pid;
40937 +
40938 +       /* TODO: reuse incoming transaction for reply */
40939 +       t = kzalloc(sizeof(*t), GFP_KERNEL);
40940 +       if (t == NULL) {
40941 +               return_error = BR_FAILED_REPLY;
40942 +               goto err_alloc_t_failed;
40943 +       }
40944 +       binder_stats.obj_created[BINDER_STAT_TRANSACTION]++;
40945 +
40946 +       tcomplete = kzalloc(sizeof(*tcomplete), GFP_KERNEL);
40947 +       if (tcomplete == NULL) {
40948 +               return_error = BR_FAILED_REPLY;
40949 +               goto err_alloc_tcomplete_failed;
40950 +       }
40951 +       binder_stats.obj_created[BINDER_STAT_TRANSACTION_COMPLETE]++;
40952 +
40953 +       t->debug_id = ++binder_last_id;
40954 +       e->debug_id = t->debug_id;
40955 +
40956 +       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION) {
40957 +               if (reply)
40958 +                       printk(KERN_INFO "binder: %d:%d BC_REPLY %d -> %d:%d, "
40959 +                              "data %p-%p size %d-%d\n",
40960 +                              proc->pid, thread->pid, t->debug_id,
40961 +                              target_proc->pid, target_thread->pid,
40962 +                              tr->data.ptr.buffer, tr->data.ptr.offsets,
40963 +                              tr->data_size, tr->offsets_size);
40964 +               else
40965 +                       printk(KERN_INFO "binder: %d:%d BC_TRANSACTION %d -> "
40966 +                              "%d - node %d, data %p-%p size %d-%d\n",
40967 +                              proc->pid, thread->pid, t->debug_id,
40968 +                              target_proc->pid, target_node->debug_id,
40969 +                              tr->data.ptr.buffer, tr->data.ptr.offsets,
40970 +                              tr->data_size, tr->offsets_size);
40971 +       }
40972 +
40973 +       if (!reply && !(tr->flags & TF_ONE_WAY))
40974 +               t->from = thread;
40975 +       else
40976 +               t->from = NULL;
40977 +       t->sender_euid = proc->tsk->euid;
40978 +       t->to_proc = target_proc;
40979 +       t->to_thread = target_thread;
40980 +       t->code = tr->code;
40981 +       t->flags = tr->flags;
40982 +       t->priority = task_nice(current);
40983 +       t->buffer = binder_alloc_buf(target_proc, tr->data_size,
40984 +               tr->offsets_size, !reply && (t->flags & TF_ONE_WAY));
40985 +       if (t->buffer == NULL) {
40986 +               return_error = BR_FAILED_REPLY;
40987 +               goto err_binder_alloc_buf_failed;
40988 +       }
40989 +       t->buffer->allow_user_free = 0;
40990 +       t->buffer->debug_id = t->debug_id;
40991 +       t->buffer->transaction = t;
40992 +       t->buffer->target_node = target_node;
40993 +       if (target_node)
40994 +               binder_inc_node(target_node, 1, 0, NULL);
40995 +
40996 +       offp = (size_t *)(t->buffer->data + ALIGN(tr->data_size, sizeof(void *)));
40997 +
40998 +       if (copy_from_user(t->buffer->data, tr->data.ptr.buffer, tr->data_size)) {
40999 +               binder_user_error("binder: %d:%d got transaction with invalid "
41000 +                       "data ptr\n", proc->pid, thread->pid);
41001 +               return_error = BR_FAILED_REPLY;
41002 +               goto err_copy_data_failed;
41003 +       }
41004 +       if (copy_from_user(offp, tr->data.ptr.offsets, tr->offsets_size)) {
41005 +               binder_user_error("binder: %d:%d got transaction with invalid "
41006 +                       "offsets ptr\n", proc->pid, thread->pid);
41007 +               return_error = BR_FAILED_REPLY;
41008 +               goto err_copy_data_failed;
41009 +       }
41010 +       off_end = (void *)offp + tr->offsets_size;
41011 +       for (; offp < off_end; offp++) {
41012 +               struct flat_binder_object *fp;
41013 +               if (*offp > t->buffer->data_size - sizeof(*fp)) {
41014 +                       binder_user_error("binder: %d:%d got transaction with "
41015 +                               "invalid offset, %d\n",
41016 +                               proc->pid, thread->pid, *offp);
41017 +                       return_error = BR_FAILED_REPLY;
41018 +                       goto err_bad_offset;
41019 +               }
41020 +               fp = (struct flat_binder_object *)(t->buffer->data + *offp);
41021 +               switch (fp->type) {
41022 +               case BINDER_TYPE_BINDER:
41023 +               case BINDER_TYPE_WEAK_BINDER: {
41024 +                       struct binder_ref *ref;
41025 +                       struct binder_node *node = binder_get_node(proc, fp->binder);
41026 +                       if (node == NULL) {
41027 +                               node = binder_new_node(proc, fp->binder, fp->cookie);
41028 +                               if (node == NULL) {
41029 +                                       return_error = BR_FAILED_REPLY;
41030 +                                       goto err_binder_new_node_failed;
41031 +                               }
41032 +                               node->min_priority = fp->flags & FLAT_BINDER_FLAG_PRIORITY_MASK;
41033 +                               node->accept_fds = !!(fp->flags & FLAT_BINDER_FLAG_ACCEPTS_FDS);
41034 +                       }
41035 +                       if (fp->cookie != node->cookie) {
41036 +                               binder_user_error("binder: %d:%d sending u%p "
41037 +                                       "node %d, cookie mismatch %p != %p\n",
41038 +                                       proc->pid, thread->pid,
41039 +                                       fp->binder, node->debug_id,
41040 +                                       fp->cookie, node->cookie);
41041 +                               goto err_binder_get_ref_for_node_failed;
41042 +                       }
41043 +                       ref = binder_get_ref_for_node(target_proc, node);
41044 +                       if (ref == NULL) {
41045 +                               return_error = BR_FAILED_REPLY;
41046 +                               goto err_binder_get_ref_for_node_failed;
41047 +                       }
41048 +                       if (fp->type == BINDER_TYPE_BINDER)
41049 +                               fp->type = BINDER_TYPE_HANDLE;
41050 +                       else
41051 +                               fp->type = BINDER_TYPE_WEAK_HANDLE;
41052 +                       fp->handle = ref->desc;
41053 +                       binder_inc_ref(ref, fp->type == BINDER_TYPE_HANDLE, &thread->todo);
41054 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41055 +                               printk(KERN_INFO "        node %d u%p -> ref %d desc %d\n",
41056 +                                      node->debug_id, node->ptr, ref->debug_id, ref->desc);
41057 +               } break;
41058 +               case BINDER_TYPE_HANDLE:
41059 +               case BINDER_TYPE_WEAK_HANDLE: {
41060 +                       struct binder_ref *ref = binder_get_ref(proc, fp->handle);
41061 +                       if (ref == NULL) {
41062 +                               binder_user_error("binder: %d:%d got "
41063 +                                       "transaction with invalid "
41064 +                                       "handle, %ld\n", proc->pid,
41065 +                                       thread->pid, fp->handle);
41066 +                               return_error = BR_FAILED_REPLY;
41067 +                               goto err_binder_get_ref_failed;
41068 +                       }
41069 +                       if (ref->node->proc == target_proc) {
41070 +                               if (fp->type == BINDER_TYPE_HANDLE)
41071 +                                       fp->type = BINDER_TYPE_BINDER;
41072 +                               else
41073 +                                       fp->type = BINDER_TYPE_WEAK_BINDER;
41074 +                               fp->binder = ref->node->ptr;
41075 +                               fp->cookie = ref->node->cookie;
41076 +                               binder_inc_node(ref->node, fp->type == BINDER_TYPE_BINDER, 0, NULL);
41077 +                               if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41078 +                                       printk(KERN_INFO "        ref %d desc %d -> node %d u%p\n",
41079 +                                              ref->debug_id, ref->desc, ref->node->debug_id, ref->node->ptr);
41080 +                       } else {
41081 +                               struct binder_ref *new_ref;
41082 +                               new_ref = binder_get_ref_for_node(target_proc, ref->node);
41083 +                               if (new_ref == NULL) {
41084 +                                       return_error = BR_FAILED_REPLY;
41085 +                                       goto err_binder_get_ref_for_node_failed;
41086 +                               }
41087 +                               fp->handle = new_ref->desc;
41088 +                               binder_inc_ref(new_ref, fp->type == BINDER_TYPE_HANDLE, NULL);
41089 +                               if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41090 +                                       printk(KERN_INFO "        ref %d desc %d -> ref %d desc %d (node %d)\n",
41091 +                                              ref->debug_id, ref->desc, new_ref->debug_id, new_ref->desc, ref->node->debug_id);
41092 +                       }
41093 +               } break;
41094 +
41095 +               case BINDER_TYPE_FD: {
41096 +                       int target_fd;
41097 +                       struct file *file;
41098 +
41099 +                       if (reply) {
41100 +                               if (!(in_reply_to->flags & TF_ACCEPT_FDS)) {
41101 +                                       binder_user_error("binder: %d:%d got reply with fd, %ld, but target does not allow fds\n",
41102 +                                               proc->pid, thread->pid, fp->handle);
41103 +                                       return_error = BR_FAILED_REPLY;
41104 +                                       goto err_fd_not_allowed;
41105 +                               }
41106 +                       } else if (!target_node->accept_fds) {
41107 +                               binder_user_error("binder: %d:%d got transaction with fd, %ld, but target does not allow fds\n",
41108 +                                       proc->pid, thread->pid, fp->handle);
41109 +                               return_error = BR_FAILED_REPLY;
41110 +                               goto err_fd_not_allowed;
41111 +                       }
41112 +
41113 +                       file = fget(fp->handle);
41114 +                       if (file == NULL) {
41115 +                               binder_user_error("binder: %d:%d got transaction with invalid fd, %ld\n",
41116 +                                       proc->pid, thread->pid, fp->handle);
41117 +                               return_error = BR_FAILED_REPLY;
41118 +                               goto err_fget_failed;
41119 +                       }
41120 +                       target_fd = task_get_unused_fd_flags(target_proc->tsk, O_CLOEXEC);
41121 +                       if (target_fd < 0) {
41122 +                               fput(file);
41123 +                               return_error = BR_FAILED_REPLY;
41124 +                               goto err_get_unused_fd_failed;
41125 +                       }
41126 +                       task_fd_install(target_proc->tsk, target_fd, file);
41127 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41128 +                               printk(KERN_INFO "        fd %ld -> %d\n", fp->handle, target_fd);
41129 +                       /* TODO: fput? */
41130 +                       fp->handle = target_fd;
41131 +               } break;
41132 +
41133 +               default:
41134 +                       binder_user_error("binder: %d:%d got transactio"
41135 +                               "n with invalid object type, %lx\n",
41136 +                               proc->pid, thread->pid, fp->type);
41137 +                       return_error = BR_FAILED_REPLY;
41138 +                       goto err_bad_object_type;
41139 +               }
41140 +       }
41141 +       if (reply) {
41142 +               BUG_ON(t->buffer->async_transaction != 0);
41143 +               binder_pop_transaction(target_thread, in_reply_to);
41144 +       } else if (!(t->flags & TF_ONE_WAY)) {
41145 +               BUG_ON(t->buffer->async_transaction != 0);
41146 +               t->need_reply = 1;
41147 +               t->from_parent = thread->transaction_stack;
41148 +               thread->transaction_stack = t;
41149 +       } else {
41150 +               BUG_ON(target_node == NULL);
41151 +               BUG_ON(t->buffer->async_transaction != 1);
41152 +               if (target_node->has_async_transaction) {
41153 +                       target_list = &target_node->async_todo;
41154 +                       target_wait = NULL;
41155 +               } else
41156 +                       target_node->has_async_transaction = 1;
41157 +       }
41158 +       t->work.type = BINDER_WORK_TRANSACTION;
41159 +       list_add_tail(&t->work.entry, target_list);
41160 +       tcomplete->type = BINDER_WORK_TRANSACTION_COMPLETE;
41161 +       list_add_tail(&tcomplete->entry, &thread->todo);
41162 +       if (target_wait)
41163 +               wake_up_interruptible(target_wait);
41164 +       return;
41165 +
41166 +err_get_unused_fd_failed:
41167 +err_fget_failed:
41168 +err_fd_not_allowed:
41169 +err_binder_get_ref_for_node_failed:
41170 +err_binder_get_ref_failed:
41171 +err_binder_new_node_failed:
41172 +err_bad_object_type:
41173 +err_bad_offset:
41174 +err_copy_data_failed:
41175 +       binder_transaction_buffer_release(target_proc, t->buffer, offp);
41176 +       t->buffer->transaction = NULL;
41177 +       binder_free_buf(target_proc, t->buffer);
41178 +err_binder_alloc_buf_failed:
41179 +       kfree(tcomplete);
41180 +       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
41181 +err_alloc_tcomplete_failed:
41182 +       kfree(t);
41183 +       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
41184 +err_alloc_t_failed:
41185 +err_bad_call_stack:
41186 +err_empty_call_stack:
41187 +err_dead_binder:
41188 +err_invalid_target_handle:
41189 +err_no_context_mgr_node:
41190 +       if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
41191 +               printk(KERN_INFO "binder: %d:%d transaction failed %d, size %d-%d\n",
41192 +                          proc->pid, thread->pid, return_error,
41193 +                          tr->data_size, tr->offsets_size);
41194 +
41195 +       {
41196 +               struct binder_transaction_log_entry *fe;
41197 +               fe = binder_transaction_log_add(&binder_transaction_log_failed);
41198 +               *fe = *e;
41199 +       }
41200 +
41201 +       BUG_ON(thread->return_error != BR_OK);
41202 +       if (in_reply_to) {
41203 +               thread->return_error = BR_TRANSACTION_COMPLETE;
41204 +               binder_send_failed_reply(in_reply_to, return_error);
41205 +       } else
41206 +               thread->return_error = return_error;
41207 +}
41208 +
41209 +static void
41210 +binder_transaction_buffer_release(struct binder_proc *proc, struct binder_buffer *buffer, size_t *failed_at)
41211 +{
41212 +       size_t *offp, *off_end;
41213 +       int debug_id = buffer->debug_id;
41214 +
41215 +       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41216 +               printk(KERN_INFO "binder: %d buffer release %d, size %d-%d, failed at %p\n",
41217 +                          proc->pid, buffer->debug_id,
41218 +                          buffer->data_size, buffer->offsets_size, failed_at);
41219 +
41220 +       if (buffer->target_node)
41221 +               binder_dec_node(buffer->target_node, 1, 0);
41222 +
41223 +       offp = (size_t *)(buffer->data + ALIGN(buffer->data_size, sizeof(void *)));
41224 +       if (failed_at)
41225 +               off_end = failed_at;
41226 +       else
41227 +               off_end = (void *)offp + buffer->offsets_size;
41228 +       for (; offp < off_end; offp++) {
41229 +               struct flat_binder_object *fp;
41230 +               if (*offp > buffer->data_size - sizeof(*fp)) {
41231 +                       printk(KERN_ERR "binder: transaction release %d bad offset %d, size %d\n", debug_id, *offp, buffer->data_size);
41232 +                       continue;
41233 +               }
41234 +               fp = (struct flat_binder_object *)(buffer->data + *offp);
41235 +               switch (fp->type) {
41236 +               case BINDER_TYPE_BINDER:
41237 +               case BINDER_TYPE_WEAK_BINDER: {
41238 +                       struct binder_node *node = binder_get_node(proc, fp->binder);
41239 +                       if (node == NULL) {
41240 +                               printk(KERN_ERR "binder: transaction release %d bad node %p\n", debug_id, fp->binder);
41241 +                               break;
41242 +                       }
41243 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41244 +                               printk(KERN_INFO "        node %d u%p\n",
41245 +                                      node->debug_id, node->ptr);
41246 +                       binder_dec_node(node, fp->type == BINDER_TYPE_BINDER, 0);
41247 +               } break;
41248 +               case BINDER_TYPE_HANDLE:
41249 +               case BINDER_TYPE_WEAK_HANDLE: {
41250 +                       struct binder_ref *ref = binder_get_ref(proc, fp->handle);
41251 +                       if (ref == NULL) {
41252 +                               printk(KERN_ERR "binder: transaction release %d bad handle %ld\n", debug_id, fp->handle);
41253 +                               break;
41254 +                       }
41255 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41256 +                               printk(KERN_INFO "        ref %d desc %d (node %d)\n",
41257 +                                      ref->debug_id, ref->desc, ref->node->debug_id);
41258 +                       binder_dec_ref(ref, fp->type == BINDER_TYPE_HANDLE);
41259 +               } break;
41260 +
41261 +               case BINDER_TYPE_FD:
41262 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41263 +                               printk(KERN_INFO "        fd %ld\n", fp->handle);
41264 +                       if (failed_at)
41265 +                               task_close_fd(proc->tsk, fp->handle);
41266 +                       break;
41267 +
41268 +               default:
41269 +                       printk(KERN_ERR "binder: transaction release %d bad object type %lx\n", debug_id, fp->type);
41270 +                       break;
41271 +               }
41272 +       }
41273 +}
41274 +
41275 +int
41276 +binder_thread_write(struct binder_proc *proc, struct binder_thread *thread,
41277 +                   void __user *buffer, int size, signed long *consumed)
41278 +{
41279 +       uint32_t cmd;
41280 +       void __user *ptr = buffer + *consumed;
41281 +       void __user *end = buffer + size;
41282 +
41283 +       while (ptr < end && thread->return_error == BR_OK) {
41284 +               if (get_user(cmd, (uint32_t __user *)ptr))
41285 +                       return -EFAULT;
41286 +               ptr += sizeof(uint32_t);
41287 +               if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.bc)) {
41288 +                       binder_stats.bc[_IOC_NR(cmd)]++;
41289 +                       proc->stats.bc[_IOC_NR(cmd)]++;
41290 +                       thread->stats.bc[_IOC_NR(cmd)]++;
41291 +               }
41292 +               switch (cmd) {
41293 +               case BC_INCREFS:
41294 +               case BC_ACQUIRE:
41295 +               case BC_RELEASE:
41296 +               case BC_DECREFS: {
41297 +                       uint32_t target;
41298 +                       struct binder_ref *ref;
41299 +                       const char *debug_string;
41300 +
41301 +                       if (get_user(target, (uint32_t __user *)ptr))
41302 +                               return -EFAULT;
41303 +                       ptr += sizeof(uint32_t);
41304 +                       if (target == 0 && binder_context_mgr_node &&
41305 +                           (cmd == BC_INCREFS || cmd == BC_ACQUIRE)) {
41306 +                               ref = binder_get_ref_for_node(proc,
41307 +                                              binder_context_mgr_node);
41308 +                               if (ref->desc != target) {
41309 +                                       binder_user_error("binder: %d:"
41310 +                                               "%d tried to acquire "
41311 +                                               "reference to desc 0, "
41312 +                                               "got %d instead\n",
41313 +                                               proc->pid, thread->pid,
41314 +                                               ref->desc);
41315 +                               }
41316 +                       } else
41317 +                               ref = binder_get_ref(proc, target);
41318 +                       if (ref == NULL) {
41319 +                               binder_user_error("binder: %d:%d refcou"
41320 +                                       "nt change on invalid ref %d\n",
41321 +                                       proc->pid, thread->pid, target);
41322 +                               break;
41323 +                       }
41324 +                       switch (cmd) {
41325 +                       case BC_INCREFS:
41326 +                               debug_string = "IncRefs";
41327 +                               binder_inc_ref(ref, 0, NULL);
41328 +                               break;
41329 +                       case BC_ACQUIRE:
41330 +                               debug_string = "Acquire";
41331 +                               binder_inc_ref(ref, 1, NULL);
41332 +                               break;
41333 +                       case BC_RELEASE:
41334 +                               debug_string = "Release";
41335 +                               binder_dec_ref(ref, 1);
41336 +                               break;
41337 +                       case BC_DECREFS:
41338 +                       default:
41339 +                               debug_string = "DecRefs";
41340 +                               binder_dec_ref(ref, 0);
41341 +                               break;
41342 +                       }
41343 +                       if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
41344 +                               printk(KERN_INFO "binder: %d:%d %s ref %d desc %d s %d w %d for node %d\n",
41345 +                                      proc->pid, thread->pid, debug_string, ref->debug_id, ref->desc, ref->strong, ref->weak, ref->node->debug_id);
41346 +                       break;
41347 +               }
41348 +               case BC_INCREFS_DONE:
41349 +               case BC_ACQUIRE_DONE: {
41350 +                       void __user *node_ptr;
41351 +                       void *cookie;
41352 +                       struct binder_node *node;
41353 +
41354 +                       if (get_user(node_ptr, (void * __user *)ptr))
41355 +                               return -EFAULT;
41356 +                       ptr += sizeof(void *);
41357 +                       if (get_user(cookie, (void * __user *)ptr))
41358 +                               return -EFAULT;
41359 +                       ptr += sizeof(void *);
41360 +                       node = binder_get_node(proc, node_ptr);
41361 +                       if (node == NULL) {
41362 +                               binder_user_error("binder: %d:%d "
41363 +                                       "%s u%p no match\n",
41364 +                                       proc->pid, thread->pid,
41365 +                                       cmd == BC_INCREFS_DONE ?
41366 +                                       "BC_INCREFS_DONE" :
41367 +                                       "BC_ACQUIRE_DONE",
41368 +                                       node_ptr);
41369 +                               break;
41370 +                       }
41371 +                       if (cookie != node->cookie) {
41372 +                               binder_user_error("binder: %d:%d %s u%p node %d"
41373 +                                       " cookie mismatch %p != %p\n",
41374 +                                       proc->pid, thread->pid,
41375 +                                       cmd == BC_INCREFS_DONE ?
41376 +                                       "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE",
41377 +                                       node_ptr, node->debug_id,
41378 +                                       cookie, node->cookie);
41379 +                               break;
41380 +                       }
41381 +                       if (cmd == BC_ACQUIRE_DONE) {
41382 +                               if (node->pending_strong_ref == 0) {
41383 +                                       binder_user_error("binder: %d:%d "
41384 +                                               "BC_ACQUIRE_DONE node %d has "
41385 +                                               "no pending acquire request\n",
41386 +                                               proc->pid, thread->pid,
41387 +                                               node->debug_id);
41388 +                                       break;
41389 +                               }
41390 +                               node->pending_strong_ref = 0;
41391 +                       } else {
41392 +                               if (node->pending_weak_ref == 0) {
41393 +                                       binder_user_error("binder: %d:%d "
41394 +                                               "BC_INCREFS_DONE node %d has "
41395 +                                               "no pending increfs request\n",
41396 +                                               proc->pid, thread->pid,
41397 +                                               node->debug_id);
41398 +                                       break;
41399 +                               }
41400 +                               node->pending_weak_ref = 0;
41401 +                       }
41402 +                       binder_dec_node(node, cmd == BC_ACQUIRE_DONE, 0);
41403 +                       if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
41404 +                               printk(KERN_INFO "binder: %d:%d %s node %d ls %d lw %d\n",
41405 +                                      proc->pid, thread->pid, cmd == BC_INCREFS_DONE ? "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE", node->debug_id, node->local_strong_refs, node->local_weak_refs);
41406 +                       break;
41407 +               }
41408 +               case BC_ATTEMPT_ACQUIRE:
41409 +                       printk(KERN_ERR "binder: BC_ATTEMPT_ACQUIRE not supported\n");
41410 +                       return -EINVAL;
41411 +               case BC_ACQUIRE_RESULT:
41412 +                       printk(KERN_ERR "binder: BC_ACQUIRE_RESULT not supported\n");
41413 +                       return -EINVAL;
41414 +
41415 +               case BC_FREE_BUFFER: {
41416 +                       void __user *data_ptr;
41417 +                       struct binder_buffer *buffer;
41418 +
41419 +                       if (get_user(data_ptr, (void * __user *)ptr))
41420 +                               return -EFAULT;
41421 +                       ptr += sizeof(void *);
41422 +
41423 +                       buffer = binder_buffer_lookup(proc, data_ptr);
41424 +                       if (buffer == NULL) {
41425 +                               binder_user_error("binder: %d:%d "
41426 +                                       "BC_FREE_BUFFER u%p no match\n",
41427 +                                       proc->pid, thread->pid, data_ptr);
41428 +                               break;
41429 +                       }
41430 +                       if (!buffer->allow_user_free) {
41431 +                               binder_user_error("binder: %d:%d "
41432 +                                       "BC_FREE_BUFFER u%p matched "
41433 +                                       "unreturned buffer\n",
41434 +                                       proc->pid, thread->pid, data_ptr);
41435 +                               break;
41436 +                       }
41437 +                       if (binder_debug_mask & BINDER_DEBUG_FREE_BUFFER)
41438 +                               printk(KERN_INFO "binder: %d:%d BC_FREE_BUFFER u%p found buffer %d for %s transaction\n",
41439 +                                      proc->pid, thread->pid, data_ptr, buffer->debug_id,
41440 +                                      buffer->transaction ? "active" : "finished");
41441 +
41442 +                       if (buffer->transaction) {
41443 +                               buffer->transaction->buffer = NULL;
41444 +                               buffer->transaction = NULL;
41445 +                       }
41446 +                       if (buffer->async_transaction && buffer->target_node) {
41447 +                               BUG_ON(!buffer->target_node->has_async_transaction);
41448 +                               if (list_empty(&buffer->target_node->async_todo))
41449 +                                       buffer->target_node->has_async_transaction = 0;
41450 +                               else
41451 +                                       list_move_tail(buffer->target_node->async_todo.next, &thread->todo);
41452 +                       }
41453 +                       binder_transaction_buffer_release(proc, buffer, NULL);
41454 +                       binder_free_buf(proc, buffer);
41455 +                       break;
41456 +               }
41457 +
41458 +               case BC_TRANSACTION:
41459 +               case BC_REPLY: {
41460 +                       struct binder_transaction_data tr;
41461 +
41462 +                       if (copy_from_user(&tr, ptr, sizeof(tr)))
41463 +                               return -EFAULT;
41464 +                       ptr += sizeof(tr);
41465 +                       binder_transaction(proc, thread, &tr, cmd == BC_REPLY);
41466 +                       break;
41467 +               }
41468 +
41469 +               case BC_REGISTER_LOOPER:
41470 +                       if (binder_debug_mask & BINDER_DEBUG_THREADS)
41471 +                               printk(KERN_INFO "binder: %d:%d BC_REGISTER_LOOPER\n",
41472 +                                      proc->pid, thread->pid);
41473 +                       if (thread->looper & BINDER_LOOPER_STATE_ENTERED) {
41474 +                               thread->looper |= BINDER_LOOPER_STATE_INVALID;
41475 +                               binder_user_error("binder: %d:%d ERROR:"
41476 +                                       " BC_REGISTER_LOOPER called "
41477 +                                       "after BC_ENTER_LOOPER\n",
41478 +                                       proc->pid, thread->pid);
41479 +                       } else if (proc->requested_threads == 0) {
41480 +                               thread->looper |= BINDER_LOOPER_STATE_INVALID;
41481 +                               binder_user_error("binder: %d:%d ERROR:"
41482 +                                       " BC_REGISTER_LOOPER called "
41483 +                                       "without request\n",
41484 +                                       proc->pid, thread->pid);
41485 +                       } else {
41486 +                               proc->requested_threads--;
41487 +                               proc->requested_threads_started++;
41488 +                       }
41489 +                       thread->looper |= BINDER_LOOPER_STATE_REGISTERED;
41490 +                       break;
41491 +               case BC_ENTER_LOOPER:
41492 +                       if (binder_debug_mask & BINDER_DEBUG_THREADS)
41493 +                               printk(KERN_INFO "binder: %d:%d BC_ENTER_LOOPER\n",
41494 +                                      proc->pid, thread->pid);
41495 +                       if (thread->looper & BINDER_LOOPER_STATE_REGISTERED) {
41496 +                               thread->looper |= BINDER_LOOPER_STATE_INVALID;
41497 +                               binder_user_error("binder: %d:%d ERROR:"
41498 +                                       " BC_ENTER_LOOPER called after "
41499 +                                       "BC_REGISTER_LOOPER\n",
41500 +                                       proc->pid, thread->pid);
41501 +                       }
41502 +                       thread->looper |= BINDER_LOOPER_STATE_ENTERED;
41503 +                       break;
41504 +               case BC_EXIT_LOOPER:
41505 +                       if (binder_debug_mask & BINDER_DEBUG_THREADS)
41506 +                               printk(KERN_INFO "binder: %d:%d BC_EXIT_LOOPER\n",
41507 +                                      proc->pid, thread->pid);
41508 +                       thread->looper |= BINDER_LOOPER_STATE_EXITED;
41509 +                       break;
41510 +
41511 +               case BC_REQUEST_DEATH_NOTIFICATION:
41512 +               case BC_CLEAR_DEATH_NOTIFICATION: {
41513 +                       uint32_t target;
41514 +                       void __user *cookie;
41515 +                       struct binder_ref *ref;
41516 +                       struct binder_ref_death *death;
41517 +
41518 +                       if (get_user(target, (uint32_t __user *)ptr))
41519 +                               return -EFAULT;
41520 +                       ptr += sizeof(uint32_t);
41521 +                       if (get_user(cookie, (void __user * __user *)ptr))
41522 +                               return -EFAULT;
41523 +                       ptr += sizeof(void *);
41524 +                       ref = binder_get_ref(proc, target);
41525 +                       if (ref == NULL) {
41526 +                               binder_user_error("binder: %d:%d %s "
41527 +                                       "invalid ref %d\n",
41528 +                                       proc->pid, thread->pid,
41529 +                                       cmd == BC_REQUEST_DEATH_NOTIFICATION ?
41530 +                                       "BC_REQUEST_DEATH_NOTIFICATION" :
41531 +                                       "BC_CLEAR_DEATH_NOTIFICATION",
41532 +                                       target);
41533 +                               break;
41534 +                       }
41535 +
41536 +                       if (binder_debug_mask & BINDER_DEBUG_DEATH_NOTIFICATION)
41537 +                               printk(KERN_INFO "binder: %d:%d %s %p ref %d desc %d s %d w %d for node %d\n",
41538 +                                      proc->pid, thread->pid,
41539 +                                      cmd == BC_REQUEST_DEATH_NOTIFICATION ?
41540 +                                      "BC_REQUEST_DEATH_NOTIFICATION" :
41541 +                                      "BC_CLEAR_DEATH_NOTIFICATION",
41542 +                                      cookie, ref->debug_id, ref->desc,
41543 +                                      ref->strong, ref->weak, ref->node->debug_id);
41544 +
41545 +                       if (cmd == BC_REQUEST_DEATH_NOTIFICATION) {
41546 +                               if (ref->death) {
41547 +                                       binder_user_error("binder: %d:%"
41548 +                                               "d BC_REQUEST_DEATH_NOTI"
41549 +                                               "FICATION death notific"
41550 +                                               "ation already set\n",
41551 +                                               proc->pid, thread->pid);
41552 +                                       break;
41553 +                               }
41554 +                               death = kzalloc(sizeof(*death), GFP_KERNEL);
41555 +                               if (death == NULL) {
41556 +                                       thread->return_error = BR_ERROR;
41557 +                                       if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
41558 +                                               printk(KERN_INFO "binder: %d:%d "
41559 +                                                       "BC_REQUEST_DEATH_NOTIFICATION failed\n",
41560 +                                                       proc->pid, thread->pid);
41561 +                                       break;
41562 +                               }
41563 +                               binder_stats.obj_created[BINDER_STAT_DEATH]++;
41564 +                               INIT_LIST_HEAD(&death->work.entry);
41565 +                               death->cookie = cookie;
41566 +                               ref->death = death;
41567 +                               if (ref->node->proc == NULL) {
41568 +                                       ref->death->work.type = BINDER_WORK_DEAD_BINDER;
41569 +                                       if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
41570 +                                               list_add_tail(&ref->death->work.entry, &thread->todo);
41571 +                                       } else {
41572 +                                               list_add_tail(&ref->death->work.entry, &proc->todo);
41573 +                                               wake_up_interruptible(&proc->wait);
41574 +                                       }
41575 +                               }
41576 +                       } else {
41577 +                               if (ref->death == NULL) {
41578 +                                       binder_user_error("binder: %d:%"
41579 +                                               "d BC_CLEAR_DEATH_NOTIFI"
41580 +                                               "CATION death notificat"
41581 +                                               "ion not active\n",
41582 +                                               proc->pid, thread->pid);
41583 +                                       break;
41584 +                               }
41585 +                               death = ref->death;
41586 +                               if (death->cookie != cookie) {
41587 +                                       binder_user_error("binder: %d:%"
41588 +                                               "d BC_CLEAR_DEATH_NOTIFI"
41589 +                                               "CATION death notificat"
41590 +                                               "ion cookie mismatch "
41591 +                                               "%p != %p\n",
41592 +                                               proc->pid, thread->pid,
41593 +                                               death->cookie, cookie);
41594 +                                       break;
41595 +                               }
41596 +                               ref->death = NULL;
41597 +                               if (list_empty(&death->work.entry)) {
41598 +                                       death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION;
41599 +                                       if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
41600 +                                               list_add_tail(&death->work.entry, &thread->todo);
41601 +                                       } else {
41602 +                                               list_add_tail(&death->work.entry, &proc->todo);
41603 +                                               wake_up_interruptible(&proc->wait);
41604 +                                       }
41605 +                               } else {
41606 +                                       BUG_ON(death->work.type != BINDER_WORK_DEAD_BINDER);
41607 +                                       death->work.type = BINDER_WORK_DEAD_BINDER_AND_CLEAR;
41608 +                               }
41609 +                       }
41610 +               } break;
41611 +               case BC_DEAD_BINDER_DONE: {
41612 +                       struct binder_work *w;
41613 +                       void __user *cookie;
41614 +                       struct binder_ref_death *death = NULL;
41615 +                       if (get_user(cookie, (void __user * __user *)ptr))
41616 +                               return -EFAULT;
41617 +
41618 +                       ptr += sizeof(void *);
41619 +                       list_for_each_entry(w, &proc->delivered_death, entry) {
41620 +                               struct binder_ref_death *tmp_death = container_of(w, struct binder_ref_death, work);
41621 +                               if (tmp_death->cookie == cookie) {
41622 +                                       death = tmp_death;
41623 +                                       break;
41624 +                               }
41625 +                       }
41626 +                       if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
41627 +                               printk(KERN_INFO "binder: %d:%d BC_DEAD_BINDER_DONE %p found %p\n",
41628 +                                      proc->pid, thread->pid, cookie, death);
41629 +                       if (death == NULL) {
41630 +                               binder_user_error("binder: %d:%d BC_DEAD"
41631 +                                       "_BINDER_DONE %p not found\n",
41632 +                                       proc->pid, thread->pid, cookie);
41633 +                               break;
41634 +                       }
41635 +
41636 +                       list_del_init(&death->work.entry);
41637 +                       if (death->work.type == BINDER_WORK_DEAD_BINDER_AND_CLEAR) {
41638 +                               death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION;
41639 +                               if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
41640 +                                       list_add_tail(&death->work.entry, &thread->todo);
41641 +                               } else {
41642 +                                       list_add_tail(&death->work.entry, &proc->todo);
41643 +                                       wake_up_interruptible(&proc->wait);
41644 +                               }
41645 +                       }
41646 +               } break;
41647 +
41648 +               default:
41649 +                       printk(KERN_ERR "binder: %d:%d unknown command %d\n", proc->pid, thread->pid, cmd);
41650 +                       return -EINVAL;
41651 +               }
41652 +               *consumed = ptr - buffer;
41653 +       }
41654 +       return 0;
41655 +}
41656 +
41657 +void
41658 +binder_stat_br(struct binder_proc *proc, struct binder_thread *thread, uint32_t cmd)
41659 +{
41660 +       if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.br)) {
41661 +               binder_stats.br[_IOC_NR(cmd)]++;
41662 +               proc->stats.br[_IOC_NR(cmd)]++;
41663 +               thread->stats.br[_IOC_NR(cmd)]++;
41664 +       }
41665 +}
41666 +
41667 +static int
41668 +binder_has_proc_work(struct binder_proc *proc, struct binder_thread *thread)
41669 +{
41670 +       return !list_empty(&proc->todo) || (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN);
41671 +}
41672 +
41673 +static int
41674 +binder_has_thread_work(struct binder_thread *thread)
41675 +{
41676 +       return !list_empty(&thread->todo) || thread->return_error != BR_OK ||
41677 +               (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN);
41678 +}
41679 +
41680 +static int
41681 +binder_thread_read(struct binder_proc *proc, struct binder_thread *thread,
41682 +       void  __user *buffer, int size, signed long *consumed, int non_block)
41683 +{
41684 +       void __user *ptr = buffer + *consumed;
41685 +       void __user *end = buffer + size;
41686 +
41687 +       int ret = 0;
41688 +       int wait_for_proc_work;
41689 +
41690 +       if (*consumed == 0) {
41691 +               if (put_user(BR_NOOP, (uint32_t __user *)ptr))
41692 +                       return -EFAULT;
41693 +               ptr += sizeof(uint32_t);
41694 +       }
41695 +
41696 +retry:
41697 +       wait_for_proc_work = thread->transaction_stack == NULL && list_empty(&thread->todo);
41698 +
41699 +       if (thread->return_error != BR_OK && ptr < end) {
41700 +               if (thread->return_error2 != BR_OK) {
41701 +                       if (put_user(thread->return_error2, (uint32_t __user *)ptr))
41702 +                               return -EFAULT;
41703 +                       ptr += sizeof(uint32_t);
41704 +                       if (ptr == end)
41705 +                               goto done;
41706 +                       thread->return_error2 = BR_OK;
41707 +               }
41708 +               if (put_user(thread->return_error, (uint32_t __user *)ptr))
41709 +                       return -EFAULT;
41710 +               ptr += sizeof(uint32_t);
41711 +               thread->return_error = BR_OK;
41712 +               goto done;
41713 +       }
41714 +
41715 +
41716 +       thread->looper |= BINDER_LOOPER_STATE_WAITING;
41717 +       if (wait_for_proc_work)
41718 +               proc->ready_threads++;
41719 +       mutex_unlock(&binder_lock);
41720 +       if (wait_for_proc_work) {
41721 +               if (!(thread->looper & (BINDER_LOOPER_STATE_REGISTERED |
41722 +                                       BINDER_LOOPER_STATE_ENTERED))) {
41723 +                       binder_user_error("binder: %d:%d ERROR: Thread waiting "
41724 +                               "for process work before calling BC_REGISTER_"
41725 +                               "LOOPER or BC_ENTER_LOOPER (state %x)\n",
41726 +                               proc->pid, thread->pid, thread->looper);
41727 +                       wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
41728 +               }
41729 +               binder_set_nice(proc->default_priority);
41730 +               if (non_block) {
41731 +                       if (!binder_has_proc_work(proc, thread))
41732 +                               ret = -EAGAIN;
41733 +               } else
41734 +                       ret = wait_event_interruptible_exclusive(proc->wait, binder_has_proc_work(proc, thread));
41735 +       } else {
41736 +               if (non_block) {
41737 +                       if (!binder_has_thread_work(thread))
41738 +                               ret = -EAGAIN;
41739 +               } else
41740 +                       ret = wait_event_interruptible(thread->wait, binder_has_thread_work(thread));
41741 +       }
41742 +       mutex_lock(&binder_lock);
41743 +       if (wait_for_proc_work)
41744 +               proc->ready_threads--;
41745 +       thread->looper &= ~BINDER_LOOPER_STATE_WAITING;
41746 +
41747 +       if (ret)
41748 +               return ret;
41749 +
41750 +       while (1) {
41751 +               uint32_t cmd;
41752 +               struct binder_transaction_data tr;
41753 +               struct binder_work *w;
41754 +               struct binder_transaction *t = NULL;
41755 +
41756 +               if (!list_empty(&thread->todo))
41757 +                       w = list_first_entry(&thread->todo, struct binder_work, entry);
41758 +               else if (!list_empty(&proc->todo) && wait_for_proc_work)
41759 +                       w = list_first_entry(&proc->todo, struct binder_work, entry);
41760 +               else {
41761 +                       if (ptr - buffer == 4 && !(thread->looper & BINDER_LOOPER_STATE_NEED_RETURN)) /* no data added */
41762 +                               goto retry;
41763 +                       break;
41764 +               }
41765 +
41766 +               if (end - ptr < sizeof(tr) + 4)
41767 +                       break;
41768 +
41769 +               switch (w->type) {
41770 +               case BINDER_WORK_TRANSACTION: {
41771 +                       t = container_of(w, struct binder_transaction, work);
41772 +               } break;
41773 +               case BINDER_WORK_TRANSACTION_COMPLETE: {
41774 +                       cmd = BR_TRANSACTION_COMPLETE;
41775 +                       if (put_user(cmd, (uint32_t __user *)ptr))
41776 +                               return -EFAULT;
41777 +                       ptr += sizeof(uint32_t);
41778 +
41779 +                       binder_stat_br(proc, thread, cmd);
41780 +                       if (binder_debug_mask & BINDER_DEBUG_TRANSACTION_COMPLETE)
41781 +                               printk(KERN_INFO "binder: %d:%d BR_TRANSACTION_COMPLETE\n",
41782 +                                      proc->pid, thread->pid);
41783 +
41784 +                       list_del(&w->entry);
41785 +                       kfree(w);
41786 +                       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
41787 +               } break;
41788 +               case BINDER_WORK_NODE: {
41789 +                       struct binder_node *node = container_of(w, struct binder_node, work);
41790 +                       uint32_t cmd = BR_NOOP;
41791 +                       const char *cmd_name;
41792 +                       int strong = node->internal_strong_refs || node->local_strong_refs;
41793 +                       int weak = !hlist_empty(&node->refs) || node->local_weak_refs || strong;
41794 +                       if (weak && !node->has_weak_ref) {
41795 +                               cmd = BR_INCREFS;
41796 +                               cmd_name = "BR_INCREFS";
41797 +                               node->has_weak_ref = 1;
41798 +                               node->pending_weak_ref = 1;
41799 +                               node->local_weak_refs++;
41800 +                       } else if (strong && !node->has_strong_ref) {
41801 +                               cmd = BR_ACQUIRE;
41802 +                               cmd_name = "BR_ACQUIRE";
41803 +                               node->has_strong_ref = 1;
41804 +                               node->pending_strong_ref = 1;
41805 +                               node->local_strong_refs++;
41806 +                       } else if (!strong && node->has_strong_ref) {
41807 +                               cmd = BR_RELEASE;
41808 +                               cmd_name = "BR_RELEASE";
41809 +                               node->has_strong_ref = 0;
41810 +                       } else if (!weak && node->has_weak_ref) {
41811 +                               cmd = BR_DECREFS;
41812 +                               cmd_name = "BR_DECREFS";
41813 +                               node->has_weak_ref = 0;
41814 +                       }
41815 +                       if (cmd != BR_NOOP) {
41816 +                               if (put_user(cmd, (uint32_t __user *)ptr))
41817 +                                       return -EFAULT;
41818 +                               ptr += sizeof(uint32_t);
41819 +                               if (put_user(node->ptr, (void * __user *)ptr))
41820 +                                       return -EFAULT;
41821 +                               ptr += sizeof(void *);
41822 +                               if (put_user(node->cookie, (void * __user *)ptr))
41823 +                                       return -EFAULT;
41824 +                               ptr += sizeof(void *);
41825 +
41826 +                               binder_stat_br(proc, thread, cmd);
41827 +                               if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
41828 +                                       printk(KERN_INFO "binder: %d:%d %s %d u%p c%p\n",
41829 +                                              proc->pid, thread->pid, cmd_name, node->debug_id, node->ptr, node->cookie);
41830 +                       } else {
41831 +                               list_del_init(&w->entry);
41832 +                               if (!weak && !strong) {
41833 +                                       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
41834 +                                               printk(KERN_INFO "binder: %d:%d node %d u%p c%p deleted\n",
41835 +                                                      proc->pid, thread->pid, node->debug_id, node->ptr, node->cookie);
41836 +                                       rb_erase(&node->rb_node, &proc->nodes);
41837 +                                       kfree(node);
41838 +                                       binder_stats.obj_deleted[BINDER_STAT_NODE]++;
41839 +                               } else {
41840 +                                       if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
41841 +                                               printk(KERN_INFO "binder: %d:%d node %d u%p c%p state unchanged\n",
41842 +                                                      proc->pid, thread->pid, node->debug_id, node->ptr, node->cookie);
41843 +                               }
41844 +                       }
41845 +               } break;
41846 +               case BINDER_WORK_DEAD_BINDER:
41847 +               case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
41848 +               case BINDER_WORK_CLEAR_DEATH_NOTIFICATION: {
41849 +                       struct binder_ref_death *death = container_of(w, struct binder_ref_death, work);
41850 +                       uint32_t cmd;
41851 +                       if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION)
41852 +                               cmd = BR_CLEAR_DEATH_NOTIFICATION_DONE;
41853 +                       else
41854 +                               cmd = BR_DEAD_BINDER;
41855 +                       if (put_user(cmd, (uint32_t __user *)ptr))
41856 +                               return -EFAULT;
41857 +                       ptr += sizeof(uint32_t);
41858 +                       if (put_user(death->cookie, (void * __user *)ptr))
41859 +                               return -EFAULT;
41860 +                       ptr += sizeof(void *);
41861 +                       if (binder_debug_mask & BINDER_DEBUG_DEATH_NOTIFICATION)
41862 +                               printk(KERN_INFO "binder: %d:%d %s %p\n",
41863 +                                      proc->pid, thread->pid,
41864 +                                      cmd == BR_DEAD_BINDER ?
41865 +                                      "BR_DEAD_BINDER" :
41866 +                                      "BR_CLEAR_DEATH_NOTIFICATION_DONE",
41867 +                                      death->cookie);
41868 +
41869 +                       if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION) {
41870 +                               list_del(&w->entry);
41871 +                               kfree(death);
41872 +                               binder_stats.obj_deleted[BINDER_STAT_DEATH]++;
41873 +                       } else
41874 +                               list_move(&w->entry, &proc->delivered_death);
41875 +                       if (cmd == BR_DEAD_BINDER)
41876 +                               goto done; /* DEAD_BINDER notifications can cause transactions */
41877 +               } break;
41878 +               }
41879 +
41880 +               if (!t)
41881 +                       continue;
41882 +
41883 +               BUG_ON(t->buffer == NULL);
41884 +               if (t->buffer->target_node) {
41885 +                       struct binder_node *target_node = t->buffer->target_node;
41886 +                       tr.target.ptr = target_node->ptr;
41887 +                       tr.cookie =  target_node->cookie;
41888 +                       t->saved_priority = task_nice(current);
41889 +                       if (t->priority < target_node->min_priority &&
41890 +                           !(t->flags & TF_ONE_WAY))
41891 +                               binder_set_nice(t->priority);
41892 +                       else if (!(t->flags & TF_ONE_WAY) ||
41893 +                                t->saved_priority > target_node->min_priority)
41894 +                               binder_set_nice(target_node->min_priority);
41895 +                       cmd = BR_TRANSACTION;
41896 +               } else {
41897 +                       tr.target.ptr = NULL;
41898 +                       tr.cookie = NULL;
41899 +                       cmd = BR_REPLY;
41900 +               }
41901 +               tr.code = t->code;
41902 +               tr.flags = t->flags;
41903 +               tr.sender_euid = t->sender_euid;
41904 +
41905 +               if (t->from) {
41906 +                       struct task_struct *sender = t->from->proc->tsk;
41907 +                       tr.sender_pid = task_tgid_nr_ns(sender, current->nsproxy->pid_ns);
41908 +               } else {
41909 +                       tr.sender_pid = 0;
41910 +               }
41911 +
41912 +               tr.data_size = t->buffer->data_size;
41913 +               tr.offsets_size = t->buffer->offsets_size;
41914 +               tr.data.ptr.buffer = (void *)((void *)t->buffer->data + proc->user_buffer_offset);
41915 +               tr.data.ptr.offsets = tr.data.ptr.buffer + ALIGN(t->buffer->data_size, sizeof(void *));
41916 +
41917 +               if (put_user(cmd, (uint32_t __user *)ptr))
41918 +                       return -EFAULT;
41919 +               ptr += sizeof(uint32_t);
41920 +               if (copy_to_user(ptr, &tr, sizeof(tr)))
41921 +                       return -EFAULT;
41922 +               ptr += sizeof(tr);
41923 +
41924 +               binder_stat_br(proc, thread, cmd);
41925 +               if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
41926 +                       printk(KERN_INFO "binder: %d:%d %s %d %d:%d, cmd %d size %d-%d ptr %p-%p\n",
41927 +                              proc->pid, thread->pid,
41928 +                              (cmd == BR_TRANSACTION) ? "BR_TRANSACTION" : "BR_REPLY",
41929 +                              t->debug_id, t->from ? t->from->proc->pid : 0,
41930 +                              t->from ? t->from->pid : 0, cmd,
41931 +                              t->buffer->data_size, t->buffer->offsets_size,
41932 +                              tr.data.ptr.buffer, tr.data.ptr.offsets);
41933 +
41934 +               list_del(&t->work.entry);
41935 +               t->buffer->allow_user_free = 1;
41936 +               if (cmd == BR_TRANSACTION && !(t->flags & TF_ONE_WAY)) {
41937 +                       t->to_parent = thread->transaction_stack;
41938 +                       t->to_thread = thread;
41939 +                       thread->transaction_stack = t;
41940 +               } else {
41941 +                       t->buffer->transaction = NULL;
41942 +                       kfree(t);
41943 +                       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
41944 +               }
41945 +               break;
41946 +       }
41947 +
41948 +done:
41949 +
41950 +       *consumed = ptr - buffer;
41951 +       if (proc->requested_threads + proc->ready_threads == 0 &&
41952 +           proc->requested_threads_started < proc->max_threads &&
41953 +           (thread->looper & (BINDER_LOOPER_STATE_REGISTERED |
41954 +            BINDER_LOOPER_STATE_ENTERED)) /* the user-space code fails to */
41955 +            /*spawn a new thread if we leave this out */) {
41956 +               proc->requested_threads++;
41957 +               if (binder_debug_mask & BINDER_DEBUG_THREADS)
41958 +                       printk(KERN_INFO "binder: %d:%d BR_SPAWN_LOOPER\n",
41959 +                              proc->pid, thread->pid);
41960 +               if (put_user(BR_SPAWN_LOOPER, (uint32_t __user *)buffer))
41961 +                       return -EFAULT;
41962 +       }
41963 +       return 0;
41964 +}
41965 +
41966 +static void binder_release_work(struct list_head *list)
41967 +{
41968 +       struct binder_work *w;
41969 +       while (!list_empty(list)) {
41970 +               w = list_first_entry(list, struct binder_work, entry);
41971 +               list_del_init(&w->entry);
41972 +               switch (w->type) {
41973 +               case BINDER_WORK_TRANSACTION: {
41974 +                       struct binder_transaction *t = container_of(w, struct binder_transaction, work);
41975 +                       if (t->buffer->target_node && !(t->flags & TF_ONE_WAY))
41976 +                               binder_send_failed_reply(t, BR_DEAD_REPLY);
41977 +               } break;
41978 +               case BINDER_WORK_TRANSACTION_COMPLETE: {
41979 +                       kfree(w);
41980 +                       binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
41981 +               } break;
41982 +               default:
41983 +                       break;
41984 +               }
41985 +       }
41986 +
41987 +}
41988 +
41989 +static struct binder_thread *binder_get_thread(struct binder_proc *proc)
41990 +{
41991 +       struct binder_thread *thread = NULL;
41992 +       struct rb_node *parent = NULL;
41993 +       struct rb_node **p = &proc->threads.rb_node;
41994 +
41995 +       while (*p) {
41996 +               parent = *p;
41997 +               thread = rb_entry(parent, struct binder_thread, rb_node);
41998 +
41999 +               if (current->pid < thread->pid)
42000 +                       p = &(*p)->rb_left;
42001 +               else if (current->pid > thread->pid)
42002 +                       p = &(*p)->rb_right;
42003 +               else
42004 +                       break;
42005 +       }
42006 +       if (*p == NULL) {
42007 +               thread = kzalloc(sizeof(*thread), GFP_KERNEL);
42008 +               if (thread == NULL)
42009 +                       return NULL;
42010 +               binder_stats.obj_created[BINDER_STAT_THREAD]++;
42011 +               thread->proc = proc;
42012 +               thread->pid = current->pid;
42013 +               init_waitqueue_head(&thread->wait);
42014 +               INIT_LIST_HEAD(&thread->todo);
42015 +               rb_link_node(&thread->rb_node, parent, p);
42016 +               rb_insert_color(&thread->rb_node, &proc->threads);
42017 +               thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN;
42018 +               thread->return_error = BR_OK;
42019 +               thread->return_error2 = BR_OK;
42020 +       }
42021 +       return thread;
42022 +}
42023 +
42024 +static int binder_free_thread(struct binder_proc *proc, struct binder_thread *thread)
42025 +{
42026 +       struct binder_transaction *t;
42027 +       struct binder_transaction *send_reply = NULL;
42028 +       int active_transactions = 0;
42029 +
42030 +       rb_erase(&thread->rb_node, &proc->threads);
42031 +       t = thread->transaction_stack;
42032 +       if (t && t->to_thread == thread)
42033 +               send_reply = t;
42034 +       while (t) {
42035 +               active_transactions++;
42036 +               if (binder_debug_mask & BINDER_DEBUG_DEAD_TRANSACTION)
42037 +                       printk(KERN_INFO "binder: release %d:%d transaction %d %s, still active\n",
42038 +                              proc->pid, thread->pid, t->debug_id, (t->to_thread == thread) ? "in" : "out");
42039 +               if (t->to_thread == thread) {
42040 +                       t->to_proc = NULL;
42041 +                       t->to_thread = NULL;
42042 +                       if (t->buffer) {
42043 +                               t->buffer->transaction = NULL;
42044 +                               t->buffer = NULL;
42045 +                       }
42046 +                       t = t->to_parent;
42047 +               } else if (t->from == thread) {
42048 +                       t->from = NULL;
42049 +                       t = t->from_parent;
42050 +               } else
42051 +                       BUG();
42052 +       }
42053 +       if (send_reply)
42054 +               binder_send_failed_reply(send_reply, BR_DEAD_REPLY);
42055 +       binder_release_work(&thread->todo);
42056 +       kfree(thread);
42057 +       binder_stats.obj_deleted[BINDER_STAT_THREAD]++;
42058 +       return active_transactions;
42059 +}
42060 +
42061 +static unsigned int binder_poll(struct file *filp, struct poll_table_struct *wait)
42062 +{
42063 +       struct binder_proc *proc = filp->private_data;
42064 +       struct binder_thread *thread = NULL;
42065 +       int wait_for_proc_work;
42066 +
42067 +       mutex_lock(&binder_lock);
42068 +       thread = binder_get_thread(proc);
42069 +
42070 +       wait_for_proc_work = thread->transaction_stack == NULL &&
42071 +               list_empty(&thread->todo) && thread->return_error == BR_OK;
42072 +       mutex_unlock(&binder_lock);
42073 +
42074 +       if (wait_for_proc_work) {
42075 +               if (binder_has_proc_work(proc, thread))
42076 +                       return POLLIN;
42077 +               poll_wait(filp, &proc->wait, wait);
42078 +               if (binder_has_proc_work(proc, thread))
42079 +                       return POLLIN;
42080 +       } else {
42081 +               if (binder_has_thread_work(thread))
42082 +                       return POLLIN;
42083 +               poll_wait(filp, &thread->wait, wait);
42084 +               if (binder_has_thread_work(thread))
42085 +                       return POLLIN;
42086 +       }
42087 +       return 0;
42088 +}
42089 +
42090 +static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
42091 +{
42092 +       int ret;
42093 +       struct binder_proc *proc = filp->private_data;
42094 +       struct binder_thread *thread;
42095 +       unsigned int size = _IOC_SIZE(cmd);
42096 +       void __user *ubuf = (void __user *)arg;
42097 +
42098 +       /*printk(KERN_INFO "binder_ioctl: %d:%d %x %lx\n", proc->pid, current->pid, cmd, arg);*/
42099 +
42100 +       ret = wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
42101 +       if (ret)
42102 +               return ret;
42103 +
42104 +       mutex_lock(&binder_lock);
42105 +       thread = binder_get_thread(proc);
42106 +       if (thread == NULL) {
42107 +               ret = -ENOMEM;
42108 +               goto err;
42109 +       }
42110 +
42111 +       switch (cmd) {
42112 +       case BINDER_WRITE_READ: {
42113 +               struct binder_write_read bwr;
42114 +               if (size != sizeof(struct binder_write_read)) {
42115 +                       ret = -EINVAL;
42116 +                       goto err;
42117 +               }
42118 +               if (copy_from_user(&bwr, ubuf, sizeof(bwr))) {
42119 +                       ret = -EFAULT;
42120 +                       goto err;
42121 +               }
42122 +               if (binder_debug_mask & BINDER_DEBUG_READ_WRITE)
42123 +                       printk(KERN_INFO "binder: %d:%d write %ld at %08lx, read %ld at %08lx\n",
42124 +                              proc->pid, thread->pid, bwr.write_size, bwr.write_buffer, bwr.read_size, bwr.read_buffer);
42125 +               if (bwr.write_size > 0) {
42126 +                       ret = binder_thread_write(proc, thread, (void __user *)bwr.write_buffer, bwr.write_size, &bwr.write_consumed);
42127 +                       if (ret < 0) {
42128 +                               bwr.read_consumed = 0;
42129 +                               if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
42130 +                                       ret = -EFAULT;
42131 +                               goto err;
42132 +                       }
42133 +               }
42134 +               if (bwr.read_size > 0) {
42135 +                       ret = binder_thread_read(proc, thread, (void __user *)bwr.read_buffer, bwr.read_size, &bwr.read_consumed, filp->f_flags & O_NONBLOCK);
42136 +                       if (!list_empty(&proc->todo))
42137 +                               wake_up_interruptible(&proc->wait);
42138 +                       if (ret < 0) {
42139 +                               if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
42140 +                                       ret = -EFAULT;
42141 +                               goto err;
42142 +                       }
42143 +               }
42144 +               if (binder_debug_mask & BINDER_DEBUG_READ_WRITE)
42145 +                       printk(KERN_INFO "binder: %d:%d wrote %ld of %ld, read return %ld of %ld\n",
42146 +                              proc->pid, thread->pid, bwr.write_consumed, bwr.write_size, bwr.read_consumed, bwr.read_size);
42147 +               if (copy_to_user(ubuf, &bwr, sizeof(bwr))) {
42148 +                       ret = -EFAULT;
42149 +                       goto err;
42150 +               }
42151 +               break;
42152 +       }
42153 +       case BINDER_SET_MAX_THREADS:
42154 +               if (copy_from_user(&proc->max_threads, ubuf, sizeof(proc->max_threads))) {
42155 +                       ret = -EINVAL;
42156 +                       goto err;
42157 +               }
42158 +               break;
42159 +       case BINDER_SET_CONTEXT_MGR:
42160 +               if (binder_context_mgr_node != NULL) {
42161 +                       printk(KERN_ERR "binder: BINDER_SET_CONTEXT_MGR already set\n");
42162 +                       ret = -EBUSY;
42163 +                       goto err;
42164 +               }
42165 +               if (binder_context_mgr_uid != -1) {
42166 +                       if (binder_context_mgr_uid != current->euid) {
42167 +                               printk(KERN_ERR "binder: BINDER_SET_"
42168 +                                      "CONTEXT_MGR bad uid %d != %d\n",
42169 +                                      current->euid,
42170 +                                      binder_context_mgr_uid);
42171 +                               ret = -EPERM;
42172 +                               goto err;
42173 +                       }
42174 +               } else
42175 +                       binder_context_mgr_uid = current->euid;
42176 +               binder_context_mgr_node = binder_new_node(proc, NULL, NULL);
42177 +               if (binder_context_mgr_node == NULL) {
42178 +                       ret = -ENOMEM;
42179 +                       goto err;
42180 +               }
42181 +               binder_context_mgr_node->local_weak_refs++;
42182 +               binder_context_mgr_node->local_strong_refs++;
42183 +               binder_context_mgr_node->has_strong_ref = 1;
42184 +               binder_context_mgr_node->has_weak_ref = 1;
42185 +               break;
42186 +       case BINDER_THREAD_EXIT:
42187 +               if (binder_debug_mask & BINDER_DEBUG_THREADS)
42188 +                       printk(KERN_INFO "binder: %d:%d exit\n",
42189 +                              proc->pid, thread->pid);
42190 +               binder_free_thread(proc, thread);
42191 +               thread = NULL;
42192 +               break;
42193 +       case BINDER_VERSION:
42194 +               if (size != sizeof(struct binder_version)) {
42195 +                       ret = -EINVAL;
42196 +                       goto err;
42197 +               }
42198 +               if (put_user(BINDER_CURRENT_PROTOCOL_VERSION, &((struct binder_version *)ubuf)->protocol_version)) {
42199 +                       ret = -EINVAL;
42200 +                       goto err;
42201 +               }
42202 +               break;
42203 +       default:
42204 +               ret = -EINVAL;
42205 +               goto err;
42206 +       }
42207 +       ret = 0;
42208 +err:
42209 +       if (thread)
42210 +               thread->looper &= ~BINDER_LOOPER_STATE_NEED_RETURN;
42211 +       mutex_unlock(&binder_lock);
42212 +       wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
42213 +       if (ret && ret != -ERESTARTSYS)
42214 +               printk(KERN_INFO "binder: %d:%d ioctl %x %lx returned %d\n", proc->pid, current->pid, cmd, arg, ret);
42215 +       return ret;
42216 +}
42217 +
42218 +static void binder_vma_open(struct vm_area_struct *vma)
42219 +{
42220 +       struct binder_proc *proc = vma->vm_private_data;
42221 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
42222 +               printk(KERN_INFO "binder: %d open vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
42223 +       dump_stack();
42224 +}
42225 +static void binder_vma_close(struct vm_area_struct *vma)
42226 +{
42227 +       struct binder_proc *proc = vma->vm_private_data;
42228 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
42229 +               printk(KERN_INFO "binder: %d close vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
42230 +       proc->vma = NULL;
42231 +}
42232 +
42233 +static struct vm_operations_struct binder_vm_ops = {
42234 +       .open = binder_vma_open,
42235 +       .close = binder_vma_close,
42236 +};
42237 +
42238 +static int binder_mmap(struct file *filp, struct vm_area_struct *vma)
42239 +{
42240 +       int ret;
42241 +       struct vm_struct *area;
42242 +       struct binder_proc *proc = filp->private_data;
42243 +       const char *failure_string;
42244 +       struct binder_buffer *buffer;
42245 +
42246 +       if ((vma->vm_end - vma->vm_start) > SZ_4M)
42247 +               vma->vm_end = vma->vm_start + SZ_4M;
42248 +
42249 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
42250 +               printk(KERN_INFO "binder_mmap: %d %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
42251 +
42252 +       if (vma->vm_flags & FORBIDDEN_MMAP_FLAGS) {
42253 +               ret = -EPERM;
42254 +               failure_string = "bad vm_flags";
42255 +               goto err_bad_arg;
42256 +       }
42257 +       vma->vm_flags = (vma->vm_flags | VM_DONTCOPY) & ~VM_MAYWRITE;
42258 +
42259 +       area = get_vm_area(vma->vm_end - vma->vm_start, VM_IOREMAP);
42260 +       if (area == NULL) {
42261 +               ret = -ENOMEM;
42262 +               failure_string = "get_vm_area";
42263 +               goto err_get_vm_area_failed;
42264 +       }
42265 +       proc->buffer = area->addr;
42266 +       proc->user_buffer_offset = vma->vm_start - (size_t)proc->buffer;
42267 +
42268 +#if defined(CONFIG_CPU_CACHE_VIPT) && !defined(CONFIG_CPU_S3C6410)
42269 +       if (cache_is_vipt_aliasing()) {
42270 +               while (CACHE_COLOUR((vma->vm_start ^ (uint32_t)proc->buffer))) {
42271 +                       printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p bad alignment\n", proc->pid, vma->vm_start, vma->vm_end, proc->buffer);
42272 +                       vma->vm_start += PAGE_SIZE;
42273 +               }
42274 +       }
42275 +#endif
42276 +       proc->pages = kzalloc(sizeof(proc->pages[0]) * ((vma->vm_end - vma->vm_start) / PAGE_SIZE), GFP_KERNEL);
42277 +       if (proc->pages == NULL) {
42278 +               ret = -ENOMEM;
42279 +               failure_string = "alloc page array";
42280 +               goto err_alloc_pages_failed;
42281 +       }
42282 +       proc->buffer_size = vma->vm_end - vma->vm_start;
42283 +
42284 +       vma->vm_ops = &binder_vm_ops;
42285 +       vma->vm_private_data = proc;
42286 +
42287 +       if (binder_update_page_range(proc, 1, proc->buffer, proc->buffer + PAGE_SIZE, vma)) {
42288 +               ret = -ENOMEM;
42289 +               failure_string = "alloc small buf";
42290 +               goto err_alloc_small_buf_failed;
42291 +       }
42292 +       buffer = proc->buffer;
42293 +       INIT_LIST_HEAD(&proc->buffers);
42294 +       list_add(&buffer->entry, &proc->buffers);
42295 +       buffer->free = 1;
42296 +       binder_insert_free_buffer(proc, buffer);
42297 +       proc->free_async_space = proc->buffer_size / 2;
42298 +       barrier();
42299 +       proc->vma = vma;
42300 +
42301 +       /*printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p\n", proc->pid, vma->vm_start, vma->vm_end, proc->buffer);*/
42302 +       return 0;
42303 +
42304 +err_alloc_small_buf_failed:
42305 +       kfree(proc->pages);
42306 +err_alloc_pages_failed:
42307 +       vfree(proc->buffer);
42308 +err_get_vm_area_failed:
42309 +       mutex_unlock(&binder_lock);
42310 +err_bad_arg:
42311 +       printk(KERN_ERR "binder_mmap: %d %lx-%lx %s failed %d\n", proc->pid, vma->vm_start, vma->vm_end, failure_string, ret);
42312 +       return ret;
42313 +}
42314 +
42315 +static int binder_open(struct inode *nodp, struct file *filp)
42316 +{
42317 +       struct binder_proc *proc;
42318 +
42319 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
42320 +               printk(KERN_INFO "binder_open: %d:%d\n", current->group_leader->pid, current->pid);
42321 +
42322 +       proc = kzalloc(sizeof(*proc), GFP_KERNEL);
42323 +       if (proc == NULL)
42324 +               return -ENOMEM;
42325 +       get_task_struct(current);
42326 +       proc->tsk = current;
42327 +       INIT_LIST_HEAD(&proc->todo);
42328 +       init_waitqueue_head(&proc->wait);
42329 +       proc->default_priority = task_nice(current);
42330 +       mutex_lock(&binder_lock);
42331 +       binder_stats.obj_created[BINDER_STAT_PROC]++;
42332 +       hlist_add_head(&proc->proc_node, &binder_procs);
42333 +       proc->pid = current->group_leader->pid;
42334 +       INIT_LIST_HEAD(&proc->delivered_death);
42335 +       filp->private_data = proc;
42336 +       mutex_unlock(&binder_lock);
42337 +
42338 +       if (binder_proc_dir_entry_proc) {
42339 +               char strbuf[11];
42340 +               snprintf(strbuf, sizeof(strbuf), "%u", proc->pid);
42341 +               create_proc_read_entry(strbuf, S_IRUGO, binder_proc_dir_entry_proc, binder_read_proc_proc, proc);
42342 +       }
42343 +
42344 +       return 0;
42345 +}
42346 +
42347 +static int binder_flush(struct file *filp, fl_owner_t id)
42348 +{
42349 +       struct rb_node *n;
42350 +       struct binder_proc *proc = filp->private_data;
42351 +       int wake_count = 0;
42352 +
42353 +       mutex_lock(&binder_lock);
42354 +       for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n)) {
42355 +               struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node);
42356 +               thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN;
42357 +               if (thread->looper & BINDER_LOOPER_STATE_WAITING) {
42358 +                       wake_up_interruptible(&thread->wait);
42359 +                       wake_count++;
42360 +               }
42361 +       }
42362 +       wake_up_interruptible_all(&proc->wait);
42363 +       mutex_unlock(&binder_lock);
42364 +
42365 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
42366 +               printk(KERN_INFO "binder_flush: %d woke %d threads\n", proc->pid, wake_count);
42367 +
42368 +       return 0;
42369 +}
42370 +
42371 +static int binder_release(struct inode *nodp, struct file *filp)
42372 +{
42373 +       struct hlist_node *pos;
42374 +       struct binder_transaction *t;
42375 +       struct rb_node *n;
42376 +       struct binder_proc *proc = filp->private_data;
42377 +       int threads, nodes, incoming_refs, outgoing_refs, buffers, active_transactions, page_count;
42378 +
42379 +       if (binder_proc_dir_entry_proc) {
42380 +               char strbuf[11];
42381 +               snprintf(strbuf, sizeof(strbuf), "%u", proc->pid);
42382 +               remove_proc_entry(strbuf, binder_proc_dir_entry_proc);
42383 +       }
42384 +       mutex_lock(&binder_lock);
42385 +       hlist_del(&proc->proc_node);
42386 +       if (binder_context_mgr_node && binder_context_mgr_node->proc == proc) {
42387 +               if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
42388 +                       printk(KERN_INFO "binder_release: %d context_mgr_node gone\n", proc->pid);
42389 +               binder_context_mgr_node = NULL;
42390 +       }
42391 +
42392 +       threads = 0;
42393 +       active_transactions = 0;
42394 +       while ((n = rb_first(&proc->threads))) {
42395 +               struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node);
42396 +               threads++;
42397 +               active_transactions += binder_free_thread(proc, thread);
42398 +       }
42399 +       nodes = 0;
42400 +       incoming_refs = 0;
42401 +       while ((n = rb_first(&proc->nodes))) {
42402 +               struct binder_node *node = rb_entry(n, struct binder_node, rb_node);
42403 +
42404 +               nodes++;
42405 +               rb_erase(&node->rb_node, &proc->nodes);
42406 +               list_del_init(&node->work.entry);
42407 +               if (hlist_empty(&node->refs)) {
42408 +                       kfree(node);
42409 +                       binder_stats.obj_deleted[BINDER_STAT_NODE]++;
42410 +               } else {
42411 +                       struct binder_ref *ref;
42412 +                       int death = 0;
42413 +
42414 +                       node->proc = NULL;
42415 +                       node->local_strong_refs = 0;
42416 +                       node->local_weak_refs = 0;
42417 +                       hlist_add_head(&node->dead_node, &binder_dead_nodes);
42418 +
42419 +                       hlist_for_each_entry(ref, pos, &node->refs, node_entry) {
42420 +                               incoming_refs++;
42421 +                               if (ref->death) {
42422 +                                       death++;
42423 +                                       if (list_empty(&ref->death->work.entry)) {
42424 +                                               ref->death->work.type = BINDER_WORK_DEAD_BINDER;
42425 +                                               list_add_tail(&ref->death->work.entry, &ref->proc->todo);
42426 +                                               wake_up_interruptible(&ref->proc->wait);
42427 +                                       } else
42428 +                                               BUG();
42429 +                               }
42430 +                       }
42431 +                       if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
42432 +                               printk(KERN_INFO "binder: node %d now dead, refs %d, death %d\n", node->debug_id, incoming_refs, death);
42433 +               }
42434 +       }
42435 +       outgoing_refs = 0;
42436 +       while ((n = rb_first(&proc->refs_by_desc))) {
42437 +               struct binder_ref *ref = rb_entry(n, struct binder_ref, rb_node_desc);
42438 +               outgoing_refs++;
42439 +               binder_delete_ref(ref);
42440 +       }
42441 +       binder_release_work(&proc->todo);
42442 +       buffers = 0;
42443 +
42444 +       while ((n = rb_first(&proc->allocated_buffers))) {
42445 +               struct binder_buffer *buffer = rb_entry(n, struct binder_buffer, rb_node);
42446 +               t = buffer->transaction;
42447 +               if (t) {
42448 +                       t->buffer = NULL;
42449 +                       buffer->transaction = NULL;
42450 +                       printk(KERN_ERR "binder: release proc %d, transaction %d, not freed\n", proc->pid, t->debug_id);
42451 +                       /*BUG();*/
42452 +               }
42453 +               binder_free_buf(proc, buffer);
42454 +               buffers++;
42455 +       }
42456 +
42457 +       binder_stats.obj_deleted[BINDER_STAT_PROC]++;
42458 +       mutex_unlock(&binder_lock);
42459 +
42460 +       page_count = 0;
42461 +       if (proc->pages) {
42462 +               int i;
42463 +               for (i = 0; i < proc->buffer_size / PAGE_SIZE; i++) {
42464 +                       if (proc->pages[i]) {
42465 +                               if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
42466 +                                       printk(KERN_INFO "binder_release: %d: page %d at %p not freed\n", proc->pid, i, proc->buffer + i * PAGE_SIZE);
42467 +                               __free_page(proc->pages[i]);
42468 +                               page_count++;
42469 +                       }
42470 +               }
42471 +               kfree(proc->pages);
42472 +               vfree(proc->buffer);
42473 +       }
42474 +
42475 +       put_task_struct(proc->tsk);
42476 +
42477 +       if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
42478 +               printk(KERN_INFO "binder_release: %d threads %d, nodes %d (ref %d), refs %d, active transactions %d, buffers %d, pages %d\n",
42479 +                      proc->pid, threads, nodes, incoming_refs, outgoing_refs, active_transactions, buffers, page_count);
42480 +
42481 +       kfree(proc);
42482 +       return 0;
42483 +}
42484 +
42485 +static char *print_binder_transaction(char *buf, char *end, const char *prefix, struct binder_transaction *t)
42486 +{
42487 +       buf += snprintf(buf, end - buf, "%s %d: %p from %d:%d to %d:%d code %x flags %x pri %ld r%d",
42488 +                       prefix, t->debug_id, t, t->from ? t->from->proc->pid : 0,
42489 +                       t->from ? t->from->pid : 0,
42490 +                       t->to_proc ? t->to_proc->pid : 0,
42491 +                       t->to_thread ? t->to_thread->pid : 0,
42492 +                       t->code, t->flags, t->priority, t->need_reply);
42493 +       if (buf >= end)
42494 +               return buf;
42495 +       if (t->buffer == NULL) {
42496 +               buf += snprintf(buf, end - buf, " buffer free\n");
42497 +               return buf;
42498 +       }
42499 +       if (t->buffer->target_node) {
42500 +               buf += snprintf(buf, end - buf, " node %d",
42501 +                               t->buffer->target_node->debug_id);
42502 +               if (buf >= end)
42503 +                       return buf;
42504 +       }
42505 +       buf += snprintf(buf, end - buf, " size %d:%d data %p\n",
42506 +                       t->buffer->data_size, t->buffer->offsets_size,
42507 +                       t->buffer->data);
42508 +       return buf;
42509 +}
42510 +
42511 +static char *print_binder_buffer(char *buf, char *end, const char *prefix, struct binder_buffer *buffer)
42512 +{
42513 +       buf += snprintf(buf, end - buf, "%s %d: %p size %d:%d %s\n",
42514 +                       prefix, buffer->debug_id, buffer->data,
42515 +                       buffer->data_size, buffer->offsets_size,
42516 +                       buffer->transaction ? "active" : "delivered");
42517 +       return buf;
42518 +}
42519 +
42520 +static char *print_binder_work(char *buf, char *end, const char *prefix,
42521 +       const char *transaction_prefix, struct binder_work *w)
42522 +{
42523 +       struct binder_node *node;
42524 +       struct binder_transaction *t;
42525 +
42526 +       switch (w->type) {
42527 +       case BINDER_WORK_TRANSACTION:
42528 +               t = container_of(w, struct binder_transaction, work);
42529 +               buf = print_binder_transaction(buf, end, transaction_prefix, t);
42530 +               break;
42531 +       case BINDER_WORK_TRANSACTION_COMPLETE:
42532 +               buf += snprintf(buf, end - buf,
42533 +                               "%stransaction complete\n", prefix);
42534 +               break;
42535 +       case BINDER_WORK_NODE:
42536 +               node = container_of(w, struct binder_node, work);
42537 +               buf += snprintf(buf, end - buf, "%snode work %d: u%p c%p\n",
42538 +                               prefix, node->debug_id, node->ptr, node->cookie);
42539 +               break;
42540 +       case BINDER_WORK_DEAD_BINDER:
42541 +               buf += snprintf(buf, end - buf, "%shas dead binder\n", prefix);
42542 +               break;
42543 +       case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
42544 +               buf += snprintf(buf, end - buf,
42545 +                               "%shas cleared dead binder\n", prefix);
42546 +               break;
42547 +       case BINDER_WORK_CLEAR_DEATH_NOTIFICATION:
42548 +               buf += snprintf(buf, end - buf,
42549 +                               "%shas cleared death notification\n", prefix);
42550 +               break;
42551 +       default:
42552 +               buf += snprintf(buf, end - buf, "%sunknown work: type %d\n",
42553 +                               prefix, w->type);
42554 +               break;
42555 +       }
42556 +       return buf;
42557 +}
42558 +
42559 +static char *print_binder_thread(char *buf, char *end, struct binder_thread *thread, int print_always)
42560 +{
42561 +       struct binder_transaction *t;
42562 +       struct binder_work *w;
42563 +       char *start_buf = buf;
42564 +       char *header_buf;
42565 +
42566 +       buf += snprintf(buf, end - buf, "  thread %d: l %02x\n", thread->pid, thread->looper);
42567 +       header_buf = buf;
42568 +       t = thread->transaction_stack;
42569 +       while (t) {
42570 +               if (buf >= end)
42571 +                       break;
42572 +               if (t->from == thread) {
42573 +                       buf = print_binder_transaction(buf, end, "    outgoing transaction", t);
42574 +                       t = t->from_parent;
42575 +               } else if (t->to_thread == thread) {
42576 +                       buf = print_binder_transaction(buf, end, "    incoming transaction", t);
42577 +                       t = t->to_parent;
42578 +               } else {
42579 +                       buf = print_binder_transaction(buf, end, "    bad transaction", t);
42580 +                       t = NULL;
42581 +               }
42582 +       }
42583 +       list_for_each_entry(w, &thread->todo, entry) {
42584 +               if (buf >= end)
42585 +                       break;
42586 +               buf = print_binder_work(buf, end, "    ",
42587 +                                       "    pending transaction", w);
42588 +       }
42589 +       if (!print_always && buf == header_buf)
42590 +               buf = start_buf;
42591 +       return buf;
42592 +}
42593 +
42594 +static char *print_binder_node(char *buf, char *end, struct binder_node *node)
42595 +{
42596 +       struct binder_ref *ref;
42597 +       struct hlist_node *pos;
42598 +       struct binder_work *w;
42599 +       int count;
42600 +       count = 0;
42601 +       hlist_for_each_entry(ref, pos, &node->refs, node_entry)
42602 +               count++;
42603 +
42604 +       buf += snprintf(buf, end - buf, "  node %d: u%p c%p hs %d hw %d ls %d lw %d is %d iw %d",
42605 +                       node->debug_id, node->ptr, node->cookie,
42606 +                       node->has_strong_ref, node->has_weak_ref,
42607 +                       node->local_strong_refs, node->local_weak_refs,
42608 +                       node->internal_strong_refs, count);
42609 +       if (buf >= end)
42610 +               return buf;
42611 +       if (count) {
42612 +               buf += snprintf(buf, end - buf, " proc");
42613 +               if (buf >= end)
42614 +                       return buf;
42615 +               hlist_for_each_entry(ref, pos, &node->refs, node_entry) {
42616 +                       buf += snprintf(buf, end - buf, " %d", ref->proc->pid);
42617 +                       if (buf >= end)
42618 +                               return buf;
42619 +               }
42620 +       }
42621 +       buf += snprintf(buf, end - buf, "\n");
42622 +       list_for_each_entry(w, &node->async_todo, entry) {
42623 +               if (buf >= end)
42624 +                       break;
42625 +               buf = print_binder_work(buf, end, "    ",
42626 +                                       "    pending async transaction", w);
42627 +       }
42628 +       return buf;
42629 +}
42630 +
42631 +static char *print_binder_ref(char *buf, char *end, struct binder_ref *ref)
42632 +{
42633 +       buf += snprintf(buf, end - buf, "  ref %d: desc %d %snode %d s %d w %d d %p\n",
42634 +                       ref->debug_id, ref->desc, ref->node->proc ? "" : "dead ",
42635 +                       ref->node->debug_id, ref->strong, ref->weak, ref->death);
42636 +       return buf;
42637 +}
42638 +
42639 +static char *print_binder_proc(char *buf, char *end, struct binder_proc *proc, int print_all)
42640 +{
42641 +       struct binder_work *w;
42642 +       struct rb_node *n;
42643 +       char *start_buf = buf;
42644 +       char *header_buf;
42645 +
42646 +       buf += snprintf(buf, end - buf, "proc %d\n", proc->pid);
42647 +       header_buf = buf;
42648 +
42649 +       for (n = rb_first(&proc->threads); n != NULL && buf < end; n = rb_next(n))
42650 +               buf = print_binder_thread(buf, end, rb_entry(n, struct binder_thread, rb_node), print_all);
42651 +       for (n = rb_first(&proc->nodes); n != NULL && buf < end; n = rb_next(n)) {
42652 +               struct binder_node *node = rb_entry(n, struct binder_node, rb_node);
42653 +               if (print_all || node->has_async_transaction)
42654 +                       buf = print_binder_node(buf, end, node);
42655 +       }
42656 +       if (print_all) {
42657 +               for (n = rb_first(&proc->refs_by_desc); n != NULL && buf < end; n = rb_next(n))
42658 +                       buf = print_binder_ref(buf, end, rb_entry(n, struct binder_ref, rb_node_desc));
42659 +       }
42660 +       for (n = rb_first(&proc->allocated_buffers); n != NULL && buf < end; n = rb_next(n))
42661 +               buf = print_binder_buffer(buf, end, "  buffer", rb_entry(n, struct binder_buffer, rb_node));
42662 +       list_for_each_entry(w, &proc->todo, entry) {
42663 +               if (buf >= end)
42664 +                       break;
42665 +               buf = print_binder_work(buf, end, "  ",
42666 +                                       "  pending transaction", w);
42667 +       }
42668 +       list_for_each_entry(w, &proc->delivered_death, entry) {
42669 +               if (buf >= end)
42670 +                       break;
42671 +               buf += snprintf(buf, end - buf, "  has delivered dead binder\n");
42672 +               break;
42673 +       }
42674 +       if (!print_all && buf == header_buf)
42675 +               buf = start_buf;
42676 +       return buf;
42677 +}
42678 +
42679 +static const char *binder_return_strings[] = {
42680 +       "BR_ERROR",
42681 +       "BR_OK",
42682 +       "BR_TRANSACTION",
42683 +       "BR_REPLY",
42684 +       "BR_ACQUIRE_RESULT",
42685 +       "BR_DEAD_REPLY",
42686 +       "BR_TRANSACTION_COMPLETE",
42687 +       "BR_INCREFS",
42688 +       "BR_ACQUIRE",
42689 +       "BR_RELEASE",
42690 +       "BR_DECREFS",
42691 +       "BR_ATTEMPT_ACQUIRE",
42692 +       "BR_NOOP",
42693 +       "BR_SPAWN_LOOPER",
42694 +       "BR_FINISHED",
42695 +       "BR_DEAD_BINDER",
42696 +       "BR_CLEAR_DEATH_NOTIFICATION_DONE",
42697 +       "BR_FAILED_REPLY"
42698 +};
42699 +
42700 +static const char *binder_command_strings[] = {
42701 +       "BC_TRANSACTION",
42702 +       "BC_REPLY",
42703 +       "BC_ACQUIRE_RESULT",
42704 +       "BC_FREE_BUFFER",
42705 +       "BC_INCREFS",
42706 +       "BC_ACQUIRE",
42707 +       "BC_RELEASE",
42708 +       "BC_DECREFS",
42709 +       "BC_INCREFS_DONE",
42710 +       "BC_ACQUIRE_DONE",
42711 +       "BC_ATTEMPT_ACQUIRE",
42712 +       "BC_REGISTER_LOOPER",
42713 +       "BC_ENTER_LOOPER",
42714 +       "BC_EXIT_LOOPER",
42715 +       "BC_REQUEST_DEATH_NOTIFICATION",
42716 +       "BC_CLEAR_DEATH_NOTIFICATION",
42717 +       "BC_DEAD_BINDER_DONE"
42718 +};
42719 +
42720 +static const char *binder_objstat_strings[] = {
42721 +       "proc",
42722 +       "thread",
42723 +       "node",
42724 +       "ref",
42725 +       "death",
42726 +       "transaction",
42727 +       "transaction_complete"
42728 +};
42729 +
42730 +static char *print_binder_stats(char *buf, char *end, const char *prefix, struct binder_stats *stats)
42731 +{
42732 +       int i;
42733 +
42734 +       BUILD_BUG_ON(ARRAY_SIZE(stats->bc) != ARRAY_SIZE(binder_command_strings));
42735 +       for (i = 0; i < ARRAY_SIZE(stats->bc); i++) {
42736 +               if (stats->bc[i])
42737 +                       buf += snprintf(buf, end - buf, "%s%s: %d\n", prefix,
42738 +                                       binder_command_strings[i], stats->bc[i]);
42739 +               if (buf >= end)
42740 +                       return buf;
42741 +       }
42742 +
42743 +       BUILD_BUG_ON(ARRAY_SIZE(stats->br) != ARRAY_SIZE(binder_return_strings));
42744 +       for (i = 0; i < ARRAY_SIZE(stats->br); i++) {
42745 +               if (stats->br[i])
42746 +                       buf += snprintf(buf, end - buf, "%s%s: %d\n", prefix,
42747 +                                       binder_return_strings[i], stats->br[i]);
42748 +               if (buf >= end)
42749 +                       return buf;
42750 +       }
42751 +
42752 +       BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != ARRAY_SIZE(binder_objstat_strings));
42753 +       BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != ARRAY_SIZE(stats->obj_deleted));
42754 +       for (i = 0; i < ARRAY_SIZE(stats->obj_created); i++) {
42755 +               if (stats->obj_created[i] || stats->obj_deleted[i])
42756 +                       buf += snprintf(buf, end - buf, "%s%s: active %d total %d\n", prefix,
42757 +                                       binder_objstat_strings[i],
42758 +                                       stats->obj_created[i] - stats->obj_deleted[i],
42759 +                                       stats->obj_created[i]);
42760 +               if (buf >= end)
42761 +                       return buf;
42762 +       }
42763 +       return buf;
42764 +}
42765 +
42766 +static char *print_binder_proc_stats(char *buf, char *end, struct binder_proc *proc)
42767 +{
42768 +       struct binder_work *w;
42769 +       struct rb_node *n;
42770 +       int count, strong, weak;
42771 +
42772 +       buf += snprintf(buf, end - buf, "proc %d\n", proc->pid);
42773 +       if (buf >= end)
42774 +               return buf;
42775 +       count = 0;
42776 +       for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n))
42777 +               count++;
42778 +       buf += snprintf(buf, end - buf, "  threads: %d\n", count);
42779 +       if (buf >= end)
42780 +               return buf;
42781 +       buf += snprintf(buf, end - buf, "  requested threads: %d+%d/%d\n"
42782 +                       "  ready threads %d\n"
42783 +                       "  free async space %d\n", proc->requested_threads,
42784 +                       proc->requested_threads_started, proc->max_threads,
42785 +                       proc->ready_threads, proc->free_async_space);
42786 +       if (buf >= end)
42787 +               return buf;
42788 +       count = 0;
42789 +       for (n = rb_first(&proc->nodes); n != NULL; n = rb_next(n))
42790 +               count++;
42791 +       buf += snprintf(buf, end - buf, "  nodes: %d\n", count);
42792 +       if (buf >= end)
42793 +               return buf;
42794 +       count = 0;
42795 +       strong = 0;
42796 +       weak = 0;
42797 +       for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
42798 +               struct binder_ref *ref = rb_entry(n, struct binder_ref, rb_node_desc);
42799 +               count++;
42800 +               strong += ref->strong;
42801 +               weak += ref->weak;
42802 +       }
42803 +       buf += snprintf(buf, end - buf, "  refs: %d s %d w %d\n", count, strong, weak);
42804 +       if (buf >= end)
42805 +               return buf;
42806 +
42807 +       count = 0;
42808 +       for (n = rb_first(&proc->allocated_buffers); n != NULL; n = rb_next(n))
42809 +               count++;
42810 +       buf += snprintf(buf, end - buf, "  buffers: %d\n", count);
42811 +       if (buf >= end)
42812 +               return buf;
42813 +
42814 +       count = 0;
42815 +       list_for_each_entry(w, &proc->todo, entry) {
42816 +               switch (w->type) {
42817 +               case BINDER_WORK_TRANSACTION:
42818 +                       count++;
42819 +                       break;
42820 +               default:
42821 +                       break;
42822 +               }
42823 +       }
42824 +       buf += snprintf(buf, end - buf, "  pending transactions: %d\n", count);
42825 +       if (buf >= end)
42826 +               return buf;
42827 +
42828 +       buf = print_binder_stats(buf, end, "  ", &proc->stats);
42829 +
42830 +       return buf;
42831 +}
42832 +
42833 +
42834 +static int binder_read_proc_state(
42835 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42836 +{
42837 +       struct binder_proc *proc;
42838 +       struct hlist_node *pos;
42839 +       struct binder_node *node;
42840 +       int len = 0;
42841 +       char *buf = page;
42842 +       char *end = page + PAGE_SIZE;
42843 +       int do_lock = !binder_debug_no_lock;
42844 +
42845 +       if (off)
42846 +               return 0;
42847 +
42848 +       if (do_lock)
42849 +               mutex_lock(&binder_lock);
42850 +
42851 +       buf += snprintf(buf, end - buf, "binder state:\n");
42852 +
42853 +       if (!hlist_empty(&binder_dead_nodes))
42854 +               buf += snprintf(buf, end - buf, "dead nodes:\n");
42855 +       hlist_for_each_entry(node, pos, &binder_dead_nodes, dead_node) {
42856 +               if (buf >= end)
42857 +                       break;
42858 +               buf = print_binder_node(buf, end, node);
42859 +       }
42860 +
42861 +       hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
42862 +               if (buf >= end)
42863 +                       break;
42864 +               buf = print_binder_proc(buf, end, proc, 1);
42865 +       }
42866 +       if (do_lock)
42867 +               mutex_unlock(&binder_lock);
42868 +       if (buf > page + PAGE_SIZE)
42869 +               buf = page + PAGE_SIZE;
42870 +
42871 +       *start = page + off;
42872 +
42873 +       len = buf - page;
42874 +       if (len > off)
42875 +               len -= off;
42876 +       else
42877 +               len = 0;
42878 +
42879 +       return len < count ? len  : count;
42880 +}
42881 +
42882 +static int binder_read_proc_stats(
42883 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42884 +{
42885 +       struct binder_proc *proc;
42886 +       struct hlist_node *pos;
42887 +       int len = 0;
42888 +       char *p = page;
42889 +       int do_lock = !binder_debug_no_lock;
42890 +
42891 +       if (off)
42892 +               return 0;
42893 +
42894 +       if (do_lock)
42895 +               mutex_lock(&binder_lock);
42896 +
42897 +       p += snprintf(p, PAGE_SIZE, "binder stats:\n");
42898 +
42899 +       p = print_binder_stats(p, page + PAGE_SIZE, "", &binder_stats);
42900 +
42901 +       hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
42902 +               if (p >= page + PAGE_SIZE)
42903 +                       break;
42904 +               p = print_binder_proc_stats(p, page + PAGE_SIZE, proc);
42905 +       }
42906 +       if (do_lock)
42907 +               mutex_unlock(&binder_lock);
42908 +       if (p > page + PAGE_SIZE)
42909 +               p = page + PAGE_SIZE;
42910 +
42911 +       *start = page + off;
42912 +
42913 +       len = p - page;
42914 +       if (len > off)
42915 +               len -= off;
42916 +       else
42917 +               len = 0;
42918 +
42919 +       return len < count ? len  : count;
42920 +}
42921 +
42922 +static int binder_read_proc_transactions(
42923 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42924 +{
42925 +       struct binder_proc *proc;
42926 +       struct hlist_node *pos;
42927 +       int len = 0;
42928 +       char *buf = page;
42929 +       char *end = page + PAGE_SIZE;
42930 +       int do_lock = !binder_debug_no_lock;
42931 +
42932 +       if (off)
42933 +               return 0;
42934 +
42935 +       if (do_lock)
42936 +               mutex_lock(&binder_lock);
42937 +
42938 +       buf += snprintf(buf, end - buf, "binder transactions:\n");
42939 +       hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
42940 +               if (buf >= end)
42941 +                       break;
42942 +               buf = print_binder_proc(buf, end, proc, 0);
42943 +       }
42944 +       if (do_lock)
42945 +               mutex_unlock(&binder_lock);
42946 +       if (buf > page + PAGE_SIZE)
42947 +               buf = page + PAGE_SIZE;
42948 +
42949 +       *start = page + off;
42950 +
42951 +       len = buf - page;
42952 +       if (len > off)
42953 +               len -= off;
42954 +       else
42955 +               len = 0;
42956 +
42957 +       return len < count ? len  : count;
42958 +}
42959 +
42960 +static int binder_read_proc_proc(
42961 +       char *page, char **start, off_t off, int count, int *eof, void *data)
42962 +{
42963 +       struct binder_proc *proc = data;
42964 +       int len = 0;
42965 +       char *p = page;
42966 +       int do_lock = !binder_debug_no_lock;
42967 +
42968 +       if (off)
42969 +               return 0;
42970 +
42971 +       if (do_lock)
42972 +               mutex_lock(&binder_lock);
42973 +       p += snprintf(p, PAGE_SIZE, "binder proc state:\n");
42974 +       p = print_binder_proc(p, page + PAGE_SIZE, proc, 1);
42975 +       if (do_lock)
42976 +               mutex_unlock(&binder_lock);
42977 +
42978 +       if (p > page + PAGE_SIZE)
42979 +               p = page + PAGE_SIZE;
42980 +       *start = page + off;
42981 +
42982 +       len = p - page;
42983 +       if (len > off)
42984 +               len -= off;
42985 +       else
42986 +               len = 0;
42987 +
42988 +       return len < count ? len  : count;
42989 +}
42990 +
42991 +static char *print_binder_transaction_log_entry(char *buf, char *end, struct binder_transaction_log_entry *e)
42992 +{
42993 +       buf += snprintf(buf, end - buf, "%d: %s from %d:%d to %d:%d node %d handle %d size %d:%d\n",
42994 +                       e->debug_id, (e->call_type == 2) ? "reply" :
42995 +                       ((e->call_type == 1) ? "async" : "call "), e->from_proc,
42996 +                       e->from_thread, e->to_proc, e->to_thread, e->to_node,
42997 +                       e->target_handle, e->data_size, e->offsets_size);
42998 +       return buf;
42999 +}
43000 +
43001 +static int binder_read_proc_transaction_log(
43002 +       char *page, char **start, off_t off, int count, int *eof, void *data)
43003 +{
43004 +       struct binder_transaction_log *log = data;
43005 +       int len = 0;
43006 +       int i;
43007 +       char *buf = page;
43008 +       char *end = page + PAGE_SIZE;
43009 +
43010 +       if (off)
43011 +               return 0;
43012 +
43013 +       if (log->full) {
43014 +               for (i = log->next; i < ARRAY_SIZE(log->entry); i++) {
43015 +                       if (buf >= end)
43016 +                               break;
43017 +                       buf = print_binder_transaction_log_entry(buf, end, &log->entry[i]);
43018 +               }
43019 +       }
43020 +       for (i = 0; i < log->next; i++) {
43021 +               if (buf >= end)
43022 +                       break;
43023 +               buf = print_binder_transaction_log_entry(buf, end, &log->entry[i]);
43024 +       }
43025 +
43026 +       *start = page + off;
43027 +
43028 +       len = buf - page;
43029 +       if (len > off)
43030 +               len -= off;
43031 +       else
43032 +               len = 0;
43033 +
43034 +       return len < count ? len  : count;
43035 +}
43036 +
43037 +static struct file_operations binder_fops = {
43038 +       .owner = THIS_MODULE,
43039 +       .poll = binder_poll,
43040 +       .unlocked_ioctl = binder_ioctl,
43041 +       .mmap = binder_mmap,
43042 +       .open = binder_open,
43043 +       .flush = binder_flush,
43044 +       .release = binder_release,
43045 +};
43046 +
43047 +static struct miscdevice binder_miscdev = {
43048 +       .minor = MISC_DYNAMIC_MINOR,
43049 +       .name = "binder",
43050 +       .fops = &binder_fops
43051 +};
43052 +
43053 +static int __init binder_init(void)
43054 +{
43055 +       int ret;
43056 +
43057 +       binder_proc_dir_entry_root = proc_mkdir("binder", NULL);
43058 +       if (binder_proc_dir_entry_root)
43059 +               binder_proc_dir_entry_proc = proc_mkdir("proc", binder_proc_dir_entry_root);
43060 +       ret = misc_register(&binder_miscdev);
43061 +       if (binder_proc_dir_entry_root) {
43062 +               create_proc_read_entry("state", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_state, NULL);
43063 +               create_proc_read_entry("stats", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_stats, NULL);
43064 +               create_proc_read_entry("transactions", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transactions, NULL);
43065 +               create_proc_read_entry("transaction_log", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transaction_log, &binder_transaction_log);
43066 +               create_proc_read_entry("failed_transaction_log", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transaction_log, &binder_transaction_log_failed);
43067 +       }
43068 +       return ret;
43069 +}
43070 +
43071 +device_initcall(binder_init);
43072 +
43073 Index: linux-2.6.28/drivers/android/Kconfig
43074 ===================================================================
43075 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
43076 +++ linux-2.6.28/drivers/android/Kconfig        2009-01-02 00:01:56.000000000 +0100
43077 @@ -0,0 +1,93 @@
43078 +menu "Android"
43079 +
43080 +config ANDROID_BINDER_IPC
43081 +       tristate "Binder IPC Driver"
43082 +       default y
43083 +
43084 +config ANDROID_POWER
43085 +       bool "Android power driver"
43086 +       depends on PM && RTC_CLASS
43087 +       default n
43088 +
43089 +config ANDROID_POWER_STAT
43090 +       bool "Android power driver lock stats"
43091 +       depends on ANDROID_POWER
43092 +       default y
43093 +
43094 +config ANDROID_POWER_ALARM
43095 +       bool "Android alarm driver"
43096 +       depends on ANDROID_POWER
43097 +       default y
43098 +
43099 +config ANDROID_LOGGER
43100 +       bool "Android log driver"
43101 +       default y
43102 +
43103 +config ANDROID_RAM_CONSOLE
43104 +       bool "RAM buffer console"
43105 +       default n
43106 +
43107 +config ANDROID_RAM_CONSOLE_ENABLE_VERBOSE
43108 +       bool "Enable verbose console messages"
43109 +       default y
43110 +       depends on ANDROID_RAM_CONSOLE
43111 +
43112 +menuconfig ANDROID_RAM_CONSOLE_ERROR_CORRECTION
43113 +       bool "Enable error correction"
43114 +       default n
43115 +       depends on ANDROID_RAM_CONSOLE
43116 +       select REED_SOLOMON
43117 +       select REED_SOLOMON_ENC8
43118 +       select REED_SOLOMON_DEC8
43119 +
43120 +if ANDROID_RAM_CONSOLE_ERROR_CORRECTION
43121 +
43122 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE
43123 +       int "Data data size"
43124 +       default 128
43125 +       help
43126 +         Must be a power of 2.
43127 +
43128 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE
43129 +       int "ECC size"
43130 +       default 16
43131 +
43132 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE
43133 +       int "Symbol size"
43134 +       default 8
43135 +
43136 +config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL
43137 +       hex "Polynomial"
43138 +       default 0x19 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 4)
43139 +       default 0x29 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 5)
43140 +       default 0x61 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 6)
43141 +       default 0x89 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 7)
43142 +       default 0x11d if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 8)
43143 +
43144 +endif #ANDROID_RAM_CONSOLE_ERROR_CORRECTION
43145 +
43146 +config ANDROID_RAM_CONSOLE_EARLY_INIT
43147 +       bool "Start ram console early"
43148 +       default n
43149 +       depends on ANDROID_RAM_CONSOLE
43150 +
43151 +config ANDROID_RAM_CONSOLE_EARLY_ADDR
43152 +       hex "RAM console virtual address"
43153 +       default 0
43154 +       depends on ANDROID_RAM_CONSOLE_EARLY_INIT
43155 +
43156 +config ANDROID_RAM_CONSOLE_EARLY_SIZE
43157 +       hex "RAM console buffer size"
43158 +       default 0
43159 +       depends on ANDROID_RAM_CONSOLE_EARLY_INIT
43160 +
43161 +config ANDROID_TIMED_GPIO
43162 +       bool "Android timed gpio driver"
43163 +       depends on GENERIC_GPIO
43164 +       default y
43165 +
43166 +config ANDROID_PARANOID_NETWORK
43167 +       bool "Only allow certain groups to create sockets"
43168 +       default y
43169 +
43170 +endmenu
43171 Index: linux-2.6.28/drivers/android/logger.c
43172 ===================================================================
43173 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
43174 +++ linux-2.6.28/drivers/android/logger.c       2009-01-02 00:01:56.000000000 +0100
43175 @@ -0,0 +1,607 @@
43176 +/*
43177 + * drivers/android/logger.c
43178 + *
43179 + * Android Logging Subsystem
43180 + *
43181 + * Copyright (C) 2007-2008 Google, Inc.
43182 + *
43183 + * Robert Love <rlove@google.com>
43184 + *
43185 + * This software is licensed under the terms of the GNU General Public
43186 + * License version 2, as published by the Free Software Foundation, and
43187 + * may be copied, distributed, and modified under those terms.
43188 + *
43189 + * This program is distributed in the hope that it will be useful,
43190 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
43191 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
43192 + * GNU General Public License for more details.
43193 + */
43194 +
43195 +#include <linux/module.h>
43196 +#include <linux/fs.h>
43197 +#include <linux/miscdevice.h>
43198 +#include <linux/uaccess.h>
43199 +#include <linux/poll.h>
43200 +#include <linux/time.h>
43201 +#include <linux/logger.h>
43202 +
43203 +#include <asm/ioctls.h>
43204 +
43205 +/*
43206 + * struct logger_log - represents a specific log, such as 'main' or 'radio'
43207 + *
43208 + * This structure lives from module insertion until module removal, so it does
43209 + * not need additional reference counting. The structure is protected by the
43210 + * mutex 'mutex'.
43211 + */
43212 +struct logger_log {
43213 +       unsigned char *         buffer; /* the ring buffer itself */
43214 +       struct miscdevice       misc;   /* misc device representing the log */
43215 +       wait_queue_head_t       wq;     /* wait queue for readers */
43216 +       struct list_head        readers; /* this log's readers */
43217 +       struct mutex            mutex;  /* mutex protecting buffer */
43218 +       size_t                  w_off;  /* current write head offset */
43219 +       size_t                  head;   /* new readers start here */
43220 +       size_t                  size;   /* size of the log */
43221 +};
43222 +
43223 +/*
43224 + * struct logger_reader - a logging device open for reading
43225 + *
43226 + * This object lives from open to release, so we don't need additional
43227 + * reference counting. The structure is protected by log->mutex.
43228 + */
43229 +struct logger_reader {
43230 +       struct logger_log *     log;    /* associated log */
43231 +       struct list_head        list;   /* entry in logger_log's list */
43232 +       size_t                  r_off;  /* current read head offset */
43233 +};
43234 +
43235 +/* logger_offset - returns index 'n' into the log via (optimized) modulus */
43236 +#define logger_offset(n)       ((n) & (log->size - 1))
43237 +
43238 +/*
43239 + * file_get_log - Given a file structure, return the associated log
43240 + *
43241 + * This isn't aesthetic. We have several goals:
43242 + *
43243 + *     1) Need to quickly obtain the associated log during an I/O operation
43244 + *     2) Readers need to maintain state (logger_reader)
43245 + *     3) Writers need to be very fast (open() should be a near no-op)
43246 + *
43247 + * In the reader case, we can trivially go file->logger_reader->logger_log.
43248 + * For a writer, we don't want to maintain a logger_reader, so we just go
43249 + * file->logger_log. Thus what file->private_data points at depends on whether
43250 + * or not the file was opened for reading. This function hides that dirtiness.
43251 + */
43252 +static inline struct logger_log * file_get_log(struct file *file)
43253 +{
43254 +       if (file->f_mode & FMODE_READ) {
43255 +               struct logger_reader *reader = file->private_data;
43256 +               return reader->log;
43257 +       } else
43258 +               return file->private_data;
43259 +}
43260 +
43261 +/*
43262 + * get_entry_len - Grabs the length of the payload of the next entry starting
43263 + * from 'off'.
43264 + *
43265 + * Caller needs to hold log->mutex.
43266 + */
43267 +static __u32 get_entry_len(struct logger_log *log, size_t off)
43268 +{
43269 +       __u16 val;
43270 +
43271 +       switch (log->size - off) {
43272 +       case 1:
43273 +               memcpy(&val, log->buffer + off, 1);
43274 +               memcpy(((char *) &val) + 1, log->buffer, 1);
43275 +               break;
43276 +       default:
43277 +               memcpy(&val, log->buffer + off, 2);
43278 +       }
43279 +
43280 +       return sizeof(struct logger_entry) + val;
43281 +}
43282 +
43283 +/*
43284 + * do_read_log_to_user - reads exactly 'count' bytes from 'log' into the
43285 + * user-space buffer 'buf'. Returns 'count' on success.
43286 + *
43287 + * Caller must hold log->mutex.
43288 + */
43289 +static ssize_t do_read_log_to_user(struct logger_log *log,
43290 +                                  struct logger_reader *reader,
43291 +                                  char __user *buf,
43292 +                                  size_t count)
43293 +{
43294 +       size_t len;
43295 +
43296 +       /*
43297 +        * We read from the log in two disjoint operations. First, we read from
43298 +        * the current read head offset up to 'count' bytes or to the end of
43299 +        * the log, whichever comes first.
43300 +        */
43301 +       len = min(count, log->size - reader->r_off);
43302 +       if (copy_to_user(buf, log->buffer + reader->r_off, len))
43303 +               return -EFAULT;
43304 +
43305 +       /*
43306 +        * Second, we read any remaining bytes, starting back at the head of
43307 +        * the log.
43308 +        */
43309 +       if (count != len)
43310 +               if (copy_to_user(buf + len, log->buffer, count - len))
43311 +                       return -EFAULT;
43312 +
43313 +       reader->r_off = logger_offset(reader->r_off + count);
43314 +
43315 +       return count;
43316 +}
43317 +
43318 +/*
43319 + * logger_read - our log's read() method
43320 + *
43321 + * Behavior:
43322 + *
43323 + *     - O_NONBLOCK works
43324 + *     - If there are no log entries to read, blocks until log is written to
43325 + *     - Atomically reads exactly one log entry
43326 + *
43327 + * Optimal read size is LOGGER_ENTRY_MAX_LEN. Will set errno to EINVAL if read
43328 + * buffer is insufficient to hold next entry.
43329 + */
43330 +static ssize_t logger_read(struct file *file, char __user *buf,
43331 +                          size_t count, loff_t *pos)
43332 +{
43333 +       struct logger_reader *reader = file->private_data;
43334 +       struct logger_log *log = reader->log;
43335 +       ssize_t ret;
43336 +       DEFINE_WAIT(wait);
43337 +
43338 +start:
43339 +       while (1) {
43340 +               prepare_to_wait(&log->wq, &wait, TASK_INTERRUPTIBLE);
43341 +
43342 +               mutex_lock(&log->mutex);
43343 +               ret = (log->w_off == reader->r_off);
43344 +               mutex_unlock(&log->mutex);
43345 +               if (!ret)
43346 +                       break;
43347 +
43348 +               if (file->f_flags & O_NONBLOCK) {
43349 +                       ret = -EAGAIN;
43350 +                       break;
43351 +               }
43352 +
43353 +               if (signal_pending(current)) {
43354 +                       ret = -EINTR;
43355 +                       break;
43356 +               }
43357 +
43358 +               schedule();
43359 +       }
43360 +
43361 +       finish_wait(&log->wq, &wait);
43362 +       if (ret)
43363 +               return ret;
43364 +
43365 +       mutex_lock(&log->mutex);
43366 +
43367 +       /* is there still something to read or did we race? */
43368 +       if (unlikely(log->w_off == reader->r_off)) {
43369 +               mutex_unlock(&log->mutex);
43370 +               goto start;
43371 +       }
43372 +
43373 +       /* get the size of the next entry */
43374 +       ret = get_entry_len(log, reader->r_off);
43375 +       if (count < ret) {
43376 +               ret = -EINVAL;
43377 +               goto out;
43378 +       }
43379 +
43380 +       /* get exactly one entry from the log */
43381 +       ret = do_read_log_to_user(log, reader, buf, ret);
43382 +
43383 +out:
43384 +       mutex_unlock(&log->mutex);
43385 +
43386 +       return ret;
43387 +}
43388 +
43389 +/*
43390 + * get_next_entry - return the offset of the first valid entry at least 'len'
43391 + * bytes after 'off'.
43392 + *
43393 + * Caller must hold log->mutex.
43394 + */
43395 +static size_t get_next_entry(struct logger_log *log, size_t off, size_t len)
43396 +{
43397 +       size_t count = 0;
43398 +
43399 +       do {
43400 +               size_t nr = get_entry_len(log, off);
43401 +               off = logger_offset(off + nr);
43402 +               count += nr;
43403 +       } while (count < len);
43404 +
43405 +       return off;
43406 +}
43407 +
43408 +/*
43409 + * clock_interval - is a < c < b in mod-space? Put another way, does the line
43410 + * from a to b cross c?
43411 + */
43412 +static inline int clock_interval(size_t a, size_t b, size_t c)
43413 +{
43414 +       if (b < a) {
43415 +               if (a < c || b >= c)
43416 +                       return 1;
43417 +       } else {
43418 +               if (a < c && b >= c)
43419 +                       return 1;
43420 +       }
43421 +
43422 +       return 0;
43423 +}
43424 +
43425 +/*
43426 + * fix_up_readers - walk the list of all readers and "fix up" any who were
43427 + * lapped by the writer; also do the same for the default "start head".
43428 + * We do this by "pulling forward" the readers and start head to the first
43429 + * entry after the new write head.
43430 + *
43431 + * The caller needs to hold log->mutex.
43432 + */
43433 +static void fix_up_readers(struct logger_log *log, size_t len)
43434 +{
43435 +       size_t old = log->w_off;
43436 +       size_t new = logger_offset(old + len);
43437 +       struct logger_reader *reader;
43438 +
43439 +       if (clock_interval(old, new, log->head))
43440 +               log->head = get_next_entry(log, log->head, len);
43441 +
43442 +       list_for_each_entry(reader, &log->readers, list)
43443 +               if (clock_interval(old, new, reader->r_off))
43444 +                       reader->r_off = get_next_entry(log, reader->r_off, len);
43445 +}
43446 +
43447 +/*
43448 + * do_write_log - writes 'len' bytes from 'buf' to 'log'
43449 + *
43450 + * The caller needs to hold log->mutex.
43451 + */
43452 +static void do_write_log(struct logger_log *log, const void *buf, size_t count)
43453 +{
43454 +       size_t len;
43455 +
43456 +       len = min(count, log->size - log->w_off);
43457 +       memcpy(log->buffer + log->w_off, buf, len);
43458 +
43459 +       if (count != len)
43460 +               memcpy(log->buffer, buf + len, count - len);
43461 +
43462 +       log->w_off = logger_offset(log->w_off + count);
43463 +
43464 +}
43465 +
43466 +/*
43467 + * do_write_log_user - writes 'len' bytes from the user-space buffer 'buf' to
43468 + * the log 'log'
43469 + *
43470 + * The caller needs to hold log->mutex.
43471 + *
43472 + * Returns 'count' on success, negative error code on failure.
43473 + */
43474 +static ssize_t do_write_log_from_user(struct logger_log *log,
43475 +                                     const void __user *buf, size_t count)
43476 +{
43477 +       size_t len;
43478 +
43479 +       len = min(count, log->size - log->w_off);
43480 +       if (len && copy_from_user(log->buffer + log->w_off, buf, len))
43481 +               return -EFAULT;
43482 +
43483 +       if (count != len)
43484 +               if (copy_from_user(log->buffer, buf + len, count - len))
43485 +                       return -EFAULT;
43486 +
43487 +       log->w_off = logger_offset(log->w_off + count);
43488 +
43489 +       return count;
43490 +}
43491 +
43492 +/*
43493 + * logger_aio_write - our write method, implementing support for write(),
43494 + * writev(), and aio_write(). Writes are our fast path, and we try to optimize
43495 + * them above all else.
43496 + */
43497 +ssize_t logger_aio_write(struct kiocb *iocb, const struct iovec *iov,
43498 +                        unsigned long nr_segs, loff_t ppos)
43499 +{
43500 +       struct logger_log *log = file_get_log(iocb->ki_filp);
43501 +       size_t orig = log->w_off;
43502 +       struct logger_entry header;
43503 +       struct timespec now;
43504 +       ssize_t ret = 0;
43505 +
43506 +       now = current_kernel_time();
43507 +
43508 +       header.pid = current->tgid;
43509 +       header.tid = current->pid;
43510 +       header.sec = now.tv_sec;
43511 +       header.nsec = now.tv_nsec;
43512 +       header.len = min_t(size_t, iocb->ki_left, LOGGER_ENTRY_MAX_PAYLOAD);
43513 +
43514 +       /* null writes succeed, return zero */
43515 +       if (unlikely(!header.len))
43516 +               return 0;
43517 +
43518 +       mutex_lock(&log->mutex);
43519 +
43520 +       /*
43521 +        * Fix up any readers, pulling them forward to the first readable
43522 +        * entry after (what will be) the new write offset. We do this now
43523 +        * because if we partially fail, we can end up with clobbered log
43524 +        * entries that encroach on readable buffer.
43525 +        */
43526 +       fix_up_readers(log, sizeof(struct logger_entry) + header.len);
43527 +
43528 +       do_write_log(log, &header, sizeof(struct logger_entry));
43529 +
43530 +       while (nr_segs-- > 0) {
43531 +               size_t len;
43532 +               ssize_t nr;
43533 +
43534 +               /* figure out how much of this vector we can keep */
43535 +               len = min_t(size_t, iov->iov_len, header.len - ret);
43536 +
43537 +               /* write out this segment's payload */
43538 +               nr = do_write_log_from_user(log, iov->iov_base, len);
43539 +               if (unlikely(nr < 0)) {
43540 +                       log->w_off = orig;
43541 +                       mutex_unlock(&log->mutex);
43542 +                       return nr;
43543 +               }
43544 +
43545 +               iov++;
43546 +               ret += nr;
43547 +       }
43548 +
43549 +       mutex_unlock(&log->mutex);
43550 +
43551 +       /* wake up any blocked readers */
43552 +       wake_up_interruptible(&log->wq);
43553 +
43554 +       return ret;
43555 +}
43556 +
43557 +static struct logger_log * get_log_from_minor(int);
43558 +
43559 +/*
43560 + * logger_open - the log's open() file operation
43561 + *
43562 + * Note how near a no-op this is in the write-only case. Keep it that way!
43563 + */
43564 +static int logger_open(struct inode *inode, struct file *file)
43565 +{
43566 +       struct logger_log *log;
43567 +       int ret;
43568 +
43569 +       ret = nonseekable_open(inode, file);
43570 +       if (ret)
43571 +               return ret;
43572 +
43573 +       log = get_log_from_minor(MINOR(inode->i_rdev));
43574 +       if (!log)
43575 +               return -ENODEV;
43576 +
43577 +       if (file->f_mode & FMODE_READ) {
43578 +               struct logger_reader *reader;
43579 +
43580 +               reader = kmalloc(sizeof(struct logger_reader), GFP_KERNEL);
43581 +               if (!reader)
43582 +                       return -ENOMEM;
43583 +
43584 +               reader->log = log;
43585 +               INIT_LIST_HEAD(&reader->list);
43586 +
43587 +               mutex_lock(&log->mutex);
43588 +               reader->r_off = log->head;
43589 +               list_add_tail(&reader->list, &log->readers);
43590 +               mutex_unlock(&log->mutex);
43591 +
43592 +               file->private_data = reader;
43593 +       } else
43594 +               file->private_data = log;
43595 +
43596 +       return 0;
43597 +}
43598 +
43599 +/*
43600 + * logger_release - the log's release file operation
43601 + *
43602 + * Note this is a total no-op in the write-only case. Keep it that way!
43603 + */
43604 +static int logger_release(struct inode *ignored, struct file *file)
43605 +{
43606 +       if (file->f_mode & FMODE_READ) {
43607 +               struct logger_reader *reader = file->private_data;
43608 +               list_del(&reader->list);
43609 +               kfree(reader);
43610 +       }
43611 +
43612 +       return 0;
43613 +}
43614 +
43615 +/*
43616 + * logger_poll - the log's poll file operation, for poll/select/epoll
43617 + *
43618 + * Note we always return POLLOUT, because you can always write() to the log.
43619 + * Note also that, strictly speaking, a return value of POLLIN does not
43620 + * guarantee that the log is readable without blocking, as there is a small
43621 + * chance that the writer can lap the reader in the interim between poll()
43622 + * returning and the read() request.
43623 + */
43624 +static unsigned int logger_poll(struct file *file, poll_table *wait)
43625 +{
43626 +       struct logger_reader *reader;
43627 +       struct logger_log *log;
43628 +       unsigned int ret = POLLOUT | POLLWRNORM;
43629 +
43630 +       if (!(file->f_mode & FMODE_READ))
43631 +               return ret;
43632 +
43633 +       reader = file->private_data;
43634 +       log = reader->log;
43635 +
43636 +       poll_wait(file, &log->wq, wait);
43637 +
43638 +       mutex_lock(&log->mutex);
43639 +       if (log->w_off != reader->r_off)
43640 +               ret |= POLLIN | POLLRDNORM;
43641 +       mutex_unlock(&log->mutex);
43642 +
43643 +       return ret;
43644 +}
43645 +
43646 +static long logger_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
43647 +{
43648 +       struct logger_log *log = file_get_log(file);
43649 +       struct logger_reader *reader;
43650 +       long ret = -ENOTTY;
43651 +
43652 +       mutex_lock(&log->mutex);
43653 +
43654 +       switch (cmd) {
43655 +       case LOGGER_GET_LOG_BUF_SIZE:
43656 +               ret = log->size;
43657 +               break;
43658 +       case LOGGER_GET_LOG_LEN:
43659 +               if (!(file->f_mode & FMODE_READ)) {
43660 +                       ret = -EBADF;
43661 +                       break;
43662 +               }
43663 +               reader = file->private_data;
43664 +               if (log->w_off >= reader->r_off)
43665 +                       ret = log->w_off - reader->r_off;
43666 +               else
43667 +                       ret = (log->size - reader->r_off) + log->w_off;
43668 +               break;
43669 +       case LOGGER_GET_NEXT_ENTRY_LEN:
43670 +               if (!(file->f_mode & FMODE_READ)) {
43671 +                       ret = -EBADF;
43672 +                       break;
43673 +               }
43674 +               reader = file->private_data;
43675 +               if (log->w_off != reader->r_off)
43676 +                       ret = get_entry_len(log, reader->r_off);
43677 +               else
43678 +                       ret = 0;
43679 +               break;
43680 +       case LOGGER_FLUSH_LOG:
43681 +               if (!(file->f_mode & FMODE_WRITE)) {
43682 +                       ret = -EBADF;
43683 +                       break;
43684 +               }
43685 +               list_for_each_entry(reader, &log->readers, list)
43686 +                       reader->r_off = log->w_off;
43687 +               log->head = log->w_off;
43688 +               ret = 0;
43689 +               break;
43690 +       }
43691 +
43692 +       mutex_unlock(&log->mutex);
43693 +
43694 +       return ret;
43695 +}
43696 +
43697 +static struct file_operations logger_fops = {
43698 +       .owner = THIS_MODULE,
43699 +       .read = logger_read,
43700 +       .aio_write = logger_aio_write,
43701 +       .poll = logger_poll,
43702 +       .unlocked_ioctl = logger_ioctl,
43703 +       .compat_ioctl = logger_ioctl,
43704 +       .open = logger_open,
43705 +       .release = logger_release,
43706 +};
43707 +
43708 +/*
43709 + * Defines a log structure with name 'NAME' and a size of 'SIZE' bytes, which
43710 + * must be a power of two, greater than LOGGER_ENTRY_MAX_LEN, and less than
43711 + * LONG_MAX minus LOGGER_ENTRY_MAX_LEN.
43712 + */
43713 +#define DEFINE_LOGGER_DEVICE(VAR, NAME, SIZE) \
43714 +static unsigned char _buf_ ## VAR[SIZE]; \
43715 +static struct logger_log VAR = { \
43716 +       .buffer = _buf_ ## VAR, \
43717 +       .misc = { \
43718 +               .minor = MISC_DYNAMIC_MINOR, \
43719 +               .name = NAME, \
43720 +               .fops = &logger_fops, \
43721 +               .parent = NULL, \
43722 +       }, \
43723 +       .wq = __WAIT_QUEUE_HEAD_INITIALIZER(VAR .wq), \
43724 +       .readers = LIST_HEAD_INIT(VAR .readers), \
43725 +       .mutex = __MUTEX_INITIALIZER(VAR .mutex), \
43726 +       .w_off = 0, \
43727 +       .head = 0, \
43728 +       .size = SIZE, \
43729 +};
43730 +
43731 +DEFINE_LOGGER_DEVICE(log_main, LOGGER_LOG_MAIN, 64*1024)
43732 +DEFINE_LOGGER_DEVICE(log_events, LOGGER_LOG_EVENTS, 256*1024)
43733 +DEFINE_LOGGER_DEVICE(log_radio, LOGGER_LOG_RADIO, 64*1024)
43734 +
43735 +static struct logger_log * get_log_from_minor(int minor)
43736 +{
43737 +       if (log_main.misc.minor == minor)
43738 +               return &log_main;
43739 +       if (log_events.misc.minor == minor)
43740 +               return &log_events;
43741 +       if (log_radio.misc.minor == minor)
43742 +               return &log_radio;
43743 +       return NULL;
43744 +}
43745 +
43746 +static int __init init_log(struct logger_log *log)
43747 +{
43748 +       int ret;
43749 +
43750 +       ret = misc_register(&log->misc);
43751 +       if (unlikely(ret)) {
43752 +               printk(KERN_ERR "logger: failed to register misc "
43753 +                      "device for log '%s'!\n", log->misc.name);
43754 +               return ret;
43755 +       }
43756 +
43757 +       printk(KERN_INFO "logger: created %luK log '%s'\n",
43758 +              (unsigned long) log->size >> 10, log->misc.name);
43759 +
43760 +       return 0;
43761 +}
43762 +
43763 +static int __init logger_init(void)
43764 +{
43765 +       int ret;
43766 +
43767 +       ret = init_log(&log_main);
43768 +       if (unlikely(ret))
43769 +               goto out;
43770 +
43771 +       ret = init_log(&log_events);
43772 +       if (unlikely(ret))
43773 +               goto out;
43774 +
43775 +       ret = init_log(&log_radio);
43776 +       if (unlikely(ret))
43777 +               goto out;
43778 +
43779 +out:
43780 +       return ret;
43781 +}
43782 +device_initcall(logger_init);
43783 Index: linux-2.6.28/drivers/android/Makefile
43784 ===================================================================
43785 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
43786 +++ linux-2.6.28/drivers/android/Makefile       2009-01-02 00:01:56.000000000 +0100
43787 @@ -0,0 +1,6 @@
43788 +obj-$(CONFIG_ANDROID_BINDER_IPC)       += binder.o
43789 +obj-$(CONFIG_ANDROID_POWER)            += power.o
43790 +obj-$(CONFIG_ANDROID_POWER_ALARM)              += alarm.o
43791 +obj-$(CONFIG_ANDROID_LOGGER)           += logger.o
43792 +obj-$(CONFIG_ANDROID_RAM_CONSOLE)      += ram_console.o
43793 +obj-$(CONFIG_ANDROID_TIMED_GPIO)       += timed_gpio.o
43794 Index: linux-2.6.28/drivers/android/power.c
43795 ===================================================================
43796 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
43797 +++ linux-2.6.28/drivers/android/power.c        2009-01-02 00:01:56.000000000 +0100
43798 @@ -0,0 +1,1336 @@
43799 +/* drivers/android/power.c
43800 + *
43801 + * Copyright (C) 2005-2008 Google, Inc.
43802 + *
43803 + * This software is licensed under the terms of the GNU General Public
43804 + * License version 2, as published by the Free Software Foundation, and
43805 + * may be copied, distributed, and modified under those terms.
43806 + *
43807 + * This program is distributed in the hope that it will be useful,
43808 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
43809 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
43810 + * GNU General Public License for more details.
43811 + *
43812 + */
43813 +
43814 +#include <linux/list.h>
43815 +#include <linux/module.h>
43816 +#include <linux/miscdevice.h>
43817 +//#include <linux/platform_device.h>
43818 +#include <linux/sysdev.h>
43819 +#include <linux/fs.h>
43820 +#include <linux/poll.h>
43821 +#include <linux/interrupt.h>
43822 +#include <linux/delay.h>
43823 +#include <linux/clk.h>
43824 +#include <linux/rtc.h>
43825 +#include <linux/wait.h>
43826 +#include <linux/android_power.h>
43827 +#include <linux/suspend.h>
43828 +#include <linux/syscalls.h> // sys_sync
43829 +#include <linux/console.h>
43830 +#include <linux/kbd_kern.h>
43831 +#include <linux/vt_kern.h>
43832 +#include <linux/freezer.h>
43833 +#ifdef CONFIG_ANDROID_POWER_STAT
43834 +#include <linux/proc_fs.h>
43835 +#endif
43836 +
43837 +enum {
43838 +       ANDROID_POWER_DEBUG_USER_STATE = 1U << 0,
43839 +       ANDROID_POWER_DEBUG_EXIT_SUSPEND = 1U << 1,
43840 +       ANDROID_POWER_DEBUG_SUSPEND = 1U << 2,
43841 +       ANDROID_POWER_DEBUG_USER_WAKE_LOCK = 1U << 3,
43842 +       ANDROID_POWER_DEBUG_WAKE_LOCK = 1U << 4,
43843 +};
43844 +static int android_power_debug_mask =
43845 +       ANDROID_POWER_DEBUG_USER_STATE | ANDROID_POWER_DEBUG_EXIT_SUSPEND;
43846 +module_param_named(debug_mask, android_power_debug_mask,
43847 +                       int, S_IRUGO | S_IWUSR | S_IWGRP);
43848 +
43849 +#define ANDROID_POWER_TEST_EARLY_SUSPEND 0
43850 +
43851 +MODULE_DESCRIPTION("OMAP CSMI Driver");
43852 +MODULE_LICENSE("GPL");
43853 +MODULE_VERSION("1.0");
43854 +
43855 +#define ANDROID_SUSPEND_CONSOLE        (MAX_NR_CONSOLES-2)
43856 +
43857 +static spinlock_t g_list_lock = SPIN_LOCK_UNLOCKED;
43858 +static DEFINE_MUTEX(g_early_suspend_lock);
43859 +
43860 +wait_queue_head_t g_wait_queue;
43861 +
43862 +static LIST_HEAD(g_inactive_locks);
43863 +static LIST_HEAD(g_active_idle_wake_locks);
43864 +static LIST_HEAD(g_active_partial_wake_locks);
43865 +static LIST_HEAD(g_active_full_wake_locks);
43866 +static LIST_HEAD(g_early_suspend_handlers);
43867 +static enum {
43868 +       USER_AWAKE,
43869 +       USER_NOTIFICATION,
43870 +       USER_SLEEP
43871 +} g_user_suspend_state;
43872 +static int g_current_event_num;
43873 +static struct workqueue_struct *g_suspend_work_queue;
43874 +static void android_power_suspend(struct work_struct *work);
43875 +static void android_power_wakeup_locked(int notification, ktime_t time);
43876 +static DECLARE_WORK(g_suspend_work, android_power_suspend);
43877 +static int g_max_user_lockouts = 16;
43878 +
43879 +//static const char g_free_user_lockout_name[] = "free_user";
43880 +static struct {
43881 +       enum {
43882 +               USER_WAKE_LOCK_INACTIVE,
43883 +               USER_WAKE_LOCK_PARTIAL,
43884 +               USER_WAKE_LOCK_FULL
43885 +       }                       state;
43886 +       android_suspend_lock_t  suspend_lock;
43887 +       char                    name_buffer[32];
43888 +} *g_user_wake_locks;
43889 +#ifdef CONFIG_ANDROID_POWER_STAT
43890 +android_suspend_lock_t g_deleted_wake_locks;
43891 +android_suspend_lock_t g_no_wake_locks;
43892 +#endif
43893 +static struct kobject *android_power_kobj;
43894 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
43895 +static wait_queue_head_t fb_state_wq;
43896 +static spinlock_t fb_state_lock = SPIN_LOCK_UNLOCKED;
43897 +int fb_state;
43898 +#endif
43899 +
43900 +#if 0
43901 +android_suspend_lock_t *android_allocate_suspend_lock(const char *debug_name)
43902 +{
43903 +       unsigned long irqflags;
43904 +       struct android_power *e;
43905 +
43906 +       e = kzalloc(sizeof(*e), GFP_KERNEL);
43907 +       if(e == NULL) {
43908 +               printk("android_power_allocate: kzalloc failed\n");
43909 +               return NULL;
43910 +       }
43911 +       e->name = debug_name;
43912 +       spin_lock_irqsave(&g_list_lock, irqflags);
43913 +       list_add(&e->link, &g_allocated);
43914 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43915 +       return e;
43916 +}
43917 +#endif
43918 +
43919 +static int android_init_suspend_lock_internal(
43920 +       android_suspend_lock_t *lock, int has_spin_lock)
43921 +{
43922 +       unsigned long irqflags;
43923 +
43924 +       if(lock->name == NULL) {
43925 +               printk(KERN_ERR "android_init_suspend_lock: error name=NULL, "
43926 +                       "lock=%p\n", lock);
43927 +               dump_stack();
43928 +               return -EINVAL;
43929 +       }
43930 +
43931 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43932 +               printk(KERN_INFO "android_init_suspend_lock name=%s\n",
43933 +                       lock->name);
43934 +#ifdef CONFIG_ANDROID_POWER_STAT
43935 +       lock->stat.count = 0;
43936 +       lock->stat.expire_count = 0;
43937 +       lock->stat.total_time = ktime_set(0, 0);
43938 +       lock->stat.max_time = ktime_set(0, 0);
43939 +       lock->stat.last_time = ktime_set(0, 0);
43940 +#endif
43941 +       lock->flags = 0;
43942 +
43943 +       INIT_LIST_HEAD(&lock->link);
43944 +       if (!has_spin_lock)
43945 +               spin_lock_irqsave(&g_list_lock, irqflags);
43946 +       list_add(&lock->link, &g_inactive_locks);
43947 +       if (!has_spin_lock)
43948 +               spin_unlock_irqrestore(&g_list_lock, irqflags);
43949 +//     if(lock->flags & ANDROID_SUSPEND_LOCK_FLAG_USER_VISIBLE_MASK) {
43950 +//             sysfs_create_file(struct kobject * k, const struct attribute * a)
43951 +//     }
43952 +       return 0;
43953 +}
43954 +
43955 +int android_init_suspend_lock(android_suspend_lock_t *lock)
43956 +{
43957 +       return android_init_suspend_lock_internal(lock, 0);
43958 +}
43959 +
43960 +void android_uninit_suspend_lock(android_suspend_lock_t *lock)
43961 +{
43962 +       unsigned long irqflags;
43963 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43964 +               printk(KERN_INFO "android_uninit_suspend_lock name=%s\n",
43965 +                       lock->name);
43966 +       spin_lock_irqsave(&g_list_lock, irqflags);
43967 +#ifdef CONFIG_ANDROID_POWER_STAT
43968 +       if(lock->stat.count) {
43969 +               if(g_deleted_wake_locks.stat.count == 0) {
43970 +                       g_deleted_wake_locks.name = "deleted_wake_locks";
43971 +                       android_init_suspend_lock_internal(
43972 +                               &g_deleted_wake_locks, 1);
43973 +               }
43974 +               g_deleted_wake_locks.stat.count += lock->stat.count;
43975 +               g_deleted_wake_locks.stat.expire_count += lock->stat.expire_count;
43976 +               g_deleted_wake_locks.stat.total_time = ktime_add(g_deleted_wake_locks.stat.total_time, lock->stat.total_time);
43977 +               g_deleted_wake_locks.stat.max_time = ktime_add(g_deleted_wake_locks.stat.max_time, lock->stat.max_time);
43978 +       }
43979 +#endif
43980 +       list_del(&lock->link);
43981 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
43982 +}
43983 +
43984 +void android_lock_idle(android_suspend_lock_t *lock)
43985 +{
43986 +       unsigned long irqflags;
43987 +       spin_lock_irqsave(&g_list_lock, irqflags);
43988 +#ifdef CONFIG_ANDROID_POWER_STAT
43989 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
43990 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
43991 +               lock->stat.last_time = ktime_get();
43992 +       }
43993 +#endif
43994 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
43995 +               printk(KERN_INFO "android_power: acquire idle wake lock: %s\n",
43996 +                       lock->name);
43997 +       lock->expires = INT_MAX;
43998 +       lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
43999 +       list_del(&lock->link);
44000 +       list_add(&lock->link, &g_active_idle_wake_locks);
44001 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44002 +}
44003 +
44004 +void android_lock_idle_auto_expire(android_suspend_lock_t *lock, int timeout)
44005 +{
44006 +       unsigned long irqflags;
44007 +       spin_lock_irqsave(&g_list_lock, irqflags);
44008 +#ifdef CONFIG_ANDROID_POWER_STAT
44009 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
44010 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
44011 +               lock->stat.last_time = ktime_get();
44012 +       }
44013 +#endif
44014 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
44015 +               printk(KERN_INFO "android_power: acquire idle wake lock: %s, "
44016 +                       "timeout %d.%03lu\n", lock->name, timeout / HZ,
44017 +                       (timeout % HZ) * MSEC_PER_SEC / HZ);
44018 +       lock->expires = jiffies + timeout;
44019 +       lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
44020 +       list_del(&lock->link);
44021 +       list_add(&lock->link, &g_active_idle_wake_locks);
44022 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44023 +}
44024 +
44025 +void android_lock_suspend(android_suspend_lock_t *lock)
44026 +{
44027 +       unsigned long irqflags;
44028 +       spin_lock_irqsave(&g_list_lock, irqflags);
44029 +#ifdef CONFIG_ANDROID_POWER_STAT
44030 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
44031 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
44032 +               lock->stat.last_time = ktime_get();
44033 +       }
44034 +#endif
44035 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
44036 +               printk(KERN_INFO "android_power: acquire wake lock: %s\n",
44037 +                       lock->name);
44038 +       lock->expires = INT_MAX;
44039 +       lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
44040 +       list_del(&lock->link);
44041 +       list_add(&lock->link, &g_active_partial_wake_locks);
44042 +       g_current_event_num++;
44043 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44044 +}
44045 +
44046 +void android_lock_suspend_auto_expire(android_suspend_lock_t *lock, int timeout)
44047 +{
44048 +       unsigned long irqflags;
44049 +       spin_lock_irqsave(&g_list_lock, irqflags);
44050 +#ifdef CONFIG_ANDROID_POWER_STAT
44051 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
44052 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
44053 +               lock->stat.last_time = ktime_get();
44054 +       }
44055 +#endif
44056 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
44057 +               printk(KERN_INFO "android_power: acquire wake lock: %s, "
44058 +                       "timeout %d.%03lu\n", lock->name, timeout / HZ,
44059 +                       (timeout % HZ) * MSEC_PER_SEC / HZ);
44060 +       lock->expires = jiffies + timeout;
44061 +       lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
44062 +       list_del(&lock->link);
44063 +       list_add(&lock->link, &g_active_partial_wake_locks);
44064 +       g_current_event_num++;
44065 +       wake_up(&g_wait_queue);
44066 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44067 +}
44068 +
44069 +void android_lock_partial_suspend_auto_expire(android_suspend_lock_t *lock, int timeout)
44070 +{
44071 +       unsigned long irqflags;
44072 +       spin_lock_irqsave(&g_list_lock, irqflags);
44073 +#ifdef CONFIG_ANDROID_POWER_STAT
44074 +       if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
44075 +               lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
44076 +               lock->stat.last_time = ktime_get();
44077 +       }
44078 +#endif
44079 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
44080 +               printk(KERN_INFO "android_power: acquire full wake lock: %s, "
44081 +                       "timeout %d.%03lu\n", lock->name, timeout / HZ,
44082 +                       (timeout % HZ) * MSEC_PER_SEC / HZ);
44083 +       lock->expires = jiffies + timeout;
44084 +       lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
44085 +       list_del(&lock->link);
44086 +       list_add(&lock->link, &g_active_full_wake_locks);
44087 +       g_current_event_num++;
44088 +       wake_up(&g_wait_queue);
44089 +       android_power_wakeup_locked(1, ktime_get());
44090 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44091 +}
44092 +
44093 +#ifdef CONFIG_ANDROID_POWER_STAT
44094 +static int print_lock_stat(char *buf, android_suspend_lock_t *lock)
44095 +{
44096 +       ktime_t active_time;
44097 +       if(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)
44098 +               active_time = ktime_sub(ktime_get(), lock->stat.last_time);
44099 +       else
44100 +               active_time = ktime_set(0, 0);
44101 +       return sprintf(buf, "\"%s\"\t%d\t%d\t%lld\t%lld\t%lld\t%lld\n",
44102 +                      lock->name,
44103 +                      lock->stat.count, lock->stat.expire_count,
44104 +                      ktime_to_ns(active_time),
44105 +                      ktime_to_ns(lock->stat.total_time),
44106 +                      ktime_to_ns(lock->stat.max_time),
44107 +                      ktime_to_ns(lock->stat.last_time));
44108 +}
44109 +
44110 +
44111 +static int wakelocks_read_proc(char *page, char **start, off_t off,
44112 +                               int count, int *eof, void *data)
44113 +{
44114 +       unsigned long irqflags;
44115 +       android_suspend_lock_t *lock;
44116 +       int len = 0;
44117 +       char *p = page;
44118 +
44119 +       spin_lock_irqsave(&g_list_lock, irqflags);
44120 +
44121 +       p += sprintf(p, "name\tcount\texpire_count\tactive_since\ttotal_time\tmax_time\tlast_change\n");
44122 +       list_for_each_entry(lock, &g_inactive_locks, link) {
44123 +               p += print_lock_stat(p, lock);
44124 +       }
44125 +       list_for_each_entry(lock, &g_active_partial_wake_locks, link) {
44126 +               p += print_lock_stat(p, lock);
44127 +       }
44128 +       list_for_each_entry(lock, &g_active_full_wake_locks, link) {
44129 +               p += print_lock_stat(p, lock);
44130 +       }
44131 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44132 +
44133 +
44134 +       *start = page + off;
44135 +
44136 +       len = p - page;
44137 +       if (len > off)
44138 +               len -= off;
44139 +       else
44140 +               len = 0;
44141 +
44142 +       return len < count ? len  : count;
44143 +}
44144 +
44145 +static void android_unlock_suspend_stat_locked(android_suspend_lock_t *lock)
44146 +{
44147 +       if(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE) {
44148 +               ktime_t duration;
44149 +               lock->flags &= ~ANDROID_SUSPEND_LOCK_ACTIVE;
44150 +               lock->stat.count++;
44151 +               duration = ktime_sub(ktime_get(), lock->stat.last_time);
44152 +               lock->stat.total_time = ktime_add(lock->stat.total_time, duration);
44153 +               if(ktime_to_ns(duration) > ktime_to_ns(lock->stat.max_time))
44154 +                       lock->stat.max_time = duration;
44155 +               lock->stat.last_time = ktime_get();
44156 +       }
44157 +}
44158 +#endif
44159 +
44160 +void android_unlock_suspend(android_suspend_lock_t *lock)
44161 +{
44162 +       int had_full_wake_locks;
44163 +       unsigned long irqflags;
44164 +       spin_lock_irqsave(&g_list_lock, irqflags);
44165 +#ifdef CONFIG_ANDROID_POWER_STAT
44166 +       android_unlock_suspend_stat_locked(lock);
44167 +#endif
44168 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
44169 +               printk(KERN_INFO "android_power: release wake lock: %s\n",
44170 +                       lock->name);
44171 +       lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
44172 +       had_full_wake_locks = !list_empty(&g_active_full_wake_locks);
44173 +       list_del(&lock->link);
44174 +       list_add(&lock->link, &g_inactive_locks);
44175 +       wake_up(&g_wait_queue);
44176 +       if(had_full_wake_locks && list_empty(&g_active_full_wake_locks)) {
44177 +               printk("android_unlock_suspend: released at %lld\n", ktime_to_ns(ktime_get()));
44178 +               if(g_user_suspend_state == USER_NOTIFICATION) {
44179 +                       printk("android sleep state %d->%d at %lld\n", g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_get()));
44180 +                       g_user_suspend_state = USER_SLEEP;
44181 +                       queue_work(g_suspend_work_queue, &g_suspend_work);
44182 +               }
44183 +       }
44184 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44185 +}
44186 +
44187 +static void android_power_wakeup_locked(int notification, ktime_t time)
44188 +{
44189 +       int new_state = (notification == 0) ? USER_AWAKE : USER_NOTIFICATION;
44190 +
44191 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE) {
44192 +               struct timespec ts;
44193 +               struct rtc_time tm;
44194 +               getnstimeofday(&ts);
44195 +               rtc_time_to_tm(ts.tv_sec, &tm);
44196 +               printk(KERN_INFO "android_power: wakeup (%d->%d) at %lld "
44197 +                       "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
44198 +                       g_user_suspend_state, new_state, ktime_to_ns(time),
44199 +                       tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
44200 +                       tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
44201 +       }
44202 +
44203 +       if(new_state >= g_user_suspend_state) {
44204 +               return;
44205 +       }
44206 +       g_user_suspend_state = new_state;
44207 +       g_current_event_num++;
44208 +       wake_up(&g_wait_queue);
44209 +}
44210 +
44211 +static void android_power_wakeup(void)
44212 +{
44213 +       unsigned long irqflags;
44214 +
44215 +       ktime_t ktime_now;
44216 +
44217 +       spin_lock_irqsave(&g_list_lock, irqflags);
44218 +       ktime_now = ktime_get();
44219 +       android_power_wakeup_locked(0, ktime_now);
44220 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44221 +}
44222 +
44223 +static void android_power_request_sleep(void)
44224 +{
44225 +       unsigned long irqflags;
44226 +       int already_suspended;
44227 +       android_suspend_lock_t *lock, *next_lock;
44228 +
44229 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE) {
44230 +               ktime_t ktime_now;
44231 +               struct timespec ts;
44232 +               struct rtc_time tm;
44233 +               ktime_now = ktime_get();
44234 +               getnstimeofday(&ts);
44235 +               rtc_time_to_tm(ts.tv_sec, &tm);
44236 +               printk(KERN_INFO "android_power: sleep (%d->%d) at %lld "
44237 +                      "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
44238 +                      g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_now),
44239 +                      tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
44240 +                      tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
44241 +       }
44242 +
44243 +       spin_lock_irqsave(&g_list_lock, irqflags);
44244 +       already_suspended = g_user_suspend_state == USER_SLEEP;
44245 +       if(!already_suspended) {
44246 +               g_user_suspend_state = USER_SLEEP;
44247 +       }
44248 +
44249 +       list_for_each_entry_safe(lock, next_lock, &g_active_full_wake_locks, link) {
44250 +#ifdef CONFIG_ANDROID_POWER_STAT
44251 +               android_unlock_suspend_stat_locked(lock);
44252 +#endif
44253 +               list_del(&lock->link);
44254 +               list_add(&lock->link, &g_inactive_locks);
44255 +               printk("android_power_suspend: aborted full wake lock %s\n", lock->name);
44256 +       }
44257 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44258 +       queue_work(g_suspend_work_queue, &g_suspend_work);
44259 +}
44260 +
44261 +void android_register_early_suspend(android_early_suspend_t *handler)
44262 +{
44263 +       struct list_head *pos;
44264 +
44265 +       mutex_lock(&g_early_suspend_lock);
44266 +       list_for_each(pos, &g_early_suspend_handlers) {
44267 +               android_early_suspend_t *e = list_entry(pos, android_early_suspend_t, link);
44268 +               if(e->level > handler->level)
44269 +                       break;
44270 +       }
44271 +       list_add_tail(&handler->link, pos);
44272 +       mutex_unlock(&g_early_suspend_lock);
44273 +}
44274 +
44275 +void android_unregister_early_suspend(android_early_suspend_t *handler)
44276 +{
44277 +       mutex_lock(&g_early_suspend_lock);
44278 +       list_del(&handler->link);
44279 +       mutex_unlock(&g_early_suspend_lock);
44280 +}
44281 +
44282 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
44283 +static int orig_fgconsole;
44284 +static void console_early_suspend(android_early_suspend_t *h)
44285 +{
44286 +       acquire_console_sem();
44287 +       orig_fgconsole = fg_console;
44288 +       if (vc_allocate(ANDROID_SUSPEND_CONSOLE))
44289 +               goto err;
44290 +       if (set_console(ANDROID_SUSPEND_CONSOLE))
44291 +               goto err;
44292 +       release_console_sem();
44293 +
44294 +       if (vt_waitactive(ANDROID_SUSPEND_CONSOLE))
44295 +               pr_warning("console_early_suspend: Can't switch VCs.\n");
44296 +       return;
44297 +err:
44298 +       pr_warning("console_early_suspend: Can't set console\n");
44299 +       release_console_sem();
44300 +}
44301 +
44302 +static void console_late_resume(android_early_suspend_t *h)
44303 +{
44304 +       int ret;
44305 +       acquire_console_sem();
44306 +       ret = set_console(orig_fgconsole);
44307 +       release_console_sem();
44308 +       if (ret) {
44309 +               pr_warning("console_late_resume: Can't set console.\n");
44310 +               return;
44311 +       }
44312 +
44313 +       if (vt_waitactive(orig_fgconsole))
44314 +               pr_warning("console_late_resume: Can't switch VCs.\n");
44315 +}
44316 +
44317 +static android_early_suspend_t console_early_suspend_desc = {
44318 +       .level = ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH,
44319 +       .suspend = console_early_suspend,
44320 +       .resume = console_late_resume,
44321 +};
44322 +#else
44323 +/* tell userspace to stop drawing, wait for it to stop */
44324 +static void stop_drawing_early_suspend(android_early_suspend_t *h)
44325 +{
44326 +       int ret;
44327 +       unsigned long irq_flags;
44328 +
44329 +       spin_lock_irqsave(&fb_state_lock, irq_flags);
44330 +       fb_state = ANDROID_REQUEST_STOP_DRAWING;
44331 +       spin_unlock_irqrestore(&fb_state_lock, irq_flags);
44332 +
44333 +       wake_up_all(&fb_state_wq);
44334 +       ret = wait_event_timeout(fb_state_wq,
44335 +                                fb_state == ANDROID_STOPPED_DRAWING,
44336 +                                HZ);
44337 +       if (unlikely(fb_state != ANDROID_STOPPED_DRAWING))
44338 +               printk(KERN_WARNING "android_power: timeout waiting for "
44339 +                      "userspace to stop drawing\n");
44340 +}
44341 +
44342 +/* tell userspace to start drawing */
44343 +static void start_drawing_late_resume(android_early_suspend_t *h)
44344 +{
44345 +       unsigned long irq_flags;
44346 +
44347 +       spin_lock_irqsave(&fb_state_lock, irq_flags);
44348 +       fb_state = ANDROID_DRAWING_OK;
44349 +       spin_unlock_irqrestore(&fb_state_lock, irq_flags);
44350 +       wake_up(&fb_state_wq);
44351 +}
44352 +
44353 +static android_early_suspend_t stop_drawing_early_suspend_desc = {
44354 +       .level = ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH,
44355 +       .suspend = stop_drawing_early_suspend,
44356 +       .resume = start_drawing_late_resume,
44357 +};
44358 +#endif
44359 +
44360 +#if ANDROID_POWER_TEST_EARLY_SUSPEND
44361 +
44362 +typedef struct
44363 +{
44364 +       android_early_suspend_t h;
44365 +       const char *string;
44366 +} early_suspend_test_t;
44367 +
44368 +static void early_suspend_test(android_early_suspend_t *h)
44369 +{
44370 +       early_suspend_test_t *est = container_of(h, early_suspend_test_t, h);
44371 +       printk("early suspend %s (l %d)\n", est->string, h->level);
44372 +}
44373 +
44374 +static void late_resume_test(android_early_suspend_t *h)
44375 +{
44376 +       early_suspend_test_t *est = container_of(h, early_suspend_test_t, h);
44377 +       printk("late resume %s (l %d)\n", est->string, h->level);
44378 +}
44379 +
44380 +#define EARLY_SUSPEND_TEST_ENTRY(ilevel, istring) \
44381 +{ \
44382 +       .h = { \
44383 +               .level = ilevel, \
44384 +               .suspend = early_suspend_test, \
44385 +               .resume = late_resume_test \
44386 +       }, \
44387 +       .string = istring \
44388 +}
44389 +static early_suspend_test_t early_suspend_tests[] = {
44390 +       EARLY_SUSPEND_TEST_ENTRY(10, "1"),
44391 +       EARLY_SUSPEND_TEST_ENTRY(5, "2"),
44392 +       EARLY_SUSPEND_TEST_ENTRY(10, "3"),
44393 +       EARLY_SUSPEND_TEST_ENTRY(15, "4"),
44394 +       EARLY_SUSPEND_TEST_ENTRY(8, "5")
44395 +};
44396 +
44397 +#endif
44398 +
44399 +static int get_wait_timeout(int print_locks, int state, struct list_head *list_head)
44400 +{
44401 +       unsigned long irqflags;
44402 +       android_suspend_lock_t *lock, *next;
44403 +       int max_timeout = 0;
44404 +
44405 +       spin_lock_irqsave(&g_list_lock, irqflags);
44406 +       list_for_each_entry_safe(lock, next, list_head, link) {
44407 +               if(lock->flags & ANDROID_SUSPEND_LOCK_AUTO_EXPIRE) {
44408 +                       int timeout = lock->expires - (int)jiffies;
44409 +                       if(timeout <= 0) {
44410 +                               lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
44411 +#ifdef CONFIG_ANDROID_POWER_STAT
44412 +                               lock->stat.expire_count++;
44413 +                               android_unlock_suspend_stat_locked(lock);
44414 +#endif
44415 +                               list_del(&lock->link);
44416 +                               list_add(&lock->link, &g_inactive_locks);
44417 +                               if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
44418 +                                       printk("expired wake lock %s\n", lock->name);
44419 +                       }
44420 +                       else {
44421 +                               if(timeout > max_timeout)
44422 +                                       max_timeout = timeout;
44423 +                               if(print_locks)
44424 +                                       printk("active wake lock %s, time left %d\n", lock->name, timeout);
44425 +                       }
44426 +               }
44427 +               else {
44428 +                       if(print_locks)
44429 +                               printk("active wake lock %s\n", lock->name);
44430 +               }
44431 +       }
44432 +       if(g_user_suspend_state != state || list_empty(list_head))
44433 +               max_timeout = -1;
44434 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44435 +       return max_timeout;
44436 +}
44437 +
44438 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
44439 +static int android_power_class_suspend(struct sys_device *sdev, pm_message_t state)
44440 +{
44441 +       int rv = 0;
44442 +       unsigned long irqflags;
44443 +
44444 +       printk("android_power_suspend: enter\n");
44445 +       spin_lock_irqsave(&g_list_lock, irqflags);
44446 +       if(!list_empty(&g_active_partial_wake_locks)) {
44447 +               printk("android_power_suspend: abort for partial wakeup\n");
44448 +               rv = -EAGAIN;
44449 +       }
44450 +       if(g_user_suspend_state != USER_SLEEP) {
44451 +               printk("android_power_suspend: abort for full wakeup\n");
44452 +               rv = -EAGAIN;
44453 +       }
44454 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44455 +       return rv;
44456 +}
44457 +
44458 +static int android_power_device_suspend(struct sys_device *sdev, pm_message_t state)
44459 +{
44460 +       int rv = 0;
44461 +       unsigned long irqflags;
44462 +
44463 +       printk("android_power_device_suspend: enter\n");
44464 +       spin_lock_irqsave(&g_list_lock, irqflags);
44465 +       if(!list_empty(&g_active_partial_wake_locks)) {
44466 +               printk("android_power_device_suspend: abort for partial wakeup\n");
44467 +               rv = -EAGAIN;
44468 +       }
44469 +       if(g_user_suspend_state != USER_SLEEP) {
44470 +               printk("android_power_device_suspend: abort for full wakeup\n");
44471 +               rv = -EAGAIN;
44472 +       }
44473 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44474 +       return rv;
44475 +}
44476 +#endif
44477 +
44478 +int android_power_is_driver_suspended(void)
44479 +{
44480 +       return (get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) < 0) && (g_user_suspend_state == USER_SLEEP);
44481 +}
44482 +
44483 +int android_power_is_low_power_idle_ok(void)
44484 +{
44485 +       get_wait_timeout(0, USER_SLEEP, &g_active_idle_wake_locks);
44486 +       return list_empty(&g_active_idle_wake_locks);
44487 +}
44488 +
44489 +static void android_power_suspend(struct work_struct *work)
44490 +{
44491 +       int entry_event_num;
44492 +       int ret;
44493 +       int wait = 0;
44494 +       android_early_suspend_t *pos;
44495 +       int print_locks = 0;
44496 +       unsigned long irqflags;
44497 +
44498 +       while(g_user_suspend_state != USER_AWAKE) {
44499 +               while(g_user_suspend_state == USER_NOTIFICATION) {
44500 +                       wait = get_wait_timeout(print_locks, USER_NOTIFICATION, &g_active_full_wake_locks);
44501 +                       if(wait < 0)
44502 +                               break;
44503 +                       if(wait)
44504 +                               wait_event_interruptible_timeout(g_wait_queue, get_wait_timeout(0, USER_NOTIFICATION, &g_active_full_wake_locks) != wait, wait);
44505 +               }
44506 +               spin_lock_irqsave(&g_list_lock, irqflags);
44507 +               if(g_user_suspend_state == USER_NOTIFICATION && list_empty(&g_active_full_wake_locks)) {
44508 +                       printk("android sleep state %d->%d at %lld\n", g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_get()));
44509 +                       g_user_suspend_state = USER_SLEEP;
44510 +               }
44511 +               spin_unlock_irqrestore(&g_list_lock, irqflags);
44512 +               wait = 0;
44513 +               if(g_user_suspend_state == USER_AWAKE) {
44514 +                       printk("android_power_suspend: suspend aborted\n");
44515 +                       return;
44516 +               }
44517 +
44518 +               mutex_lock(&g_early_suspend_lock);
44519 +               //printk("android_power_suspend: call early suspend handlers\n");
44520 +               list_for_each_entry(pos, &g_early_suspend_handlers, link) {
44521 +                       if(pos->suspend != NULL)
44522 +                               pos->suspend(pos);
44523 +               }
44524 +               //printk("android_power_suspend: call early suspend handlers\n");
44525 +
44526 +               //printk("android_power_suspend: enter\n");
44527 +
44528 +               sys_sync();
44529 +
44530 +               while(g_user_suspend_state == USER_SLEEP) {
44531 +                       //printk("android_power_suspend: enter wait (%d)\n", wait);
44532 +                       if(wait) {
44533 +                               wait_event_interruptible_timeout(g_wait_queue, g_user_suspend_state != USER_SLEEP, wait);
44534 +                               wait = 0;
44535 +                       }
44536 +                       if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
44537 +                               print_locks = 1;
44538 +                       while(1) {
44539 +                               wait = get_wait_timeout(print_locks, USER_SLEEP, &g_active_partial_wake_locks);
44540 +                               print_locks = 0;
44541 +                               if(wait < 0)
44542 +                                       break;
44543 +                               if(wait)
44544 +                                       wait_event_interruptible_timeout(g_wait_queue, get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) != wait, wait);
44545 +                               else
44546 +                                       wait_event_interruptible(g_wait_queue, get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) != wait);
44547 +                       }
44548 +                       wait = 0;
44549 +                       //printk("android_power_suspend: exit wait\n");
44550 +                       entry_event_num = g_current_event_num;
44551 +                       if(g_user_suspend_state != USER_SLEEP)
44552 +                               break;
44553 +                       sys_sync();
44554 +                       if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
44555 +                               printk(KERN_INFO "android_power_suspend: enter suspend\n");
44556 +                       ret = pm_suspend(PM_SUSPEND_MEM);
44557 +                       if (android_power_debug_mask & ANDROID_POWER_DEBUG_EXIT_SUSPEND) {
44558 +                               struct timespec ts;
44559 +                               struct rtc_time tm;
44560 +                               getnstimeofday(&ts);
44561 +                               rtc_time_to_tm(ts.tv_sec, &tm);
44562 +                               printk("android_power_suspend: exit suspend, ret = %d "
44563 +                                       "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n", ret,
44564 +                                       tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
44565 +                                       tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
44566 +                       }
44567 +                       if(g_current_event_num == entry_event_num) {
44568 +                               if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
44569 +                                       printk(KERN_INFO "android_power_suspend: pm_suspend returned with no event\n");
44570 +                               wait = HZ / 2;
44571 +#ifdef CONFIG_ANDROID_POWER_STAT
44572 +                               if(g_no_wake_locks.stat.count == 0) {
44573 +                                       g_no_wake_locks.name = "unknown_wakeups";
44574 +                                       android_init_suspend_lock(&g_no_wake_locks);
44575 +                               }
44576 +                               g_no_wake_locks.stat.count++;
44577 +                               g_no_wake_locks.stat.total_time = ktime_add(
44578 +                                       g_no_wake_locks.stat.total_time,
44579 +                                       ktime_set(0, 500 * NSEC_PER_MSEC));
44580 +                               g_no_wake_locks.stat.max_time =
44581 +                                       ktime_set(0, 500 * NSEC_PER_MSEC);
44582 +#endif
44583 +                       }
44584 +               }
44585 +               if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE)
44586 +                       printk("android_power_suspend: done\n");
44587 +               //printk("android_power_suspend: call late resume handlers\n");
44588 +               list_for_each_entry_reverse(pos, &g_early_suspend_handlers, link) {
44589 +                       if(pos->resume != NULL)
44590 +                               pos->resume(pos);
44591 +               }
44592 +               //printk("android_power_suspend: call late resume handlers\n");
44593 +               mutex_unlock(&g_early_suspend_lock);
44594 +       }
44595 +}
44596 +
44597 +#if 0
44598 +struct sysdev_class android_power_sysclass = {
44599 +       set_kset_name("android_power"),
44600 +       .suspend = android_power_class_suspend
44601 +};
44602 +static struct sysdev_class *g_android_power_sysclass = NULL;
44603 +
44604 +static struct {
44605 +       struct sys_device sysdev;
44606 +//     omap_csmi_gsm_image_info_t *pdata;
44607 +} android_power_device = {
44608 +       .sysdev = {
44609 +               .id             = 0,
44610 +               .cls            = &android_power_sysclass,
44611 +//             .suspend = android_power_device_suspend
44612 +       },
44613 +//     .pdata = &g_gsm_image_info
44614 +};
44615 +
44616 +struct sysdev_class *android_power_get_sysclass(void)
44617 +{
44618 +       return g_android_power_sysclass;
44619 +}
44620 +#endif
44621 +
44622 +static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44623 +{
44624 +       char * s = buf;
44625 +       unsigned long irqflags;
44626 +
44627 +       spin_lock_irqsave(&g_list_lock, irqflags);
44628 +       s += sprintf(s, "%d-%d-%d\n", g_user_suspend_state, list_empty(&g_active_full_wake_locks), list_empty(&g_active_partial_wake_locks));
44629 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44630 +       return (s - buf);
44631 +}
44632 +
44633 +static ssize_t state_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44634 +{
44635 +       if(n >= strlen("standby") &&
44636 +          strncmp(buf, "standby", strlen("standby")) == 0) {
44637 +               android_power_request_sleep();
44638 +               wait_event_interruptible(g_wait_queue, g_user_suspend_state == USER_AWAKE);
44639 +               return n;
44640 +       }
44641 +       if(n >= strlen("wake") &&
44642 +          strncmp(buf, "wake", strlen("wake")) == 0) {
44643 +               android_power_wakeup();
44644 +               return n;
44645 +       }
44646 +       printk("android_power state_store: invalid argument\n");
44647 +       return -EINVAL;
44648 +}
44649 +
44650 +static ssize_t request_state_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44651 +{
44652 +       char * s = buf;
44653 +       unsigned long irqflags;
44654 +
44655 +       spin_lock_irqsave(&g_list_lock, irqflags);
44656 +       if(g_user_suspend_state == USER_AWAKE)
44657 +               s += sprintf(s, "wake\n");
44658 +       else if(g_user_suspend_state == USER_NOTIFICATION)
44659 +               s += sprintf(s, "standby (w/full wake lock)\n");
44660 +       else
44661 +               s += sprintf(s, "standby\n");
44662 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44663 +       return (s - buf);
44664 +}
44665 +
44666 +static ssize_t request_state_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44667 +{
44668 +       if(n >= strlen("standby") &&
44669 +          strncmp(buf, "standby", strlen("standby")) == 0) {
44670 +               android_power_request_sleep();
44671 +               return n;
44672 +       }
44673 +       if(n >= strlen("wake") &&
44674 +          strncmp(buf, "wake", strlen("wake")) == 0) {
44675 +               android_power_wakeup();
44676 +               return n;
44677 +       }
44678 +       printk("android_power state_store: invalid argument\n");
44679 +       return -EINVAL;
44680 +}
44681 +
44682 +
44683 +static int lookup_wake_lock_name(const char *buf, size_t n, int allocate, int *timeout)
44684 +{
44685 +       int i;
44686 +       int free_index = -1;
44687 +       int inactive_index = -1;
44688 +       int expires_index = -1;
44689 +       int expires_time = INT_MAX;
44690 +       char *tmp_buf[64];
44691 +       char name[32];
44692 +       u64 nanoseconds;
44693 +       int num_arg;
44694 +
44695 +       if(n <= 0)
44696 +               return -EINVAL;
44697 +       if(n >= sizeof(tmp_buf))
44698 +               return -EOVERFLOW;
44699 +       if(n == sizeof(tmp_buf) - 1 && buf[n - 1] != '\0')
44700 +               return -EOVERFLOW;
44701 +
44702 +       memcpy(tmp_buf, buf, n);
44703 +       if(tmp_buf[n - 1] != '\0')
44704 +               tmp_buf[n] = '\0';
44705 +
44706 +       num_arg = sscanf(buf, "%31s %llu", name, &nanoseconds);
44707 +       if(num_arg < 1)
44708 +               return -EINVAL;
44709 +
44710 +       if(strlen(name) >= sizeof(g_user_wake_locks[i].name_buffer))
44711 +               return -EOVERFLOW;
44712 +
44713 +       if(timeout != NULL) {
44714 +               if(num_arg > 1) {
44715 +                       do_div(nanoseconds, (NSEC_PER_SEC / HZ));
44716 +                       if(nanoseconds <= 0)
44717 +                               nanoseconds = 1;
44718 +                       *timeout = nanoseconds;
44719 +               }
44720 +               else
44721 +                       *timeout = 0;
44722 +       }
44723 +
44724 +       for(i = 0; i < g_max_user_lockouts; i++) {
44725 +               if(strcmp(g_user_wake_locks[i].name_buffer, name) == 0)
44726 +                       return i;
44727 +               if(g_user_wake_locks[i].name_buffer[0] == '\0')
44728 +                       free_index = i;
44729 +               else if(g_user_wake_locks[i].state == USER_WAKE_LOCK_INACTIVE)
44730 +                       inactive_index = i;
44731 +               else if(g_user_wake_locks[i].suspend_lock.expires < expires_time)
44732 +                       expires_index = i;
44733 +       }
44734 +       if(allocate) {
44735 +               if(free_index >= 0)
44736 +                       i = free_index;
44737 +               else if(inactive_index >= 0)
44738 +                       i = inactive_index;
44739 +               else if(expires_index >= 0) {
44740 +                       i = expires_index;
44741 +                       printk("lookup_wake_lock_name: overwriting expired lock, %s\n", g_user_wake_locks[i].name_buffer);
44742 +               }
44743 +               else {
44744 +                       i = 0;
44745 +                       printk("lookup_wake_lock_name: overwriting active lock, %s\n", g_user_wake_locks[i].name_buffer);
44746 +               }
44747 +               strcpy(g_user_wake_locks[i].name_buffer, name);
44748 +               return i;
44749 +       }
44750 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44751 +               printk(KERN_INFO "lookup_wake_lock_name: %s not found\n", name);
44752 +       return -EINVAL;
44753 +}
44754 +
44755 +static ssize_t acquire_full_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44756 +{
44757 +       int i;
44758 +       char * s = buf;
44759 +       unsigned long irqflags;
44760 +
44761 +       spin_lock_irqsave(&g_list_lock, irqflags);
44762 +       for(i = 0; i < g_max_user_lockouts; i++) {
44763 +               if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_FULL)
44764 +                       s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
44765 +       }
44766 +       s += sprintf(s, "\n");
44767 +
44768 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44769 +       return (s - buf);
44770 +}
44771 +
44772 +static ssize_t acquire_full_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44773 +{
44774 +       int i;
44775 +       unsigned long irqflags;
44776 +       int timeout;
44777 +
44778 +       spin_lock_irqsave(&g_list_lock, irqflags);
44779 +       i = lookup_wake_lock_name(buf, n, 1, &timeout);
44780 +       if(i >= 0)
44781 +               g_user_wake_locks[i].state = USER_WAKE_LOCK_FULL;
44782 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44783 +       if(i < 0)
44784 +               return i;
44785 +
44786 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44787 +               printk(KERN_INFO "acquire_full_wake_lock_store: %s, size %d\n",
44788 +                       g_user_wake_locks[i].name_buffer, n);
44789 +
44790 +       //android_lock_partial_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, ktime_to_timespec(g_auto_off_timeout).tv_sec * HZ);
44791 +       if(timeout == 0)
44792 +               timeout = INT_MAX;
44793 +       android_lock_partial_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, timeout);
44794 +
44795 +       return n;
44796 +}
44797 +
44798 +static ssize_t acquire_partial_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44799 +{
44800 +       int i;
44801 +       char * s = buf;
44802 +       unsigned long irqflags;
44803 +
44804 +       spin_lock_irqsave(&g_list_lock, irqflags);
44805 +       for(i = 0; i < g_max_user_lockouts; i++) {
44806 +               if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_PARTIAL)
44807 +                       s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
44808 +       }
44809 +       s += sprintf(s, "\n");
44810 +
44811 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44812 +       return (s - buf);
44813 +}
44814 +
44815 +static ssize_t acquire_partial_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44816 +{
44817 +       int i;
44818 +       unsigned long irqflags;
44819 +       int timeout;
44820 +
44821 +       spin_lock_irqsave(&g_list_lock, irqflags);
44822 +       i = lookup_wake_lock_name(buf, n, 1, &timeout);
44823 +       if(i >= 0)
44824 +               g_user_wake_locks[i].state = USER_WAKE_LOCK_PARTIAL;
44825 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44826 +       if(i < 0)
44827 +               return 0;
44828 +
44829 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44830 +               printk(KERN_INFO "acquire_partial_wake_lock_store: %s, "
44831 +                       "size %d\n", g_user_wake_locks[i].name_buffer, n);
44832 +
44833 +       if(timeout)
44834 +               android_lock_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, timeout);
44835 +       else
44836 +               android_lock_suspend(&g_user_wake_locks[i].suspend_lock);
44837 +
44838 +       return n;
44839 +}
44840 +
44841 +
44842 +static ssize_t release_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
44843 +{
44844 +       int i;
44845 +       char * s = buf;
44846 +       unsigned long irqflags;
44847 +
44848 +       spin_lock_irqsave(&g_list_lock, irqflags);
44849 +       for(i = 0; i < g_max_user_lockouts; i++) {
44850 +               if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_INACTIVE)
44851 +                       s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
44852 +       }
44853 +       s += sprintf(s, "\n");
44854 +
44855 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44856 +       return (s - buf);
44857 +}
44858 +
44859 +static ssize_t release_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
44860 +{
44861 +       int i;
44862 +       unsigned long irqflags;
44863 +
44864 +       spin_lock_irqsave(&g_list_lock, irqflags);
44865 +       i = lookup_wake_lock_name(buf, n, 1, NULL);
44866 +       if(i >= 0) {
44867 +               g_user_wake_locks[i].state = USER_WAKE_LOCK_INACTIVE;
44868 +       }
44869 +       spin_unlock_irqrestore(&g_list_lock, irqflags);
44870 +
44871 +       if(i < 0)
44872 +               return i;
44873 +
44874 +       if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
44875 +               printk(KERN_INFO "release_wake_lock_store: %s, size %d\n",
44876 +                       g_user_wake_locks[i].name_buffer, n);
44877 +
44878 +       android_unlock_suspend(&g_user_wake_locks[i].suspend_lock);
44879 +       return n;
44880 +}
44881 +
44882 +
44883 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
44884 +static ssize_t wait_for_fb_sleep_show(struct kobject *kobj,
44885 +                                     struct kobj_attribute *attr, char *buf)
44886 +{
44887 +       char * s = buf;
44888 +       int ret;
44889 +
44890 +       ret = wait_event_interruptible(fb_state_wq,
44891 +                                      fb_state != ANDROID_DRAWING_OK);
44892 +       if (ret && fb_state == ANDROID_DRAWING_OK)
44893 +               return ret;
44894 +       else
44895 +               s += sprintf(buf, "sleeping");
44896 +       return (s - buf);
44897 +}
44898 +
44899 +static ssize_t wait_for_fb_wake_show(struct kobject *kobj,
44900 +                                    struct kobj_attribute *attr, char *buf)
44901 +{
44902 +       char * s = buf;
44903 +       int ret;
44904 +       unsigned long irq_flags;
44905 +
44906 +       spin_lock_irqsave(&fb_state_lock, irq_flags);
44907 +       if (fb_state == ANDROID_REQUEST_STOP_DRAWING) {
44908 +               fb_state = ANDROID_STOPPED_DRAWING;
44909 +               wake_up(&fb_state_wq);
44910 +       }
44911 +       spin_unlock_irqrestore(&fb_state_lock, irq_flags);
44912 +
44913 +       ret = wait_event_interruptible(fb_state_wq,
44914 +                                      fb_state == ANDROID_DRAWING_OK);
44915 +       if (ret && fb_state != ANDROID_DRAWING_OK)
44916 +               return ret;
44917 +       else
44918 +               s += sprintf(buf, "awake");
44919 +
44920 +       return (s - buf);
44921 +}
44922 +#endif
44923 +
44924 +#define android_power_attr(_name) \
44925 +static struct kobj_attribute _name##_attr = {  \
44926 +       .attr   = {                             \
44927 +               .name = __stringify(_name),     \
44928 +               .mode = 0664,                   \
44929 +       },                                      \
44930 +       .show   = _name##_show,                 \
44931 +       .store  = _name##_store,                \
44932 +}
44933 +
44934 +#define android_power_ro_attr(_name) \
44935 +static struct kobj_attribute _name##_attr = {  \
44936 +       .attr   = {                             \
44937 +               .name = __stringify(_name),     \
44938 +               .mode = 0444,                   \
44939 +       },                                      \
44940 +       .show   = _name##_show,                 \
44941 +       .store  = NULL,         \
44942 +}
44943 +
44944 +android_power_attr(state);
44945 +android_power_attr(request_state);
44946 +android_power_attr(acquire_full_wake_lock);
44947 +android_power_attr(acquire_partial_wake_lock);
44948 +android_power_attr(release_wake_lock);
44949 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
44950 +android_power_ro_attr(wait_for_fb_sleep);
44951 +android_power_ro_attr(wait_for_fb_wake);
44952 +#endif
44953 +
44954 +static struct attribute * g[] = {
44955 +       &state_attr.attr,
44956 +       &request_state_attr.attr,
44957 +       &acquire_full_wake_lock_attr.attr,
44958 +       &acquire_partial_wake_lock_attr.attr,
44959 +       &release_wake_lock_attr.attr,
44960 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
44961 +       &wait_for_fb_sleep_attr.attr,
44962 +       &wait_for_fb_wake_attr.attr,
44963 +#endif
44964 +       NULL,
44965 +};
44966 +
44967 +static struct attribute_group attr_group = {
44968 +       .attrs = g,
44969 +};
44970 +
44971 +#if 0
44972 +// test code when there is no platform suspend
44973 +
44974 +static android_suspend_lock_t test_pm_ops_suspend_lock = {
44975 +       .name = "test_pm_ops"
44976 +};
44977 +
44978 +int test_pm_op_enter(suspend_state_t state)
44979 +{
44980 +       printk("test_pm_op_enter reached\n");
44981 +       android_lock_suspend(&test_pm_ops_suspend_lock);
44982 +       printk("test_pm_op_enter returned\n");
44983 +       return 0;
44984 +}
44985 +
44986 +void test_pm_ops_late_resume_handler(android_early_suspend_t *h)
44987 +{
44988 +       printk("test_pm_ops_late_resume_handler reached\n");
44989 +       android_unlock_suspend(&test_pm_ops_suspend_lock);
44990 +       printk("test_pm_ops_late_resume_handler returned\n");
44991 +}
44992 +
44993 +static struct pm_ops test_pm_ops = {
44994 +       .enter = test_pm_op_enter
44995 +};
44996 +
44997 +static android_early_suspend_t test_pm_ops_early_suspend_handler = {
44998 +       .resume = test_pm_ops_late_resume_handler
44999 +};
45000 +#endif
45001 +
45002 +static int __init android_power_init(void)
45003 +{
45004 +       int ret;
45005 +       int i;
45006 +
45007 +#if 0
45008 +       if(pm_ops == NULL) {
45009 +               printk("android_power_init no pm_ops, installing test code\n");
45010 +               pm_set_ops(&test_pm_ops);
45011 +               android_init_suspend_lock(&test_pm_ops_suspend_lock);
45012 +               android_register_early_suspend(&test_pm_ops_early_suspend_handler);
45013 +       }
45014 +#endif
45015 +
45016 +#ifdef CONFIG_ANDROID_POWER_STAT
45017 +       g_deleted_wake_locks.stat.count = 0;
45018 +#endif
45019 +       init_waitqueue_head(&g_wait_queue);
45020 +#ifndef CONFIG_FRAMEBUFFER_CONSOLE
45021 +       init_waitqueue_head(&fb_state_wq);
45022 +       fb_state = ANDROID_DRAWING_OK;
45023 +#endif
45024 +
45025 +       g_user_wake_locks = kzalloc(sizeof(*g_user_wake_locks) * g_max_user_lockouts, GFP_KERNEL);
45026 +       if(g_user_wake_locks == NULL) {
45027 +               ret = -ENOMEM;
45028 +               goto err1;
45029 +       }
45030 +       for(i = 0; i < g_max_user_lockouts; i++) {
45031 +               g_user_wake_locks[i].suspend_lock.name = g_user_wake_locks[i].name_buffer;
45032 +               android_init_suspend_lock(&g_user_wake_locks[i].suspend_lock);
45033 +       }
45034 +
45035 +       g_suspend_work_queue = create_workqueue("suspend");
45036 +       if(g_suspend_work_queue == NULL) {
45037 +               ret = -ENOMEM;
45038 +               goto err2;
45039 +       }
45040 +
45041 +       android_power_kobj = kobject_create_and_add("android_power", NULL);
45042 +       if (android_power_kobj == NULL) {
45043 +               printk("android_power_init: subsystem_register failed\n");
45044 +               ret = -ENOMEM;
45045 +               goto err3;
45046 +       }
45047 +       ret = sysfs_create_group(android_power_kobj, &attr_group);
45048 +       if(ret) {
45049 +               printk("android_power_init: sysfs_create_group failed\n");
45050 +               goto err4;
45051 +       }
45052 +#ifdef CONFIG_ANDROID_POWER_STAT
45053 +       create_proc_read_entry("wakelocks", S_IRUGO, NULL, wakelocks_read_proc, NULL);
45054 +#endif
45055 +
45056 +#if ANDROID_POWER_TEST_EARLY_SUSPEND
45057 +       {
45058 +               int i;
45059 +               for(i = 0; i < sizeof(early_suspend_tests) / sizeof(early_suspend_tests[0]); i++)
45060 +                       android_register_early_suspend(&early_suspend_tests[i].h);
45061 +       }
45062 +#endif
45063 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
45064 +       android_register_early_suspend(&console_early_suspend_desc);
45065 +#else
45066 +       android_register_early_suspend(&stop_drawing_early_suspend_desc);
45067 +#endif
45068 +
45069 +#if 0
45070 +       ret = sysdev_class_register(&android_power_sysclass);
45071 +       if(ret) {
45072 +               printk("android_power_init: sysdev_class_register failed\n");
45073 +               goto err1;
45074 +       }
45075 +       ret = sysdev_register(&android_power_device.sysdev);
45076 +       if(ret < 0)
45077 +               goto err2;
45078 +
45079 +       g_android_power_sysclass = &android_power_sysclass;
45080 +#endif
45081 +       return 0;
45082 +
45083 +//err2:
45084 +//     sysdev_class_unregister(&android_power_sysclass);
45085 +err4:
45086 +       kobject_del(android_power_kobj);
45087 +err3:
45088 +       destroy_workqueue(g_suspend_work_queue);
45089 +err2:
45090 +       for(i = 0; i < g_max_user_lockouts; i++) {
45091 +               android_uninit_suspend_lock(&g_user_wake_locks[i].suspend_lock);
45092 +       }
45093 +       kfree(g_user_wake_locks);
45094 +err1:
45095 +       return ret;
45096 +}
45097 +
45098 +static void  __exit android_power_exit(void)
45099 +{
45100 +       int i;
45101 +//     g_android_power_sysclass = NULL;
45102 +//     sysdev_unregister(&android_power_device.sysdev);
45103 +//     sysdev_class_unregister(&android_power_sysclass);
45104 +#ifdef CONFIG_FRAMEBUFFER_CONSOLE
45105 +       android_unregister_early_suspend(&console_early_suspend_desc);
45106 +#else
45107 +       android_unregister_early_suspend(&stop_drawing_early_suspend_desc);
45108 +#endif
45109 +#ifdef CONFIG_ANDROID_POWER_STAT
45110 +       remove_proc_entry("wakelocks", NULL);
45111 +#endif
45112 +       sysfs_remove_group(android_power_kobj, &attr_group);
45113 +       kobject_del(android_power_kobj);
45114 +       destroy_workqueue(g_suspend_work_queue);
45115 +       for(i = 0; i < g_max_user_lockouts; i++) {
45116 +               android_uninit_suspend_lock(&g_user_wake_locks[i].suspend_lock);
45117 +       }
45118 +       kfree(g_user_wake_locks);
45119 +}
45120 +
45121 +core_initcall(android_power_init);
45122 +module_exit(android_power_exit);
45123 +
45124 +//EXPORT_SYMBOL(android_power_get_sysclass);
45125 +EXPORT_SYMBOL(android_init_suspend_lock);
45126 +EXPORT_SYMBOL(android_uninit_suspend_lock);
45127 +EXPORT_SYMBOL(android_lock_suspend);
45128 +EXPORT_SYMBOL(android_lock_suspend_auto_expire);
45129 +EXPORT_SYMBOL(android_unlock_suspend);
45130 +EXPORT_SYMBOL(android_power_wakeup);
45131 +EXPORT_SYMBOL(android_register_early_suspend);
45132 +EXPORT_SYMBOL(android_unregister_early_suspend);
45133 +
45134 +
45135 Index: linux-2.6.28/drivers/android/ram_console.c
45136 ===================================================================
45137 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
45138 +++ linux-2.6.28/drivers/android/ram_console.c  2009-01-02 00:01:56.000000000 +0100
45139 @@ -0,0 +1,395 @@
45140 +/* drivers/android/ram_console.c
45141 + *
45142 + * Copyright (C) 2007-2008 Google, Inc.
45143 + *
45144 + * This software is licensed under the terms of the GNU General Public
45145 + * License version 2, as published by the Free Software Foundation, and
45146 + * may be copied, distributed, and modified under those terms.
45147 + *
45148 + * This program is distributed in the hope that it will be useful,
45149 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
45150 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
45151 + * GNU General Public License for more details.
45152 + *
45153 + */
45154 +
45155 +#include <linux/console.h>
45156 +#include <linux/init.h>
45157 +#include <linux/module.h>
45158 +#include <linux/platform_device.h>
45159 +#include <linux/proc_fs.h>
45160 +#include <linux/string.h>
45161 +#include <linux/uaccess.h>
45162 +#include <asm/io.h>
45163 +
45164 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45165 +#include <linux/rslib.h>
45166 +#endif
45167 +
45168 +struct ram_console_buffer {
45169 +       uint32_t    sig;
45170 +       uint32_t    start;
45171 +       uint32_t    size;
45172 +       uint8_t     data[0];
45173 +};
45174 +
45175 +#define RAM_CONSOLE_SIG (0x43474244) /* DBGC */
45176 +
45177 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
45178 +static char __initdata
45179 +       ram_console_old_log_init_buffer[CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE];
45180 +#endif
45181 +static char *ram_console_old_log;
45182 +static size_t ram_console_old_log_size;
45183 +
45184 +static struct ram_console_buffer *ram_console_buffer;
45185 +static size_t ram_console_buffer_size;
45186 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45187 +static char *ram_console_par_buffer;
45188 +static struct rs_control *ram_console_rs_decoder;
45189 +static int ram_console_corrected_bytes;
45190 +static int ram_console_bad_blocks;
45191 +#define ECC_BLOCK_SIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE
45192 +#define ECC_SIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE
45193 +#define ECC_SYMSIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE
45194 +#define ECC_POLY CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL
45195 +#endif
45196 +
45197 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45198 +static void ram_console_encode_rs8(uint8_t *data, size_t len, uint8_t *ecc)
45199 +{
45200 +       int i;
45201 +       uint16_t par[ECC_SIZE];
45202 +       /* Initialize the parity buffer */
45203 +       memset(par, 0, sizeof(par));
45204 +       encode_rs8(ram_console_rs_decoder, data, len, par, 0);
45205 +       for (i = 0; i < ECC_SIZE; i++)
45206 +               ecc[i] = par[i];
45207 +}
45208 +
45209 +static int ram_console_decode_rs8(void *data, size_t len, uint8_t *ecc)
45210 +{
45211 +       int i;
45212 +       uint16_t par[ECC_SIZE];
45213 +       for (i = 0; i < ECC_SIZE; i++)
45214 +               par[i] = ecc[i];
45215 +       return decode_rs8(ram_console_rs_decoder, data, par, len,
45216 +                               NULL, 0, NULL, 0, NULL);
45217 +}
45218 +#endif
45219 +
45220 +static void ram_console_update(const char *s, unsigned int count)
45221 +{
45222 +       struct ram_console_buffer *buffer = ram_console_buffer;
45223 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45224 +       uint8_t *buffer_end = buffer->data + ram_console_buffer_size;
45225 +       uint8_t *block;
45226 +       uint8_t *par;
45227 +       int size = ECC_BLOCK_SIZE;
45228 +#endif
45229 +       memcpy(buffer->data + buffer->start, s, count);
45230 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45231 +       block = buffer->data + (buffer->start & ~(ECC_BLOCK_SIZE - 1));
45232 +       par = ram_console_par_buffer +
45233 +             (buffer->start / ECC_BLOCK_SIZE) * ECC_SIZE;
45234 +       do {
45235 +               if (block + ECC_BLOCK_SIZE > buffer_end)
45236 +                       size = buffer_end - block;
45237 +               ram_console_encode_rs8(block, size, par);
45238 +               block += ECC_BLOCK_SIZE;
45239 +               par += ECC_SIZE;
45240 +       } while (block < buffer->data + buffer->start + count);
45241 +#endif
45242 +}
45243 +
45244 +static void ram_console_update_header(void)
45245 +{
45246 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45247 +       struct ram_console_buffer *buffer = ram_console_buffer;
45248 +       uint8_t *par;
45249 +       par = ram_console_par_buffer +
45250 +             DIV_ROUND_UP(ram_console_buffer_size, ECC_BLOCK_SIZE) * ECC_SIZE;
45251 +       ram_console_encode_rs8((uint8_t *)buffer, sizeof(*buffer), par);
45252 +#endif
45253 +}
45254 +
45255 +static void
45256 +ram_console_write(struct console *console, const char *s, unsigned int count)
45257 +{
45258 +       int rem;
45259 +       struct ram_console_buffer *buffer = ram_console_buffer;
45260 +
45261 +       if (count > ram_console_buffer_size) {
45262 +               s += count - ram_console_buffer_size;
45263 +               count = ram_console_buffer_size;
45264 +       }
45265 +       rem = ram_console_buffer_size - buffer->start;
45266 +       if (rem < count) {
45267 +               ram_console_update(s, rem);
45268 +               s += rem;
45269 +               count -= rem;
45270 +               buffer->start = 0;
45271 +               buffer->size = ram_console_buffer_size;
45272 +       }
45273 +       ram_console_update(s, count);
45274 +
45275 +       buffer->start += count;
45276 +       if (buffer->size < ram_console_buffer_size)
45277 +               buffer->size += count;
45278 +       ram_console_update_header();
45279 +}
45280 +
45281 +static struct console ram_console = {
45282 +       .name   = "ram",
45283 +       .write  = ram_console_write,
45284 +       .flags  = CON_PRINTBUFFER | CON_ENABLED,
45285 +       .index  = -1,
45286 +};
45287 +
45288 +static void __init
45289 +ram_console_save_old(struct ram_console_buffer *buffer, char *dest)
45290 +{
45291 +       size_t old_log_size = buffer->size;
45292 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45293 +       uint8_t *block;
45294 +       uint8_t *par;
45295 +       char strbuf[80];
45296 +       int strbuf_len;
45297 +
45298 +       block = buffer->data;
45299 +       par = ram_console_par_buffer;
45300 +       while (block < buffer->data + buffer->size) {
45301 +               int numerr;
45302 +               int size = ECC_BLOCK_SIZE;
45303 +               if (block + size > buffer->data + ram_console_buffer_size)
45304 +                       size = buffer->data + ram_console_buffer_size - block;
45305 +               numerr = ram_console_decode_rs8(block, size, par);
45306 +               if (numerr > 0) {
45307 +#if 0
45308 +                       printk(KERN_INFO "ram_console: error in block %p, %d\n",
45309 +                              block, numerr);
45310 +#endif
45311 +                       ram_console_corrected_bytes += numerr;
45312 +               } else if (numerr < 0) {
45313 +#if 0
45314 +                       printk(KERN_INFO "ram_console: uncorrectable error in "
45315 +                              "block %p\n", block);
45316 +#endif
45317 +                       ram_console_bad_blocks++;
45318 +               }
45319 +               block += ECC_BLOCK_SIZE;
45320 +               par += ECC_SIZE;
45321 +       }
45322 +       if (ram_console_corrected_bytes || ram_console_bad_blocks)
45323 +               strbuf_len = snprintf(strbuf, sizeof(strbuf),
45324 +                       "\n%d Corrected bytes, %d unrecoverable blocks\n",
45325 +                       ram_console_corrected_bytes, ram_console_bad_blocks);
45326 +       else
45327 +               strbuf_len = snprintf(strbuf, sizeof(strbuf),
45328 +                                     "\nNo errors detected\n");
45329 +       if (strbuf_len >= sizeof(strbuf))
45330 +               strbuf_len = sizeof(strbuf) - 1;
45331 +       old_log_size += strbuf_len;
45332 +#endif
45333 +
45334 +       if (dest == NULL) {
45335 +               dest = kmalloc(old_log_size, GFP_KERNEL);
45336 +               if (dest == NULL) {
45337 +                       printk(KERN_ERR
45338 +                              "ram_console: failed to allocate buffer\n");
45339 +                       return;
45340 +               }
45341 +       }
45342 +
45343 +       ram_console_old_log = dest;
45344 +       ram_console_old_log_size = old_log_size;
45345 +       memcpy(ram_console_old_log,
45346 +              &buffer->data[buffer->start], buffer->size - buffer->start);
45347 +       memcpy(ram_console_old_log + buffer->size - buffer->start,
45348 +              &buffer->data[0], buffer->start);
45349 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45350 +       memcpy(ram_console_old_log + old_log_size - strbuf_len,
45351 +              strbuf, strbuf_len);
45352 +#endif
45353 +}
45354 +
45355 +static int __init ram_console_init(struct ram_console_buffer *buffer,
45356 +                                  size_t buffer_size, char *old_buf)
45357 +{
45358 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45359 +       int numerr;
45360 +       uint8_t *par;
45361 +#endif
45362 +       ram_console_buffer = buffer;
45363 +       ram_console_buffer_size =
45364 +               buffer_size - sizeof(struct ram_console_buffer);
45365 +
45366 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
45367 +       ram_console_buffer_size -= (DIV_ROUND_UP(ram_console_buffer_size,
45368 +                                               ECC_BLOCK_SIZE) + 1) * ECC_SIZE;
45369 +       ram_console_par_buffer = buffer->data + ram_console_buffer_size;
45370 +
45371 +
45372 +       /* first consecutive root is 0
45373 +        * primitive element to generate roots = 1
45374 +        */
45375 +       ram_console_rs_decoder = init_rs(ECC_SYMSIZE, ECC_POLY, 0, 1, ECC_SIZE);
45376 +       if (ram_console_rs_decoder == NULL) {
45377 +               printk(KERN_INFO "ram_console: init_rs failed\n");
45378 +               return 0;
45379 +       }
45380 +
45381 +       ram_console_corrected_bytes = 0;
45382 +       ram_console_bad_blocks = 0;
45383 +
45384 +       par = ram_console_par_buffer +
45385 +             DIV_ROUND_UP(ram_console_buffer_size, ECC_BLOCK_SIZE) * ECC_SIZE;
45386 +
45387 +       numerr = ram_console_decode_rs8(buffer, sizeof(*buffer), par);
45388 +       if (numerr > 0) {
45389 +               printk(KERN_INFO "ram_console: error in header, %d\n", numerr);
45390 +               ram_console_corrected_bytes += numerr;
45391 +       } else if (numerr < 0) {
45392 +               printk(KERN_INFO
45393 +                      "ram_console: uncorrectable error in header\n");
45394 +               ram_console_bad_blocks++;
45395 +       }
45396 +#endif
45397 +
45398 +       if (buffer->sig == RAM_CONSOLE_SIG) {
45399 +               if (buffer->size > ram_console_buffer_size
45400 +                   || buffer->start > buffer->size)
45401 +                       printk(KERN_INFO "ram_console: found existing invalid "
45402 +                              "buffer, size %d, start %d\n",
45403 +                              buffer->size, buffer->start);
45404 +               else {
45405 +                       printk(KERN_INFO "ram_console: found existing buffer, "
45406 +                              "size %d, start %d\n",
45407 +                              buffer->size, buffer->start);
45408 +                       ram_console_save_old(buffer, old_buf);
45409 +               }
45410 +       } else {
45411 +               printk(KERN_INFO "ram_console: no valid data in buffer "
45412 +                      "(sig = 0x%08x)\n", buffer->sig);
45413 +       }
45414 +
45415 +       buffer->sig = RAM_CONSOLE_SIG;
45416 +       buffer->start = 0;
45417 +       buffer->size = 0;
45418 +
45419 +       register_console(&ram_console);
45420 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE
45421 +       console_verbose();
45422 +#endif
45423 +       return 0;
45424 +}
45425 +
45426 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
45427 +static int __init ram_console_early_init(void)
45428 +{
45429 +       return ram_console_init((struct ram_console_buffer *)
45430 +               CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR,
45431 +               CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE,
45432 +               ram_console_old_log_init_buffer);
45433 +}
45434 +#else
45435 +static int ram_console_driver_probe(struct platform_device *pdev)
45436 +{
45437 +       struct resource *res = pdev->resource;
45438 +       size_t start;
45439 +       size_t buffer_size;
45440 +       void *buffer;
45441 +
45442 +       if (res == NULL || pdev->num_resources != 1 ||
45443 +           !(res->flags & IORESOURCE_MEM)) {
45444 +               printk(KERN_ERR "ram_console: invalid resource, %p %d flags "
45445 +                      "%lx\n", res, pdev->num_resources, res ? res->flags : 0);
45446 +               return -ENXIO;
45447 +       }
45448 +       buffer_size = res->end - res->start + 1;
45449 +       start = res->start;
45450 +       printk(KERN_INFO "ram_console: got buffer at %x, size %x\n",
45451 +              start, buffer_size);
45452 +       buffer = ioremap(res->start, buffer_size);
45453 +       if (buffer == NULL) {
45454 +               printk(KERN_ERR "ram_console: failed to map memory\n");
45455 +               return -ENOMEM;
45456 +       }
45457 +
45458 +       return ram_console_init(buffer, buffer_size, NULL/* allocate */);
45459 +}
45460 +
45461 +static struct platform_driver ram_console_driver = {
45462 +       .probe = ram_console_driver_probe,
45463 +       .driver         = {
45464 +               .name   = "ram_console",
45465 +       },
45466 +};
45467 +
45468 +static int __init ram_console_module_init(void)
45469 +{
45470 +       int err;
45471 +       err = platform_driver_register(&ram_console_driver);
45472 +       return err;
45473 +}
45474 +#endif
45475 +
45476 +static ssize_t ram_console_read_old(struct file *file, char __user *buf,
45477 +                                   size_t len, loff_t *offset)
45478 +{
45479 +       loff_t pos = *offset;
45480 +       ssize_t count;
45481 +
45482 +       if (pos >= ram_console_old_log_size)
45483 +               return 0;
45484 +
45485 +       count = min(len, (size_t)(ram_console_old_log_size - pos));
45486 +       if (copy_to_user(buf, ram_console_old_log + pos, count))
45487 +               return -EFAULT;
45488 +
45489 +       *offset += count;
45490 +       return count;
45491 +}
45492 +
45493 +static struct file_operations ram_console_file_ops = {
45494 +       .owner = THIS_MODULE,
45495 +       .read = ram_console_read_old,
45496 +};
45497 +
45498 +static int __init ram_console_late_init(void)
45499 +{
45500 +       struct proc_dir_entry *entry;
45501 +
45502 +       if (ram_console_old_log == NULL)
45503 +               return 0;
45504 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
45505 +       ram_console_old_log = kmalloc(ram_console_old_log_size, GFP_KERNEL);
45506 +       if (ram_console_old_log == NULL) {
45507 +               printk(KERN_ERR
45508 +                      "ram_console: failed to allocate buffer for old log\n");
45509 +               ram_console_old_log_size = 0;
45510 +               return 0;
45511 +       }
45512 +       memcpy(ram_console_old_log,
45513 +              ram_console_old_log_init_buffer, ram_console_old_log_size);
45514 +#endif
45515 +       entry = create_proc_entry("last_kmsg", S_IFREG | S_IRUGO, NULL);
45516 +       if (!entry) {
45517 +               printk(KERN_ERR "ram_console: failed to create proc entry\n");
45518 +               kfree(ram_console_old_log);
45519 +               ram_console_old_log = NULL;
45520 +               return 0;
45521 +       }
45522 +
45523 +       entry->proc_fops = &ram_console_file_ops;
45524 +       entry->size = ram_console_old_log_size;
45525 +       return 0;
45526 +}
45527 +
45528 +#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
45529 +console_initcall(ram_console_early_init);
45530 +#else
45531 +module_init(ram_console_module_init);
45532 +#endif
45533 +late_initcall(ram_console_late_init);
45534 +
45535 Index: linux-2.6.28/drivers/android/timed_gpio.c
45536 ===================================================================
45537 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
45538 +++ linux-2.6.28/drivers/android/timed_gpio.c   2009-01-02 00:01:56.000000000 +0100
45539 @@ -0,0 +1,177 @@
45540 +/* drivers/android/timed_gpio.c
45541 + *
45542 + * Copyright (C) 2008 Google, Inc.
45543 + * Author: Mike Lockwood <lockwood@android.com>
45544 + *
45545 + * This software is licensed under the terms of the GNU General Public
45546 + * License version 2, as published by the Free Software Foundation, and
45547 + * may be copied, distributed, and modified under those terms.
45548 + *
45549 + * This program is distributed in the hope that it will be useful,
45550 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
45551 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
45552 + * GNU General Public License for more details.
45553 + *
45554 + */
45555 +
45556 +#include <linux/module.h>
45557 +#include <linux/platform_device.h>
45558 +#include <linux/hrtimer.h>
45559 +#include <linux/err.h>
45560 +#include <mach/gpio.h>
45561 +
45562 +#include <linux/android_timed_gpio.h>
45563 +
45564 +
45565 +static struct class *timed_gpio_class;
45566 +
45567 +struct timed_gpio_data {
45568 +       struct device *dev;
45569 +       struct hrtimer timer;
45570 +       spinlock_t lock;
45571 +       unsigned        gpio;
45572 +       int             max_timeout;
45573 +       u8              active_low;
45574 +};
45575 +
45576 +static enum hrtimer_restart gpio_timer_func(struct hrtimer *timer)
45577 +{
45578 +       struct timed_gpio_data *gpio_data = container_of(timer, struct timed_gpio_data, timer);
45579 +
45580 +       gpio_direction_output(gpio_data->gpio, gpio_data->active_low ? 1 : 0);
45581 +       return HRTIMER_NORESTART;
45582 +}
45583 +
45584 +static ssize_t gpio_enable_show(struct device *dev, struct device_attribute *attr, char *buf)
45585 +{
45586 +       struct timed_gpio_data *gpio_data = dev_get_drvdata(dev);
45587 +       int remaining;
45588 +
45589 +       if (hrtimer_active(&gpio_data->timer)) {
45590 +               ktime_t r = hrtimer_get_remaining(&gpio_data->timer);
45591 +               remaining = r.tv.sec * 1000 + r.tv.nsec / 1000000;
45592 +       } else
45593 +               remaining = 0;
45594 +
45595 +       return sprintf(buf, "%d\n", remaining);
45596 +}
45597 +
45598 +static ssize_t gpio_enable_store(
45599 +               struct device *dev, struct device_attribute *attr,
45600 +               const char *buf, size_t size)
45601 +{
45602 +       struct timed_gpio_data *gpio_data = dev_get_drvdata(dev);
45603 +       int value;
45604 +       unsigned long   flags;
45605 +
45606 +       sscanf(buf, "%d", &value);
45607 +
45608 +       spin_lock_irqsave(&gpio_data->lock, flags);
45609 +
45610 +       /* cancel previous timer and set GPIO according to value */
45611 +       hrtimer_cancel(&gpio_data->timer);
45612 +       gpio_direction_output(gpio_data->gpio, gpio_data->active_low ? !value : !!value);
45613 +
45614 +       if (value > 0) {
45615 +               if (value > gpio_data->max_timeout)
45616 +                       value = gpio_data->max_timeout;
45617 +
45618 +               hrtimer_start(&gpio_data->timer,
45619 +                                               ktime_set(value / 1000, (value % 1000) * 1000000),
45620 +                                               HRTIMER_MODE_REL);
45621 +       }
45622 +
45623 +       spin_unlock_irqrestore(&gpio_data->lock, flags);
45624 +
45625 +       return size;
45626 +}
45627 +
45628 +static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, gpio_enable_show, gpio_enable_store);
45629 +
45630 +static int android_timed_gpio_probe(struct platform_device *pdev)
45631 +{
45632 +       struct timed_gpio_platform_data *pdata = pdev->dev.platform_data;
45633 +       struct timed_gpio *cur_gpio;
45634 +       struct timed_gpio_data *gpio_data, *gpio_dat;
45635 +       int i, ret = 0;
45636 +
45637 +       if (!pdata)
45638 +               return -EBUSY;
45639 +
45640 +       gpio_data = kzalloc(sizeof(struct timed_gpio_data) * pdata->num_gpios, GFP_KERNEL);
45641 +       if (!gpio_data)
45642 +               return -ENOMEM;
45643 +
45644 +       for (i = 0; i < pdata->num_gpios; i++) {
45645 +               cur_gpio = &pdata->gpios[i];
45646 +               gpio_dat = &gpio_data[i];
45647 +
45648 +               hrtimer_init(&gpio_dat->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
45649 +               gpio_dat->timer.function = gpio_timer_func;
45650 +               spin_lock_init(&gpio_dat->lock);
45651 +
45652 +               gpio_dat->gpio = cur_gpio->gpio;
45653 +               gpio_dat->max_timeout = cur_gpio->max_timeout;
45654 +               gpio_dat->active_low = cur_gpio->active_low;
45655 +               gpio_direction_output(gpio_dat->gpio, gpio_dat->active_low);
45656 +
45657 +               gpio_dat->dev = device_create(timed_gpio_class, &pdev->dev, 0, "%s", cur_gpio->name);
45658 +               if (unlikely(IS_ERR(gpio_dat->dev)))
45659 +                       return PTR_ERR(gpio_dat->dev);
45660 +
45661 +               dev_set_drvdata(gpio_dat->dev, gpio_dat);
45662 +               ret = device_create_file(gpio_dat->dev, &dev_attr_enable);
45663 +               if (ret)
45664 +                       return ret;
45665 +       }
45666 +
45667 +       platform_set_drvdata(pdev, gpio_data);
45668 +
45669 +       return 0;
45670 +}
45671 +
45672 +static int android_timed_gpio_remove(struct platform_device *pdev)
45673 +{
45674 +       struct timed_gpio_platform_data *pdata = pdev->dev.platform_data;
45675 +       struct timed_gpio_data *gpio_data = platform_get_drvdata(pdev);
45676 +       int i;
45677 +
45678 +       for (i = 0; i < pdata->num_gpios; i++) {
45679 +               device_remove_file(gpio_data[i].dev, &dev_attr_enable);
45680 +               device_unregister(gpio_data[i].dev);
45681 +       }
45682 +
45683 +       kfree(gpio_data);
45684 +
45685 +       return 0;
45686 +}
45687 +
45688 +static struct platform_driver android_timed_gpio_driver = {
45689 +       .probe          = android_timed_gpio_probe,
45690 +       .remove         = android_timed_gpio_remove,
45691 +       .driver         = {
45692 +               .name           = "android-timed-gpio",
45693 +               .owner          = THIS_MODULE,
45694 +       },
45695 +};
45696 +
45697 +static int __init android_timed_gpio_init(void)
45698 +{
45699 +       timed_gpio_class = class_create(THIS_MODULE, "timed_output");
45700 +       if (IS_ERR(timed_gpio_class))
45701 +               return PTR_ERR(timed_gpio_class);
45702 +       return platform_driver_register(&android_timed_gpio_driver);
45703 +}
45704 +
45705 +static void __exit android_timed_gpio_exit(void)
45706 +{
45707 +       class_destroy(timed_gpio_class);
45708 +       platform_driver_unregister(&android_timed_gpio_driver);
45709 +}
45710 +
45711 +module_init(android_timed_gpio_init);
45712 +module_exit(android_timed_gpio_exit);
45713 +
45714 +MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>");
45715 +MODULE_DESCRIPTION("Android timed gpio driver");
45716 +MODULE_LICENSE("GPL");
45717 Index: linux-2.6.28/drivers/ar6000/ar6000/ar6000_drv.c
45718 ===================================================================
45719 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
45720 +++ linux-2.6.28/drivers/ar6000/ar6000/ar6000_drv.c     2009-01-02 00:01:56.000000000 +0100
45721 @@ -0,0 +1,3124 @@
45722 +/*
45723 + *
45724 + * Copyright (c) 2004-2007 Atheros Communications Inc.
45725 + * All rights reserved.
45726 + *
45727 + *
45728 + *  This program is free software; you can redistribute it and/or modify
45729 + *  it under the terms of the GNU General Public License version 2 as
45730 + *  published by the Free Software Foundation;
45731 + *
45732 + *  Software distributed under the License is distributed on an "AS
45733 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
45734 + *  implied. See the License for the specific language governing
45735 + *  rights and limitations under the License.
45736 + *
45737 + *
45738 + *
45739 + */
45740 +
45741 +/*
45742 + * This driver is a pseudo ethernet driver to access the Atheros AR6000
45743 + * WLAN Device
45744 + */
45745 +static const char athId[] __attribute__ ((unused)) = "$Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/ar6000_drv.c#2 $";
45746 +
45747 +#include "ar6000_drv.h"
45748 +#include "htc.h"
45749 +
45750 +MODULE_LICENSE("GPL and additional rights");
45751 +
45752 +#ifndef REORG_APTC_HEURISTICS
45753 +#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45754 +#endif /* REORG_APTC_HEURISTICS */
45755 +
45756 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45757 +#define APTC_TRAFFIC_SAMPLING_INTERVAL     100  /* msec */
45758 +#define APTC_UPPER_THROUGHPUT_THRESHOLD    3000 /* Kbps */
45759 +#define APTC_LOWER_THROUGHPUT_THRESHOLD    2000 /* Kbps */
45760 +
45761 +typedef struct aptc_traffic_record {
45762 +    A_BOOL timerScheduled;
45763 +    struct timeval samplingTS;
45764 +    unsigned long bytesReceived;
45765 +    unsigned long bytesTransmitted;
45766 +} APTC_TRAFFIC_RECORD;
45767 +
45768 +A_TIMER aptcTimer;
45769 +APTC_TRAFFIC_RECORD aptcTR;
45770 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45771 +
45772 +int bmienable = 0;
45773 +unsigned int bypasswmi = 0;
45774 +unsigned int debuglevel = 0;
45775 +int tspecCompliance = 1;
45776 +unsigned int busspeedlow = 0;
45777 +unsigned int onebitmode = 0;
45778 +unsigned int skipflash = 0;
45779 +unsigned int wmitimeout = 2;
45780 +unsigned int wlanNodeCaching = 1;
45781 +unsigned int enableuartprint = 0;
45782 +unsigned int logWmiRawMsgs = 0;
45783 +unsigned int enabletimerwar = 0;
45784 +unsigned int mbox_yield_limit = 99;
45785 +int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF;
45786 +int allow_trace_signal = 0;
45787 +#ifdef CONFIG_HOST_TCMD_SUPPORT
45788 +unsigned int testmode =0;
45789 +#endif
45790 +
45791 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45792 +module_param(bmienable, int, 0644);
45793 +module_param(bypasswmi, int, 0644);
45794 +module_param(debuglevel, int, 0644);
45795 +module_param(tspecCompliance, int, 0644);
45796 +module_param(onebitmode, int, 0644);
45797 +module_param(busspeedlow, int, 0644);
45798 +module_param(skipflash, int, 0644);
45799 +module_param(wmitimeout, int, 0644);
45800 +module_param(wlanNodeCaching, int, 0644);
45801 +module_param(logWmiRawMsgs, int, 0644);
45802 +module_param(enableuartprint, int, 0644);
45803 +module_param(enabletimerwar, int, 0644);
45804 +module_param(mbox_yield_limit, int, 0644);
45805 +module_param(reduce_credit_dribble, int, 0644);
45806 +module_param(allow_trace_signal, int, 0644);
45807 +#ifdef CONFIG_HOST_TCMD_SUPPORT
45808 +module_param(testmode, int, 0644);
45809 +#endif
45810 +#else
45811 +
45812 +#define __user
45813 +/* for linux 2.4 and lower */
45814 +MODULE_PARM(bmienable,"i");
45815 +MODULE_PARM(bypasswmi,"i");
45816 +MODULE_PARM(debuglevel, "i");
45817 +MODULE_PARM(onebitmode,"i");
45818 +MODULE_PARM(busspeedlow, "i");
45819 +MODULE_PARM(skipflash, "i");
45820 +MODULE_PARM(wmitimeout, "i");
45821 +MODULE_PARM(wlanNodeCaching, "i");
45822 +MODULE_PARM(enableuartprint,"i");
45823 +MODULE_PARM(logWmiRawMsgs, "i");
45824 +MODULE_PARM(enabletimerwar,"i");
45825 +MODULE_PARM(mbox_yield_limit,"i");
45826 +MODULE_PARM(reduce_credit_dribble,"i");
45827 +MODULE_PARM(allow_trace_signal,"i");
45828 +#ifdef CONFIG_HOST_TCMD_SUPPORT
45829 +MODULE_PARM(testmode, "i");
45830 +#endif
45831 +#endif
45832 +
45833 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)
45834 +/* in 2.6.10 and later this is now a pointer to a uint */
45835 +unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
45836 +#define mboxnum &_mboxnum
45837 +#else
45838 +unsigned int mboxnum = HTC_MAILBOX_NUM_MAX;
45839 +#endif
45840 +
45841 +#ifdef DEBUG
45842 +A_UINT32 g_dbg_flags = DBG_DEFAULTS;
45843 +unsigned int debugflags = 0;
45844 +int debugdriver = 1;
45845 +unsigned int debughtc = 128;
45846 +unsigned int debugbmi = 1;
45847 +unsigned int debughif = 2;
45848 +unsigned int resetok = 1;
45849 +unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0};
45850 +unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0};
45851 +unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0};
45852 +unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0};
45853 +
45854 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45855 +module_param(debugflags, int, 0644);
45856 +module_param(debugdriver, int, 0644);
45857 +module_param(debughtc, int, 0644);
45858 +module_param(debugbmi, int, 0644);
45859 +module_param(debughif, int, 0644);
45860 +module_param(resetok, int, 0644);
45861 +module_param_array(txcreditsavailable, int, mboxnum, 0644);
45862 +module_param_array(txcreditsconsumed, int, mboxnum, 0644);
45863 +module_param_array(txcreditintrenable, int, mboxnum, 0644);
45864 +module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644);
45865 +#else
45866 +/* linux 2.4 and lower */
45867 +MODULE_PARM(debugflags,"i");
45868 +MODULE_PARM(debugdriver, "i");
45869 +MODULE_PARM(debughtc, "i");
45870 +MODULE_PARM(debugbmi, "i");
45871 +MODULE_PARM(debughif, "i");
45872 +MODULE_PARM(resetok, "i");
45873 +MODULE_PARM(txcreditsavailable, "0-3i");
45874 +MODULE_PARM(txcreditsconsumed, "0-3i");
45875 +MODULE_PARM(txcreditintrenable, "0-3i");
45876 +MODULE_PARM(txcreditintrenableaggregate, "0-3i");
45877 +#endif
45878 +
45879 +#else
45880 +unsigned int resetok = 1;
45881 +
45882 +#endif /* DEBUG */
45883 +
45884 +unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0};
45885 +unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0};
45886 +unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0};
45887 +unsigned int hifBusRequestNumMax = 40;
45888 +unsigned int war23838_disabled = 0;
45889 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45890 +unsigned int enableAPTCHeuristics = 1;
45891 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45892 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45893 +module_param_array(tx_attempt, int, mboxnum, 0644);
45894 +module_param_array(tx_post, int, mboxnum, 0644);
45895 +module_param_array(tx_complete, int, mboxnum, 0644);
45896 +module_param(hifBusRequestNumMax, int, 0644);
45897 +module_param(war23838_disabled, int, 0644);
45898 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45899 +module_param(enableAPTCHeuristics, int, 0644);
45900 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45901 +#else
45902 +MODULE_PARM(tx_attempt, "0-3i");
45903 +MODULE_PARM(tx_post, "0-3i");
45904 +MODULE_PARM(tx_complete, "0-3i");
45905 +MODULE_PARM(hifBusRequestNumMax, "i");
45906 +MODULE_PARM(war23838_disabled, "i");
45907 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
45908 +MODULE_PARM(enableAPTCHeuristics, "i");
45909 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
45910 +#endif
45911 +
45912 +#ifdef BLOCK_TX_PATH_FLAG
45913 +int blocktx = 0;
45914 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
45915 +module_param(blocktx, int, 0644);
45916 +#else
45917 +MODULE_PARM(blocktx, "i");
45918 +#endif
45919 +#endif /* BLOCK_TX_PATH_FLAG */
45920 +
45921 +// TODO move to arsoft_c
45922 +USER_RSSI_THOLD rssi_map[12];
45923 +
45924 +int reconnect_flag = 0;
45925 +
45926 +DECLARE_WAIT_QUEUE_HEAD(ar6000_scan_queue);
45927 +
45928 +/* Function declarations */
45929 +static int ar6000_init_module(void);
45930 +static void ar6000_cleanup_module(void);
45931 +
45932 +int ar6000_init(struct net_device *dev);
45933 +static int ar6000_open(struct net_device *dev);
45934 +static int ar6000_close(struct net_device *dev);
45935 +static void ar6000_init_control_info(AR_SOFTC_T *ar);
45936 +static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev);
45937 +
45938 +static void ar6000_destroy(struct net_device *dev, unsigned int unregister);
45939 +static void ar6000_detect_error(unsigned long ptr);
45940 +static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
45941 +static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev);
45942 +
45943 +/*
45944 + * HTC service connection handlers
45945 + */
45946 +static void ar6000_avail_ev(HTC_HANDLE HTCHandle);
45947 +
45948 +static void ar6000_unavail_ev(void *Instance);
45949 +
45950 +static void ar6000_target_failure(void *Instance, A_STATUS Status);
45951 +
45952 +static void ar6000_rx(void *Context, HTC_PACKET *pPacket);
45953 +
45954 +static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint);
45955 +
45956 +static void ar6000_tx_complete(void *Context, HTC_PACKET *pPacket);
45957 +
45958 +static void ar6000_tx_queue_full(void *Context, HTC_ENDPOINT_ID Endpoint);
45959 +
45960 +/*
45961 + * Static variables
45962 + */
45963 +
45964 +static struct net_device *ar6000_devices[MAX_AR6000];
45965 +extern struct iw_handler_def ath_iw_handler_def;
45966 +DECLARE_WAIT_QUEUE_HEAD(arEvent);
45967 +static void ar6000_cookie_init(AR_SOFTC_T *ar);
45968 +static void ar6000_cookie_cleanup(AR_SOFTC_T *ar);
45969 +static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie);
45970 +static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar);
45971 +static void ar6000_TxDataCleanup(AR_SOFTC_T *ar);
45972 +
45973 +#ifdef USER_KEYS
45974 +static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl);
45975 +#endif
45976 +
45977 +
45978 +static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
45979 +
45980 +#define HOST_INTEREST_ITEM_ADDRESS(ar, item)    \
45981 +((ar->arTargetType == TARGET_TYPE_AR6001) ?     \
45982 +   AR6001_HOST_INTEREST_ITEM_ADDRESS(item) :    \
45983 +   AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
45984 +
45985 +
45986 +/* Debug log support */
45987 +
45988 +/*
45989 + * Flag to govern whether the debug logs should be parsed in the kernel
45990 + * or reported to the application.
45991 + */
45992 +#ifdef DEBUG
45993 +#define REPORT_DEBUG_LOGS_TO_APP
45994 +#endif
45995 +
45996 +A_STATUS
45997 +ar6000_set_host_app_area(AR_SOFTC_T *ar)
45998 +{
45999 +    A_UINT32 address, data;
46000 +    struct host_app_area_s host_app_area;
46001 +
46002 +    /* Fetch the address of the host_app_area_s instance in the host interest area */
46003 +    address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest);
46004 +    if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) {
46005 +        return A_ERROR;
46006 +    }
46007 +    address = data;
46008 +    host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION;
46009 +    if (ar6000_WriteDataDiag(ar->arHifDevice, address,
46010 +                             (A_UCHAR *)&host_app_area,
46011 +                             sizeof(struct host_app_area_s)) != A_OK)
46012 +    {
46013 +        return A_ERROR;
46014 +    }
46015 +
46016 +    return A_OK;
46017 +}
46018 +
46019 +A_UINT32
46020 +dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar)
46021 +{
46022 +    A_UINT32 param;
46023 +    A_UINT32 address;
46024 +    A_STATUS status;
46025 +
46026 +    address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr);
46027 +    if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address,
46028 +                                      (A_UCHAR *)&param, 4)) != A_OK)
46029 +    {
46030 +        param = 0;
46031 +    }
46032 +
46033 +    return param;
46034 +}
46035 +
46036 +/*
46037 + * The dbglog module has been initialized. Its ok to access the relevant
46038 + * data stuctures over the diagnostic window.
46039 + */
46040 +void
46041 +ar6000_dbglog_init_done(AR_SOFTC_T *ar)
46042 +{
46043 +    ar->dbglog_init_done = TRUE;
46044 +}
46045 +
46046 +A_UINT32
46047 +dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit)
46048 +{
46049 +    A_INT32 *buffer;
46050 +    A_UINT32 count;
46051 +    A_UINT32 numargs;
46052 +    A_UINT32 length;
46053 +    A_UINT32 fraglen;
46054 +
46055 +    count = fraglen = 0;
46056 +    buffer = (A_INT32 *)datap;
46057 +    length = (limit >> 2);
46058 +
46059 +    if (len <= limit) {
46060 +        fraglen = len;
46061 +    } else {
46062 +        while (count < length) {
46063 +            numargs = DBGLOG_GET_NUMARGS(buffer[count]);
46064 +            fraglen = (count << 2);
46065 +            count += numargs + 1;
46066 +        }
46067 +    }
46068 +
46069 +    return fraglen;
46070 +}
46071 +
46072 +void
46073 +dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len)
46074 +{
46075 +    A_INT32 *buffer;
46076 +    A_UINT32 count;
46077 +    A_UINT32 timestamp;
46078 +    A_UINT32 debugid;
46079 +    A_UINT32 moduleid;
46080 +    A_UINT32 numargs;
46081 +    A_UINT32 length;
46082 +
46083 +    count = 0;
46084 +    buffer = (A_INT32 *)datap;
46085 +    length = (len >> 2);
46086 +    while (count < length) {
46087 +        debugid = DBGLOG_GET_DBGID(buffer[count]);
46088 +        moduleid = DBGLOG_GET_MODULEID(buffer[count]);
46089 +        numargs = DBGLOG_GET_NUMARGS(buffer[count]);
46090 +        timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]);
46091 +        switch (numargs) {
46092 +            case 0:
46093 +            AR_DEBUG_PRINTF("%d %d (%d)\n", moduleid, debugid, timestamp);
46094 +            break;
46095 +
46096 +            case 1:
46097 +            AR_DEBUG_PRINTF("%d %d (%d): 0x%x\n", moduleid, debugid,
46098 +                            timestamp, buffer[count+1]);
46099 +            break;
46100 +
46101 +            case 2:
46102 +            AR_DEBUG_PRINTF("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid,
46103 +                            timestamp, buffer[count+1], buffer[count+2]);
46104 +            break;
46105 +
46106 +            default:
46107 +            AR_DEBUG_PRINTF("Invalid args: %d\n", numargs);
46108 +        }
46109 +        count += numargs + 1;
46110 +    }
46111 +}
46112 +
46113 +int
46114 +ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar)
46115 +{
46116 +    struct dbglog_hdr_s debug_hdr;
46117 +    struct dbglog_buf_s debug_buf;
46118 +    A_UINT32 address;
46119 +    A_UINT32 length;
46120 +    A_UINT32 dropped;
46121 +    A_UINT32 firstbuf;
46122 +    A_UINT32 debug_hdr_ptr;
46123 +
46124 +    if (!ar->dbglog_init_done) return A_ERROR;
46125 +
46126 +
46127 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
46128 +
46129 +    if (ar->dbgLogFetchInProgress) {
46130 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46131 +        return A_EBUSY;
46132 +    }
46133 +
46134 +        /* block out others */
46135 +    ar->dbgLogFetchInProgress = TRUE;
46136 +
46137 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46138 +
46139 +    debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar);
46140 +    printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr);
46141 +
46142 +    /* Get the contents of the ring buffer */
46143 +    if (debug_hdr_ptr) {
46144 +        address = debug_hdr_ptr;
46145 +        length = sizeof(struct dbglog_hdr_s);
46146 +        ar6000_ReadDataDiag(ar->arHifDevice, address,
46147 +                            (A_UCHAR *)&debug_hdr, length);
46148 +        address = (A_UINT32)debug_hdr.dbuf;
46149 +        firstbuf = address;
46150 +        dropped = debug_hdr.dropped;
46151 +        length = sizeof(struct dbglog_buf_s);
46152 +        ar6000_ReadDataDiag(ar->arHifDevice, address,
46153 +                            (A_UCHAR *)&debug_buf, length);
46154 +
46155 +        do {
46156 +            address = (A_UINT32)debug_buf.buffer;
46157 +            length = debug_buf.length;
46158 +            if ((length) && (debug_buf.length <= debug_buf.bufsize)) {
46159 +                /* Rewind the index if it is about to overrun the buffer */
46160 +                if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) {
46161 +                    ar->log_cnt = 0;
46162 +                }
46163 +                if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
46164 +                                    (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length))
46165 +                {
46166 +                    break;
46167 +                }
46168 +                ar6000_dbglog_event(ar, dropped, &ar->log_buffer[ar->log_cnt], length);
46169 +                ar->log_cnt += length;
46170 +            } else {
46171 +                AR_DEBUG_PRINTF("Length: %d (Total size: %d)\n",
46172 +                                debug_buf.length, debug_buf.bufsize);
46173 +            }
46174 +
46175 +            address = (A_UINT32)debug_buf.next;
46176 +            length = sizeof(struct dbglog_buf_s);
46177 +            if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
46178 +                                (A_UCHAR *)&debug_buf, length))
46179 +            {
46180 +                break;
46181 +            }
46182 +
46183 +        } while (address != firstbuf);
46184 +    }
46185 +
46186 +    ar->dbgLogFetchInProgress = FALSE;
46187 +
46188 +    return A_OK;
46189 +}
46190 +
46191 +void
46192 +ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped,
46193 +                    A_INT8 *buffer, A_UINT32 length)
46194 +{
46195 +#ifdef REPORT_DEBUG_LOGS_TO_APP
46196 +    #define MAX_WIRELESS_EVENT_SIZE 252
46197 +    /*
46198 +     * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages.
46199 +     * There seems to be a limitation on the length of message that could be
46200 +     * transmitted to the user app via this mechanism.
46201 +     */
46202 +    A_UINT32 send, sent;
46203 +
46204 +    sent = 0;
46205 +    send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
46206 +                                     MAX_WIRELESS_EVENT_SIZE);
46207 +    while (send) {
46208 +        ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, &buffer[sent], send);
46209 +        sent += send;
46210 +        send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
46211 +                                         MAX_WIRELESS_EVENT_SIZE);
46212 +    }
46213 +#else
46214 +    AR_DEBUG_PRINTF("Dropped logs: 0x%x\nDebug info length: %d\n",
46215 +                    dropped, length);
46216 +
46217 +    /* Interpret the debug logs */
46218 +    dbglog_parse_debug_logs(buffer, length);
46219 +#endif /* REPORT_DEBUG_LOGS_TO_APP */
46220 +}
46221 +
46222 +
46223 +
46224 +static int __init
46225 +ar6000_init_module(void)
46226 +{
46227 +    static int probed = 0;
46228 +    A_STATUS status;
46229 +    HTC_INIT_INFO initInfo;
46230 +
46231 +    A_MEMZERO(&initInfo,sizeof(initInfo));
46232 +    initInfo.AddInstance = ar6000_avail_ev;
46233 +    initInfo.DeleteInstance = ar6000_unavail_ev;
46234 +    initInfo.TargetFailure = ar6000_target_failure;
46235 +
46236 +
46237 +#ifdef DEBUG
46238 +    /* Set the debug flags if specified at load time */
46239 +    if(debugflags != 0)
46240 +    {
46241 +        g_dbg_flags = debugflags;
46242 +    }
46243 +#endif
46244 +
46245 +    if (probed) {
46246 +        return -ENODEV;
46247 +    }
46248 +    probed++;
46249 +
46250 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
46251 +    memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD));
46252 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
46253 +
46254 +#ifdef CONFIG_HOST_GPIO_SUPPORT
46255 +    ar6000_gpio_init();
46256 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
46257 +
46258 +    status = HTCInit(&initInfo);
46259 +    if(status != A_OK)
46260 +        return -ENODEV;
46261 +
46262 +    return 0;
46263 +}
46264 +
46265 +static void __exit
46266 +ar6000_cleanup_module(void)
46267 +{
46268 +    int i = 0;
46269 +    struct net_device *ar6000_netdev;
46270 +
46271 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
46272 +    /* Delete the Adaptive Power Control timer */
46273 +    if (timer_pending(&aptcTimer)) {
46274 +        del_timer_sync(&aptcTimer);
46275 +    }
46276 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
46277 +
46278 +    for (i=0; i < MAX_AR6000; i++) {
46279 +        if (ar6000_devices[i] != NULL) {
46280 +            ar6000_netdev = ar6000_devices[i];
46281 +            ar6000_devices[i] = NULL;
46282 +            ar6000_destroy(ar6000_netdev, 1);
46283 +        }
46284 +    }
46285 +
46286 +        /* shutting down HTC will cause the HIF layer to detach from the
46287 +         * underlying bus driver which will cause the subsequent deletion of
46288 +         * all HIF and HTC instances */
46289 +    HTCShutDown();
46290 +
46291 +    AR_DEBUG_PRINTF("ar6000_cleanup: success\n");
46292 +}
46293 +
46294 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
46295 +void
46296 +aptcTimerHandler(unsigned long arg)
46297 +{
46298 +    A_UINT32 numbytes;
46299 +    A_UINT32 throughput;
46300 +    AR_SOFTC_T *ar;
46301 +    A_STATUS status;
46302 +
46303 +    ar = (AR_SOFTC_T *)arg;
46304 +    A_ASSERT(ar != NULL);
46305 +    A_ASSERT(!timer_pending(&aptcTimer));
46306 +
46307 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
46308 +
46309 +    /* Get the number of bytes transferred */
46310 +    numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
46311 +    aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
46312 +
46313 +    /* Calculate and decide based on throughput thresholds */
46314 +    throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */
46315 +    if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) {
46316 +        /* Enable Sleep and delete the timer */
46317 +        A_ASSERT(ar->arWmiReady == TRUE);
46318 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46319 +        status = wmi_powermode_cmd(ar->arWmi, REC_POWER);
46320 +        AR6000_SPIN_LOCK(&ar->arLock, 0);
46321 +        A_ASSERT(status == A_OK);
46322 +        aptcTR.timerScheduled = FALSE;
46323 +    } else {
46324 +        A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
46325 +    }
46326 +
46327 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46328 +}
46329 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
46330 +
46331 +
46332 +
46333 +/* set HTC block size, assume BMI is already initialized */
46334 +A_STATUS ar6000_SetHTCBlockSize(AR_SOFTC_T *ar)
46335 +{
46336 +    A_STATUS status;
46337 +    A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
46338 +
46339 +    do {
46340 +            /* get the block sizes */
46341 +        status = HIFConfigureDevice(ar->arHifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
46342 +                                    blocksizes, sizeof(blocksizes));
46343 +
46344 +        if (A_FAILED(status)) {
46345 +            AR_DEBUG_PRINTF("Failed to get block size info from HIF layer...\n");
46346 +            break;
46347 +        }
46348 +            /* note: we actually get the block size for mailbox 1, for SDIO the block
46349 +             * size on mailbox 0 is artificially set to 1 */
46350 +            /* must be a power of 2 */
46351 +        A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
46352 +
46353 +            /* set the host interest area for the block size */
46354 +        status = BMIWriteMemory(ar->arHifDevice,
46355 +                                HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_io_block_sz),
46356 +                                (A_UCHAR *)&blocksizes[1],
46357 +                                4);
46358 +
46359 +        if (A_FAILED(status)) {
46360 +            AR_DEBUG_PRINTF("BMIWriteMemory for IO block size failed \n");
46361 +            break;
46362 +        }
46363 +
46364 +        AR_DEBUG_PRINTF("Block Size Set: %d (target address:0x%X)\n",
46365 +                blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_io_block_sz));
46366 +
46367 +            /* set the host interest area for the mbox ISR yield limit */
46368 +        status = BMIWriteMemory(ar->arHifDevice,
46369 +                                HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_isr_yield_limit),
46370 +                                (A_UCHAR *)&mbox_yield_limit,
46371 +                                4);
46372 +
46373 +        if (A_FAILED(status)) {
46374 +            AR_DEBUG_PRINTF("BMIWriteMemory for yield limit failed \n");
46375 +            break;
46376 +        }
46377 +
46378 +    } while (FALSE);
46379 +
46380 +    return status;
46381 +}
46382 +
46383 +static void free_raw_buffers(AR_SOFTC_T *ar)
46384 +{
46385 +    int i, j;
46386 +
46387 +    for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) {
46388 +       for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++)
46389 +           kfree(ar->raw_htc_read_buffer[i][j]);
46390 +       for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++)
46391 +           kfree(ar->raw_htc_write_buffer[i][j]);
46392 +    }
46393 +}
46394 +
46395 +static int alloc_raw_buffers(AR_SOFTC_T *ar)
46396 +{
46397 +    int i, j;
46398 +    raw_htc_buffer *b;
46399 +
46400 +    for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) {
46401 +       for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++) {
46402 +           b = kzalloc(sizeof(*b), GFP_KERNEL);
46403 +           if (!b)
46404 +               return -ENOMEM;
46405 +           ar->raw_htc_read_buffer[i][j] = b;
46406 +       }
46407 +       for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++) {
46408 +           b = kzalloc(sizeof(*b), GFP_KERNEL);
46409 +           if (!b)
46410 +               return -ENOMEM;
46411 +           ar->raw_htc_write_buffer[i][j] = b;
46412 +       }
46413 +    }
46414 +    return 0;
46415 +}
46416 +
46417 +/*
46418 + * HTC Event handlers
46419 + */
46420 +static void
46421 +ar6000_avail_ev(HTC_HANDLE HTCHandle)
46422 +{
46423 +    int i;
46424 +    struct net_device *dev;
46425 +    AR_SOFTC_T *ar;
46426 +    int device_index = 0;
46427 +
46428 +    AR_DEBUG_PRINTF("ar6000_available\n");
46429 +
46430 +    for (i=0; i < MAX_AR6000; i++) {
46431 +        if (ar6000_devices[i] == NULL) {
46432 +            break;
46433 +        }
46434 +    }
46435 +
46436 +    if (i == MAX_AR6000) {
46437 +        AR_DEBUG_PRINTF("ar6000_available: max devices reached\n");
46438 +        return;
46439 +    }
46440 +
46441 +    /* Save this. It gives a bit better readability especially since */
46442 +    /* we use another local "i" variable below.                      */
46443 +    device_index = i;
46444 +
46445 +    A_ASSERT(HTCHandle != NULL);
46446 +
46447 +    dev = alloc_etherdev(sizeof(AR_SOFTC_T));
46448 +    if (dev == NULL) {
46449 +        AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n");
46450 +        return;
46451 +    }
46452 +
46453 +    ether_setup(dev);
46454 +
46455 +    if (dev->priv == NULL) {
46456 +        printk(KERN_CRIT "ar6000_available: Could not allocate memory\n");
46457 +        return;
46458 +    }
46459 +
46460 +    A_MEMZERO(dev->priv, sizeof(AR_SOFTC_T));
46461 +
46462 +    ar                       = (AR_SOFTC_T *)dev->priv;
46463 +    ar->arNetDev             = dev;
46464 +    ar->arHtcTarget          = HTCHandle;
46465 +    ar->arHifDevice          = HTCGetHifDevice(HTCHandle);
46466 +    ar->arWlanState          = WLAN_ENABLED;
46467 +    ar->arRadioSwitch        = WLAN_ENABLED;
46468 +    ar->arDeviceIndex        = device_index;
46469 +
46470 +    A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev);
46471 +    ar->arHBChallengeResp.seqNum = 0;
46472 +    ar->arHBChallengeResp.outstanding = FALSE;
46473 +    ar->arHBChallengeResp.missCnt = 0;
46474 +    ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT;
46475 +    ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT;
46476 +
46477 +    ar6000_init_control_info(ar);
46478 +    init_waitqueue_head(&arEvent);
46479 +    sema_init(&ar->arSem, 1);
46480 +
46481 +    if (alloc_raw_buffers(ar)) {
46482 +       free_raw_buffers(ar);
46483 +       /*
46484 +        * @@@ Clean up our own mess, but for anything else, cheerfully mimick
46485 +        * the beautiful error non-handling of the rest of this function.
46486 +        */
46487 +       return;
46488 +    }
46489 +
46490 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
46491 +    A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar);
46492 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
46493 +
46494 +    /*
46495 +     * If requested, perform some magic which requires no cooperation from
46496 +     * the Target.  It causes the Target to ignore flash and execute to the
46497 +     * OS from ROM.
46498 +     *
46499 +     * This is intended to support recovery from a corrupted flash on Targets
46500 +     * that support flash.
46501 +     */
46502 +    if (skipflash)
46503 +    {
46504 +        ar6000_reset_device_skipflash(ar->arHifDevice);
46505 +            }
46506 +
46507 +    BMIInit();
46508 +    {
46509 +        struct bmi_target_info targ_info;
46510 +
46511 +        if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) {
46512 +            return;
46513 +        }
46514 +
46515 +        ar->arVersion.target_ver = targ_info.target_ver;
46516 +        ar->arTargetType = targ_info.target_type;
46517 +    }
46518 +
46519 +    if (enableuartprint) {
46520 +        A_UINT32 param;
46521 +        param = 1;
46522 +        if (BMIWriteMemory(ar->arHifDevice,
46523 +                           HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable),
46524 +                           (A_UCHAR *)&param,
46525 +                           4)!= A_OK)
46526 +        {
46527 +             AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n");
46528 +             return ;
46529 +        }
46530 +        AR_DEBUG_PRINTF("Serial console prints enabled\n");
46531 +    }
46532 +#ifdef CONFIG_HOST_TCMD_SUPPORT
46533 +    if(testmode) {
46534 +        ar->arTargetMode = AR6000_TCMD_MODE;
46535 +    }else {
46536 +        ar->arTargetMode = AR6000_WLAN_MODE;
46537 +    }
46538 +#endif
46539 +    if (enabletimerwar) {
46540 +        A_UINT32 param;
46541 +
46542 +        if (BMIReadMemory(ar->arHifDevice,
46543 +            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
46544 +            (A_UCHAR *)&param,
46545 +            4)!= A_OK)
46546 +        {
46547 +            AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n");
46548 +            return;
46549 +        }
46550 +
46551 +        param |= HI_OPTION_TIMER_WAR;
46552 +
46553 +        if (BMIWriteMemory(ar->arHifDevice,
46554 +            HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
46555 +            (A_UCHAR *)&param,
46556 +            4) != A_OK)
46557 +        {
46558 +            AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n");
46559 +            return;
46560 +        }
46561 +        AR_DEBUG_PRINTF("Timer WAR enabled\n");
46562 +    }
46563 +
46564 +
46565 +        /* since BMIInit is called in the driver layer, we have to set the block
46566 +         * size here for the target */
46567 +
46568 +    if (A_FAILED(ar6000_SetHTCBlockSize(ar))) {
46569 +        return;
46570 +    }
46571 +
46572 +    spin_lock_init(&ar->arLock);
46573 +
46574 +    /* Don't install the init function if BMI is requested */
46575 +    if(!bmienable)
46576 +    {
46577 +        dev->init = ar6000_init;
46578 +    } else {
46579 +        AR_DEBUG_PRINTF(" BMI enabled \n");
46580 +    }
46581 +
46582 +    dev->open = &ar6000_open;
46583 +    dev->stop = &ar6000_close;
46584 +    dev->hard_start_xmit = &ar6000_data_tx;
46585 +    dev->get_stats = &ar6000_get_stats;
46586 +
46587 +    /* dev->tx_timeout = ar6000_tx_timeout; */
46588 +    dev->do_ioctl = &ar6000_ioctl;
46589 +    dev->watchdog_timeo = AR6000_TX_TIMEOUT;
46590 +    ar6000_ioctl_iwsetup(&ath_iw_handler_def);
46591 +    dev->wireless_handlers = &ath_iw_handler_def;
46592 +    ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
46593 +
46594 +    /*
46595 +     * We need the OS to provide us with more headroom in order to
46596 +     * perform dix to 802.3, WMI header encap, and the HTC header
46597 +     */
46598 +    dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
46599 +        sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN;
46600 +
46601 +    /* This runs the init function */
46602 +    SET_NETDEV_DEV(dev, HIFGetOSDevice(ar->arHifDevice));
46603 +    if (register_netdev(dev)) {
46604 +        AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n");
46605 +        ar6000_destroy(dev, 0);
46606 +        return;
46607 +    }
46608 +
46609 +    HTCSetInstance(ar->arHtcTarget, ar);
46610 +
46611 +    /* We only register the device in the global list if we succeed. */
46612 +    /* If the device is in the global list, it will be destroyed     */
46613 +    /* when the module is unloaded.                                  */
46614 +    ar6000_devices[device_index] = dev;
46615 +
46616 +    AR_DEBUG_PRINTF("ar6000_avail: name=%s htcTarget=0x%x, dev=0x%x (%d), ar=0x%x\n",
46617 +                    dev->name, (A_UINT32)HTCHandle, (A_UINT32)dev, device_index,
46618 +                    (A_UINT32)ar);
46619 +}
46620 +
46621 +static void ar6000_target_failure(void *Instance, A_STATUS Status)
46622 +{
46623 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
46624 +    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
46625 +    static A_BOOL sip = FALSE;
46626 +
46627 +    if (Status != A_OK) {
46628 +        if (timer_pending(&ar->arHBChallengeResp.timer)) {
46629 +            A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
46630 +        }
46631 +
46632 +        /* try dumping target assertion information (if any) */
46633 +        ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType);
46634 +
46635 +        /*
46636 +         * Fetch the logs from the target via the diagnostic
46637 +         * window.
46638 +         */
46639 +        ar6000_dbglog_get_debug_logs(ar);
46640 +
46641 +        /* Report the error only once */
46642 +        if (!sip) {
46643 +            sip = TRUE;
46644 +            errEvent.errorVal = WMI_TARGET_COM_ERR |
46645 +                                WMI_TARGET_FATAL_ERR;
46646 +#ifdef SEND_EVENT_TO_APP
46647 +            ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
46648 +                                     (A_UINT8 *)&errEvent,
46649 +                                     sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
46650 +#endif
46651 +        }
46652 +    }
46653 +}
46654 +
46655 +static void
46656 +ar6000_unavail_ev(void *Instance)
46657 +{
46658 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
46659 +        /* NULL out it's entry in the global list */
46660 +    ar6000_devices[ar->arDeviceIndex] = NULL;
46661 +    ar6000_destroy(ar->arNetDev, 1);
46662 +}
46663 +
46664 +/*
46665 + * We need to differentiate between the surprise and planned removal of the
46666 + * device because of the following consideration:
46667 + * - In case of surprise removal, the hcd already frees up the pending
46668 + *   for the device and hence there is no need to unregister the function
46669 + *   driver inorder to get these requests. For planned removal, the function
46670 + *   driver has to explictly unregister itself to have the hcd return all the
46671 + *   pending requests before the data structures for the devices are freed up.
46672 + *   Note that as per the current implementation, the function driver will
46673 + *   end up releasing all the devices since there is no API to selectively
46674 + *   release a particular device.
46675 + * - Certain commands issued to the target can be skipped for surprise
46676 + *   removal since they will anyway not go through.
46677 + */
46678 +static void
46679 +ar6000_destroy(struct net_device *dev, unsigned int unregister)
46680 +{
46681 +    AR_SOFTC_T *ar;
46682 +
46683 +    AR_DEBUG_PRINTF("+ar6000_destroy \n");
46684 +
46685 +    if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL))
46686 +    {
46687 +        AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__);
46688 +        return;
46689 +    }
46690 +
46691 +    /* Stop the transmit queues */
46692 +    netif_stop_queue(dev);
46693 +
46694 +    /* Disable the target and the interrupts associated with it */
46695 +    if (ar->arWmiReady == TRUE)
46696 +    {
46697 +        if (!bypasswmi)
46698 +        {
46699 +            if (ar->arConnected == TRUE || ar->arConnectPending == TRUE)
46700 +            {
46701 +                AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__);
46702 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
46703 +                ar6000_init_profile_info(ar);
46704 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46705 +                wmi_disconnect_cmd(ar->arWmi);
46706 +            }
46707 +
46708 +            ar6000_dbglog_get_debug_logs(ar);
46709 +            ar->arWmiReady  = FALSE;
46710 +            ar->arConnected = FALSE;
46711 +            ar->arConnectPending = FALSE;
46712 +            wmi_shutdown(ar->arWmi);
46713 +            ar->arWmiEnabled = FALSE;
46714 +            ar->arWmi = NULL;
46715 +            ar->arWlanState = WLAN_ENABLED;
46716 +#ifdef USER_KEYS
46717 +            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
46718 +            ar->user_key_ctrl      = 0;
46719 +#endif
46720 +        }
46721 +
46722 +         AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__);
46723 +    }
46724 +    else
46725 +    {
46726 +        AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n",
46727 +            __func__, (unsigned int) ar, (unsigned int) ar->arWmi);
46728 +
46729 +        /* Shut down WMI if we have started it */
46730 +        if(ar->arWmiEnabled == TRUE)
46731 +        {
46732 +            AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__);
46733 +            wmi_shutdown(ar->arWmi);
46734 +            ar->arWmiEnabled = FALSE;
46735 +            ar->arWmi = NULL;
46736 +        }
46737 +    }
46738 +
46739 +    /* stop HTC */
46740 +    HTCStop(ar->arHtcTarget);
46741 +
46742 +    /* set the instance to NULL so we do not get called back on remove incase we
46743 +     * we're explicity destroyed by module unload */
46744 +    HTCSetInstance(ar->arHtcTarget, NULL);
46745 +
46746 +    if (resetok) {
46747 +        /* try to reset the device if we can
46748 +         * The driver may have been configure NOT to reset the target during
46749 +         * a debug session */
46750 +        AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n");
46751 +        ar6000_reset_device(ar->arHifDevice, ar->arTargetType);
46752 +    } else {
46753 +        AR_DEBUG_PRINTF(" Host does not want target reset. \n");
46754 +    }
46755 +
46756 +       /* Done with cookies */
46757 +    ar6000_cookie_cleanup(ar);
46758 +
46759 +    /* Cleanup BMI */
46760 +    BMIInit();
46761 +
46762 +    /* Clear the tx counters */
46763 +    memset(tx_attempt, 0, sizeof(tx_attempt));
46764 +    memset(tx_post, 0, sizeof(tx_post));
46765 +    memset(tx_complete, 0, sizeof(tx_complete));
46766 +
46767 +
46768 +    /* Free up the device data structure */
46769 +    if (unregister)
46770 +           unregister_netdev(dev);
46771 +
46772 +    free_raw_buffers(ar);
46773 +
46774 +#ifndef free_netdev
46775 +    kfree(dev);
46776 +#else
46777 +    free_netdev(dev);
46778 +#endif
46779 +
46780 +    AR_DEBUG_PRINTF("-ar6000_destroy \n");
46781 +}
46782 +
46783 +static void ar6000_detect_error(unsigned long ptr)
46784 +{
46785 +    struct net_device *dev = (struct net_device *)ptr;
46786 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
46787 +    WMI_TARGET_ERROR_REPORT_EVENT errEvent;
46788 +
46789 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
46790 +
46791 +    if (ar->arHBChallengeResp.outstanding) {
46792 +        ar->arHBChallengeResp.missCnt++;
46793 +    } else {
46794 +        ar->arHBChallengeResp.missCnt = 0;
46795 +    }
46796 +
46797 +    if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) {
46798 +        /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */
46799 +        ar->arHBChallengeResp.missCnt = 0;
46800 +        ar->arHBChallengeResp.seqNum = 0;
46801 +        errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR;
46802 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46803 +#ifdef SEND_EVENT_TO_APP
46804 +        ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
46805 +                                 (A_UINT8 *)&errEvent,
46806 +                                 sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
46807 +#endif
46808 +        return;
46809 +    }
46810 +
46811 +    /* Generate the sequence number for the next challenge */
46812 +    ar->arHBChallengeResp.seqNum++;
46813 +    ar->arHBChallengeResp.outstanding = TRUE;
46814 +
46815 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
46816 +
46817 +    /* Send the challenge on the control channel */
46818 +    if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) {
46819 +        AR_DEBUG_PRINTF("Unable to send heart beat challenge\n");
46820 +    }
46821 +
46822 +
46823 +    /* Reschedule the timer for the next challenge */
46824 +    A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
46825 +}
46826 +
46827 +void ar6000_init_profile_info(AR_SOFTC_T *ar)
46828 +{
46829 +    ar->arSsidLen            = 0;
46830 +    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
46831 +    ar->arNetworkType        = INFRA_NETWORK;
46832 +    ar->arDot11AuthMode      = OPEN_AUTH;
46833 +    ar->arAuthMode           = NONE_AUTH;
46834 +    ar->arPairwiseCrypto     = NONE_CRYPT;
46835 +    ar->arPairwiseCryptoLen  = 0;
46836 +    ar->arGroupCrypto        = NONE_CRYPT;
46837 +    ar->arGroupCryptoLen     = 0;
46838 +    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
46839 +    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
46840 +    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
46841 +    ar->arBssChannel = 0;
46842 +}
46843 +
46844 +static void
46845 +ar6000_init_control_info(AR_SOFTC_T *ar)
46846 +{
46847 +    ar->arWmiEnabled         = FALSE;
46848 +    ar6000_init_profile_info(ar);
46849 +    ar->arDefTxKeyIndex      = 0;
46850 +    A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
46851 +    ar->arChannelHint        = 0;
46852 +    ar->arListenInterval     = MAX_LISTEN_INTERVAL;
46853 +    ar->arVersion.host_ver   = AR6K_SW_VERSION;
46854 +    ar->arRssi               = 0;
46855 +    ar->arTxPwr              = 0;
46856 +    ar->arTxPwrSet           = FALSE;
46857 +    ar->arSkipScan           = 0;
46858 +    ar->arBeaconInterval     = 0;
46859 +    ar->arBitRate            = 0;
46860 +    ar->arMaxRetries         = 0;
46861 +    ar->arWmmEnabled         = TRUE;
46862 +}
46863 +
46864 +static int
46865 +ar6000_open(struct net_device *dev)
46866 +{
46867 +    /* Wake up the queues */
46868 +    netif_wake_queue(dev);
46869 +
46870 +    return 0;
46871 +}
46872 +
46873 +static int
46874 +ar6000_close(struct net_device *dev)
46875 +{
46876 +    netif_stop_queue(dev);
46877 +
46878 +    return 0;
46879 +}
46880 +
46881 +/* connect to a service */
46882 +static A_STATUS ar6000_connectservice(AR_SOFTC_T               *ar,
46883 +                                      HTC_SERVICE_CONNECT_REQ  *pConnect,
46884 +                                      WMI_PRI_STREAM_ID        WmiStreamID,
46885 +                                      char                     *pDesc)
46886 +{
46887 +    A_STATUS                 status;
46888 +    HTC_SERVICE_CONNECT_RESP response;
46889 +
46890 +    do {
46891 +
46892 +        A_MEMZERO(&response,sizeof(response));
46893 +
46894 +        status = HTCConnectService(ar->arHtcTarget,
46895 +                                   pConnect,
46896 +                                   &response);
46897 +
46898 +        if (A_FAILED(status)) {
46899 +            AR_DEBUG_PRINTF(" Failed to connect to %s service status:%d \n", pDesc, status);
46900 +            break;
46901 +        }
46902 +
46903 +        if (WmiStreamID == WMI_NOT_MAPPED) {
46904 +                /* done */
46905 +            break;
46906 +        }
46907 +
46908 +            /* set endpoint mapping for the WMI stream in the driver layer */
46909 +        arSetWMIStream2EndpointIDMap(ar,WmiStreamID,response.Endpoint);
46910 +
46911 +    } while (FALSE);
46912 +
46913 +    return status;
46914 +}
46915 +
46916 +static void ar6000_TxDataCleanup(AR_SOFTC_T *ar)
46917 +{
46918 +        /* flush all the data (non-control) streams
46919 +         * we only flush packets that are tagged as data, we leave any control packets that
46920 +         * were in the TX queues alone */
46921 +    HTCFlushEndpoint(ar->arHtcTarget,
46922 +                     arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI),
46923 +                     AR6K_DATA_PKT_TAG);
46924 +    HTCFlushEndpoint(ar->arHtcTarget,
46925 +                     arWMIStream2EndpointID(ar,WMI_LOW_PRI),
46926 +                     AR6K_DATA_PKT_TAG);
46927 +    HTCFlushEndpoint(ar->arHtcTarget,
46928 +                     arWMIStream2EndpointID(ar,WMI_HIGH_PRI),
46929 +                     AR6K_DATA_PKT_TAG);
46930 +    HTCFlushEndpoint(ar->arHtcTarget,
46931 +                     arWMIStream2EndpointID(ar,WMI_HIGHEST_PRI),
46932 +                     AR6K_DATA_PKT_TAG);
46933 +}
46934 +
46935 +/* This function does one time initialization for the lifetime of the device */
46936 +int ar6000_init(struct net_device *dev)
46937 +{
46938 +    AR_SOFTC_T *ar;
46939 +    A_STATUS    status;
46940 +    A_INT32     timeleft;
46941 +
46942 +    if((ar = netdev_priv(dev)) == NULL)
46943 +    {
46944 +        return(-EIO);
46945 +    }
46946 +
46947 +    /* Do we need to finish the BMI phase */
46948 +    if(BMIDone(ar->arHifDevice) != A_OK)
46949 +    {
46950 +        return -EIO;
46951 +    }
46952 +
46953 +    if (!bypasswmi)
46954 +    {
46955 +#if 0 /* TBDXXX */
46956 +        if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
46957 +            A_PRINTF("WARNING: Host version 0x%x does not match Target "
46958 +                    " version 0x%x!\n",
46959 +                    ar->arVersion.host_ver, ar->arVersion.target_ver);
46960 +        }
46961 +#endif
46962 +
46963 +        /* Indicate that WMI is enabled (although not ready yet) */
46964 +        ar->arWmiEnabled = TRUE;
46965 +        if ((ar->arWmi = wmi_init((void *) ar)) == NULL)
46966 +        {
46967 +            AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__);
46968 +            return(-EIO);
46969 +        }
46970 +
46971 +        AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__,
46972 +            (unsigned int) ar->arWmi);
46973 +    }
46974 +
46975 +    do {
46976 +        HTC_SERVICE_CONNECT_REQ connect;
46977 +
46978 +            /* the reason we have to wait for the target here is that the driver layer
46979 +             * has to init BMI in order to set the host block size,
46980 +             */
46981 +        status = HTCWaitTarget(ar->arHtcTarget);
46982 +
46983 +        if (A_FAILED(status)) {
46984 +            break;
46985 +        }
46986 +
46987 +        A_MEMZERO(&connect,sizeof(connect));
46988 +            /* meta data is unused for now */
46989 +        connect.pMetaData = NULL;
46990 +        connect.MetaDataLength = 0;
46991 +            /* these fields are the same for all service endpoints */
46992 +        connect.EpCallbacks.pContext = ar;
46993 +        connect.EpCallbacks.EpTxComplete = ar6000_tx_complete;
46994 +        connect.EpCallbacks.EpRecv = ar6000_rx;
46995 +        connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill;
46996 +        connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full;
46997 +            /* set the max queue depth so that our ar6000_tx_queue_full handler gets called.
46998 +             * Linux has the peculiarity of not providing flow control between the
46999 +             * NIC and the network stack. There is no API to indicate that a TX packet
47000 +             * was sent which could provide some back pressure to the network stack.
47001 +             * Under linux you would have to wait till the network stack consumed all sk_buffs
47002 +             * before any back-flow kicked in. Which isn't very friendly.
47003 +             * So we have to manage this ourselves */
47004 +        connect.MaxSendQueueDepth = 32;
47005 +
47006 +            /* connect to control service */
47007 +        connect.ServiceID = WMI_CONTROL_SVC;
47008 +        status = ar6000_connectservice(ar,
47009 +                                       &connect,
47010 +                                       WMI_CONTROL_PRI,
47011 +                                       "WMI CONTROL");
47012 +        if (A_FAILED(status)) {
47013 +            break;
47014 +        }
47015 +
47016 +            /* for the remaining data services set the connection flag to reduce dribbling,
47017 +             * if configured to do so */
47018 +        if (reduce_credit_dribble) {
47019 +            connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE;
47020 +            /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value
47021 +             * of 0-3 */
47022 +            connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
47023 +            connect.ConnectionFlags |=
47024 +                        ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
47025 +        }
47026 +            /* connect to best-effort service */
47027 +        connect.ServiceID = WMI_DATA_BE_SVC;
47028 +
47029 +        status = ar6000_connectservice(ar,
47030 +                                       &connect,
47031 +                                       WMI_BEST_EFFORT_PRI,
47032 +                                       "WMI DATA BE");
47033 +        if (A_FAILED(status)) {
47034 +            break;
47035 +        }
47036 +
47037 +            /* connect to back-ground
47038 +             * map this to WMI LOW_PRI */
47039 +        connect.ServiceID = WMI_DATA_BK_SVC;
47040 +        status = ar6000_connectservice(ar,
47041 +                                       &connect,
47042 +                                       WMI_LOW_PRI,
47043 +                                       "WMI DATA BK");
47044 +        if (A_FAILED(status)) {
47045 +            break;
47046 +        }
47047 +
47048 +            /* connect to Video service, map this to
47049 +             * to HI PRI */
47050 +        connect.ServiceID = WMI_DATA_VI_SVC;
47051 +        status = ar6000_connectservice(ar,
47052 +                                       &connect,
47053 +                                       WMI_HIGH_PRI,
47054 +                                       "WMI DATA VI");
47055 +        if (A_FAILED(status)) {
47056 +            break;
47057 +        }
47058 +
47059 +            /* connect to VO service, this is currently not
47060 +             * mapped to a WMI priority stream due to historical reasons.
47061 +             * WMI originally defined 3 priorities over 3 mailboxes
47062 +             * We can change this when WMI is reworked so that priorities are not
47063 +             * dependent on mailboxes */
47064 +        connect.ServiceID = WMI_DATA_VO_SVC;
47065 +        status = ar6000_connectservice(ar,
47066 +                                       &connect,
47067 +                                       WMI_HIGHEST_PRI,
47068 +                                       "WMI DATA VO");
47069 +        if (A_FAILED(status)) {
47070 +            break;
47071 +        }
47072 +
47073 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_CONTROL_PRI) != 0);
47074 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI) != 0);
47075 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_LOW_PRI) != 0);
47076 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_HIGH_PRI) != 0);
47077 +        A_ASSERT(arWMIStream2EndpointID(ar,WMI_HIGHEST_PRI) != 0);
47078 +    } while (FALSE);
47079 +
47080 +    if (A_FAILED(status)) {
47081 +        return (-EIO);
47082 +    }
47083 +
47084 +    /*
47085 +     * give our connected endpoints some buffers
47086 +     */
47087 +    ar6000_rx_refill(ar, arWMIStream2EndpointID(ar,WMI_CONTROL_PRI));
47088 +
47089 +    ar6000_rx_refill(ar, arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI));
47090 +
47091 +    /*
47092 +     * We will post the receive buffers only for SPE testing and so we are
47093 +     * making it conditional on the 'bypasswmi' flag.
47094 +     */
47095 +    if (bypasswmi) {
47096 +        ar6000_rx_refill(ar,arWMIStream2EndpointID(ar,WMI_LOW_PRI));
47097 +        ar6000_rx_refill(ar,arWMIStream2EndpointID(ar,WMI_HIGH_PRI));
47098 +    }
47099 +
47100 +        /* setup credit distribution */
47101 +    ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo);
47102 +
47103 +    /* Since cookies are used for HTC transports, they should be */
47104 +    /* initialized prior to enabling HTC.                        */
47105 +    ar6000_cookie_init(ar);
47106 +
47107 +    /* start HTC */
47108 +    status = HTCStart(ar->arHtcTarget);
47109 +
47110 +    if (status != A_OK) {
47111 +        if (ar->arWmiEnabled == TRUE) {
47112 +            wmi_shutdown(ar->arWmi);
47113 +            ar->arWmiEnabled = FALSE;
47114 +            ar->arWmi = NULL;
47115 +        }
47116 +        ar6000_cookie_cleanup(ar);
47117 +        return -EIO;
47118 +    }
47119 +
47120 +    if (!bypasswmi) {
47121 +        /* Wait for Wmi event to be ready */
47122 +        timeleft = wait_event_interruptible_timeout(arEvent,
47123 +            (ar->arWmiReady == TRUE), wmitimeout * HZ);
47124 +
47125 +        if(!timeleft || signal_pending(current))
47126 +        {
47127 +            AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n");
47128 +#if defined(DWSIM) /* TBDXXX */
47129 +            AR_DEBUG_PRINTF(".....but proceed anyway.\n");
47130 +#else
47131 +            return -EIO;
47132 +#endif
47133 +        }
47134 +
47135 +        AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__);
47136 +
47137 +        /* Communicate the wmi protocol verision to the target */
47138 +        if ((ar6000_set_host_app_area(ar)) != A_OK) {
47139 +            AR_DEBUG_PRINTF("Unable to set the host app area\n");
47140 +        }
47141 +    }
47142 +
47143 +    ar->arNumDataEndPts = 1;
47144 +
47145 +    return(0);
47146 +}
47147 +
47148 +
47149 +void
47150 +ar6000_bitrate_rx(void *devt, A_INT32 rateKbps)
47151 +{
47152 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
47153 +
47154 +    ar->arBitRate = rateKbps;
47155 +    wake_up(&arEvent);
47156 +}
47157 +
47158 +void
47159 +ar6000_ratemask_rx(void *devt, A_UINT16 ratemask)
47160 +{
47161 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
47162 +
47163 +    ar->arRateMask = ratemask;
47164 +    wake_up(&arEvent);
47165 +}
47166 +
47167 +void
47168 +ar6000_txPwr_rx(void *devt, A_UINT8 txPwr)
47169 +{
47170 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
47171 +
47172 +    ar->arTxPwr = txPwr;
47173 +    wake_up(&arEvent);
47174 +}
47175 +
47176 +
47177 +void
47178 +ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList)
47179 +{
47180 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
47181 +
47182 +    A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16));
47183 +    ar->arNumChannels = numChan;
47184 +
47185 +    wake_up(&arEvent);
47186 +}
47187 +
47188 +A_UINT8
47189 +ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo)
47190 +{
47191 +    AR_SOFTC_T      *ar = (AR_SOFTC_T *)dev->priv;
47192 +    A_UINT8         *datap;
47193 +    ATH_MAC_HDR     *macHdr;
47194 +    A_UINT32         i, eptMap;
47195 +
47196 +    (*mapNo) = 0;
47197 +    datap = A_NETBUF_DATA(skb);
47198 +    macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR));
47199 +    if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
47200 +        return ENDPOINT_2;
47201 +    }
47202 +
47203 +    eptMap = -1;
47204 +    for (i = 0; i < ar->arNodeNum; i ++) {
47205 +        if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
47206 +            (*mapNo) = i + 1;
47207 +            ar->arNodeMap[i].txPending ++;
47208 +            return ar->arNodeMap[i].epId;
47209 +        }
47210 +
47211 +        if ((eptMap == -1) && !ar->arNodeMap[i].txPending) {
47212 +            eptMap = i;
47213 +        }
47214 +    }
47215 +
47216 +    if (eptMap == -1) {
47217 +        eptMap = ar->arNodeNum;
47218 +        ar->arNodeNum ++;
47219 +        A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
47220 +    }
47221 +
47222 +    A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN);
47223 +
47224 +    for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) {
47225 +        if (!ar->arTxPending[i]) {
47226 +            ar->arNodeMap[eptMap].epId = i;
47227 +            break;
47228 +        }
47229 +        // No free endpoint is available, start redistribution on the inuse endpoints.
47230 +        if (i == ENDPOINT_5) {
47231 +            ar->arNodeMap[eptMap].epId = ar->arNexEpId;
47232 +            ar->arNexEpId ++;
47233 +            if (ar->arNexEpId > ENDPOINT_5) {
47234 +                ar->arNexEpId = ENDPOINT_2;
47235 +            }
47236 +        }
47237 +    }
47238 +
47239 +    (*mapNo) = eptMap + 1;
47240 +    ar->arNodeMap[eptMap].txPending ++;
47241 +
47242 +    return ar->arNodeMap[eptMap].epId;
47243 +}
47244 +
47245 +#ifdef DEBUG
47246 +static void ar6000_dump_skb(struct sk_buff *skb)
47247 +{
47248 +   u_char *ch;
47249 +   for (ch = A_NETBUF_DATA(skb);
47250 +        (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) +
47251 +        A_NETBUF_LEN(skb)); ch++)
47252 +    {
47253 +         AR_DEBUG_PRINTF("%2.2x ", *ch);
47254 +    }
47255 +    AR_DEBUG_PRINTF("\n");
47256 +}
47257 +#endif
47258 +
47259 +static int
47260 +ar6000_data_tx(struct sk_buff *skb, struct net_device *dev)
47261 +{
47262 +    AR_SOFTC_T        *ar = (AR_SOFTC_T *)dev->priv;
47263 +    WMI_PRI_STREAM_ID streamID = WMI_NOT_MAPPED;
47264 +    A_UINT32          mapNo = 0;
47265 +    int               len;
47266 +    struct ar_cookie *cookie;
47267 +    A_BOOL            checkAdHocPsMapping = FALSE;
47268 +
47269 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)
47270 +    skb->list = NULL;
47271 +#endif
47272 +
47273 +    AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n",
47274 +                     (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb),
47275 +                     A_NETBUF_LEN(skb));
47276 +#ifdef CONFIG_HOST_TCMD_SUPPORT
47277 +     /* TCMD doesnt support any data, free the buf and return */
47278 +    if(ar->arTargetMode == AR6000_TCMD_MODE) {
47279 +        A_NETBUF_FREE(skb);
47280 +        return 0;
47281 +    }
47282 +#endif
47283 +    do {
47284 +
47285 +        if (ar->arWmiReady == FALSE && bypasswmi == 0) {
47286 +            break;
47287 +        }
47288 +
47289 +#ifdef BLOCK_TX_PATH_FLAG
47290 +        if (blocktx) {
47291 +            break;
47292 +        }
47293 +#endif /* BLOCK_TX_PATH_FLAG */
47294 +
47295 +        if (ar->arWmiEnabled) {
47296 +            if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len) {
47297 +                struct sk_buff  *newbuf;
47298 +                /*
47299 +                 * We really should have gotten enough headroom but sometimes
47300 +                 * we still get packets with not enough headroom.  Copy the packet.
47301 +                 */
47302 +                len = A_NETBUF_LEN(skb);
47303 +                newbuf = A_NETBUF_ALLOC(len);
47304 +                if (newbuf == NULL) {
47305 +                    break;
47306 +                }
47307 +                A_NETBUF_PUT(newbuf, len);
47308 +                A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len);
47309 +                A_NETBUF_FREE(skb);
47310 +                skb = newbuf;
47311 +                /* fall through and assemble header */
47312 +            }
47313 +
47314 +            if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
47315 +                AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n");
47316 +                break;
47317 +            }
47318 +
47319 +            if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE) != A_OK) {
47320 +                AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n");
47321 +                break;
47322 +            }
47323 +
47324 +            if ((ar->arNetworkType == ADHOC_NETWORK) &&
47325 +                ar->arIbssPsEnable && ar->arConnected) {
47326 +                    /* flag to check adhoc mapping once we take the lock below: */
47327 +                checkAdHocPsMapping = TRUE;
47328 +
47329 +            } else {
47330 +                    /* get the stream mapping */
47331 +                if (ar->arWmmEnabled) {
47332 +                    streamID = wmi_get_stream_id(ar->arWmi,
47333 +                                    wmi_implicit_create_pstream(ar->arWmi, skb, UPLINK_TRAFFIC, UNDEFINED_PRI));
47334 +                } else {
47335 +                    streamID = WMI_BEST_EFFORT_PRI;
47336 +                }
47337 +            }
47338 +
47339 +        } else {
47340 +            struct iphdr    *ipHdr;
47341 +            /*
47342 +             * the endpoint is directly based on the TOS field in the IP
47343 +             * header **** only for testing ******
47344 +             */
47345 +            ipHdr = A_NETBUF_DATA(skb) + sizeof(ATH_MAC_HDR);
47346 +                /* here we map the TOS field to an endpoint number, this is for
47347 +                 * the endpointping test application */
47348 +            streamID = IP_TOS_TO_WMI_PRI(ipHdr->tos);
47349 +        }
47350 +
47351 +    } while (FALSE);
47352 +
47353 +        /* did we succeed ? */
47354 +    if ((streamID == WMI_NOT_MAPPED) && !checkAdHocPsMapping) {
47355 +            /* cleanup and exit */
47356 +        A_NETBUF_FREE(skb);
47357 +        AR6000_STAT_INC(ar, tx_dropped);
47358 +        AR6000_STAT_INC(ar, tx_aborted_errors);
47359 +        return 0;
47360 +    }
47361 +
47362 +    cookie = NULL;
47363 +
47364 +        /* take the lock to protect driver data */
47365 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47366 +
47367 +    do {
47368 +
47369 +        if (checkAdHocPsMapping) {
47370 +            streamID = ar6000_ibss_map_epid(skb, dev, &mapNo);
47371 +        }
47372 +
47373 +        A_ASSERT(streamID != WMI_NOT_MAPPED);
47374 +
47375 +            /* validate that the endpoint is connected */
47376 +        if (arWMIStream2EndpointID(ar,streamID) == 0) {
47377 +            AR_DEBUG_PRINTF("Stream %d is NOT mapped!\n",streamID);
47378 +            break;
47379 +        }
47380 +            /* allocate resource for this packet */
47381 +        cookie = ar6000_alloc_cookie(ar);
47382 +
47383 +        if (cookie != NULL) {
47384 +                /* update counts while the lock is held */
47385 +            ar->arTxPending[streamID]++;
47386 +            ar->arTotalTxDataPending++;
47387 +        }
47388 +
47389 +    } while (FALSE);
47390 +
47391 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47392 +
47393 +    if (cookie != NULL) {
47394 +        cookie->arc_bp[0] = (A_UINT32)skb;
47395 +        cookie->arc_bp[1] = mapNo;
47396 +        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
47397 +                               cookie,
47398 +                               A_NETBUF_DATA(skb),
47399 +                               A_NETBUF_LEN(skb),
47400 +                               arWMIStream2EndpointID(ar,streamID),
47401 +                               AR6K_DATA_PKT_TAG);
47402 +
47403 +#ifdef DEBUG
47404 +        if (debugdriver >= 3) {
47405 +            ar6000_dump_skb(skb);
47406 +        }
47407 +#endif
47408 +            /* HTC interface is asynchronous, if this fails, cleanup will happen in
47409 +             * the ar6000_tx_complete callback */
47410 +        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
47411 +    } else {
47412 +            /* no packet to send, cleanup */
47413 +        A_NETBUF_FREE(skb);
47414 +        AR6000_STAT_INC(ar, tx_dropped);
47415 +        AR6000_STAT_INC(ar, tx_aborted_errors);
47416 +    }
47417 +
47418 +    return 0;
47419 +}
47420 +
47421 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
47422 +static void
47423 +tvsub(register struct timeval *out, register struct timeval *in)
47424 +{
47425 +    if((out->tv_usec -= in->tv_usec) < 0) {
47426 +        out->tv_sec--;
47427 +        out->tv_usec += 1000000;
47428 +    }
47429 +    out->tv_sec -= in->tv_sec;
47430 +}
47431 +
47432 +void
47433 +applyAPTCHeuristics(AR_SOFTC_T *ar)
47434 +{
47435 +    A_UINT32 duration;
47436 +    A_UINT32 numbytes;
47437 +    A_UINT32 throughput;
47438 +    struct timeval ts;
47439 +    A_STATUS status;
47440 +
47441 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47442 +
47443 +    if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) {
47444 +        do_gettimeofday(&ts);
47445 +        tvsub(&ts, &aptcTR.samplingTS);
47446 +        duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */
47447 +        numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
47448 +
47449 +        if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) {
47450 +            /* Initialize the time stamp and byte count */
47451 +            aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
47452 +            do_gettimeofday(&aptcTR.samplingTS);
47453 +
47454 +            /* Calculate and decide based on throughput thresholds */
47455 +            throughput = ((numbytes * 8) / duration);
47456 +            if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) {
47457 +                /* Disable Sleep and schedule a timer */
47458 +                A_ASSERT(ar->arWmiReady == TRUE);
47459 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47460 +                status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER);
47461 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
47462 +                A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
47463 +                aptcTR.timerScheduled = TRUE;
47464 +            }
47465 +        }
47466 +    }
47467 +
47468 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47469 +}
47470 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
47471 +
47472 +static void ar6000_tx_queue_full(void *Context, HTC_ENDPOINT_ID Endpoint)
47473 +{
47474 +    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
47475 +
47476 +
47477 +    if (Endpoint == arWMIStream2EndpointID(ar,WMI_CONTROL_PRI)) {
47478 +        if (!bypasswmi) {
47479 +                /* under normal WMI if this is getting full, then something is running rampant
47480 +                 * the host should not be exhausting the WMI queue with too many commands
47481 +                 * the only exception to this is during testing using endpointping */
47482 +
47483 +            AR6000_SPIN_LOCK(&ar->arLock, 0);
47484 +                /* set flag to handle subsequent messages */
47485 +            ar->arWMIControlEpFull = TRUE;
47486 +            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47487 +            AR_DEBUG_PRINTF("WMI Control Endpoint is FULL!!! \n");
47488 +        }
47489 +    } else {
47490 +
47491 +        AR6000_SPIN_LOCK(&ar->arLock, 0);
47492 +        ar->arNetQueueStopped = TRUE;
47493 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47494 +        /* one of the data endpoints queues is getting full..need to stop network stack
47495 +         * the queue will resume in ar6000_tx_complete() */
47496 +        netif_stop_queue(ar->arNetDev);
47497 +    }
47498 +
47499 +
47500 +}
47501 +
47502 +
47503 +static void
47504 +ar6000_tx_complete(void *Context, HTC_PACKET *pPacket)
47505 +{
47506 +    AR_SOFTC_T     *ar = (AR_SOFTC_T *)Context;
47507 +    void           *cookie = (void *)pPacket->pPktContext;
47508 +    struct sk_buff *skb = NULL;
47509 +    A_UINT32        mapNo = 0;
47510 +    A_STATUS        status;
47511 +    struct ar_cookie * ar_cookie;
47512 +    WMI_PRI_STREAM_ID streamID;
47513 +    A_BOOL          wakeEvent = FALSE;
47514 +
47515 +    status = pPacket->Status;
47516 +    ar_cookie = (struct ar_cookie *)cookie;
47517 +    skb = (struct sk_buff *)ar_cookie->arc_bp[0];
47518 +    streamID = arEndpoint2WMIStreamID(ar,pPacket->Endpoint);
47519 +    mapNo = ar_cookie->arc_bp[1];
47520 +
47521 +    A_ASSERT(skb);
47522 +    A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(skb));
47523 +
47524 +    if (A_SUCCESS(status)) {
47525 +        A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(skb));
47526 +    }
47527 +
47528 +    AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x sid=%d ",
47529 +                     (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
47530 +                     pPacket->ActualLength,
47531 +                     streamID);
47532 +
47533 +        /* lock the driver as we update internal state */
47534 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47535 +
47536 +    ar->arTxPending[streamID]--;
47537 +
47538 +    if ((streamID != WMI_CONTROL_PRI) || bypasswmi) {
47539 +        ar->arTotalTxDataPending--;
47540 +    }
47541 +
47542 +    if (streamID == WMI_CONTROL_PRI)
47543 +    {
47544 +        if (ar->arWMIControlEpFull) {
47545 +                /* since this packet completed, the WMI EP is no longer full */
47546 +            ar->arWMIControlEpFull = FALSE;
47547 +        }
47548 +
47549 +        if (ar->arTxPending[streamID] == 0) {
47550 +            wakeEvent = TRUE;
47551 +        }
47552 +    }
47553 +
47554 +    if (A_FAILED(status)) {
47555 +        AR_DEBUG_PRINTF("%s() -TX ERROR, status: 0x%x\n", __func__,
47556 +                        status);
47557 +        AR6000_STAT_INC(ar, tx_errors);
47558 +    } else {
47559 +        AR_DEBUG2_PRINTF("OK\n");
47560 +        AR6000_STAT_INC(ar, tx_packets);
47561 +        ar->arNetStats.tx_bytes += A_NETBUF_LEN(skb);
47562 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
47563 +        aptcTR.bytesTransmitted += a_netbuf_to_len(skb);
47564 +        applyAPTCHeuristics(ar);
47565 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
47566 +    }
47567 +
47568 +    // TODO this needs to be looked at
47569 +    if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
47570 +        && (streamID != WMI_CONTROL_PRI) && mapNo)
47571 +    {
47572 +        mapNo --;
47573 +        ar->arNodeMap[mapNo].txPending --;
47574 +
47575 +        if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) {
47576 +            A_UINT32 i;
47577 +            for (i = ar->arNodeNum; i > 0; i --) {
47578 +                if (!ar->arNodeMap[i - 1].txPending) {
47579 +                    A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping));
47580 +                    ar->arNodeNum --;
47581 +                } else {
47582 +                    break;
47583 +                }
47584 +            }
47585 +        }
47586 +    }
47587 +
47588 +    /* Freeing a cookie should not be contingent on either of */
47589 +    /* these flags, just if we have a cookie or not.           */
47590 +    /* Can we even get here without a cookie? Fix later.       */
47591 +    if (ar->arWmiReady == TRUE || (bypasswmi))
47592 +    {
47593 +        ar6000_free_cookie(ar, cookie);
47594 +    }
47595 +
47596 +    if (ar->arNetQueueStopped) {
47597 +        ar->arNetQueueStopped = FALSE;
47598 +    }
47599 +
47600 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47601 +
47602 +    /* lock is released, we can freely call other kernel APIs */
47603 +
47604 +        /* this indirectly frees the HTC_PACKET */
47605 +    A_NETBUF_FREE(skb);
47606 +
47607 +    if ((ar->arConnected == TRUE) || (bypasswmi)) {
47608 +        if (status != A_ECANCELED) {
47609 +                /* don't wake the queue if we are flushing, other wise it will just
47610 +                 * keep queueing packets, which will keep failing */
47611 +            netif_wake_queue(ar->arNetDev);
47612 +        }
47613 +    }
47614 +
47615 +    if (wakeEvent) {
47616 +        wake_up(&arEvent);
47617 +    }
47618 +
47619 +}
47620 +
47621 +/*
47622 + * Receive event handler.  This is called by HTC when a packet is received
47623 + */
47624 +int pktcount;
47625 +static void
47626 +ar6000_rx(void *Context, HTC_PACKET *pPacket)
47627 +{
47628 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
47629 +    struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext;
47630 +    int minHdrLen;
47631 +    A_STATUS        status = pPacket->Status;
47632 +    WMI_PRI_STREAM_ID streamID = arEndpoint2WMIStreamID(ar,pPacket->Endpoint);
47633 +    HTC_ENDPOINT_ID   ept = pPacket->Endpoint;
47634 +
47635 +    A_ASSERT((status != A_OK) || (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN)));
47636 +
47637 +    AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x sid=%d, skb=0x%x, data=0x%x, len=0x%x ",
47638 +                    (A_UINT32)ar, streamID, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
47639 +                    pPacket->ActualLength);
47640 +    if (status != A_OK) {
47641 +        AR_DEBUG2_PRINTF("ERR\n");
47642 +    } else {
47643 +        AR_DEBUG2_PRINTF("OK\n");
47644 +    }
47645 +
47646 +        /* take lock to protect buffer counts
47647 +         * and adaptive power throughput state */
47648 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47649 +
47650 +    ar->arRxBuffers[streamID]--;
47651 +
47652 +    if (A_SUCCESS(status)) {
47653 +        AR6000_STAT_INC(ar, rx_packets);
47654 +        ar->arNetStats.rx_bytes += pPacket->ActualLength;
47655 +#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
47656 +        aptcTR.bytesReceived += a_netbuf_to_len(skb);
47657 +        applyAPTCHeuristics(ar);
47658 +#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
47659 +
47660 +        A_NETBUF_PUT(skb, pPacket->ActualLength +  HTC_HEADER_LEN);
47661 +        A_NETBUF_PULL(skb, HTC_HEADER_LEN);
47662 +
47663 +#ifdef DEBUG
47664 +        if (debugdriver >= 2) {
47665 +            ar6000_dump_skb(skb);
47666 +        }
47667 +#endif /* DEBUG */
47668 +    }
47669 +
47670 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47671 +
47672 +    if (status != A_OK) {
47673 +        AR6000_STAT_INC(ar, rx_errors);
47674 +        A_NETBUF_FREE(skb);
47675 +    } else if (ar->arWmiEnabled == TRUE) {
47676 +        if (streamID == WMI_CONTROL_PRI) {
47677 +           /*
47678 +            * this is a wmi control msg
47679 +            */
47680 +            wmi_control_rx(ar->arWmi, skb);
47681 +        } else {
47682 +            WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb);
47683 +            if (WMI_DATA_HDR_IS_MSG_TYPE(dhdr, CNTL_MSGTYPE)) {
47684 +                /*
47685 +                 * this is a wmi control msg
47686 +                 */
47687 +                /* strip off WMI hdr */
47688 +                wmi_data_hdr_remove(ar->arWmi, skb);
47689 +                wmi_control_rx(ar->arWmi, skb);
47690 +            } else {
47691 +                /*
47692 +                 * this is a wmi data packet
47693 +                 */
47694 +                minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
47695 +                            sizeof(ATH_LLC_SNAP_HDR);
47696 +
47697 +                if ((pPacket->ActualLength < minHdrLen) ||
47698 +                    (pPacket->ActualLength > AR6000_BUFFER_SIZE))
47699 +                {
47700 +                    /*
47701 +                     * packet is too short or too long
47702 +                     */
47703 +                    AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n");
47704 +                    AR6000_STAT_INC(ar, rx_errors);
47705 +                    AR6000_STAT_INC(ar, rx_length_errors);
47706 +                    A_NETBUF_FREE(skb);
47707 +                } else {
47708 +                    if (ar->arWmmEnabled) {
47709 +                        wmi_implicit_create_pstream(ar->arWmi, skb,
47710 +                            DNLINK_TRAFFIC, UNDEFINED_PRI);
47711 +                    }
47712 +#if 0
47713 +                    /* Access RSSI values here */
47714 +                    AR_DEBUG_PRINTF("RSSI %d\n",
47715 +                        ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi);
47716 +#endif
47717 +                    wmi_data_hdr_remove(ar->arWmi, skb);
47718 +                    wmi_dot3_2_dix(ar->arWmi, skb);
47719 +
47720 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
47721 +                    /*
47722 +                     * extra push and memcpy, for eth_type_trans() of 2.4 kernel
47723 +                     * will pull out hard_header_len bytes of the skb.
47724 +                     */
47725 +                    A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN);
47726 +                    A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) +
47727 +                             sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR));
47728 +#endif
47729 +                    if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
47730 +                    {
47731 +                        skb->dev = ar->arNetDev;
47732 +                        skb->protocol = eth_type_trans(skb, ar->arNetDev);
47733 +                        netif_rx(skb);
47734 +                    }
47735 +                    else
47736 +                    {
47737 +                        A_NETBUF_FREE(skb);
47738 +                    }
47739 +                }
47740 +            }
47741 +        }
47742 +    } else {
47743 +        if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
47744 +        {
47745 +            skb->dev = ar->arNetDev;
47746 +            skb->protocol = eth_type_trans(skb, ar->arNetDev);
47747 +            netif_rx(skb);
47748 +        }
47749 +        else
47750 +        {
47751 +            A_NETBUF_FREE(skb);
47752 +        }
47753 +    }
47754 +
47755 +    if (status != A_ECANCELED) {
47756 +        /*
47757 +         * HTC provides A_ECANCELED status when it doesn't want to be refilled
47758 +         * (probably due to a shutdown)
47759 +         */
47760 +        ar6000_rx_refill(Context, ept);
47761 +    }
47762 +
47763 +
47764 +}
47765 +
47766 +static void
47767 +ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint)
47768 +{
47769 +    AR_SOFTC_T  *ar = (AR_SOFTC_T *)Context;
47770 +    void        *osBuf;
47771 +    int         RxBuffers;
47772 +    int         buffersToRefill;
47773 +    HTC_PACKET  *pPacket;
47774 +    WMI_PRI_STREAM_ID streamId = arEndpoint2WMIStreamID(ar,Endpoint);
47775 +
47776 +    buffersToRefill = (int)AR6000_MAX_RX_BUFFERS -
47777 +                                    (int)ar->arRxBuffers[streamId];
47778 +
47779 +    if (buffersToRefill <= 0) {
47780 +            /* fast return, nothing to fill */
47781 +        return;
47782 +    }
47783 +
47784 +    AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n",
47785 +                    buffersToRefill, Endpoint);
47786 +
47787 +    for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) {
47788 +        osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE);
47789 +        if (NULL == osBuf) {
47790 +            break;
47791 +        }
47792 +            /* the HTC packet wrapper is at the head of the reserved area
47793 +             * in the skb */
47794 +        pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
47795 +            /* set re-fill info */
47796 +        SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint);
47797 +            /* add this packet */
47798 +        HTCAddReceivePkt(ar->arHtcTarget, pPacket);
47799 +    }
47800 +
47801 +        /* update count */
47802 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
47803 +    ar->arRxBuffers[streamId] += RxBuffers;
47804 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
47805 +}
47806 +
47807 +static struct net_device_stats *
47808 +ar6000_get_stats(struct net_device *dev)
47809 +{
47810 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
47811 +    return &ar->arNetStats;
47812 +}
47813 +
47814 +static struct iw_statistics *
47815 +ar6000_get_iwstats(struct net_device * dev)
47816 +{
47817 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
47818 +    TARGET_STATS *pStats = &ar->arTargetStats;
47819 +    struct iw_statistics * pIwStats = &ar->arIwStats;
47820 +
47821 +    if ((ar->arWmiReady == FALSE)
47822 +    /*
47823 +     * The in_atomic function is used to determine if the scheduling is
47824 +     * allowed in the current context or not. This was introduced in 2.6
47825 +     * From what I have read on the differences between 2.4 and 2.6, the
47826 +     * 2.4 kernel did not support preemption and so this check might not
47827 +     * be required for 2.4 kernels.
47828 +     */
47829 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
47830 +        || (in_atomic())
47831 +#endif
47832 +       )
47833 +    {
47834 +        pIwStats->status = 0;
47835 +        pIwStats->qual.qual = 0;
47836 +        pIwStats->qual.level =0;
47837 +        pIwStats->qual.noise = 0;
47838 +        pIwStats->discard.code =0;
47839 +        pIwStats->discard.retries=0;
47840 +        pIwStats->miss.beacon =0;
47841 +        return pIwStats;
47842 +    }
47843 +    if (down_interruptible(&ar->arSem)) {
47844 +        pIwStats->status = 0;
47845 +        return pIwStats;
47846 +    }
47847 +
47848 +
47849 +    ar->statsUpdatePending = TRUE;
47850 +
47851 +    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
47852 +        up(&ar->arSem);
47853 +        pIwStats->status = 0;
47854 +        return pIwStats;
47855 +    }
47856 +
47857 +    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
47858 +
47859 +    if (signal_pending(current)) {
47860 +        AR_DEBUG_PRINTF("ar6000 : WMI get stats timeout \n");
47861 +        up(&ar->arSem);
47862 +        pIwStats->status = 0;
47863 +        return pIwStats;
47864 +    }
47865 +    pIwStats->status = 1 ;
47866 +    pIwStats->qual.qual = pStats->cs_aveBeacon_rssi;
47867 +    pIwStats->qual.level =pStats->cs_aveBeacon_rssi + 161;  /* noise is -95 dBm */
47868 +    pIwStats->qual.noise = pStats->noise_floor_calibation;
47869 +    pIwStats->discard.code = pStats->rx_decrypt_err;
47870 +    pIwStats->discard.retries = pStats->tx_retry_cnt;
47871 +    pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
47872 +    up(&ar->arSem);
47873 +    return pIwStats;
47874 +}
47875 +
47876 +void
47877 +ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap)
47878 +{
47879 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
47880 +    struct net_device *dev = ar->arNetDev;
47881 +
47882 +    ar->arWmiReady = TRUE;
47883 +    wake_up(&arEvent);
47884 +    A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
47885 +    AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
47886 +        dev->dev_addr[0], dev->dev_addr[1],
47887 +        dev->dev_addr[2], dev->dev_addr[3],
47888 +        dev->dev_addr[4], dev->dev_addr[5]);
47889 +
47890 +    ar->arPhyCapability = phyCap;
47891 +}
47892 +
47893 +A_UINT8
47894 +ar6000_iptos_to_userPriority(A_UINT8 *pkt)
47895 +{
47896 +    struct iphdr *ipHdr = (struct iphdr *)pkt;
47897 +    A_UINT8 userPriority;
47898 +
47899 +    /*
47900 +     * IP Tos format :
47901 +     *      (Refer Pg 57 WMM-test-plan-v1.2)
47902 +     * IP-TOS - 8bits
47903 +     *          : DSCP(6-bits) ECN(2-bits)
47904 +     *          : DSCP - P2 P1 P0 X X X
47905 +     *              where (P2 P1 P0) form 802.1D
47906 +     */
47907 +    userPriority = ipHdr->tos >> 5;
47908 +    return (userPriority & 0x7);
47909 +}
47910 +
47911 +void
47912 +ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid,
47913 +                     A_UINT16 listenInterval, A_UINT16 beaconInterval,
47914 +                     NETWORK_TYPE networkType, A_UINT8 beaconIeLen,
47915 +                     A_UINT8 assocReqLen, A_UINT8 assocRespLen,
47916 +                     A_UINT8 *assocInfo)
47917 +{
47918 +    union iwreq_data wrqu;
47919 +    int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
47920 +    static const char *tag1 = "ASSOCINFO(ReqIEs=";
47921 +    static const char *tag2 = "ASSOCRESPIE=";
47922 +    static const char *beaconIetag = "BEACONIE=";
47923 +    char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + sizeof(tag1)];
47924 +    char *pos;
47925 +    A_UINT8 key_op_ctrl;
47926 +
47927 +    A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
47928 +    ar->arBssChannel = channel;
47929 +
47930 +    A_PRINTF("AR6000 connected event on freq %d ", channel);
47931 +    A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
47932 +            " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d"
47933 +            " assocRespLen =%d\n",
47934 +             bssid[0], bssid[1], bssid[2],
47935 +             bssid[3], bssid[4], bssid[5],
47936 +             listenInterval, beaconInterval,
47937 +             beaconIeLen, assocReqLen, assocRespLen);
47938 +    if (networkType & ADHOC_NETWORK) {
47939 +        if (networkType & ADHOC_CREATOR) {
47940 +            A_PRINTF("Network: Adhoc (Creator)\n");
47941 +        } else {
47942 +            A_PRINTF("Network: Adhoc (Joiner)\n");
47943 +        }
47944 +    } else {
47945 +        A_PRINTF("Network: Infrastructure\n");
47946 +    }
47947 +
47948 +    if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
47949 +        AR_DEBUG_PRINTF("\nBeaconIEs= ");
47950 +
47951 +        beacon_ie_pos = 0;
47952 +        A_MEMZERO(buf, sizeof(buf));
47953 +        sprintf(buf, "%s", beaconIetag);
47954 +        pos = buf + 9;
47955 +        for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
47956 +            AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
47957 +            sprintf(pos, "%2.2x", assocInfo[i]);
47958 +            pos += 2;
47959 +        }
47960 +        AR_DEBUG_PRINTF("\n");
47961 +
47962 +        A_MEMZERO(&wrqu, sizeof(wrqu));
47963 +        wrqu.data.length = strlen(buf);
47964 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
47965 +    }
47966 +
47967 +    if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2))))
47968 +    {
47969 +        assoc_resp_ie_pos = beaconIeLen + assocReqLen +
47970 +                            sizeof(A_UINT16)  +  /* capinfo*/
47971 +                            sizeof(A_UINT16)  +  /* status Code */
47972 +                            sizeof(A_UINT16)  ;  /* associd */
47973 +        A_MEMZERO(buf, sizeof(buf));
47974 +        sprintf(buf, "%s", tag2);
47975 +        pos = buf + 12;
47976 +        AR_DEBUG_PRINTF("\nAssocRespIEs= ");
47977 +        /*
47978 +         * The Association Response Frame w.o. the WLAN header is delivered to
47979 +         * the host, so skip over to the IEs
47980 +         */
47981 +        for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++)
47982 +        {
47983 +            AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
47984 +            sprintf(pos, "%2.2x", assocInfo[i]);
47985 +            pos += 2;
47986 +        }
47987 +        AR_DEBUG_PRINTF("\n");
47988 +
47989 +        A_MEMZERO(&wrqu, sizeof(wrqu));
47990 +        wrqu.data.length = strlen(buf);
47991 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
47992 +    }
47993 +
47994 +    if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
47995 +        /*
47996 +         * assoc Request includes capability and listen interval. Skip these.
47997 +         */
47998 +        assoc_req_ie_pos =  beaconIeLen +
47999 +                            sizeof(A_UINT16)  +  /* capinfo*/
48000 +                            sizeof(A_UINT16);    /* listen interval */
48001 +
48002 +        A_MEMZERO(buf, sizeof(buf));
48003 +        sprintf(buf, "%s", tag1);
48004 +        pos = buf + 17;
48005 +        AR_DEBUG_PRINTF("AssocReqIEs= ");
48006 +        for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) {
48007 +            AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
48008 +            sprintf(pos, "%2.2x", assocInfo[i]);
48009 +            pos += 2;;
48010 +        }
48011 +        AR_DEBUG_PRINTF("\n");
48012 +
48013 +        A_MEMZERO(&wrqu, sizeof(wrqu));
48014 +        wrqu.data.length = strlen(buf);
48015 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
48016 +    }
48017 +
48018 +#ifdef USER_KEYS
48019 +    if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN &&
48020 +        ar->user_saved_keys.keyOk == TRUE)
48021 +    {
48022 +
48023 +        key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC;
48024 +        if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) {
48025 +            key_op_ctrl &= ~KEY_OP_INIT_RSC;
48026 +        } else {
48027 +            key_op_ctrl |= KEY_OP_INIT_RSC;
48028 +        }
48029 +        ar6000_reinstall_keys(ar, key_op_ctrl);
48030 +    }
48031 +#endif /* USER_KEYS */
48032 +
48033 +        /* flush data queues */
48034 +    ar6000_TxDataCleanup(ar);
48035 +
48036 +    netif_wake_queue(ar->arNetDev);
48037 +
48038 +    if ((OPEN_AUTH == ar->arDot11AuthMode) &&
48039 +        (NONE_AUTH == ar->arAuthMode)      &&
48040 +        (WEP_CRYPT == ar->arPairwiseCrypto))
48041 +    {
48042 +        if (!ar->arConnected) {
48043 +            ar6000_install_static_wep_keys(ar);
48044 +        }
48045 +    }
48046 +
48047 +    ar->arConnected  = TRUE;
48048 +    ar->arConnectPending = FALSE;
48049 +
48050 +    reconnect_flag = 0;
48051 +
48052 +    A_MEMZERO(&wrqu, sizeof(wrqu));
48053 +    A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
48054 +    wrqu.addr.sa_family = ARPHRD_ETHER;
48055 +    wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
48056 +    if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
48057 +        A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
48058 +        ar->arNodeNum = 0;
48059 +        ar->arNexEpId = ENDPOINT_2;
48060 +    }
48061 +
48062 +}
48063 +
48064 +void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num)
48065 +{
48066 +    A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
48067 +    ar->arNumDataEndPts = num;
48068 +}
48069 +
48070 +void
48071 +ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid,
48072 +                        A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
48073 +{
48074 +    A_UINT8 i;
48075 +
48076 +    A_PRINTF("AR6000 disconnected");
48077 +    if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) {
48078 +        A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
48079 +                 bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
48080 +    }
48081 +    A_PRINTF("\n");
48082 +
48083 +    AR_DEBUG_PRINTF("\nDisconnect Reason is %d", reason);
48084 +    AR_DEBUG_PRINTF("\nProtocol Reason/Status Code is %d", protocolReasonStatus);
48085 +    AR_DEBUG_PRINTF("\nAssocResp Frame = %s",
48086 +                    assocRespLen ? " " : "NULL");
48087 +    for (i = 0; i < assocRespLen; i++) {
48088 +        if (!(i % 0x10)) {
48089 +            AR_DEBUG_PRINTF("\n");
48090 +        }
48091 +        AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
48092 +    }
48093 +    AR_DEBUG_PRINTF("\n");
48094 +    /*
48095 +     * If the event is due to disconnect cmd from the host, only they the target
48096 +     * would stop trying to connect. Under any other condition, target would
48097 +     * keep trying to connect.
48098 +     *
48099 +     */
48100 +    if( reason == DISCONNECT_CMD)
48101 +    {
48102 +        ar->arConnectPending = FALSE;
48103 +    } else {
48104 +        ar->arConnectPending = TRUE;
48105 +        if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) ||
48106 +            ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) {
48107 +            ar->arConnected = TRUE;
48108 +            return;
48109 +        }
48110 +    }
48111 +    ar->arConnected = FALSE;
48112 +
48113 +    if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) {
48114 +        reconnect_flag = 0;
48115 +    }
48116 +
48117 +#ifdef USER_KEYS
48118 +    if (reason != CSERV_DISCONNECT)
48119 +    {
48120 +        ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
48121 +        ar->user_key_ctrl      = 0;
48122 +    }
48123 +#endif /* USER_KEYS */
48124 +
48125 +    netif_stop_queue(ar->arNetDev);
48126 +    A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
48127 +    ar->arBssChannel = 0;
48128 +    ar->arBeaconInterval = 0;
48129 +
48130 +    ar6000_TxDataCleanup(ar);
48131 +}
48132 +
48133 +void
48134 +ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode)
48135 +{
48136 +    A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
48137 +    ar->arRegCode = regCode;
48138 +}
48139 +
48140 +void
48141 +ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info)
48142 +{
48143 +    static const char *tag = "PRE-AUTH";
48144 +    char buf[128];
48145 +    union iwreq_data wrqu;
48146 +    int i;
48147 +
48148 +    AR_DEBUG_PRINTF("AR6000 Neighbor Report Event\n");
48149 +    for (i=0; i < numAps; info++, i++) {
48150 +        AR_DEBUG_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
48151 +            info->bssid[0], info->bssid[1], info->bssid[2],
48152 +            info->bssid[3], info->bssid[4], info->bssid[5]);
48153 +        if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
48154 +            AR_DEBUG_PRINTF("preauth-cap");
48155 +        }
48156 +        if (info->bssFlags & WMI_PMKID_VALID_BSS) {
48157 +            AR_DEBUG_PRINTF(" pmkid-valid\n");
48158 +            continue;           /* we skip bss if the pmkid is already valid */
48159 +        }
48160 +        AR_DEBUG_PRINTF("\n");
48161 +        snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
48162 +                 tag,
48163 +                 info->bssid[0], info->bssid[1], info->bssid[2],
48164 +                 info->bssid[3], info->bssid[4], info->bssid[5],
48165 +                 i, info->bssFlags);
48166 +        A_MEMZERO(&wrqu, sizeof(wrqu));
48167 +        wrqu.data.length = strlen(buf);
48168 +        wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
48169 +    }
48170 +}
48171 +
48172 +void
48173 +ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
48174 +{
48175 +    static const char *tag = "MLME-MICHAELMICFAILURE.indication";
48176 +    char buf[128];
48177 +    union iwreq_data wrqu;
48178 +
48179 +    A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
48180 +             keyid, ismcast ? "multi": "uni");
48181 +    snprintf(buf, sizeof(buf), "%s(keyid=%d %scat)", tag, keyid,
48182 +             ismcast ? "multi" : "uni");
48183 +    memset(&wrqu, 0, sizeof(wrqu));
48184 +    wrqu.data.length = strlen(buf);
48185 +    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
48186 +}
48187 +
48188 +void
48189 +ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
48190 +{
48191 +       AR_DEBUG_PRINTF("AR6000 scan complete: %d\n", status);
48192 +
48193 +       ar->scan_complete = 1;
48194 +       wake_up_interruptible(&ar6000_scan_queue);
48195 +}
48196 +
48197 +void
48198 +ar6000_targetStats_event(AR_SOFTC_T *ar,  WMI_TARGET_STATS *pTarget)
48199 +{
48200 +    TARGET_STATS *pStats = &ar->arTargetStats;
48201 +    A_UINT8 ac;
48202 +
48203 +    /*A_PRINTF("AR6000 updating target stats\n");*/
48204 +    pStats->tx_packets          += pTarget->txrxStats.tx_stats.tx_packets;
48205 +    pStats->tx_bytes            += pTarget->txrxStats.tx_stats.tx_bytes;
48206 +    pStats->tx_unicast_pkts     += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
48207 +    pStats->tx_unicast_bytes    += pTarget->txrxStats.tx_stats.tx_unicast_bytes;
48208 +    pStats->tx_multicast_pkts   += pTarget->txrxStats.tx_stats.tx_multicast_pkts;
48209 +    pStats->tx_multicast_bytes  += pTarget->txrxStats.tx_stats.tx_multicast_bytes;
48210 +    pStats->tx_broadcast_pkts   += pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
48211 +    pStats->tx_broadcast_bytes  += pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
48212 +    pStats->tx_rts_success_cnt  += pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
48213 +    for(ac = 0; ac < WMM_NUM_AC; ac++)
48214 +        pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
48215 +    pStats->tx_errors           += pTarget->txrxStats.tx_stats.tx_errors;
48216 +    pStats->tx_failed_cnt       += pTarget->txrxStats.tx_stats.tx_failed_cnt;
48217 +    pStats->tx_retry_cnt        += pTarget->txrxStats.tx_stats.tx_retry_cnt;
48218 +    pStats->tx_rts_fail_cnt     += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
48219 +    pStats->tx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate);
48220 +
48221 +    pStats->rx_packets          += pTarget->txrxStats.rx_stats.rx_packets;
48222 +    pStats->rx_bytes            += pTarget->txrxStats.rx_stats.rx_bytes;
48223 +    pStats->rx_unicast_pkts     += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
48224 +    pStats->rx_unicast_bytes    += pTarget->txrxStats.rx_stats.rx_unicast_bytes;
48225 +    pStats->rx_multicast_pkts   += pTarget->txrxStats.rx_stats.rx_multicast_pkts;
48226 +    pStats->rx_multicast_bytes  += pTarget->txrxStats.rx_stats.rx_multicast_bytes;
48227 +    pStats->rx_broadcast_pkts   += pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
48228 +    pStats->rx_broadcast_bytes  += pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
48229 +    pStats->rx_fragment_pkt     += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
48230 +    pStats->rx_errors           += pTarget->txrxStats.rx_stats.rx_errors;
48231 +    pStats->rx_crcerr           += pTarget->txrxStats.rx_stats.rx_crcerr;
48232 +    pStats->rx_key_cache_miss   += pTarget->txrxStats.rx_stats.rx_key_cache_miss;
48233 +    pStats->rx_decrypt_err      += pTarget->txrxStats.rx_stats.rx_decrypt_err;
48234 +    pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames;
48235 +    pStats->rx_unicast_rate      = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate);
48236 +
48237 +
48238 +    pStats->tkip_local_mic_failure
48239 +                                += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
48240 +    pStats->tkip_counter_measures_invoked
48241 +                                += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
48242 +    pStats->tkip_replays        += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
48243 +    pStats->tkip_format_errors  += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
48244 +    pStats->ccmp_format_errors  += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
48245 +    pStats->ccmp_replays        += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
48246 +
48247 +
48248 +    pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt;
48249 +    pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
48250 +
48251 +    pStats->cs_bmiss_cnt        += pTarget->cservStats.cs_bmiss_cnt;
48252 +    pStats->cs_lowRssi_cnt      += pTarget->cservStats.cs_lowRssi_cnt;
48253 +    pStats->cs_connect_cnt      += pTarget->cservStats.cs_connect_cnt;
48254 +    pStats->cs_disconnect_cnt   += pTarget->cservStats.cs_disconnect_cnt;
48255 +    pStats->cs_aveBeacon_snr    = pTarget->cservStats.cs_aveBeacon_snr;
48256 +    pStats->cs_aveBeacon_rssi   = pTarget->cservStats.cs_aveBeacon_rssi;
48257 +    pStats->cs_lastRoam_msec    = pTarget->cservStats.cs_lastRoam_msec;
48258 +    pStats->cs_snr              = pTarget->cservStats.cs_snr;
48259 +    pStats->cs_rssi             = pTarget->cservStats.cs_rssi;
48260 +
48261 +    pStats->lq_val              = pTarget->lqVal;
48262 +
48263 +    pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped;
48264 +    pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups;
48265 +    pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups;
48266 +    pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded;
48267 +
48268 +    ar->statsUpdatePending = FALSE;
48269 +    wake_up(&arEvent);
48270 +}
48271 +
48272 +void
48273 +ar6000_rssiThreshold_event(AR_SOFTC_T *ar,  WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi)
48274 +{
48275 +    USER_RSSI_THOLD userRssiThold;
48276 +
48277 +    userRssiThold.tag = rssi_map[newThreshold].tag;
48278 +    userRssiThold.rssi = rssi;
48279 +    AR_DEBUG2_PRINTF("rssi Threshold range = %d tag = %d  rssi = %d\n", newThreshold, userRssiThold.tag, rssi);
48280 +#ifdef SEND_EVENT_TO_APP
48281 +    ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD));
48282 +#endif
48283 +}
48284 +
48285 +
48286 +void
48287 +ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source)
48288 +{
48289 +    if (source == APP_HB_CHALLENGE) {
48290 +        /* Report it to the app in case it wants a positive acknowledgement */
48291 +#ifdef SEND_EVENT_TO_APP
48292 +        ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID,
48293 +                                 (A_UINT8 *)&cookie, sizeof(cookie));
48294 +#endif
48295 +    } else {
48296 +        /* This would ignore the replys that come in after their due time */
48297 +        if (cookie == ar->arHBChallengeResp.seqNum) {
48298 +            ar->arHBChallengeResp.outstanding = FALSE;
48299 +        }
48300 +    }
48301 +}
48302 +
48303 +
48304 +void
48305 +ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal)
48306 +{
48307 +    char    *errString[] = {
48308 +                [WMI_TARGET_PM_ERR_FAIL]    "WMI_TARGET_PM_ERR_FAIL",
48309 +                [WMI_TARGET_KEY_NOT_FOUND]  "WMI_TARGET_KEY_NOT_FOUND",
48310 +                [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
48311 +                [WMI_TARGET_BMISS]          "WMI_TARGET_BMISS",
48312 +                [WMI_PSDISABLE_NODE_JOIN]   "WMI_PSDISABLE_NODE_JOIN"
48313 +                };
48314 +
48315 +    A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
48316 +
48317 +    /* One error is reported at a time, and errorval is a bitmask */
48318 +    if(errorVal & (errorVal - 1))
48319 +       return;
48320 +
48321 +    A_PRINTF("AR6000 Error type = ");
48322 +    switch(errorVal)
48323 +    {
48324 +        case WMI_TARGET_PM_ERR_FAIL:
48325 +        case WMI_TARGET_KEY_NOT_FOUND:
48326 +        case WMI_TARGET_DECRYPTION_ERR:
48327 +        case WMI_TARGET_BMISS:
48328 +        case WMI_PSDISABLE_NODE_JOIN:
48329 +            A_PRINTF("%s\n", errString[errorVal]);
48330 +            break;
48331 +        default:
48332 +            A_PRINTF("INVALID\n");
48333 +            break;
48334 +    }
48335 +
48336 +}
48337 +
48338 +
48339 +void
48340 +ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication,
48341 +                 A_UINT8 statusCode, A_UINT8 *tspecSuggestion)
48342 +{
48343 +    WMM_TSPEC_IE    *tspecIe;
48344 +
48345 +    /*
48346 +     * This is the TSPEC IE suggestion from AP.
48347 +     * Suggestion provided by AP under some error
48348 +     * cases, could be helpful for the host app.
48349 +     * Check documentation.
48350 +     */
48351 +    tspecIe = (WMM_TSPEC_IE *)tspecSuggestion;
48352 +
48353 +    /*
48354 +     * What do we do, if we get TSPEC rejection? One thought
48355 +     * that comes to mind is implictly delete the pstream...
48356 +     */
48357 +    A_PRINTF("AR6000 CAC notification. "
48358 +                "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
48359 +                 ac, cacIndication, statusCode);
48360 +}
48361 +
48362 +#define AR6000_PRINT_BSSID(_pBss)  do {     \
48363 +        A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
48364 +                 (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
48365 +                 (_pBss)[4],(_pBss)[5]);  \
48366 +} while(0)
48367 +
48368 +void
48369 +ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl)
48370 +{
48371 +    A_UINT8 i;
48372 +
48373 +    A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
48374 +              pTbl->numEntries, pTbl->roamMode);
48375 +    for (i= 0; i < pTbl->numEntries; i++) {
48376 +        A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
48377 +            pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1],
48378 +            pTbl->bssRoamInfo[i].bssid[2],
48379 +            pTbl->bssRoamInfo[i].bssid[3],
48380 +            pTbl->bssRoamInfo[i].bssid[4],
48381 +            pTbl->bssRoamInfo[i].bssid[5]);
48382 +        A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
48383 +                 " BIAS %d\n",
48384 +            pTbl->bssRoamInfo[i].rssi,
48385 +            pTbl->bssRoamInfo[i].rssidt,
48386 +            pTbl->bssRoamInfo[i].last_rssi,
48387 +            pTbl->bssRoamInfo[i].util,
48388 +            pTbl->bssRoamInfo[i].roam_util,
48389 +            pTbl->bssRoamInfo[i].bias);
48390 +    }
48391 +}
48392 +
48393 +void
48394 +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply)
48395 +{
48396 +    A_UINT8 i,j;
48397 +
48398 +    /*Each event now contains exactly one filter, see bug 26613*/
48399 +    A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num,                 wow_reply->num_filters);
48400 +    A_PRINTF("wow mode = %s host mode = %s\n",
48401 +            (wow_reply->wow_mode == 0? "disabled":"enabled"),
48402 +            (wow_reply->host_mode == 1 ? "awake":"asleep"));
48403 +
48404 +
48405 +    /*If there are no patterns, the reply will only contain generic
48406 +      WoW information. Pattern information will exist only if there are
48407 +      patterns present. Bug 26716*/
48408 +
48409 +   /* If this event contains pattern information, display it*/
48410 +    if (wow_reply->this_filter_num) {
48411 +        i=0;
48412 +        A_PRINTF("id=%d size=%d offset=%d\n",
48413 +                    wow_reply->wow_filters[i].wow_filter_id,
48414 +                    wow_reply->wow_filters[i].wow_filter_size,
48415 +                    wow_reply->wow_filters[i].wow_filter_offset);
48416 +       A_PRINTF("wow pattern = ");
48417 +       for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
48418 +             A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]);
48419 +        }
48420 +
48421 +        A_PRINTF("\nwow mask = ");
48422 +        for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
48423 +            A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]);
48424 +        }
48425 +        A_PRINTF("\n");
48426 +    }
48427 +}
48428 +
48429 +/*
48430 + * Report the Roaming related data collected on the target
48431 + */
48432 +void
48433 +ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p)
48434 +{
48435 +    A_PRINTF("Disconnect Data : BSSID: ");
48436 +    AR6000_PRINT_BSSID(p->disassoc_bssid);
48437 +    A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
48438 +             p->disassoc_bss_rssi,p->disassoc_time,
48439 +             p->no_txrx_time);
48440 +    A_PRINTF("Connect Data: BSSID: ");
48441 +    AR6000_PRINT_BSSID(p->assoc_bssid);
48442 +    A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
48443 +             p->assoc_bss_rssi,p->assoc_time,
48444 +             p->allow_txrx_time);
48445 +    A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\
48446 +             "First Data Tx Time (after Assoc) %d\n",
48447 +             p->last_data_txrx_time, p->first_data_txrx_time);
48448 +}
48449 +
48450 +void
48451 +ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p)
48452 +{
48453 +    switch (p->roamDataType) {
48454 +        case ROAM_DATA_TIME:
48455 +            ar6000_display_roam_time(&p->u.roamTime);
48456 +            break;
48457 +        default:
48458 +            break;
48459 +    }
48460 +}
48461 +
48462 +void
48463 +ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len)
48464 +{
48465 +    struct sk_buff *skb;
48466 +    WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap;
48467 +
48468 +
48469 +    if (!ar->arMgmtFilter) {
48470 +        return;
48471 +    }
48472 +    if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) &&
48473 +        (bih->frameType != BEACON_FTYPE))  ||
48474 +        ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) &&
48475 +        (bih->frameType != PROBERESP_FTYPE)))
48476 +    {
48477 +        return;
48478 +    }
48479 +
48480 +    if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) {
48481 +
48482 +        A_NETBUF_PUT(skb, len);
48483 +        A_MEMCPY(A_NETBUF_DATA(skb), datap, len);
48484 +        skb->dev = ar->arNetDev;
48485 +       printk("MAC RAW...\n");
48486 +//        skb->mac.raw = A_NETBUF_DATA(skb);
48487 +        skb->ip_summed = CHECKSUM_NONE;
48488 +        skb->pkt_type = PACKET_OTHERHOST;
48489 +        skb->protocol = __constant_htons(0x0019);
48490 +        netif_rx(skb);
48491 +    }
48492 +}
48493 +
48494 +A_UINT32 wmiSendCmdNum;
48495 +
48496 +A_STATUS
48497 +ar6000_control_tx(void *devt, void *osbuf, WMI_PRI_STREAM_ID streamID)
48498 +{
48499 +    AR_SOFTC_T       *ar = (AR_SOFTC_T *)devt;
48500 +    A_STATUS         status = A_OK;
48501 +    struct ar_cookie *cookie = NULL;
48502 +    int i;
48503 +
48504 +        /* take lock to protect ar6000_alloc_cookie() */
48505 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
48506 +
48507 +    do {
48508 +
48509 +        AR_DEBUG2_PRINTF("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x, sid=%d\n",
48510 +                         (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), streamID);
48511 +
48512 +        if ((streamID == WMI_CONTROL_PRI) && (ar->arWMIControlEpFull)) {
48513 +                /* control endpoint is full, don't allocate resources, we
48514 +                 * are just going to drop this packet */
48515 +            cookie = NULL;
48516 +            AR_DEBUG_PRINTF(" WMI Control EP full, dropping packet : 0x%X, len:%d \n",
48517 +                    (A_UINT32)osbuf, A_NETBUF_LEN(osbuf));
48518 +        } else {
48519 +            cookie = ar6000_alloc_cookie(ar);
48520 +        }
48521 +
48522 +        if (cookie == NULL) {
48523 +            status = A_NO_MEMORY;
48524 +            break;
48525 +        }
48526 +
48527 +        if(logWmiRawMsgs) {
48528 +            A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum);
48529 +            for(i = 0; i < a_netbuf_to_len(osbuf); i++)
48530 +                A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]);
48531 +            A_PRINTF("\n");
48532 +        }
48533 +
48534 +        wmiSendCmdNum++;
48535 +
48536 +    } while (FALSE);
48537 +
48538 +    if (cookie != NULL) {
48539 +            /* got a structure to send it out on */
48540 +        ar->arTxPending[streamID]++;
48541 +
48542 +        if (streamID != WMI_CONTROL_PRI) {
48543 +            ar->arTotalTxDataPending++;
48544 +        }
48545 +    }
48546 +
48547 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
48548 +
48549 +    if (cookie != NULL) {
48550 +        cookie->arc_bp[0] = (A_UINT32)osbuf;
48551 +        cookie->arc_bp[1] = 0;
48552 +        SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
48553 +                               cookie,
48554 +                               A_NETBUF_DATA(osbuf),
48555 +                               A_NETBUF_LEN(osbuf),
48556 +                               arWMIStream2EndpointID(ar,streamID),
48557 +                               AR6K_CONTROL_PKT_TAG);
48558 +            /* this interface is asynchronous, if there is an error, cleanup will happen in the
48559 +             * TX completion callback */
48560 +        HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
48561 +        status = A_OK;
48562 +    }
48563 +
48564 +    return status;
48565 +}
48566 +
48567 +/* indicate tx activity or inactivity on a WMI stream */
48568 +void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active)
48569 +{
48570 +    AR_SOFTC_T  *ar = (AR_SOFTC_T *)devt;
48571 +    WMI_PRI_STREAM_ID streamid;
48572 +
48573 +    if (ar->arWmiEnabled) {
48574 +        streamid = wmi_get_stream_id(ar->arWmi, TrafficClass);
48575 +    } else {
48576 +            /* for mbox ping testing, the traffic class is mapped directly as a stream ID,
48577 +             * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */
48578 +        streamid = (WMI_PRI_STREAM_ID)TrafficClass;
48579 +    }
48580 +
48581 +        /* notify HTC, this may cause credit distribution changes */
48582 +
48583 +    HTCIndicateActivityChange(ar->arHtcTarget,
48584 +                              arWMIStream2EndpointID(ar,streamid),
48585 +                              Active);
48586 +
48587 +}
48588 +
48589 +module_init(ar6000_init_module);
48590 +module_exit(ar6000_cleanup_module);
48591 +
48592 +/* Init cookie queue */
48593 +static void
48594 +ar6000_cookie_init(AR_SOFTC_T *ar)
48595 +{
48596 +    A_UINT32    i;
48597 +
48598 +    ar->arCookieList = NULL;
48599 +    A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
48600 +
48601 +    for (i = 0; i < MAX_COOKIE_NUM; i++) {
48602 +        ar6000_free_cookie(ar, &s_ar_cookie_mem[i]);
48603 +    }
48604 +}
48605 +
48606 +/* cleanup cookie queue */
48607 +static void
48608 +ar6000_cookie_cleanup(AR_SOFTC_T *ar)
48609 +{
48610 +    /* It is gone .... */
48611 +    ar->arCookieList = NULL;
48612 +}
48613 +
48614 +/* Init cookie queue */
48615 +static void
48616 +ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie)
48617 +{
48618 +    /* Insert first */
48619 +    A_ASSERT(ar != NULL);
48620 +    A_ASSERT(cookie != NULL);
48621 +    cookie->arc_list_next = ar->arCookieList;
48622 +    ar->arCookieList = cookie;
48623 +}
48624 +
48625 +/* cleanup cookie queue */
48626 +static struct ar_cookie *
48627 +ar6000_alloc_cookie(AR_SOFTC_T  *ar)
48628 +{
48629 +    struct ar_cookie   *cookie;
48630 +
48631 +    cookie = ar->arCookieList;
48632 +    if(cookie != NULL)
48633 +    {
48634 +        ar->arCookieList = cookie->arc_list_next;
48635 +    }
48636 +
48637 +    return cookie;
48638 +}
48639 +
48640 +#ifdef SEND_EVENT_TO_APP
48641 +/*
48642 + * This function is used to send event which come from taget to
48643 + * the application. The buf which send to application is include
48644 + * the event ID and event content.
48645 + */
48646 +#define EVENT_ID_LEN   2
48647 +void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
48648 +                              A_UINT8 *datap, int len)
48649 +{
48650 +
48651 +#if (WIRELESS_EXT >= 15)
48652 +
48653 +/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */
48654 +
48655 +    char *buf;
48656 +    A_UINT16 size;
48657 +    union iwreq_data wrqu;
48658 +
48659 +    size = len + EVENT_ID_LEN;
48660 +
48661 +    if (size > IW_CUSTOM_MAX) {
48662 +        AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n",
48663 +                eventId, size, IW_CUSTOM_MAX);
48664 +        return;
48665 +    }
48666 +
48667 +    buf = A_MALLOC_NOWAIT(size);
48668 +    A_MEMZERO(buf, size);
48669 +    A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
48670 +    A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
48671 +
48672 +    //AR_DEBUG_PRINTF("event ID = %d,len = %d\n",*(A_UINT16*)buf, size);
48673 +    A_MEMZERO(&wrqu, sizeof(wrqu));
48674 +    wrqu.data.length = size;
48675 +    wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
48676 +
48677 +    A_FREE(buf);
48678 +#endif
48679 +
48680 +
48681 +}
48682 +#endif
48683 +
48684 +
48685 +void
48686 +ar6000_tx_retry_err_event(void *devt)
48687 +{
48688 +    AR_DEBUG2_PRINTF("Tx retries reach maximum!\n");
48689 +}
48690 +
48691 +void
48692 +ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr)
48693 +{
48694 +    AR_DEBUG2_PRINTF("snr threshold range %d, snr %d\n", newThreshold, snr);
48695 +}
48696 +
48697 +void
48698 +ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq)
48699 +{
48700 +    AR_DEBUG2_PRINTF("lq threshold range %d, lq %d\n", newThreshold, lq);
48701 +}
48702 +
48703 +
48704 +
48705 +A_UINT32
48706 +a_copy_to_user(void *to, const void *from, A_UINT32 n)
48707 +{
48708 +    return(copy_to_user(to, from, n));
48709 +}
48710 +
48711 +A_UINT32
48712 +a_copy_from_user(void *to, const void *from, A_UINT32 n)
48713 +{
48714 +    return(copy_from_user(to, from, n));
48715 +}
48716 +
48717 +
48718 +A_STATUS
48719 +ar6000_get_driver_cfg(struct net_device *dev,
48720 +                        A_UINT16 cfgParam,
48721 +                        void *result)
48722 +{
48723 +
48724 +    A_STATUS    ret = 0;
48725 +
48726 +    switch(cfgParam)
48727 +    {
48728 +        case AR6000_DRIVER_CFG_GET_WLANNODECACHING:
48729 +           *((A_UINT32 *)result) = wlanNodeCaching;
48730 +           break;
48731 +        case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS:
48732 +           *((A_UINT32 *)result) = logWmiRawMsgs;
48733 +            break;
48734 +        default:
48735 +           ret = EINVAL;
48736 +           break;
48737 +    }
48738 +
48739 +    return ret;
48740 +}
48741 +
48742 +void
48743 +ar6000_keepalive_rx(void *devt, A_UINT8 configured)
48744 +{
48745 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
48746 +
48747 +    ar->arKeepaliveConfigured = configured;
48748 +    wake_up(&arEvent);
48749 +}
48750 +
48751 +void
48752 +ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList)
48753 +{
48754 +    A_UINT8 i, j;
48755 +
48756 +    A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID);
48757 +
48758 +    for (i = 0; i < numPMKID; i++) {
48759 +        A_PRINTF("\nPMKID %d ", i);
48760 +            for (j = 0; j < WMI_PMKID_LEN; j++) {
48761 +                A_PRINTF("%2.2x", pmkidList->pmkid[j]);
48762 +            }
48763 +        pmkidList++;
48764 +    }
48765 +}
48766 +
48767 +#ifdef USER_KEYS
48768 +static A_STATUS
48769 +
48770 +ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl)
48771 +{
48772 +    A_STATUS status = A_OK;
48773 +    struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik;
48774 +    struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik;
48775 +    CRYPTO_TYPE  keyType = ar->user_saved_keys.keyType;
48776 +
48777 +    if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) {
48778 +        if (NONE_CRYPT == keyType) {
48779 +            goto _reinstall_keys_out;
48780 +        }
48781 +
48782 +        if (uik->ik_keylen) {
48783 +            status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix,
48784 +                    ar->user_saved_keys.keyType, PAIRWISE_USAGE,
48785 +                    uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc,
48786 +                    uik->ik_keydata, key_op_ctrl, SYNC_BEFORE_WMIFLAG);
48787 +        }
48788 +
48789 +    } else {
48790 +        status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata);
48791 +    }
48792 +
48793 +    if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) {
48794 +        if (NONE_CRYPT == keyType) {
48795 +            goto _reinstall_keys_out;
48796 +        }
48797 +
48798 +        if (bik->ik_keylen) {
48799 +            status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix,
48800 +                    ar->user_saved_keys.keyType, GROUP_USAGE,
48801 +                    bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc,
48802 +                    bik->ik_keydata, key_op_ctrl, NO_SYNC_WMIFLAG);
48803 +        }
48804 +    } else {
48805 +        status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata);
48806 +    }
48807 +
48808 +_reinstall_keys_out:
48809 +    ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
48810 +    ar->user_key_ctrl      = 0;
48811 +
48812 +    return status;
48813 +}
48814 +#endif /* USER_KEYS */
48815 +
48816 +
48817 +void
48818 +ar6000_dset_open_req(
48819 +    void *context,
48820 +    A_UINT32 id,
48821 +    A_UINT32 targHandle,
48822 +    A_UINT32 targReplyFn,
48823 +    A_UINT32 targReplyArg)
48824 +{
48825 +}
48826 +
48827 +void
48828 +ar6000_dset_close(
48829 +    void *context,
48830 +    A_UINT32 access_cookie)
48831 +{
48832 +    return;
48833 +}
48834 +
48835 +void
48836 +ar6000_dset_data_req(
48837 +   void *context,
48838 +   A_UINT32 accessCookie,
48839 +   A_UINT32 offset,
48840 +   A_UINT32 length,
48841 +   A_UINT32 targBuf,
48842 +   A_UINT32 targReplyFn,
48843 +   A_UINT32 targReplyArg)
48844 +{
48845 +}
48846 Index: linux-2.6.28/drivers/ar6000/ar6000/ar6000_drv.h
48847 ===================================================================
48848 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
48849 +++ linux-2.6.28/drivers/ar6000/ar6000/ar6000_drv.h     2009-01-02 00:01:56.000000000 +0100
48850 @@ -0,0 +1,361 @@
48851 +/*
48852 + *
48853 + * Copyright (c) 2004-2007 Atheros Communications Inc.
48854 + * All rights reserved.
48855 + *
48856 + *
48857 + *  This program is free software; you can redistribute it and/or modify
48858 + *  it under the terms of the GNU General Public License version 2 as
48859 + *  published by the Free Software Foundation;
48860 + *
48861 + *  Software distributed under the License is distributed on an "AS
48862 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
48863 + *  implied. See the License for the specific language governing
48864 + *  rights and limitations under the License.
48865 + *
48866 + *
48867 + *
48868 + */
48869 +
48870 +#ifndef _AR6000_H_
48871 +#define _AR6000_H_
48872 +
48873 +#include <linux/version.h>
48874 +
48875 +
48876 +#include <linux/autoconf.h>
48877 +#include <linux/init.h>
48878 +#include <linux/kernel.h>
48879 +#include <linux/spinlock.h>
48880 +#include <linux/skbuff.h>
48881 +#include <linux/if_ether.h>
48882 +#include <linux/netdevice.h>
48883 +#include <linux/etherdevice.h>
48884 +#include <net/iw_handler.h>
48885 +#include <linux/if_arp.h>
48886 +#include <linux/ip.h>
48887 +#include <linux/semaphore.h>
48888 +#include <linux/wireless.h>
48889 +#include <linux/module.h>
48890 +#include <asm/io.h>
48891 +
48892 +#include <a_config.h>
48893 +#include <athdefs.h>
48894 +#include "a_types.h"
48895 +#include "a_osapi.h"
48896 +#include "htc_api.h"
48897 +#include "wmi.h"
48898 +#include "a_drv.h"
48899 +#include "bmi.h"
48900 +#include <ieee80211.h>
48901 +#include <ieee80211_ioctl.h>
48902 +#include <wlan_api.h>
48903 +#include <wmi_api.h>
48904 +#include "gpio_api.h"
48905 +#include "gpio.h"
48906 +#include <host_version.h>
48907 +#include <linux/rtnetlink.h>
48908 +#include <linux/init.h>
48909 +#include <linux/moduleparam.h>
48910 +#include "AR6Khwreg.h"
48911 +#include "ar6000_api.h"
48912 +#ifdef CONFIG_HOST_TCMD_SUPPORT
48913 +#include <testcmd.h>
48914 +#endif
48915 +
48916 +#include "targaddrs.h"
48917 +#include "dbglog_api.h"
48918 +#include "ar6000_diag.h"
48919 +#include "common_drv.h"
48920 +
48921 +#ifndef  __dev_put
48922 +#define  __dev_put(dev) dev_put(dev)
48923 +#endif
48924 +
48925 +#ifdef USER_KEYS
48926 +
48927 +#define USER_SAVEDKEYS_STAT_INIT     0
48928 +#define USER_SAVEDKEYS_STAT_RUN      1
48929 +
48930 +// TODO this needs to move into the AR_SOFTC struct
48931 +struct USER_SAVEDKEYS {
48932 +    struct ieee80211req_key   ucast_ik;
48933 +    struct ieee80211req_key   bcast_ik;
48934 +    CRYPTO_TYPE               keyType;
48935 +    A_BOOL                    keyOk;
48936 +};
48937 +#endif
48938 +
48939 +#define DBG_INFO               0x00000001
48940 +#define DBG_ERROR              0x00000002
48941 +#define DBG_WARNING            0x00000004
48942 +#define DBG_SDIO               0x00000008
48943 +#define DBG_HIF                        0x00000010
48944 +#define DBG_HTC                        0x00000020
48945 +#define DBG_WMI                        0x00000040
48946 +#define DBG_WMI2               0x00000080
48947 +#define DBG_DRIVER             0x00000100
48948 +
48949 +#define DBG_DEFAULTS   (DBG_ERROR|DBG_WARNING)
48950 +
48951 +
48952 +#ifdef DEBUG
48953 +#define AR_DEBUG_PRINTF(args...)        if (debugdriver) A_PRINTF(args);
48954 +#define AR_DEBUG2_PRINTF(args...)        if (debugdriver >= 2) A_PRINTF(args);
48955 +extern int debugdriver;
48956 +#else
48957 +#define AR_DEBUG_PRINTF(args...)
48958 +#define AR_DEBUG2_PRINTF(args...)
48959 +#endif
48960 +
48961 +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
48962 +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
48963 +
48964 +#ifdef __cplusplus
48965 +extern "C" {
48966 +#endif
48967 +
48968 +#define        MAX_AR6000                        1
48969 +#define AR6000_MAX_RX_BUFFERS             16
48970 +#define AR6000_BUFFER_SIZE                1664
48971 +#define AR6000_TX_TIMEOUT                 10
48972 +#define        AR6000_ETH_ADDR_LEN               6
48973 +#define        AR6000_MAX_ENDPOINTS              4
48974 +#define MAX_NODE_NUM                      15
48975 +#define MAX_COOKIE_NUM                    150
48976 +#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT        1
48977 +#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT  1
48978 +
48979 +enum {
48980 +    DRV_HB_CHALLENGE = 0,
48981 +    APP_HB_CHALLENGE
48982 +};
48983 +
48984 +/* HTC RAW streams */
48985 +typedef enum _HTC_RAW_STREAM_ID {
48986 +    HTC_RAW_STREAM_NOT_MAPPED = -1,
48987 +    HTC_RAW_STREAM_0 = 0,
48988 +    HTC_RAW_STREAM_1 = 1,
48989 +    HTC_RAW_STREAM_2 = 2,
48990 +    HTC_RAW_STREAM_3 = 3,
48991 +    HTC_RAW_STREAM_NUM_MAX
48992 +} HTC_RAW_STREAM_ID;
48993 +
48994 +#define RAW_HTC_READ_BUFFERS_NUM    4
48995 +#define RAW_HTC_WRITE_BUFFERS_NUM   4
48996 +
48997 +typedef struct {
48998 +    int currPtr;
48999 +    int length;
49000 +    unsigned char data[AR6000_BUFFER_SIZE];
49001 +    HTC_PACKET    HTCPacket;
49002 +} raw_htc_buffer;
49003 +
49004 +#ifdef CONFIG_HOST_TCMD_SUPPORT
49005 +/*
49006 + *  add TCMD_MODE besides wmi and bypasswmi
49007 + *  in TCMD_MODE, only few TCMD releated wmi commands
49008 + *  counld be hanlder
49009 + */
49010 +enum {
49011 +    AR6000_WMI_MODE = 0,
49012 +    AR6000_BYPASS_MODE,
49013 +    AR6000_TCMD_MODE,
49014 +    AR6000_WLAN_MODE
49015 +};
49016 +#endif /* CONFIG_HOST_TCMD_SUPPORT */
49017 +
49018 +struct ar_wep_key {
49019 +    A_UINT8                 arKeyIndex;
49020 +    A_UINT8                 arKeyLen;
49021 +    A_UINT8                 arKey[64];
49022 +} ;
49023 +
49024 +struct ar_node_mapping {
49025 +    A_UINT8                 macAddress[6];
49026 +    A_UINT8                 epId;
49027 +    A_UINT8                 txPending;
49028 +};
49029 +
49030 +struct ar_cookie {
49031 +    A_UINT32               arc_bp[2];    /* Must be first field */
49032 +    HTC_PACKET             HtcPkt;       /* HTC packet wrapper */
49033 +    struct ar_cookie *arc_list_next;
49034 +};
49035 +
49036 +struct ar_hb_chlng_resp {
49037 +    A_TIMER                 timer;
49038 +    A_UINT32                frequency;
49039 +    A_UINT32                seqNum;
49040 +    A_BOOL                  outstanding;
49041 +    A_UINT8                 missCnt;
49042 +    A_UINT8                 missThres;
49043 +};
49044 +
49045 +typedef struct ar6_softc {
49046 +    struct net_device       *arNetDev;    /* net_device pointer */
49047 +    void                    *arWmi;
49048 +    int                     arTxPending[WMI_PRI_MAX_COUNT];
49049 +    int                     arTotalTxDataPending;
49050 +    A_UINT8                 arNumDataEndPts;
49051 +    A_BOOL                  arWmiEnabled;
49052 +    A_BOOL                  arWmiReady;
49053 +    A_BOOL                  arConnected;
49054 +    A_BOOL                  arRadioSwitch;
49055 +    HTC_HANDLE              arHtcTarget;
49056 +    void                    *arHifDevice;
49057 +    spinlock_t              arLock;
49058 +    struct semaphore        arSem;
49059 +    int                     arRxBuffers[WMI_PRI_MAX_COUNT];
49060 +    int                     arSsidLen;
49061 +    u_char                  arSsid[32];
49062 +    A_UINT8                 arNetworkType;
49063 +    A_UINT8                 arDot11AuthMode;
49064 +    A_UINT8                 arAuthMode;
49065 +    A_UINT8                 arPairwiseCrypto;
49066 +    A_UINT8                 arPairwiseCryptoLen;
49067 +    A_UINT8                 arGroupCrypto;
49068 +    A_UINT8                 arGroupCryptoLen;
49069 +    A_UINT8                 arDefTxKeyIndex;
49070 +    struct ar_wep_key       arWepKeyList[WMI_MAX_KEY_INDEX + 1];
49071 +    A_UINT8                 arBssid[6];
49072 +    A_UINT8                 arReqBssid[6];
49073 +    A_UINT16                arChannelHint;
49074 +    A_UINT16                arBssChannel;
49075 +    A_UINT16                arListenInterval;
49076 +    struct ar6000_version   arVersion;
49077 +    A_UINT32                arTargetType;
49078 +    A_INT8                  arRssi;
49079 +    A_UINT8                 arTxPwr;
49080 +    A_BOOL                  arTxPwrSet;
49081 +    A_INT32                 arBitRate;
49082 +    struct net_device_stats arNetStats;
49083 +    struct iw_statistics       arIwStats;
49084 +    A_INT8                  arNumChannels;
49085 +    A_UINT16                arChannelList[32];
49086 +    A_UINT32                arRegCode;
49087 +    A_BOOL                  statsUpdatePending;
49088 +    TARGET_STATS            arTargetStats;
49089 +    A_INT8                  arMaxRetries;
49090 +    A_UINT8                 arPhyCapability;
49091 +#ifdef CONFIG_HOST_TCMD_SUPPORT
49092 +    A_UINT8                 tcmdRxReport;
49093 +    A_UINT32                tcmdRxTotalPkt;
49094 +    A_INT32                 tcmdRxRssi;
49095 +    A_UINT32                tcmdPm;
49096 +   A_UINT32                 arTargetMode;
49097 +#endif
49098 +    AR6000_WLAN_STATE       arWlanState;
49099 +    struct ar_node_mapping  arNodeMap[MAX_NODE_NUM];
49100 +    A_UINT8                 arIbssPsEnable;
49101 +    A_UINT8                 arNodeNum;
49102 +    A_UINT8                 arNexEpId;
49103 +    struct ar_cookie        *arCookieList;
49104 +    A_UINT16                arRateMask;
49105 +    A_UINT8                 arSkipScan;
49106 +    A_UINT16                arBeaconInterval;
49107 +    A_BOOL                  arConnectPending;
49108 +    A_BOOL                  arWmmEnabled;
49109 +    struct ar_hb_chlng_resp arHBChallengeResp;
49110 +    A_UINT8                 arKeepaliveConfigured;
49111 +    A_UINT32                arMgmtFilter;
49112 +    HTC_ENDPOINT_ID         arWmi2EpMapping[WMI_PRI_MAX_COUNT];
49113 +    WMI_PRI_STREAM_ID       arEp2WmiMapping[ENDPOINT_MAX];
49114 +#ifdef HTC_RAW_INTERFACE
49115 +    HTC_ENDPOINT_ID         arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX];
49116 +    HTC_RAW_STREAM_ID       arEp2RawMapping[ENDPOINT_MAX];
49117 +    struct semaphore        raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX];
49118 +    struct semaphore        raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX];
49119 +    wait_queue_head_t       raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX];
49120 +    wait_queue_head_t       raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX];
49121 +    raw_htc_buffer          *raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
49122 +    raw_htc_buffer          *raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
49123 +    A_BOOL                  write_buffer_available[HTC_RAW_STREAM_NUM_MAX];
49124 +    A_BOOL                  read_buffer_available[HTC_RAW_STREAM_NUM_MAX];
49125 +#endif
49126 +    A_BOOL                  arNetQueueStopped;
49127 +    A_BOOL                  arRawIfInit;
49128 +    int                     arDeviceIndex;
49129 +    COMMON_CREDIT_STATE_INFO arCreditStateInfo;
49130 +    A_BOOL                  arWMIControlEpFull;
49131 +    A_BOOL                  dbgLogFetchInProgress;
49132 +    A_UCHAR                 log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE];
49133 +    A_UINT32                log_cnt;
49134 +    A_UINT32                dbglog_init_done;
49135 +    A_UINT32                arConnectCtrlFlags;
49136 +       A_UINT32                scan_complete;
49137 +#ifdef USER_KEYS
49138 +    A_INT32                 user_savedkeys_stat;
49139 +    A_UINT32                user_key_ctrl;
49140 +    struct USER_SAVEDKEYS   user_saved_keys;
49141 +#endif
49142 +} AR_SOFTC_T;
49143 +
49144 +
49145 +#define arWMIStream2EndpointID(ar,wmi)          (ar)->arWmi2EpMapping[(wmi)]
49146 +#define arSetWMIStream2EndpointIDMap(ar,wmi,ep)  \
49147 +{  (ar)->arWmi2EpMapping[(wmi)] = (ep); \
49148 +   (ar)->arEp2WmiMapping[(ep)] = (wmi); }
49149 +#define arEndpoint2WMIStreamID(ar,ep)           (ar)->arEp2WmiMapping[(ep)]
49150 +
49151 +#define arRawIfEnabled(ar) (ar)->arRawIfInit
49152 +#define arRawStream2EndpointID(ar,raw)          (ar)->arRaw2EpMapping[(raw)]
49153 +#define arSetRawStream2EndpointIDMap(ar,raw,ep)  \
49154 +{  (ar)->arRaw2EpMapping[(raw)] = (ep); \
49155 +   (ar)->arEp2RawMapping[(ep)] = (raw); }
49156 +#define arEndpoint2RawStreamID(ar,ep)           (ar)->arEp2RawMapping[(ep)]
49157 +
49158 +struct ar_giwscan_param {
49159 +    char    *current_ev;
49160 +    char    *end_buf;
49161 +    A_BOOL  firstPass;
49162 +};
49163 +
49164 +#define AR6000_STAT_INC(ar, stat)       (ar->arNetStats.stat++)
49165 +
49166 +#define AR6000_SPIN_LOCK(lock, param)   do {                            \
49167 +    if (irqs_disabled()) {                                              \
49168 +        AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n");                 \
49169 +    }                                                                   \
49170 +    spin_lock_bh(lock);                                                 \
49171 +} while (0)
49172 +
49173 +#define AR6000_SPIN_UNLOCK(lock, param) do {                            \
49174 +    if (irqs_disabled()) {                                              \
49175 +        AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n");              \
49176 +    }                                                                   \
49177 +    spin_unlock_bh(lock);                                               \
49178 +} while (0)
49179 +
49180 +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
49181 +int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd);
49182 +void ar6000_ioctl_iwsetup(struct iw_handler_def *def);
49183 +void ar6000_gpio_init(void);
49184 +void ar6000_init_profile_info(AR_SOFTC_T *ar);
49185 +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar);
49186 +int ar6000_init(struct net_device *dev);
49187 +int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar);
49188 +A_STATUS ar6000_SetHTCBlockSize(AR_SOFTC_T *ar);
49189 +
49190 +#ifdef HTC_RAW_INTERFACE
49191 +
49192 +#ifndef __user
49193 +#define __user
49194 +#endif
49195 +
49196 +int ar6000_htc_raw_open(AR_SOFTC_T *ar);
49197 +int ar6000_htc_raw_close(AR_SOFTC_T *ar);
49198 +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar,
49199 +                            HTC_RAW_STREAM_ID StreamID,
49200 +                            char __user *buffer, size_t count);
49201 +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar,
49202 +                             HTC_RAW_STREAM_ID StreamID,
49203 +                             char __user *buffer, size_t count);
49204 +
49205 +#endif /* HTC_RAW_INTERFACE */
49206 +
49207 +#ifdef __cplusplus
49208 +}
49209 +#endif
49210 +
49211 +#endif /* _AR6000_H_ */
49212 Index: linux-2.6.28/drivers/ar6000/ar6000/ar6000_raw_if.c
49213 ===================================================================
49214 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
49215 +++ linux-2.6.28/drivers/ar6000/ar6000/ar6000_raw_if.c  2009-01-02 00:01:56.000000000 +0100
49216 @@ -0,0 +1,439 @@
49217 +/*
49218 + *
49219 + * Copyright (c) 2004-2007 Atheros Communications Inc.
49220 + * All rights reserved.
49221 + *
49222 + *
49223 + *  This program is free software; you can redistribute it and/or modify
49224 + *  it under the terms of the GNU General Public License version 2 as
49225 + *  published by the Free Software Foundation;
49226 + *
49227 + *  Software distributed under the License is distributed on an "AS
49228 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
49229 + *  implied. See the License for the specific language governing
49230 + *  rights and limitations under the License.
49231 + *
49232 + *
49233 + *
49234 + */
49235 +
49236 +#include "ar6000_drv.h"
49237 +
49238 +#ifdef HTC_RAW_INTERFACE
49239 +
49240 +static void
49241 +ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket)
49242 +{
49243 +    AR_SOFTC_T        *ar = (AR_SOFTC_T *)Context;
49244 +    raw_htc_buffer    *busy;
49245 +    HTC_RAW_STREAM_ID streamID;
49246 +
49247 +    busy = (raw_htc_buffer *)pPacket->pPktContext;
49248 +    A_ASSERT(busy != NULL);
49249 +
49250 +    if (pPacket->Status == A_ECANCELED) {
49251 +        /*
49252 +         * HTC provides A_ECANCELED status when it doesn't want to be refilled
49253 +         * (probably due to a shutdown)
49254 +         */
49255 +        return;
49256 +    }
49257 +
49258 +    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
49259 +    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
49260 +
49261 +#ifdef CF
49262 +   if (down_trylock(&ar->raw_htc_read_sem[streamID])) {
49263 +#else
49264 +    if (down_interruptible(&ar->raw_htc_read_sem[streamID])) {
49265 +#endif /* CF */
49266 +        AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
49267 +    }
49268 +
49269 +    A_ASSERT((pPacket->Status != A_OK) ||
49270 +             (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN)));
49271 +
49272 +    busy->length = pPacket->ActualLength + HTC_HEADER_LEN;
49273 +    busy->currPtr = HTC_HEADER_LEN;
49274 +    ar->read_buffer_available[streamID] = TRUE;
49275 +    //AR_DEBUG_PRINTF("raw read cb:  0x%X 0x%X \n", busy->currPtr,busy->length);
49276 +    up(&ar->raw_htc_read_sem[streamID]);
49277 +
49278 +    /* Signal the waiting process */
49279 +    AR_DEBUG2_PRINTF("Waking up the StreamID(%d) read process\n", streamID);
49280 +    wake_up_interruptible(&ar->raw_htc_read_queue[streamID]);
49281 +}
49282 +
49283 +static void
49284 +ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket)
49285 +{
49286 +    AR_SOFTC_T          *ar = (AR_SOFTC_T  *)Context;
49287 +    raw_htc_buffer      *free;
49288 +    HTC_RAW_STREAM_ID   streamID;
49289 +
49290 +    free = (raw_htc_buffer *)pPacket->pPktContext;
49291 +    A_ASSERT(free != NULL);
49292 +
49293 +    if (pPacket->Status == A_ECANCELED) {
49294 +        /*
49295 +         * HTC provides A_ECANCELED status when it doesn't want to be refilled
49296 +         * (probably due to a shutdown)
49297 +         */
49298 +        return;
49299 +    }
49300 +
49301 +    streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
49302 +    A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
49303 +
49304 +#ifdef CF
49305 +    if (down_trylock(&ar->raw_htc_write_sem[streamID])) {
49306 +#else
49307 +    if (down_interruptible(&ar->raw_htc_write_sem[streamID])) {
49308 +#endif
49309 +        AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
49310 +    }
49311 +
49312 +    A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN));
49313 +
49314 +    free->length = 0;
49315 +    ar->write_buffer_available[streamID] = TRUE;
49316 +    up(&ar->raw_htc_write_sem[streamID]);
49317 +
49318 +    /* Signal the waiting process */
49319 +    AR_DEBUG2_PRINTF("Waking up the StreamID(%d) write process\n", streamID);
49320 +    wake_up_interruptible(&ar->raw_htc_write_queue[streamID]);
49321 +}
49322 +
49323 +/* connect to a service */
49324 +static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T        *ar,
49325 +                                           HTC_RAW_STREAM_ID StreamID)
49326 +{
49327 +    A_STATUS                 status;
49328 +    HTC_SERVICE_CONNECT_RESP response;
49329 +    A_UINT8                  streamNo;
49330 +    HTC_SERVICE_CONNECT_REQ  connect;
49331 +
49332 +    do {
49333 +
49334 +        A_MEMZERO(&connect,sizeof(connect));
49335 +            /* pass the stream ID as meta data to the RAW streams service */
49336 +        streamNo = (A_UINT8)StreamID;
49337 +        connect.pMetaData = &streamNo;
49338 +        connect.MetaDataLength = sizeof(A_UINT8);
49339 +            /* these fields are the same for all endpoints */
49340 +        connect.EpCallbacks.pContext = ar;
49341 +        connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb;
49342 +        connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb;
49343 +            /* simple interface, we don't need these optional callbacks */
49344 +        connect.EpCallbacks.EpRecvRefill = NULL;
49345 +        connect.EpCallbacks.EpSendFull = NULL;
49346 +        connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM;
49347 +
49348 +            /* connect to the raw streams service, we may be able to get 1 or more
49349 +             * connections, depending on WHAT is running on the target */
49350 +        connect.ServiceID = HTC_RAW_STREAMS_SVC;
49351 +
49352 +        A_MEMZERO(&response,sizeof(response));
49353 +
49354 +            /* try to connect to the raw stream, it is okay if this fails with
49355 +             * status HTC_SERVICE_NO_MORE_EP */
49356 +        status = HTCConnectService(ar->arHtcTarget,
49357 +                                   &connect,
49358 +                                   &response);
49359 +
49360 +        if (A_FAILED(status)) {
49361 +            if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) {
49362 +                AR_DEBUG_PRINTF("HTC RAW , No more streams allowed \n");
49363 +                status = A_OK;
49364 +            }
49365 +            break;
49366 +        }
49367 +
49368 +            /* set endpoint mapping for the RAW HTC streams */
49369 +        arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint);
49370 +
49371 +        AR_DEBUG_PRINTF("HTC RAW : stream ID: %d, endpoint: %d\n",
49372 +                        StreamID, arRawStream2EndpointID(ar,StreamID));
49373 +
49374 +    } while (FALSE);
49375 +
49376 +    return status;
49377 +}
49378 +
49379 +int ar6000_htc_raw_open(AR_SOFTC_T *ar)
49380 +{
49381 +    A_STATUS status;
49382 +    int streamID, endPt, count2;
49383 +    raw_htc_buffer *buffer;
49384 +    HTC_SERVICE_ID servicepriority;
49385 +
49386 +    A_ASSERT(ar->arHtcTarget != NULL);
49387 +
49388 +        /* wait for target */
49389 +    status = HTCWaitTarget(ar->arHtcTarget);
49390 +
49391 +    if (A_FAILED(status)) {
49392 +        AR_DEBUG_PRINTF("HTCWaitTarget failed (%d)\n", status);
49393 +        return -ENODEV;
49394 +    }
49395 +
49396 +    for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) {
49397 +        ar->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED;
49398 +    }
49399 +
49400 +    for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) {
49401 +        /* Initialize the data structures */
49402 +        init_MUTEX(&ar->raw_htc_read_sem[streamID]);
49403 +        init_MUTEX(&ar->raw_htc_write_sem[streamID]);
49404 +        init_waitqueue_head(&ar->raw_htc_read_queue[streamID]);
49405 +        init_waitqueue_head(&ar->raw_htc_write_queue[streamID]);
49406 +
49407 +            /* try to connect to the raw service */
49408 +        status = ar6000_connect_raw_service(ar,streamID);
49409 +
49410 +        if (A_FAILED(status)) {
49411 +            break;
49412 +        }
49413 +
49414 +        if (arRawStream2EndpointID(ar,streamID) == 0) {
49415 +            break;
49416 +        }
49417 +
49418 +        for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) {
49419 +            /* Initialize the receive buffers */
49420 +            buffer = ar->raw_htc_write_buffer[streamID][count2];
49421 +            memset(buffer, 0, sizeof(raw_htc_buffer));
49422 +            buffer = ar->raw_htc_read_buffer[streamID][count2];
49423 +            memset(buffer, 0, sizeof(raw_htc_buffer));
49424 +
49425 +            SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket,
49426 +                                          buffer,
49427 +                                          buffer->data,
49428 +                                          AR6000_BUFFER_SIZE,
49429 +                                          arRawStream2EndpointID(ar,streamID));
49430 +
49431 +            /* Queue buffers to HTC for receive */
49432 +            if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK)
49433 +            {
49434 +                BMIInit();
49435 +                return -EIO;
49436 +            }
49437 +        }
49438 +
49439 +        for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) {
49440 +            /* Initialize the receive buffers */
49441 +            buffer = ar->raw_htc_write_buffer[streamID][count2];
49442 +            memset(buffer, 0, sizeof(raw_htc_buffer));
49443 +        }
49444 +
49445 +        ar->read_buffer_available[streamID] = FALSE;
49446 +        ar->write_buffer_available[streamID] = TRUE;
49447 +    }
49448 +
49449 +    if (A_FAILED(status)) {
49450 +        return -EIO;
49451 +    }
49452 +
49453 +    AR_DEBUG_PRINTF("HTC RAW, number of streams the target supports: %d \n", streamID);
49454 +
49455 +    servicepriority = HTC_RAW_STREAMS_SVC;  /* only 1 */
49456 +
49457 +        /* set callbacks and priority list */
49458 +    HTCSetCreditDistribution(ar->arHtcTarget,
49459 +                             ar,
49460 +                             NULL,  /* use default */
49461 +                             NULL,  /* use default */
49462 +                             &servicepriority,
49463 +                             1);
49464 +
49465 +    /* Start the HTC component */
49466 +    if ((status = HTCStart(ar->arHtcTarget)) != A_OK) {
49467 +        BMIInit();
49468 +        return -EIO;
49469 +    }
49470 +
49471 +    (ar)->arRawIfInit = TRUE;
49472 +
49473 +    return 0;
49474 +}
49475 +
49476 +int ar6000_htc_raw_close(AR_SOFTC_T *ar)
49477 +{
49478 +    A_PRINTF("ar6000_htc_raw_close called \n");
49479 +    HTCStop(ar->arHtcTarget);
49480 +
49481 +        /* reset the device */
49482 +    ar6000_reset_device(ar->arHifDevice, ar->arTargetType);
49483 +    /* Initialize the BMI component */
49484 +    BMIInit();
49485 +
49486 +    return 0;
49487 +}
49488 +
49489 +raw_htc_buffer *
49490 +get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID)
49491 +{
49492 +    int count;
49493 +    raw_htc_buffer *busy;
49494 +
49495 +    /* Check for data */
49496 +    for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) {
49497 +        busy = ar->raw_htc_read_buffer[StreamID][count];
49498 +        if (busy->length) {
49499 +            break;
49500 +        }
49501 +    }
49502 +    if (busy->length) {
49503 +        ar->read_buffer_available[StreamID] = TRUE;
49504 +    } else {
49505 +        ar->read_buffer_available[StreamID] = FALSE;
49506 +    }
49507 +
49508 +    return busy;
49509 +}
49510 +
49511 +ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
49512 +                            char __user *buffer, size_t length)
49513 +{
49514 +    int readPtr;
49515 +    raw_htc_buffer *busy;
49516 +
49517 +    if (arRawStream2EndpointID(ar,StreamID) == 0) {
49518 +        AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID);
49519 +        return -EFAULT;
49520 +    }
49521 +
49522 +    if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) {
49523 +        return -ERESTARTSYS;
49524 +    }
49525 +
49526 +    busy = get_filled_buffer(ar,StreamID);
49527 +    while (!ar->read_buffer_available[StreamID]) {
49528 +        up(&ar->raw_htc_read_sem[StreamID]);
49529 +
49530 +        /* Wait for the data */
49531 +        AR_DEBUG2_PRINTF("Sleeping StreamID(%d) read process\n", StreamID);
49532 +        if (wait_event_interruptible(ar->raw_htc_read_queue[StreamID],
49533 +                                     ar->read_buffer_available[StreamID]))
49534 +        {
49535 +            return -EINTR;
49536 +        }
49537 +        if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) {
49538 +            return -ERESTARTSYS;
49539 +        }
49540 +        busy = get_filled_buffer(ar,StreamID);
49541 +    }
49542 +
49543 +    /* Read the data */
49544 +    readPtr = busy->currPtr;
49545 +    if (length > busy->length - HTC_HEADER_LEN) {
49546 +        length = busy->length - HTC_HEADER_LEN;
49547 +    }
49548 +    if (copy_to_user(buffer, &busy->data[readPtr], length)) {
49549 +        up(&ar->raw_htc_read_sem[StreamID]);
49550 +        return -EFAULT;
49551 +    }
49552 +
49553 +    busy->currPtr += length;
49554 +
49555 +    //AR_DEBUG_PRINTF("raw read ioctl:  currPTR : 0x%X 0x%X \n", busy->currPtr,busy->length);
49556 +
49557 +    if (busy->currPtr == busy->length)
49558 +    {
49559 +        busy->currPtr = 0;
49560 +        busy->length = 0;
49561 +        HTC_PACKET_RESET_RX(&busy->HTCPacket);
49562 +        //AR_DEBUG_PRINTF("raw read ioctl:  ep for packet:%d \n", busy->HTCPacket.Endpoint);
49563 +        HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket);
49564 +    }
49565 +    ar->read_buffer_available[StreamID] = FALSE;
49566 +    up(&ar->raw_htc_read_sem[StreamID]);
49567 +
49568 +    return length;
49569 +}
49570 +
49571 +static raw_htc_buffer *
49572 +get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID)
49573 +{
49574 +    int count;
49575 +    raw_htc_buffer *free;
49576 +
49577 +    free = NULL;
49578 +    for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) {
49579 +        free = ar->raw_htc_write_buffer[StreamID][count];
49580 +        if (free->length == 0) {
49581 +            break;
49582 +        }
49583 +    }
49584 +    if (!free->length) {
49585 +        ar->write_buffer_available[StreamID] = TRUE;
49586 +    } else {
49587 +        ar->write_buffer_available[StreamID] = FALSE;
49588 +    }
49589 +
49590 +    return free;
49591 +}
49592 +
49593 +ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
49594 +                     char __user *buffer, size_t length)
49595 +{
49596 +    int writePtr;
49597 +    raw_htc_buffer *free;
49598 +
49599 +    if (arRawStream2EndpointID(ar,StreamID) == 0) {
49600 +        AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID);
49601 +        return -EFAULT;
49602 +    }
49603 +
49604 +    if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) {
49605 +        return -ERESTARTSYS;
49606 +    }
49607 +
49608 +    /* Search for a free buffer */
49609 +    free = get_free_buffer(ar,StreamID);
49610 +
49611 +    /* Check if there is space to write else wait */
49612 +    while (!ar->write_buffer_available[StreamID]) {
49613 +        up(&ar->raw_htc_write_sem[StreamID]);
49614 +
49615 +        /* Wait for buffer to become free */
49616 +        AR_DEBUG2_PRINTF("Sleeping StreamID(%d) write process\n", StreamID);
49617 +        if (wait_event_interruptible(ar->raw_htc_write_queue[StreamID],
49618 +                                     ar->write_buffer_available[StreamID]))
49619 +        {
49620 +            return -EINTR;
49621 +        }
49622 +        if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) {
49623 +            return -ERESTARTSYS;
49624 +        }
49625 +        free = get_free_buffer(ar,StreamID);
49626 +    }
49627 +
49628 +    /* Send the data */
49629 +    writePtr = HTC_HEADER_LEN;
49630 +    if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) {
49631 +        length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN;
49632 +    }
49633 +
49634 +    if (copy_from_user(&free->data[writePtr], buffer, length)) {
49635 +        up(&ar->raw_htc_read_sem[StreamID]);
49636 +        return -EFAULT;
49637 +    }
49638 +
49639 +    free->length = length;
49640 +
49641 +    SET_HTC_PACKET_INFO_TX(&free->HTCPacket,
49642 +                           free,
49643 +                           &free->data[writePtr],
49644 +                           length,
49645 +                           arRawStream2EndpointID(ar,StreamID),
49646 +                           AR6K_DATA_PKT_TAG);
49647 +
49648 +    HTCSendPkt(ar->arHtcTarget,&free->HTCPacket);
49649 +
49650 +    ar->write_buffer_available[StreamID] = FALSE;
49651 +    up(&ar->raw_htc_write_sem[StreamID]);
49652 +
49653 +    return length;
49654 +}
49655 +#endif /* HTC_RAW_INTERFACE */
49656 Index: linux-2.6.28/drivers/ar6000/ar6000/ar6xapi_linux.h
49657 ===================================================================
49658 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
49659 +++ linux-2.6.28/drivers/ar6000/ar6000/ar6xapi_linux.h  2009-01-02 00:01:56.000000000 +0100
49660 @@ -0,0 +1,128 @@
49661 +#ifndef _AR6XAPI_LINUX_H
49662 +#define _AR6XAPI_LINUX_H
49663 +/*
49664 + *
49665 + * Copyright (c) 2004-2007 Atheros Communications Inc.
49666 + * All rights reserved.
49667 + *
49668 + *
49669 + *  This program is free software; you can redistribute it and/or modify
49670 + *  it under the terms of the GNU General Public License version 2 as
49671 + *  published by the Free Software Foundation;
49672 + *
49673 + *  Software distributed under the License is distributed on an "AS
49674 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
49675 + *  implied. See the License for the specific language governing
49676 + *  rights and limitations under the License.
49677 + *
49678 + *
49679 + *
49680 + */
49681 +
49682 +#ifdef __cplusplus
49683 +extern "C" {
49684 +#endif
49685 +
49686 +struct ar6_softc;
49687 +
49688 +void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap);
49689 +A_UINT8 ar6000_iptos_to_userPriority(A_UINT8 *pkt);
49690 +A_STATUS ar6000_control_tx(void *devt, void *osbuf, WMI_PRI_STREAM_ID streamID);
49691 +void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel,
49692 +                          A_UINT8 *bssid, A_UINT16 listenInterval,
49693 +                          A_UINT16 beaconInterval, NETWORK_TYPE networkType,
49694 +                          A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
49695 +                          A_UINT8 assocRespLen,A_UINT8 *assocInfo);
49696 +void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason,
49697 +                             A_UINT8 *bssid, A_UINT8 assocRespLen,
49698 +                             A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
49699 +void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid,
49700 +                              A_BOOL ismcast);
49701 +void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps);
49702 +void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList);
49703 +void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode);
49704 +void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr);
49705 +void ar6000_keepalive_rx(void *devt, A_UINT8 configured);
49706 +void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps,
49707 +                                 WMI_NEIGHBOR_INFO *info);
49708 +void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num);
49709 +void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status);
49710 +void ar6000_targetStats_event(struct ar6_softc *ar,  WMI_TARGET_STATS *pStats);
49711 +void ar6000_rssiThreshold_event(struct ar6_softc *ar,
49712 +                                WMI_RSSI_THRESHOLD_VAL newThreshold,
49713 +                                A_INT16 rssi);
49714 +void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal);
49715 +void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication,
49716 +                                A_UINT8 statusCode, A_UINT8 *tspecSuggestion);
49717 +void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source);
49718 +void
49719 +ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl);
49720 +
49721 +void
49722 +ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p);
49723 +
49724 +void
49725 +ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters,
49726 +                      WMI_GET_WOW_LIST_REPLY *wow_reply);
49727 +
49728 +void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID,
49729 +                             WMI_PMKID *pmkidList);
49730 +
49731 +void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values);
49732 +void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value);
49733 +void ar6000_gpio_ack_rx(void);
49734 +
49735 +void ar6000_dbglog_init_done(struct ar6_softc *ar);
49736 +
49737 +#ifdef SEND_EVENT_TO_APP
49738 +void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
49739 +#endif
49740 +
49741 +#ifdef CONFIG_HOST_TCMD_SUPPORT
49742 +void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len);
49743 +#endif
49744 +
49745 +void ar6000_tx_retry_err_event(void *devt);
49746 +
49747 +void ar6000_snrThresholdEvent_rx(void *devt,
49748 +                                 WMI_SNR_THRESHOLD_VAL newThreshold,
49749 +                                 A_UINT8 snr);
49750 +
49751 +void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal);
49752 +
49753 +
49754 +void ar6000_ratemask_rx(void *devt, A_UINT16 ratemask);
49755 +
49756 +A_STATUS ar6000_get_driver_cfg(struct net_device *dev,
49757 +                                A_UINT16 cfgParam,
49758 +                                void *result);
49759 +void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len);
49760 +
49761 +void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped,
49762 +                         A_INT8 *buffer, A_UINT32 length);
49763 +
49764 +int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar);
49765 +
49766 +void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active);
49767 +
49768 +void ar6000_dset_open_req(void *devt,
49769 +                          A_UINT32 id,
49770 +                          A_UINT32 targ_handle,
49771 +                          A_UINT32 targ_reply_fn,
49772 +                          A_UINT32 targ_reply_arg);
49773 +void ar6000_dset_close(void *devt, A_UINT32 access_cookie);
49774 +void ar6000_dset_data_req(void *devt,
49775 +                          A_UINT32 access_cookie,
49776 +                          A_UINT32 offset,
49777 +                          A_UINT32 length,
49778 +                          A_UINT32 targ_buf,
49779 +                          A_UINT32 targ_reply_fn,
49780 +                          A_UINT32 targ_reply_arg);
49781 +
49782 +
49783 +
49784 +#ifdef __cplusplus
49785 +}
49786 +#endif
49787 +
49788 +#endif
49789 Index: linux-2.6.28/drivers/ar6000/ar6000/athdrv_linux.h
49790 ===================================================================
49791 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
49792 +++ linux-2.6.28/drivers/ar6000/ar6000/athdrv_linux.h   2009-01-02 00:01:56.000000000 +0100
49793 @@ -0,0 +1,993 @@
49794 +/*
49795 + * Copyright (c) 2004-2006 Atheros Communications Inc.
49796 + * All rights reserved.
49797 + *
49798 + *
49799 + *
49800 + *  This program is free software; you can redistribute it and/or modify
49801 + *  it under the terms of the GNU General Public License version 2 as
49802 + *  published by the Free Software Foundation;
49803 + *
49804 + *  Software distributed under the License is distributed on an "AS
49805 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
49806 + *  implied. See the License for the specific language governing
49807 + *  rights and limitations under the License.
49808 + *
49809 + *
49810 + *
49811 + */
49812 +
49813 +#ifndef _ATHDRV_LINUX_H
49814 +#define _ATHDRV_LINUX_H
49815 +
49816 +#ifdef __cplusplus
49817 +extern "C" {
49818 +#endif
49819 +
49820 +
49821 +/*
49822 + * There are two types of ioctl's here: Standard ioctls and
49823 + * eXtended ioctls.  All extended ioctls (XIOCTL) are multiplexed
49824 + * off of the single ioctl command, AR6000_IOCTL_EXTENDED.  The
49825 + * arguments for every XIOCTL starts with a 32-bit command word
49826 + * that is used to select which extended ioctl is in use.  After
49827 + * the command word are command-specific arguments.
49828 + */
49829 +
49830 +/* Linux standard Wireless Extensions, private ioctl interfaces */
49831 +#define IEEE80211_IOCTL_SETPARAM             (SIOCIWFIRSTPRIV+0)
49832 +#define IEEE80211_IOCTL_GETPARAM             (SIOCIWFIRSTPRIV+1)
49833 +#define IEEE80211_IOCTL_SETKEY               (SIOCIWFIRSTPRIV+2)
49834 +#define IEEE80211_IOCTL_SETWMMPARAMS         (SIOCIWFIRSTPRIV+3)
49835 +#define IEEE80211_IOCTL_DELKEY               (SIOCIWFIRSTPRIV+4)
49836 +#define IEEE80211_IOCTL_GETWMMPARAMS         (SIOCIWFIRSTPRIV+5)
49837 +#define IEEE80211_IOCTL_SETOPTIE             (SIOCIWFIRSTPRIV+6)
49838 +#define IEEE80211_IOCTL_SETMLME              (SIOCIWFIRSTPRIV+7)
49839 +//#define IEEE80211_IOCTL_GETOPTIE             (SIOCIWFIRSTPRIV+7)
49840 +#define IEEE80211_IOCTL_ADDPMKID             (SIOCIWFIRSTPRIV+8)
49841 +//#define IEEE80211_IOCTL_SETAUTHALG           (SIOCIWFIRSTPRIV+10)
49842 +#define IEEE80211_IOCTL_LASTONE              (SIOCIWFIRSTPRIV+9)
49843 +
49844 +
49845 +
49846 +/*                      ====WMI Ioctls====                                    */
49847 +/*
49848 + *
49849 + * Many ioctls simply provide WMI services to application code:
49850 + * an application makes such an ioctl call with a set of arguments
49851 + * that are packaged into the corresponding WMI message, and sent
49852 + * to the Target.
49853 + */
49854 +
49855 +#define AR6000_IOCTL_WMI_GETREV              (SIOCIWFIRSTPRIV+10)
49856 +/*
49857 + * arguments:
49858 + *   ar6000_version *revision
49859 + */
49860 +
49861 +#define AR6000_IOCTL_WMI_SETPWR              (SIOCIWFIRSTPRIV+11)
49862 +/*
49863 + * arguments:
49864 + *   WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
49865 + * uses: WMI_SET_POWER_MODE_CMDID
49866 + */
49867 +
49868 +#define AR6000_IOCTL_WMI_SETSCAN             (SIOCIWFIRSTPRIV+12)
49869 +/*
49870 + * arguments:
49871 + *   WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
49872 + * uses: WMI_SET_SCAN_PARAMS_CMDID
49873 + */
49874 +
49875 +#define AR6000_IOCTL_WMI_SETLISTENINT        (SIOCIWFIRSTPRIV+13)
49876 +/*
49877 + * arguments:
49878 + *   UINT32 listenInterval
49879 + * uses: WMI_SET_LISTEN_INT_CMDID
49880 + */
49881 +
49882 +#define AR6000_IOCTL_WMI_SETBSSFILTER        (SIOCIWFIRSTPRIV+14)
49883 +/*
49884 + * arguments:
49885 + *   WMI_BSS_FILTER filter (see include/wmi.h)
49886 + * uses: WMI_SET_BSS_FILTER_CMDID
49887 + */
49888 +
49889 +#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS   (SIOCIWFIRSTPRIV+16)
49890 +/*
49891 + * arguments:
49892 + *   WMI_CHANNEL_PARAMS_CMD chParams
49893 + * uses: WMI_SET_CHANNEL_PARAMS_CMDID
49894 + */
49895 +
49896 +#define AR6000_IOCTL_WMI_SET_PROBEDSSID      (SIOCIWFIRSTPRIV+17)
49897 +/*
49898 + * arguments:
49899 + *   WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
49900 + * uses: WMI_SETPROBED_SSID_CMDID
49901 + */
49902 +
49903 +#define AR6000_IOCTL_WMI_SET_PMPARAMS        (SIOCIWFIRSTPRIV+18)
49904 +/*
49905 + * arguments:
49906 + *   WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
49907 + * uses: WMI_SET_POWER_PARAMS_CMDID
49908 + */
49909 +
49910 +#define AR6000_IOCTL_WMI_SET_BADAP           (SIOCIWFIRSTPRIV+19)
49911 +/*
49912 + * arguments:
49913 + *   WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
49914 + * uses: WMI_ADD_BAD_AP_CMDID
49915 + */
49916 +
49917 +#define AR6000_IOCTL_WMI_GET_QOS_QUEUE       (SIOCIWFIRSTPRIV+20)
49918 +/*
49919 + * arguments:
49920 + *   ar6000_queuereq queueRequest (see below)
49921 + */
49922 +
49923 +#define AR6000_IOCTL_WMI_CREATE_QOS          (SIOCIWFIRSTPRIV+21)
49924 +/*
49925 + * arguments:
49926 + *   WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
49927 + * uses: WMI_CREATE_PSTREAM_CMDID
49928 + */
49929 +
49930 +#define AR6000_IOCTL_WMI_DELETE_QOS          (SIOCIWFIRSTPRIV+22)
49931 +/*
49932 + * arguments:
49933 + *   WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
49934 + * uses: WMI_DELETE_PSTREAM_CMDID
49935 + */
49936 +
49937 +#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD   (SIOCIWFIRSTPRIV+23)
49938 +/*
49939 + * arguments:
49940 + *   WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
49941 + * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID
49942 + */
49943 +
49944 +#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
49945 +/*
49946 + * arguments:
49947 + *   WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
49948 + * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
49949 + */
49950 +
49951 +#define AR6000_IOCTL_WMI_GET_TARGET_STATS    (SIOCIWFIRSTPRIV+25)
49952 +/*
49953 + * arguments:
49954 + *   TARGET_STATS *targetStats (see below)
49955 + * uses: WMI_GET_STATISTICS_CMDID
49956 + */
49957 +
49958 +#define AR6000_IOCTL_WMI_SET_ASSOC_INFO      (SIOCIWFIRSTPRIV+26)
49959 +/*
49960 + * arguments:
49961 + *   WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
49962 + * uses: WMI_SET_ASSOC_INFO_CMDID
49963 + */
49964 +
49965 +#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS   (SIOCIWFIRSTPRIV+27)
49966 +/*
49967 + * arguments:
49968 + *   WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
49969 + * uses: WMI_SET_ACCESS_PARAMS_CMDID
49970 + */
49971 +
49972 +#define AR6000_IOCTL_WMI_SET_BMISS_TIME      (SIOCIWFIRSTPRIV+28)
49973 +/*
49974 + * arguments:
49975 + *   UINT32 beaconMissTime
49976 + * uses: WMI_SET_BMISS_TIME_CMDID
49977 + */
49978 +
49979 +#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT    (SIOCIWFIRSTPRIV+29)
49980 +/*
49981 + * arguments:
49982 + *   WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
49983 + * uses: WMI_SET_DISC_TIMEOUT_CMDID
49984 + */
49985 +
49986 +#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS    (SIOCIWFIRSTPRIV+30)
49987 +/*
49988 + * arguments:
49989 + *   WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
49990 + * uses: WMI_SET_IBSS_PM_CAPS_CMDID
49991 + */
49992 +
49993 +/*
49994 + * There is a very small space available for driver-private
49995 + * wireless ioctls.  In order to circumvent this limitation,
49996 + * we multiplex a bunch of ioctls (XIOCTLs) on top of a
49997 + * single AR6000_IOCTL_EXTENDED ioctl.
49998 + */
49999 +#define AR6000_IOCTL_EXTENDED                (SIOCIWFIRSTPRIV+31)
50000 +
50001 +
50002 +/*                         ====BMI Extended Ioctls====                        */
50003 +
50004 +#define AR6000_XIOCTL_BMI_DONE                                  1
50005 +/*
50006 + * arguments:
50007 + *   UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
50008 + * uses: BMI_DONE
50009 + */
50010 +
50011 +#define AR6000_XIOCTL_BMI_READ_MEMORY                           2
50012 +/*
50013 + * arguments:
50014 + *   union {
50015 + *     struct {
50016 + *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
50017 + *       UINT32 address
50018 + *       UINT32 length
50019 + *     }
50020 + *     char results[length]
50021 + *   }
50022 + * uses: BMI_READ_MEMORY
50023 + */
50024 +
50025 +#define AR6000_XIOCTL_BMI_WRITE_MEMORY                          3
50026 +/*
50027 + * arguments:
50028 + *   UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
50029 + *   UINT32 address
50030 + *   UINT32 length
50031 + *   char data[length]
50032 + * uses: BMI_WRITE_MEMORY
50033 + */
50034 +
50035 +#define AR6000_XIOCTL_BMI_EXECUTE                               4
50036 +/*
50037 + * arguments:
50038 + *   UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
50039 + *   UINT32 TargetAddress
50040 + *   UINT32 parameter
50041 + * uses: BMI_EXECUTE
50042 + */
50043 +
50044 +#define AR6000_XIOCTL_BMI_SET_APP_START                         5
50045 +/*
50046 + * arguments:
50047 + *   UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
50048 + *   UINT32 TargetAddress
50049 + * uses: BMI_SET_APP_START
50050 + */
50051 +
50052 +#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER                     6
50053 +/*
50054 + * arguments:
50055 + *   union {
50056 + *     struct {
50057 + *       UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
50058 + *       UINT32 TargetAddress, 32-bit aligned
50059 + *     }
50060 + *     UINT32 result
50061 + *   }
50062 + * uses: BMI_READ_SOC_REGISTER
50063 + */
50064 +
50065 +#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER                    7
50066 +/*
50067 + * arguments:
50068 + *     struct {
50069 + *       UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
50070 + *       UINT32 TargetAddress, 32-bit aligned
50071 + *       UINT32 newValue
50072 + *     }
50073 + * uses: BMI_WRITE_SOC_REGISTER
50074 + */
50075 +
50076 +#define AR6000_XIOCTL_BMI_TEST                                  8
50077 +/*
50078 + * arguments:
50079 + *   UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
50080 + *   UINT32 address
50081 + *   UINT32 length
50082 + *   UINT32 count
50083 + */
50084 +
50085 +
50086 +
50087 +/* Historical Host-side DataSet support */
50088 +#define AR6000_XIOCTL_UNUSED9                                   9
50089 +#define AR6000_XIOCTL_UNUSED10                                  10
50090 +#define AR6000_XIOCTL_UNUSED11                                  11
50091 +
50092 +/*                      ====Misc Extended Ioctls====                          */
50093 +
50094 +#define AR6000_XIOCTL_FORCE_TARGET_RESET                        12
50095 +/*
50096 + * arguments:
50097 + *   UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
50098 + */
50099 +
50100 +
50101 +#ifdef HTC_RAW_INTERFACE
50102 +/* HTC Raw Interface Ioctls */
50103 +#define AR6000_XIOCTL_HTC_RAW_OPEN                              13
50104 +/*
50105 + * arguments:
50106 + *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
50107 + */
50108 +
50109 +#define AR6000_XIOCTL_HTC_RAW_CLOSE                             14
50110 +/*
50111 + * arguments:
50112 + *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
50113 + */
50114 +
50115 +#define AR6000_XIOCTL_HTC_RAW_READ                              15
50116 +/*
50117 + * arguments:
50118 + *   union {
50119 + *     struct {
50120 + *       UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
50121 + *       UINT32 mailboxID
50122 + *       UINT32 length
50123 + *     }
50124 + *     results[length]
50125 + *   }
50126 + */
50127 +
50128 +#define AR6000_XIOCTL_HTC_RAW_WRITE                             16
50129 +/*
50130 + * arguments:
50131 + *   UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
50132 + *   UINT32 mailboxID
50133 + *   UINT32 length
50134 + *   char buffer[length]
50135 + */
50136 +#endif /* HTC_RAW_INTERFACE */
50137 +
50138 +#define AR6000_XIOCTL_CHECK_TARGET_READY                        17
50139 +/*
50140 + * arguments:
50141 + *   UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
50142 + */
50143 +
50144 +
50145 +
50146 +/*                ====GPIO (General Purpose I/O) Extended Ioctls====          */
50147 +
50148 +#define AR6000_XIOCTL_GPIO_OUTPUT_SET                           18
50149 +/*
50150 + * arguments:
50151 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
50152 + *   ar6000_gpio_output_set_cmd_s (see below)
50153 + * uses: WMIX_GPIO_OUTPUT_SET_CMDID
50154 + */
50155 +
50156 +#define AR6000_XIOCTL_GPIO_INPUT_GET                            19
50157 +/*
50158 + * arguments:
50159 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
50160 + * uses: WMIX_GPIO_INPUT_GET_CMDID
50161 + */
50162 +
50163 +#define AR6000_XIOCTL_GPIO_REGISTER_SET                         20
50164 +/*
50165 + * arguments:
50166 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
50167 + *   ar6000_gpio_register_cmd_s (see below)
50168 + * uses: WMIX_GPIO_REGISTER_SET_CMDID
50169 + */
50170 +
50171 +#define AR6000_XIOCTL_GPIO_REGISTER_GET                         21
50172 +/*
50173 + * arguments:
50174 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
50175 + *   ar6000_gpio_register_cmd_s (see below)
50176 + * uses: WMIX_GPIO_REGISTER_GET_CMDID
50177 + */
50178 +
50179 +#define AR6000_XIOCTL_GPIO_INTR_ACK                             22
50180 +/*
50181 + * arguments:
50182 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
50183 + *   ar6000_cpio_intr_ack_cmd_s (see below)
50184 + * uses: WMIX_GPIO_INTR_ACK_CMDID
50185 + */
50186 +
50187 +#define AR6000_XIOCTL_GPIO_INTR_WAIT                            23
50188 +/*
50189 + * arguments:
50190 + *   UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
50191 + */
50192 +
50193 +
50194 +
50195 +/*                    ====more wireless commands====                          */
50196 +
50197 +#define AR6000_XIOCTL_SET_ADHOC_BSSID                           24
50198 +/*
50199 + * arguments:
50200 + *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
50201 + *   WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
50202 + */
50203 +
50204 +#define AR6000_XIOCTL_SET_OPT_MODE                              25
50205 +/*
50206 + * arguments:
50207 + *   UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
50208 + *   WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
50209 + * uses: WMI_SET_OPT_MODE_CMDID
50210 + */
50211 +
50212 +#define AR6000_XIOCTL_OPT_SEND_FRAME                            26
50213 +/*
50214 + * arguments:
50215 + *   UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
50216 + *   WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
50217 + * uses: WMI_OPT_TX_FRAME_CMDID
50218 + */
50219 +
50220 +#define AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL                   27
50221 +/*
50222 + * arguments:
50223 + *   UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL)
50224 + *   WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
50225 + * uses: WMI_SET_BEACON_INT_CMDID
50226 + */
50227 +
50228 +
50229 +#define IEEE80211_IOCTL_SETAUTHALG                              28
50230 +
50231 +
50232 +#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE                        29
50233 +/*
50234 + * arguments:
50235 + *   UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
50236 + *   WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
50237 + * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
50238 + */
50239 +
50240 +
50241 +#define AR6000_XIOCTL_SET_MAX_SP                                30
50242 +/*
50243 + * arguments:
50244 + *   UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
50245 + *   WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
50246 + * uses: WMI_SET_MAX_SP_LEN_CMDID
50247 + */
50248 +
50249 +#define AR6000_XIOCTL_WMI_GET_ROAM_TBL                          31
50250 +
50251 +#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL                         32
50252 +
50253 +#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS                 33
50254 +
50255 +
50256 +/*
50257 + * arguments:
50258 + *   UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
50259 + *   WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
50260 + *   WMI_SET_POWERSAVE_TIMERS_CMDID
50261 + */
50262 +
50263 +#define AR6000_XIOCTRL_WMI_GET_POWER_MODE                        34
50264 +/*
50265 + * arguments:
50266 + *   UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
50267 + */
50268 +
50269 +#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE                       35
50270 +typedef enum {
50271 +    WLAN_DISABLED,
50272 +    WLAN_ENABLED
50273 +} AR6000_WLAN_STATE;
50274 +/*
50275 + * arguments:
50276 + * enable/disable
50277 + */
50278 +
50279 +#define AR6000_XIOCTL_WMI_GET_ROAM_DATA                         36
50280 +
50281 +#define AR6000_XIOCTL_WMI_SETRETRYLIMITS                37
50282 +/*
50283 + * arguments:
50284 + *   WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd
50285 + * uses: WMI_SET_RETRY_LIMITS_CMDID
50286 + */
50287 +
50288 +#ifdef CONFIG_HOST_TCMD_SUPPORT
50289 +/*       ====extended commands for radio test ====                          */
50290 +
50291 +#define AR6000_XIOCTL_TCMD_CONT_TX                      38
50292 +/*
50293 + * arguments:
50294 + *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX)
50295 + *   WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h)
50296 + * uses: WMI_TCMD_CONT_TX_CMDID
50297 + */
50298 +
50299 +#define AR6000_XIOCTL_TCMD_CONT_RX                      39
50300 +/*
50301 + * arguments:
50302 + *   UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX)
50303 + *   WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h)
50304 + * uses: WMI_TCMD_CONT_RX_CMDID
50305 + */
50306 +
50307 +#define AR6000_XIOCTL_TCMD_PM                           40
50308 +/*
50309 + * arguments:
50310 + *   UINT32 cmd (AR6000_XIOCTL_TCMD_PM)
50311 + *   WMI_TCMD_PM_CMD pmCmd (see include/wmi.h)
50312 + * uses: WMI_TCMD_PM_CMDID
50313 + */
50314 +
50315 +#endif /* CONFIG_HOST_TCMD_SUPPORT */
50316 +
50317 +#define AR6000_XIOCTL_WMI_STARTSCAN                     41
50318 +/*
50319 + * arguments:
50320 + *   UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN)
50321 + *   UINT8  scanType
50322 + *   UINT8  scanConnected
50323 + *   A_BOOL forceFgScan
50324 + * uses: WMI_START_SCAN_CMDID
50325 + */
50326 +
50327 +#define AR6000_XIOCTL_WMI_SETFIXRATES                   42
50328 +
50329 +#define AR6000_XIOCTL_WMI_GETFIXRATES                   43
50330 +
50331 +
50332 +#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD             44
50333 +/*
50334 + * arguments:
50335 + *   WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
50336 + * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
50337 + */
50338 +
50339 +#define AR6000_XIOCTL_WMI_CLR_RSSISNR                   45
50340 +/*
50341 + * arguments:
50342 + *   WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h)
50343 + * uses: WMI_CLR_RSSISNR_CMDID
50344 + */
50345 +
50346 +#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD               46
50347 +/*
50348 + * arguments:
50349 + *   WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
50350 + * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID
50351 + */
50352 +
50353 +#define AR6000_XIOCTL_WMI_SET_RTS                        47
50354 +/*
50355 + * arguments:
50356 + *   WMI_SET_RTS_MODE_CMD (see include/wmi.h)
50357 + * uses: WMI_SET_RTS_MODE_CMDID
50358 + */
50359 +
50360 +#define AR6000_XIOCTL_WMI_SET_LPREAMBLE                 48
50361 +
50362 +#define AR6000_XIOCTL_WMI_SET_AUTHMODE                  49
50363 +/*
50364 + * arguments:
50365 + *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE)
50366 + *   UINT8  mode
50367 + * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID
50368 + */
50369 +
50370 +#define AR6000_XIOCTL_WMI_SET_REASSOCMODE               50
50371 +
50372 +/*
50373 + * arguments:
50374 + *   UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM)
50375 + *   UINT8  mode
50376 + * uses: WMI_SET_WMM_CMDID
50377 + */
50378 +#define AR6000_XIOCTL_WMI_SET_WMM                       51
50379 +
50380 +/*
50381 + * arguments:
50382 + * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS)
50383 + * UINT32 frequency
50384 + * UINT8  threshold
50385 + */
50386 +#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS  52
50387 +
50388 +/*
50389 + * arguments:
50390 + * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP)
50391 + * UINT32 cookie
50392 + */
50393 +#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP         53
50394 +
50395 +/*
50396 + * arguments:
50397 + *   UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD)
50398 + *   UINT32 regDomain
50399 + */
50400 +#define AR6000_XIOCTL_WMI_GET_RD                        54
50401 +
50402 +#define AR6000_XIOCTL_DIAG_READ                         55
50403 +
50404 +#define AR6000_XIOCTL_DIAG_WRITE                        56
50405 +
50406 +/*
50407 + * arguments cmd (AR6000_XIOCTL_SET_TXOP)
50408 + * WMI_TXOP_CFG  txopEnable
50409 + */
50410 +#define AR6000_XIOCTL_WMI_SET_TXOP                      57
50411 +
50412 +#ifdef USER_KEYS
50413 +/*
50414 + * arguments:
50415 + * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS)
50416 + * UINT32 keyOpCtrl
50417 + * uses AR6000_USER_SETKEYS_INFO
50418 + */
50419 +#define AR6000_XIOCTL_USER_SETKEYS                      58
50420 +#endif /* USER_KEYS */
50421 +
50422 +#define AR6000_XIOCTL_WMI_SET_KEEPALIVE                 59
50423 +/*
50424 + * arguments:
50425 + *   UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE)
50426 + *   UINT8 keepaliveInterval
50427 + * uses: WMI_SET_KEEPALIVE_CMDID
50428 + */
50429 +
50430 +#define AR6000_XIOCTL_WMI_GET_KEEPALIVE                 60
50431 +/*
50432 + * arguments:
50433 + *   UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE)
50434 + *   UINT8 keepaliveInterval
50435 + *   A_BOOL configured
50436 + * uses: WMI_GET_KEEPALIVE_CMDID
50437 + */
50438 +
50439 +/*               ====ROM Patching Extended Ioctls====                       */
50440 +
50441 +#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL              61
50442 +/*
50443 + * arguments:
50444 + *     union {
50445 + *       struct {
50446 + *         UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL)
50447 + *         UINT32 ROM Address
50448 + *         UINT32 RAM Address
50449 + *         UINT32 number of bytes
50450 + *         UINT32 activate? (0 or 1)
50451 + *       }
50452 + *       A_UINT32 resulting rompatch ID
50453 + *     }
50454 + * uses: BMI_ROMPATCH_INSTALL
50455 + */
50456 +
50457 +#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL            62
50458 +/*
50459 + * arguments:
50460 + *     struct {
50461 + *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL)
50462 + *       UINT32 rompatch ID
50463 + *     }
50464 + * uses: BMI_ROMPATCH_UNINSTALL
50465 + */
50466 +
50467 +#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE             63
50468 +/*
50469 + * arguments:
50470 + *     struct {
50471 + *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE)
50472 + *       UINT32 rompatch count
50473 + *       UINT32 rompatch IDs[rompatch count]
50474 + *     }
50475 + * uses: BMI_ROMPATCH_ACTIVATE
50476 + */
50477 +
50478 +#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE           64
50479 +/*
50480 + * arguments:
50481 + *     struct {
50482 + *       UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE)
50483 + *       UINT32 rompatch count
50484 + *       UINT32 rompatch IDs[rompatch count]
50485 + *     }
50486 + * uses: BMI_ROMPATCH_DEACTIVATE
50487 + */
50488 +
50489 +#define AR6000_XIOCTL_WMI_SET_APPIE             65
50490 +/*
50491 + * arguments:
50492 + *      struct {
50493 + *          UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE)
50494 + *          UINT32  app_frmtype;
50495 + *          UINT32  app_buflen;
50496 + *          UINT8   app_buf[];
50497 + *      }
50498 + */
50499 +#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER    66
50500 +/*
50501 + * arguments:
50502 + *      A_UINT32 filter_type;
50503 + */
50504 +
50505 +#define AR6000_XIOCTL_DBGLOG_CFG_MODULE             67
50506 +
50507 +#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS         68
50508 +
50509 +#define AR6000_XIOCTL_WMI_SET_WSC_STATUS               70
50510 +/*
50511 + * arguments:
50512 + *      A_UINT32 wsc_status;
50513 + *            (WSC_REG_INACTIVE or WSC_REG_ACTIVE)
50514 + */
50515 +
50516 +/*
50517 + * arguments:
50518 + *      struct {
50519 + *          A_UINT8 streamType;
50520 + *          A_UINT8 status;
50521 + *      }
50522 + * uses: WMI_SET_BT_STATUS_CMDID
50523 + */
50524 +#define AR6000_XIOCTL_WMI_SET_BT_STATUS             71
50525 +
50526 +/*
50527 + * arguments:
50528 + *      struct {
50529 + *           A_UINT8 paramType;
50530 + *           union {
50531 + *               A_UINT8 noSCOPkts;
50532 + *               BT_PARAMS_A2DP a2dpParams;
50533 + *               BT_COEX_REGS regs;
50534 + *           };
50535 + *      }
50536 + * uses: WMI_SET_BT_PARAM_CMDID
50537 + */
50538 +#define AR6000_XIOCTL_WMI_SET_BT_PARAMS             72
50539 +
50540 +#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE       73
50541 +#define AR6000_XIOCTL_WMI_SET_WOW_MODE              74
50542 +#define AR6000_XIOCTL_WMI_GET_WOW_LIST              75
50543 +#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN           76
50544 +#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN           77
50545 +
50546 +
50547 +
50548 +#define AR6000_XIOCTL_TARGET_INFO                   78
50549 +/*
50550 + * arguments:
50551 + *   UINT32 cmd (AR6000_XIOCTL_TARGET_INFO)
50552 + *   A_UINT32 TargetVersion (returned)
50553 + *   A_UINT32 TargetType    (returned)
50554 + * (See also bmi_msg.h target_ver and target_type)
50555 + */
50556 +
50557 +#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE         79
50558 +/*
50559 + * arguments:
50560 + *      none
50561 + */
50562 +
50563 +#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE       80
50564 +/*
50565 + * This ioctl is used to emulate traffic activity
50566 + * timeouts.  Activity/inactivity will trigger the driver
50567 + * to re-balance credits.
50568 + *
50569 + * arguments:
50570 + *      ar6000_traffic_activity_change
50571 + */
50572 +
50573 +#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS    81
50574 +/*
50575 + * This ioctl is used to set the connect control flags
50576 + *
50577 + * arguments:
50578 + *      A_UINT32 connectCtrlFlags
50579 + */
50580 +
50581 +#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS              82
50582 +/*
50583 + * This IOCTL sets any Authentication,Key Management and Protection
50584 + * related parameters. This is used along with the information set in
50585 + * Connect Command.
50586 + * Currently this enables Multiple PMKIDs to an AP.
50587 + *
50588 + * arguments:
50589 + *      struct {
50590 + *          A_UINT32    akmpInfo;
50591 + *      }
50592 + * uses: WMI_SET_AKMP_PARAMS_CMD
50593 + */
50594 +
50595 +#define AR6000_XIOCTL_WMI_GET_PMKID_LIST            83
50596 +
50597 +#define AR6000_XIOCTL_WMI_SET_PMKID_LIST            84
50598 +/*
50599 + * This IOCTL is used to set a list of PMKIDs. This list of
50600 + * PMKIDs is used in the [Re]AssocReq Frame. This list is used
50601 + * only if the MultiPMKID option is enabled via the
50602 + * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS  IOCTL.
50603 + *
50604 + * arguments:
50605 + *      struct {
50606 + *          A_UINT32    numPMKID;
50607 + *          WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
50608 + *      }
50609 + * uses: WMI_SET_PMKIDLIST_CMD
50610 + */
50611 +
50612 +/* Historical DSETPATCH support for INI patches */
50613 +#define AR6000_XIOCTL_UNUSED90                      90
50614 +
50615 +
50616 +
50617 +/* used by AR6000_IOCTL_WMI_GETREV */
50618 +struct ar6000_version {
50619 +    A_UINT32        host_ver;
50620 +    A_UINT32        target_ver;
50621 +};
50622 +
50623 +/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
50624 +struct ar6000_queuereq {
50625 +    A_UINT8         trafficClass;
50626 +    A_UINT16        activeTsids;
50627 +};
50628 +
50629 +/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
50630 +typedef struct targetStats_t {
50631 +    A_UINT64    tx_packets;
50632 +    A_UINT64    tx_bytes;
50633 +    A_UINT64    tx_unicast_pkts;
50634 +    A_UINT64    tx_unicast_bytes;
50635 +    A_UINT64    tx_multicast_pkts;
50636 +    A_UINT64    tx_multicast_bytes;
50637 +    A_UINT64    tx_broadcast_pkts;
50638 +    A_UINT64    tx_broadcast_bytes;
50639 +    A_UINT64    tx_rts_success_cnt;
50640 +    A_UINT64    tx_packet_per_ac[4];
50641 +
50642 +    A_UINT64    tx_errors;
50643 +    A_UINT64    tx_failed_cnt;
50644 +    A_UINT64    tx_retry_cnt;
50645 +    A_UINT64    tx_rts_fail_cnt;
50646 +    A_INT32     tx_unicast_rate;
50647 +    A_UINT64    rx_packets;
50648 +    A_UINT64    rx_bytes;
50649 +    A_UINT64    rx_unicast_pkts;
50650 +    A_UINT64    rx_unicast_bytes;
50651 +    A_UINT64    rx_multicast_pkts;
50652 +    A_UINT64    rx_multicast_bytes;
50653 +    A_UINT64    rx_broadcast_pkts;
50654 +    A_UINT64    rx_broadcast_bytes;
50655 +    A_UINT64    rx_fragment_pkt;
50656 +
50657 +    A_UINT64    rx_errors;
50658 +    A_UINT64    rx_crcerr;
50659 +    A_UINT64    rx_key_cache_miss;
50660 +    A_UINT64    rx_decrypt_err;
50661 +    A_UINT64    rx_duplicate_frames;
50662 +    A_INT32     rx_unicast_rate;
50663 +
50664 +    A_UINT64    tkip_local_mic_failure;
50665 +    A_UINT64    tkip_counter_measures_invoked;
50666 +    A_UINT64    tkip_replays;
50667 +    A_UINT64    tkip_format_errors;
50668 +    A_UINT64    ccmp_format_errors;
50669 +    A_UINT64    ccmp_replays;
50670 +
50671 +    A_UINT64    power_save_failure_cnt;
50672 +    A_INT16     noise_floor_calibation;
50673 +
50674 +    A_UINT64    cs_bmiss_cnt;
50675 +    A_UINT64    cs_lowRssi_cnt;
50676 +    A_UINT64    cs_connect_cnt;
50677 +    A_UINT64    cs_disconnect_cnt;
50678 +    A_UINT8     cs_aveBeacon_snr;
50679 +    A_INT16     cs_aveBeacon_rssi;
50680 +    A_UINT8     cs_lastRoam_msec;
50681 +    A_UINT8     cs_snr;
50682 +    A_INT16     cs_rssi;
50683 +
50684 +    A_UINT32    lq_val;
50685 +
50686 +    A_UINT32    wow_num_pkts_dropped;
50687 +    A_UINT8     wow_num_host_pkt_wakeups;
50688 +    A_UINT8     wow_num_host_event_wakeups;
50689 +    A_UINT16    wow_num_events_discarded;
50690 +
50691 +}TARGET_STATS;
50692 +
50693 +typedef struct targetStats_cmd_t {
50694 +    TARGET_STATS targetStats;
50695 +    int clearStats;
50696 +} TARGET_STATS_CMD;
50697 +
50698 +/* used by AR6000_XIOCTL_USER_SETKEYS */
50699 +
50700 +/*
50701 + * Setting this bit to 1 doesnot initialize the RSC on the firmware
50702 + */
50703 +#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL    1
50704 +#define AR6000_USER_SETKEYS_RSC_UNCHANGED     0x00000002
50705 +
50706 +typedef struct {
50707 +    A_UINT32  keyOpCtrl;  /* Bit Map of Key Mgmt Ctrl Flags */
50708 +} AR6000_USER_SETKEYS_INFO;
50709 +
50710 +
50711 +/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
50712 +struct ar6000_gpio_output_set_cmd_s {
50713 +    A_UINT32 set_mask;
50714 +    A_UINT32 clear_mask;
50715 +    A_UINT32 enable_mask;
50716 +    A_UINT32 disable_mask;
50717 +};
50718 +
50719 +/*
50720 + * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
50721 + */
50722 +struct ar6000_gpio_register_cmd_s {
50723 +    A_UINT32 gpioreg_id;
50724 +    A_UINT32 value;
50725 +};
50726 +
50727 +/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
50728 +struct ar6000_gpio_intr_ack_cmd_s {
50729 +    A_UINT32 ack_mask;
50730 +};
50731 +
50732 +/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
50733 +struct ar6000_gpio_intr_wait_cmd_s {
50734 +    A_UINT32 intr_mask;
50735 +    A_UINT32 input_values;
50736 +};
50737 +
50738 +/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */
50739 +typedef struct ar6000_dbglog_module_config_s {
50740 +    A_UINT32 valid;
50741 +    A_UINT16 mmask;
50742 +    A_UINT16 tsr;
50743 +    A_BOOL   rep;
50744 +    A_UINT16 size;
50745 +} DBGLOG_MODULE_CONFIG;
50746 +
50747 +typedef struct user_rssi_thold_t {
50748 +    A_INT16     tag;
50749 +    A_INT16     rssi;
50750 +} USER_RSSI_THOLD;
50751 +
50752 +typedef struct user_rssi_params_t {
50753 +    A_UINT8            weight;
50754 +    A_UINT32           pollTime;
50755 +    USER_RSSI_THOLD    tholds[12];
50756 +} USER_RSSI_PARAMS;
50757 +
50758 +/*
50759 + * Host driver may have some config parameters. Typically, these
50760 + * config params are one time config parameters. These could
50761 + * correspond to any of the underlying modules. Host driver exposes
50762 + * an api for the underlying modules to get this config.
50763 + */
50764 +#define AR6000_DRIVER_CFG_BASE                  0x8000
50765 +
50766 +/* Should driver perform wlan node caching? */
50767 +#define AR6000_DRIVER_CFG_GET_WLANNODECACHING   0x8001
50768 +/*Should we log raw WMI msgs */
50769 +#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS      0x8002
50770 +
50771 +/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */
50772 +struct ar6000_diag_window_cmd_s {
50773 +    unsigned int addr;
50774 +    unsigned int value;
50775 +};
50776 +
50777 +
50778 +struct ar6000_traffic_activity_change {
50779 +    A_UINT32    StreamID;   /* stream ID to indicate activity change */
50780 +    A_UINT32    Active;     /* active (1) or inactive (0) */
50781 +};
50782 +
50783 +#ifdef __cplusplus
50784 +}
50785 +#endif
50786 +#endif
50787 Index: linux-2.6.28/drivers/ar6000/ar6000/athtypes_linux.h
50788 ===================================================================
50789 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
50790 +++ linux-2.6.28/drivers/ar6000/ar6000/athtypes_linux.h 2009-01-02 00:01:56.000000000 +0100
50791 @@ -0,0 +1,47 @@
50792 +/*
50793 + * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/athtypes_linux.h#1 $
50794 + *
50795 + * This file contains the definitions of the basic atheros data types.
50796 + * It is used to map the data types in atheros files to a platform specific
50797 + * type.
50798 + *
50799 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
50800 + *
50801 + *
50802 + *  This program is free software; you can redistribute it and/or modify
50803 + *  it under the terms of the GNU General Public License version 2 as
50804 + *  published by the Free Software Foundation;
50805 + *
50806 + *  Software distributed under the License is distributed on an "AS
50807 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50808 + *  implied. See the License for the specific language governing
50809 + *  rights and limitations under the License.
50810 + *
50811 + *
50812 + *
50813 + */
50814 +
50815 +#ifndef _ATHTYPES_LINUX_H_
50816 +#define _ATHTYPES_LINUX_H_
50817 +
50818 +#ifdef __KERNEL__
50819 +#include <linux/types.h>
50820 +#endif
50821 +
50822 +typedef int8_t      A_INT8;
50823 +typedef int16_t     A_INT16;
50824 +typedef int32_t     A_INT32;
50825 +typedef int64_t     A_INT64;
50826 +
50827 +typedef u_int8_t     A_UINT8;
50828 +typedef u_int16_t    A_UINT16;
50829 +typedef u_int32_t    A_UINT32;
50830 +typedef u_int64_t    A_UINT64;
50831 +
50832 +typedef int             A_BOOL;
50833 +typedef char            A_CHAR;
50834 +typedef unsigned char   A_UCHAR;
50835 +typedef unsigned long   A_ATH_TIMER;
50836 +
50837 +
50838 +#endif /* _ATHTYPES_LINUX_H_ */
50839 Index: linux-2.6.28/drivers/ar6000/ar6000/config_linux.h
50840 ===================================================================
50841 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
50842 +++ linux-2.6.28/drivers/ar6000/ar6000/config_linux.h   2009-01-02 00:01:56.000000000 +0100
50843 @@ -0,0 +1,44 @@
50844 +/*
50845 + * Copyright (c) 2004-2007 Atheros Communications Inc.
50846 + * All rights reserved.
50847 + *
50848 + *
50849 + *  This program is free software; you can redistribute it and/or modify
50850 + *  it under the terms of the GNU General Public License version 2 as
50851 + *  published by the Free Software Foundation;
50852 + *
50853 + *  Software distributed under the License is distributed on an "AS
50854 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50855 + *  implied. See the License for the specific language governing
50856 + *  rights and limitations under the License.
50857 + *
50858 + *
50859 + *
50860 + */
50861 +
50862 +#ifndef _CONFIG_LINUX_H_
50863 +#define _CONFIG_LINUX_H_
50864 +
50865 +#ifdef __cplusplus
50866 +extern "C" {
50867 +#endif
50868 +
50869 +/*
50870 + * Host-side GPIO support is optional.
50871 + * If run-time access to GPIO pins is not required, then
50872 + * this should be changed to #undef.
50873 + */
50874 +#define CONFIG_HOST_GPIO_SUPPORT
50875 +
50876 +/*
50877 + * Host side Test Command support
50878 + */
50879 +#define CONFIG_HOST_TCMD_SUPPORT
50880 +
50881 +#define USE_4BYTE_REGISTER_ACCESS
50882 +
50883 +#ifdef __cplusplus
50884 +}
50885 +#endif
50886 +
50887 +#endif
50888 Index: linux-2.6.28/drivers/ar6000/ar6000/debug_linux.h
50889 ===================================================================
50890 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
50891 +++ linux-2.6.28/drivers/ar6000/ar6000/debug_linux.h    2009-01-02 00:01:56.000000000 +0100
50892 @@ -0,0 +1,86 @@
50893 +/*
50894 + * Copyright (c) 2004-2006 Atheros Communications Inc.
50895 + * All rights reserved.
50896 + *
50897 + *
50898 + *  This program is free software; you can redistribute it and/or modify
50899 + *  it under the terms of the GNU General Public License version 2 as
50900 + *  published by the Free Software Foundation;
50901 + *
50902 + *  Software distributed under the License is distributed on an "AS
50903 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50904 + *  implied. See the License for the specific language governing
50905 + *  rights and limitations under the License.
50906 + *
50907 + *
50908 + *
50909 + */
50910 +
50911 +#ifndef _DEBUG_LINUX_H_
50912 +#define _DEBUG_LINUX_H_
50913 +
50914 +#define DBG_DEFAULTS   (DBG_ERROR|DBG_WARNING)
50915 +
50916 +extern A_UINT32 g_dbg_flags;
50917 +
50918 +#define DBGFMT  "%s() : "
50919 +#define DBGARG  __func__
50920 +#define DBGFN  A_PRINTF
50921 +
50922 +/* ------- Debug related stuff ------- */
50923 +enum {
50924 +    ATH_DEBUG_SEND = 0x0001,
50925 +    ATH_DEBUG_RECV = 0x0002,
50926 +    ATH_DEBUG_SYNC = 0x0004,
50927 +    ATH_DEBUG_DUMP = 0x0008,
50928 +    ATH_DEBUG_IRQ  = 0x0010,
50929 +    ATH_DEBUG_TRC  = 0x0020,
50930 +    ATH_DEBUG_WARN = 0x0040,
50931 +    ATH_DEBUG_ERR  = 0x0080,
50932 +    ATH_LOG_INF           = 0x0100,
50933 +    ATH_DEBUG_BMI  = 0x0110,
50934 +    ATH_DEBUG_WMI  = 0x0120,
50935 +    ATH_DEBUG_HIF  = 0x0140,
50936 +    ATH_DEBUG_HTC  = 0x0180,
50937 +    ATH_DEBUG_WLAN = 0x1000,
50938 +    ATH_LOG_ERR           = 0x1010,
50939 +    ATH_DEBUG_ANY  = 0xFFFF,
50940 +};
50941 +
50942 +#ifdef DEBUG
50943 +
50944 +#define A_DPRINTF(f, a) \
50945 +       if(g_dbg_flags & (f)) \
50946 +       {       \
50947 +               DBGFN a ; \
50948 +       }
50949 +
50950 +
50951 +// TODO FIX usage of A_PRINTF!
50952 +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl))
50953 +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do {   \
50954 +    if (debughtc & ATH_DEBUG_DUMP) {             \
50955 +        DebugDumpBytes(buffer, length,desc);               \
50956 +    }                                            \
50957 +} while(0)
50958 +#define PRINTX_ARG(arg...) arg
50959 +#define AR_DEBUG_PRINTF(flags, args) do {        \
50960 +    if (debughtc & (flags)) {                    \
50961 +        A_PRINTF(KERN_ALERT PRINTX_ARG args);    \
50962 +    }                                            \
50963 +} while (0)
50964 +#define AR_DEBUG_ASSERT(test) do {               \
50965 +    if (!(test)) {                               \
50966 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test));         \
50967 +    }                                            \
50968 +} while(0)
50969 +extern int debughtc;
50970 +#else
50971 +#define AR_DEBUG_PRINTF(flags, args)
50972 +#define AR_DEBUG_PRINTBUF(buffer, length, desc)
50973 +#define AR_DEBUG_ASSERT(test)
50974 +#define AR_DEBUG_LVL_CHECK(lvl) 0
50975 +#define A_DPRINTF(f, a)
50976 +#endif
50977 +
50978 +#endif /* _DEBUG_LINUX_H_ */
50979 Index: linux-2.6.28/drivers/ar6000/ar6000/ioctl.c
50980 ===================================================================
50981 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
50982 +++ linux-2.6.28/drivers/ar6000/ar6000/ioctl.c  2009-01-02 00:01:56.000000000 +0100
50983 @@ -0,0 +1,2540 @@
50984 +/*
50985 + *
50986 + * Copyright (c) 2004-2007 Atheros Communications Inc.
50987 + * All rights reserved.
50988 + *
50989 + *
50990 + *  This program is free software; you can redistribute it and/or modify
50991 + *  it under the terms of the GNU General Public License version 2 as
50992 + *  published by the Free Software Foundation;
50993 + *
50994 + *  Software distributed under the License is distributed on an "AS
50995 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
50996 + *  implied. See the License for the specific language governing
50997 + *  rights and limitations under the License.
50998 + *
50999 + *
51000 + *
51001 + */
51002 +
51003 +#include "ar6000_drv.h"
51004 +
51005 +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
51006 +static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
51007 +extern USER_RSSI_THOLD rssi_map[12];
51008 +extern unsigned int wmitimeout;
51009 +extern A_WAITQUEUE_HEAD arEvent;
51010 +extern int tspecCompliance;
51011 +extern int bmienable;
51012 +extern int bypasswmi;
51013 +
51014 +static int
51015 +ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
51016 +{
51017 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51018 +
51019 +    if (ar->arWmiReady == FALSE) {
51020 +        return -EIO;
51021 +    }
51022 +
51023 +    if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
51024 +        return -EIO;
51025 +    }
51026 +
51027 +    return 0;
51028 +}
51029 +
51030 +static int
51031 +ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
51032 +{
51033 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51034 +
51035 +    if (ar->arWmiReady == FALSE) {
51036 +        return -EIO;
51037 +    }
51038 +
51039 +
51040 +    /* currently assume only roam times are required */
51041 +    if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
51042 +        return -EIO;
51043 +    }
51044 +
51045 +
51046 +    return 0;
51047 +}
51048 +
51049 +static int
51050 +ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
51051 +{
51052 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51053 +    WMI_SET_ROAM_CTRL_CMD cmd;
51054 +    A_UINT8 size = sizeof(cmd);
51055 +
51056 +    if (ar->arWmiReady == FALSE) {
51057 +        return -EIO;
51058 +    }
51059 +
51060 +
51061 +    if (copy_from_user(&cmd, userdata, size)) {
51062 +        return -EFAULT;
51063 +    }
51064 +
51065 +    if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
51066 +        if (cmd.info.bssBiasInfo.numBss > 1) {
51067 +            size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
51068 +        }
51069 +    }
51070 +
51071 +    if (copy_from_user(&cmd, userdata, size)) {
51072 +        return -EFAULT;
51073 +    }
51074 +
51075 +    if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
51076 +        return -EIO;
51077 +    }
51078 +
51079 +    return 0;
51080 +}
51081 +
51082 +static int
51083 +ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
51084 +{
51085 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51086 +    WMI_POWERSAVE_TIMERS_POLICY_CMD cmd;
51087 +    A_UINT8 size = sizeof(cmd);
51088 +
51089 +    if (ar->arWmiReady == FALSE) {
51090 +        return -EIO;
51091 +    }
51092 +
51093 +    if (copy_from_user(&cmd, userdata, size)) {
51094 +        return -EFAULT;
51095 +    }
51096 +
51097 +    if (copy_from_user(&cmd, userdata, size)) {
51098 +        return -EFAULT;
51099 +    }
51100 +
51101 +    if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
51102 +        return -EIO;
51103 +    }
51104 +
51105 +    return 0;
51106 +}
51107 +
51108 +static int
51109 +ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq)
51110 +{
51111 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51112 +    WMI_SET_WMM_CMD cmd;
51113 +    A_STATUS ret;
51114 +
51115 +    if ((dev->flags & IFF_UP) != IFF_UP) {
51116 +        return -EIO;
51117 +    }
51118 +    if (ar->arWmiReady == FALSE) {
51119 +        return -EIO;
51120 +    }
51121 +
51122 +    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
51123 +                                sizeof(cmd)))
51124 +    {
51125 +        return -EFAULT;
51126 +    }
51127 +
51128 +    if (cmd.status == WMI_WMM_ENABLED) {
51129 +        ar->arWmmEnabled = TRUE;
51130 +    } else {
51131 +        ar->arWmmEnabled = FALSE;
51132 +    }
51133 +
51134 +    ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status);
51135 +
51136 +    switch (ret) {
51137 +        case A_OK:
51138 +            return 0;
51139 +        case A_EBUSY :
51140 +            return -EBUSY;
51141 +        case A_NO_MEMORY:
51142 +            return -ENOMEM;
51143 +        case A_EINVAL:
51144 +        default:
51145 +            return -EFAULT;
51146 +    }
51147 +}
51148 +
51149 +static int
51150 +ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq)
51151 +{
51152 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51153 +    WMI_SET_WMM_TXOP_CMD cmd;
51154 +    A_STATUS ret;
51155 +
51156 +    if ((dev->flags & IFF_UP) != IFF_UP) {
51157 +        return -EIO;
51158 +    }
51159 +    if (ar->arWmiReady == FALSE) {
51160 +        return -EIO;
51161 +    }
51162 +
51163 +    if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
51164 +                                sizeof(cmd)))
51165 +    {
51166 +        return -EFAULT;
51167 +    }
51168 +
51169 +    ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable);
51170 +
51171 +    switch (ret) {
51172 +        case A_OK:
51173 +            return 0;
51174 +        case A_EBUSY :
51175 +            return -EBUSY;
51176 +        case A_NO_MEMORY:
51177 +            return -ENOMEM;
51178 +        case A_EINVAL:
51179 +        default:
51180 +            return -EFAULT;
51181 +    }
51182 +}
51183 +
51184 +static int
51185 +ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq)
51186 +{
51187 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51188 +    A_STATUS ret = 0;
51189 +
51190 +    if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) {
51191 +        return -EIO;
51192 +    }
51193 +
51194 +    if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1),
51195 +                            &ar->arRegCode, sizeof(ar->arRegCode)))
51196 +        ret = -EFAULT;
51197 +
51198 +    return ret;
51199 +}
51200 +
51201 +
51202 +/* Get power mode command */
51203 +static int
51204 +ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
51205 +{
51206 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51207 +    WMI_POWER_MODE_CMD power_mode;
51208 +    int ret = 0;
51209 +
51210 +    if (ar->arWmiReady == FALSE) {
51211 +        return -EIO;
51212 +    }
51213 +
51214 +    power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
51215 +    if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
51216 +        ret = -EFAULT;
51217 +    }
51218 +
51219 +    return ret;
51220 +}
51221 +
51222 +
51223 +static int
51224 +ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
51225 +{
51226 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51227 +    WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
51228 +    int ret = 0;
51229 +
51230 +    if (ar->arWmiReady == FALSE) {
51231 +        return -EIO;
51232 +    }
51233 +
51234 +
51235 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51236 +        return -EFAULT;
51237 +    }
51238 +
51239 +    if (cmd.numChannels > 1) {
51240 +        cmdp = A_MALLOC(130);
51241 +        if (copy_from_user(cmdp, rq->ifr_data,
51242 +                           sizeof (*cmdp) +
51243 +                           ((cmd.numChannels - 1) * sizeof(A_UINT16))))
51244 +        {
51245 +            kfree(cmdp);
51246 +            return -EFAULT;
51247 +        }
51248 +    } else {
51249 +        cmdp = &cmd;
51250 +    }
51251 +
51252 +    if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
51253 +        ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
51254 +    {
51255 +        ret = -EINVAL;
51256 +    }
51257 +
51258 +    if (!ret &&
51259 +        (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode,
51260 +                                   cmdp->numChannels, cmdp->channelList)
51261 +         != A_OK))
51262 +    {
51263 +        ret = -EIO;
51264 +    }
51265 +
51266 +    if (cmd.numChannels > 1) {
51267 +        kfree(cmdp);
51268 +    }
51269 +
51270 +    return ret;
51271 +}
51272 +
51273 +static int
51274 +ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq)
51275 +{
51276 +
51277 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51278 +    WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
51279 +    int ret = 0;
51280 +
51281 +    if (ar->arWmiReady == FALSE) {
51282 +        return -EIO;
51283 +    }
51284 +
51285 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51286 +        return -EFAULT;
51287 +    }
51288 +
51289 +    if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) {
51290 +        ret = -EIO;
51291 +    }
51292 +
51293 +    return ret;
51294 +}
51295 +
51296 +static int
51297 +ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq)
51298 +{
51299 +#define SWAP_THOLD(thold1, thold2) do { \
51300 +    USER_RSSI_THOLD tmpThold;           \
51301 +    tmpThold.tag = thold1.tag;          \
51302 +    tmpThold.rssi = thold1.rssi;        \
51303 +    thold1.tag = thold2.tag;            \
51304 +    thold1.rssi = thold2.rssi;          \
51305 +    thold2.tag = tmpThold.tag;          \
51306 +    thold2.rssi = tmpThold.rssi;        \
51307 +} while (0)
51308 +
51309 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51310 +    WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
51311 +    USER_RSSI_PARAMS rssiParams;
51312 +    A_INT32 i, j;
51313 +
51314 +    int ret = 0;
51315 +
51316 +    if (ar->arWmiReady == FALSE) {
51317 +        return -EIO;
51318 +    }
51319 +
51320 +    if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) {
51321 +        return -EFAULT;
51322 +    }
51323 +    cmd.weight = rssiParams.weight;
51324 +    cmd.pollTime = rssiParams.pollTime;
51325 +
51326 +    A_MEMCPY(rssi_map, &rssiParams.tholds, sizeof(rssi_map));
51327 +    /*
51328 +     *  only 6 elements, so use bubble sorting, in ascending order
51329 +     */
51330 +    for (i = 5; i > 0; i--) {
51331 +        for (j = 0; j < i; j++) { /* above tholds */
51332 +            if (rssi_map[j+1].rssi < rssi_map[j].rssi) {
51333 +                SWAP_THOLD(rssi_map[j+1], rssi_map[j]);
51334 +            } else if (rssi_map[j+1].rssi == rssi_map[j].rssi) {
51335 +                return EFAULT;
51336 +            }
51337 +        }
51338 +    }
51339 +    for (i = 11; i > 6; i--) {
51340 +        for (j = 6; j < i; j++) { /* below tholds */
51341 +            if (rssi_map[j+1].rssi < rssi_map[j].rssi) {
51342 +                SWAP_THOLD(rssi_map[j+1], rssi_map[j]);
51343 +            } else if (rssi_map[j+1].rssi == rssi_map[j].rssi) {
51344 +                return EFAULT;
51345 +            }
51346 +        }
51347 +    }
51348 +
51349 +#ifdef DEBUG
51350 +    for (i = 0; i < 12; i++) {
51351 +        AR_DEBUG2_PRINTF("thold[%d].tag: %d, thold[%d].rssi: %d \n",
51352 +                i, rssi_map[i].tag, i, rssi_map[i].rssi);
51353 +    }
51354 +#endif
51355 +    cmd.thresholdAbove1_Val = rssi_map[0].rssi;
51356 +    cmd.thresholdAbove2_Val = rssi_map[1].rssi;
51357 +    cmd.thresholdAbove3_Val = rssi_map[2].rssi;
51358 +    cmd.thresholdAbove4_Val = rssi_map[3].rssi;
51359 +    cmd.thresholdAbove5_Val = rssi_map[4].rssi;
51360 +    cmd.thresholdAbove6_Val = rssi_map[5].rssi;
51361 +    cmd.thresholdBelow1_Val = rssi_map[6].rssi;
51362 +    cmd.thresholdBelow2_Val = rssi_map[7].rssi;
51363 +    cmd.thresholdBelow3_Val = rssi_map[8].rssi;
51364 +    cmd.thresholdBelow4_Val = rssi_map[9].rssi;
51365 +    cmd.thresholdBelow5_Val = rssi_map[10].rssi;
51366 +    cmd.thresholdBelow6_Val = rssi_map[11].rssi;
51367 +
51368 +    if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) {
51369 +        ret = -EIO;
51370 +    }
51371 +
51372 +    return ret;
51373 +}
51374 +
51375 +static int
51376 +ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq)
51377 +{
51378 +
51379 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51380 +    WMI_LQ_THRESHOLD_PARAMS_CMD cmd;
51381 +    int ret = 0;
51382 +
51383 +    if (ar->arWmiReady == FALSE) {
51384 +        return -EIO;
51385 +    }
51386 +
51387 +    if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) {
51388 +        return -EFAULT;
51389 +    }
51390 +
51391 +    if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) {
51392 +        ret = -EIO;
51393 +    }
51394 +
51395 +    return ret;
51396 +}
51397 +
51398 +
51399 +static int
51400 +ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
51401 +{
51402 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51403 +    WMI_PROBED_SSID_CMD cmd;
51404 +    int ret = 0;
51405 +
51406 +    if (ar->arWmiReady == FALSE) {
51407 +        return -EIO;
51408 +    }
51409 +
51410 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51411 +        return -EFAULT;
51412 +    }
51413 +
51414 +    if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
51415 +                                  cmd.ssid) != A_OK)
51416 +    {
51417 +        ret = -EIO;
51418 +    }
51419 +
51420 +    return ret;
51421 +}
51422 +
51423 +static int
51424 +ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
51425 +{
51426 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51427 +    WMI_ADD_BAD_AP_CMD cmd;
51428 +    int ret = 0;
51429 +
51430 +    if (ar->arWmiReady == FALSE) {
51431 +        return -EIO;
51432 +    }
51433 +
51434 +
51435 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51436 +        return -EFAULT;
51437 +    }
51438 +
51439 +    if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
51440 +        return -EIO;
51441 +    }
51442 +
51443 +    if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
51444 +        /*
51445 +         * This is a delete badAP.
51446 +         */
51447 +        if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
51448 +            ret = -EIO;
51449 +        }
51450 +    } else {
51451 +        if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
51452 +            ret = -EIO;
51453 +        }
51454 +    }
51455 +
51456 +    return ret;
51457 +}
51458 +
51459 +static int
51460 +ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
51461 +{
51462 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51463 +    WMI_CREATE_PSTREAM_CMD cmd;
51464 +    A_STATUS ret;
51465 +
51466 +    if (ar->arWmiReady == FALSE) {
51467 +        return -EIO;
51468 +    }
51469 +
51470 +
51471 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51472 +        return -EFAULT;
51473 +    }
51474 +
51475 +    ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
51476 +    if (ret == A_OK)
51477 +        ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
51478 +
51479 +    switch (ret) {
51480 +        case A_OK:
51481 +            return 0;
51482 +        case A_EBUSY :
51483 +            return -EBUSY;
51484 +        case A_NO_MEMORY:
51485 +            return -ENOMEM;
51486 +        case A_EINVAL:
51487 +        default:
51488 +            return -EFAULT;
51489 +    }
51490 +}
51491 +
51492 +static int
51493 +ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
51494 +{
51495 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51496 +    WMI_DELETE_PSTREAM_CMD cmd;
51497 +    int ret = 0;
51498 +
51499 +    if (ar->arWmiReady == FALSE) {
51500 +        return -EIO;
51501 +    }
51502 +
51503 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51504 +        return -EFAULT;
51505 +    }
51506 +
51507 +    ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid);
51508 +
51509 +    switch (ret) {
51510 +        case A_OK:
51511 +            return 0;
51512 +        case A_EBUSY :
51513 +            return -EBUSY;
51514 +        case A_NO_MEMORY:
51515 +            return -ENOMEM;
51516 +        case A_EINVAL:
51517 +        default:
51518 +            return -EFAULT;
51519 +    }
51520 +}
51521 +
51522 +static int
51523 +ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
51524 +{
51525 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51526 +    struct ar6000_queuereq qreq;
51527 +    int ret = 0;
51528 +
51529 +    if (ar->arWmiReady == FALSE) {
51530 +        return -EIO;
51531 +    }
51532 +
51533 +    if( copy_from_user(&qreq, rq->ifr_data,
51534 +                  sizeof(struct ar6000_queuereq)))
51535 +        return -EFAULT;
51536 +
51537 +    qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass);
51538 +
51539 +    if (copy_to_user(rq->ifr_data, &qreq,
51540 +                 sizeof(struct ar6000_queuereq)))
51541 +    {
51542 +        ret = -EFAULT;
51543 +    }
51544 +
51545 +    return ret;
51546 +}
51547 +
51548 +#ifdef CONFIG_HOST_TCMD_SUPPORT
51549 +static A_STATUS
51550 +ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev,
51551 +                                 struct ifreq *rq, A_UINT8 *data, A_UINT32 len)
51552 +{
51553 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51554 +    A_UINT32    buf[2];
51555 +    int ret = 0;
51556 +
51557 +    if (ar->arWmiReady == FALSE) {
51558 +        return -EIO;
51559 +    }
51560 +
51561 +    if (down_interruptible(&ar->arSem)) {
51562 +        return -ERESTARTSYS;
51563 +    }
51564 +    ar->tcmdRxReport = 0;
51565 +    if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) {
51566 +        up(&ar->arSem);
51567 +        return -EIO;
51568 +    }
51569 +
51570 +    wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ);
51571 +
51572 +    if (signal_pending(current)) {
51573 +        ret = -EINTR;
51574 +    }
51575 +
51576 +    buf[0] = ar->tcmdRxTotalPkt;
51577 +    buf[1] = ar->tcmdRxRssi;
51578 +    if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) {
51579 +        ret = -EFAULT;
51580 +    }
51581 +
51582 +    up(&ar->arSem);
51583 +
51584 +    return ret;
51585 +}
51586 +
51587 +void
51588 +ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len)
51589 +{
51590 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
51591 +    TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results;
51592 +
51593 +    ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt;
51594 +    ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm;
51595 +    ar->tcmdRxReport = 1;
51596 +
51597 +    wake_up(&arEvent);
51598 +}
51599 +#endif /* CONFIG_HOST_TCMD_SUPPORT*/
51600 +
51601 +static int
51602 +ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
51603 +{
51604 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51605 +    WMI_TARGET_ERROR_REPORT_BITMASK cmd;
51606 +    int ret = 0;
51607 +
51608 +    if (ar->arWmiReady == FALSE) {
51609 +        return -EIO;
51610 +    }
51611 +
51612 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51613 +        return -EFAULT;
51614 +    }
51615 +
51616 +    ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
51617 +
51618 +    return  (ret==0 ? ret : -EINVAL);
51619 +}
51620 +
51621 +static int
51622 +ar6000_clear_target_stats(struct net_device *dev)
51623 +{
51624 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51625 +    TARGET_STATS *pStats = &ar->arTargetStats;
51626 +    int ret = 0;
51627 +
51628 +    if (ar->arWmiReady == FALSE) {
51629 +       return -EIO;
51630 +    }
51631 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
51632 +    A_MEMZERO(pStats, sizeof(TARGET_STATS));
51633 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
51634 +    return ret;
51635 +}
51636 +
51637 +static int
51638 +ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
51639 +{
51640 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51641 +    TARGET_STATS_CMD cmd;
51642 +    TARGET_STATS *pStats = &ar->arTargetStats;
51643 +    int ret = 0;
51644 +
51645 +    if (ar->arWmiReady == FALSE) {
51646 +        return -EIO;
51647 +    }
51648 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51649 +        return -EFAULT;
51650 +    }
51651 +    if (down_interruptible(&ar->arSem)) {
51652 +        return -ERESTARTSYS;
51653 +    }
51654 +
51655 +    ar->statsUpdatePending = TRUE;
51656 +
51657 +    if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
51658 +        up(&ar->arSem);
51659 +        return -EIO;
51660 +    }
51661 +
51662 +    wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
51663 +
51664 +    if (signal_pending(current)) {
51665 +        ret = -EINTR;
51666 +    }
51667 +
51668 +    if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
51669 +        ret = -EFAULT;
51670 +    }
51671 +
51672 +    if (cmd.clearStats == 1) {
51673 +        ret = ar6000_clear_target_stats(dev);
51674 +    }
51675 +
51676 +    up(&ar->arSem);
51677 +
51678 +    return ret;
51679 +}
51680 +
51681 +static int
51682 +ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
51683 +{
51684 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51685 +    WMI_SET_ACCESS_PARAMS_CMD cmd;
51686 +    int ret = 0;
51687 +
51688 +    if (ar->arWmiReady == FALSE) {
51689 +        return -EIO;
51690 +    }
51691 +
51692 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51693 +        return -EFAULT;
51694 +    }
51695 +
51696 +    if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax,
51697 +                                  cmd.aifsn) == A_OK)
51698 +    {
51699 +        ret = 0;
51700 +    } else {
51701 +        ret = -EINVAL;
51702 +    }
51703 +
51704 +    return (ret);
51705 +}
51706 +
51707 +static int
51708 +ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
51709 +{
51710 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51711 +    WMI_DISC_TIMEOUT_CMD cmd;
51712 +    int ret = 0;
51713 +
51714 +    if (ar->arWmiReady == FALSE) {
51715 +        return -EIO;
51716 +    }
51717 +
51718 +    if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
51719 +        return -EFAULT;
51720 +    }
51721 +
51722 +    if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK)
51723 +    {
51724 +        ret = 0;
51725 +    } else {
51726 +        ret = -EINVAL;
51727 +    }
51728 +
51729 +    return (ret);
51730 +}
51731 +
51732 +static int
51733 +ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata)
51734 +{
51735 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51736 +    WMI_SET_VOICE_PKT_SIZE_CMD cmd;
51737 +    int ret = 0;
51738 +
51739 +    if (ar->arWmiReady == FALSE) {
51740 +        return -EIO;
51741 +    }
51742 +
51743 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51744 +        return -EFAULT;
51745 +    }
51746 +
51747 +    if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK)
51748 +    {
51749 +        ret = 0;
51750 +    } else {
51751 +        ret = -EINVAL;
51752 +    }
51753 +
51754 +
51755 +    return (ret);
51756 +}
51757 +
51758 +static int
51759 +ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata)
51760 +{
51761 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51762 +    WMI_SET_MAX_SP_LEN_CMD cmd;
51763 +    int ret = 0;
51764 +
51765 +    if (ar->arWmiReady == FALSE) {
51766 +        return -EIO;
51767 +    }
51768 +
51769 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51770 +        return -EFAULT;
51771 +    }
51772 +
51773 +    if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK)
51774 +    {
51775 +        ret = 0;
51776 +    } else {
51777 +        ret = -EINVAL;
51778 +    }
51779 +
51780 +    return (ret);
51781 +}
51782 +
51783 +
51784 +static int
51785 +ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata)
51786 +{
51787 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51788 +    WMI_SET_BT_STATUS_CMD cmd;
51789 +    int ret = 0;
51790 +
51791 +    if (ar->arWmiReady == FALSE) {
51792 +        return -EIO;
51793 +    }
51794 +
51795 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51796 +        return -EFAULT;
51797 +    }
51798 +
51799 +    if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK)
51800 +    {
51801 +        ret = 0;
51802 +    } else {
51803 +        ret = -EINVAL;
51804 +    }
51805 +
51806 +    return (ret);
51807 +}
51808 +
51809 +static int
51810 +ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata)
51811 +{
51812 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51813 +    WMI_SET_BT_PARAMS_CMD cmd;
51814 +    int ret = 0;
51815 +
51816 +    if (ar->arWmiReady == FALSE) {
51817 +        return -EIO;
51818 +    }
51819 +
51820 +    if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
51821 +        return -EFAULT;
51822 +    }
51823 +
51824 +    if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK)
51825 +    {
51826 +        ret = 0;
51827 +    } else {
51828 +        ret = -EINVAL;
51829 +    }
51830 +
51831 +    return (ret);
51832 +}
51833 +
51834 +#ifdef CONFIG_HOST_GPIO_SUPPORT
51835 +struct ar6000_gpio_intr_wait_cmd_s  gpio_intr_results;
51836 +/* gpio_reg_results and gpio_data_available are protected by arSem */
51837 +static struct ar6000_gpio_register_cmd_s gpio_reg_results;
51838 +static A_BOOL gpio_data_available; /* Requested GPIO data available */
51839 +static A_BOOL gpio_intr_available; /* GPIO interrupt info available */
51840 +static A_BOOL gpio_ack_received;   /* GPIO ack was received */
51841 +
51842 +/* Host-side initialization for General Purpose I/O support */
51843 +void ar6000_gpio_init(void)
51844 +{
51845 +    gpio_intr_available = FALSE;
51846 +    gpio_data_available = FALSE;
51847 +    gpio_ack_received   = FALSE;
51848 +}
51849 +
51850 +/*
51851 + * Called when a GPIO interrupt is received from the Target.
51852 + * intr_values shows which GPIO pins have interrupted.
51853 + * input_values shows a recent value of GPIO pins.
51854 + */
51855 +void
51856 +ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values)
51857 +{
51858 +    gpio_intr_results.intr_mask = intr_mask;
51859 +    gpio_intr_results.input_values = input_values;
51860 +    *((volatile A_BOOL *)&gpio_intr_available) = TRUE;
51861 +    wake_up(&arEvent);
51862 +}
51863 +
51864 +/*
51865 + * This is called when a response is received from the Target
51866 + * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
51867 + * call.
51868 + */
51869 +void
51870 +ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value)
51871 +{
51872 +    gpio_reg_results.gpioreg_id = reg_id;
51873 +    gpio_reg_results.value = value;
51874 +    *((volatile A_BOOL *)&gpio_data_available) = TRUE;
51875 +    wake_up(&arEvent);
51876 +}
51877 +
51878 +/*
51879 + * This is called when an acknowledgement is received from the Target
51880 + * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
51881 + * call.
51882 + */
51883 +void
51884 +ar6000_gpio_ack_rx(void)
51885 +{
51886 +    gpio_ack_received = TRUE;
51887 +    wake_up(&arEvent);
51888 +}
51889 +
51890 +A_STATUS
51891 +ar6000_gpio_output_set(struct net_device *dev,
51892 +                       A_UINT32 set_mask,
51893 +                       A_UINT32 clear_mask,
51894 +                       A_UINT32 enable_mask,
51895 +                       A_UINT32 disable_mask)
51896 +{
51897 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51898 +
51899 +    gpio_ack_received = FALSE;
51900 +    return wmi_gpio_output_set(ar->arWmi,
51901 +                set_mask, clear_mask, enable_mask, disable_mask);
51902 +}
51903 +
51904 +static A_STATUS
51905 +ar6000_gpio_input_get(struct net_device *dev)
51906 +{
51907 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51908 +
51909 +    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
51910 +    return wmi_gpio_input_get(ar->arWmi);
51911 +}
51912 +
51913 +static A_STATUS
51914 +ar6000_gpio_register_set(struct net_device *dev,
51915 +                         A_UINT32 gpioreg_id,
51916 +                         A_UINT32 value)
51917 +{
51918 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51919 +
51920 +    gpio_ack_received = FALSE;
51921 +    return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
51922 +}
51923 +
51924 +static A_STATUS
51925 +ar6000_gpio_register_get(struct net_device *dev,
51926 +                         A_UINT32 gpioreg_id)
51927 +{
51928 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51929 +
51930 +    *((volatile A_BOOL *)&gpio_data_available) = FALSE;
51931 +    return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
51932 +}
51933 +
51934 +static A_STATUS
51935 +ar6000_gpio_intr_ack(struct net_device *dev,
51936 +                     A_UINT32 ack_mask)
51937 +{
51938 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51939 +
51940 +    gpio_intr_available = FALSE;
51941 +    return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
51942 +}
51943 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
51944 +
51945 +int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
51946 +{
51947 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
51948 +    HIF_DEVICE *hifDevice = ar->arHifDevice;
51949 +    int ret, param, param2;
51950 +    unsigned int address = 0;
51951 +    unsigned int length = 0;
51952 +    unsigned char *buffer;
51953 +    char *userdata;
51954 +    A_UINT32 connectCtrlFlags;
51955 +
51956 +
51957 +    static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0,
51958 +                                           WMI_SHORTSCANRATIO_DEFAULT,
51959 +                                           DEFAULT_SCAN_CTRL_FLAGS,
51960 +                                           0};
51961 +    WMI_SET_AKMP_PARAMS_CMD  akmpParams;
51962 +    WMI_SET_PMKID_LIST_CMD   pmkidInfo;
51963 +
51964 +    if (cmd == AR6000_IOCTL_EXTENDED)
51965 +    {
51966 +        /*
51967 +         * This allows for many more wireless ioctls than would otherwise
51968 +         * be available.  Applications embed the actual ioctl command in
51969 +         * the first word of the parameter block, and use the command
51970 +         * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
51971 +         */
51972 +        get_user(cmd, (int *)rq->ifr_data);
51973 +        userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
51974 +    }
51975 +    else
51976 +    {
51977 +        userdata = (char *)rq->ifr_data;
51978 +    }
51979 +
51980 +    if ((ar->arWlanState == WLAN_DISABLED) &&
51981 +        ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) &&
51982 +         (cmd != AR6000_XIOCTL_DIAG_READ) &&
51983 +         (cmd != AR6000_XIOCTL_DIAG_WRITE)))
51984 +    {
51985 +        return -EIO;
51986 +    }
51987 +
51988 +    ret = 0;
51989 +    switch(cmd)
51990 +    {
51991 +#ifdef CONFIG_HOST_TCMD_SUPPORT
51992 +        case AR6000_XIOCTL_TCMD_CONT_TX:
51993 +            {
51994 +                TCMD_CONT_TX txCmd;
51995 +
51996 +                if (ar->tcmdPm == TCMD_PM_SLEEP) {
51997 +                    A_PRINTF("Can NOT send tx tcmd when target is asleep! \n");
51998 +                    return -EFAULT;
51999 +                }
52000 +
52001 +                if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX)))
52002 +                    return -EFAULT;
52003 +                wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX));
52004 +            }
52005 +            break;
52006 +        case AR6000_XIOCTL_TCMD_CONT_RX:
52007 +            {
52008 +                TCMD_CONT_RX rxCmd;
52009 +
52010 +                if (ar->tcmdPm == TCMD_PM_SLEEP) {
52011 +                    A_PRINTF("Can NOT send rx tcmd when target is asleep! \n");
52012 +                    return -EFAULT;
52013 +                }
52014 +                if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX)))
52015 +                    return -EFAULT;
52016 +                switch(rxCmd.act)
52017 +                {
52018 +                    case TCMD_CONT_RX_PROMIS:
52019 +                    case TCMD_CONT_RX_FILTER:
52020 +                    case TCMD_CONT_RX_SETMAC:
52021 +                         wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd,
52022 +                                                sizeof(TCMD_CONT_RX));
52023 +                         break;
52024 +                    case TCMD_CONT_RX_REPORT:
52025 +                         ar6000_ioctl_tcmd_get_rx_report(dev, rq,
52026 +                         (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX));
52027 +                         break;
52028 +                    default:
52029 +                         A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act);
52030 +                         return -EINVAL;
52031 +                }
52032 +            }
52033 +            break;
52034 +        case AR6000_XIOCTL_TCMD_PM:
52035 +            {
52036 +                TCMD_PM pmCmd;
52037 +
52038 +                if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM)))
52039 +                    return -EFAULT;
52040 +                ar->tcmdPm = pmCmd.mode;
52041 +                wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM));
52042 +            }
52043 +            break;
52044 +#endif /* CONFIG_HOST_TCMD_SUPPORT */
52045 +
52046 +        case AR6000_XIOCTL_BMI_DONE:
52047 +            if(bmienable)
52048 +            {
52049 +                ret = ar6000_init(dev);
52050 +            }
52051 +            else
52052 +            {
52053 +                ret = BMIDone(hifDevice);
52054 +            }
52055 +            break;
52056 +
52057 +        case AR6000_XIOCTL_BMI_READ_MEMORY:
52058 +            get_user(address, (unsigned int *)userdata);
52059 +            get_user(length, (unsigned int *)userdata + 1);
52060 +            AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n",
52061 +                             address, length);
52062 +            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
52063 +                A_MEMZERO(buffer, length);
52064 +                ret = BMIReadMemory(hifDevice, address, buffer, length);
52065 +                if (copy_to_user(rq->ifr_data, buffer, length)) {
52066 +                    ret = -EFAULT;
52067 +                }
52068 +                A_FREE(buffer);
52069 +            } else {
52070 +                ret = -ENOMEM;
52071 +            }
52072 +            break;
52073 +
52074 +        case AR6000_XIOCTL_BMI_WRITE_MEMORY:
52075 +            get_user(address, (unsigned int *)userdata);
52076 +            get_user(length, (unsigned int *)userdata + 1);
52077 +            AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n",
52078 +                             address, length);
52079 +            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
52080 +                A_MEMZERO(buffer, length);
52081 +                if (copy_from_user(buffer, &userdata[sizeof(address) +
52082 +                                   sizeof(length)], length))
52083 +                {
52084 +                    ret = -EFAULT;
52085 +                } else {
52086 +                    ret = BMIWriteMemory(hifDevice, address, buffer, length);
52087 +                }
52088 +                A_FREE(buffer);
52089 +            } else {
52090 +                ret = -ENOMEM;
52091 +            }
52092 +            break;
52093 +
52094 +        case AR6000_XIOCTL_BMI_TEST:
52095 +           AR_DEBUG_PRINTF("No longer supported\n");
52096 +           ret = -EOPNOTSUPP;
52097 +           break;
52098 +
52099 +        case AR6000_XIOCTL_BMI_EXECUTE:
52100 +            get_user(address, (unsigned int *)userdata);
52101 +            get_user(param, (unsigned int *)userdata + 1);
52102 +            AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n",
52103 +                             address, param);
52104 +            ret = BMIExecute(hifDevice, address, &param);
52105 +            put_user(param, (unsigned int *)rq->ifr_data); /* return value */
52106 +            break;
52107 +
52108 +        case AR6000_XIOCTL_BMI_SET_APP_START:
52109 +            get_user(address, (unsigned int *)userdata);
52110 +            AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address);
52111 +            ret = BMISetAppStart(hifDevice, address);
52112 +            break;
52113 +
52114 +        case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
52115 +            get_user(address, (unsigned int *)userdata);
52116 +            ret = BMIReadSOCRegister(hifDevice, address, &param);
52117 +            put_user(param, (unsigned int *)rq->ifr_data); /* return value */
52118 +            break;
52119 +
52120 +        case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
52121 +            get_user(address, (unsigned int *)userdata);
52122 +            get_user(param, (unsigned int *)userdata + 1);
52123 +            ret = BMIWriteSOCRegister(hifDevice, address, param);
52124 +            break;
52125 +
52126 +#ifdef HTC_RAW_INTERFACE
52127 +        case AR6000_XIOCTL_HTC_RAW_OPEN:
52128 +            ret = A_OK;
52129 +            if (!arRawIfEnabled(ar)) {
52130 +                /* make sure block size is set in case the target was reset since last
52131 +                  * BMI phase (i.e. flashup downloads) */
52132 +                ret = ar6000_SetHTCBlockSize(ar);
52133 +                if (A_FAILED(ret)) {
52134 +                    break;
52135 +                }
52136 +                /* Terminate the BMI phase */
52137 +                ret = BMIDone(hifDevice);
52138 +                if (ret == A_OK) {
52139 +                    ret = ar6000_htc_raw_open(ar);
52140 +                }
52141 +            }
52142 +            break;
52143 +
52144 +        case AR6000_XIOCTL_HTC_RAW_CLOSE:
52145 +            if (arRawIfEnabled(ar)) {
52146 +                ret = ar6000_htc_raw_close(ar);
52147 +                arRawIfEnabled(ar) = FALSE;
52148 +            } else {
52149 +                ret = A_ERROR;
52150 +            }
52151 +            break;
52152 +
52153 +        case AR6000_XIOCTL_HTC_RAW_READ:
52154 +            if (arRawIfEnabled(ar)) {
52155 +                unsigned int streamID;
52156 +                get_user(streamID, (unsigned int *)userdata);
52157 +                get_user(length, (unsigned int *)userdata + 1);
52158 +                buffer = rq->ifr_data + sizeof(length);
52159 +                ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID,
52160 +                                          buffer, length);
52161 +                put_user(ret, (unsigned int *)rq->ifr_data);
52162 +            } else {
52163 +                ret = A_ERROR;
52164 +            }
52165 +            break;
52166 +
52167 +        case AR6000_XIOCTL_HTC_RAW_WRITE:
52168 +            if (arRawIfEnabled(ar)) {
52169 +                unsigned int streamID;
52170 +                get_user(streamID, (unsigned int *)userdata);
52171 +                get_user(length, (unsigned int *)userdata + 1);
52172 +                buffer = userdata + sizeof(streamID) + sizeof(length);
52173 +                ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID,
52174 +                                           buffer, length);
52175 +                put_user(ret, (unsigned int *)rq->ifr_data);
52176 +            } else {
52177 +                ret = A_ERROR;
52178 +            }
52179 +            break;
52180 +#endif /* HTC_RAW_INTERFACE */
52181 +
52182 +        case AR6000_IOCTL_WMI_GETREV:
52183 +        {
52184 +            if (copy_to_user(rq->ifr_data, &ar->arVersion,
52185 +                             sizeof(ar->arVersion)))
52186 +            {
52187 +                ret = -EFAULT;
52188 +            }
52189 +            break;
52190 +        }
52191 +        case AR6000_IOCTL_WMI_SETPWR:
52192 +        {
52193 +            WMI_POWER_MODE_CMD pwrModeCmd;
52194 +
52195 +            if (ar->arWmiReady == FALSE) {
52196 +                ret = -EIO;
52197 +            } else if (copy_from_user(&pwrModeCmd, userdata,
52198 +                                   sizeof(pwrModeCmd)))
52199 +            {
52200 +                ret = -EFAULT;
52201 +            } else {
52202 +                if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
52203 +                       != A_OK)
52204 +                {
52205 +                    ret = -EIO;
52206 +                }
52207 +            }
52208 +            break;
52209 +        }
52210 +        case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
52211 +        {
52212 +            WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
52213 +
52214 +            if (ar->arWmiReady == FALSE) {
52215 +                ret = -EIO;
52216 +            } else if (copy_from_user(&ibssPmCaps, userdata,
52217 +                                   sizeof(ibssPmCaps)))
52218 +            {
52219 +                ret = -EFAULT;
52220 +            } else {
52221 +                if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
52222 +                    ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK)
52223 +                {
52224 +                    ret = -EIO;
52225 +                }
52226 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
52227 +                ar->arIbssPsEnable = ibssPmCaps.power_saving;
52228 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52229 +            }
52230 +            break;
52231 +        }
52232 +        case AR6000_IOCTL_WMI_SET_PMPARAMS:
52233 +        {
52234 +            WMI_POWER_PARAMS_CMD pmParams;
52235 +
52236 +            if (ar->arWmiReady == FALSE) {
52237 +                ret = -EIO;
52238 +            } else if (copy_from_user(&pmParams, userdata,
52239 +                                      sizeof(pmParams)))
52240 +            {
52241 +                ret = -EFAULT;
52242 +            } else {
52243 +                if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
52244 +                                     pmParams.pspoll_number,
52245 +                                     pmParams.dtim_policy) != A_OK)
52246 +                {
52247 +                    ret = -EIO;
52248 +                }
52249 +            }
52250 +            break;
52251 +        }
52252 +        case AR6000_IOCTL_WMI_SETSCAN:
52253 +        {
52254 +            if (ar->arWmiReady == FALSE) {
52255 +                ret = -EIO;
52256 +            } else if (copy_from_user(&scParams, userdata,
52257 +                                      sizeof(scParams)))
52258 +            {
52259 +                ret = -EFAULT;
52260 +            } else {
52261 +                if (CAN_SCAN_IN_CONNECT(scParams.scanCtrlFlags)) {
52262 +                    ar->arSkipScan = FALSE;
52263 +                } else {
52264 +                    ar->arSkipScan = TRUE;
52265 +                }
52266 +
52267 +                if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
52268 +                                       scParams.fg_end_period,
52269 +                                       scParams.bg_period,
52270 +                                       scParams.minact_chdwell_time,
52271 +                                       scParams.maxact_chdwell_time,
52272 +                                       scParams.pas_chdwell_time,
52273 +                                       scParams.shortScanRatio,
52274 +                                       scParams.scanCtrlFlags,
52275 +                                       scParams.max_dfsch_act_time) != A_OK)
52276 +                {
52277 +                    ret = -EIO;
52278 +                }
52279 +            }
52280 +            break;
52281 +        }
52282 +        case AR6000_IOCTL_WMI_SETLISTENINT:
52283 +        {
52284 +            WMI_LISTEN_INT_CMD listenCmd;
52285 +
52286 +            if (ar->arWmiReady == FALSE) {
52287 +                ret = -EIO;
52288 +            } else if (copy_from_user(&listenCmd, userdata,
52289 +                                      sizeof(listenCmd)))
52290 +            {
52291 +                ret = -EFAULT;
52292 +            } else {
52293 +                    if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) {
52294 +                        ret = -EIO;
52295 +                    } else {
52296 +                        AR6000_SPIN_LOCK(&ar->arLock, 0);
52297 +                        ar->arListenInterval = param;
52298 +                        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52299 +                    }
52300 +
52301 +                }
52302 +            break;
52303 +        }
52304 +        case AR6000_IOCTL_WMI_SET_BMISS_TIME:
52305 +        {
52306 +            WMI_BMISS_TIME_CMD bmissCmd;
52307 +
52308 +            if (ar->arWmiReady == FALSE) {
52309 +                ret = -EIO;
52310 +            } else if (copy_from_user(&bmissCmd, userdata,
52311 +                                      sizeof(bmissCmd)))
52312 +            {
52313 +                ret = -EFAULT;
52314 +            } else {
52315 +                if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) {
52316 +                    ret = -EIO;
52317 +                }
52318 +            }
52319 +            break;
52320 +        }
52321 +        case AR6000_IOCTL_WMI_SETBSSFILTER:
52322 +        {
52323 +            if (ar->arWmiReady == FALSE) {
52324 +                ret = -EIO;
52325 +            } else {
52326 +
52327 +                get_user(param, (unsigned char *)userdata);
52328 +                get_user(param2, (unsigned int *)(userdata + 1));
52329 +               printk("SETBSSFILTER: filter 0x%x, mask: 0x%x\n", param, param2);
52330 +                if (wmi_bssfilter_cmd(ar->arWmi, param, param2) != A_OK) {
52331 +                    ret = -EIO;
52332 +                }
52333 +            }
52334 +            break;
52335 +        }
52336 +        case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD:
52337 +        {
52338 +            ret = ar6000_ioctl_set_snr_threshold(dev, rq);
52339 +            break;
52340 +        }
52341 +        case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD:
52342 +        {
52343 +            ret = ar6000_ioctl_set_rssi_threshold(dev, rq);
52344 +            break;
52345 +        }
52346 +        case AR6000_XIOCTL_WMI_CLR_RSSISNR:
52347 +        {
52348 +            if (ar->arWmiReady == FALSE) {
52349 +                ret = -EIO;
52350 +            }
52351 +            ret = wmi_clr_rssi_snr(ar->arWmi);
52352 +            break;
52353 +        }
52354 +        case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD:
52355 +        {
52356 +            ret = ar6000_ioctl_set_lq_threshold(dev, rq);
52357 +            break;
52358 +        }
52359 +        case AR6000_XIOCTL_WMI_SET_LPREAMBLE:
52360 +        {
52361 +            WMI_SET_LPREAMBLE_CMD setLpreambleCmd;
52362 +
52363 +            if (ar->arWmiReady == FALSE) {
52364 +                ret = -EIO;
52365 +            } else if (copy_from_user(&setLpreambleCmd, userdata,
52366 +                                   sizeof(setLpreambleCmd)))
52367 +            {
52368 +                ret = -EFAULT;
52369 +            } else {
52370 +                if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status)
52371 +                       != A_OK)
52372 +                {
52373 +                    ret = -EIO;
52374 +                }
52375 +            }
52376 +
52377 +            break;
52378 +        }
52379 +        case AR6000_XIOCTL_WMI_SET_RTS:
52380 +        {
52381 +            WMI_SET_RTS_CMD rtsCmd;
52382 +
52383 +            if (ar->arWmiReady == FALSE) {
52384 +                ret = -EIO;
52385 +            } else if (copy_from_user(&rtsCmd, userdata,
52386 +                                   sizeof(rtsCmd)))
52387 +            {
52388 +                ret = -EFAULT;
52389 +            } else {
52390 +                if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold)
52391 +                       != A_OK)
52392 +                {
52393 +                    ret = -EIO;
52394 +                }
52395 +            }
52396 +
52397 +            break;
52398 +        }
52399 +        case AR6000_XIOCTL_WMI_SET_WMM:
52400 +        {
52401 +            ret = ar6000_ioctl_set_wmm(dev, rq);
52402 +            break;
52403 +        }
52404 +        case AR6000_XIOCTL_WMI_SET_TXOP:
52405 +        {
52406 +            ret = ar6000_ioctl_set_txop(dev, rq);
52407 +            break;
52408 +        }
52409 +        case AR6000_XIOCTL_WMI_GET_RD:
52410 +        {
52411 +            ret = ar6000_ioctl_get_rd(dev, rq);
52412 +            break;
52413 +        }
52414 +        case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
52415 +        {
52416 +            ret = ar6000_ioctl_set_channelParams(dev, rq);
52417 +            break;
52418 +        }
52419 +        case AR6000_IOCTL_WMI_SET_PROBEDSSID:
52420 +        {
52421 +            ret = ar6000_ioctl_set_probedSsid(dev, rq);
52422 +            break;
52423 +        }
52424 +        case AR6000_IOCTL_WMI_SET_BADAP:
52425 +        {
52426 +            ret = ar6000_ioctl_set_badAp(dev, rq);
52427 +            break;
52428 +        }
52429 +        case AR6000_IOCTL_WMI_CREATE_QOS:
52430 +        {
52431 +            ret = ar6000_ioctl_create_qos(dev, rq);
52432 +            break;
52433 +        }
52434 +        case AR6000_IOCTL_WMI_DELETE_QOS:
52435 +        {
52436 +            ret = ar6000_ioctl_delete_qos(dev, rq);
52437 +            break;
52438 +        }
52439 +        case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
52440 +        {
52441 +            ret = ar6000_ioctl_get_qos_queue(dev, rq);
52442 +            break;
52443 +        }
52444 +        case AR6000_IOCTL_WMI_GET_TARGET_STATS:
52445 +        {
52446 +            ret = ar6000_ioctl_get_target_stats(dev, rq);
52447 +            break;
52448 +        }
52449 +        case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
52450 +        {
52451 +            ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
52452 +            break;
52453 +        }
52454 +        case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
52455 +        {
52456 +            WMI_SET_ASSOC_INFO_CMD cmd;
52457 +            A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
52458 +
52459 +            if (ar->arWmiReady == FALSE) {
52460 +                ret = -EIO;
52461 +            } else {
52462 +                get_user(cmd.ieType, userdata);
52463 +                if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
52464 +                    ret = -EIO;
52465 +                } else {
52466 +                    get_user(cmd.bufferSize, userdata + 1);
52467 +                    if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) {
52468 +                        ret = -EFAULT;
52469 +                        break;
52470 +                    }
52471 +                    if (copy_from_user(assocInfo, userdata + 2,
52472 +                                       cmd.bufferSize))
52473 +                    {
52474 +                        ret = -EFAULT;
52475 +                    } else {
52476 +                        if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
52477 +                                                 cmd.bufferSize,
52478 +                                                 assocInfo) != A_OK)
52479 +                        {
52480 +                            ret = -EIO;
52481 +                        }
52482 +                    }
52483 +                }
52484 +            }
52485 +            break;
52486 +        }
52487 +        case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
52488 +        {
52489 +            ret = ar6000_ioctl_set_access_params(dev, rq);
52490 +            break;
52491 +        }
52492 +        case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
52493 +        {
52494 +            ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
52495 +            break;
52496 +        }
52497 +        case AR6000_XIOCTL_FORCE_TARGET_RESET:
52498 +        {
52499 +            if (ar->arHtcTarget)
52500 +            {
52501 +//                HTCForceReset(htcTarget);
52502 +            }
52503 +            else
52504 +            {
52505 +                AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n");
52506 +            }
52507 +            break;
52508 +        }
52509 +        case AR6000_XIOCTL_TARGET_INFO:
52510 +        case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */
52511 +        {
52512 +            /* If we made it to here, then the Target exists and is ready. */
52513 +
52514 +            if (cmd == AR6000_XIOCTL_TARGET_INFO) {
52515 +                if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver,
52516 +                                 sizeof(ar->arVersion.target_ver)))
52517 +                {
52518 +                    ret = -EFAULT;
52519 +                }
52520 +                if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType,
52521 +                                 sizeof(ar->arTargetType)))
52522 +                {
52523 +                    ret = -EFAULT;
52524 +                }
52525 +            }
52526 +            break;
52527 +        }
52528 +        case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS:
52529 +        {
52530 +            WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam;
52531 +
52532 +            if (copy_from_user(&hbparam, userdata, sizeof(hbparam)))
52533 +            {
52534 +                ret = -EFAULT;
52535 +            } else {
52536 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
52537 +                /* Start a cyclic timer with the parameters provided. */
52538 +                if (hbparam.frequency) {
52539 +                    ar->arHBChallengeResp.frequency = hbparam.frequency;
52540 +                }
52541 +                if (hbparam.threshold) {
52542 +                    ar->arHBChallengeResp.missThres = hbparam.threshold;
52543 +                }
52544 +
52545 +                /* Delete the pending timer and start a new one */
52546 +                if (timer_pending(&ar->arHBChallengeResp.timer)) {
52547 +                    A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
52548 +                }
52549 +                A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
52550 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52551 +            }
52552 +            break;
52553 +        }
52554 +        case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP:
52555 +        {
52556 +            A_UINT32 cookie;
52557 +
52558 +            if (copy_from_user(&cookie, userdata, sizeof(cookie))) {
52559 +                return -EFAULT;
52560 +            }
52561 +
52562 +            /* Send the challenge on the control channel */
52563 +            if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) {
52564 +                return -EIO;
52565 +            }
52566 +            break;
52567 +        }
52568 +#ifdef USER_KEYS
52569 +        case AR6000_XIOCTL_USER_SETKEYS:
52570 +        {
52571 +
52572 +            ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN;
52573 +
52574 +            if (copy_from_user(&ar->user_key_ctrl, userdata,
52575 +                               sizeof(ar->user_key_ctrl)))
52576 +            {
52577 +                return -EFAULT;
52578 +            }
52579 +
52580 +            A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl);
52581 +            break;
52582 +        }
52583 +#endif /* USER_KEYS */
52584 +
52585 +#ifdef CONFIG_HOST_GPIO_SUPPORT
52586 +        case AR6000_XIOCTL_GPIO_OUTPUT_SET:
52587 +        {
52588 +            struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
52589 +
52590 +            if (ar->arWmiReady == FALSE) {
52591 +                return -EIO;
52592 +            }
52593 +            if (down_interruptible(&ar->arSem)) {
52594 +                return -ERESTARTSYS;
52595 +            }
52596 +
52597 +            if (copy_from_user(&gpio_output_set_cmd, userdata,
52598 +                                sizeof(gpio_output_set_cmd)))
52599 +            {
52600 +                ret = -EFAULT;
52601 +            } else {
52602 +                ret = ar6000_gpio_output_set(dev,
52603 +                                             gpio_output_set_cmd.set_mask,
52604 +                                             gpio_output_set_cmd.clear_mask,
52605 +                                             gpio_output_set_cmd.enable_mask,
52606 +                                             gpio_output_set_cmd.disable_mask);
52607 +                if (ret != A_OK) {
52608 +                    ret = EIO;
52609 +                }
52610 +            }
52611 +            up(&ar->arSem);
52612 +            break;
52613 +        }
52614 +        case AR6000_XIOCTL_GPIO_INPUT_GET:
52615 +        {
52616 +            if (ar->arWmiReady == FALSE) {
52617 +                return -EIO;
52618 +            }
52619 +            if (down_interruptible(&ar->arSem)) {
52620 +                return -ERESTARTSYS;
52621 +            }
52622 +
52623 +            ret = ar6000_gpio_input_get(dev);
52624 +            if (ret != A_OK) {
52625 +                up(&ar->arSem);
52626 +                return -EIO;
52627 +            }
52628 +
52629 +            /* Wait for Target to respond. */
52630 +            wait_event_interruptible(arEvent, gpio_data_available);
52631 +            if (signal_pending(current)) {
52632 +                ret = -EINTR;
52633 +            } else {
52634 +                A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
52635 +
52636 +                if (copy_to_user(userdata, &gpio_reg_results.value,
52637 +                                 sizeof(gpio_reg_results.value)))
52638 +                {
52639 +                    ret = -EFAULT;
52640 +                }
52641 +            }
52642 +            up(&ar->arSem);
52643 +            break;
52644 +        }
52645 +        case AR6000_XIOCTL_GPIO_REGISTER_SET:
52646 +        {
52647 +            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
52648 +
52649 +            if (ar->arWmiReady == FALSE) {
52650 +                return -EIO;
52651 +            }
52652 +            if (down_interruptible(&ar->arSem)) {
52653 +                return -ERESTARTSYS;
52654 +            }
52655 +
52656 +            if (copy_from_user(&gpio_register_cmd, userdata,
52657 +                                sizeof(gpio_register_cmd)))
52658 +            {
52659 +                ret = -EFAULT;
52660 +            } else {
52661 +                ret = ar6000_gpio_register_set(dev,
52662 +                                               gpio_register_cmd.gpioreg_id,
52663 +                                               gpio_register_cmd.value);
52664 +                if (ret != A_OK) {
52665 +                    ret = EIO;
52666 +                }
52667 +
52668 +                /* Wait for acknowledgement from Target */
52669 +                wait_event_interruptible(arEvent, gpio_ack_received);
52670 +                if (signal_pending(current)) {
52671 +                    ret = -EINTR;
52672 +                }
52673 +            }
52674 +            up(&ar->arSem);
52675 +            break;
52676 +        }
52677 +        case AR6000_XIOCTL_GPIO_REGISTER_GET:
52678 +        {
52679 +            struct ar6000_gpio_register_cmd_s gpio_register_cmd;
52680 +
52681 +            if (ar->arWmiReady == FALSE) {
52682 +                return -EIO;
52683 +            }
52684 +            if (down_interruptible(&ar->arSem)) {
52685 +                return -ERESTARTSYS;
52686 +            }
52687 +
52688 +            if (copy_from_user(&gpio_register_cmd, userdata,
52689 +                                sizeof(gpio_register_cmd)))
52690 +            {
52691 +                ret = -EFAULT;
52692 +            } else {
52693 +                ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
52694 +                if (ret != A_OK) {
52695 +                    up(&ar->arSem);
52696 +                    return -EIO;
52697 +                }
52698 +
52699 +                /* Wait for Target to respond. */
52700 +                wait_event_interruptible(arEvent, gpio_data_available);
52701 +                if (signal_pending(current)) {
52702 +                    ret = -EINTR;
52703 +                } else {
52704 +                    A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
52705 +                    if (copy_to_user(userdata, &gpio_reg_results,
52706 +                                     sizeof(gpio_reg_results)))
52707 +                    {
52708 +                        ret = -EFAULT;
52709 +                    }
52710 +                }
52711 +            }
52712 +            up(&ar->arSem);
52713 +            break;
52714 +        }
52715 +        case AR6000_XIOCTL_GPIO_INTR_ACK:
52716 +        {
52717 +            struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
52718 +
52719 +            if (ar->arWmiReady == FALSE) {
52720 +                return -EIO;
52721 +            }
52722 +            if (down_interruptible(&ar->arSem)) {
52723 +                return -ERESTARTSYS;
52724 +            }
52725 +
52726 +            if (copy_from_user(&gpio_intr_ack_cmd, userdata,
52727 +                                sizeof(gpio_intr_ack_cmd)))
52728 +            {
52729 +                ret = -EFAULT;
52730 +            } else {
52731 +                ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
52732 +                if (ret != A_OK) {
52733 +                    ret = EIO;
52734 +                }
52735 +            }
52736 +            up(&ar->arSem);
52737 +            break;
52738 +        }
52739 +        case AR6000_XIOCTL_GPIO_INTR_WAIT:
52740 +        {
52741 +            /* Wait for Target to report an interrupt. */
52742 +            dev_hold(dev);
52743 +            rtnl_unlock();
52744 +            wait_event_interruptible(arEvent, gpio_intr_available);
52745 +            rtnl_lock();
52746 +            __dev_put(dev);
52747 +
52748 +            if (signal_pending(current)) {
52749 +                ret = -EINTR;
52750 +            } else {
52751 +                if (copy_to_user(userdata, &gpio_intr_results,
52752 +                                 sizeof(gpio_intr_results)))
52753 +                {
52754 +                    ret = -EFAULT;
52755 +                }
52756 +            }
52757 +            break;
52758 +        }
52759 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
52760 +
52761 +        case AR6000_XIOCTL_DBGLOG_CFG_MODULE:
52762 +        {
52763 +            struct ar6000_dbglog_module_config_s config;
52764 +
52765 +            if (copy_from_user(&config, userdata, sizeof(config))) {
52766 +                return -EFAULT;
52767 +            }
52768 +
52769 +            /* Send the challenge on the control channel */
52770 +            if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask,
52771 +                                            config.tsr, config.rep,
52772 +                                            config.size, config.valid) != A_OK)
52773 +            {
52774 +                return -EIO;
52775 +            }
52776 +            break;
52777 +        }
52778 +
52779 +        case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS:
52780 +        {
52781 +            /* Send the challenge on the control channel */
52782 +            if (ar6000_dbglog_get_debug_logs(ar) != A_OK)
52783 +            {
52784 +                return -EIO;
52785 +            }
52786 +            break;
52787 +        }
52788 +
52789 +        case AR6000_XIOCTL_SET_ADHOC_BSSID:
52790 +        {
52791 +            WMI_SET_ADHOC_BSSID_CMD adhocBssid;
52792 +
52793 +            if (ar->arWmiReady == FALSE) {
52794 +                ret = -EIO;
52795 +            } else if (copy_from_user(&adhocBssid, userdata,
52796 +                                      sizeof(adhocBssid)))
52797 +            {
52798 +                ret = -EFAULT;
52799 +            } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
52800 +                                AR6000_ETH_ADDR_LEN) == 0)
52801 +            {
52802 +                ret = -EFAULT;
52803 +            } else {
52804 +
52805 +                A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
52806 +        }
52807 +            break;
52808 +        }
52809 +
52810 +        case AR6000_XIOCTL_SET_OPT_MODE:
52811 +        {
52812 +        WMI_SET_OPT_MODE_CMD optModeCmd;
52813 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
52814 +
52815 +            if (ar->arWmiReady == FALSE) {
52816 +                ret = -EIO;
52817 +            } else if (copy_from_user(&optModeCmd, userdata,
52818 +                                      sizeof(optModeCmd)))
52819 +            {
52820 +                ret = -EFAULT;
52821 +            } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
52822 +                ret = -EFAULT;
52823 +
52824 +            } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
52825 +                       != A_OK)
52826 +            {
52827 +                ret = -EIO;
52828 +            }
52829 +            break;
52830 +        }
52831 +
52832 +        case AR6000_XIOCTL_OPT_SEND_FRAME:
52833 +        {
52834 +        WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
52835 +            A_UINT8 data[MAX_OPT_DATA_LEN];
52836 +
52837 +            if (ar->arWmiReady == FALSE) {
52838 +                ret = -EIO;
52839 +            } else if (copy_from_user(&optTxFrmCmd, userdata,
52840 +                                      sizeof(optTxFrmCmd)))
52841 +            {
52842 +                ret = -EFAULT;
52843 +            } else if (copy_from_user(data,
52844 +                                      userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1,
52845 +                                      optTxFrmCmd.optIEDataLen))
52846 +            {
52847 +                ret = -EFAULT;
52848 +            } else {
52849 +                ret = wmi_opt_tx_frame_cmd(ar->arWmi,
52850 +                                           optTxFrmCmd.frmType,
52851 +                                           optTxFrmCmd.dstAddr,
52852 +                                           optTxFrmCmd.bssid,
52853 +                                           optTxFrmCmd.optIEDataLen,
52854 +                                           data);
52855 +            }
52856 +
52857 +            break;
52858 +        }
52859 +        case AR6000_XIOCTL_WMI_SETRETRYLIMITS:
52860 +        {
52861 +            WMI_SET_RETRY_LIMITS_CMD setRetryParams;
52862 +
52863 +            if (ar->arWmiReady == FALSE) {
52864 +                ret = -EIO;
52865 +            } else if (copy_from_user(&setRetryParams, userdata,
52866 +                                      sizeof(setRetryParams)))
52867 +            {
52868 +                ret = -EFAULT;
52869 +            } else {
52870 +                if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType,
52871 +                                          setRetryParams.trafficClass,
52872 +                                          setRetryParams.maxRetries,
52873 +                                          setRetryParams.enableNotify) != A_OK)
52874 +                {
52875 +                    ret = -EIO;
52876 +                }
52877 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
52878 +                ar->arMaxRetries = setRetryParams.maxRetries;
52879 +                AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52880 +            }
52881 +            break;
52882 +        }
52883 +
52884 +        case AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL:
52885 +        {
52886 +            WMI_BEACON_INT_CMD bIntvlCmd;
52887 +
52888 +            if (ar->arWmiReady == FALSE) {
52889 +                ret = -EIO;
52890 +            } else if (copy_from_user(&bIntvlCmd, userdata,
52891 +                       sizeof(bIntvlCmd)))
52892 +            {
52893 +                ret = -EFAULT;
52894 +            } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
52895 +                        != A_OK)
52896 +            {
52897 +                ret = -EIO;
52898 +            }
52899 +            break;
52900 +        }
52901 +        case IEEE80211_IOCTL_SETAUTHALG:
52902 +        {
52903 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
52904 +            struct ieee80211req_authalg req;
52905 +
52906 +            if (ar->arWmiReady == FALSE) {
52907 +                ret = -EIO;
52908 +            } else if (copy_from_user(&req, userdata,
52909 +                       sizeof(struct ieee80211req_authalg)))
52910 +            {
52911 +                ret = -EFAULT;
52912 +            } else if (req.auth_alg == AUTH_ALG_OPEN_SYSTEM) {
52913 +                ar->arDot11AuthMode  = OPEN_AUTH;
52914 +                ar->arPairwiseCrypto  = NONE_CRYPT;
52915 +                ar->arGroupCrypto     = NONE_CRYPT;
52916 +            } else if (req.auth_alg == AUTH_ALG_LEAP) {
52917 +                ar->arDot11AuthMode   = LEAP_AUTH;
52918 +            } else {
52919 +                ret = -EIO;
52920 +            }
52921 +            break;
52922 +        }
52923 +
52924 +        case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
52925 +            ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
52926 +            break;
52927 +
52928 +        case AR6000_XIOCTL_SET_MAX_SP:
52929 +            ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
52930 +            break;
52931 +
52932 +        case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
52933 +            ret = ar6000_ioctl_get_roam_tbl(dev, rq);
52934 +            break;
52935 +        case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
52936 +            ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
52937 +            break;
52938 +        case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
52939 +            ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
52940 +            break;
52941 +        case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
52942 +            ret = ar6000_ioctl_get_power_mode(dev, rq);
52943 +            break;
52944 +        case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
52945 +            get_user(ar->arWlanState, (unsigned int *)userdata);
52946 +            if (ar->arWmiReady == FALSE) {
52947 +                ret = -EIO;
52948 +                break;
52949 +            }
52950 +
52951 +            if (ar->arWlanState == WLAN_ENABLED) {
52952 +                /* Enable foreground scanning */
52953 +                if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
52954 +                                       scParams.fg_end_period,
52955 +                                       scParams.bg_period,
52956 +                                       scParams.minact_chdwell_time,
52957 +                                       scParams.maxact_chdwell_time,
52958 +                                       scParams.pas_chdwell_time,
52959 +                                       scParams.shortScanRatio,
52960 +                                       scParams.scanCtrlFlags,
52961 +                                       scParams.max_dfsch_act_time) != A_OK)
52962 +                {
52963 +                    ret = -EIO;
52964 +                }
52965 +                if (ar->arSsidLen) {
52966 +                    ar->arConnectPending = TRUE;
52967 +                    if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
52968 +                                        ar->arDot11AuthMode, ar->arAuthMode,
52969 +                                        ar->arPairwiseCrypto,
52970 +                                        ar->arPairwiseCryptoLen,
52971 +                                        ar->arGroupCrypto, ar->arGroupCryptoLen,
52972 +                                        ar->arSsidLen, ar->arSsid,
52973 +                                        ar->arReqBssid, ar->arChannelHint,
52974 +                                        ar->arConnectCtrlFlags) != A_OK)
52975 +                    {
52976 +                        ret = -EIO;
52977 +                        ar->arConnectPending = FALSE;
52978 +                    }
52979 +                }
52980 +            } else {
52981 +                /* Disconnect from the AP and disable foreground scanning */
52982 +                AR6000_SPIN_LOCK(&ar->arLock, 0);
52983 +                if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
52984 +                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52985 +                    wmi_disconnect_cmd(ar->arWmi);
52986 +                } else {
52987 +                    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
52988 +                }
52989 +
52990 +                if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0xFF, 0) != A_OK)
52991 +                {
52992 +                    ret = -EIO;
52993 +                }
52994 +            }
52995 +            break;
52996 +        case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
52997 +            ret = ar6000_ioctl_get_roam_data(dev, rq);
52998 +            break;
52999 +        case AR6000_XIOCTL_WMI_SET_BT_STATUS:
53000 +            ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata);
53001 +            break;
53002 +        case AR6000_XIOCTL_WMI_SET_BT_PARAMS:
53003 +            ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata);
53004 +            break;
53005 +        case AR6000_XIOCTL_WMI_STARTSCAN:
53006 +        {
53007 +            WMI_START_SCAN_CMD setStartScanCmd;
53008 +
53009 +            if (ar->arWmiReady == FALSE) {
53010 +                    ret = -EIO;
53011 +                } else if (copy_from_user(&setStartScanCmd, userdata,
53012 +                                          sizeof(setStartScanCmd)))
53013 +                {
53014 +                    ret = -EFAULT;
53015 +                } else {
53016 +                    if (wmi_startscan_cmd(ar->arWmi, setStartScanCmd.scanType,
53017 +                                    setStartScanCmd.forceFgScan,
53018 +                                    setStartScanCmd.isLegacy,
53019 +                                    setStartScanCmd.homeDwellTime,
53020 +                                    setStartScanCmd.forceScanInterval) != A_OK)
53021 +                    {
53022 +                        ret = -EIO;
53023 +                    }
53024 +                }
53025 +            break;
53026 +        }
53027 +        case AR6000_XIOCTL_WMI_SETFIXRATES:
53028 +        {
53029 +            WMI_FIX_RATES_CMD setFixRatesCmd;
53030 +            A_STATUS returnStatus;
53031 +
53032 +            if (ar->arWmiReady == FALSE) {
53033 +                    ret = -EIO;
53034 +                } else if (copy_from_user(&setFixRatesCmd, userdata,
53035 +                                          sizeof(setFixRatesCmd)))
53036 +                {
53037 +                    ret = -EFAULT;
53038 +                } else {
53039 +                    returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask);
53040 +                    if (returnStatus == A_EINVAL)
53041 +                    {
53042 +                        ret = -EINVAL;
53043 +                    }
53044 +                    else if(returnStatus != A_OK) {
53045 +                        ret = -EIO;
53046 +                    }
53047 +                }
53048 +            break;
53049 +        }
53050 +
53051 +        case AR6000_XIOCTL_WMI_GETFIXRATES:
53052 +        {
53053 +            WMI_FIX_RATES_CMD getFixRatesCmd;
53054 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
53055 +            int ret = 0;
53056 +
53057 +            if (ar->arWmiReady == FALSE) {
53058 +                return -EIO;
53059 +            }
53060 +
53061 +            if (down_interruptible(&ar->arSem)) {
53062 +                return -ERESTARTSYS;
53063 +            }
53064 +            /* Used copy_from_user/copy_to_user to access user space data */
53065 +            if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) {
53066 +                ret = -EFAULT;
53067 +            } else {
53068 +                ar->arRateMask = 0xFFFF;
53069 +
53070 +                if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) {
53071 +                    up(&ar->arSem);
53072 +                    return -EIO;
53073 +                }
53074 +
53075 +                wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFF, wmitimeout * HZ);
53076 +
53077 +                if (signal_pending(current)) {
53078 +                    ret = -EINTR;
53079 +                }
53080 +
53081 +                if (!ret) {
53082 +                    getFixRatesCmd.fixRateMask = ar->arRateMask;
53083 +                }
53084 +
53085 +                if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) {
53086 +                   ret = -EFAULT;
53087 +                }
53088 +
53089 +                up(&ar->arSem);
53090 +            }
53091 +            break;
53092 +        }
53093 +        case AR6000_XIOCTL_WMI_SET_AUTHMODE:
53094 +        {
53095 +            WMI_SET_AUTH_MODE_CMD setAuthMode;
53096 +
53097 +            if (ar->arWmiReady == FALSE) {
53098 +                ret = -EIO;
53099 +            } else if (copy_from_user(&setAuthMode, userdata,
53100 +                                      sizeof(setAuthMode)))
53101 +            {
53102 +                ret = -EFAULT;
53103 +            } else {
53104 +                if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK)
53105 +                {
53106 +                    ret = -EIO;
53107 +                }
53108 +            }
53109 +            break;
53110 +        }
53111 +        case AR6000_XIOCTL_WMI_SET_REASSOCMODE:
53112 +        {
53113 +            WMI_SET_REASSOC_MODE_CMD setReassocMode;
53114 +
53115 +            if (ar->arWmiReady == FALSE) {
53116 +                ret = -EIO;
53117 +            } else if (copy_from_user(&setReassocMode, userdata,
53118 +                                      sizeof(setReassocMode)))
53119 +            {
53120 +                ret = -EFAULT;
53121 +            } else {
53122 +                if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK)
53123 +                {
53124 +                    ret = -EIO;
53125 +                }
53126 +            }
53127 +            break;
53128 +        }
53129 +        case AR6000_XIOCTL_DIAG_READ:
53130 +        {
53131 +            A_UINT32 addr, data;
53132 +            get_user(addr, (unsigned int *)userdata);
53133 +            if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
53134 +                ret = -EIO;
53135 +            }
53136 +            put_user(data, (unsigned int *)userdata + 1);
53137 +            break;
53138 +        }
53139 +        case AR6000_XIOCTL_DIAG_WRITE:
53140 +        {
53141 +            A_UINT32 addr, data;
53142 +            get_user(addr, (unsigned int *)userdata);
53143 +            get_user(data, (unsigned int *)userdata + 1);
53144 +            if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
53145 +                ret = -EIO;
53146 +            }
53147 +            break;
53148 +        }
53149 +        case AR6000_XIOCTL_WMI_SET_KEEPALIVE:
53150 +        {
53151 +             WMI_SET_KEEPALIVE_CMD setKeepAlive;
53152 +             if (ar->arWmiReady == FALSE) {
53153 +                 return -EIO;
53154 +             } else if (copy_from_user(&setKeepAlive, userdata,
53155 +                        sizeof(setKeepAlive))){
53156 +                 ret = -EFAULT;
53157 +             } else {
53158 +                 if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) {
53159 +                     ret = -EIO;
53160 +               }
53161 +             }
53162 +             break;
53163 +        }
53164 +        case AR6000_XIOCTL_WMI_GET_KEEPALIVE:
53165 +        {
53166 +            AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
53167 +            WMI_GET_KEEPALIVE_CMD getKeepAlive;
53168 +            int ret = 0;
53169 +            if (ar->arWmiReady == FALSE) {
53170 +               return -EIO;
53171 +            }
53172 +            if (down_interruptible(&ar->arSem)) {
53173 +                return -ERESTARTSYS;
53174 +            }
53175 +            if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) {
53176 +               ret = -EFAULT;
53177 +            } else {
53178 +            getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi);
53179 +            ar->arKeepaliveConfigured = 0xFF;
53180 +            if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){
53181 +                up(&ar->arSem);
53182 +                return -EIO;
53183 +            }
53184 +            wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ);
53185 +            if (signal_pending(current)) {
53186 +                ret = -EINTR;
53187 +            }
53188 +
53189 +            if (!ret) {
53190 +                getKeepAlive.configured = ar->arKeepaliveConfigured;
53191 +            }
53192 +            if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) {
53193 +               ret = -EFAULT;
53194 +            }
53195 +            up(&ar->arSem);
53196 +            }
53197 +            break;
53198 +        }
53199 +        case AR6000_XIOCTL_WMI_SET_APPIE:
53200 +        {
53201 +            WMI_SET_APPIE_CMD appIEcmd;
53202 +            A_UINT8           appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN];
53203 +            A_UINT32            fType,ieLen;
53204 +
53205 +           if (ar->arWmiReady == FALSE) {
53206 +                   return -EIO;
53207 +           }
53208 +           get_user(fType, (A_UINT32 *)userdata);
53209 +           appIEcmd.mgmtFrmType = fType;
53210 +           if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) {
53211 +                   ret = -EIO;
53212 +           } else {
53213 +                   get_user(ieLen, (A_UINT32 *)(userdata + 4));
53214 +                   appIEcmd.ieLen = ieLen;
53215 +                   if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) {
53216 +                           ret = -EIO;
53217 +                           break;
53218 +                   }
53219 +                   if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) {
53220 +                           ret = -EFAULT;
53221 +                   } else {
53222 +                           if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType,
53223 +                                                 appIEcmd.ieLen,  appIeInfo) != A_OK)
53224 +                           {
53225 +                                   ret = -EIO;
53226 +                           }
53227 +                   }
53228 +            }
53229 +            break;
53230 +        }
53231 +        case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER:
53232 +        {
53233 +            WMI_BSS_FILTER_CMD cmd;
53234 +            A_UINT32    filterType;
53235 +
53236 +            if (copy_from_user(&filterType, userdata, sizeof(A_UINT32)))
53237 +            {
53238 +                return -EFAULT;
53239 +            }
53240 +            if (filterType & (IEEE80211_FILTER_TYPE_BEACON |
53241 +                                    IEEE80211_FILTER_TYPE_PROBE_RESP))
53242 +            {
53243 +                cmd.bssFilter = ALL_BSS_FILTER;
53244 +            } else {
53245 +                cmd.bssFilter = NONE_BSS_FILTER;
53246 +            }
53247 +            if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) {
53248 +                ret = -EIO;
53249 +            }
53250 +
53251 +            AR6000_SPIN_LOCK(&ar->arLock, 0);
53252 +            ar->arMgmtFilter = filterType;
53253 +            AR6000_SPIN_UNLOCK(&ar->arLock, 0);
53254 +            break;
53255 +        }
53256 +        case AR6000_XIOCTL_WMI_SET_WSC_STATUS:
53257 +        {
53258 +            A_UINT32    wsc_status;
53259 +
53260 +            if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32)))
53261 +            {
53262 +                return -EFAULT;
53263 +            }
53264 +            if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) {
53265 +                ret = -EIO;
53266 +            }
53267 +            break;
53268 +        }
53269 +        case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL:
53270 +        {
53271 +            A_UINT32 ROM_addr;
53272 +            A_UINT32 RAM_addr;
53273 +            A_UINT32 nbytes;
53274 +            A_UINT32 do_activate;
53275 +            A_UINT32 rompatch_id;
53276 +
53277 +            get_user(ROM_addr, (A_UINT32 *)userdata);
53278 +            get_user(RAM_addr, (A_UINT32 *)userdata + 1);
53279 +            get_user(nbytes, (A_UINT32 *)userdata + 2);
53280 +            get_user(do_activate, (A_UINT32 *)userdata + 3);
53281 +            AR_DEBUG_PRINTF("Install rompatch from ROM: 0x%x to RAM: 0x%x  length: %d\n",
53282 +                             ROM_addr, RAM_addr, nbytes);
53283 +            ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr,
53284 +                                        nbytes, do_activate, &rompatch_id);
53285 +            if (ret == A_OK) {
53286 +                put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */
53287 +            }
53288 +            break;
53289 +        }
53290 +
53291 +        case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL:
53292 +        {
53293 +            A_UINT32 rompatch_id;
53294 +
53295 +            get_user(rompatch_id, (A_UINT32 *)userdata);
53296 +            AR_DEBUG_PRINTF("UNinstall rompatch_id %d\n", rompatch_id);
53297 +            ret = BMIrompatchUninstall(hifDevice, rompatch_id);
53298 +            break;
53299 +        }
53300 +
53301 +        case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE:
53302 +        case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE:
53303 +        {
53304 +            A_UINT32 rompatch_count;
53305 +
53306 +            get_user(rompatch_count, (A_UINT32 *)userdata);
53307 +            AR_DEBUG_PRINTF("Change rompatch activation count=%d\n", rompatch_count);
53308 +            length = sizeof(A_UINT32) * rompatch_count;
53309 +            if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
53310 +                A_MEMZERO(buffer, length);
53311 +                if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length))
53312 +                {
53313 +                    ret = -EFAULT;
53314 +                } else {
53315 +                    if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) {
53316 +                        ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
53317 +                    } else {
53318 +                        ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
53319 +                    }
53320 +                }
53321 +                A_FREE(buffer);
53322 +            } else {
53323 +                ret = -ENOMEM;
53324 +            }
53325 +
53326 +            break;
53327 +        }
53328 +
53329 +        case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE:
53330 +        {
53331 +            WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode;
53332 +
53333 +            if (ar->arWmiReady == FALSE) {
53334 +                ret = -EIO;
53335 +            } else if (copy_from_user(&setHostSleepMode, userdata,
53336 +                                      sizeof(setHostSleepMode)))
53337 +            {
53338 +                ret = -EFAULT;
53339 +            } else {
53340 +                if (wmi_set_host_sleep_mode_cmd(ar->arWmi,
53341 +                                &setHostSleepMode) != A_OK)
53342 +                {
53343 +                    ret = -EIO;
53344 +                }
53345 +            }
53346 +            break;
53347 +        }
53348 +        case AR6000_XIOCTL_WMI_SET_WOW_MODE:
53349 +        {
53350 +            WMI_SET_WOW_MODE_CMD setWowMode;
53351 +
53352 +            if (ar->arWmiReady == FALSE) {
53353 +                ret = -EIO;
53354 +            } else if (copy_from_user(&setWowMode, userdata,
53355 +                                      sizeof(setWowMode)))
53356 +            {
53357 +                ret = -EFAULT;
53358 +            } else {
53359 +                if (wmi_set_wow_mode_cmd(ar->arWmi,
53360 +                                &setWowMode) != A_OK)
53361 +                {
53362 +                    ret = -EIO;
53363 +                }
53364 +            }
53365 +            break;
53366 +        }
53367 +        case AR6000_XIOCTL_WMI_GET_WOW_LIST:
53368 +        {
53369 +            WMI_GET_WOW_LIST_CMD getWowList;
53370 +
53371 +            if (ar->arWmiReady == FALSE) {
53372 +                ret = -EIO;
53373 +            } else if (copy_from_user(&getWowList, userdata,
53374 +                                      sizeof(getWowList)))
53375 +            {
53376 +                ret = -EFAULT;
53377 +            } else {
53378 +                if (wmi_get_wow_list_cmd(ar->arWmi,
53379 +                                &getWowList) != A_OK)
53380 +                {
53381 +                    ret = -EIO;
53382 +                }
53383 +            }
53384 +            break;
53385 +        }
53386 +        case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN:
53387 +        {
53388 +#define WOW_PATTERN_SIZE 64
53389 +#define WOW_MASK_SIZE 64
53390 +
53391 +            WMI_ADD_WOW_PATTERN_CMD cmd;
53392 +            A_UINT8 mask_data[WOW_PATTERN_SIZE]={0};
53393 +            A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0};
53394 +
53395 +            if (ar->arWmiReady == FALSE) {
53396 +                ret = -EIO;
53397 +            } else {
53398 +
53399 +                if(copy_from_user(&cmd, userdata,
53400 +                            sizeof(WMI_ADD_WOW_PATTERN_CMD)))
53401 +                      return -EFAULT;
53402 +                if (copy_from_user(pattern_data,
53403 +                                      userdata + 3,
53404 +                                      cmd.filter_size)){
53405 +                        ret = -EFAULT;
53406 +                        break;
53407 +                }
53408 +                if (copy_from_user(mask_data,
53409 +                                      (userdata + 3 + cmd.filter_size),
53410 +                                      cmd.filter_size)){
53411 +                        ret = -EFAULT;
53412 +                        break;
53413 +                } else {
53414 +                    if (wmi_add_wow_pattern_cmd(ar->arWmi,
53415 +                                &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK){
53416 +                        ret = -EIO;
53417 +                    }
53418 +                }
53419 +            }
53420 +#undef WOW_PATTERN_SIZE
53421 +#undef WOW_MASK_SIZE
53422 +            break;
53423 +        }
53424 +        case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN:
53425 +        {
53426 +            WMI_DEL_WOW_PATTERN_CMD delWowPattern;
53427 +
53428 +            if (ar->arWmiReady == FALSE) {
53429 +                ret = -EIO;
53430 +            } else if (copy_from_user(&delWowPattern, userdata,
53431 +                                      sizeof(delWowPattern)))
53432 +            {
53433 +                ret = -EFAULT;
53434 +            } else {
53435 +                if (wmi_del_wow_pattern_cmd(ar->arWmi,
53436 +                                &delWowPattern) != A_OK)
53437 +                {
53438 +                    ret = -EIO;
53439 +                }
53440 +            }
53441 +            break;
53442 +        }
53443 +        case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE:
53444 +            if (ar->arHtcTarget != NULL) {
53445 +                HTCDumpCreditStates(ar->arHtcTarget);
53446 +            }
53447 +            break;
53448 +        case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE:
53449 +            if (ar->arHtcTarget != NULL) {
53450 +                struct ar6000_traffic_activity_change data;
53451 +
53452 +                if (copy_from_user(&data, userdata, sizeof(data)))
53453 +                {
53454 +                    return -EFAULT;
53455 +                }
53456 +                    /* note, this is used for testing (mbox ping testing), indicate activity
53457 +                     * change using the stream ID as the traffic class */
53458 +                ar6000_indicate_tx_activity(ar,
53459 +                                            (A_UINT8)data.StreamID,
53460 +                                            data.Active ? TRUE : FALSE);
53461 +            }
53462 +            break;
53463 +        case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS:
53464 +            if (ar->arWmiReady == FALSE) {
53465 +                ret = -EIO;
53466 +            } else if (copy_from_user(&connectCtrlFlags, userdata,
53467 +                                      sizeof(connectCtrlFlags)))
53468 +            {
53469 +                ret = -EFAULT;
53470 +            } else {
53471 +                ar->arConnectCtrlFlags = connectCtrlFlags;
53472 +            }
53473 +            break;
53474 +        case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS:
53475 +            if (ar->arWmiReady == FALSE) {
53476 +                ret = -EIO;
53477 +            } else if (copy_from_user(&akmpParams, userdata,
53478 +                                      sizeof(WMI_SET_AKMP_PARAMS_CMD)))
53479 +            {
53480 +                ret = -EFAULT;
53481 +            } else {
53482 +                if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) {
53483 +                    ret = -EIO;
53484 +                }
53485 +            }
53486 +            break;
53487 +        case AR6000_XIOCTL_WMI_SET_PMKID_LIST:
53488 +            if (ar->arWmiReady == FALSE) {
53489 +                ret = -EIO;
53490 +            } else {
53491 +                if (copy_from_user(&pmkidInfo.numPMKID, userdata,
53492 +                                      sizeof(pmkidInfo.numPMKID)))
53493 +                {
53494 +                    ret = -EFAULT;
53495 +                    break;
53496 +                }
53497 +                if (copy_from_user(&pmkidInfo.pmkidList,
53498 +                                   userdata + sizeof(pmkidInfo.numPMKID),
53499 +                                   pmkidInfo.numPMKID * sizeof(WMI_PMKID)))
53500 +                {
53501 +                    ret = -EFAULT;
53502 +                    break;
53503 +                }
53504 +                if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) {
53505 +                    ret = -EIO;
53506 +                }
53507 +            }
53508 +            break;
53509 +        case AR6000_XIOCTL_WMI_GET_PMKID_LIST:
53510 +            if (ar->arWmiReady == FALSE) {
53511 +                ret = -EIO;
53512 +            } else  {
53513 +                if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) {
53514 +                    ret = -EIO;
53515 +                }
53516 +            }
53517 +            break;
53518 +        default:
53519 +            ret = -EOPNOTSUPP;
53520 +    }
53521 +    return ret;
53522 +}
53523 +
53524 Index: linux-2.6.28/drivers/ar6000/ar6000/netbuf.c
53525 ===================================================================
53526 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
53527 +++ linux-2.6.28/drivers/ar6000/ar6000/netbuf.c 2009-01-02 00:01:56.000000000 +0100
53528 @@ -0,0 +1,225 @@
53529 +
53530 +/*
53531 + *
53532 + * Copyright (c) 2004-2007 Atheros Communications Inc.
53533 + * All rights reserved.
53534 + *
53535 + *
53536 + *  This program is free software; you can redistribute it and/or modify
53537 + *  it under the terms of the GNU General Public License version 2 as
53538 + *  published by the Free Software Foundation;
53539 + *
53540 + *  Software distributed under the License is distributed on an "AS
53541 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
53542 + *  implied. See the License for the specific language governing
53543 + *  rights and limitations under the License.
53544 + *
53545 + *
53546 + *
53547 + */
53548 +#include <linux/kernel.h>
53549 +#include <linux/skbuff.h>
53550 +#include <a_config.h>
53551 +#include "athdefs.h"
53552 +#include "a_types.h"
53553 +#include "a_osapi.h"
53554 +#include "htc_packet.h"
53555 +
53556 +#define AR6000_DATA_OFFSET    64
53557 +
53558 +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt)
53559 +{
53560 +    skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt);
53561 +}
53562 +
53563 +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt)
53564 +{
53565 +    skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt);
53566 +}
53567 +
53568 +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q)
53569 +{
53570 +    return((void *) skb_dequeue((struct sk_buff_head *) q));
53571 +}
53572 +
53573 +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q)
53574 +{
53575 +    return(skb_queue_len((struct sk_buff_head *) q));
53576 +}
53577 +
53578 +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q)
53579 +{
53580 +    return(skb_queue_empty((struct sk_buff_head *) q));
53581 +}
53582 +
53583 +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q)
53584 +{
53585 +    skb_queue_head_init((struct sk_buff_head *) q);
53586 +}
53587 +
53588 +void *
53589 +a_netbuf_alloc(int size)
53590 +{
53591 +    struct sk_buff *skb;
53592 +    skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size);
53593 +    skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET));
53594 +    return ((void *)skb);
53595 +}
53596 +
53597 +/*
53598 + * Allocate an SKB w.o. any encapsulation requirement.
53599 + */
53600 +void *
53601 +a_netbuf_alloc_raw(int size)
53602 +{
53603 +    struct sk_buff *skb;
53604 +
53605 +    skb = dev_alloc_skb(size);
53606 +
53607 +    return ((void *)skb);
53608 +}
53609 +
53610 +void
53611 +a_netbuf_free(void *bufPtr)
53612 +{
53613 +    struct sk_buff *skb = (struct sk_buff *)bufPtr;
53614 +
53615 +    dev_kfree_skb(skb);
53616 +}
53617 +
53618 +A_UINT32
53619 +a_netbuf_to_len(void *bufPtr)
53620 +{
53621 +    return (((struct sk_buff *)bufPtr)->len);
53622 +}
53623 +
53624 +void *
53625 +a_netbuf_to_data(void *bufPtr)
53626 +{
53627 +    return (((struct sk_buff *)bufPtr)->data);
53628 +}
53629 +
53630 +/*
53631 + * Add len # of bytes to the beginning of the network buffer
53632 + * pointed to by bufPtr
53633 + */
53634 +A_STATUS
53635 +a_netbuf_push(void *bufPtr, A_INT32 len)
53636 +{
53637 +    skb_push((struct sk_buff *)bufPtr, len);
53638 +
53639 +    return A_OK;
53640 +}
53641 +
53642 +/*
53643 + * Add len # of bytes to the beginning of the network buffer
53644 + * pointed to by bufPtr and also fill with data
53645 + */
53646 +A_STATUS
53647 +a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len)
53648 +{
53649 +    skb_push((struct sk_buff *) bufPtr, len);
53650 +    A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len);
53651 +
53652 +    return A_OK;
53653 +}
53654 +
53655 +/*
53656 + * Add len # of bytes to the end of the network buffer
53657 + * pointed to by bufPtr
53658 + */
53659 +A_STATUS
53660 +a_netbuf_put(void *bufPtr, A_INT32 len)
53661 +{
53662 +    skb_put((struct sk_buff *)bufPtr, len);
53663 +
53664 +    return A_OK;
53665 +}
53666 +
53667 +/*
53668 + * Add len # of bytes to the end of the network buffer
53669 + * pointed to by bufPtr and also fill with data
53670 + */
53671 +A_STATUS
53672 +a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len)
53673 +{
53674 +    char *start = ((struct sk_buff *)bufPtr)->data +
53675 +        ((struct sk_buff *)bufPtr)->len;
53676 +    skb_put((struct sk_buff *)bufPtr, len);
53677 +    A_MEMCPY(start, srcPtr, len);
53678 +
53679 +    return A_OK;
53680 +}
53681 +
53682 +
53683 +/*
53684 + * Trim the network buffer pointed to by bufPtr to len # of bytes
53685 + */
53686 +A_STATUS
53687 +a_netbuf_setlen(void *bufPtr, A_INT32 len)
53688 +{
53689 +    skb_trim((struct sk_buff *)bufPtr, len);
53690 +
53691 +    return A_OK;
53692 +}
53693 +
53694 +/*
53695 + * Chop of len # of bytes from the end of the buffer.
53696 + */
53697 +A_STATUS
53698 +a_netbuf_trim(void *bufPtr, A_INT32 len)
53699 +{
53700 +    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
53701 +
53702 +    return A_OK;
53703 +}
53704 +
53705 +/*
53706 + * Chop of len # of bytes from the end of the buffer and return the data.
53707 + */
53708 +A_STATUS
53709 +a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len)
53710 +{
53711 +    char *start = ((struct sk_buff *)bufPtr)->data +
53712 +        (((struct sk_buff *)bufPtr)->len - len);
53713 +
53714 +    A_MEMCPY(dstPtr, start, len);
53715 +    skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
53716 +
53717 +    return A_OK;
53718 +}
53719 +
53720 +
53721 +/*
53722 + * Returns the number of bytes available to a a_netbuf_push()
53723 + */
53724 +A_INT32
53725 +a_netbuf_headroom(void *bufPtr)
53726 +{
53727 +    return (skb_headroom((struct sk_buff *)bufPtr));
53728 +}
53729 +
53730 +/*
53731 + * Removes specified number of bytes from the beginning of the buffer
53732 + */
53733 +A_STATUS
53734 +a_netbuf_pull(void *bufPtr, A_INT32 len)
53735 +{
53736 +    skb_pull((struct sk_buff *)bufPtr, len);
53737 +
53738 +    return A_OK;
53739 +}
53740 +
53741 +/*
53742 + * Removes specified number of bytes from the beginning of the buffer
53743 + * and return the data
53744 + */
53745 +A_STATUS
53746 +a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len)
53747 +{
53748 +    A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len);
53749 +    skb_pull((struct sk_buff *)bufPtr, len);
53750 +
53751 +    return A_OK;
53752 +}
53753 +
53754 Index: linux-2.6.28/drivers/ar6000/ar6000/osapi_linux.h
53755 ===================================================================
53756 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
53757 +++ linux-2.6.28/drivers/ar6000/ar6000/osapi_linux.h    2009-01-02 00:01:56.000000000 +0100
53758 @@ -0,0 +1,319 @@
53759 +/*
53760 + * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/osapi_linux.h#1 $
53761 + *
53762 + * This file contains the definitions of the basic atheros data types.
53763 + * It is used to map the data types in atheros files to a platform specific
53764 + * type.
53765 + *
53766 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
53767 + *
53768 + *
53769 + *  This program is free software; you can redistribute it and/or modify
53770 + *  it under the terms of the GNU General Public License version 2 as
53771 + *  published by the Free Software Foundation;
53772 + *
53773 + *  Software distributed under the License is distributed on an "AS
53774 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
53775 + *  implied. See the License for the specific language governing
53776 + *  rights and limitations under the License.
53777 + *
53778 + *
53779 + *
53780 + */
53781 +
53782 +#ifndef _OSAPI_LINUX_H_
53783 +#define _OSAPI_LINUX_H_
53784 +
53785 +#ifdef __KERNEL__
53786 +
53787 +#include <linux/version.h>
53788 +#include <linux/types.h>
53789 +#include <linux/kernel.h>
53790 +#include <linux/string.h>
53791 +#include <linux/skbuff.h>
53792 +#include <linux/netdevice.h>
53793 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
53794 +#include <linux/jiffies.h>
53795 +#endif
53796 +#include <linux/timer.h>
53797 +#include <linux/delay.h>
53798 +#include <linux/wait.h>
53799 +#ifdef KERNEL_2_4
53800 +#include <asm/arch/irq.h>
53801 +#include <asm/irq.h>
53802 +#endif
53803 +
53804 +#ifdef __GNUC__
53805 +#define __ATTRIB_PACK           __attribute__ ((packed))
53806 +#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
53807 +#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
53808 +#ifndef INLINE
53809 +#define INLINE                  __inline__
53810 +#endif
53811 +#else /* Not GCC */
53812 +#define __ATTRIB_PACK
53813 +#define __ATTRIB_PRINTF
53814 +#define __ATTRIB_NORETURN
53815 +#ifndef INLINE
53816 +#define INLINE                  __inline
53817 +#endif
53818 +#endif /* End __GNUC__ */
53819 +
53820 +#define PREPACK
53821 +#define POSTPACK                __ATTRIB_PACK
53822 +
53823 +/*
53824 + * Endianes macros
53825 + */
53826 +#define A_BE2CPU8(x)       ntohb(x)
53827 +#define A_BE2CPU16(x)      ntohs(x)
53828 +#define A_BE2CPU32(x)      ntohl(x)
53829 +
53830 +#define A_LE2CPU8(x)       (x)
53831 +#define A_LE2CPU16(x)      (x)
53832 +#define A_LE2CPU32(x)      (x)
53833 +
53834 +#define A_CPU2BE8(x)       htonb(x)
53835 +#define A_CPU2BE16(x)      htons(x)
53836 +#define A_CPU2BE32(x)      htonl(x)
53837 +
53838 +#define A_MEMCPY(dst, src, len)         memcpy((A_UINT8 *)(dst), (src), (len))
53839 +#define A_MEMZERO(addr, len)            memset(addr, 0, len)
53840 +#define A_MEMCMP(addr1, addr2, len)     memcmp((addr1), (addr2), (len))
53841 +#define A_MALLOC(size)                  kmalloc((size), GFP_KERNEL)
53842 +#define A_MALLOC_NOWAIT(size)           kmalloc((size), GFP_ATOMIC)
53843 +#define A_FREE(addr)                    kfree(addr)
53844 +#define A_PRINTF(args...)               printk(args)
53845 +
53846 +/* Mutual Exclusion */
53847 +typedef spinlock_t                      A_MUTEX_T;
53848 +#define A_MUTEX_INIT(mutex)             spin_lock_init(mutex)
53849 +#define A_MUTEX_LOCK(mutex)             spin_lock_bh(mutex)
53850 +#define A_MUTEX_UNLOCK(mutex)           spin_unlock_bh(mutex)
53851 +#define A_IS_MUTEX_VALID(mutex)         TRUE  /* okay to return true, since A_MUTEX_DELETE does nothing */
53852 +#define A_MUTEX_DELETE(mutex)           /* spin locks are not kernel resources so nothing to free.. */
53853 +
53854 +/* Get current time in ms adding a constant offset (in ms) */
53855 +#define A_GET_MS(offset)    \
53856 +       (jiffies + ((offset) / 1000) * HZ)
53857 +
53858 +/*
53859 + * Timer Functions
53860 + */
53861 +#define A_MDELAY(msecs)                 mdelay(msecs)
53862 +typedef struct timer_list               A_TIMER;
53863 +
53864 +#define A_INIT_TIMER(pTimer, pFunction, pArg) do {              \
53865 +    init_timer(pTimer);                                         \
53866 +    (pTimer)->function = (pFunction);                           \
53867 +    (pTimer)->data   = (unsigned long)(pArg);                   \
53868 +} while (0)
53869 +
53870 +/*
53871 + * Start a Timer that elapses after 'periodMSec' milli-seconds
53872 + * Support is provided for a one-shot timer. The 'repeatFlag' is
53873 + * ignored.
53874 + */
53875 +#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do {                   \
53876 +    if (repeatFlag) {                                                       \
53877 +        printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__);     \
53878 +        panic("Timer Repeat");                                              \
53879 +    }                                                                       \
53880 +    mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000);                \
53881 +} while (0)
53882 +
53883 +/*
53884 + * Cancel the Timer.
53885 + */
53886 +#define A_UNTIMEOUT(pTimer) do {                                \
53887 +    del_timer((pTimer));                                        \
53888 +} while (0)
53889 +
53890 +#define A_DELETE_TIMER(pTimer) do {                             \
53891 +} while (0)
53892 +
53893 +/*
53894 + * Wait Queue related functions
53895 + */
53896 +typedef wait_queue_head_t               A_WAITQUEUE_HEAD;
53897 +#define A_INIT_WAITQUEUE_HEAD(head)     init_waitqueue_head(head)
53898 +#ifndef wait_event_interruptible_timeout
53899 +#define __wait_event_interruptible_timeout(wq, condition, ret)          \
53900 +do {                                                                    \
53901 +        wait_queue_t __wait;                                            \
53902 +        init_waitqueue_entry(&__wait, current);                         \
53903 +                                                                        \
53904 +        add_wait_queue(&wq, &__wait);                                   \
53905 +        for (;;) {                                                      \
53906 +                set_current_state(TASK_INTERRUPTIBLE);                  \
53907 +                if (condition)                                          \
53908 +                        break;                                          \
53909 +                if (!signal_pending(current)) {                         \
53910 +                        ret = schedule_timeout(ret);                    \
53911 +                        if (!ret)                                       \
53912 +                                break;                                  \
53913 +                        continue;                                       \
53914 +                }                                                       \
53915 +                ret = -ERESTARTSYS;                                     \
53916 +                break;                                                  \
53917 +        }                                                               \
53918 +        current->state = TASK_RUNNING;                                  \
53919 +        remove_wait_queue(&wq, &__wait);                                \
53920 +} while (0)
53921 +
53922 +#define wait_event_interruptible_timeout(wq, condition, timeout)        \
53923 +({                                                                      \
53924 +        long __ret = timeout;                                           \
53925 +        if (!(condition))                                               \
53926 +                __wait_event_interruptible_timeout(wq, condition, __ret); \
53927 +        __ret;                                                          \
53928 +})
53929 +#endif /* wait_event_interruptible_timeout */
53930 +
53931 +#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
53932 +    wait_event_interruptible_timeout(head, condition, timeout); \
53933 +} while (0)
53934 +
53935 +#define A_WAKE_UP(head)                 wake_up(head)
53936 +
53937 +#ifdef DEBUG
53938 +#define A_ASSERT(expr)  \
53939 +    if (!(expr)) {   \
53940 +        printk(KERN_ALERT "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
53941 +        panic(#expr); \
53942 +    }
53943 +
53944 +#else
53945 +#define A_ASSERT(expr)
53946 +#endif /* DEBUG */
53947 +
53948 +/*
53949 + * Initialization of the network buffer subsystem
53950 + */
53951 +#define A_NETBUF_INIT()
53952 +
53953 +/*
53954 + * Network buffer queue support
53955 + */
53956 +typedef struct sk_buff_head A_NETBUF_QUEUE_T;
53957 +
53958 +#define A_NETBUF_QUEUE_INIT(q)  \
53959 +    a_netbuf_queue_init(q)
53960 +
53961 +#define A_NETBUF_ENQUEUE(q, pkt) \
53962 +    a_netbuf_enqueue((q), (pkt))
53963 +#define A_NETBUF_PREQUEUE(q, pkt) \
53964 +    a_netbuf_prequeue((q), (pkt))
53965 +#define A_NETBUF_DEQUEUE(q) \
53966 +    (a_netbuf_dequeue(q))
53967 +#define A_NETBUF_QUEUE_SIZE(q)  \
53968 +    a_netbuf_queue_size(q)
53969 +#define A_NETBUF_QUEUE_EMPTY(q) \
53970 +    a_netbuf_queue_empty(q)
53971 +
53972 +/*
53973 + * Network buffer support
53974 + */
53975 +#define A_NETBUF_ALLOC(size) \
53976 +    a_netbuf_alloc(size)
53977 +#define A_NETBUF_ALLOC_RAW(size) \
53978 +    a_netbuf_alloc_raw(size)
53979 +#define A_NETBUF_FREE(bufPtr) \
53980 +    a_netbuf_free(bufPtr)
53981 +#define A_NETBUF_DATA(bufPtr) \
53982 +    a_netbuf_to_data(bufPtr)
53983 +#define A_NETBUF_LEN(bufPtr) \
53984 +    a_netbuf_to_len(bufPtr)
53985 +#define A_NETBUF_PUSH(bufPtr, len) \
53986 +    a_netbuf_push(bufPtr, len)
53987 +#define A_NETBUF_PUT(bufPtr, len) \
53988 +    a_netbuf_put(bufPtr, len)
53989 +#define A_NETBUF_TRIM(bufPtr,len) \
53990 +    a_netbuf_trim(bufPtr, len)
53991 +#define A_NETBUF_PULL(bufPtr, len) \
53992 +    a_netbuf_pull(bufPtr, len)
53993 +#define A_NETBUF_HEADROOM(bufPtr)\
53994 +    a_netbuf_headroom(bufPtr)
53995 +#define A_NETBUF_SETLEN(bufPtr,len) \
53996 +    a_netbuf_setlen(bufPtr, len)
53997 +
53998 +/* Add data to end of a buffer  */
53999 +#define A_NETBUF_PUT_DATA(bufPtr, srcPtr,  len) \
54000 +    a_netbuf_put_data(bufPtr, srcPtr, len)
54001 +
54002 +/* Add data to start of the  buffer */
54003 +#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr,  len) \
54004 +    a_netbuf_push_data(bufPtr, srcPtr, len)
54005 +
54006 +/* Remove data at start of the buffer */
54007 +#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \
54008 +    a_netbuf_pull_data(bufPtr, dstPtr, len)
54009 +
54010 +/* Remove data from the end of the buffer */
54011 +#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \
54012 +    a_netbuf_trim_data(bufPtr, dstPtr, len)
54013 +
54014 +/* View data as "size" contiguous bytes of type "t" */
54015 +#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \
54016 +    (t )( ((struct skbuf *)(bufPtr))->data)
54017 +
54018 +/* return the beginning of the headroom for the buffer */
54019 +#define A_NETBUF_HEAD(bufPtr) \
54020 +        ((((struct sk_buff *)(bufPtr))->head))
54021 +
54022 +/*
54023 + * OS specific network buffer access routines
54024 + */
54025 +void *a_netbuf_alloc(int size);
54026 +void *a_netbuf_alloc_raw(int size);
54027 +void a_netbuf_free(void *bufPtr);
54028 +void *a_netbuf_to_data(void *bufPtr);
54029 +A_UINT32 a_netbuf_to_len(void *bufPtr);
54030 +A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len);
54031 +A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len);
54032 +A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len);
54033 +A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len);
54034 +A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len);
54035 +A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len);
54036 +A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len);
54037 +A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len);
54038 +A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len);
54039 +A_INT32 a_netbuf_headroom(void *bufPtr);
54040 +void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt);
54041 +void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt);
54042 +void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q);
54043 +int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q);
54044 +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
54045 +int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
54046 +void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q);
54047 +
54048 +/*
54049 + * Kernel v.s User space functions
54050 + */
54051 +A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n);
54052 +A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n);
54053 +
54054 +#else /* __KERNEL__ */
54055 +
54056 +#ifdef __GNUC__
54057 +#define __ATTRIB_PACK           __attribute__ ((packed))
54058 +#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
54059 +#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
54060 +#ifndef INLINE
54061 +#define INLINE                  __inline__
54062 +#endif
54063 +#else /* Not GCC */
54064 +#define __ATTRIB_PACK
54065 +#define __ATTRIB_PRINTF
54066 +#define __ATTRIB_NORETURN
54067 +#ifndef INLINE
54068 +#define INLINE                  __inline
54069 +#endif
54070 +#endif /* End __GNUC__ */
54071 +
54072 +#define PREPACK
54073 +#define POSTPACK                __ATTRIB_PACK
54074 +
54075 +#endif /* __KERNEL__ */
54076 +
54077 +#endif /* _OSAPI_LINUX_H_ */
54078 Index: linux-2.6.28/drivers/ar6000/ar6000/wireless_ext.c
54079 ===================================================================
54080 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
54081 +++ linux-2.6.28/drivers/ar6000/ar6000/wireless_ext.c   2009-01-02 00:01:56.000000000 +0100
54082 @@ -0,0 +1,1972 @@
54083 +/*
54084 + *
54085 + * Copyright (c) 2004-2007 Atheros Communications Inc.
54086 + * All rights reserved.
54087 + *
54088 + *
54089 + *  This program is free software; you can redistribute it and/or modify
54090 + *  it under the terms of the GNU General Public License version 2 as
54091 + *  published by the Free Software Foundation;
54092 + *
54093 + *  Software distributed under the License is distributed on an "AS
54094 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
54095 + *  implied. See the License for the specific language governing
54096 + *  rights and limitations under the License.
54097 + *
54098 + *
54099 + *
54100 + */
54101 +
54102 +#include "ar6000_drv.h"
54103 +
54104 +static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
54105 +static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi);
54106 +extern unsigned int wmitimeout;
54107 +extern A_WAITQUEUE_HEAD arEvent;
54108 +extern wait_queue_head_t ar6000_scan_queue;
54109 +
54110 +/*
54111 + * Encode a WPA or RSN information element as a custom
54112 + * element using the hostap format.
54113 + */
54114 +static u_int
54115 +encode_ie(void *buf, size_t bufsize,
54116 +    const u_int8_t *ie, size_t ielen,
54117 +    const char *leader, size_t leader_len)
54118 +{
54119 +    u_int8_t *p;
54120 +    int i;
54121 +
54122 +    if (bufsize < leader_len)
54123 +        return 0;
54124 +    p = buf;
54125 +    memcpy(p, leader, leader_len);
54126 +    bufsize -= leader_len;
54127 +    p += leader_len;
54128 +    for (i = 0; i < ielen && bufsize > 2; i++)
54129 +        p += sprintf(p, "%02x", ie[i]);
54130 +    return (i == ielen ? p - (u_int8_t *)buf : 0);
54131 +}
54132 +
54133 +void
54134 +ar6000_scan_node(void *arg, bss_t *ni)
54135 +{
54136 +    struct iw_event iwe;
54137 +#if WIRELESS_EXT > 14
54138 +    char buf[64*2 + 30];
54139 +#endif
54140 +    struct ar_giwscan_param *param;
54141 +    A_CHAR *current_ev;
54142 +    A_CHAR *end_buf;
54143 +    struct ieee80211_common_ie  *cie;
54144 +       struct iw_request_info info;
54145 +
54146 +       info.cmd = 0;
54147 +       info.flags = 0;
54148 +
54149 +    param = (struct ar_giwscan_param *)arg;
54150 +
54151 +    if (param->current_ev >= param->end_buf) {
54152 +        return;
54153 +    }
54154 +    if ((param->firstPass == TRUE) &&
54155 +        ((ni->ni_cie.ie_wpa == NULL) && (ni->ni_cie.ie_rsn == NULL))) {
54156 +        /*
54157 +         * Only forward wpa bss's in first pass
54158 +         */
54159 +        return;
54160 +    }
54161 +
54162 +     if ((param->firstPass == FALSE) &&
54163 +        ((ni->ni_cie.ie_wpa != NULL) || (ni->ni_cie.ie_rsn != NULL))) {
54164 +        /*
54165 +         * Only forward non-wpa bss's in 2nd pass
54166 +         */
54167 +        return;
54168 +    }
54169 +
54170 +    current_ev = param->current_ev;
54171 +    end_buf = param->end_buf;
54172 +
54173 +    cie = &ni->ni_cie;
54174 +
54175 +    A_MEMZERO(&iwe, sizeof(iwe));
54176 +    iwe.cmd = SIOCGIWAP;
54177 +    iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
54178 +    A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
54179 +    current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
54180 +                                      IW_EV_ADDR_LEN);
54181 +
54182 +    A_MEMZERO(&iwe, sizeof(iwe));
54183 +    iwe.cmd = SIOCGIWESSID;
54184 +    iwe.u.data.flags = 1;
54185 +    iwe.u.data.length = cie->ie_ssid[1];
54186 +    current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
54187 +                                      &cie->ie_ssid[2]);
54188 +
54189 +    if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
54190 +        A_MEMZERO(&iwe, sizeof(iwe));
54191 +        iwe.cmd = SIOCGIWMODE;
54192 +        iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
54193 +                IW_MODE_MASTER : IW_MODE_ADHOC;
54194 +        current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
54195 +                                          IW_EV_UINT_LEN);
54196 +    }
54197 +
54198 +    A_MEMZERO(&iwe, sizeof(iwe));
54199 +    iwe.cmd = SIOCGIWFREQ;
54200 +    iwe.u.freq.m = cie->ie_chan * 100000;
54201 +    iwe.u.freq.e = 1;
54202 +    current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
54203 +                                      IW_EV_FREQ_LEN);
54204 +
54205 +    A_MEMZERO(&iwe, sizeof(iwe));
54206 +    iwe.cmd = IWEVQUAL;
54207 +    ar6000_set_quality(&iwe.u.qual, ni->ni_snr);
54208 +    current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
54209 +                                      IW_EV_QUAL_LEN);
54210 +
54211 +    A_MEMZERO(&iwe, sizeof(iwe));
54212 +    iwe.cmd = SIOCGIWENCODE;
54213 +    if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
54214 +        iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
54215 +    } else {
54216 +        iwe.u.data.flags = IW_ENCODE_DISABLED;
54217 +    }
54218 +    iwe.u.data.length = 0;
54219 +    current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe, "");
54220 +
54221 +    A_MEMZERO(&iwe, sizeof(iwe));
54222 +    iwe.cmd = IWEVCUSTOM;
54223 +    snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
54224 +    iwe.u.data.length = strlen(buf);
54225 +    current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe, buf);
54226 +
54227 +    if (cie->ie_wpa != NULL) {
54228 +        static const char wpa_leader[] = "wpa_ie=";
54229 +
54230 +        A_MEMZERO(&iwe, sizeof(iwe));
54231 +        iwe.cmd = IWEVCUSTOM;
54232 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
54233 +                                      cie->ie_wpa[1]+2,
54234 +                                      wpa_leader, sizeof(wpa_leader)-1);
54235 +
54236 +        if (iwe.u.data.length != 0) {
54237 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
54238 +                                                                          buf);
54239 +        }
54240 +    }
54241 +
54242 +    if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
54243 +        static const char rsn_leader[] = "rsn_ie=";
54244 +
54245 +        A_MEMZERO(&iwe, sizeof(iwe));
54246 +        iwe.cmd = IWEVCUSTOM;
54247 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn,
54248 +                                      cie->ie_rsn[1]+2,
54249 +                                      rsn_leader, sizeof(rsn_leader)-1);
54250 +
54251 +        if (iwe.u.data.length != 0) {
54252 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
54253 +                                                                          buf);
54254 +        }
54255 +    }
54256 +
54257 +    if (cie->ie_wmm != NULL) {
54258 +        static const char wmm_leader[] = "wmm_ie=";
54259 +
54260 +        A_MEMZERO(&iwe, sizeof(iwe));
54261 +        iwe.cmd = IWEVCUSTOM;
54262 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
54263 +                                      cie->ie_wmm[1]+2,
54264 +                                      wmm_leader, sizeof(wmm_leader)-1);
54265 +        if (iwe.u.data.length != 0) {
54266 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
54267 +                                                                          buf);
54268 +        }
54269 +    }
54270 +
54271 +    if (cie->ie_ath != NULL) {
54272 +        static const char ath_leader[] = "ath_ie=";
54273 +
54274 +        A_MEMZERO(&iwe, sizeof(iwe));
54275 +        iwe.cmd = IWEVCUSTOM;
54276 +        iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
54277 +                                      cie->ie_ath[1]+2,
54278 +                                      ath_leader, sizeof(ath_leader)-1);
54279 +        if (iwe.u.data.length != 0) {
54280 +            current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
54281 +                                                                          buf);
54282 +        }
54283 +    }
54284 +
54285 +    param->current_ev = current_ev;
54286 +}
54287 +
54288 +int
54289 +ar6000_ioctl_giwscan(struct net_device *dev,
54290 +            struct iw_request_info *info,
54291 +            struct iw_point *data, char *extra)
54292 +{
54293 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54294 +    struct ar_giwscan_param param;
54295 +    int i;
54296 +
54297 +    if (ar->arWlanState == WLAN_DISABLED) {
54298 +        return -EIO;
54299 +    }
54300 +
54301 +    if (ar->arWmiReady == FALSE) {
54302 +        return -EIO;
54303 +    }
54304 +
54305 +    param.current_ev = extra;
54306 +    param.end_buf = extra + IW_SCAN_MAX_DATA;
54307 +    param.firstPass = TRUE;
54308 +
54309 +    /*
54310 +     * Do two passes to insure WPA scan candidates
54311 +     * are sorted to the front.  This is a hack to deal with
54312 +     * the wireless extensions capping scan results at
54313 +     * IW_SCAN_MAX_DATA bytes.  In densely populated environments
54314 +     * it's easy to overflow this buffer (especially with WPA/RSN
54315 +     * information elements).  Note this sorting hack does not
54316 +     * guarantee we won't overflow anyway.
54317 +     */
54318 +    for (i = 0; i < 2; i++) {
54319 +        /*
54320 +         * Translate data to WE format.
54321 +         */
54322 +        wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, &param);
54323 +        param.firstPass = FALSE;
54324 +        if (param.current_ev >= param.end_buf) {
54325 +            data->length = param.current_ev - extra;
54326 +            return -E2BIG;
54327 +        }
54328 +    }
54329 +
54330 +    if(!(data->length = param.current_ev - extra)) {
54331 +           printk("%s(): data length %d\n", __FUNCTION__, data->length);
54332 +           return -EAGAIN;
54333 +    }
54334 +    return 0;
54335 +}
54336 +
54337 +extern int reconnect_flag;
54338 +/* SIOCSIWESSID */
54339 +static int
54340 +ar6000_ioctl_siwessid(struct net_device *dev,
54341 +                     struct iw_request_info *info,
54342 +                     struct iw_point *data, char *ssid)
54343 +{
54344 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54345 +    A_STATUS status;
54346 +    A_UINT8     arNetworkType;
54347 +
54348 +    if (ar->arWlanState == WLAN_DISABLED) {
54349 +        return -EIO;
54350 +    }
54351 +
54352 +    if (ar->arWmiReady == FALSE) {
54353 +        return -EIO;
54354 +    }
54355 +
54356 +    /*
54357 +     * iwconfig passes a string with length excluding any trailing NUL.
54358 +     * FIXME: we should be able to set an ESSID of 32 bytes, yet things fall
54359 +     * over badly if we do. So we limit the ESSID to 31 bytes.
54360 +     */
54361 +    if (data->flags && (!data->length || data->length >= sizeof(ar->arSsid))) {
54362 +        /*
54363 +         * ssid is invalid
54364 +         */
54365 +        return -EINVAL;
54366 +    }
54367 +    /* Added for bug 25178, return an IOCTL error instead of target returning
54368 +       Illegal parameter error when either the BSSID or channel is missing
54369 +       and we cannot scan during connect.
54370 +     */
54371 +    if (data->flags) {
54372 +        if (ar->arSkipScan == TRUE &&
54373 +            (ar->arChannelHint == 0 ||
54374 +             (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] &&
54375 +              !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5])))
54376 +        {
54377 +            return -EINVAL;
54378 +        }
54379 +    }
54380 +
54381 +    if (down_interruptible(&ar->arSem)) {
54382 +        return -ERESTARTSYS;
54383 +    }
54384 +
54385 +    if (ar->arTxPending[WMI_CONTROL_PRI]) {
54386 +        /*
54387 +         * sleep until the command queue drains
54388 +         */
54389 +        wait_event_interruptible_timeout(arEvent,
54390 +            ar->arTxPending[WMI_CONTROL_PRI] == 0, wmitimeout * HZ);
54391 +        if (signal_pending(current)) {
54392 +            return -EINTR;
54393 +        }
54394 +    }
54395 +
54396 +    if (!data->flags) {
54397 +        arNetworkType = ar->arNetworkType;
54398 +        ar6000_init_profile_info(ar);
54399 +        ar->arNetworkType = arNetworkType;
54400 +    }
54401 +
54402 +    /*
54403 +     * The original logic here prevented a disconnect if issuing an "essid off"
54404 +     * if no ESSID was set, presumably to prevent sending multiple disconnects
54405 +     * to the WMI.
54406 +     *
54407 +     * Unfortunately, this also meant that no disconnect was sent when we were
54408 +     * already connected, but the profile has been changed since (which also
54409 +     * clears the ESSID as a reminder that the WMI needs updating.)
54410 +     *
54411 +     * The "1 ||" makes sure we always disconnect or reconnect. The WMI doesn't
54412 +     * seem to mind being sent multiple disconnects.
54413 +     */
54414 +    if (1 || (ar->arSsidLen) || (!data->flags))
54415 +    {
54416 +        if ((!data->flags) ||
54417 +            (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
54418 +            (ar->arSsidLen != (data->length)))
54419 +        {
54420 +            /*
54421 +             * SSID set previously or essid off has been issued.
54422 +             *
54423 +             * Disconnect Command is issued in two cases after wmi is ready
54424 +             * (1) ssid is different from the previous setting
54425 +             * (2) essid off has been issued
54426 +             *
54427 +             */
54428 +            if (ar->arWmiReady == TRUE) {
54429 +                reconnect_flag = 0;
54430 +                status = wmi_disconnect_cmd(ar->arWmi);
54431 +                A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
54432 +                ar->arSsidLen = 0;
54433 +                if (ar->arSkipScan == FALSE) {
54434 +                    A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
54435 +                }
54436 +                if (!data->flags) {
54437 +                    up(&ar->arSem);
54438 +                    return 0;
54439 +                }
54440 +            } else {
54441 +                 up(&ar->arSem);
54442 +            }
54443 +        }
54444 +        else
54445 +        {
54446 +            /*
54447 +             * SSID is same, so we assume profile hasn't changed.
54448 +             * If the interface is up and wmi is ready, we issue
54449 +             * a reconnect cmd. Issue a reconnect only we are already
54450 +             * connected.
54451 +             */
54452 +            if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE))
54453 +            {
54454 +                reconnect_flag = TRUE;
54455 +                status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
54456 +                                           ar->arChannelHint);
54457 +                up(&ar->arSem);
54458 +                if (status != A_OK) {
54459 +                    return -EIO;
54460 +                }
54461 +                return 0;
54462 +            }
54463 +            else{
54464 +                /*
54465 +                 * Dont return if connect is pending.
54466 +                 */
54467 +                if(!(ar->arConnectPending)) {
54468 +                    up(&ar->arSem);
54469 +                    return 0;
54470 +                }
54471 +            }
54472 +        }
54473 +    }
54474 +
54475 +    ar->arSsidLen = data->length;
54476 +    A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
54477 +
54478 +    /* The ssid length check prevents second "essid off" from the user,
54479 +       to be treated as a connect cmd. The second "essid off" is ignored.
54480 +    */
54481 +    if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) )
54482 +    {
54483 +        AR6000_SPIN_LOCK(&ar->arLock, 0);
54484 +        if (SHARED_AUTH == ar->arDot11AuthMode) {
54485 +            ar6000_install_static_wep_keys(ar);
54486 +        }
54487 +        AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\
54488 +                        " PW crypto %d PW crypto Len %d GRP crypto %d"\
54489 +                        " GRP crypto Len %d\n",
54490 +                        ar->arAuthMode, ar->arDot11AuthMode,
54491 +                        ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
54492 +                        ar->arGroupCrypto, ar->arGroupCryptoLen);
54493 +        reconnect_flag = 0;
54494 +        AR6000_SPIN_UNLOCK(&ar->arLock, 0);
54495 +        status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
54496 +                                 ar->arDot11AuthMode, ar->arAuthMode,
54497 +                                 ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
54498 +                                 ar->arGroupCrypto,ar->arGroupCryptoLen,
54499 +                                 ar->arSsidLen, ar->arSsid,
54500 +                                 ar->arReqBssid, ar->arChannelHint,
54501 +                                 ar->arConnectCtrlFlags);
54502 +
54503 +
54504 +        up(&ar->arSem);
54505 +
54506 +        if (status != A_OK) {
54507 +            return -EIO;
54508 +        }
54509 +        ar->arConnectPending = TRUE;
54510 +    }else{
54511 +      up(&ar->arSem);
54512 +    }
54513 +    return 0;
54514 +}
54515 +
54516 +/* SIOCGIWESSID */
54517 +static int
54518 +ar6000_ioctl_giwessid(struct net_device *dev,
54519 +                     struct iw_request_info *info,
54520 +                     struct iw_point *data, char *essid)
54521 +{
54522 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54523 +
54524 +    if (ar->arWlanState == WLAN_DISABLED) {
54525 +        return -EIO;
54526 +    }
54527 +
54528 +    data->flags = 1;
54529 +    data->length = ar->arSsidLen;
54530 +    A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
54531 +
54532 +    return 0;
54533 +}
54534 +
54535 +
54536 +void ar6000_install_static_wep_keys(AR_SOFTC_T *ar)
54537 +{
54538 +    A_UINT8 index;
54539 +    A_UINT8 keyUsage;
54540 +
54541 +    for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
54542 +        if (ar->arWepKeyList[index].arKeyLen) {
54543 +            keyUsage = GROUP_USAGE;
54544 +            if (index == ar->arDefTxKeyIndex) {
54545 +                keyUsage |= TX_USAGE;
54546 +            }
54547 +            wmi_addKey_cmd(ar->arWmi,
54548 +                           index,
54549 +                           WEP_CRYPT,
54550 +                           keyUsage,
54551 +                           ar->arWepKeyList[index].arKeyLen,
54552 +                           NULL,
54553 +                           ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL,
54554 +                           NO_SYNC_WMIFLAG);
54555 +        }
54556 +    }
54557 +}
54558 +
54559 +int
54560 +ar6000_ioctl_delkey(struct net_device *dev, struct iw_request_info *info,
54561 +             void *w, char *extra)
54562 +{
54563 +    return 0;
54564 +}
54565 +
54566 +int
54567 +ar6000_ioctl_setmlme(struct net_device *dev, struct iw_request_info *info,
54568 +             void *w, char *extra)
54569 +{
54570 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54571 +    struct ieee80211req_mlme *mlme = (struct ieee80211req_mlme *)extra;
54572 +
54573 +    if ((ar->arWmiReady == FALSE) || (ar->arConnected != TRUE))
54574 +               return -EIO;
54575 +
54576 +    switch (mlme->im_op) {
54577 +        case IEEE80211_MLME_DISASSOC:
54578 +        case IEEE80211_MLME_DEAUTH:
54579 +            /* Not Supported */
54580 +            break;
54581 +        default:
54582 +            break;
54583 +    }
54584 +    return 0;
54585 +}
54586 +
54587 +
54588 +int
54589 +ar6000_ioctl_setwmmparams(struct net_device *dev, struct iw_request_info *info,
54590 +             void *w, char *extra)
54591 +{
54592 +    return -EIO;            /* for now */
54593 +}
54594 +
54595 +int
54596 +ar6000_ioctl_getwmmparams(struct net_device *dev, struct iw_request_info *info,
54597 +             void *w, char *extra)
54598 +{
54599 +    return -EIO;            /* for now */
54600 +}
54601 +
54602 +int ar6000_ioctl_setoptie(struct net_device *dev, struct iw_request_info *info,
54603 +                         struct iw_point *data, char *extra)
54604 +{
54605 +       /* The target generates the WPA/RSN IE */
54606 +       return 0;
54607 +}
54608 +
54609 +int
54610 +ar6000_ioctl_setauthalg(struct net_device *dev, struct iw_request_info *info,
54611 +             void *w, char *extra)
54612 +{
54613 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54614 +    struct ieee80211req_authalg *req = (struct ieee80211req_authalg *)extra;
54615 +    int ret = 0;
54616 +
54617 +
54618 +    AR6000_SPIN_LOCK(&ar->arLock, 0);
54619 +
54620 +    if (req->auth_alg == AUTH_ALG_OPEN_SYSTEM) {
54621 +        ar->arDot11AuthMode  = OPEN_AUTH;
54622 +    } else if (req->auth_alg == AUTH_ALG_LEAP) {
54623 +        ar->arDot11AuthMode   = LEAP_AUTH;
54624 +        ar->arPairwiseCrypto  = WEP_CRYPT;
54625 +        ar->arGroupCrypto     = WEP_CRYPT;
54626 +    } else {
54627 +        ret = -EIO;
54628 +    }
54629 +
54630 +    AR6000_SPIN_UNLOCK(&ar->arLock, 0);
54631 +
54632 +    return ret;
54633 +}
54634 +static int
54635 +ar6000_ioctl_addpmkid(struct net_device *dev, struct iw_request_info *info,
54636 +             void *w, char *extra)
54637 +{
54638 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54639 +    struct ieee80211req_addpmkid  *req = (struct ieee80211req_addpmkid *)extra;
54640 +    A_STATUS status;
54641 +
54642 +    if (ar->arWlanState == WLAN_DISABLED) {
54643 +        return -EIO;
54644 +    }
54645 +
54646 +    AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
54647 +                    req->pi_bssid[0], req->pi_bssid[1], req->pi_bssid[2],
54648 +                    req->pi_bssid[3], req->pi_bssid[4], req->pi_bssid[5],
54649 +                    req->pi_enable);
54650 +
54651 +    status = wmi_setPmkid_cmd(ar->arWmi, req->pi_bssid, req->pi_pmkid,
54652 +                              req->pi_enable);
54653 +
54654 +    if (status != A_OK) {
54655 +        return -EIO;
54656 +    }
54657 +
54658 +    return 0;
54659 +}
54660 +
54661 +/*
54662 + * SIOCSIWRATE
54663 + */
54664 +int
54665 +ar6000_ioctl_siwrate(struct net_device *dev,
54666 +            struct iw_request_info *info,
54667 +            struct iw_param *rrq, char *extra)
54668 +{
54669 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54670 +    A_UINT32  kbps;
54671 +
54672 +    if (rrq->fixed) {
54673 +        kbps = rrq->value / 1000;           /* rrq->value is in bps */
54674 +    } else {
54675 +        kbps = -1;                          /* -1 indicates auto rate */
54676 +    }
54677 +    if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL)
54678 +    {
54679 +        AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps);
54680 +        return -EINVAL;
54681 +    }
54682 +    ar->arBitRate = kbps;
54683 +    if(ar->arWmiReady == TRUE)
54684 +    {
54685 +        if (wmi_set_bitrate_cmd(ar->arWmi, kbps) != A_OK) {
54686 +            return -EINVAL;
54687 +        }
54688 +    }
54689 +    return 0;
54690 +}
54691 +
54692 +/*
54693 + * SIOCGIWRATE
54694 + */
54695 +int
54696 +ar6000_ioctl_giwrate(struct net_device *dev,
54697 +            struct iw_request_info *info,
54698 +            struct iw_param *rrq, char *extra)
54699 +{
54700 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54701 +    int ret = 0;
54702 +
54703 +    if (down_interruptible(&ar->arSem)) {
54704 +        return -ERESTARTSYS;
54705 +    }
54706 +    if(ar->arWmiReady == TRUE)
54707 +    {
54708 +        ar->arBitRate = 0xFFFF;
54709 +        if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
54710 +            up(&ar->arSem);
54711 +            return -EIO;
54712 +        }
54713 +        wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ);
54714 +        if (signal_pending(current)) {
54715 +            ret = -EINTR;
54716 +        }
54717 +    }
54718 +    /* If the interface is down or wmi is not ready or the target is not
54719 +       connected - return the value stored in the device structure */
54720 +    if (!ret) {
54721 +        if (ar->arBitRate == -1) {
54722 +            rrq->fixed = TRUE;
54723 +            rrq->value = 0;
54724 +        } else {
54725 +            rrq->value = ar->arBitRate * 1000;
54726 +        }
54727 +    }
54728 +
54729 +    up(&ar->arSem);
54730 +
54731 +    return ret;
54732 +}
54733 +
54734 +/*
54735 + * SIOCSIWTXPOW
54736 + */
54737 +static int
54738 +ar6000_ioctl_siwtxpow(struct net_device *dev,
54739 +             struct iw_request_info *info,
54740 +             struct iw_param *rrq, char *extra)
54741 +{
54742 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54743 +    A_UINT8 dbM;
54744 +
54745 +    if (ar->arWlanState == WLAN_DISABLED) {
54746 +        return -EIO;
54747 +    }
54748 +
54749 +    if (ar->arRadioSwitch == WLAN_ENABLED
54750 +       && rrq->disabled) {
54751 +           if (wmi_switch_radio(ar->arWmi, WLAN_DISABLED) < 0)
54752 +                   return -EIO;
54753 +           ar->arRadioSwitch = WLAN_DISABLED;
54754 +    } else if (ar->arRadioSwitch == WLAN_DISABLED
54755 +              && !rrq->disabled) {
54756 +           if (wmi_switch_radio(ar->arWmi, WLAN_ENABLED) < 0)
54757 +                   return -EIO;
54758 +           ar->arRadioSwitch = WLAN_ENABLED;
54759 +    }
54760 +
54761 +    if (rrq->fixed) {
54762 +        if (rrq->flags != IW_TXPOW_DBM) {
54763 +            return -EOPNOTSUPP;
54764 +        }
54765 +        ar->arTxPwr= dbM = rrq->value;
54766 +        ar->arTxPwrSet = TRUE;
54767 +    } else {
54768 +        ar->arTxPwr = dbM = 0;
54769 +        ar->arTxPwrSet = FALSE;
54770 +    }
54771 +    if(ar->arWmiReady == TRUE)
54772 +    {
54773 +        AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM);
54774 +        wmi_set_txPwr_cmd(ar->arWmi, dbM);
54775 +    }
54776 +    return 0;
54777 +}
54778 +
54779 +/*
54780 + * SIOCGIWTXPOW
54781 + */
54782 +int
54783 +ar6000_ioctl_giwtxpow(struct net_device *dev,
54784 +            struct iw_request_info *info,
54785 +            struct iw_param *rrq, char *extra)
54786 +{
54787 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54788 +    int ret = 0;
54789 +
54790 +    if (ar->arWlanState == WLAN_DISABLED) {
54791 +        return -EIO;
54792 +    }
54793 +
54794 +    if (ar->arRadioSwitch == WLAN_DISABLED) {
54795 +           rrq->disabled = 1;
54796 +           return 0;
54797 +    }
54798 +
54799 +    if (down_interruptible(&ar->arSem)) {
54800 +        return -ERESTARTSYS;
54801 +    }
54802 +    if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE))
54803 +    {
54804 +        ar->arTxPwr = 0;
54805 +
54806 +        if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
54807 +            up(&ar->arSem);
54808 +            return -EIO;
54809 +        }
54810 +
54811 +        wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ);
54812 +
54813 +        if (signal_pending(current)) {
54814 +            ret = -EINTR;
54815 +         }
54816 +    }
54817 +   /* If the interace is down or wmi is not ready or target is not connected
54818 +      then return value stored in the device structure */
54819 +
54820 +    if (!ret) {
54821 +         if (ar->arTxPwrSet == TRUE) {
54822 +            rrq->fixed = TRUE;
54823 +        }
54824 +        rrq->value = ar->arTxPwr;
54825 +        rrq->flags = IW_TXPOW_DBM;
54826 +    }
54827 +
54828 +    up(&ar->arSem);
54829 +
54830 +    return ret;
54831 +}
54832 +
54833 +/*
54834 + * SIOCSIWRETRY
54835 + * since iwconfig only provides us with one max retry value, we use it
54836 + * to apply to data frames of the BE traffic class.
54837 + */
54838 +static int
54839 +ar6000_ioctl_siwretry(struct net_device *dev,
54840 +             struct iw_request_info *info,
54841 +             struct iw_param *rrq, char *extra)
54842 +{
54843 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54844 +
54845 +    if (ar->arWlanState == WLAN_DISABLED) {
54846 +        return -EIO;
54847 +    }
54848 +
54849 +    if (rrq->disabled) {
54850 +        return -EOPNOTSUPP;
54851 +    }
54852 +
54853 +    if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
54854 +        return -EOPNOTSUPP;
54855 +    }
54856 +
54857 +    if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
54858 +            return - EINVAL;
54859 +    }
54860 +    if(ar->arWmiReady == TRUE)
54861 +    {
54862 +        if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
54863 +                                     rrq->value, 0) != A_OK){
54864 +            return -EINVAL;
54865 +        }
54866 +    }
54867 +    ar->arMaxRetries = rrq->value;
54868 +    return 0;
54869 +}
54870 +
54871 +/*
54872 + * SIOCGIWRETRY
54873 + */
54874 +static int
54875 +ar6000_ioctl_giwretry(struct net_device *dev,
54876 +             struct iw_request_info *info,
54877 +             struct iw_param *rrq, char *extra)
54878 +{
54879 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54880 +
54881 +    if (ar->arWlanState == WLAN_DISABLED) {
54882 +        return -EIO;
54883 +    }
54884 +
54885 +    rrq->disabled = 0;
54886 +    switch (rrq->flags & IW_RETRY_TYPE) {
54887 +    case IW_RETRY_LIFETIME:
54888 +        return -EOPNOTSUPP;
54889 +        break;
54890 +    case IW_RETRY_LIMIT:
54891 +        rrq->flags = IW_RETRY_LIMIT;
54892 +        switch (rrq->flags & IW_RETRY_MODIFIER) {
54893 +        case IW_RETRY_MIN:
54894 +            rrq->flags |= IW_RETRY_MIN;
54895 +            rrq->value = WMI_MIN_RETRIES;
54896 +            break;
54897 +        case IW_RETRY_MAX:
54898 +            rrq->flags |= IW_RETRY_MAX;
54899 +            rrq->value = ar->arMaxRetries;
54900 +            break;
54901 +        }
54902 +        break;
54903 +    }
54904 +    return 0;
54905 +}
54906 +
54907 +/*
54908 + * SIOCSIWENCODE
54909 + */
54910 +static int
54911 +ar6000_ioctl_siwencode(struct net_device *dev,
54912 +              struct iw_request_info *info,
54913 +              struct iw_point *erq, char *keybuf)
54914 +{
54915 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
54916 +    int index;
54917 +    A_INT32 auth = ar->arDot11AuthMode;
54918 +
54919 +    if (ar->arWlanState == WLAN_DISABLED) {
54920 +        return -EIO;
54921 +    }
54922 +
54923 +    index = erq->flags & IW_ENCODE_INDEX;
54924 +
54925 +    if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
54926 +                  ((index - 1) > WMI_MAX_KEY_INDEX)))
54927 +    {
54928 +        return -EIO;
54929 +    }
54930 +
54931 +    if (erq->flags & IW_ENCODE_DISABLED) {
54932 +        /*
54933 +         * Encryption disabled
54934 +         */
54935 +        if (index) {
54936 +            /*
54937 +             * If key index was specified then clear the specified key
54938 +             */
54939 +            index--;
54940 +            A_MEMZERO(ar->arWepKeyList[index].arKey,
54941 +                      sizeof(ar->arWepKeyList[index].arKey));
54942 +            ar->arWepKeyList[index].arKeyLen = 0;
54943 +        }
54944 +        ar->arDot11AuthMode       = OPEN_AUTH;
54945 +        ar->arPairwiseCrypto      = NONE_CRYPT;
54946 +        ar->arGroupCrypto         = NONE_CRYPT;
54947 +        ar->arAuthMode            = NONE_AUTH;
54948 +    } else {
54949 +        /*
54950 +         * Enabling WEP encryption
54951 +         */
54952 +        if (index) {
54953 +            index--;                /* keyindex is off base 1 in iwconfig */
54954 +        }
54955 +
54956 +        if (erq->flags & IW_ENCODE_OPEN) {
54957 +            auth = OPEN_AUTH;
54958 +        } else if (erq->flags & IW_ENCODE_RESTRICTED) {
54959 +            auth = SHARED_AUTH;
54960 +        }
54961 +
54962 +        if (erq->length) {
54963 +            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
54964 +                return -EIO;
54965 +            }
54966 +
54967 +            A_MEMZERO(ar->arWepKeyList[index].arKey,
54968 +                      sizeof(ar->arWepKeyList[index].arKey));
54969 +            A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
54970 +            ar->arWepKeyList[index].arKeyLen = erq->length;
54971 +        } else {
54972 +            if (ar->arWepKeyList[index].arKeyLen == 0) {
54973 +                return -EIO;
54974 +            }
54975 +            ar->arDefTxKeyIndex = index;
54976 +        }
54977 +
54978 +        ar->arPairwiseCrypto      = WEP_CRYPT;
54979 +        ar->arGroupCrypto         = WEP_CRYPT;
54980 +        ar->arDot11AuthMode       = auth;
54981 +        ar->arAuthMode            = NONE_AUTH;
54982 +    }
54983 +
54984 +    /*
54985 +     * profile has changed.  Erase ssid to signal change
54986 +     */
54987 +    A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
54988 +    ar->arSsidLen = 0;
54989 +
54990 +    return 0;
54991 +}
54992 +
54993 +static int
54994 +ar6000_ioctl_giwencode(struct net_device *dev,
54995 +              struct iw_request_info *info,
54996 +              struct iw_point *erq, char *key)
54997 +{
54998 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
54999 +    A_UINT8 keyIndex;
55000 +    struct ar_wep_key *wk;
55001 +
55002 +    if (ar->arWlanState == WLAN_DISABLED) {
55003 +        return -EIO;
55004 +    }
55005 +
55006 +    if (ar->arPairwiseCrypto == NONE_CRYPT) {
55007 +        erq->length = 0;
55008 +        erq->flags = IW_ENCODE_DISABLED;
55009 +    } else {
55010 +        /* get the keyIndex */
55011 +        keyIndex = erq->flags & IW_ENCODE_INDEX;
55012 +        if (0 == keyIndex) {
55013 +            keyIndex = ar->arDefTxKeyIndex;
55014 +        } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
55015 +                   (keyIndex - 1 > WMI_MAX_KEY_INDEX))
55016 +        {
55017 +            keyIndex = WMI_MIN_KEY_INDEX;
55018 +        } else {
55019 +            keyIndex--;
55020 +        }
55021 +        erq->flags = keyIndex + 1;
55022 +        erq->flags |= IW_ENCODE_ENABLED;
55023 +        wk = &ar->arWepKeyList[keyIndex];
55024 +        if (erq->length > wk->arKeyLen) {
55025 +            erq->length = wk->arKeyLen;
55026 +        }
55027 +        if (wk->arKeyLen) {
55028 +            A_MEMCPY(key, wk->arKey, erq->length);
55029 +        }
55030 +        if (ar->arDot11AuthMode == OPEN_AUTH) {
55031 +            erq->flags |= IW_ENCODE_OPEN;
55032 +        } else if (ar->arDot11AuthMode == SHARED_AUTH) {
55033 +            erq->flags |= IW_ENCODE_RESTRICTED;
55034 +        }
55035 +    }
55036 +
55037 +    return 0;
55038 +}
55039 +
55040 +static int ar6000_ioctl_siwpower(struct net_device *dev,
55041 +                                struct iw_request_info *info,
55042 +                                union iwreq_data *wrqu, char *extra)
55043 +{
55044 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
55045 +       WMI_POWER_MODE power_mode;
55046 +
55047 +       if (wrqu->power.disabled)
55048 +               power_mode = MAX_PERF_POWER;
55049 +       else
55050 +               power_mode = REC_POWER;
55051 +
55052 +       if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0)
55053 +               return -EIO;
55054 +
55055 +       return 0;
55056 +}
55057 +
55058 +static int ar6000_ioctl_giwpower(struct net_device *dev,
55059 +                                struct iw_request_info *info,
55060 +                                union iwreq_data *wrqu, char *extra)
55061 +{
55062 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
55063 +
55064 +       return wmi_get_power_mode_cmd(ar->arWmi);
55065 +}
55066 +
55067 +static int ar6000_ioctl_siwgenie(struct net_device *dev,
55068 +                                struct iw_request_info *info,
55069 +                                struct iw_point *dwrq,
55070 +                                char *extra)
55071 +{
55072 +       /* The target does that for us */
55073 +       return 0;
55074 +}
55075 +
55076 +static int ar6000_ioctl_giwgenie(struct net_device *dev,
55077 +                                struct iw_request_info *info,
55078 +                                struct iw_point *dwrq,
55079 +                                char *extra)
55080 +{
55081 +       return 0;
55082 +}
55083 +
55084 +static int ar6000_ioctl_siwauth(struct net_device *dev,
55085 +                               struct iw_request_info *info,
55086 +                               struct iw_param *param,
55087 +                               char *extra)
55088 +{
55089 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
55090 +       int reset = 0;
55091 +
55092 +       switch (param->flags & IW_AUTH_INDEX) {
55093 +       case IW_AUTH_WPA_VERSION:
55094 +               if (param->value & IW_AUTH_WPA_VERSION_DISABLED) {
55095 +                       ar->arAuthMode = NONE_AUTH;
55096 +               }
55097 +               if (param->value & IW_AUTH_WPA_VERSION_WPA) {
55098 +                       ar->arAuthMode = WPA_AUTH;
55099 +               }
55100 +               if (param->value & IW_AUTH_WPA_VERSION_WPA2) {
55101 +                       ar->arAuthMode = WPA2_AUTH;
55102 +               }
55103 +
55104 +               reset = 1;
55105 +               break;
55106 +       case IW_AUTH_CIPHER_PAIRWISE:
55107 +               if (param->value & IW_AUTH_CIPHER_NONE) {
55108 +                       ar->arPairwiseCrypto = NONE_CRYPT;
55109 +               }
55110 +               if (param->value & IW_AUTH_CIPHER_WEP40) {
55111 +                       ar->arPairwiseCrypto = WEP_CRYPT;
55112 +               }
55113 +               if (param->value & IW_AUTH_CIPHER_TKIP) {
55114 +                       ar->arPairwiseCrypto = TKIP_CRYPT;
55115 +               }
55116 +               if (param->value & IW_AUTH_CIPHER_CCMP) {
55117 +                       ar->arPairwiseCrypto = AES_CRYPT;
55118 +               }
55119 +
55120 +               reset = 1;
55121 +               break;
55122 +       case IW_AUTH_CIPHER_GROUP:
55123 +               if (param->value & IW_AUTH_CIPHER_NONE) {
55124 +                       ar->arGroupCrypto = NONE_CRYPT;
55125 +               }
55126 +               if (param->value & IW_AUTH_CIPHER_WEP40) {
55127 +                       ar->arGroupCrypto = WEP_CRYPT;
55128 +               }
55129 +               if (param->value & IW_AUTH_CIPHER_TKIP) {
55130 +                       ar->arGroupCrypto = TKIP_CRYPT;
55131 +               }
55132 +               if (param->value & IW_AUTH_CIPHER_CCMP) {
55133 +                       ar->arGroupCrypto = AES_CRYPT;
55134 +               }
55135 +
55136 +               reset = 1;
55137 +               break;
55138 +       case IW_AUTH_KEY_MGMT:
55139 +               if (param->value & IW_AUTH_KEY_MGMT_PSK) {
55140 +                       if (ar->arAuthMode == WPA_AUTH) {
55141 +                               ar->arAuthMode = WPA_PSK_AUTH;
55142 +                       } else if (ar->arAuthMode == WPA2_AUTH) {
55143 +                               ar->arAuthMode = WPA2_PSK_AUTH;
55144 +                       }
55145 +
55146 +                       reset = 1;
55147 +               }
55148 +               break;
55149 +
55150 +       case IW_AUTH_TKIP_COUNTERMEASURES:
55151 +               if (ar->arWmiReady == FALSE) {
55152 +                       return -EIO;
55153 +               }
55154 +               wmi_set_tkip_countermeasures_cmd(ar->arWmi, param->value);
55155 +               break;
55156 +
55157 +       case IW_AUTH_DROP_UNENCRYPTED:
55158 +               break;
55159 +
55160 +       case IW_AUTH_80211_AUTH_ALG:
55161 +               if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) {
55162 +                       ar->arDot11AuthMode  = OPEN_AUTH;
55163 +               }
55164 +               if (param->value & IW_AUTH_ALG_SHARED_KEY) {
55165 +                       ar->arDot11AuthMode  = SHARED_AUTH;
55166 +               }
55167 +               if (param->value & IW_AUTH_ALG_LEAP) {
55168 +                       ar->arDot11AuthMode   = LEAP_AUTH;
55169 +                       ar->arPairwiseCrypto  = WEP_CRYPT;
55170 +                       ar->arGroupCrypto     = WEP_CRYPT;
55171 +               }
55172 +
55173 +               reset = 1;
55174 +               break;
55175 +
55176 +       case IW_AUTH_WPA_ENABLED:
55177 +               reset = 1;
55178 +               break;
55179 +
55180 +       case IW_AUTH_RX_UNENCRYPTED_EAPOL:
55181 +               break;
55182 +
55183 +       case IW_AUTH_PRIVACY_INVOKED:
55184 +               break;
55185 +
55186 +       default:
55187 +               printk("%s(): Unknown flag 0x%x\n", __FUNCTION__, param->flags);
55188 +               return -EOPNOTSUPP;
55189 +       }
55190 +
55191 +       if (reset) {
55192 +               A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
55193 +               ar->arSsidLen = 0;
55194 +       }
55195 +
55196 +       return 0;
55197 +}
55198 +
55199 +static int ar6000_ioctl_giwauth(struct net_device *dev,
55200 +                               struct iw_request_info *info,
55201 +                               struct iw_param *dwrq,
55202 +                               char *extra)
55203 +{
55204 +       return 0;
55205 +}
55206 +
55207 +static int ar6000_ioctl_siwencodeext(struct net_device *dev,
55208 +                                    struct iw_request_info *info,
55209 +                                    union iwreq_data *wrqu,
55210 +                                    char *extra)
55211 +{
55212 +       AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
55213 +       struct iw_point *encoding = &wrqu->encoding;
55214 +       struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
55215 +       int alg = ext->alg, idx;
55216 +
55217 +       if (ar->arWlanState == WLAN_DISABLED) {
55218 +               return -EIO;
55219 +       }
55220 +
55221 +       /* Determine and validate the key index */
55222 +       idx = (encoding->flags & IW_ENCODE_INDEX) - 1;
55223 +       if (idx) {
55224 +               if (idx < 0 || idx > 3)
55225 +                       return -EINVAL;
55226 +       }
55227 +
55228 +       if ((alg == IW_ENCODE_ALG_TKIP) || (alg == IW_ENCODE_ALG_CCMP)) {
55229 +               struct ieee80211req_key ik;
55230 +               KEY_USAGE key_usage;
55231 +               CRYPTO_TYPE key_type = NONE_CRYPT;
55232 +               int status;
55233 +
55234 +               ar->user_saved_keys.keyOk = FALSE;
55235 +
55236 +               if (alg == IW_ENCODE_ALG_TKIP) {
55237 +                       key_type = TKIP_CRYPT;
55238 +                       ik.ik_type = IEEE80211_CIPHER_TKIP;
55239 +               } else {
55240 +                       key_type = AES_CRYPT;
55241 +                       ik.ik_type = IEEE80211_CIPHER_AES_CCM;
55242 +               }
55243 +
55244 +               ik.ik_keyix = idx;
55245 +               ik.ik_keylen = ext->key_len;
55246 +               ik.ik_flags = IEEE80211_KEY_RECV;
55247 +               if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
55248 +                       ik.ik_flags |= IEEE80211_KEY_XMIT
55249 +                               | IEEE80211_KEY_DEFAULT;
55250 +               }
55251 +
55252 +               if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
55253 +                       memcpy(&ik.ik_keyrsc, ext->rx_seq, 8);
55254 +               }
55255 +
55256 +               memcpy(ik.ik_keydata, ext->key, ext->key_len);
55257 +
55258 +               ar->user_saved_keys.keyType = key_type;
55259 +               if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
55260 +                       key_usage = GROUP_USAGE;
55261 +                       memset(ik.ik_macaddr, 0, ETH_ALEN);
55262 +                       memcpy(&ar->user_saved_keys.bcast_ik, &ik,
55263 +                              sizeof(struct ieee80211req_key));
55264 +               } else {
55265 +                       key_usage = PAIRWISE_USAGE;
55266 +                       memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN);
55267 +                       memcpy(&ar->user_saved_keys.ucast_ik, &ik,
55268 +                              sizeof(struct ieee80211req_key));
55269 +               }
55270 +
55271 +               status = wmi_addKey_cmd(ar->arWmi, ik.ik_keyix, key_type,
55272 +                                       key_usage, ik.ik_keylen,
55273 +                                       (A_UINT8 *)&ik.ik_keyrsc,
55274 +                                       ik.ik_keydata,
55275 +                                       KEY_OP_INIT_VAL, SYNC_BEFORE_WMIFLAG);
55276 +
55277 +               if (status < 0)
55278 +                       return -EIO;
55279 +
55280 +               ar->user_saved_keys.keyOk = TRUE;
55281 +
55282 +               return 0;
55283 +
55284 +       } else {
55285 +               /* WEP falls back to SIWENCODE */
55286 +               return -EOPNOTSUPP;
55287 +       }
55288 +
55289 +       return 0;
55290 +}
55291 +
55292 +
55293 +static int ar6000_ioctl_giwencodeext(struct net_device *dev,
55294 +                                    struct iw_request_info *info,
55295 +                                    struct iw_point *dwrq,
55296 +                                    char *extra)
55297 +{
55298 +       return 0;
55299 +}
55300 +
55301 +
55302 +static int
55303 +ar6000_ioctl_setparam(struct net_device *dev,
55304 +                      struct iw_request_info *info,
55305 +                      void *erq, char *extra)
55306 +{
55307 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55308 +    int *i = (int *)extra;
55309 +    int param = i[0];
55310 +    int value = i[1];
55311 +    int ret = 0;
55312 +    A_BOOL profChanged = FALSE;
55313 +
55314 +    if (ar->arWlanState == WLAN_DISABLED) {
55315 +        return -EIO;
55316 +    }
55317 +
55318 +    switch (param) {
55319 +        case IEEE80211_PARAM_WPA:
55320 +            switch (value) {
55321 +                case WPA_MODE_WPA1:
55322 +                    ar->arAuthMode = WPA_AUTH;
55323 +                    profChanged    = TRUE;
55324 +                    break;
55325 +                case WPA_MODE_WPA2:
55326 +                    ar->arAuthMode = WPA2_AUTH;
55327 +                    profChanged    = TRUE;
55328 +                    break;
55329 +                case WPA_MODE_NONE:
55330 +                    ar->arAuthMode = NONE_AUTH;
55331 +                    profChanged    = TRUE;
55332 +                    break;
55333 +           default:
55334 +                   printk("IEEE80211_PARAM_WPA: Unknown value %d\n", value);
55335 +            }
55336 +            break;
55337 +        case IEEE80211_PARAM_AUTHMODE:
55338 +            switch(value) {
55339 +                case IEEE80211_AUTH_WPA_PSK:
55340 +                    if (WPA_AUTH == ar->arAuthMode) {
55341 +                        ar->arAuthMode = WPA_PSK_AUTH;
55342 +                        profChanged    = TRUE;
55343 +                    } else if (WPA2_AUTH == ar->arAuthMode) {
55344 +                        ar->arAuthMode = WPA2_PSK_AUTH;
55345 +                        profChanged    = TRUE;
55346 +                    } else {
55347 +                        AR_DEBUG_PRINTF("Error -  Setting PSK mode when WPA "\
55348 +                                        "param was set to %d\n",
55349 +                                        ar->arAuthMode);
55350 +                        ret = -1;
55351 +                    }
55352 +                    break;
55353 +                case IEEE80211_AUTH_WPA_CCKM:
55354 +                    if (WPA2_AUTH == ar->arAuthMode) {
55355 +                        ar->arAuthMode = WPA2_AUTH_CCKM;
55356 +                    } else {
55357 +                        ar->arAuthMode = WPA_AUTH_CCKM;
55358 +                    }
55359 +                    break;
55360 +                default:
55361 +                    break;
55362 +            }
55363 +            break;
55364 +        case IEEE80211_PARAM_UCASTCIPHER:
55365 +            switch (value) {
55366 +                case IEEE80211_CIPHER_AES_CCM:
55367 +                    ar->arPairwiseCrypto = AES_CRYPT;
55368 +                    profChanged          = TRUE;
55369 +                    break;
55370 +                case IEEE80211_CIPHER_TKIP:
55371 +                    ar->arPairwiseCrypto = TKIP_CRYPT;
55372 +                    profChanged          = TRUE;
55373 +                    break;
55374 +                case IEEE80211_CIPHER_WEP:
55375 +                    ar->arPairwiseCrypto = WEP_CRYPT;
55376 +                    profChanged          = TRUE;
55377 +                    break;
55378 +                case IEEE80211_CIPHER_NONE:
55379 +                    ar->arPairwiseCrypto = NONE_CRYPT;
55380 +                    profChanged          = TRUE;
55381 +                    break;
55382 +            }
55383 +            break;
55384 +        case IEEE80211_PARAM_UCASTKEYLEN:
55385 +            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
55386 +                ret = -EIO;
55387 +            } else {
55388 +                ar->arPairwiseCryptoLen = value;
55389 +            }
55390 +            break;
55391 +        case IEEE80211_PARAM_MCASTCIPHER:
55392 +            switch (value) {
55393 +                case IEEE80211_CIPHER_AES_CCM:
55394 +                    ar->arGroupCrypto = AES_CRYPT;
55395 +                    profChanged       = TRUE;
55396 +                    break;
55397 +                case IEEE80211_CIPHER_TKIP:
55398 +                    ar->arGroupCrypto = TKIP_CRYPT;
55399 +                    profChanged       = TRUE;
55400 +                    break;
55401 +                case IEEE80211_CIPHER_WEP:
55402 +                    ar->arGroupCrypto = WEP_CRYPT;
55403 +                    profChanged       = TRUE;
55404 +                    break;
55405 +                case IEEE80211_CIPHER_NONE:
55406 +                    ar->arGroupCrypto = NONE_CRYPT;
55407 +                    profChanged       = TRUE;
55408 +                    break;
55409 +            }
55410 +            break;
55411 +        case IEEE80211_PARAM_MCASTKEYLEN:
55412 +            if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
55413 +                ret = -EIO;
55414 +            } else {
55415 +                ar->arGroupCryptoLen = value;
55416 +            }
55417 +            break;
55418 +        case IEEE80211_PARAM_COUNTERMEASURES:
55419 +            if (ar->arWmiReady == FALSE) {
55420 +                return -EIO;
55421 +            }
55422 +            wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
55423 +            break;
55424 +        default:
55425 +            break;
55426 +    }
55427 +
55428 +    if (profChanged == TRUE) {
55429 +        /*
55430 +         * profile has changed.  Erase ssid to signal change
55431 +         */
55432 +       A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
55433 +       ar->arSsidLen = 0;
55434 +    }
55435 +
55436 +    return ret;
55437 +}
55438 +
55439 +int
55440 +ar6000_ioctl_getparam(struct net_device *dev, struct iw_request_info *info,
55441 +            void *w, char *extra)
55442 +{
55443 +    return -EIO;            /* for now */
55444 +}
55445 +
55446 +int
55447 +ar6000_ioctl_setkey(struct net_device *dev, struct iw_request_info *info,
55448 +                   void *w, char *extra)
55449 +{
55450 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55451 +    struct ieee80211req_key *ik = (struct ieee80211req_key *)extra;
55452 +    KEY_USAGE keyUsage;
55453 +    A_STATUS status;
55454 +    CRYPTO_TYPE keyType = NONE_CRYPT;
55455 +
55456 +    if (ar->arWlanState == WLAN_DISABLED) {
55457 +        return -EIO;
55458 +    }
55459 +
55460 +    ar->user_saved_keys.keyOk = FALSE;
55461 +
55462 +    if ( 0 == memcmp(ik->ik_macaddr, "\x00\x00\x00\x00\x00\x00",
55463 +                     IEEE80211_ADDR_LEN)) {
55464 +        keyUsage = GROUP_USAGE;
55465 +        A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik,
55466 +                 sizeof(struct ieee80211req_key));
55467 +    } else {
55468 +        keyUsage = PAIRWISE_USAGE;
55469 +        A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik,
55470 +                 sizeof(struct ieee80211req_key));
55471 +    }
55472 +
55473 +    switch (ik->ik_type) {
55474 +        case IEEE80211_CIPHER_WEP:
55475 +            keyType = WEP_CRYPT;
55476 +            break;
55477 +        case IEEE80211_CIPHER_TKIP:
55478 +            keyType = TKIP_CRYPT;
55479 +            break;
55480 +        case IEEE80211_CIPHER_AES_CCM:
55481 +            keyType = AES_CRYPT;
55482 +            break;
55483 +        default:
55484 +            break;
55485 +    }
55486 +    ar->user_saved_keys.keyType = keyType;
55487 +
55488 +    if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
55489 +        if (NONE_CRYPT == keyType) {
55490 +            return -EIO;
55491 +        }
55492 +
55493 +        status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
55494 +                                ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
55495 +                                ik->ik_keydata, KEY_OP_INIT_VAL,
55496 +                                SYNC_BEFORE_WMIFLAG);
55497 +
55498 +        if (status != A_OK) {
55499 +            return -EIO;
55500 +        }
55501 +    } else {
55502 +        status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
55503 +    }
55504 +
55505 +    ar->user_saved_keys.keyOk = TRUE;
55506 +
55507 +    return 0;
55508 +}
55509 +
55510 +
55511 +/*
55512 + * SIOCGIWNAME
55513 + */
55514 +int
55515 +ar6000_ioctl_giwname(struct net_device *dev,
55516 +           struct iw_request_info *info,
55517 +           char *name, char *extra)
55518 +{
55519 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55520 +
55521 +    if (ar->arWlanState == WLAN_DISABLED) {
55522 +        return -EIO;
55523 +    }
55524 +
55525 +    switch (ar->arPhyCapability) {
55526 +    case (WMI_11A_CAPABILITY):
55527 +        strncpy(name, "AR6000 802.11a", IFNAMSIZ);
55528 +        break;
55529 +    case (WMI_11G_CAPABILITY):
55530 +        strncpy(name, "AR6000 802.11g", IFNAMSIZ);
55531 +        break;
55532 +    case (WMI_11AG_CAPABILITY):
55533 +        strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
55534 +        break;
55535 +    default:
55536 +        strncpy(name, "AR6000 802.11", IFNAMSIZ);
55537 +        break;
55538 +    }
55539 +
55540 +    return 0;
55541 +}
55542 +
55543 +/*
55544 + * SIOCSIWFREQ
55545 + */
55546 +int
55547 +ar6000_ioctl_siwfreq(struct net_device *dev,
55548 +            struct iw_request_info *info,
55549 +            struct iw_freq *freq, char *extra)
55550 +{
55551 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55552 +
55553 +    if (ar->arWlanState == WLAN_DISABLED) {
55554 +        return -EIO;
55555 +    }
55556 +
55557 +    /*
55558 +     * We support limiting the channels via wmiconfig.
55559 +     *
55560 +     * We use this command to configure the channel hint for the connect cmd
55561 +     * so it is possible the target will end up connecting to a different
55562 +     * channel.
55563 +     */
55564 +    if (freq->e > 1) {
55565 +        return -EINVAL;
55566 +    } else if (freq->e == 1) {
55567 +        ar->arChannelHint = freq->m / 100000;
55568 +    } else {
55569 +        ar->arChannelHint = wlan_ieee2freq(freq->m);
55570 +    }
55571 +
55572 +    A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
55573 +    return 0;
55574 +}
55575 +
55576 +/*
55577 + * SIOCGIWFREQ
55578 + */
55579 +int
55580 +ar6000_ioctl_giwfreq(struct net_device *dev,
55581 +                struct iw_request_info *info,
55582 +                struct iw_freq *freq, char *extra)
55583 +{
55584 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55585 +
55586 +    if (ar->arWlanState == WLAN_DISABLED) {
55587 +        return -EIO;
55588 +    }
55589 +
55590 +    if (ar->arConnected != TRUE) {
55591 +        return -EINVAL;
55592 +    }
55593 +
55594 +    freq->m = ar->arBssChannel * 100000;
55595 +    freq->e = 1;
55596 +
55597 +    return 0;
55598 +}
55599 +
55600 +/*
55601 + * SIOCSIWMODE
55602 + */
55603 +int
55604 +ar6000_ioctl_siwmode(struct net_device *dev,
55605 +            struct iw_request_info *info,
55606 +            __u32 *mode, char *extra)
55607 +{
55608 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55609 +
55610 +    if (ar->arWlanState == WLAN_DISABLED) {
55611 +        return -EIO;
55612 +    }
55613 +
55614 +    switch (*mode) {
55615 +    case IW_MODE_INFRA:
55616 +        ar->arNetworkType = INFRA_NETWORK;
55617 +        break;
55618 +    case IW_MODE_ADHOC:
55619 +        ar->arNetworkType = ADHOC_NETWORK;
55620 +        break;
55621 +    default:
55622 +        return -EINVAL;
55623 +    }
55624 +
55625 +    return 0;
55626 +}
55627 +
55628 +/*
55629 + * SIOCGIWMODE
55630 + */
55631 +int
55632 +ar6000_ioctl_giwmode(struct net_device *dev,
55633 +            struct iw_request_info *info,
55634 +            __u32 *mode, char *extra)
55635 +{
55636 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55637 +
55638 +    if (ar->arWlanState == WLAN_DISABLED) {
55639 +        return -EIO;
55640 +    }
55641 +
55642 +    switch (ar->arNetworkType) {
55643 +    case INFRA_NETWORK:
55644 +        *mode = IW_MODE_INFRA;
55645 +        break;
55646 +    case ADHOC_NETWORK:
55647 +        *mode = IW_MODE_ADHOC;
55648 +        break;
55649 +    default:
55650 +        return -EIO;
55651 +    }
55652 +    return 0;
55653 +}
55654 +
55655 +/*
55656 + * SIOCSIWSENS
55657 + */
55658 +int
55659 +ar6000_ioctl_siwsens(struct net_device *dev,
55660 +            struct iw_request_info *info,
55661 +            struct iw_param *sens, char *extra)
55662 +{
55663 +    return 0;
55664 +}
55665 +
55666 +/*
55667 + * SIOCGIWSENS
55668 + */
55669 +int
55670 +ar6000_ioctl_giwsens(struct net_device *dev,
55671 +            struct iw_request_info *info,
55672 +            struct iw_param *sens, char *extra)
55673 +{
55674 +    sens->value = 0;
55675 +    sens->fixed = 1;
55676 +
55677 +    return 0;
55678 +}
55679 +
55680 +/*
55681 + * SIOCGIWRANGE
55682 + */
55683 +int
55684 +ar6000_ioctl_giwrange(struct net_device *dev,
55685 +             struct iw_request_info *info,
55686 +             struct iw_point *data, char *extra)
55687 +{
55688 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55689 +    struct iw_range *range = (struct iw_range *) extra;
55690 +    int i, ret = 0;
55691 +
55692 +    if (ar->arWmiReady == FALSE) {
55693 +        return -EIO;
55694 +    }
55695 +
55696 +    if (ar->arWlanState == WLAN_DISABLED) {
55697 +        return -EIO;
55698 +    }
55699 +
55700 +    if (down_interruptible(&ar->arSem)) {
55701 +        return -ERESTARTSYS;
55702 +    }
55703 +    ar->arNumChannels = -1;
55704 +    A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
55705 +
55706 +    if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
55707 +        up(&ar->arSem);
55708 +        return -EIO;
55709 +    }
55710 +
55711 +    wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ);
55712 +
55713 +    if (signal_pending(current)) {
55714 +        up(&ar->arSem);
55715 +        return -EINTR;
55716 +    }
55717 +
55718 +    data->length = sizeof(struct iw_range);
55719 +    A_MEMZERO(range, sizeof(struct iw_range));
55720 +
55721 +    range->txpower_capa = IW_TXPOW_DBM;
55722 +
55723 +    range->min_pmp = 1 * 1024;
55724 +    range->max_pmp = 65535 * 1024;
55725 +    range->min_pmt = 1 * 1024;
55726 +    range->max_pmt = 1000 * 1024;
55727 +    range->pmp_flags = IW_POWER_PERIOD;
55728 +    range->pmt_flags = IW_POWER_TIMEOUT;
55729 +    range->pm_capa = 0;
55730 +
55731 +    range->we_version_compiled = WIRELESS_EXT;
55732 +    range->we_version_source = 13;
55733 +
55734 +    range->retry_capa = IW_RETRY_LIMIT;
55735 +    range->retry_flags = IW_RETRY_LIMIT;
55736 +    range->min_retry = 0;
55737 +    range->max_retry = 255;
55738 +
55739 +    range->num_frequency = range->num_channels = ar->arNumChannels;
55740 +    for (i = 0; i < ar->arNumChannels; i++) {
55741 +        range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
55742 +        range->freq[i].m = ar->arChannelList[i] * 100000;
55743 +        range->freq[i].e = 1;
55744 +         /*
55745 +         * Linux supports max of 32 channels, bail out once you
55746 +         * reach the max.
55747 +         */
55748 +        if (i == IW_MAX_FREQUENCIES) {
55749 +            break;
55750 +        }
55751 +    }
55752 +
55753 +    /* Max quality is max field value minus noise floor */
55754 +    range->max_qual.qual  = 0xff - 161;
55755 +
55756 +    /*
55757 +     * In order to use dBm measurements, 'level' must be lower
55758 +     * than any possible measurement (see iw_print_stats() in
55759 +     * wireless tools).  It's unclear how this is meant to be
55760 +     * done, but setting zero in these values forces dBm and
55761 +     * the actual numbers are not used.
55762 +     */
55763 +    range->max_qual.level = 0;
55764 +    range->max_qual.noise = 0;
55765 +
55766 +    range->sensitivity = 3;
55767 +
55768 +    range->max_encoding_tokens = 4;
55769 +    /* XXX query driver to find out supported key sizes */
55770 +    range->num_encoding_sizes = 3;
55771 +    range->encoding_size[0] = 5;        /* 40-bit */
55772 +    range->encoding_size[1] = 13;       /* 104-bit */
55773 +    range->encoding_size[2] = 16;       /* 128-bit */
55774 +
55775 +    range->num_bitrates = 0;
55776 +
55777 +    /* estimated maximum TCP throughput values (bps) */
55778 +    range->throughput = 22000000;
55779 +
55780 +    range->min_rts = 0;
55781 +    range->max_rts = 2347;
55782 +    range->min_frag = 256;
55783 +    range->max_frag = 2346;
55784 +
55785 +    up(&ar->arSem);
55786 +
55787 +    return ret;
55788 +}
55789 +
55790 +
55791 +/*
55792 + * SIOCSIWAP
55793 + * This ioctl is used to set the desired bssid for the connect command.
55794 + */
55795 +int
55796 +ar6000_ioctl_siwap(struct net_device *dev,
55797 +              struct iw_request_info *info,
55798 +              struct sockaddr *ap_addr, char *extra)
55799 +{
55800 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55801 +
55802 +    if (ar->arWlanState == WLAN_DISABLED) {
55803 +        return -EIO;
55804 +    }
55805 +
55806 +    if (ap_addr->sa_family != ARPHRD_ETHER) {
55807 +        return -EIO;
55808 +    }
55809 +
55810 +    if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
55811 +        A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
55812 +    } else {
55813 +        A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data,  sizeof(ar->arReqBssid));
55814 +    }
55815 +
55816 +    return 0;
55817 +}
55818 +
55819 +/*
55820 + * SIOCGIWAP
55821 + */
55822 +int
55823 +ar6000_ioctl_giwap(struct net_device *dev,
55824 +              struct iw_request_info *info,
55825 +              struct sockaddr *ap_addr, char *extra)
55826 +{
55827 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55828 +
55829 +    if (ar->arWlanState == WLAN_DISABLED) {
55830 +        return -EIO;
55831 +    }
55832 +
55833 +    if (ar->arConnected != TRUE) {
55834 +        return -EINVAL;
55835 +    }
55836 +
55837 +    A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
55838 +    ap_addr->sa_family = ARPHRD_ETHER;
55839 +
55840 +    return 0;
55841 +}
55842 +
55843 +/*
55844 + * SIOCGIWAPLIST
55845 + */
55846 +int
55847 +ar6000_ioctl_iwaplist(struct net_device *dev,
55848 +            struct iw_request_info *info,
55849 +            struct iw_point *data, char *extra)
55850 +{
55851 +    return -EIO;            /* for now */
55852 +}
55853 +
55854 +/*
55855 + * SIOCSIWSCAN
55856 + */
55857 +int
55858 +ar6000_ioctl_siwscan(struct net_device *dev,
55859 +                     struct iw_request_info *info,
55860 +                     struct iw_point *data, char *extra)
55861 +{
55862 +#define ACT_DWELLTIME_DEFAULT   105
55863 +#define HOME_TXDRAIN_TIME       100
55864 +#define SCAN_INT                HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT
55865 +    AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
55866 +    int ret = 0;
55867 +
55868 +    if (ar->arWmiReady == FALSE) {
55869 +        return -EIO;
55870 +    }
55871 +
55872 +    if (ar->arWlanState == WLAN_DISABLED) {
55873 +        return -EIO;
55874 +    }
55875 +
55876 +    /* We ask for everything from the target */
55877 +    if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
55878 +           printk("Couldn't set filtering\n");
55879 +           ret = -EIO;
55880 +    }
55881 +
55882 +    if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \
55883 +                          HOME_TXDRAIN_TIME, SCAN_INT) != A_OK) {
55884 +        ret = -EIO;
55885 +    }
55886 +
55887 +    ar->scan_complete = 0;
55888 +    wait_event_interruptible_timeout(ar6000_scan_queue, ar->scan_complete,
55889 +                                    5 * HZ);
55890 +
55891 +    if (wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0) != A_OK) {
55892 +           printk("Couldn't set filtering\n");
55893 +           ret = -EIO;
55894 +    }
55895 +
55896 +    return ret;
55897 +#undef  ACT_DWELLTIME_DEFAULT
55898 +#undef HOME_TXDRAIN_TIME
55899 +#undef SCAN_INT
55900 +}
55901 +
55902 +
55903 +/*
55904 + * Units are in db above the noise floor. That means the
55905 + * rssi values reported in the tx/rx descriptors in the
55906 + * driver are the SNR expressed in db.
55907 + *
55908 + * If you assume that the noise floor is -95, which is an
55909 + * excellent assumption 99.5 % of the time, then you can
55910 + * derive the absolute signal level (i.e. -95 + rssi).
55911 + * There are some other slight factors to take into account
55912 + * depending on whether the rssi measurement is from 11b,
55913 + * 11g, or 11a.   These differences are at most 2db and
55914 + * can be documented.
55915 + *
55916 + * NB: various calculations are based on the orinoco/wavelan
55917 + *     drivers for compatibility
55918 + */
55919 +static void
55920 +ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi)
55921 +{
55922 +    if (rssi < 0) {
55923 +        iq->qual = 0;
55924 +    } else {
55925 +        iq->qual = rssi;
55926 +    }
55927 +
55928 +    /* NB: max is 94 because noise is hardcoded to 161 */
55929 +    if (iq->qual > 94)
55930 +        iq->qual = 94;
55931 +
55932 +    iq->noise = 161;        /* -95dBm */
55933 +    iq->level = iq->noise + iq->qual;
55934 +    iq->updated = 7;
55935 +}
55936 +
55937 +
55938 +/* Structures to export the Wireless Handlers */
55939 +static const iw_handler ath_handlers[] = {
55940 +    (iw_handler) NULL,                          /* SIOCSIWCOMMIT */
55941 +    (iw_handler) ar6000_ioctl_giwname,          /* SIOCGIWNAME */
55942 +    (iw_handler) NULL,                          /* SIOCSIWNWID */
55943 +    (iw_handler) NULL,                          /* SIOCGIWNWID */
55944 +    (iw_handler) ar6000_ioctl_siwfreq,          /* SIOCSIWFREQ */
55945 +    (iw_handler) ar6000_ioctl_giwfreq,          /* SIOCGIWFREQ */
55946 +    (iw_handler) ar6000_ioctl_siwmode,          /* SIOCSIWMODE */
55947 +    (iw_handler) ar6000_ioctl_giwmode,          /* SIOCGIWMODE */
55948 +    (iw_handler) ar6000_ioctl_siwsens,          /* SIOCSIWSENS */
55949 +    (iw_handler) ar6000_ioctl_giwsens,          /* SIOCGIWSENS */
55950 +    (iw_handler) NULL /* not _used */,          /* SIOCSIWRANGE */
55951 +    (iw_handler) ar6000_ioctl_giwrange,         /* SIOCGIWRANGE */
55952 +    (iw_handler) NULL /* not used */,           /* SIOCSIWPRIV */
55953 +    (iw_handler) NULL /* kernel code */,        /* SIOCGIWPRIV */
55954 +    (iw_handler) NULL /* not used */,           /* SIOCSIWSTATS */
55955 +    (iw_handler) NULL /* kernel code */,        /* SIOCGIWSTATS */
55956 +    (iw_handler) NULL,                          /* SIOCSIWSPY */
55957 +    (iw_handler) NULL,                          /* SIOCGIWSPY */
55958 +    (iw_handler) NULL,                          /* SIOCSIWTHRSPY */
55959 +    (iw_handler) NULL,                          /* SIOCGIWTHRSPY */
55960 +    (iw_handler) ar6000_ioctl_siwap,            /* SIOCSIWAP */
55961 +    (iw_handler) ar6000_ioctl_giwap,            /* SIOCGIWAP */
55962 +    (iw_handler) NULL,                          /* -- hole -- */
55963 +    (iw_handler) ar6000_ioctl_iwaplist,         /* SIOCGIWAPLIST */
55964 +    (iw_handler) ar6000_ioctl_siwscan,          /* SIOCSIWSCAN */
55965 +    (iw_handler) ar6000_ioctl_giwscan,          /* SIOCGIWSCAN */
55966 +    (iw_handler) ar6000_ioctl_siwessid,         /* SIOCSIWESSID */
55967 +    (iw_handler) ar6000_ioctl_giwessid,         /* SIOCGIWESSID */
55968 +    (iw_handler) NULL,                          /* SIOCSIWNICKN */
55969 +    (iw_handler) NULL,                          /* SIOCGIWNICKN */
55970 +    (iw_handler) NULL,                          /* -- hole -- */
55971 +    (iw_handler) NULL,                          /* -- hole -- */
55972 +    (iw_handler) ar6000_ioctl_siwrate,          /* SIOCSIWRATE */
55973 +    (iw_handler) ar6000_ioctl_giwrate,          /* SIOCGIWRATE */
55974 +    (iw_handler) NULL,           /* SIOCSIWRTS */
55975 +    (iw_handler) NULL,           /* SIOCGIWRTS */
55976 +    (iw_handler) NULL,          /* SIOCSIWFRAG */
55977 +    (iw_handler) NULL,          /* SIOCGIWFRAG */
55978 +    (iw_handler) ar6000_ioctl_siwtxpow,         /* SIOCSIWTXPOW */
55979 +    (iw_handler) ar6000_ioctl_giwtxpow,         /* SIOCGIWTXPOW */
55980 +    (iw_handler) ar6000_ioctl_siwretry,         /* SIOCSIWRETRY */
55981 +    (iw_handler) ar6000_ioctl_giwretry,         /* SIOCGIWRETRY */
55982 +    (iw_handler) ar6000_ioctl_siwencode,        /* SIOCSIWENCODE */
55983 +    (iw_handler) ar6000_ioctl_giwencode,        /* SIOCGIWENCODE */
55984 +    (iw_handler) ar6000_ioctl_siwpower,         /* SIOCSIWPOWER */
55985 +    (iw_handler) ar6000_ioctl_giwpower,         /* SIOCGIWPOWER */
55986 +    (iw_handler) NULL, /* -- hole -- */
55987 +    (iw_handler) NULL, /* -- hole -- */
55988 +    (iw_handler) ar6000_ioctl_siwgenie,        /* SIOCSIWGENIE */
55989 +    (iw_handler) ar6000_ioctl_giwgenie,        /* SIOCGIWGENIE */
55990 +    (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */
55991 +    (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */
55992 +    (iw_handler) ar6000_ioctl_siwencodeext,/* SIOCSIWENCODEEXT */
55993 +    (iw_handler) ar6000_ioctl_giwencodeext,/* SIOCGIWENCODEEXT */
55994 +    (iw_handler) NULL,         /* SIOCSIWPMKSA */
55995 +};
55996 +
55997 +static const iw_handler ath_priv_handlers[] = {
55998 +    (iw_handler) ar6000_ioctl_setparam,         /* SIOCWFIRSTPRIV+0 */
55999 +    (iw_handler) ar6000_ioctl_getparam,         /* SIOCWFIRSTPRIV+1 */
56000 +    (iw_handler) ar6000_ioctl_setkey,           /* SIOCWFIRSTPRIV+2 */
56001 +    (iw_handler) ar6000_ioctl_setwmmparams,     /* SIOCWFIRSTPRIV+3 */
56002 +    (iw_handler) ar6000_ioctl_delkey,           /* SIOCWFIRSTPRIV+4 */
56003 +    (iw_handler) ar6000_ioctl_getwmmparams,     /* SIOCWFIRSTPRIV+5 */
56004 +    (iw_handler) ar6000_ioctl_setoptie,         /* SIOCWFIRSTPRIV+6 */
56005 +    (iw_handler) ar6000_ioctl_setmlme,          /* SIOCWFIRSTPRIV+7 */
56006 +    (iw_handler) ar6000_ioctl_addpmkid,         /* SIOCWFIRSTPRIV+8 */
56007 +};
56008 +
56009 +#define IW_PRIV_TYPE_KEY \
56010 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_key))
56011 +#define IW_PRIV_TYPE_DELKEY \
56012 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_del_key))
56013 +#define IW_PRIV_TYPE_MLME \
56014 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_mlme))
56015 +#define IW_PRIV_TYPE_ADDPMKID \
56016 +    (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_addpmkid))
56017 +
56018 +static const struct iw_priv_args ar6000_priv_args[] = {
56019 +    { IEEE80211_IOCTL_SETKEY,
56020 +      IW_PRIV_TYPE_KEY | IW_PRIV_SIZE_FIXED, 0,       "setkey"},
56021 +    { IEEE80211_IOCTL_DELKEY,
56022 +      IW_PRIV_TYPE_DELKEY | IW_PRIV_SIZE_FIXED, 0,    "delkey"},
56023 +    { IEEE80211_IOCTL_SETPARAM,
56024 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0,   "setparam"},
56025 +    { IEEE80211_IOCTL_GETPARAM,
56026 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
56027 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,      "getparam"},
56028 +    { IEEE80211_IOCTL_SETWMMPARAMS,
56029 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 4, 0,   "setwmmparams"},
56030 +    { IEEE80211_IOCTL_GETWMMPARAMS,
56031 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3,
56032 +      IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,      "getwmmparams"},
56033 +    { IEEE80211_IOCTL_SETOPTIE,
56034 +      IW_PRIV_TYPE_BYTE, 0,       "setie"},
56035 +    { IEEE80211_IOCTL_SETMLME,
56036 +      IW_PRIV_TYPE_MLME, 0,       "setmlme"},
56037 +    { IEEE80211_IOCTL_ADDPMKID,
56038 +      IW_PRIV_TYPE_ADDPMKID | IW_PRIV_SIZE_FIXED, 0,  "addpmkid"},
56039 +};
56040 +
56041 +void ar6000_ioctl_iwsetup(struct iw_handler_def *def)
56042 +{
56043 +    def->private_args = (struct iw_priv_args *)ar6000_priv_args;
56044 +    def->num_private_args = ARRAY_SIZE(ar6000_priv_args);
56045 +}
56046 +
56047 +struct iw_handler_def ath_iw_handler_def = {
56048 +    .standard         = (iw_handler *)ath_handlers,
56049 +    .num_standard     = ARRAY_SIZE(ath_handlers),
56050 +    .private          = (iw_handler *)ath_priv_handlers,
56051 +    .num_private      = ARRAY_SIZE(ath_priv_handlers),
56052 +};
56053 +
56054 +
56055 Index: linux-2.6.28/drivers/ar6000/bmi/bmi.c
56056 ===================================================================
56057 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
56058 +++ linux-2.6.28/drivers/ar6000/bmi/bmi.c       2009-01-02 00:01:56.000000000 +0100
56059 @@ -0,0 +1,657 @@
56060 +/*
56061 + * Copyright (c) 2004-2007 Atheros Communications Inc.
56062 + * All rights reserved.
56063 + *
56064 + *
56065 + *  This program is free software; you can redistribute it and/or modify
56066 + *  it under the terms of the GNU General Public License version 2 as
56067 + *  published by the Free Software Foundation;
56068 + *
56069 + *  Software distributed under the License is distributed on an "AS
56070 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
56071 + *  implied. See the License for the specific language governing
56072 + *  rights and limitations under the License.
56073 + *
56074 + *
56075 + *
56076 + */
56077 +
56078 +#include "hif.h"
56079 +#include "bmi.h"
56080 +#include "htc_api.h"
56081 +#include "bmi_internal.h"
56082 +
56083 +/*
56084 +Although we had envisioned BMI to run on top of HTC, this is not what the
56085 +final implementation boiled down to on dragon. Its a part of BSP and does
56086 +not use the HTC protocol either. On the host side, however, we were still
56087 +living with the original idea. I think the time has come to accept the truth
56088 +and separate it from HTC which has been carrying BMI's burden all this while.
56089 +It shall make HTC state machine relatively simpler
56090 +*/
56091 +
56092 +/* APIs visible to the driver */
56093 +void
56094 +BMIInit(void)
56095 +{
56096 +    bmiDone = FALSE;
56097 +}
56098 +
56099 +A_STATUS
56100 +BMIDone(HIF_DEVICE *device)
56101 +{
56102 +    A_STATUS status;
56103 +    A_UINT32 cid;
56104 +
56105 +    if (bmiDone) {
56106 +        AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n"));
56107 +        return A_OK;
56108 +    }
56109 +
56110 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device));
56111 +    bmiDone = TRUE;
56112 +    cid = BMI_DONE;
56113 +
56114 +    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
56115 +    if (status != A_OK) {
56116 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56117 +        return A_ERROR;
56118 +    }
56119 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n"));
56120 +
56121 +    return A_OK;
56122 +}
56123 +
56124 +A_STATUS
56125 +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info)
56126 +{
56127 +    A_STATUS status;
56128 +    A_UINT32 cid;
56129 +
56130 +    if (bmiDone) {
56131 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56132 +        return A_ERROR;
56133 +    }
56134 +
56135 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device));
56136 +    cid = BMI_GET_TARGET_INFO;
56137 +
56138 +    status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
56139 +    if (status != A_OK) {
56140 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56141 +        return A_ERROR;
56142 +    }
56143 +
56144 +    status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver,
56145 +                                                sizeof(targ_info->target_ver));
56146 +    if (status != A_OK) {
56147 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n"));
56148 +        return A_ERROR;
56149 +    }
56150 +
56151 +    if (targ_info->target_ver == TARGET_VERSION_SENTINAL) {
56152 +        /* Determine how many bytes are in the Target's targ_info */
56153 +        status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count,
56154 +                                            sizeof(targ_info->target_info_byte_count));
56155 +        if (status != A_OK) {
56156 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n"));
56157 +            return A_ERROR;
56158 +        }
56159 +
56160 +        /*
56161 +         * The Target's targ_info doesn't match the Host's targ_info.
56162 +         * We need to do some backwards compatibility work to make this OK.
56163 +         */
56164 +        A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info));
56165 +
56166 +        /* Read the remainder of the targ_info */
56167 +        status = bmiBufferReceive(device,
56168 +                        ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count),
56169 +                        sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count));
56170 +        if (status != A_OK) {
56171 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n",
56172 +                                                               targ_info->target_info_byte_count));
56173 +            return A_ERROR;
56174 +        }
56175 +    } else {
56176 +        /*
56177 +         * Target must be an AR6001 whose firmware does not
56178 +         * support BMI_GET_TARGET_INFO.  Construct the data
56179 +         * that it would have sent.
56180 +         */
56181 +        targ_info->target_info_byte_count = sizeof(targ_info);
56182 +        targ_info->target_type = TARGET_TYPE_AR6001;
56183 +    }
56184 +
56185 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
56186 +                                                               targ_info->target_ver, targ_info->target_type));
56187 +    printk("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
56188 +          targ_info->target_ver, targ_info->target_type);
56189 +
56190 +    return A_OK;
56191 +}
56192 +
56193 +A_STATUS
56194 +BMIReadMemory(HIF_DEVICE *device,
56195 +              A_UINT32 address,
56196 +              A_UCHAR *buffer,
56197 +              A_UINT32 length)
56198 +{
56199 +    A_UINT32 cid;
56200 +    A_STATUS status;
56201 +    A_UINT32 offset;
56202 +    A_UINT32 remaining, rxlen;
56203 +    static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)];
56204 +    memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length));
56205 +
56206 +    if (bmiDone) {
56207 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56208 +        return A_ERROR;
56209 +    }
56210 +
56211 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56212 +                               ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
56213 +                               device, address, length));
56214 +
56215 +    cid = BMI_READ_MEMORY;
56216 +
56217 +    remaining = length;
56218 +
56219 +    while (remaining)
56220 +    {
56221 +        rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
56222 +        offset = 0;
56223 +        A_MEMCPY(&data[offset], &cid, sizeof(cid));
56224 +        offset += sizeof(cid);
56225 +        A_MEMCPY(&data[offset], &address, sizeof(address));
56226 +        offset += sizeof(address);
56227 +        A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen));
56228 +        offset += sizeof(length);
56229 +
56230 +        status = bmiBufferSend(device, data, offset);
56231 +        if (status != A_OK) {
56232 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56233 +            return A_ERROR;
56234 +        }
56235 +        status = bmiBufferReceive(device, data, rxlen);
56236 +        if (status != A_OK) {
56237 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
56238 +            return A_ERROR;
56239 +        }
56240 +        A_MEMCPY(&buffer[length - remaining], data, rxlen);
56241 +        remaining -= rxlen; address += rxlen;
56242 +    }
56243 +
56244 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n"));
56245 +    return A_OK;
56246 +}
56247 +
56248 +A_STATUS
56249 +BMIWriteMemory(HIF_DEVICE *device,
56250 +               A_UINT32 address,
56251 +               A_UCHAR *buffer,
56252 +               A_UINT32 length)
56253 +{
56254 +    A_UINT32 cid;
56255 +    A_STATUS status;
56256 +    A_UINT32 offset;
56257 +    A_UINT32 remaining, txlen;
56258 +    const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
56259 +    static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)];
56260 +       memset (&data, 0, header);
56261 +
56262 +    if (bmiDone) {
56263 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56264 +        return A_ERROR;
56265 +    }
56266 +
56267 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56268 +         ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
56269 +         device, address, length));
56270 +
56271 +    cid = BMI_WRITE_MEMORY;
56272 +
56273 +    remaining = length;
56274 +    while (remaining)
56275 +    {
56276 +        txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
56277 +                                       remaining : (BMI_DATASZ_MAX - header);
56278 +        offset = 0;
56279 +        A_MEMCPY(&data[offset], &cid, sizeof(cid));
56280 +        offset += sizeof(cid);
56281 +        A_MEMCPY(&data[offset], &address, sizeof(address));
56282 +        offset += sizeof(address);
56283 +        A_MEMCPY(&data[offset], &txlen, sizeof(txlen));
56284 +        offset += sizeof(txlen);
56285 +        A_MEMCPY(&data[offset], &buffer[length - remaining], txlen);
56286 +        offset += txlen;
56287 +        status = bmiBufferSend(device, data, offset);
56288 +        if (status != A_OK) {
56289 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56290 +            return A_ERROR;
56291 +        }
56292 +        remaining -= txlen; address += txlen;
56293 +    }
56294 +
56295 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n"));
56296 +
56297 +    return A_OK;
56298 +}
56299 +
56300 +A_STATUS
56301 +BMIExecute(HIF_DEVICE *device,
56302 +           A_UINT32 address,
56303 +           A_UINT32 *param)
56304 +{
56305 +    A_UINT32 cid;
56306 +    A_STATUS status;
56307 +    A_UINT32 offset;
56308 +    static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(*param)];
56309 +    memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(*param));
56310 +
56311 +    if (bmiDone) {
56312 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56313 +        return A_ERROR;
56314 +    }
56315 +
56316 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56317 +       ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
56318 +        device, address, *param));
56319 +
56320 +    cid = BMI_EXECUTE;
56321 +
56322 +    offset = 0;
56323 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56324 +    offset += sizeof(cid);
56325 +    A_MEMCPY(&data[offset], &address, sizeof(address));
56326 +    offset += sizeof(address);
56327 +    A_MEMCPY(&data[offset], param, sizeof(*param));
56328 +    offset += sizeof(*param);
56329 +    status = bmiBufferSend(device, data, offset);
56330 +    if (status != A_OK) {
56331 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56332 +        return A_ERROR;
56333 +    }
56334 +
56335 +    status = bmiBufferReceive(device, data, sizeof(*param));
56336 +    if (status != A_OK) {
56337 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
56338 +        return A_ERROR;
56339 +    }
56340 +
56341 +    A_MEMCPY(param, data, sizeof(*param));
56342 +
56343 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param));
56344 +    return A_OK;
56345 +}
56346 +
56347 +A_STATUS
56348 +BMISetAppStart(HIF_DEVICE *device,
56349 +               A_UINT32 address)
56350 +{
56351 +    A_UINT32 cid;
56352 +    A_STATUS status;
56353 +    A_UINT32 offset;
56354 +    static A_UCHAR data[sizeof(cid) + sizeof(address)];
56355 +    memset (&data, 0, sizeof(cid) + sizeof(address));
56356 +
56357 +    if (bmiDone) {
56358 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56359 +        return A_ERROR;
56360 +    }
56361 +
56362 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56363 +       ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
56364 +        device, address));
56365 +
56366 +    cid = BMI_SET_APP_START;
56367 +
56368 +    offset = 0;
56369 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56370 +    offset += sizeof(cid);
56371 +    A_MEMCPY(&data[offset], &address, sizeof(address));
56372 +    offset += sizeof(address);
56373 +    status = bmiBufferSend(device, data, offset);
56374 +    if (status != A_OK) {
56375 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56376 +        return A_ERROR;
56377 +    }
56378 +
56379 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n"));
56380 +    return A_OK;
56381 +}
56382 +
56383 +A_STATUS
56384 +BMIReadSOCRegister(HIF_DEVICE *device,
56385 +                   A_UINT32 address,
56386 +                   A_UINT32 *param)
56387 +{
56388 +    A_UINT32 cid;
56389 +    A_STATUS status;
56390 +    A_UINT32 offset;
56391 +    static A_UCHAR data[sizeof(cid) + sizeof(address)];
56392 +    memset (&data, 0, sizeof(cid) + sizeof(address));
56393 +
56394 +    if (bmiDone) {
56395 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56396 +        return A_ERROR;
56397 +    }
56398 +
56399 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56400 +       ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
56401 +       device, address));
56402 +
56403 +    cid = BMI_READ_SOC_REGISTER;
56404 +
56405 +    offset = 0;
56406 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56407 +    offset += sizeof(cid);
56408 +    A_MEMCPY(&data[offset], &address, sizeof(address));
56409 +    offset += sizeof(address);
56410 +
56411 +    status = bmiBufferSend(device, data, offset);
56412 +    if (status != A_OK) {
56413 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56414 +        return A_ERROR;
56415 +    }
56416 +
56417 +    status = bmiBufferReceive(device, data, sizeof(*param));
56418 +    if (status != A_OK) {
56419 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
56420 +        return A_ERROR;
56421 +    }
56422 +    A_MEMCPY(param, data, sizeof(*param));
56423 +
56424 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param));
56425 +    return A_OK;
56426 +}
56427 +
56428 +A_STATUS
56429 +BMIWriteSOCRegister(HIF_DEVICE *device,
56430 +                    A_UINT32 address,
56431 +                    A_UINT32 param)
56432 +{
56433 +    A_UINT32 cid;
56434 +    A_STATUS status;
56435 +    A_UINT32 offset;
56436 +    static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(param)];
56437 +
56438 +    memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(param));
56439 +
56440 +    if (bmiDone) {
56441 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56442 +        return A_ERROR;
56443 +    }
56444 +
56445 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56446 +     ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
56447 +     device, address, param));
56448 +
56449 +    cid = BMI_WRITE_SOC_REGISTER;
56450 +
56451 +    offset = 0;
56452 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56453 +    offset += sizeof(cid);
56454 +    A_MEMCPY(&data[offset], &address, sizeof(address));
56455 +    offset += sizeof(address);
56456 +    A_MEMCPY(&data[offset], &param, sizeof(param));
56457 +    offset += sizeof(param);
56458 +    status = bmiBufferSend(device, data, offset);
56459 +    if (status != A_OK) {
56460 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56461 +        return A_ERROR;
56462 +    }
56463 +
56464 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n"));
56465 +    return A_OK;
56466 +}
56467 +
56468 +A_STATUS
56469 +BMIrompatchInstall(HIF_DEVICE *device,
56470 +                   A_UINT32 ROM_addr,
56471 +                   A_UINT32 RAM_addr,
56472 +                   A_UINT32 nbytes,
56473 +                   A_UINT32 do_activate,
56474 +                   A_UINT32 *rompatch_id)
56475 +{
56476 +    A_UINT32 cid;
56477 +    A_STATUS status;
56478 +    A_UINT32 offset;
56479 +    static A_UCHAR data[sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
56480 +                                sizeof(nbytes) + sizeof(do_activate)];
56481 +
56482 +       memset (&data, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
56483 +                      sizeof(nbytes) + sizeof(do_activate));
56484 +
56485 +    if (bmiDone) {
56486 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56487 +        return A_ERROR;
56488 +    }
56489 +
56490 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56491 +         ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n",
56492 +         device, ROM_addr, RAM_addr, nbytes, do_activate));
56493 +
56494 +    cid = BMI_ROMPATCH_INSTALL;
56495 +
56496 +    offset = 0;
56497 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56498 +    offset += sizeof(cid);
56499 +    A_MEMCPY(&data[offset], &ROM_addr, sizeof(ROM_addr));
56500 +    offset += sizeof(ROM_addr);
56501 +    A_MEMCPY(&data[offset], &RAM_addr, sizeof(RAM_addr));
56502 +    offset += sizeof(RAM_addr);
56503 +    A_MEMCPY(&data[offset], &nbytes, sizeof(nbytes));
56504 +    offset += sizeof(nbytes);
56505 +    A_MEMCPY(&data[offset], &do_activate, sizeof(do_activate));
56506 +    offset += sizeof(do_activate);
56507 +    status = bmiBufferSend(device, data, offset);
56508 +    if (status != A_OK) {
56509 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56510 +        return A_ERROR;
56511 +    }
56512 +
56513 +    status = bmiBufferReceive(device, (A_UCHAR *)rompatch_id, sizeof(*rompatch_id));
56514 +    if (status != A_OK) {
56515 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
56516 +        return A_ERROR;
56517 +    }
56518 +
56519 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id));
56520 +    return A_OK;
56521 +}
56522 +
56523 +A_STATUS
56524 +BMIrompatchUninstall(HIF_DEVICE *device,
56525 +                     A_UINT32 rompatch_id)
56526 +{
56527 +    A_UINT32 cid;
56528 +    A_STATUS status;
56529 +    A_UINT32 offset;
56530 +    static A_UCHAR data[sizeof(cid) + sizeof(rompatch_id)];
56531 +    memset (&data, 0, sizeof(cid) + sizeof(rompatch_id));
56532 +
56533 +    if (bmiDone) {
56534 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56535 +        return A_ERROR;
56536 +    }
56537 +
56538 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56539 +         ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n",
56540 +                                                                        device, rompatch_id));
56541 +
56542 +    cid = BMI_ROMPATCH_UNINSTALL;
56543 +
56544 +    offset = 0;
56545 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56546 +    offset += sizeof(cid);
56547 +    A_MEMCPY(&data[offset], &rompatch_id, sizeof(rompatch_id));
56548 +    offset += sizeof(rompatch_id);
56549 +    status = bmiBufferSend(device, data, offset);
56550 +    if (status != A_OK) {
56551 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56552 +        return A_ERROR;
56553 +    }
56554 +
56555 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id));
56556 +    return A_OK;
56557 +}
56558 +
56559 +static A_STATUS
56560 +_BMIrompatchChangeActivation(HIF_DEVICE *device,
56561 +                             A_UINT32 rompatch_count,
56562 +                             A_UINT32 *rompatch_list,
56563 +                             A_UINT32 do_activate)
56564 +{
56565 +    A_UINT32 cid;
56566 +    A_STATUS status;
56567 +    A_UINT32 offset;
56568 +    static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)];
56569 +    A_UINT32 length;
56570 +
56571 +       memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count));
56572 +
56573 +    if (bmiDone) {
56574 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
56575 +        return A_ERROR;
56576 +    }
56577 +
56578 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
56579 +         ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n",
56580 +           device, rompatch_count));
56581 +
56582 +    cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE;
56583 +
56584 +    offset = 0;
56585 +    A_MEMCPY(&data[offset], &cid, sizeof(cid));
56586 +    offset += sizeof(cid);
56587 +    A_MEMCPY(&data[offset], &rompatch_count, sizeof(rompatch_count));
56588 +    offset += sizeof(rompatch_count);
56589 +    length = rompatch_count * sizeof(*rompatch_list);
56590 +    A_MEMCPY(&data[offset], rompatch_list, length);
56591 +    offset += length;
56592 +    status = bmiBufferSend(device, data, offset);
56593 +    if (status != A_OK) {
56594 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
56595 +        return A_ERROR;
56596 +    }
56597 +
56598 +    AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n"));
56599 +
56600 +    return A_OK;
56601 +}
56602 +
56603 +A_STATUS
56604 +BMIrompatchActivate(HIF_DEVICE *device,
56605 +                    A_UINT32 rompatch_count,
56606 +                    A_UINT32 *rompatch_list)
56607 +{
56608 +    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1);
56609 +}
56610 +
56611 +A_STATUS
56612 +BMIrompatchDeactivate(HIF_DEVICE *device,
56613 +                      A_UINT32 rompatch_count,
56614 +                      A_UINT32 *rompatch_list)
56615 +{
56616 +    return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0);
56617 +}
56618 +
56619 +/* BMI Access routines */
56620 +A_STATUS
56621 +bmiBufferSend(HIF_DEVICE *device,
56622 +              A_UCHAR *buffer,
56623 +              A_UINT32 length)
56624 +{
56625 +    A_STATUS status;
56626 +    A_UINT32 timeout;
56627 +    A_UINT32 address;
56628 +    static A_UINT32 cmdCredits;
56629 +    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
56630 +
56631 +    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
56632 +                       &mboxAddress, sizeof(mboxAddress));
56633 +
56634 +    cmdCredits = 0;
56635 +    timeout = BMI_COMMUNICATION_TIMEOUT;
56636 +
56637 +    while(timeout-- && !cmdCredits) {
56638 +        /* Read the counter register to get the command credits */
56639 +        address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
56640 +        /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause
56641 +         * a decrement, while the remaining 3 bytes has no effect.  The rationale behind this is to
56642 +         * make all HIF accesses 4-byte aligned */
56643 +        status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4,
56644 +            HIF_RD_SYNC_BYTE_INC, NULL);
56645 +        if (status != A_OK) {
56646 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n"));
56647 +            return A_ERROR;
56648 +        }
56649 +        /* the counter is only 8=bits, ignore anything in the upper 3 bytes */
56650 +        cmdCredits &= 0xFF;
56651 +    }
56652 +
56653 +    if (cmdCredits) {
56654 +        address = mboxAddress[ENDPOINT1];
56655 +        status = HIFReadWrite(device, address, buffer, length,
56656 +            HIF_WR_SYNC_BYTE_INC, NULL);
56657 +        if (status != A_OK) {
56658 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n"));
56659 +            return A_ERROR;
56660 +        }
56661 +    } else {
56662 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout\n"));
56663 +        return A_ERROR;
56664 +    }
56665 +
56666 +    return status;
56667 +}
56668 +
56669 +A_STATUS
56670 +bmiBufferReceive(HIF_DEVICE *device,
56671 +                 A_UCHAR *buffer,
56672 +                 A_UINT32 length)
56673 +{
56674 +    A_STATUS status;
56675 +    A_UINT32 address;
56676 +    A_UINT32 timeout;
56677 +    static A_UINT32 cmdCredits;
56678 +    A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
56679 +
56680 +    HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
56681 +                       &mboxAddress, sizeof(mboxAddress));
56682 +
56683 +    cmdCredits = 0;
56684 +    timeout = BMI_COMMUNICATION_TIMEOUT;
56685 +    while(timeout-- && !cmdCredits) {
56686 +        /* Read the counter register to get the command credits */
56687 +        address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
56688 +        /* read the counter using a 4-byte read.  Since the counter is NOT auto-decrementing,
56689 +         * we can read this counter multiple times using a non-incrementing address mode.
56690 +         * The rationale here is to make all HIF accesses a multiple of 4 bytes */
56691 +        status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits),
56692 +            HIF_RD_SYNC_BYTE_FIX, NULL);
56693 +        if (status != A_OK) {
56694 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n"));
56695 +            return A_ERROR;
56696 +        }
56697 +            /* we did a 4-byte read to the same count register so mask off upper bytes */
56698 +        cmdCredits &= 0xFF;
56699 +        status = A_ERROR;
56700 +    }
56701 +
56702 +    if (cmdCredits) {
56703 +        address = mboxAddress[ENDPOINT1];
56704 +        status = HIFReadWrite(device, address, buffer, length,
56705 +            HIF_RD_SYNC_BYTE_INC, NULL);
56706 +        if (status != A_OK) {
56707 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n"));
56708 +            return A_ERROR;
56709 +        }
56710 +    } else {
56711 +        AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout\n"));
56712 +        return A_ERROR;
56713 +    }
56714 +
56715 +    return status;
56716 +}
56717 Index: linux-2.6.28/drivers/ar6000/bmi/bmi_internal.h
56718 ===================================================================
56719 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
56720 +++ linux-2.6.28/drivers/ar6000/bmi/bmi_internal.h      2009-01-02 00:01:56.000000000 +0100
56721 @@ -0,0 +1,45 @@
56722 +#ifndef BMI_INTERNAL_H
56723 +#define BMI_INTERNAL_H
56724 +/*
56725 + *
56726 + * Copyright (c) 2004-2007 Atheros Communications Inc.
56727 + * All rights reserved.
56728 + *
56729 + *
56730 + *  This program is free software; you can redistribute it and/or modify
56731 + *  it under the terms of the GNU General Public License version 2 as
56732 + *  published by the Free Software Foundation;
56733 + *
56734 + *  Software distributed under the License is distributed on an "AS
56735 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
56736 + *  implied. See the License for the specific language governing
56737 + *  rights and limitations under the License.
56738 + *
56739 + *
56740 + *
56741 + */
56742 +
56743 +#include "a_config.h"
56744 +#include "athdefs.h"
56745 +#include "a_types.h"
56746 +#include "a_osapi.h"
56747 +#include "a_debug.h"
56748 +#include "AR6Khwreg.h"
56749 +#include "bmi_msg.h"
56750 +
56751 +#define BMI_COMMUNICATION_TIMEOUT       100000
56752 +
56753 +/* ------ Global Variable Declarations ------- */
56754 +A_BOOL bmiDone;
56755 +
56756 +A_STATUS
56757 +bmiBufferSend(HIF_DEVICE *device,
56758 +              A_UCHAR *buffer,
56759 +              A_UINT32 length);
56760 +
56761 +A_STATUS
56762 +bmiBufferReceive(HIF_DEVICE *device,
56763 +                 A_UCHAR *buffer,
56764 +                 A_UINT32 length);
56765 +
56766 +#endif
56767 Index: linux-2.6.28/drivers/ar6000/hif/hif2.c
56768 ===================================================================
56769 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
56770 +++ linux-2.6.28/drivers/ar6000/hif/hif2.c      2009-01-02 00:01:56.000000000 +0100
56771 @@ -0,0 +1,646 @@
56772 +/*
56773 + * hif2.c - HIF layer re-implementation for the Linux SDIO stack
56774 + *
56775 + * Copyright (C) 2008 by OpenMoko, Inc.
56776 + * Written by Werner Almesberger <werner@openmoko.org>
56777 + * All Rights Reserved
56778 + *
56779 + * This program is free software; you can redistribute it and/or modify
56780 + * it under the terms of the GNU General Public License version 2 as
56781 + * published by the Free Software Foundation;
56782 + *
56783 + * Based on:
56784 + *
56785 + * @abstract: HIF layer reference implementation for Atheros SDIO stack
56786 + * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
56787 + */
56788 +
56789 +
56790 +#include <linux/kernel.h>
56791 +#include <linux/kthread.h>
56792 +#include <linux/list.h>
56793 +#include <linux/wait.h>
56794 +#include <linux/spinlock.h>
56795 +#include <linux/sched.h>
56796 +#include <linux/mmc/sdio_func.h>
56797 +#include <linux/mmc/sdio.h>
56798 +#include <linux/mmc/sdio_ids.h>
56799 +#include <asm/gpio.h>
56800 +
56801 +#include "athdefs.h"
56802 +#include "a_types.h"
56803 +#include "hif.h"
56804 +
56805 +
56806 +/*
56807 + * KNOWN BUGS:
56808 + *
56809 + * - HIF_DEVICE_IRQ_ASYNC_SYNC doesn't work yet (gets MMC errors)
56810 + * - latency can reach hundreds of ms, probably because of scheduling delays
56811 + * - packets go through about three queues before finally hitting the network
56812 + */
56813 +
56814 +/*
56815 + * Differences from Atheros' HIFs:
56816 + *
56817 + * - synchronous and asynchronous requests may get reordered with respect to
56818 + *   each other, e.g., if HIFReadWrite returns for an asynchronous request and
56819 + *   then HIFReadWrite is called for a synchronous request, the synchronous
56820 + *   request may be executed before the asynchronous request.
56821 + *
56822 + * - request queue locking seems unnecessarily complex in the Atheros HIFs.
56823 + *
56824 + * - Atheros mask interrupts by calling sdio_claim_irq/sdio_release_irq, which
56825 + *   can cause quite a bit of overhead. This HIF has its own light-weight
56826 + *   interrupt masking.
56827 + *
56828 + * - Atheros call deviceInsertedHandler from a thread spawned off the probe or
56829 + *   device insertion function. The original explanation for the Atheros SDIO
56830 + *   stack said that this is done because a delay is needed to let the chip
56831 + *   complete initialization. There is indeed a one second delay in the thread.
56832 + *
56833 + *   The Atheros Linux SDIO HIF removes the delay and only retains the thread.
56834 + *   Experimentally removing the thread didn't show any conflicts, so let's get
56835 + *   rid of it for good.
56836 + *
56837 + * - The Atheros SDIO stack with Samuel's driver sets SDIO_CCCR_POWER in
56838 + *   SDIO_POWER_EMPC. Atheros' Linux SDIO code apparently doesn't. We don't
56839 + *   either, and this seems to work fine.
56840 + *   @@@ Need to check this with Atheros.
56841 + */
56842 +
56843 +
56844 +#define MBOXES                 4
56845 +
56846 +#define HIF_MBOX_BLOCK_SIZE    128
56847 +#define        HIF_MBOX_BASE_ADDR      0x800
56848 +#define        HIF_MBOX_WIDTH          0x800
56849 +#define        HIF_MBOX_START_ADDR(mbox) \
56850 +    (HIF_MBOX_BASE_ADDR+(mbox)*HIF_MBOX_WIDTH)
56851 +
56852 +
56853 +struct hif_device {
56854 +       void *htc_handle;
56855 +       struct sdio_func *func;
56856 +
56857 +       /*
56858 +        * @@@ our sweet little bit of bogosity - the mechanism that lets us
56859 +        * use the SDIO stack from softirqs. This really wants to use skbs.
56860 +        */
56861 +       struct list_head queue;
56862 +       spinlock_t queue_lock;
56863 +       struct task_struct *io_task;
56864 +       wait_queue_head_t wait;
56865 +};
56866 +
56867 +struct hif_request {
56868 +       struct list_head list;
56869 +       struct sdio_func *func;
56870 +       int (*read)(struct sdio_func *func,
56871 +           void *dst, unsigned int addr, int count);
56872 +       int (*write)(struct sdio_func *func,
56873 +           unsigned int addr, void *src, int count);
56874 +       void *buf;
56875 +       unsigned long addr;
56876 +       int len;
56877 +       A_STATUS (*completion)(void *context, A_STATUS status);
56878 +       void *context;
56879 +};
56880 +
56881 +
56882 +static HTC_CALLBACKS htcCallbacks;
56883 +
56884 +/*
56885 + * shutdown_lock prevents recursion through HIFShutDownDevice
56886 + */
56887 +static DEFINE_MUTEX(shutdown_lock);
56888 +
56889 +
56890 +/* ----- Request processing ------------------------------------------------ */
56891 +
56892 +
56893 +static A_STATUS process_request(struct hif_request *req)
56894 +{
56895 +       int ret;
56896 +       A_STATUS status;
56897 +
56898 +       dev_dbg(&req->func->dev, "process_request(req %p)\n", req);
56899 +       sdio_claim_host(req->func);
56900 +       if (req->read)
56901 +               ret = req->read(req->func, req->buf, req->addr, req->len);
56902 +       else
56903 +               ret = req->write(req->func, req->addr, req->buf, req->len);
56904 +       sdio_release_host(req->func);
56905 +       status = ret ? A_ERROR : A_OK;
56906 +       if (req->completion)
56907 +               req->completion(req->context, status);
56908 +       kfree(req);
56909 +       return status;
56910 +}
56911 +
56912 +
56913 +static void enqueue_request(struct hif_device *hif, struct hif_request *req)
56914 +{
56915 +       unsigned long flags;
56916 +
56917 +       dev_dbg(&req->func->dev, "enqueue_request(req %p)\n", req);
56918 +       spin_lock_irqsave(&hif->queue_lock, flags);
56919 +       list_add_tail(&req->list, &hif->queue);
56920 +       spin_unlock_irqrestore(&hif->queue_lock, flags);
56921 +       wake_up(&hif->wait);
56922 +}
56923 +
56924 +
56925 +static struct hif_request *dequeue_request(struct hif_device *hif)
56926 +{
56927 +       struct hif_request *req;
56928 +       unsigned long flags;
56929 +
56930 +       spin_lock_irqsave(&hif->queue_lock, flags);
56931 +       if (list_empty(&hif->queue))
56932 +               req = NULL;
56933 +       else {
56934 +               req = list_first_entry(&hif->queue,
56935 +                   struct hif_request, list);
56936 +               list_del(&req->list);
56937 +       }
56938 +       spin_unlock_irqrestore(&hif->queue_lock, flags);
56939 +       return req;
56940 +}
56941 +
56942 +
56943 +static void wait_queue_empty(struct hif_device *hif)
56944 +{
56945 +       unsigned long flags;
56946 +       int empty;
56947 +
56948 +       while (1) {
56949 +               spin_lock_irqsave(&hif->queue_lock, flags);
56950 +               empty = list_empty(&hif->queue);
56951 +               spin_unlock_irqrestore(&hif->queue_lock, flags);
56952 +               if (empty)
56953 +                       break;
56954 +               else
56955 +                       yield();
56956 +       }
56957 +}
56958 +
56959 +
56960 +static int io(void *data)
56961 +{
56962 +       struct hif_device *hif = data;
56963 +       struct sched_param param = { .sched_priority = 2 };
56964 +               /* one priority level slower than ksdioirqd (which is at 1) */
56965 +       DEFINE_WAIT(wait);
56966 +       struct hif_request *req;
56967 +
56968 +       sched_setscheduler(current, SCHED_FIFO, &param);
56969 +
56970 +       while (1) {
56971 +               while (1) {
56972 +                       /*
56973 +                        * Since we never use signals here, one might think
56974 +                        * that this ought to be TASK_UNINTERRUPTIBLE. However,
56975 +                        * such a task would increase the load average and,
56976 +                        * worse, it would trigger the softlockup check.
56977 +                        */
56978 +                       prepare_to_wait(&hif->wait, &wait, TASK_INTERRUPTIBLE);
56979 +                       if (kthread_should_stop()) {
56980 +                               finish_wait(&hif->wait, &wait);
56981 +                               return 0;
56982 +                       }
56983 +                       req = dequeue_request(hif);
56984 +                       if (req)
56985 +                               break;
56986 +                       schedule();
56987 +               }
56988 +               finish_wait(&hif->wait, &wait);
56989 +
56990 +               (void) process_request(req);
56991 +       }
56992 +       return 0;
56993 +}
56994 +
56995 +
56996 +A_STATUS HIFReadWrite(HIF_DEVICE *hif, A_UINT32 address, A_UCHAR *buffer,
56997 +    A_UINT32 length, A_UINT32 request, void *context)
56998 +{
56999 +       struct device *dev = HIFGetOSDevice(hif);
57000 +       struct hif_request *req;
57001 +
57002 +       dev_dbg(dev, "HIFReadWrite(device %p, address 0x%x, buffer %p, "
57003 +           "length %d, request 0x%x, context %p)\n",
57004 +           hif, address, buffer, length, request, context);
57005 +
57006 +       BUG_ON(!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)));
57007 +       BUG_ON(!(request & (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)));
57008 +       BUG_ON(!(request & (HIF_READ | HIF_WRITE)));
57009 +       BUG_ON(!(request & HIF_EXTENDED_IO));
57010 +
57011 +       if (address >= HIF_MBOX_START_ADDR(0) &&
57012 +           address < HIF_MBOX_START_ADDR(MBOXES+1)) {
57013 +               BUG_ON(length > HIF_MBOX_WIDTH);
57014 +               /* Adjust the address so that the last byte falls on the EOM
57015 +                  address. */
57016 +               address += HIF_MBOX_WIDTH-length;
57017 +       }
57018 +
57019 +       req = kzalloc(sizeof(*req), GFP_ATOMIC);
57020 +       if (!req) {
57021 +               if (request & HIF_ASYNCHRONOUS)
57022 +                       htcCallbacks.rwCompletionHandler(context, A_ERROR);
57023 +               return A_ERROR;
57024 +       }
57025 +
57026 +       req->func = hif->func;
57027 +       req->addr = address;
57028 +       req->buf = buffer;
57029 +       req->len = length;
57030 +
57031 +       if (request & HIF_READ) {
57032 +               if (request & HIF_FIXED_ADDRESS)
57033 +                       req->read = sdio_readsb;
57034 +               else
57035 +                       req->read = sdio_memcpy_fromio;
57036 +       } else {
57037 +               if (request & HIF_FIXED_ADDRESS)
57038 +                       req->write = sdio_writesb;
57039 +               else
57040 +                       req->write = sdio_memcpy_toio;
57041 +       }
57042 +
57043 +       if (!(request & HIF_ASYNCHRONOUS))
57044 +               return process_request(req);
57045 +
57046 +       req->completion = htcCallbacks.rwCompletionHandler;
57047 +       req->context = context;
57048 +       enqueue_request(hif, req);
57049 +
57050 +       return A_OK;
57051 +}
57052 +
57053 +
57054 +/* ----- Interrupt handling ------------------------------------------------ */
57055 +
57056 +/*
57057 + * Volatile ought to be good enough to make gcc do the right thing on S3C24xx.
57058 + * No need to use atomic or put barriers, keeping the code more readable.
57059 + *
57060 + * Warning: this story changes if going SMP/SMT.
57061 + */
57062 +
57063 +static volatile int masked = 1;
57064 +static volatile int pending;
57065 +static volatile int in_interrupt;
57066 +
57067 +
57068 +static void ar6000_do_irq(struct sdio_func *func)
57069 +{
57070 +       HIF_DEVICE *hif = sdio_get_drvdata(func);
57071 +       struct device *dev = HIFGetOSDevice(hif);
57072 +       A_STATUS status;
57073 +
57074 +       dev_dbg(dev, "ar6000_do_irq -> %p\n", htcCallbacks.dsrHandler);
57075 +
57076 +       status = htcCallbacks.dsrHandler(hif->htc_handle);
57077 +       BUG_ON(status != A_OK);
57078 +}
57079 +
57080 +
57081 +static void sdio_ar6000_irq(struct sdio_func *func)
57082 +{
57083 +       HIF_DEVICE *hif = sdio_get_drvdata(func);
57084 +       struct device *dev = HIFGetOSDevice(hif);
57085 +
57086 +       dev_dbg(dev, "sdio_ar6000_irq\n");
57087 +
57088 +       in_interrupt = 1;
57089 +       if (masked) {
57090 +               in_interrupt = 0;
57091 +               pending++;
57092 +               return;
57093 +       }
57094 +       /*
57095 +        * @@@ This is ugly. If we don't drop the lock, we'll deadlock when
57096 +        * the handler tries to do SDIO. So there are four choices:
57097 +        *
57098 +        * 1) Break the call chain by calling the callback from a workqueue.
57099 +        *    Ugh.
57100 +        * 2) Make process_request aware that we already have the lock.
57101 +        * 3) Drop the lock. Which is ugly but should be safe as long as we're
57102 +        *    making sure the device doesn't go away.
57103 +        * 4) Change the AR6k driver such that it only issues asynchronous
57104 +        *    quests when called from an interrupt.
57105 +        *
57106 +        * Solution 2) is probably the best for now. Will try it later.
57107 +        */
57108 +       sdio_release_host(func);
57109 +       ar6000_do_irq(func);
57110 +       sdio_claim_host(func);
57111 +       in_interrupt = 0;
57112 +}
57113 +
57114 +
57115 +void HIFAckInterrupt(HIF_DEVICE *hif)
57116 +{
57117 +       struct device *dev = HIFGetOSDevice(hif);
57118 +
57119 +       dev_dbg(dev, "HIFAckInterrupt\n");
57120 +       /* do nothing */
57121 +}
57122 +
57123 +
57124 +void HIFUnMaskInterrupt(HIF_DEVICE *hif)
57125 +{
57126 +       struct device *dev = HIFGetOSDevice(hif);
57127 +
57128 +       dev_dbg(dev, "HIFUnMaskInterrupt\n");
57129 +       do {
57130 +               masked = 1;
57131 +               if (pending) {
57132 +                       pending = 0;
57133 +                       ar6000_do_irq(hif->func);
57134 +                       /* We may take an interrupt before unmasking and thus
57135 +                          get it pending. In this case, we just loop back. */
57136 +               }
57137 +               masked = 0;
57138 +       }
57139 +       while (pending);
57140 +}
57141 +
57142 +
57143 +void HIFMaskInterrupt(HIF_DEVICE *hif)
57144 +{
57145 +       struct device *dev = HIFGetOSDevice(hif);
57146 +
57147 +       dev_dbg(dev, "HIFMaskInterrupt\n");
57148 +       /*
57149 +        * Since sdio_ar6000_irq can also be called from a process context, we
57150 +        * may conceivably end up racing with it. Thus, we need to wait until
57151 +        * we can be sure that no concurrent interrupt processing is going on
57152 +        * before we return.
57153 +        *
57154 +        * Note: this may be a bit on the paranoid side - the callers may
57155 +        * actually be nice enough to disable scheduling. Check later.
57156 +        */
57157 +       masked = 1;
57158 +       while (in_interrupt)
57159 +               yield();
57160 +}
57161 +
57162 +
57163 +/* ----- HIF API glue functions -------------------------------------------- */
57164 +
57165 +
57166 +struct device *HIFGetOSDevice(HIF_DEVICE *hif)
57167 +{
57168 +       return &hif->func->dev;
57169 +}
57170 +
57171 +
57172 +void HIFSetHandle(void *hif_handle, void *handle)
57173 +{
57174 +       HIF_DEVICE *hif = (HIF_DEVICE *) hif_handle;
57175 +
57176 +       hif->htc_handle = handle;
57177 +}
57178 +
57179 +
57180 +/* ----- Device configuration (HIF side) ----------------------------------- */
57181 +
57182 +
57183 +A_STATUS HIFConfigureDevice(HIF_DEVICE *hif,
57184 +    HIF_DEVICE_CONFIG_OPCODE opcode, void *config, A_UINT32 configLen)
57185 +{
57186 +       struct device *dev = HIFGetOSDevice(hif);
57187 +       HIF_DEVICE_IRQ_PROCESSING_MODE *ipm_cfg = config;
57188 +       A_UINT32 *mbs_cfg = config;
57189 +       int i;
57190 +
57191 +       dev_dbg(dev, "HIFConfigureDevice\n");
57192 +
57193 +       switch (opcode) {
57194 +       case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
57195 +               for (i = 0; i != MBOXES; i++)
57196 +                       mbs_cfg[i] = HIF_MBOX_BLOCK_SIZE;
57197 +               break;
57198 +       case HIF_DEVICE_GET_MBOX_ADDR:
57199 +               for (i = 0; i != MBOXES; i++)
57200 +                       mbs_cfg[i] = HIF_MBOX_START_ADDR(i);
57201 +               break;
57202 +       case HIF_DEVICE_GET_IRQ_PROC_MODE:
57203 +               *ipm_cfg = HIF_DEVICE_IRQ_SYNC_ONLY;
57204 +//             *ipm_cfg = HIF_DEVICE_IRQ_ASYNC_SYNC;
57205 +               break;
57206 +       default:
57207 +               return A_ERROR;
57208 +       }
57209 +       return A_OK;
57210 +}
57211 +
57212 +
57213 +/* ----- Device probe and removal (Linux side) ----------------------------- */
57214 +
57215 +
57216 +static int sdio_ar6000_probe(struct sdio_func *func,
57217 +    const struct sdio_device_id *id)
57218 +{
57219 +       struct device *dev = &func->dev;
57220 +       struct hif_device *hif;
57221 +       int ret;
57222 +
57223 +       dev_dbg(dev, "sdio_ar6000_probe\n");
57224 +       BUG_ON(!htcCallbacks.deviceInsertedHandler);
57225 +
57226 +       hif = kzalloc(sizeof(*hif), GFP_KERNEL);
57227 +       if (!hif)
57228 +               return -ENOMEM;
57229 +
57230 +       sdio_set_drvdata(func, hif);
57231 +       sdio_claim_host(func);
57232 +       sdio_enable_func(func);
57233 +
57234 +       hif->func = func;
57235 +       INIT_LIST_HEAD(&hif->queue);
57236 +       init_waitqueue_head(&hif->wait);
57237 +       spin_lock_init(&hif->queue_lock);
57238 +
57239 +       ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
57240 +       if (ret < 0) {
57241 +               dev_err(dev, "sdio_set_block_size returns %d\n", ret);
57242 +               goto out_enabled;
57243 +       }
57244 +       ret = sdio_claim_irq(func, sdio_ar6000_irq);
57245 +       if (ret) {
57246 +               dev_err(dev, "sdio_claim_irq returns %d\n", ret);
57247 +               goto out_enabled;
57248 +       }
57249 +       /* Set SDIO_BUS_CD_DISABLE in SDIO_CCCR_IF ? */
57250 +#if 0
57251 +       sdio_f0_writeb(func, SDIO_CCCR_CAP_E4MI, SDIO_CCCR_CAPS, &ret);
57252 +       if (ret) {
57253 +               dev_err(dev, "sdio_f0_writeb(SDIO_CCCR_CAPS) returns %d\n",
57254 +                   ret);
57255 +               goto out_got_irq;
57256 +       }
57257 +#else
57258 +       if (0) /* avoid warning */
57259 +               goto out_got_irq;
57260 +#endif
57261 +
57262 +       sdio_release_host(func);
57263 +
57264 +       hif->io_task = kthread_run(io, hif, "ar6000_io");
57265 +       if (IS_ERR(hif->io_task)) {
57266 +               dev_err(dev, "kthread_run(ar6000_io): %d\n", ret);
57267 +               goto out_func_ready;
57268 +       }
57269 +
57270 +       ret = htcCallbacks.deviceInsertedHandler(hif);
57271 +       if (ret == A_OK)
57272 +               return 0;
57273 +
57274 +       dev_err(dev, "deviceInsertedHandler: %d\n", ret);
57275 +
57276 +       ret = kthread_stop(hif->io_task);
57277 +       if (ret)
57278 +               dev_err(dev, "kthread_stop (ar6000_io): %d\n", ret);
57279 +
57280 +out_func_ready:
57281 +       sdio_claim_host(func);
57282 +
57283 +out_got_irq:
57284 +       sdio_release_irq(func);
57285 +
57286 +out_enabled:
57287 +       sdio_set_drvdata(func, NULL);
57288 +       sdio_disable_func(func);
57289 +       sdio_release_host(func);
57290 +
57291 +       return ret;
57292 +}
57293 +
57294 +
57295 +static void sdio_ar6000_remove(struct sdio_func *func)
57296 +{
57297 +       struct device *dev = &func->dev;
57298 +       HIF_DEVICE *hif = sdio_get_drvdata(func);
57299 +       int ret;
57300 +
57301 +       dev_dbg(dev, "sdio_ar6000_remove\n");
57302 +       if (mutex_trylock(&shutdown_lock)) {
57303 +               /*
57304 +                * Funny, Atheros' HIF does this call, but this just puts us in
57305 +                * a recursion through HTCShutDown/HIFShutDown if unloading the
57306 +                * module.
57307 +                *
57308 +                * However, we need it for suspend/resume. See the comment at
57309 +                * HIFShutDown, below.
57310 +                */
57311 +               ret = htcCallbacks.deviceRemovedHandler(hif->htc_handle, A_OK);
57312 +               if (ret != A_OK)
57313 +                       dev_err(dev, "deviceRemovedHandler: %d\n", ret);
57314 +               mutex_unlock(&shutdown_lock);
57315 +       }
57316 +       wait_queue_empty(hif);
57317 +       ret = kthread_stop(hif->io_task);
57318 +       if (ret)
57319 +               dev_err(dev, "kthread_stop (ar6000_io): %d\n", ret);
57320 +       sdio_claim_host(func);
57321 +       sdio_release_irq(func);
57322 +       sdio_set_drvdata(func, NULL);
57323 +       sdio_disable_func(func);
57324 +       sdio_release_host(func);
57325 +       kfree(hif);
57326 +}
57327 +
57328 +
57329 +/* ----- Device registration/unregistration (called by HIF) ---------------- */
57330 +
57331 +
57332 +#define ATHEROS_SDIO_DEVICE(id, offset) \
57333 +    SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_##id | (offset))
57334 +
57335 +static const struct sdio_device_id sdio_ar6000_ids[] = {
57336 +       { ATHEROS_SDIO_DEVICE(AR6000, 0)        },
57337 +       { ATHEROS_SDIO_DEVICE(AR6000, 0x1)      },
57338 +       { ATHEROS_SDIO_DEVICE(AR6000, 0x8)      },
57339 +       { ATHEROS_SDIO_DEVICE(AR6000, 0x9)      },
57340 +       { ATHEROS_SDIO_DEVICE(AR6000, 0xa)      },
57341 +       { ATHEROS_SDIO_DEVICE(AR6000, 0xb)      },
57342 +       { /* end: all zeroes */                 },
57343 +};
57344 +
57345 +MODULE_DEVICE_TABLE(sdio, sdio_ar6000_ids);
57346 +
57347 +
57348 +static struct sdio_driver sdio_ar6000_driver = {
57349 +       .probe          = sdio_ar6000_probe,
57350 +       .remove         = sdio_ar6000_remove,
57351 +       .name           = "sdio_ar6000",
57352 +       .id_table       = sdio_ar6000_ids,
57353 +};
57354 +
57355 +
57356 +int HIFInit(HTC_CALLBACKS *callbacks)
57357 +{
57358 +       int ret;
57359 +
57360 +       BUG_ON(!callbacks);
57361 +
57362 +       printk(KERN_DEBUG "HIFInit\n");
57363 +       htcCallbacks = *callbacks;
57364 +
57365 +       ret = sdio_register_driver(&sdio_ar6000_driver);
57366 +       if (ret) {
57367 +               printk(KERN_ERR
57368 +                   "sdio_register_driver(sdio_ar6000_driver): %d\n", ret);
57369 +               return A_ERROR;
57370 +       }
57371 +
57372 +       return 0;
57373 +}
57374 +
57375 +
57376 +/*
57377 + * We have three possible call chains here:
57378 + *
57379 + * System shutdown/reboot:
57380 + *
57381 + *   kernel_restart_prepare ...> device_shutdown ... > s3cmci_shutdown ->
57382 + *     mmc_remove_host ..> sdio_bus_remove -> sdio_ar6000_remove ->
57383 + *     deviceRemovedHandler (HTCTargetRemovedHandler) -> HIFShutDownDevice
57384 + *
57385 + *   This is roughly the same sequence as suspend, described below.
57386 + *
57387 + * Module removal:
57388 + *
57389 + *   sys_delete_module -> ar6000_cleanup_module -> HTCShutDown ->
57390 + *     HIFShutDownDevice -> sdio_unregister_driver ...> sdio_bus_remove ->
57391 + *     sdio_ar6000_remove
57392 + *
57393 + *   In this case, HIFShutDownDevice must call sdio_unregister_driver to
57394 + *   notify the driver about its removal. sdio_ar6000_remove must not call
57395 + *   deviceRemovedHandler, because that would loop back into HIFShutDownDevice.
57396 + *
57397 + * Suspend:
57398 + *
57399 + *   device_suspend ...> s3cmci_suspend ...> sdio_bus_remove ->
57400 + *     sdio_ar6000_remove -> deviceRemovedHandler (HTCTargetRemovedHandler) ->
57401 + *     HIFShutDownDevice
57402 + *
57403 + *   We must call deviceRemovedHandler to inform the ar6k stack that the device
57404 + *   has been removed. Since HTCTargetRemovedHandler calls back into
57405 + *   HIFShutDownDevice, we must also prevent the call to
57406 + *   sdio_unregister_driver, or we'd end up recursing into the SDIO stack,
57407 + *   eventually deadlocking somewhere.
57408 + */
57409 +
57410 +void HIFShutDownDevice(HIF_DEVICE *hif)
57411 +{
57412 +       /* Beware, HTCShutDown calls us with hif == NULL ! */
57413 +       if (mutex_trylock(&shutdown_lock)) {
57414 +               sdio_unregister_driver(&sdio_ar6000_driver);
57415 +               mutex_unlock(&shutdown_lock);
57416 +       }
57417 +}
57418 Index: linux-2.6.28/drivers/ar6000/hif/hif.c
57419 ===================================================================
57420 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
57421 +++ linux-2.6.28/drivers/ar6000/hif/hif.c       2009-01-02 00:01:56.000000000 +0100
57422 @@ -0,0 +1,824 @@
57423 +/*
57424 + * @file: hif.c
57425 + *
57426 + * @abstract: HIF layer reference implementation for Atheros SDIO stack
57427 + *
57428 + * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
57429 + *
57430 + *
57431 + *  This program is free software; you can redistribute it and/or modify
57432 + *  it under the terms of the GNU General Public License version 2 as
57433 + *  published by the Free Software Foundation;
57434 + *
57435 + *  Software distributed under the License is distributed on an "AS
57436 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
57437 + *  implied. See the License for the specific language governing
57438 + *  rights and limitations under the License.
57439 + *
57440 + *
57441 + *
57442 + */
57443 +
57444 +#include "hif_internal.h"
57445 +
57446 +/* ------ Static Variables ------ */
57447 +
57448 +/* ------ Global Variable Declarations ------- */
57449 +SD_PNP_INFO Ids[] = {
57450 +    {
57451 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0xB,
57452 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
57453 +        .SDIO_FunctionClass = FUNCTION_CLASS,
57454 +        .SDIO_FunctionNo = 1
57455 +    },
57456 +    {
57457 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0xA,
57458 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
57459 +        .SDIO_FunctionClass = FUNCTION_CLASS,
57460 +        .SDIO_FunctionNo = 1
57461 +    },
57462 +    {
57463 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0x9,
57464 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
57465 +        .SDIO_FunctionClass = FUNCTION_CLASS,
57466 +        .SDIO_FunctionNo = 1
57467 +    },
57468 +    {
57469 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0x8,
57470 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
57471 +        .SDIO_FunctionClass = FUNCTION_CLASS,
57472 +        .SDIO_FunctionNo = 1
57473 +    },
57474 +    {
57475 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6002_BASE | 0x0,
57476 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
57477 +        .SDIO_FunctionClass = FUNCTION_CLASS,
57478 +        .SDIO_FunctionNo = 1
57479 +    },
57480 +    {
57481 +        .SDIO_ManufacturerID = MANUFACTURER_ID_AR6002_BASE | 0x1,
57482 +        .SDIO_ManufacturerCode = MANUFACTURER_CODE,
57483 +        .SDIO_FunctionClass = FUNCTION_CLASS,
57484 +        .SDIO_FunctionNo = 1
57485 +    },
57486 +    {
57487 +    }                      //list is null termintaed
57488 +};
57489 +
57490 +TARGET_FUNCTION_CONTEXT FunctionContext = {
57491 +    .function.Version    = CT_SDIO_STACK_VERSION_CODE,
57492 +    .function.pName      = "sdio_wlan",
57493 +    .function.MaxDevices = 1,
57494 +    .function.NumDevices = 0,
57495 +    .function.pIds       = Ids,
57496 +    .function.pProbe     = hifDeviceInserted,
57497 +    .function.pRemove    = hifDeviceRemoved,
57498 +    .function.pSuspend   = NULL,
57499 +    .function.pResume    = NULL,
57500 +    .function.pWake      = NULL,
57501 +    .function.pContext   = &FunctionContext,
57502 +};
57503 +
57504 +HIF_DEVICE hifDevice[HIF_MAX_DEVICES];
57505 +HTC_CALLBACKS htcCallbacks;
57506 +BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM];
57507 +static BUS_REQUEST *s_busRequestFreeQueue = NULL;
57508 +OS_CRITICALSECTION lock;
57509 +extern A_UINT32 onebitmode;
57510 +extern A_UINT32 busspeedlow;
57511 +
57512 +#ifdef DEBUG
57513 +extern A_UINT32 debughif;
57514 +#define ATH_DEBUG_ERROR 1
57515 +#define ATH_DEBUG_WARN  2
57516 +#define ATH_DEBUG_TRACE 3
57517 +#define _AR_DEBUG_PRINTX_ARG(arg...) arg
57518 +#define AR_DEBUG_PRINTF(lvl, args)\
57519 +    {if (lvl <= debughif)\
57520 +        A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\
57521 +    }
57522 +#else
57523 +#define AR_DEBUG_PRINTF(lvl, args)
57524 +#endif
57525 +
57526 +static BUS_REQUEST *hifAllocateBusRequest(void);
57527 +static void hifFreeBusRequest(BUS_REQUEST *busrequest);
57528 +static THREAD_RETURN insert_helper_func(POSKERNEL_HELPER pHelper);
57529 +static void ResetAllCards(void);
57530 +
57531 +/* ------ Functions ------ */
57532 +int HIFInit(HTC_CALLBACKS *callbacks)
57533 +{
57534 +    SDIO_STATUS status;
57535 +    DBG_ASSERT(callbacks != NULL);
57536 +
57537 +    /* Store the callback and event handlers */
57538 +    htcCallbacks.deviceInsertedHandler = callbacks->deviceInsertedHandler;
57539 +    htcCallbacks.deviceRemovedHandler = callbacks->deviceRemovedHandler;
57540 +    htcCallbacks.deviceSuspendHandler = callbacks->deviceSuspendHandler;
57541 +    htcCallbacks.deviceResumeHandler = callbacks->deviceResumeHandler;
57542 +    htcCallbacks.deviceWakeupHandler = callbacks->deviceWakeupHandler;
57543 +    htcCallbacks.rwCompletionHandler = callbacks->rwCompletionHandler;
57544 +    htcCallbacks.dsrHandler = callbacks->dsrHandler;
57545 +
57546 +    CriticalSectionInit(&lock);
57547 +
57548 +    /* Register with bus driver core */
57549 +    status = SDIO_RegisterFunction(&FunctionContext.function);
57550 +    DBG_ASSERT(SDIO_SUCCESS(status));
57551 +
57552 +    return(0);
57553 +}
57554 +
57555 +A_STATUS
57556 +HIFReadWrite(HIF_DEVICE *device,
57557 +             A_UINT32 address,
57558 +             A_UCHAR *buffer,
57559 +             A_UINT32 length,
57560 +             A_UINT32 request,
57561 +             void *context)
57562 +{
57563 +    A_UINT8 rw;
57564 +    A_UINT8 mode;
57565 +    A_UINT8 funcNo;
57566 +    A_UINT8 opcode;
57567 +    A_UINT16 count;
57568 +    SDREQUEST *sdrequest;
57569 +    SDIO_STATUS sdiostatus;
57570 +    BUS_REQUEST *busrequest;
57571 +    A_STATUS    status = A_OK;
57572 +
57573 +    DBG_ASSERT(device != NULL);
57574 +    DBG_ASSERT(device->handle != NULL);
57575 +
57576 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
57577 +
57578 +    do {
57579 +        busrequest = hifAllocateBusRequest();
57580 +        if (busrequest == NULL) {
57581 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF Unable to allocate bus request\n"));
57582 +            status = A_NO_RESOURCE;
57583 +            break;
57584 +        }
57585 +
57586 +        sdrequest = busrequest->request;
57587 +        busrequest->context = context;
57588 +
57589 +        sdrequest->pDataBuffer = buffer;
57590 +        if (request & HIF_SYNCHRONOUS) {
57591 +            sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS;
57592 +            sdrequest->pCompleteContext = NULL;
57593 +            sdrequest->pCompletion = NULL;
57594 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Synchronous\n"));
57595 +        } else if (request & HIF_ASYNCHRONOUS) {
57596 +            sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS |
57597 +                               SDREQ_FLAGS_TRANS_ASYNC;
57598 +            sdrequest->pCompleteContext = busrequest;
57599 +            sdrequest->pCompletion = hifRWCompletionHandler;
57600 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Asynchronous\n"));
57601 +        } else {
57602 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57603 +                            ("Invalid execution mode: 0x%08x\n", request));
57604 +            status = A_EINVAL;
57605 +            break;
57606 +        }
57607 +
57608 +        if (request & HIF_EXTENDED_IO) {
57609 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Command type: CMD53\n"));
57610 +            sdrequest->Command = CMD53;
57611 +        } else {
57612 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57613 +                            ("Invalid command type: 0x%08x\n", request));
57614 +            status = A_EINVAL;
57615 +            break;
57616 +        }
57617 +
57618 +        if (request & HIF_BLOCK_BASIS) {
57619 +            mode = CMD53_BLOCK_BASIS;
57620 +            sdrequest->BlockLen = HIF_MBOX_BLOCK_SIZE;
57621 +            sdrequest->BlockCount = length / HIF_MBOX_BLOCK_SIZE;
57622 +            count = sdrequest->BlockCount;
57623 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57624 +                            ("Block mode (BlockLen: %d, BlockCount: %d)\n",
57625 +                            sdrequest->BlockLen, sdrequest->BlockCount));
57626 +        } else if (request & HIF_BYTE_BASIS) {
57627 +            mode = CMD53_BYTE_BASIS;
57628 +            sdrequest->BlockLen = length;
57629 +            sdrequest->BlockCount = 1;
57630 +            count = sdrequest->BlockLen;
57631 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57632 +                            ("Byte mode (BlockLen: %d, BlockCount: %d)\n",
57633 +                            sdrequest->BlockLen, sdrequest->BlockCount));
57634 +        } else {
57635 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57636 +                            ("Invalid data mode: 0x%08x\n", request));
57637 +            status = A_EINVAL;
57638 +            break;
57639 +        }
57640 +
57641 +#if 0
57642 +        /* useful for checking register accesses */
57643 +        if (length & 0x3) {
57644 +            A_PRINTF(KERN_ALERT"HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n",
57645 +                                request & HIF_WRITE ? "write":"read", address, length);
57646 +        }
57647 +#endif
57648 +
57649 +        if ((address >= HIF_MBOX_START_ADDR(0)) &&
57650 +            (address <= HIF_MBOX_END_ADDR(3)))
57651 +        {
57652 +
57653 +            DBG_ASSERT(length <= HIF_MBOX_WIDTH);
57654 +
57655 +            /*
57656 +             * Mailbox write. Adjust the address so that the last byte
57657 +             * falls on the EOM address.
57658 +             */
57659 +            address += (HIF_MBOX_WIDTH - length);
57660 +        }
57661 +
57662 +
57663 +
57664 +        if (request & HIF_WRITE) {
57665 +            rw = CMD53_WRITE;
57666 +            sdrequest->Flags |= SDREQ_FLAGS_DATA_WRITE;
57667 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Write\n"));
57668 +        } else if (request & HIF_READ) {
57669 +            rw = CMD53_READ;
57670 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Read\n"));
57671 +        } else {
57672 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57673 +                            ("Invalid direction: 0x%08x\n", request));
57674 +            status = A_EINVAL;
57675 +            break;
57676 +        }
57677 +
57678 +        if (request & HIF_FIXED_ADDRESS) {
57679 +            opcode = CMD53_FIXED_ADDRESS;
57680 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Fixed\n"));
57681 +        } else if (request & HIF_INCREMENTAL_ADDRESS) {
57682 +            opcode = CMD53_INCR_ADDRESS;
57683 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Incremental\n"));
57684 +        } else {
57685 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57686 +                            ("Invalid address mode: 0x%08x\n", request));
57687 +            status = A_EINVAL;
57688 +            break;
57689 +        }
57690 +
57691 +        funcNo = SDDEVICE_GET_SDIO_FUNCNO(device->handle);
57692 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Function number: %d\n", funcNo));
57693 +        SDIO_SET_CMD53_ARG(sdrequest->Argument, rw, funcNo,
57694 +                           mode, opcode, address, count);
57695 +
57696 +        /* Send the command out */
57697 +        sdiostatus = SDDEVICE_CALL_REQUEST_FUNC(device->handle, sdrequest);
57698 +
57699 +        if (!SDIO_SUCCESS(sdiostatus)) {
57700 +            status = A_ERROR;
57701 +        }
57702 +
57703 +    } while (FALSE);
57704 +
57705 +    if (A_FAILED(status) || (request & HIF_SYNCHRONOUS)) {
57706 +        if (busrequest != NULL) {
57707 +            hifFreeBusRequest(busrequest);
57708 +        }
57709 +    }
57710 +
57711 +    if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
57712 +            /* call back async handler on failure */
57713 +        htcCallbacks.rwCompletionHandler(context, status);
57714 +    }
57715 +
57716 +    return status;
57717 +}
57718 +
57719 +A_STATUS
57720 +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
57721 +                   void *config, A_UINT32 configLen)
57722 +{
57723 +    A_UINT32 count;
57724 +
57725 +    switch(opcode) {
57726 +        case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
57727 +            ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
57728 +            ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
57729 +            ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
57730 +            ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
57731 +            break;
57732 +
57733 +        case HIF_DEVICE_GET_MBOX_ADDR:
57734 +            for (count = 0; count < 4; count ++) {
57735 +                ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
57736 +            }
57737 +            break;
57738 +        case HIF_DEVICE_GET_IRQ_PROC_MODE:
57739 +                /* the SDIO stack allows the interrupts to be processed either way, ASYNC or SYNC */
57740 +            *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_ASYNC_SYNC;
57741 +            break;
57742 +        default:
57743 +            AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
57744 +                            ("Unsupported configuration opcode: %d\n", opcode));
57745 +            return A_ERROR;
57746 +    }
57747 +
57748 +    return A_OK;
57749 +}
57750 +
57751 +void
57752 +HIFShutDownDevice(HIF_DEVICE *device)
57753 +{
57754 +    A_UINT8 data;
57755 +    A_UINT32 count;
57756 +    SDIO_STATUS status;
57757 +    SDCONFIG_BUS_MODE_DATA busSettings;
57758 +    SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
57759 +
57760 +    if (device != NULL) {
57761 +        DBG_ASSERT(device->handle != NULL);
57762 +
57763 +        /* Remove the allocated current if any */
57764 +        status = SDLIB_IssueConfig(device->handle,
57765 +                                   SDCONFIG_FUNC_FREE_SLOT_CURRENT, NULL, 0);
57766 +        DBG_ASSERT(SDIO_SUCCESS(status));
57767 +
57768 +        /* Disable the card */
57769 +        fData.EnableFlags = SDCONFIG_DISABLE_FUNC;
57770 +        fData.TimeOut = 1;
57771 +        status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ENABLE_DISABLE,
57772 +                                   &fData, sizeof(fData));
57773 +        DBG_ASSERT(SDIO_SUCCESS(status));
57774 +
57775 +        /* Perform a soft I/O reset */
57776 +        data = SDIO_IO_RESET;
57777 +        status = SDLIB_IssueCMD52(device->handle, 0, SDIO_IO_ABORT_REG,
57778 +                                  &data, 1, 1);
57779 +        DBG_ASSERT(SDIO_SUCCESS(status));
57780 +
57781 +        /*
57782 +         * WAR - Codetelligence driver does not seem to shutdown correctly in 1
57783 +         * bit mode. By default it configures the HC in the 4 bit. Its later in
57784 +         * our driver that we switch to 1 bit mode. If we try to shutdown, the
57785 +         * driver hangs so we revert to 4 bit mode, to be transparent to the
57786 +         * underlying bus driver.
57787 +         */
57788 +        if (onebitmode) {
57789 +            ZERO_OBJECT(busSettings);
57790 +            busSettings.BusModeFlags = SDDEVICE_GET_BUSMODE_FLAGS(device->handle);
57791 +            SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
57792 +                                   SDCONFIG_BUS_WIDTH_4_BIT);
57793 +
57794 +            /* Issue config request to change the bus width to 4 bit */
57795 +            status = SDLIB_IssueConfig(device->handle, SDCONFIG_BUS_MODE_CTRL,
57796 +                                       &busSettings,
57797 +                                       sizeof(SDCONFIG_BUS_MODE_DATA));
57798 +            DBG_ASSERT(SDIO_SUCCESS(status));
57799 +        }
57800 +
57801 +        /* Free the bus requests */
57802 +        for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
57803 +            SDDeviceFreeRequest(device->handle, busRequest[count].request);
57804 +        }
57805 +        /* Clean up the queue */
57806 +        s_busRequestFreeQueue = NULL;
57807 +    } else {
57808 +            /* since we are unloading the driver anyways, reset all cards in case the SDIO card
57809 +             * is externally powered and we are unloading the SDIO stack.  This avoids the problem when
57810 +             * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already
57811 +             * enumerated */
57812 +        ResetAllCards();
57813 +        /* Unregister with bus driver core */
57814 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57815 +                        ("Unregistering with the bus driver\n"));
57816 +        status = SDIO_UnregisterFunction(&FunctionContext.function);
57817 +        DBG_ASSERT(SDIO_SUCCESS(status));
57818 +    }
57819 +}
57820 +
57821 +void
57822 +hifRWCompletionHandler(SDREQUEST *request)
57823 +{
57824 +    A_STATUS status;
57825 +    void *context;
57826 +    BUS_REQUEST *busrequest;
57827 +
57828 +    if (SDIO_SUCCESS(request->Status)) {
57829 +        status = A_OK;
57830 +    } else {
57831 +        status = A_ERROR;
57832 +    }
57833 +
57834 +    DBG_ASSERT(status == A_OK);
57835 +    busrequest = (BUS_REQUEST *) request->pCompleteContext;
57836 +    context = (void *) busrequest->context;
57837 +        /* free the request before calling the callback, in case the
57838 +         * callback submits another request, this guarantees that
57839 +         * there is at least 1 free request available everytime the callback
57840 +         * is invoked */
57841 +    hifFreeBusRequest(busrequest);
57842 +    htcCallbacks.rwCompletionHandler(context, status);
57843 +}
57844 +
57845 +void
57846 +hifIRQHandler(void *context)
57847 +{
57848 +    A_STATUS status;
57849 +    HIF_DEVICE *device;
57850 +
57851 +    device = (HIF_DEVICE *)context;
57852 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
57853 +    status = htcCallbacks.dsrHandler(device->htc_handle);
57854 +    DBG_ASSERT(status == A_OK);
57855 +}
57856 +
57857 +BOOL
57858 +hifDeviceInserted(SDFUNCTION *function, SDDEVICE *handle)
57859 +{
57860 +    BOOL enabled;
57861 +    A_UINT8 data;
57862 +    A_UINT32 count;
57863 +    HIF_DEVICE *device;
57864 +    SDIO_STATUS status;
57865 +    A_UINT16 maxBlocks;
57866 +    A_UINT16 maxBlockSize;
57867 +    SDCONFIG_BUS_MODE_DATA busSettings;
57868 +    SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
57869 +    TARGET_FUNCTION_CONTEXT *functionContext;
57870 +    SDCONFIG_FUNC_SLOT_CURRENT_DATA slotCurrent;
57871 +    SD_BUSCLOCK_RATE                currentBusClock;
57872 +
57873 +    DBG_ASSERT(function != NULL);
57874 +    DBG_ASSERT(handle != NULL);
57875 +
57876 +    device = addHifDevice(handle);
57877 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
57878 +    functionContext =  (TARGET_FUNCTION_CONTEXT *)function->pContext;
57879 +
57880 +    /*
57881 +     * Issue commands to get the manufacturer ID and stuff and compare it
57882 +     * against the rev Id derived from the ID registered during the
57883 +     * initialization process. Report the device only in the case there
57884 +     * is a match. In the case od SDIO, the bus driver has already queried
57885 +     * these details so we just need to use their data structures to get the
57886 +     * relevant values. Infact, the driver has already matched it against
57887 +     * the Ids that we registered with it so we dont need to the step here.
57888 +     */
57889 +
57890 +    /* Configure the SDIO Bus Width */
57891 +    if (onebitmode) {
57892 +        data = SDIO_BUS_WIDTH_1_BIT;
57893 +        status = SDLIB_IssueCMD52(handle, 0, SDIO_BUS_IF_REG, &data, 1, 1);
57894 +        if (!SDIO_SUCCESS(status)) {
57895 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57896 +                            ("Unable to set the bus width to 1 bit\n"));
57897 +            return FALSE;
57898 +        }
57899 +    }
57900 +
57901 +    /* Get current bus flags */
57902 +    ZERO_OBJECT(busSettings);
57903 +
57904 +    busSettings.BusModeFlags = SDDEVICE_GET_BUSMODE_FLAGS(handle);
57905 +    if (onebitmode) {
57906 +        SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
57907 +                               SDCONFIG_BUS_WIDTH_1_BIT);
57908 +    }
57909 +
57910 +        /* get the current operating clock, the bus driver sets us up based
57911 +         * on what our CIS reports and what the host controller can handle
57912 +         * we can use this to determine whether we want to drop our clock rate
57913 +         * down */
57914 +    currentBusClock = SDDEVICE_GET_OPER_CLOCK(handle);
57915 +    busSettings.ClockRate = currentBusClock;
57916 +
57917 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57918 +                        ("HIF currently running at: %d \n",currentBusClock));
57919 +
57920 +        /* see if HIF wants to run at a lower clock speed, we may already be
57921 +         * at that lower clock speed */
57922 +    if (currentBusClock > (SDIO_CLOCK_FREQUENCY_DEFAULT >> busspeedlow)) {
57923 +        busSettings.ClockRate = SDIO_CLOCK_FREQUENCY_DEFAULT >> busspeedlow;
57924 +        AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
57925 +                        ("HIF overriding clock to %d \n",busSettings.ClockRate));
57926 +    }
57927 +
57928 +    /* Issue config request to override clock rate */
57929 +    status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_CHANGE_BUS_MODE, &busSettings,
57930 +                               sizeof(SDCONFIG_BUS_MODE_DATA));
57931 +    if (!SDIO_SUCCESS(status)) {
57932 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57933 +                        ("Unable to configure the host clock\n"));
57934 +        return FALSE;
57935 +    } else {
57936 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57937 +                        ("Configured clock: %d, Maximum clock: %d\n",
57938 +                        busSettings.ActualClockRate,
57939 +                        SDDEVICE_GET_MAX_CLOCK(handle)));
57940 +    }
57941 +
57942 +    /*
57943 +     * Check if the target supports block mode. This result of this check
57944 +     * can be used to implement the HIFReadWrite API.
57945 +     */
57946 +    if (SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle)) {
57947 +        /* Limit block size to operational block limit or card function
57948 +           capability */
57949 +        maxBlockSize = min(SDDEVICE_GET_OPER_BLOCK_LEN(handle),
57950 +                           SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle));
57951 +
57952 +        /* check if the card support multi-block transfers */
57953 +        if (!(SDDEVICE_GET_SDIOCARD_CAPS(handle) & SDIO_CAPS_MULTI_BLOCK)) {
57954 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Byte basis only\n"));
57955 +
57956 +            /* Limit block size to max byte basis */
57957 +            maxBlockSize =  min(maxBlockSize,
57958 +                                (A_UINT16)SDIO_MAX_LENGTH_BYTE_BASIS);
57959 +            maxBlocks = 1;
57960 +        } else {
57961 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Multi-block capable\n"));
57962 +            maxBlocks = SDDEVICE_GET_OPER_BLOCKS(handle);
57963 +            status = SDLIB_SetFunctionBlockSize(handle, HIF_MBOX_BLOCK_SIZE);
57964 +            if (!SDIO_SUCCESS(status)) {
57965 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57966 +                                ("Failed to set block size. Err:%d\n", status));
57967 +                return FALSE;
57968 +            }
57969 +        }
57970 +
57971 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
57972 +                        ("Bytes Per Block: %d bytes, Block Count:%d \n",
57973 +                        maxBlockSize, maxBlocks));
57974 +    } else {
57975 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57976 +                        ("Function does not support Block Mode!\n"));
57977 +        return FALSE;
57978 +    }
57979 +
57980 +    /* Allocate the slot current */
57981 +    status = SDLIB_GetDefaultOpCurrent(handle, &slotCurrent.SlotCurrent);
57982 +    if (SDIO_SUCCESS(status)) {
57983 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Allocating Slot current: %d mA\n",
57984 +                                slotCurrent.SlotCurrent));
57985 +        status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
57986 +                                   &slotCurrent, sizeof(slotCurrent));
57987 +        if (!SDIO_SUCCESS(status)) {
57988 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
57989 +                            ("Failed to allocate slot current %d\n", status));
57990 +            return FALSE;
57991 +        }
57992 +    }
57993 +
57994 +    /* Enable the dragon function */
57995 +    count = 0;
57996 +    enabled = FALSE;
57997 +    fData.TimeOut = 1;
57998 +    fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
57999 +    while ((count++ < SDWLAN_ENABLE_DISABLE_TIMEOUT) && !enabled)
58000 +    {
58001 +        /* Enable dragon */
58002 +        status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ENABLE_DISABLE,
58003 +                                   &fData, sizeof(fData));
58004 +        if (!SDIO_SUCCESS(status)) {
58005 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
58006 +                            ("Attempting to enable the card again\n"));
58007 +            continue;
58008 +        }
58009 +
58010 +        /* Mark the status as enabled */
58011 +        enabled = TRUE;
58012 +    }
58013 +
58014 +    /* Check if we were succesful in enabling the target */
58015 +    if (!enabled) {
58016 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
58017 +                        ("Failed to communicate with the target\n"));
58018 +        return FALSE;
58019 +    }
58020 +
58021 +    /* Allocate the bus requests to be used later */
58022 +    A_MEMZERO(busRequest, sizeof(busRequest));
58023 +    for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
58024 +        if ((busRequest[count].request = SDDeviceAllocRequest(handle)) == NULL){
58025 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Unable to allocate memory\n"));
58026 +            /* TODO: Free the memory that has already been allocated */
58027 +            return FALSE;
58028 +        }
58029 +        hifFreeBusRequest(&busRequest[count]);
58030 +
58031 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
58032 +                ("0x%08x = busRequest[%d].request = 0x%08x\n",
58033 +                               (unsigned int) &busRequest[count], count,
58034 +                               (unsigned int) busRequest[count].request));
58035 +    }
58036 +
58037 +        /* Schedule a worker to handle device inserted, this is a temporary workaround
58038 +         * to fix a deadlock if the device fails to intialize in the insertion handler
58039 +         * The failure causes the instance to shutdown the HIF layer and unregister the
58040 +         * function driver within the busdriver probe context which can deadlock
58041 +         *
58042 +         * NOTE: we cannot use the default work queue because that would block
58043 +         * SD bus request processing for all synchronous I/O. We must use a kernel
58044 +         * thread that is creating using the helper library.
58045 +         * */
58046 +
58047 +    if (SDIO_SUCCESS(SDLIB_OSCreateHelper(&device->insert_helper,
58048 +                         insert_helper_func,
58049 +                         device))) {
58050 +        device->helper_started = TRUE;
58051 +    }
58052 +
58053 +    return TRUE;
58054 +}
58055 +
58056 +static THREAD_RETURN insert_helper_func(POSKERNEL_HELPER pHelper)
58057 +{
58058 +
58059 +    /*
58060 +     * Adding a wait of around a second before we issue the very first
58061 +     * command to dragon. During the process of loading/unloading the
58062 +     * driver repeatedly it was observed that we get a data timeout
58063 +     * while accessing function 1 registers in the chip. The theory at
58064 +     * this point is that some initialization delay in dragon is
58065 +     * causing the SDIO state in dragon core to be not ready even after
58066 +     * the ready bit indicates that function 1 is ready. Accomodating
58067 +     * for this behavior by adding some delay in the driver before it
58068 +     * issues the first command after switching on dragon. Need to
58069 +     * investigate this a bit more - TODO
58070 +     */
58071 +
58072 +    A_MDELAY(1000);
58073 +        /* Inform HTC */
58074 +    if ((htcCallbacks.deviceInsertedHandler(SD_GET_OS_HELPER_CONTEXT(pHelper))) != A_OK) {
58075 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device rejected\n"));
58076 +    }
58077 +
58078 +    return 0;
58079 +}
58080 +
58081 +void
58082 +HIFAckInterrupt(HIF_DEVICE *device)
58083 +{
58084 +    SDIO_STATUS status;
58085 +    DBG_ASSERT(device != NULL);
58086 +    DBG_ASSERT(device->handle != NULL);
58087 +
58088 +    /* Acknowledge our function IRQ */
58089 +    status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ACK_IRQ,
58090 +                               NULL, 0);
58091 +    DBG_ASSERT(SDIO_SUCCESS(status));
58092 +}
58093 +
58094 +void
58095 +HIFUnMaskInterrupt(HIF_DEVICE *device)
58096 +{
58097 +    SDIO_STATUS status;
58098 +
58099 +    DBG_ASSERT(device != NULL);
58100 +    DBG_ASSERT(device->handle != NULL);
58101 +
58102 +    /* Register the IRQ Handler */
58103 +    SDDEVICE_SET_IRQ_HANDLER(device->handle, hifIRQHandler, device);
58104 +
58105 +    /* Unmask our function IRQ */
58106 +    status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_UNMASK_IRQ,
58107 +                               NULL, 0);
58108 +    DBG_ASSERT(SDIO_SUCCESS(status));
58109 +}
58110 +
58111 +void HIFMaskInterrupt(HIF_DEVICE *device)
58112 +{
58113 +    SDIO_STATUS status;
58114 +    DBG_ASSERT(device != NULL);
58115 +    DBG_ASSERT(device->handle != NULL);
58116 +
58117 +    /* Mask our function IRQ */
58118 +    status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_MASK_IRQ,
58119 +                               NULL, 0);
58120 +    DBG_ASSERT(SDIO_SUCCESS(status));
58121 +
58122 +    /* Unregister the IRQ Handler */
58123 +    SDDEVICE_SET_IRQ_HANDLER(device->handle, NULL, NULL);
58124 +}
58125 +
58126 +static BUS_REQUEST *hifAllocateBusRequest(void)
58127 +{
58128 +    BUS_REQUEST *busrequest;
58129 +
58130 +    /* Acquire lock */
58131 +    CriticalSectionAcquire(&lock);
58132 +
58133 +    /* Remove first in list */
58134 +    if((busrequest = s_busRequestFreeQueue) != NULL)
58135 +    {
58136 +        s_busRequestFreeQueue = busrequest->next;
58137 +    }
58138 +
58139 +    /* Release lock */
58140 +    CriticalSectionRelease(&lock);
58141 +
58142 +    return busrequest;
58143 +}
58144 +
58145 +static void
58146 +hifFreeBusRequest(BUS_REQUEST *busrequest)
58147 +{
58148 +    DBG_ASSERT(busrequest != NULL);
58149 +
58150 +    /* Acquire lock */
58151 +    CriticalSectionAcquire(&lock);
58152 +
58153 +    /* Insert first in list */
58154 +    busrequest->next = s_busRequestFreeQueue;
58155 +    s_busRequestFreeQueue = busrequest;
58156 +
58157 +    /* Release lock */
58158 +    CriticalSectionRelease(&lock);
58159 +}
58160 +
58161 +void
58162 +hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *handle)
58163 +{
58164 +    A_STATUS status;
58165 +    HIF_DEVICE *device;
58166 +    DBG_ASSERT(function != NULL);
58167 +    DBG_ASSERT(handle != NULL);
58168 +
58169 +    device = getHifDevice(handle);
58170 +    status = htcCallbacks.deviceRemovedHandler(device->htc_handle, A_OK);
58171 +
58172 +        /* cleanup the helper thread */
58173 +    if (device->helper_started) {
58174 +        SDLIB_OSDeleteHelper(&device->insert_helper);
58175 +        device->helper_started = FALSE;
58176 +    }
58177 +
58178 +    delHifDevice(handle);
58179 +    DBG_ASSERT(status == A_OK);
58180 +}
58181 +
58182 +HIF_DEVICE *
58183 +addHifDevice(SDDEVICE *handle)
58184 +{
58185 +    DBG_ASSERT(handle != NULL);
58186 +    hifDevice[0].handle = handle;
58187 +    return &hifDevice[0];
58188 +}
58189 +
58190 +HIF_DEVICE *
58191 +getHifDevice(SDDEVICE *handle)
58192 +{
58193 +    DBG_ASSERT(handle != NULL);
58194 +    return &hifDevice[0];
58195 +}
58196 +
58197 +void
58198 +delHifDevice(SDDEVICE *handle)
58199 +{
58200 +    DBG_ASSERT(handle != NULL);
58201 +    hifDevice[0].handle = NULL;
58202 +}
58203 +
58204 +struct device*
58205 +HIFGetOSDevice(HIF_DEVICE *device)
58206 +{
58207 +    return &device->handle->Device->dev;
58208 +}
58209 +
58210 +static void ResetAllCards(void)
58211 +{
58212 +    UINT8       data;
58213 +    SDIO_STATUS status;
58214 +    int         i;
58215 +
58216 +    data = SDIO_IO_RESET;
58217 +
58218 +    /* set the I/O CARD reset bit:
58219 +     * NOTE: we are exploiting a "feature" of the SDIO core that resets the core when you
58220 +     * set the RES bit in the SDIO_IO_ABORT register.  This bit however "normally" resets the
58221 +     * I/O functions leaving the SDIO core in the same state (as per SDIO spec).
58222 +     * In this design, this reset can be used to reset the SDIO core itself */
58223 +    for (i = 0; i < HIF_MAX_DEVICES; i++) {
58224 +        if (hifDevice[i].handle != NULL) {
58225 +            AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
58226 +                        ("Issuing I/O Card reset for instance: %d \n",i));
58227 +                /* set the I/O Card reset bit */
58228 +            status = SDLIB_IssueCMD52(hifDevice[i].handle,
58229 +                                      0,                    /* function 0 space */
58230 +                                      SDIO_IO_ABORT_REG,
58231 +                                      &data,
58232 +                                      1,                    /* 1 byte */
58233 +                                      TRUE);                /* write */
58234 +        }
58235 +    }
58236 +
58237 +}
58238 +
58239 +void HIFSetHandle(void *hif_handle, void *handle)
58240 +{
58241 +    HIF_DEVICE *device = (HIF_DEVICE *) hif_handle;
58242 +
58243 +    device->htc_handle = handle;
58244 +
58245 +    return;
58246 +}
58247 Index: linux-2.6.28/drivers/ar6000/hif/hif_internal.h
58248 ===================================================================
58249 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
58250 +++ linux-2.6.28/drivers/ar6000/hif/hif_internal.h      2009-01-02 00:01:56.000000000 +0100
58251 @@ -0,0 +1,102 @@
58252 +/*
58253 + * @file: hif_internal.h
58254 + *
58255 + * @abstract: internal header file for hif layer
58256 + *
58257 + * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
58258 + *
58259 + *
58260 + *  This program is free software; you can redistribute it and/or modify
58261 + *  it under the terms of the GNU General Public License version 2 as
58262 + *  published by the Free Software Foundation;
58263 + *
58264 + *  Software distributed under the License is distributed on an "AS
58265 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
58266 + *  implied. See the License for the specific language governing
58267 + *  rights and limitations under the License.
58268 + *
58269 + *
58270 + *
58271 + */
58272 +
58273 +#include <linux/sdio/ctsystem.h>
58274 +#include <linux/sdio/sdio_busdriver.h>
58275 +#include <linux/sdio/_sdio_defs.h>
58276 +#include <linux/sdio/sdio_lib.h>
58277 +#include "a_config.h"
58278 +#include "athdefs.h"
58279 +#include "a_types.h"
58280 +#include "a_osapi.h"
58281 +#include "hif.h"
58282 +
58283 +#define MANUFACTURER_ID_AR6001_BASE        0x100
58284 +#define MANUFACTURER_ID_AR6002_BASE        0x200
58285 +#define FUNCTION_CLASS                     0x0
58286 +#define MANUFACTURER_CODE                  0x271
58287 +
58288 +#define BUS_REQUEST_MAX_NUM                64
58289 +
58290 +#define SDIO_CLOCK_FREQUENCY_DEFAULT       25000000
58291 +#define SDWLAN_ENABLE_DISABLE_TIMEOUT      20
58292 +#define FLAGS_CARD_ENAB                    0x02
58293 +#define FLAGS_CARD_IRQ_UNMSK               0x04
58294 +
58295 +#define HIF_MBOX_BLOCK_SIZE                128
58296 +#define HIF_MBOX_BASE_ADDR                 0x800
58297 +#define HIF_MBOX_WIDTH                     0x800
58298 +#define HIF_MBOX0_BLOCK_SIZE               1
58299 +#define HIF_MBOX1_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
58300 +#define HIF_MBOX2_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
58301 +#define HIF_MBOX3_BLOCK_SIZE               HIF_MBOX_BLOCK_SIZE
58302 +
58303 +#define HIF_MBOX_START_ADDR(mbox)                        \
58304 +    HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH
58305 +
58306 +#define HIF_MBOX_END_ADDR(mbox)                                 \
58307 +    HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1
58308 +
58309 +struct hif_device {
58310 +    SDDEVICE *handle;
58311 +    void *htc_handle;
58312 +    OSKERNEL_HELPER insert_helper;
58313 +    BOOL  helper_started;
58314 +};
58315 +
58316 +typedef struct target_function_context {
58317 +    SDFUNCTION           function; /* function description of the bus driver */
58318 +    OS_SEMAPHORE         instanceSem; /* instance lock. Unused */
58319 +    SDLIST               instanceList; /* list of instances. Unused */
58320 +} TARGET_FUNCTION_CONTEXT;
58321 +
58322 +typedef struct bus_request {
58323 +    struct bus_request *next;
58324 +    SDREQUEST *request;
58325 +    void *context;
58326 +} BUS_REQUEST;
58327 +
58328 +BOOL
58329 +hifDeviceInserted(SDFUNCTION *function, SDDEVICE *device);
58330 +
58331 +void
58332 +hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *device);
58333 +
58334 +SDREQUEST *
58335 +hifAllocateDeviceRequest(SDDEVICE *device);
58336 +
58337 +void
58338 +hifFreeDeviceRequest(SDREQUEST *request);
58339 +
58340 +void
58341 +hifRWCompletionHandler(SDREQUEST *request);
58342 +
58343 +void
58344 +hifIRQHandler(void *context);
58345 +
58346 +HIF_DEVICE *
58347 +addHifDevice(SDDEVICE *handle);
58348 +
58349 +HIF_DEVICE *
58350 +getHifDevice(SDDEVICE *handle);
58351 +
58352 +void
58353 +delHifDevice(SDDEVICE *handle);
58354 Index: linux-2.6.28/drivers/ar6000/htc/ar6k.c
58355 ===================================================================
58356 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
58357 +++ linux-2.6.28/drivers/ar6000/htc/ar6k.c      2009-01-02 00:01:56.000000000 +0100
58358 @@ -0,0 +1,991 @@
58359 +/*
58360 + * AR6K device layer that handles register level I/O
58361 + *
58362 + * Copyright (c) 2007 Atheros Communications Inc.
58363 + * All rights reserved.
58364 + *
58365 + *
58366 + *  This program is free software; you can redistribute it and/or modify
58367 + *  it under the terms of the GNU General Public License version 2 as
58368 + *  published by the Free Software Foundation;
58369 + *
58370 + *  Software distributed under the License is distributed on an "AS
58371 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
58372 + *  implied. See the License for the specific language governing
58373 + *  rights and limitations under the License.
58374 + *
58375 + *
58376 + *
58377 + */
58378 +#include "a_config.h"
58379 +#include "athdefs.h"
58380 +#include "a_types.h"
58381 +#include "AR6Khwreg.h"
58382 +#include "a_osapi.h"
58383 +#include "a_debug.h"
58384 +#include "hif.h"
58385 +#include "htc_packet.h"
58386 +#include "ar6k.h"
58387 +
58388 +#define MAILBOX_FOR_BLOCK_SIZE 1
58389 +
58390 +extern A_UINT32 resetok;
58391 +
58392 +static A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
58393 +static A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
58394 +
58395 +#define LOCK_AR6K(p)      A_MUTEX_LOCK(&(p)->Lock);
58396 +#define UNLOCK_AR6K(p)    A_MUTEX_UNLOCK(&(p)->Lock);
58397 +
58398 +void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket)
58399 +{
58400 +    LOCK_AR6K(pDev);
58401 +    HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket);
58402 +    UNLOCK_AR6K(pDev);
58403 +}
58404 +
58405 +HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev)
58406 +{
58407 +    HTC_PACKET *pPacket;
58408 +
58409 +    LOCK_AR6K(pDev);
58410 +    pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList);
58411 +    UNLOCK_AR6K(pDev);
58412 +
58413 +    return pPacket;
58414 +}
58415 +
58416 +A_STATUS DevSetup(AR6K_DEVICE *pDev)
58417 +{
58418 +    A_UINT32 mailboxaddrs[AR6K_MAILBOXES];
58419 +    A_UINT32 blocksizes[AR6K_MAILBOXES];
58420 +    A_STATUS status = A_OK;
58421 +    int      i;
58422 +
58423 +    AR_DEBUG_ASSERT(AR6K_IRQ_PROC_REGS_SIZE == 16);
58424 +    AR_DEBUG_ASSERT(AR6K_IRQ_ENABLE_REGS_SIZE == 4);
58425 +
58426 +    do {
58427 +            /* give a handle to HIF for this target */
58428 +        HIFSetHandle(pDev->HIFDevice, (void *)pDev);
58429 +            /* initialize our free list of IO packets */
58430 +        INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
58431 +        A_MUTEX_INIT(&pDev->Lock);
58432 +
58433 +            /* get the addresses for all 4 mailboxes */
58434 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
58435 +                                    mailboxaddrs, sizeof(mailboxaddrs));
58436 +
58437 +        if (status != A_OK) {
58438 +            AR_DEBUG_ASSERT(FALSE);
58439 +            break;
58440 +        }
58441 +
58442 +            /* carve up register I/O packets (these are for ASYNC register I/O ) */
58443 +        for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
58444 +            HTC_PACKET *pIOPacket;
58445 +            pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
58446 +            SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
58447 +                                          pDev,
58448 +                                          pDev->RegIOBuffers[i].Buffer,
58449 +                                          AR6K_REG_IO_BUFFER_SIZE,
58450 +                                          0); /* don't care */
58451 +            AR6KFreeIOPacket(pDev,pIOPacket);
58452 +        }
58453 +
58454 +            /* get the address of the mailbox we are using */
58455 +        pDev->MailboxAddress = mailboxaddrs[HTC_MAILBOX];
58456 +
58457 +            /* get the block sizes */
58458 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
58459 +                                    blocksizes, sizeof(blocksizes));
58460 +
58461 +        if (status != A_OK) {
58462 +            AR_DEBUG_ASSERT(FALSE);
58463 +            break;
58464 +        }
58465 +
58466 +            /* note: we actually get the block size of a mailbox other than 0, for SDIO the block
58467 +             * size on mailbox 0 is artificially set to 1.  So we use the block size that is set
58468 +             * for the other 3 mailboxes */
58469 +        pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
58470 +            /* must be a power of 2 */
58471 +        AR_DEBUG_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
58472 +
58473 +            /* assemble mask, used for padding to a block */
58474 +        pDev->BlockMask = pDev->BlockSize - 1;
58475 +
58476 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
58477 +                    pDev->BlockSize, pDev->MailboxAddress));
58478 +
58479 +        pDev->GetPendingEventsFunc = NULL;
58480 +            /* see if the HIF layer implements the get pending events function  */
58481 +        HIFConfigureDevice(pDev->HIFDevice,
58482 +                           HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
58483 +                           &pDev->GetPendingEventsFunc,
58484 +                           sizeof(pDev->GetPendingEventsFunc));
58485 +
58486 +            /* assume we can process HIF interrupt events asynchronously */
58487 +        pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
58488 +
58489 +            /* see if the HIF layer overrides this assumption */
58490 +        HIFConfigureDevice(pDev->HIFDevice,
58491 +                           HIF_DEVICE_GET_IRQ_PROC_MODE,
58492 +                           &pDev->HifIRQProcessingMode,
58493 +                           sizeof(pDev->HifIRQProcessingMode));
58494 +
58495 +        switch (pDev->HifIRQProcessingMode) {
58496 +            case HIF_DEVICE_IRQ_SYNC_ONLY:
58497 +                AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is SYNC ONLY\n"));
58498 +                break;
58499 +            case HIF_DEVICE_IRQ_ASYNC_SYNC:
58500 +                AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
58501 +                break;
58502 +            default:
58503 +                AR_DEBUG_ASSERT(FALSE);
58504 +        }
58505 +
58506 +        pDev->HifMaskUmaskRecvEvent = NULL;
58507 +
58508 +            /* see if the HIF layer implements the mask/unmask recv events function  */
58509 +        HIFConfigureDevice(pDev->HIFDevice,
58510 +                           HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
58511 +                           &pDev->HifMaskUmaskRecvEvent,
58512 +                           sizeof(pDev->HifMaskUmaskRecvEvent));
58513 +
58514 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n",
58515 +                 (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent));
58516 +
58517 +        status = DevDisableInterrupts(pDev);
58518 +
58519 +    } while (FALSE);
58520 +
58521 +    if (A_FAILED(status)) {
58522 +            /* make sure handle is cleared */
58523 +        HIFSetHandle(pDev->HIFDevice, NULL);
58524 +    }
58525 +
58526 +    return status;
58527 +
58528 +}
58529 +
58530 +static A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev)
58531 +{
58532 +    A_STATUS                  status;
58533 +    AR6K_IRQ_ENABLE_REGISTERS regs;
58534 +
58535 +    LOCK_AR6K(pDev);
58536 +
58537 +        /* Enable all the interrupts except for the dragon interrupt */
58538 +    pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
58539 +                                      INT_STATUS_ENABLE_CPU_SET(0x01) |
58540 +                                      INT_STATUS_ENABLE_COUNTER_SET(0x01);
58541 +
58542 +    if (NULL == pDev->GetPendingEventsFunc) {
58543 +        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
58544 +    } else {
58545 +        /* The HIF layer provided us with a pending events function which means that
58546 +         * the detection of pending mbox messages is handled in the HIF layer.
58547 +         * This is the case for the SPI2 interface.
58548 +         * In the normal case we enable MBOX interrupts, for the case
58549 +         * with HIFs that offer this mechanism, we keep these interrupts
58550 +         * masked */
58551 +        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
58552 +    }
58553 +
58554 +
58555 +    /* Set up the CPU Interrupt Status Register */
58556 +    pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
58557 +
58558 +    /* Set up the Error Interrupt Status Register */
58559 +    pDev->IrqEnableRegisters.error_status_enable =
58560 +                                  ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
58561 +                                  ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
58562 +
58563 +    /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */
58564 +    pDev->IrqEnableRegisters.counter_int_status_enable =
58565 +        COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK);
58566 +
58567 +        /* copy into our temp area */
58568 +    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
58569 +
58570 +    UNLOCK_AR6K(pDev);
58571 +
58572 +        /* always synchronous */
58573 +    status = HIFReadWrite(pDev->HIFDevice,
58574 +                          INT_STATUS_ENABLE_ADDRESS,
58575 +                          &regs.int_status_enable,
58576 +                          AR6K_IRQ_ENABLE_REGS_SIZE,
58577 +                          HIF_WR_SYNC_BYTE_INC,
58578 +                          NULL);
58579 +
58580 +    if (status != A_OK) {
58581 +        /* Can't write it for some reason */
58582 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
58583 +                        ("Failed to update interrupt control registers err: %d\n", status));
58584 +
58585 +    }
58586 +
58587 +    return status;
58588 +}
58589 +
58590 +static A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev)
58591 +{
58592 +    AR6K_IRQ_ENABLE_REGISTERS regs;
58593 +
58594 +    LOCK_AR6K(pDev);
58595 +        /* Disable all interrupts */
58596 +    pDev->IrqEnableRegisters.int_status_enable = 0;
58597 +    pDev->IrqEnableRegisters.cpu_int_status_enable = 0;
58598 +    pDev->IrqEnableRegisters.error_status_enable = 0;
58599 +    pDev->IrqEnableRegisters.counter_int_status_enable = 0;
58600 +        /* copy into our temp area */
58601 +    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
58602 +
58603 +    UNLOCK_AR6K(pDev);
58604 +
58605 +        /* always synchronous */
58606 +    return HIFReadWrite(pDev->HIFDevice,
58607 +                        INT_STATUS_ENABLE_ADDRESS,
58608 +                        &regs.int_status_enable,
58609 +                        AR6K_IRQ_ENABLE_REGS_SIZE,
58610 +                        HIF_WR_SYNC_BYTE_INC,
58611 +                        NULL);
58612 +}
58613 +
58614 +/* enable device interrupts */
58615 +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev)
58616 +{
58617 +        /* Unmask the host controller interrupts */
58618 +    HIFUnMaskInterrupt(pDev->HIFDevice);
58619 +
58620 +    return DevEnableInterrupts(pDev);
58621 +}
58622 +
58623 +/* disable all device interrupts */
58624 +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
58625 +{
58626 +    A_STATUS status;
58627 +
58628 +    status = DevDisableInterrupts(pDev);
58629 +
58630 +    if (A_SUCCESS(status)) {
58631 +            /* Disable the interrupt at the HIF layer */
58632 +        HIFMaskInterrupt(pDev->HIFDevice);
58633 +    }
58634 +
58635 +    return status;
58636 +}
58637 +
58638 +/* callback when our fetch to enable/disable completes */
58639 +static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket)
58640 +{
58641 +    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
58642 +
58643 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
58644 +
58645 +    if (A_FAILED(pPacket->Status)) {
58646 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
58647 +                (" Failed to disable receiver, status:%d \n", pPacket->Status));
58648 +    }
58649 +        /* free this IO packet */
58650 +    AR6KFreeIOPacket(pDev,pPacket);
58651 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n"));
58652 +}
58653 +
58654 +/* disable packet reception (used in case the host runs out of buffers)
58655 + * this is the "override" method when the HIF reports another methods to
58656 + * disable recv events */
58657 +static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
58658 +{
58659 +    A_STATUS                  status = A_OK;
58660 +    HTC_PACKET                *pIOPacket = NULL;
58661 +
58662 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n",
58663 +            EnableRecv,AsyncMode));
58664 +
58665 +    do {
58666 +
58667 +        if (AsyncMode) {
58668 +
58669 +            pIOPacket = AR6KAllocIOPacket(pDev);
58670 +
58671 +            if (NULL == pIOPacket) {
58672 +                status = A_NO_MEMORY;
58673 +                AR_DEBUG_ASSERT(FALSE);
58674 +                break;
58675 +            }
58676 +
58677 +                /* stick in our completion routine when the I/O operation completes */
58678 +            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
58679 +            pIOPacket->pContext = pDev;
58680 +
58681 +                /* call the HIF layer override and do this asynchronously */
58682 +            status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
58683 +                                                 EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
58684 +                                                 pIOPacket);
58685 +            break;
58686 +        }
58687 +
58688 +            /* if we get here we are doing it synchronously */
58689 +        status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
58690 +                                             EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
58691 +                                             NULL);
58692 +
58693 +    } while (FALSE);
58694 +
58695 +    if (A_FAILED(status) && (pIOPacket != NULL)) {
58696 +        AR6KFreeIOPacket(pDev,pIOPacket);
58697 +    }
58698 +
58699 +    return status;
58700 +}
58701 +
58702 +/* disable packet reception (used in case the host runs out of buffers)
58703 + * this is the "normal" method using the interrupt enable registers through
58704 + * the host I/F */
58705 +static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
58706 +{
58707 +    A_STATUS                  status = A_OK;
58708 +    HTC_PACKET                *pIOPacket = NULL;
58709 +    AR6K_IRQ_ENABLE_REGISTERS regs;
58710 +
58711 +        /* take the lock to protect interrupt enable shadows */
58712 +    LOCK_AR6K(pDev);
58713 +
58714 +    if (EnableRecv) {
58715 +        pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
58716 +    } else {
58717 +        pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
58718 +    }
58719 +
58720 +        /* copy into our temp area */
58721 +    A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
58722 +    UNLOCK_AR6K(pDev);
58723 +
58724 +    do {
58725 +
58726 +        if (AsyncMode) {
58727 +
58728 +            pIOPacket = AR6KAllocIOPacket(pDev);
58729 +
58730 +            if (NULL == pIOPacket) {
58731 +                status = A_NO_MEMORY;
58732 +                AR_DEBUG_ASSERT(FALSE);
58733 +                break;
58734 +            }
58735 +
58736 +                /* copy values to write to our async I/O buffer */
58737 +            A_MEMCPY(pIOPacket->pBuffer,&regs,AR6K_IRQ_ENABLE_REGS_SIZE);
58738 +
58739 +                /* stick in our completion routine when the I/O operation completes */
58740 +            pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
58741 +            pIOPacket->pContext = pDev;
58742 +
58743 +                /* write it out asynchronously */
58744 +            HIFReadWrite(pDev->HIFDevice,
58745 +                         INT_STATUS_ENABLE_ADDRESS,
58746 +                         pIOPacket->pBuffer,
58747 +                         AR6K_IRQ_ENABLE_REGS_SIZE,
58748 +                         HIF_WR_ASYNC_BYTE_INC,
58749 +                         pIOPacket);
58750 +            break;
58751 +        }
58752 +
58753 +        /* if we get here we are doing it synchronously */
58754 +
58755 +        status = HIFReadWrite(pDev->HIFDevice,
58756 +                              INT_STATUS_ENABLE_ADDRESS,
58757 +                              &regs.int_status_enable,
58758 +                              AR6K_IRQ_ENABLE_REGS_SIZE,
58759 +                              HIF_WR_SYNC_BYTE_INC,
58760 +                              NULL);
58761 +
58762 +    } while (FALSE);
58763 +
58764 +    if (A_FAILED(status) && (pIOPacket != NULL)) {
58765 +        AR6KFreeIOPacket(pDev,pIOPacket);
58766 +    }
58767 +
58768 +    return status;
58769 +}
58770 +
58771 +
58772 +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
58773 +{
58774 +    if (NULL == pDev->HifMaskUmaskRecvEvent) {
58775 +        return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode);
58776 +    } else {
58777 +        return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode);
58778 +    }
58779 +}
58780 +
58781 +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
58782 +{
58783 +    if (NULL == pDev->HifMaskUmaskRecvEvent) {
58784 +        return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode);
58785 +    } else {
58786 +        return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode);
58787 +    }
58788 +}
58789 +
58790 +void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
58791 +                      AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs)
58792 +{
58793 +
58794 +    AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\n"));
58795 +
58796 +    if (pIrqProcRegs != NULL) {
58797 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58798 +            ("Int Status:               0x%x\n",pIrqProcRegs->host_int_status));
58799 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58800 +            ("CPU Int Status:            0x%x\n",pIrqProcRegs->cpu_int_status));
58801 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58802 +            ("Error Int Status:          0x%x\n",pIrqProcRegs->error_int_status));
58803 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58804 +            ("Counter Int Status:        0x%x\n",pIrqProcRegs->counter_int_status));
58805 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58806 +            ("Mbox Frame:                0x%x\n",pIrqProcRegs->mbox_frame));
58807 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58808 +            ("Rx Lookahead Valid:        0x%x\n",pIrqProcRegs->rx_lookahead_valid));
58809 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58810 +            ("Rx Lookahead 0:            0x%x\n",pIrqProcRegs->rx_lookahead[0]));
58811 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58812 +            ("Rx Lookahead 1:            0x%x\n",pIrqProcRegs->rx_lookahead[1]));
58813 +    }
58814 +
58815 +    if (pIrqEnableRegs != NULL) {
58816 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58817 +            ("Int Status Enable:         0x%x\n",pIrqEnableRegs->int_status_enable));
58818 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
58819 +            ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable));
58820 +        AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("<------------------------------->\n"));
58821 +    }
58822 +}
58823 +
58824 +
58825 +#ifdef MBOXHW_UNIT_TEST
58826 +
58827 +
58828 +/* This is a mailbox hardware unit test that must be called in a schedulable context
58829 + * This test is very simple, it will send a list of buffers with a counting pattern
58830 + * and the target will invert the data and send the message back
58831 + *
58832 + * the unit test has the following constraints:
58833 + *
58834 + * The target has at least 8 buffers of 256 bytes each. The host will send
58835 + * the following pattern of buffers in rapid succession :
58836 + *
58837 + * 1 buffer - 128 bytes
58838 + * 1 buffer - 256 bytes
58839 + * 1 buffer - 512 bytes
58840 + * 1 buffer - 1024 bytes
58841 + *
58842 + * The host will send the buffers to one mailbox and wait for buffers to be reflected
58843 + * back from the same mailbox. The target sends the buffers FIFO order.
58844 + * Once the final buffer has been received for a mailbox, the next mailbox is tested.
58845 + *
58846 + *
58847 + * Note:  To simplifythe test , we assume that the chosen buffer sizes
58848 + *        will fall on a nice block pad
58849 + *
58850 + * It is expected that higher-order tests will be written to stress the mailboxes using
58851 + * a message-based protocol (with some performance timming) that can create more
58852 + * randomness in the packets sent over mailboxes.
58853 + *
58854 + * */
58855 +
58856 +#define A_ROUND_UP_PWR2(x, align)    (((int) (x) + ((align)-1)) & ~((align)-1))
58857 +
58858 +#define BUFFER_BLOCK_PAD 128
58859 +
58860 +#if 0
58861 +#define BUFFER1 128
58862 +#define BUFFER2 256
58863 +#define BUFFER3 512
58864 +#define BUFFER4 1024
58865 +#endif
58866 +
58867 +#if 1
58868 +#define BUFFER1 80
58869 +#define BUFFER2 200
58870 +#define BUFFER3 444
58871 +#define BUFFER4 800
58872 +#endif
58873 +
58874 +#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \
58875 +                     A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \
58876 +                     A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \
58877 +                     A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) )
58878 +
58879 +#define TEST_BYTES (BUFFER1 +  BUFFER2 + BUFFER3 + BUFFER4)
58880 +
58881 +#define TEST_CREDITS_RECV_TIMEOUT 100
58882 +
58883 +static A_UINT8  g_Buffer[TOTAL_BYTES];
58884 +static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
58885 +static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
58886 +
58887 +#define BUFFER_PROC_LIST_DEPTH 4
58888 +
58889 +typedef struct _BUFFER_PROC_LIST{
58890 +    A_UINT8  *pBuffer;
58891 +    A_UINT32 length;
58892 +}BUFFER_PROC_LIST;
58893 +
58894 +
58895 +#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \
58896 +{                                                   \
58897 +    (pList)->pBuffer = (pCurrpos);                  \
58898 +    (pList)->length = (len);                        \
58899 +    (pCurrpos) += (len);                            \
58900 +    (pList)++;                                      \
58901 +}
58902 +
58903 +/* a simple and crude way to send different "message" sizes */
58904 +static void AssembleBufferList(BUFFER_PROC_LIST *pList)
58905 +{
58906 +    A_UINT8 *pBuffer = g_Buffer;
58907 +
58908 +#if BUFFER_PROC_LIST_DEPTH < 4
58909 +#error "Buffer processing list depth is not deep enough!!"
58910 +#endif
58911 +
58912 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer);
58913 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer);
58914 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer);
58915 +    PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer);
58916 +
58917 +}
58918 +
58919 +#define FILL_ZERO     TRUE
58920 +#define FILL_COUNTING FALSE
58921 +static void InitBuffers(A_BOOL Zero)
58922 +{
58923 +    A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer;
58924 +    int      i;
58925 +
58926 +        /* fill buffer with 16 bit counting pattern or zeros */
58927 +    for (i = 0; i <  (TOTAL_BYTES / 2) ; i++) {
58928 +        if (!Zero) {
58929 +            pBuffer16[i] = (A_UINT16)i;
58930 +        } else {
58931 +            pBuffer16[i] = 0;
58932 +        }
58933 +    }
58934 +}
58935 +
58936 +
58937 +static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length)
58938 +{
58939 +    int      i;
58940 +    A_UINT16 startCount;
58941 +    A_BOOL   success = TRUE;
58942 +
58943 +        /* get the starting count */
58944 +    startCount = pBuffer16[0];
58945 +        /* invert it, this is the expected value */
58946 +    startCount = ~startCount;
58947 +        /* scan the buffer and verify */
58948 +    for (i = 0; i < (Length / 2) ; i++,startCount++) {
58949 +            /* target will invert all the data */
58950 +        if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) {
58951 +            success = FALSE;
58952 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n",
58953 +                        pBuffer16[i], ((A_UINT16)~startCount), i, Length));
58954 +             AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n",
58955 +                        pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3]));
58956 +            break;
58957 +        }
58958 +    }
58959 +
58960 +    return success;
58961 +}
58962 +
58963 +static A_BOOL CheckBuffers(void)
58964 +{
58965 +    int      i;
58966 +    A_BOOL   success = TRUE;
58967 +    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
58968 +
58969 +        /* assemble the list */
58970 +    AssembleBufferList(checkList);
58971 +
58972 +        /* scan the buffers and verify */
58973 +    for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) {
58974 +        success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length);
58975 +        if (!success) {
58976 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
58977 +                        (A_UINT32)checkList[i].pBuffer, checkList[i].length));
58978 +            break;
58979 +        }
58980 +    }
58981 +
58982 +    return success;
58983 +}
58984 +
58985 +    /* find the end marker for the last buffer we will be sending */
58986 +static A_UINT16 GetEndMarker(void)
58987 +{
58988 +    A_UINT8  *pBuffer;
58989 +    BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
58990 +
58991 +        /* fill up buffers with the normal counting pattern */
58992 +    InitBuffers(FILL_COUNTING);
58993 +
58994 +        /* assemble the list we will be sending down */
58995 +    AssembleBufferList(checkList);
58996 +        /* point to the last 2 bytes of the last buffer */
58997 +    pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]);
58998 +
58999 +        /* the last count in the last buffer is the marker */
59000 +    return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8);
59001 +}
59002 +
59003 +#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR
59004 +
59005 +/* send the ordered buffers to the target */
59006 +static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox)
59007 +{
59008 +    A_STATUS         status = A_OK;
59009 +    A_UINT32         request = HIF_WR_SYNC_BLOCK_INC;
59010 +    BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
59011 +    int              i;
59012 +    int              totalBytes = 0;
59013 +    int              paddedLength;
59014 +    int              totalwPadding = 0;
59015 +
59016 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox));
59017 +
59018 +        /* fill buffer with counting pattern */
59019 +    InitBuffers(FILL_COUNTING);
59020 +
59021 +        /* assemble the order in which we send */
59022 +    AssembleBufferList(sendList);
59023 +
59024 +    for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) {
59025 +
59026 +            /* we are doing block transfers, so we need to pad everything to a block size */
59027 +        paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) &
59028 +                       (~(g_BlockSizes[mbox] - 1));
59029 +
59030 +            /* send each buffer synchronously */
59031 +        status = HIFReadWrite(pDev->HIFDevice,
59032 +                              g_MailboxAddrs[mbox],
59033 +                              sendList[i].pBuffer,
59034 +                              paddedLength,
59035 +                              request,
59036 +                              NULL);
59037 +        if (status != A_OK) {
59038 +            break;
59039 +        }
59040 +        totalBytes += sendList[i].length;
59041 +        totalwPadding += paddedLength;
59042 +    }
59043 +
59044 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox));
59045 +
59046 +    return status;
59047 +}
59048 +
59049 +/* poll the mailbox credit counter until we get a credit or timeout */
59050 +static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
59051 +{
59052 +    A_STATUS status = A_OK;
59053 +    int      timeout = TEST_CREDITS_RECV_TIMEOUT;
59054 +    A_UINT8  credits = 0;
59055 +    A_UINT32 address;
59056 +
59057 +    while (TRUE) {
59058 +
59059 +            /* Read the counter register to get credits, this auto-decrements  */
59060 +        address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4;
59061 +        status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits),
59062 +                              HIF_RD_SYNC_BYTE_FIX, NULL);
59063 +        if (status != A_OK) {
59064 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
59065 +                ("Unable to decrement the command credit count register (mbox=%d)\n",mbox));
59066 +            status = A_ERROR;
59067 +            break;
59068 +        }
59069 +
59070 +        if (credits) {
59071 +            break;
59072 +        }
59073 +
59074 +        timeout--;
59075 +
59076 +        if (timeout <= 0) {
59077 +              AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
59078 +                (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address));
59079 +            status = A_ERROR;
59080 +            break;
59081 +        }
59082 +
59083 +         /* delay a little, target may not be ready */
59084 +         A_MDELAY(1000);
59085 +
59086 +    }
59087 +
59088 +    if (status == A_OK) {
59089 +        *pCredits = credits;
59090 +    }
59091 +
59092 +    return status;
59093 +}
59094 +
59095 +
59096 +/* wait for the buffers to come back */
59097 +static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox)
59098 +{
59099 +    A_STATUS         status = A_OK;
59100 +    A_UINT32         request = HIF_RD_SYNC_BLOCK_INC;
59101 +    BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
59102 +    int              curBuffer;
59103 +    int              credits;
59104 +    int              i;
59105 +    int              totalBytes = 0;
59106 +    int              paddedLength;
59107 +    int              totalwPadding = 0;
59108 +
59109 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox));
59110 +
59111 +        /* zero the buffers */
59112 +    InitBuffers(FILL_ZERO);
59113 +
59114 +        /* assemble the order in which we should receive */
59115 +    AssembleBufferList(recvList);
59116 +
59117 +    curBuffer = 0;
59118 +
59119 +    while (curBuffer < BUFFER_PROC_LIST_DEPTH) {
59120 +
59121 +            /* get number of buffers that have been completed, this blocks
59122 +             * until we get at least 1 credit or it times out */
59123 +        status = GetCredits(pDev, mbox, &credits);
59124 +
59125 +        if (status != A_OK) {
59126 +            break;
59127 +        }
59128 +
59129 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox));
59130 +
59131 +            /* get all the buffers that are sitting on the queue */
59132 +        for (i = 0; i < credits; i++) {
59133 +            AR_DEBUG_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH);
59134 +                /* recv the current buffer synchronously, the buffers should come back in
59135 +                 * order... with padding applied by the target */
59136 +            paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) &
59137 +                       (~(g_BlockSizes[mbox] - 1));
59138 +
59139 +            status = HIFReadWrite(pDev->HIFDevice,
59140 +                                  g_MailboxAddrs[mbox],
59141 +                                  recvList[curBuffer].pBuffer,
59142 +                                  paddedLength,
59143 +                                  request,
59144 +                                  NULL);
59145 +            if (status != A_OK) {
59146 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n",
59147 +                        recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox]));
59148 +                break;
59149 +            }
59150 +
59151 +            totalwPadding += paddedLength;
59152 +            totalBytes += recvList[curBuffer].length;
59153 +            curBuffer++;
59154 +        }
59155 +
59156 +        if (status != A_OK) {
59157 +            break;
59158 +        }
59159 +            /* go back and get some more */
59160 +        credits = 0;
59161 +    }
59162 +
59163 +    if (totalBytes != TEST_BYTES) {
59164 +        AR_DEBUG_ASSERT(FALSE);
59165 +    }  else {
59166 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n",
59167 +            mbox, totalBytes, totalwPadding));
59168 +    }
59169 +
59170 +    return status;
59171 +
59172 +
59173 +}
59174 +
59175 +static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox)
59176 +{
59177 +    A_STATUS status;
59178 +
59179 +    do {
59180 +            /* send out buffers */
59181 +        status = SendBuffers(pDev,mbox);
59182 +
59183 +        if (status != A_OK) {
59184 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox));
59185 +            break;
59186 +        }
59187 +
59188 +            /* go get them, this will block */
59189 +        status =  RecvBuffers(pDev, mbox);
59190 +
59191 +        if (status != A_OK) {
59192 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox));
59193 +            break;
59194 +        }
59195 +
59196 +            /* check the returned data patterns */
59197 +        if (!CheckBuffers()) {
59198 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox));
59199 +            status = A_ERROR;
59200 +            break;
59201 +        }
59202 +
59203 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox));
59204 +
59205 +    }  while (FALSE);
59206 +
59207 +    return status;
59208 +}
59209 +
59210 +/* here is where the test starts */
59211 +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
59212 +{
59213 +    int      i;
59214 +    A_STATUS status;
59215 +    int      credits = 0;
59216 +    A_UINT8  params[4];
59217 +    int      numBufs;
59218 +    int      bufferSize;
59219 +    A_UINT16 temp;
59220 +
59221 +
59222 +    AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START -  \n"));
59223 +
59224 +    do {
59225 +            /* get the addresses for all 4 mailboxes */
59226 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
59227 +                                    g_MailboxAddrs, sizeof(g_MailboxAddrs));
59228 +
59229 +        if (status != A_OK) {
59230 +            AR_DEBUG_ASSERT(FALSE);
59231 +            break;
59232 +        }
59233 +
59234 +            /* get the block sizes */
59235 +        status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
59236 +                                    g_BlockSizes, sizeof(g_BlockSizes));
59237 +
59238 +        if (status != A_OK) {
59239 +            AR_DEBUG_ASSERT(FALSE);
59240 +            break;
59241 +        }
59242 +
59243 +            /* note, the HIF layer usually reports mbox 0 to have a block size of
59244 +             * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
59245 +             * the same. */
59246 +        g_BlockSizes[0] = g_BlockSizes[1];
59247 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
59248 +
59249 +        if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
59250 +            AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
59251 +                g_BlockSizes[1], BUFFER_BLOCK_PAD));
59252 +            break;
59253 +        }
59254 +
59255 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
59256 +
59257 +            /* the target lets us know it is ready by giving us 1 credit on
59258 +             * mailbox 0 */
59259 +        status = GetCredits(pDev, 0, &credits);
59260 +
59261 +        if (status != A_OK) {
59262 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
59263 +            break;
59264 +        }
59265 +
59266 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
59267 +
59268 +            /* read the first 4 scratch registers */
59269 +        status = HIFReadWrite(pDev->HIFDevice,
59270 +                              SCRATCH_ADDRESS,
59271 +                              params,
59272 +                              4,
59273 +                              HIF_RD_SYNC_BYTE_INC,
59274 +                              NULL);
59275 +
59276 +        if (status != A_OK) {
59277 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
59278 +            break;
59279 +        }
59280 +
59281 +        numBufs = params[0];
59282 +        bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
59283 +
59284 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
59285 +            ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
59286 +            numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
59287 +
59288 +        if ((numBufs * bufferSize) < TOTAL_BYTES) {
59289 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
59290 +                TOTAL_BYTES, (numBufs*bufferSize)));
59291 +            status = A_ERROR;
59292 +            break;
59293 +        }
59294 +
59295 +        temp = GetEndMarker();
59296 +
59297 +        status = HIFReadWrite(pDev->HIFDevice,
59298 +                              SCRATCH_ADDRESS + 4,
59299 +                              (A_UINT8 *)&temp,
59300 +                              2,
59301 +                              HIF_WR_SYNC_BYTE_INC,
59302 +                              NULL);
59303 +
59304 +        if (status != A_OK) {
59305 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
59306 +            break;
59307 +        }
59308 +
59309 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
59310 +
59311 +        temp = (A_UINT16)g_BlockSizes[1];
59312 +            /* convert to a mask */
59313 +        temp = temp - 1;
59314 +        status = HIFReadWrite(pDev->HIFDevice,
59315 +                              SCRATCH_ADDRESS + 6,
59316 +                              (A_UINT8 *)&temp,
59317 +                              2,
59318 +                              HIF_WR_SYNC_BYTE_INC,
59319 +                              NULL);
59320 +
59321 +        if (status != A_OK) {
59322 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
59323 +            break;
59324 +        }
59325 +
59326 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
59327 +
59328 +            /* execute the test on each mailbox */
59329 +        for (i = 0; i < AR6K_MAILBOXES; i++) {
59330 +            status = DoOneMboxHWTest(pDev, i);
59331 +            if (status != A_OK) {
59332 +                break;
59333 +            }
59334 +        }
59335 +
59336 +    } while (FALSE);
59337 +
59338 +    if (status == A_OK) {
59339 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! -  \n"));
59340 +    } else {
59341 +        AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! -  \n"));
59342 +    }
59343 +        /* don't let HTC_Start continue, the target is actually not running any HTC code */
59344 +    return A_ERROR;
59345 +}
59346 +#endif
59347 +
59348 +
59349 +
59350 Index: linux-2.6.28/drivers/ar6000/htc/ar6k_events.c
59351 ===================================================================
59352 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
59353 +++ linux-2.6.28/drivers/ar6000/htc/ar6k_events.c       2009-01-02 00:01:56.000000000 +0100
59354 @@ -0,0 +1,638 @@
59355 +/*
59356 + * AR6K Driver layer event handling (i.e. interrupts, message polling)
59357 + *
59358 + * Copyright (c) 2007 Atheros Communications Inc.
59359 + * All rights reserved.
59360 + *
59361 + *
59362 + *  This program is free software; you can redistribute it and/or modify
59363 + *  it under the terms of the GNU General Public License version 2 as
59364 + *  published by the Free Software Foundation;
59365 + *
59366 + *  Software distributed under the License is distributed on an "AS
59367 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
59368 + *  implied. See the License for the specific language governing
59369 + *  rights and limitations under the License.
59370 + *
59371 + *
59372 + *
59373 + */
59374 +#include "a_config.h"
59375 +#include "athdefs.h"
59376 +#include "a_types.h"
59377 +#include "AR6Khwreg.h"
59378 +#include "a_osapi.h"
59379 +#include "a_debug.h"
59380 +#include "hif.h"
59381 +#include "htc_packet.h"
59382 +#include "ar6k.h"
59383 +
59384 +extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
59385 +extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
59386 +
59387 +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
59388 +
59389 +#define DELAY_PER_INTERVAL_MS 10  /* 10 MS delay per polling interval */
59390 +
59391 +/* completion routine for ALL HIF layer async I/O */
59392 +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
59393 +{
59394 +    HTC_PACKET *pPacket = (HTC_PACKET *)context;
59395 +
59396 +    COMPLETE_HTC_PACKET(pPacket,status);
59397 +
59398 +    return A_OK;
59399 +}
59400 +
59401 +/* mailbox recv message polling */
59402 +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
59403 +                            A_UINT32    *pLookAhead,
59404 +                            int          TimeoutMS)
59405 +{
59406 +    A_STATUS status = A_OK;
59407 +    int      timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
59408 +
59409 +    AR_DEBUG_ASSERT(timeout > 0);
59410 +
59411 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
59412 +
59413 +    while (TRUE) {
59414 +
59415 +        if (pDev->GetPendingEventsFunc != NULL)
59416 +               {
59417 +
59418 +            HIF_PENDING_EVENTS_INFO events;
59419 +
59420 +            /* the HIF layer uses a special mechanism to get events, do this
59421 +             * synchronously */
59422 +            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
59423 +                                            &events,
59424 +                                            NULL);
59425 +            if (A_FAILED(status))
59426 +                       {
59427 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
59428 +                               break;
59429 +            }
59430 +
59431 +            if (events.Events & HIF_RECV_MSG_AVAIL)
59432 +                       {
59433 +                    /*  there is a message available, the lookahead should be valid now */
59434 +                *pLookAhead = events.LookAhead;
59435 +
59436 +                break;
59437 +            }
59438 +        }
59439 +               else
59440 +               {
59441 +
59442 +                /* this is the standard HIF way.... */
59443 +                /* load the register table */
59444 +            status = HIFReadWrite(pDev->HIFDevice,
59445 +                                  HOST_INT_STATUS_ADDRESS,
59446 +                                  (A_UINT8 *)&pDev->IrqProcRegisters,
59447 +                                  AR6K_IRQ_PROC_REGS_SIZE,
59448 +                                  HIF_RD_SYNC_BYTE_INC,
59449 +                                  NULL);
59450 +
59451 +            if (A_FAILED(status))
59452 +                       {
59453 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
59454 +                break;
59455 +            }
59456 +
59457 +                /* check for MBOX data and valid lookahead */
59458 +            if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX))
59459 +                       {
59460 +                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
59461 +                               {
59462 +                    /* mailbox has a message and the look ahead is valid */
59463 +                    *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
59464 +                    break;
59465 +                }
59466 +            }
59467 +
59468 +        }
59469 +
59470 +        timeout--;
59471 +
59472 +        if (timeout <= 0)
59473 +               {
59474 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
59475 +            status = A_ERROR;
59476 +
59477 +                /* check if the target asserted */
59478 +            if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
59479 +                    /* target signaled an assert, process this pending interrupt
59480 +                     * this will call the target failure handler */
59481 +                DevServiceDebugInterrupt(pDev);
59482 +            }
59483 +
59484 +            break;
59485 +        }
59486 +
59487 +            /* delay a little  */
59488 +         A_MDELAY(DELAY_PER_INTERVAL_MS);
59489 +         AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("  Retry Mbox Poll : %d \n",timeout));
59490 +    }
59491 +
59492 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
59493 +
59494 +    return status;
59495 +}
59496 +
59497 +static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
59498 +{
59499 +    A_STATUS status;
59500 +    A_UINT8  cpu_int_status;
59501 +    A_UINT8  regBuffer[4];
59502 +
59503 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
59504 +    cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
59505 +                     pDev->IrqEnableRegisters.cpu_int_status_enable;
59506 +    AR_DEBUG_ASSERT(cpu_int_status);
59507 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59508 +                    ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
59509 +                    cpu_int_status));
59510 +
59511 +        /* Clear the interrupt */
59512 +    pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
59513 +
59514 +        /* set up the register transfer buffer to hit the register 4 times , this is done
59515 +         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
59516 +         * restrict bus transfer lengths to be a multiple of 4-bytes */
59517 +
59518 +        /* set W1C value to clear the interrupt, this hits the register first */
59519 +    regBuffer[0] = cpu_int_status;
59520 +        /* the remaining 4 values are set to zero which have no-effect  */
59521 +    regBuffer[1] = 0;
59522 +    regBuffer[2] = 0;
59523 +    regBuffer[3] = 0;
59524 +
59525 +    status = HIFReadWrite(pDev->HIFDevice,
59526 +                          CPU_INT_STATUS_ADDRESS,
59527 +                          regBuffer,
59528 +                          4,
59529 +                          HIF_WR_SYNC_BYTE_FIX,
59530 +                          NULL);
59531 +
59532 +    AR_DEBUG_ASSERT(status == A_OK);
59533 +    return status;
59534 +}
59535 +
59536 +
59537 +static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
59538 +{
59539 +    A_STATUS status;
59540 +    A_UINT8  error_int_status;
59541 +    A_UINT8  regBuffer[4];
59542 +
59543 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
59544 +    error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
59545 +    AR_DEBUG_ASSERT(error_int_status);
59546 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59547 +                    ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
59548 +                    error_int_status));
59549 +
59550 +    if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
59551 +        /* Wakeup */
59552 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
59553 +    }
59554 +
59555 +    if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
59556 +        /* Rx Underflow */
59557 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
59558 +    }
59559 +
59560 +    if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
59561 +        /* Tx Overflow */
59562 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
59563 +    }
59564 +
59565 +        /* Clear the interrupt */
59566 +    pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
59567 +
59568 +        /* set up the register transfer buffer to hit the register 4 times , this is done
59569 +         * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
59570 +         * restrict bus transfer lengths to be a multiple of 4-bytes */
59571 +
59572 +        /* set W1C value to clear the interrupt, this hits the register first */
59573 +    regBuffer[0] = error_int_status;
59574 +        /* the remaining 4 values are set to zero which have no-effect  */
59575 +    regBuffer[1] = 0;
59576 +    regBuffer[2] = 0;
59577 +    regBuffer[3] = 0;
59578 +
59579 +    status = HIFReadWrite(pDev->HIFDevice,
59580 +                          ERROR_INT_STATUS_ADDRESS,
59581 +                          regBuffer,
59582 +                          4,
59583 +                          HIF_WR_SYNC_BYTE_FIX,
59584 +                          NULL);
59585 +
59586 +    AR_DEBUG_ASSERT(status == A_OK);
59587 +    return status;
59588 +}
59589 +
59590 +static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
59591 +{
59592 +    A_UINT32 dummy;
59593 +    A_STATUS status;
59594 +
59595 +    /* Send a target failure event to the application */
59596 +    AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
59597 +
59598 +    if (pDev->TargetFailureCallback != NULL) {
59599 +        pDev->TargetFailureCallback(pDev->HTCContext);
59600 +    }
59601 +
59602 +    /* clear the interrupt , the debug error interrupt is
59603 +     * counter 0 */
59604 +        /* read counter to clear interrupt */
59605 +    status = HIFReadWrite(pDev->HIFDevice,
59606 +                          COUNT_DEC_ADDRESS,
59607 +                          (A_UINT8 *)&dummy,
59608 +                          4,
59609 +                          HIF_RD_SYNC_BYTE_INC,
59610 +                          NULL);
59611 +
59612 +    AR_DEBUG_ASSERT(status == A_OK);
59613 +    return status;
59614 +}
59615 +
59616 +static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
59617 +{
59618 +    A_UINT8 counter_int_status;
59619 +
59620 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
59621 +
59622 +    counter_int_status = pDev->IrqProcRegisters.counter_int_status &
59623 +                         pDev->IrqEnableRegisters.counter_int_status_enable;
59624 +
59625 +    AR_DEBUG_ASSERT(counter_int_status);
59626 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59627 +                    ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
59628 +                    counter_int_status));
59629 +
59630 +    /* Check if the debug interrupt is pending */
59631 +    if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
59632 +        return DevServiceDebugInterrupt(pDev);
59633 +    }
59634 +
59635 +    return A_OK;
59636 +}
59637 +
59638 +/* callback when our fetch to get interrupt status registers completes */
59639 +static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
59640 +{
59641 +    AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
59642 +    A_UINT32    lookAhead = 0;
59643 +    A_BOOL      otherInts = FALSE;
59644 +
59645 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
59646 +
59647 +    do {
59648 +
59649 +        if (A_FAILED(pPacket->Status)) {
59650 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
59651 +                    (" GetEvents I/O request failed, status:%d \n", pPacket->Status));
59652 +            /* bail out, don't unmask HIF interrupt */
59653 +            break;
59654 +        }
59655 +
59656 +        if (pDev->GetPendingEventsFunc != NULL) {
59657 +                /* the HIF layer collected the information for us */
59658 +            HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
59659 +            if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
59660 +                lookAhead = pEvents->LookAhead;
59661 +                if (0 == lookAhead) {
59662 +                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
59663 +                }
59664 +            }
59665 +            if (pEvents->Events & HIF_OTHER_EVENTS) {
59666 +                otherInts = TRUE;
59667 +            }
59668 +        } else {
59669 +                /* standard interrupt table handling.... */
59670 +            AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
59671 +            A_UINT8                 host_int_status;
59672 +
59673 +            host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
59674 +
59675 +            if (host_int_status & (1 << HTC_MAILBOX)) {
59676 +                host_int_status &= ~(1 << HTC_MAILBOX);
59677 +                if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
59678 +                        /* mailbox has a message and the look ahead is valid */
59679 +                    lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
59680 +                    if (0 == lookAhead) {
59681 +                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
59682 +                    }
59683 +                }
59684 +            }
59685 +
59686 +            if (host_int_status) {
59687 +                    /* there are other interrupts to handle */
59688 +                otherInts = TRUE;
59689 +            }
59690 +        }
59691 +
59692 +        if (otherInts || (lookAhead == 0)) {
59693 +            /* if there are other interrupts to process, we cannot do this in the async handler so
59694 +             * ack the interrupt which will cause our sync handler to run again
59695 +             * if however there are no more messages, we can now ack the interrupt  */
59696 +            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59697 +                (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
59698 +                otherInts, lookAhead));
59699 +            HIFAckInterrupt(pDev->HIFDevice);
59700 +        } else {
59701 +            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59702 +                    (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
59703 +                    lookAhead));
59704 +                /* lookahead is non-zero and there are no other interrupts to service,
59705 +                 * go get the next message */
59706 +            pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, NULL);
59707 +        }
59708 +
59709 +    } while (FALSE);
59710 +
59711 +        /* free this IO packet */
59712 +    AR6KFreeIOPacket(pDev,pPacket);
59713 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
59714 +}
59715 +
59716 +/* called by the HTC layer when it wants us to check if the device has any more pending
59717 + * recv messages, this starts off a series of async requests to read interrupt registers  */
59718 +A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
59719 +{
59720 +    AR6K_DEVICE  *pDev = (AR6K_DEVICE *)context;
59721 +    A_STATUS      status = A_OK;
59722 +    HTC_PACKET   *pIOPacket;
59723 +
59724 +    /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
59725 +     * cause us to switch contexts */
59726 +
59727 +   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev));
59728 +
59729 +   do {
59730 +
59731 +        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
59732 +                /* break the async processing chain right here, no need to continue.
59733 +                 * The DevDsrHandler() will handle things in a loop when things are driven
59734 +                 * synchronously  */
59735 +            break;
59736 +        }
59737 +            /* first allocate one of our HTC packets we created for async I/O
59738 +             * we reuse HTC packet definitions so that we can use the completion mechanism
59739 +             * in DevRWCompletionHandler() */
59740 +        pIOPacket = AR6KAllocIOPacket(pDev);
59741 +
59742 +        if (NULL == pIOPacket) {
59743 +                /* there should be only 1 asynchronous request out at a time to read these registers
59744 +                 * so this should actually never happen */
59745 +            status = A_NO_MEMORY;
59746 +            AR_DEBUG_ASSERT(FALSE);
59747 +            break;
59748 +        }
59749 +
59750 +            /* stick in our completion routine when the I/O operation completes */
59751 +        pIOPacket->Completion = DevGetEventAsyncHandler;
59752 +        pIOPacket->pContext = pDev;
59753 +
59754 +        if (pDev->GetPendingEventsFunc) {
59755 +                /* HIF layer has it's own mechanism, pass the IO to it.. */
59756 +            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
59757 +                                                (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
59758 +                                                pIOPacket);
59759 +
59760 +        } else {
59761 +                /* standard way, read the interrupt register table asynchronously again */
59762 +            status = HIFReadWrite(pDev->HIFDevice,
59763 +                                  HOST_INT_STATUS_ADDRESS,
59764 +                                  pIOPacket->pBuffer,
59765 +                                  AR6K_IRQ_PROC_REGS_SIZE,
59766 +                                  HIF_RD_ASYNC_BYTE_INC,
59767 +                                  pIOPacket);
59768 +        }
59769 +
59770 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
59771 +   } while (FALSE);
59772 +
59773 +   AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
59774 +
59775 +   return status;
59776 +}
59777 +
59778 +/* process pending interrupts synchronously */
59779 +static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
59780 +{
59781 +    A_STATUS    status = A_OK;
59782 +    A_UINT8     host_int_status = 0;
59783 +    A_UINT32    lookAhead = 0;
59784 +
59785 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev));
59786 +
59787 +    /*** NOTE: the HIF implementation guarantees that the context of this call allows
59788 +     *         us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
59789 +     *         can block or switch thread/task ontexts.
59790 +     *         This is a fully schedulable context.
59791 +     * */
59792 +    do {
59793 +
59794 +        if (pDev->GetPendingEventsFunc != NULL) {
59795 +            HIF_PENDING_EVENTS_INFO events;
59796 +
59797 +                /* the HIF layer uses a special mechanism to get events
59798 +                 * get this synchronously  */
59799 +            status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
59800 +                                                &events,
59801 +                                                NULL);
59802 +
59803 +            if (A_FAILED(status)) {
59804 +                break;
59805 +            }
59806 +
59807 +            if (events.Events & HIF_RECV_MSG_AVAIL) {
59808 +                lookAhead = events.LookAhead;
59809 +                if (0 == lookAhead) {
59810 +                    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
59811 +                }
59812 +            }
59813 +
59814 +            if (!(events.Events & HIF_OTHER_EVENTS) ||
59815 +                !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
59816 +                    /* no need to read the register table, no other interesting interrupts.
59817 +                     * Some interfaces (like SPI) can shadow interrupt sources without
59818 +                     * requiring the host to do a full table read */
59819 +                break;
59820 +            }
59821 +
59822 +            /* otherwise fall through and read the register table */
59823 +        }
59824 +
59825 +        /*
59826 +         * Read the first 28 bytes of the HTC register table. This will yield us
59827 +         * the value of different int status registers and the lookahead
59828 +         * registers.
59829 +         *    length = sizeof(int_status) + sizeof(cpu_int_status) +
59830 +         *             sizeof(error_int_status) + sizeof(counter_int_status) +
59831 +         *             sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
59832 +         *             sizeof(hole) +  sizeof(rx_lookahead) +
59833 +         *             sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
59834 +         *             sizeof(error_status_enable) +
59835 +         *             sizeof(counter_int_status_enable);
59836 +         *
59837 +        */
59838 +        status = HIFReadWrite(pDev->HIFDevice,
59839 +                              HOST_INT_STATUS_ADDRESS,
59840 +                              (A_UINT8 *)&pDev->IrqProcRegisters,
59841 +                              AR6K_IRQ_PROC_REGS_SIZE,
59842 +                              HIF_RD_SYNC_BYTE_INC,
59843 +                              NULL);
59844 +
59845 +        if (A_FAILED(status)) {
59846 +            break;
59847 +        }
59848 +
59849 +        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
59850 +            DevDumpRegisters(&pDev->IrqProcRegisters,
59851 +                             &pDev->IrqEnableRegisters);
59852 +        }
59853 +
59854 +            /* Update only those registers that are enabled */
59855 +        host_int_status = pDev->IrqProcRegisters.host_int_status &
59856 +                          pDev->IrqEnableRegisters.int_status_enable;
59857 +
59858 +        if (NULL == pDev->GetPendingEventsFunc) {
59859 +                /* only look at mailbox status if the HIF layer did not provide this function,
59860 +                 * on some HIF interfaces reading the RX lookahead is not valid to do */
59861 +            if (host_int_status & (1 << HTC_MAILBOX)) {
59862 +                    /* mask out pending mailbox value, we use "lookAhead" as the real flag for
59863 +                     * mailbox processing below */
59864 +                host_int_status &= ~(1 << HTC_MAILBOX);
59865 +                if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
59866 +                        /* mailbox has a message and the look ahead is valid */
59867 +                    lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
59868 +                    if (0 == lookAhead) {
59869 +                        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
59870 +                    }
59871 +                }
59872 +            }
59873 +        } else {
59874 +                /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
59875 +            host_int_status &= ~(1 << HTC_MAILBOX);
59876 +        }
59877 +
59878 +    } while (FALSE);
59879 +
59880 +
59881 +    do {
59882 +
59883 +            /* did the interrupt status fetches succeed? */
59884 +        if (A_FAILED(status)) {
59885 +            break;
59886 +        }
59887 +
59888 +        if ((0 == host_int_status) && (0 == lookAhead)) {
59889 +                /* nothing to process, the caller can use this to break out of a loop */
59890 +            *pDone = TRUE;
59891 +            break;
59892 +        }
59893 +
59894 +        if (lookAhead != 0) {
59895 +            AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
59896 +                /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
59897 +                 * mailbox...
59898 +                 * When emptying the recv mailbox we use the async handler above called from the
59899 +                 * completion routine of the callers read request. This can improve performance
59900 +                 * by reducing context switching when we rapidly pull packets */
59901 +            status = pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, pASyncProcessing);
59902 +            if (A_FAILED(status)) {
59903 +                break;
59904 +            }
59905 +        }
59906 +
59907 +            /* now handle the rest of them */
59908 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
59909 +                            (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
59910 +                            host_int_status));
59911 +
59912 +        if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
59913 +                /* CPU Interrupt */
59914 +            status = DevServiceCPUInterrupt(pDev);
59915 +            if (A_FAILED(status)){
59916 +                break;
59917 +            }
59918 +        }
59919 +
59920 +        if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
59921 +                /* Error Interrupt */
59922 +            status = DevServiceErrorInterrupt(pDev);
59923 +            if (A_FAILED(status)){
59924 +                break;
59925 +            }
59926 +        }
59927 +
59928 +        if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
59929 +                /* Counter Interrupt */
59930 +            status = DevServiceCounterInterrupt(pDev);
59931 +            if (A_FAILED(status)){
59932 +                break;
59933 +            }
59934 +        }
59935 +
59936 +    } while (FALSE);
59937 +
59938 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
59939 +                *pDone, *pASyncProcessing, status));
59940 +
59941 +    return status;
59942 +}
59943 +
59944 +
59945 +/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
59946 +A_STATUS DevDsrHandler(void *context)
59947 +{
59948 +    AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
59949 +    A_STATUS    status = A_OK;
59950 +    A_BOOL      done = FALSE;
59951 +    A_BOOL      asyncProc = FALSE;
59952 +
59953 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
59954 +
59955 +
59956 +    while (!done) {
59957 +        status = ProcessPendingIRQs(pDev, &done, &asyncProc);
59958 +        if (A_FAILED(status)) {
59959 +            break;
59960 +        }
59961 +
59962 +        if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
59963 +            /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
59964 +            asyncProc = FALSE;
59965 +            /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
59966 +             * this has a nice side effect of blocking us until all async read requests are completed.
59967 +             * This behavior is required on some HIF implementations that do not allow ASYNC
59968 +             * processing in interrupt handlers (like Windows CE) */
59969 +        }
59970 +
59971 +        if (asyncProc) {
59972 +                /* the function performed some async I/O for performance, we
59973 +                   need to exit the ISR immediately, the check below will prevent the interrupt from being
59974 +                   Ack'd while we handle it asynchronously */
59975 +            break;
59976 +        }
59977 +
59978 +    }
59979 +
59980 +    if (A_SUCCESS(status) && !asyncProc) {
59981 +            /* Ack the interrupt only if :
59982 +             *  1. we did not get any errors in processing interrupts
59983 +             *  2. there are no outstanding async processing requests */
59984 +        AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
59985 +        HIFAckInterrupt(pDev->HIFDevice);
59986 +    }
59987 +
59988 +    AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
59989 +    return A_OK;
59990 +}
59991 +
59992 +
59993 Index: linux-2.6.28/drivers/ar6000/htc/ar6k.h
59994 ===================================================================
59995 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
59996 +++ linux-2.6.28/drivers/ar6000/htc/ar6k.h      2009-01-02 00:01:56.000000000 +0100
59997 @@ -0,0 +1,191 @@
59998 +/*
59999 + *
60000 + * Copyright (c) 2007 Atheros Communications Inc.
60001 + * All rights reserved.
60002 + *
60003 + *
60004 + *  This program is free software; you can redistribute it and/or modify
60005 + *  it under the terms of the GNU General Public License version 2 as
60006 + *  published by the Free Software Foundation;
60007 + *
60008 + *  Software distributed under the License is distributed on an "AS
60009 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60010 + *  implied. See the License for the specific language governing
60011 + *  rights and limitations under the License.
60012 + *
60013 + *
60014 + *
60015 + */
60016 +
60017 +#ifndef AR6K_H_
60018 +#define AR6K_H_
60019 +
60020 +#define AR6K_MAILBOXES 4
60021 +
60022 +/* HTC runs over mailbox 0 */
60023 +#define HTC_MAILBOX          0
60024 +
60025 +#define AR6K_TARGET_DEBUG_INTR_MASK     0x01
60026 +
60027 +#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK |   \
60028 +                            INT_STATUS_ENABLE_CPU_MASK   |   \
60029 +                            INT_STATUS_ENABLE_COUNTER_MASK)
60030 +
60031 +//#define MBOXHW_UNIT_TEST 1
60032 +
60033 +#include "athstartpack.h"
60034 +typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
60035 +    A_UINT8                      host_int_status;
60036 +    A_UINT8                      cpu_int_status;
60037 +    A_UINT8                      error_int_status;
60038 +    A_UINT8                      counter_int_status;
60039 +    A_UINT8                      mbox_frame;
60040 +    A_UINT8                      rx_lookahead_valid;
60041 +    A_UINT8                      hole[2];
60042 +    A_UINT32                     rx_lookahead[2];
60043 +} POSTPACK AR6K_IRQ_PROC_REGISTERS;
60044 +
60045 +#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
60046 +
60047 +
60048 +
60049 +typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
60050 +    A_UINT8                      int_status_enable;
60051 +    A_UINT8                      cpu_int_status_enable;
60052 +    A_UINT8                      error_status_enable;
60053 +    A_UINT8                      counter_int_status_enable;
60054 +} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
60055 +
60056 +#include "athendpack.h"
60057 +
60058 +#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
60059 +
60060 +#define AR6K_REG_IO_BUFFER_SIZE     32
60061 +#define AR6K_MAX_REG_IO_BUFFERS     8
60062 +
60063 +/* buffers for ASYNC I/O */
60064 +typedef struct AR6K_ASYNC_REG_IO_BUFFER {
60065 +    HTC_PACKET    HtcPacket;   /* we use an HTC packet as a wrapper for our async register-based I/O */
60066 +    A_UINT8       Buffer[AR6K_REG_IO_BUFFER_SIZE];
60067 +} AR6K_ASYNC_REG_IO_BUFFER;
60068 +
60069 +typedef struct _AR6K_DEVICE {
60070 +    A_MUTEX_T                   Lock;
60071 +    AR6K_IRQ_PROC_REGISTERS     IrqProcRegisters;
60072 +    AR6K_IRQ_ENABLE_REGISTERS   IrqEnableRegisters;
60073 +    void                        *HIFDevice;
60074 +    A_UINT32                    BlockSize;
60075 +    A_UINT32                    BlockMask;
60076 +    A_UINT32                    MailboxAddress;
60077 +    HIF_PENDING_EVENTS_FUNC     GetPendingEventsFunc;
60078 +    void                        *HTCContext;
60079 +    HTC_PACKET_QUEUE            RegisterIOList;
60080 +    AR6K_ASYNC_REG_IO_BUFFER    RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
60081 +    void                        (*TargetFailureCallback)(void *Context);
60082 +    A_STATUS                    (*MessagePendingCallback)(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc);
60083 +    HIF_DEVICE_IRQ_PROCESSING_MODE  HifIRQProcessingMode;
60084 +    HIF_MASK_UNMASK_RECV_EVENT      HifMaskUmaskRecvEvent;
60085 +} AR6K_DEVICE;
60086 +
60087 +#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
60088 +
60089 +A_STATUS DevSetup(AR6K_DEVICE *pDev);
60090 +A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
60091 +A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
60092 +A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
60093 +                            A_UINT32    *pLookAhead,
60094 +                            int          TimeoutMS);
60095 +A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
60096 +A_STATUS DevDsrHandler(void *context);
60097 +A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
60098 +void     DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS   *pIrqProcRegs,
60099 +                          AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
60100 +
60101 +#define DEV_STOP_RECV_ASYNC TRUE
60102 +#define DEV_STOP_RECV_SYNC  FALSE
60103 +#define DEV_ENABLE_RECV_ASYNC TRUE
60104 +#define DEV_ENABLE_RECV_SYNC  FALSE
60105 +A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
60106 +A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
60107 +
60108 +static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
60109 +    A_UINT32 paddedLength;
60110 +    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
60111 +    A_STATUS status;
60112 +
60113 +       /* adjust the length to be a multiple of block size if appropriate */
60114 +    paddedLength = (SendLength + (pDev->BlockMask)) &
60115 +                    (~(pDev->BlockMask));
60116 +#if 0 // BufferLength may not be set in , fix this...
60117 +    if (paddedLength > pPacket->BufferLength) {
60118 +        AR_DEBUG_ASSERT(FALSE);
60119 +        if (pPacket->Completion != NULL) {
60120 +            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
60121 +        }
60122 +        return A_EINVAL;
60123 +    }
60124 +#endif
60125 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
60126 +                ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
60127 +                paddedLength,
60128 +                pDev->MailboxAddress,
60129 +                sync ? "SYNC" : "ASYNC"));
60130 +
60131 +    status = HIFReadWrite(pDev->HIFDevice,
60132 +                          pDev->MailboxAddress,
60133 +                          pPacket->pBuffer,
60134 +                          paddedLength,     /* the padded length */
60135 +                          sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
60136 +                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
60137 +
60138 +    if (sync) {
60139 +        pPacket->Status = status;
60140 +    }
60141 +
60142 +    return status;
60143 +}
60144 +
60145 +static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
60146 +    A_UINT32 paddedLength;
60147 +    A_STATUS status;
60148 +    A_BOOL   sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
60149 +
60150 +        /* adjust the length to be a multiple of block size if appropriate */
60151 +    paddedLength = (RecvLength + (pDev->BlockMask)) &
60152 +                    (~(pDev->BlockMask));
60153 +    if (paddedLength > pPacket->BufferLength) {
60154 +        AR_DEBUG_ASSERT(FALSE);
60155 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
60156 +                ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
60157 +                    paddedLength,RecvLength,pPacket->BufferLength));
60158 +        if (pPacket->Completion != NULL) {
60159 +            COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
60160 +        }
60161 +        return A_EINVAL;
60162 +    }
60163 +
60164 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
60165 +                ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
60166 +                paddedLength,
60167 +                pDev->MailboxAddress,
60168 +                sync ? "SYNC" : "ASYNC"));
60169 +
60170 +    status = HIFReadWrite(pDev->HIFDevice,
60171 +                          pDev->MailboxAddress,
60172 +                          pPacket->pBuffer,
60173 +                          paddedLength,
60174 +                          sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC,
60175 +                          sync ? NULL : pPacket);  /* pass the packet as the context to the HIF request */
60176 +
60177 +    if (sync) {
60178 +        pPacket->Status = status;
60179 +    }
60180 +
60181 +    return status;
60182 +}
60183 +
60184 +#ifdef MBOXHW_UNIT_TEST
60185 +A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
60186 +#endif
60187 +
60188 +#endif /*AR6K_H_*/
60189 Index: linux-2.6.28/drivers/ar6000/htc/htc.c
60190 ===================================================================
60191 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
60192 +++ linux-2.6.28/drivers/ar6000/htc/htc.c       2009-01-02 00:01:56.000000000 +0100
60193 @@ -0,0 +1,507 @@
60194 +/*
60195 + *
60196 + * Copyright (c) 2007 Atheros Communications Inc.
60197 + * All rights reserved.
60198 + *
60199 + *
60200 + *  This program is free software; you can redistribute it and/or modify
60201 + *  it under the terms of the GNU General Public License version 2 as
60202 + *  published by the Free Software Foundation;
60203 + *
60204 + *  Software distributed under the License is distributed on an "AS
60205 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60206 + *  implied. See the License for the specific language governing
60207 + *  rights and limitations under the License.
60208 + *
60209 + *
60210 + *
60211 + */
60212 +
60213 +#include "htc_internal.h"
60214 +
60215 +
60216 +static HTC_INIT_INFO  HTCInitInfo = {NULL,NULL,NULL};
60217 +static A_BOOL         HTCInitialized = FALSE;
60218 +
60219 +static A_STATUS HTCTargetInsertedHandler(void *hif_handle);
60220 +static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status);
60221 +static void HTCReportFailure(void *Context);
60222 +
60223 +/* Initializes the HTC layer */
60224 +A_STATUS HTCInit(HTC_INIT_INFO *pInitInfo)
60225 +{
60226 +    HTC_CALLBACKS htcCallbacks;
60227 +
60228 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Enter\n"));
60229 +    if (HTCInitialized) {
60230 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
60231 +        return A_OK;
60232 +    }
60233 +
60234 +    A_MEMCPY(&HTCInitInfo,pInitInfo,sizeof(HTC_INIT_INFO));
60235 +
60236 +    A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
60237 +
60238 +        /* setup HIF layer callbacks */
60239 +    htcCallbacks.deviceInsertedHandler = HTCTargetInsertedHandler;
60240 +    htcCallbacks.deviceRemovedHandler = HTCTargetRemovedHandler;
60241 +        /* the device layer handles these */
60242 +    htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
60243 +    htcCallbacks.dsrHandler = DevDsrHandler;
60244 +    HIFInit(&htcCallbacks);
60245 +    HTCInitialized = TRUE;
60246 +
60247 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
60248 +    return A_OK;
60249 +}
60250 +
60251 +void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList)
60252 +{
60253 +    LOCK_HTC(target);
60254 +    HTC_PACKET_ENQUEUE(pList,pPacket);
60255 +    UNLOCK_HTC(target);
60256 +}
60257 +
60258 +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target,  HTC_PACKET_QUEUE *pList)
60259 +{
60260 +    HTC_PACKET *pPacket;
60261 +
60262 +    LOCK_HTC(target);
60263 +    pPacket = HTC_PACKET_DEQUEUE(pList);
60264 +    UNLOCK_HTC(target);
60265 +
60266 +    return pPacket;
60267 +}
60268 +
60269 +/* cleanup the HTC instance */
60270 +static void HTCCleanup(HTC_TARGET *target)
60271 +{
60272 +    if (A_IS_MUTEX_VALID(&target->HTCLock)) {
60273 +        A_MUTEX_DELETE(&target->HTCLock);
60274 +    }
60275 +
60276 +    if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
60277 +        A_MUTEX_DELETE(&target->HTCRxLock);
60278 +    }
60279 +
60280 +    if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
60281 +        A_MUTEX_DELETE(&target->HTCTxLock);
60282 +    }
60283 +        /* free our instance */
60284 +    A_FREE(target);
60285 +}
60286 +
60287 +/* registered target arrival callback from the HIF layer */
60288 +static A_STATUS HTCTargetInsertedHandler(void *hif_handle)
60289 +{
60290 +    HTC_TARGET              *target = NULL;
60291 +    A_STATUS                 status;
60292 +    int                      i;
60293 +
60294 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Enter\n"));
60295 +
60296 +    do {
60297 +
60298 +            /* allocate target memory */
60299 +        if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
60300 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
60301 +            status = A_ERROR;
60302 +            break;
60303 +        }
60304 +
60305 +        A_MEMZERO(target, sizeof(HTC_TARGET));
60306 +        A_MUTEX_INIT(&target->HTCLock);
60307 +        A_MUTEX_INIT(&target->HTCRxLock);
60308 +        A_MUTEX_INIT(&target->HTCTxLock);
60309 +        INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
60310 +        INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
60311 +
60312 +            /* give device layer the hif device handle */
60313 +        target->Device.HIFDevice = hif_handle;
60314 +            /* give the device layer our context (for event processing)
60315 +             * the device layer will register it's own context with HIF
60316 +             * so we need to set this so we can fetch it in the target remove handler */
60317 +        target->Device.HTCContext = target;
60318 +            /* set device layer target failure callback */
60319 +        target->Device.TargetFailureCallback = HTCReportFailure;
60320 +            /* set device layer recv message pending callback */
60321 +        target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
60322 +        target->EpWaitingForBuffers = ENDPOINT_MAX;
60323 +
60324 +            /* setup device layer */
60325 +        status = DevSetup(&target->Device);
60326 +
60327 +        if (A_FAILED(status)) {
60328 +            break;
60329 +        }
60330 +
60331 +            /* carve up buffers/packets for control messages */
60332 +        for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
60333 +            HTC_PACKET *pControlPacket;
60334 +            pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
60335 +            SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
60336 +                                          target,
60337 +                                          target->HTCControlBuffers[i].Buffer,
60338 +                                          HTC_CONTROL_BUFFER_SIZE,
60339 +                                          ENDPOINT_0);
60340 +            HTC_FREE_CONTROL_RX(target,pControlPacket);
60341 +        }
60342 +
60343 +        for (;i < NUM_CONTROL_BUFFERS;i++) {
60344 +             HTC_PACKET *pControlPacket;
60345 +             pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
60346 +             INIT_HTC_PACKET_INFO(pControlPacket,
60347 +                                  target->HTCControlBuffers[i].Buffer,
60348 +                                  HTC_CONTROL_BUFFER_SIZE);
60349 +             HTC_FREE_CONTROL_TX(target,pControlPacket);
60350 +        }
60351 +
60352 +    } while (FALSE);
60353 +
60354 +    if (A_SUCCESS(status)) {
60355 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" calling AddInstance callback \n"));
60356 +            /* announce ourselves */
60357 +        HTCInitInfo.AddInstance((HTC_HANDLE)target);
60358 +    } else {
60359 +        if (target != NULL) {
60360 +            HTCCleanup(target);
60361 +        }
60362 +    }
60363 +
60364 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Exit\n"));
60365 +
60366 +    return status;
60367 +}
60368 +
60369 +/* registered removal callback from the HIF layer */
60370 +static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status)
60371 +{
60372 +    HTC_TARGET *target;
60373 +
60374 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCTargetRemovedHandler handle:0x%X \n",(A_UINT32)handle));
60375 +
60376 +    if (NULL == handle) {
60377 +            /* this could be NULL in the event that target initialization failed */
60378 +        return A_OK;
60379 +    }
60380 +
60381 +    target = ((AR6K_DEVICE *)handle)->HTCContext;
60382 +
60383 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("   removing target:0x%X instance:0x%X ... \n",
60384 +            (A_UINT32)target, (A_UINT32)target->pInstanceContext));
60385 +
60386 +    if (target->pInstanceContext != NULL) {
60387 +            /* let upper layer know, it needs to call HTCStop() */
60388 +        HTCInitInfo.DeleteInstance(target->pInstanceContext);
60389 +    }
60390 +
60391 +    HIFShutDownDevice(target->Device.HIFDevice);
60392 +
60393 +    HTCCleanup(target);
60394 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCTargetRemovedHandler \n"));
60395 +    return A_OK;
60396 +}
60397 +
60398 +/* get the low level HIF device for the caller , the caller may wish to do low level
60399 + * HIF requests */
60400 +void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
60401 +{
60402 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60403 +    return target->Device.HIFDevice;
60404 +}
60405 +
60406 +/* set the instance block for this HTC handle, so that on removal, the blob can be
60407 + * returned to the caller */
60408 +void HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance)
60409 +{
60410 +    HTC_TARGET  *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60411 +
60412 +    target->pInstanceContext = Instance;
60413 +}
60414 +
60415 +/* wait for the target to arrive (sends HTC Ready message)
60416 + * this operation is fully synchronous and the message is polled for */
60417 +A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle)
60418 +{
60419 +    HTC_TARGET              *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60420 +    A_STATUS                 status;
60421 +    HTC_PACKET              *pPacket = NULL;
60422 +    HTC_READY_MSG           *pRdyMsg;
60423 +    HTC_SERVICE_CONNECT_REQ  connect;
60424 +    HTC_SERVICE_CONNECT_RESP resp;
60425 +
60426 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target));
60427 +
60428 +    do {
60429 +
60430 +#ifdef MBOXHW_UNIT_TEST
60431 +
60432 +        status = DoMboxHWTest(&target->Device);
60433 +
60434 +        if (status != A_OK) {
60435 +            break;
60436 +        }
60437 +
60438 +#endif
60439 +
60440 +            /* we should be getting 1 control message that the target is ready */
60441 +        status = HTCWaitforControlMessage(target, &pPacket);
60442 +
60443 +        if (A_FAILED(status)) {
60444 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
60445 +            break;
60446 +        }
60447 +
60448 +            /* we controlled the buffer creation so it has to be properly aligned */
60449 +        pRdyMsg = (HTC_READY_MSG *)pPacket->pBuffer;
60450 +
60451 +        if ((pRdyMsg->MessageID != HTC_MSG_READY_ID) ||
60452 +            (pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
60453 +                /* this message is not valid */
60454 +            AR_DEBUG_ASSERT(FALSE);
60455 +            status = A_EPROTO;
60456 +            break;
60457 +        }
60458 +
60459 +        if (pRdyMsg->CreditCount == 0 || pRdyMsg->CreditSize == 0) {
60460 +              /* this message is not valid */
60461 +            AR_DEBUG_ASSERT(FALSE);
60462 +            status = A_EPROTO;
60463 +            break;
60464 +        }
60465 +
60466 +        target->TargetCredits = pRdyMsg->CreditCount;
60467 +        target->TargetCreditSize = pRdyMsg->CreditSize;
60468 +
60469 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Target Ready: credits: %d credit size: %d\n",
60470 +                target->TargetCredits, target->TargetCreditSize));
60471 +
60472 +            /* setup our pseudo HTC control endpoint connection */
60473 +        A_MEMZERO(&connect,sizeof(connect));
60474 +        A_MEMZERO(&resp,sizeof(resp));
60475 +        connect.EpCallbacks.pContext = target;
60476 +        connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
60477 +        connect.EpCallbacks.EpRecv = HTCControlRecv;
60478 +        connect.EpCallbacks.EpRecvRefill = NULL;  /* not needed */
60479 +        connect.EpCallbacks.EpSendFull = NULL;    /* not nedded */
60480 +        connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
60481 +        connect.ServiceID = HTC_CTRL_RSVD_SVC;
60482 +
60483 +            /* connect fake service */
60484 +        status = HTCConnectService((HTC_HANDLE)target,
60485 +                                   &connect,
60486 +                                   &resp);
60487 +
60488 +        if (!A_FAILED(status)) {
60489 +            break;
60490 +        }
60491 +
60492 +    } while (FALSE);
60493 +
60494 +    if (pPacket != NULL) {
60495 +        HTC_FREE_CONTROL_RX(target,pPacket);
60496 +    }
60497 +
60498 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
60499 +
60500 +    return status;
60501 +}
60502 +
60503 +
60504 +
60505 +/* Start HTC, enable interrupts and let the target know host has finished setup */
60506 +A_STATUS HTCStart(HTC_HANDLE HTCHandle)
60507 +{
60508 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60509 +    HTC_PACKET *pPacket;
60510 +    A_STATUS   status;
60511 +
60512 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
60513 +
60514 +        /* now that we are starting, push control receive buffers into the
60515 +         * HTC control endpoint */
60516 +
60517 +    while (1) {
60518 +        pPacket = HTC_ALLOC_CONTROL_RX(target);
60519 +        if (NULL == pPacket) {
60520 +            break;
60521 +        }
60522 +        HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
60523 +    }
60524 +
60525 +    do {
60526 +
60527 +        AR_DEBUG_ASSERT(target->InitCredits != NULL);
60528 +        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
60529 +        AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
60530 +
60531 +            /* call init credits callback to do the distribution ,
60532 +             * NOTE: the first entry in the distribution list is ENDPOINT_0, so
60533 +             * we pass the start of the list after this one. */
60534 +        target->InitCredits(target->pCredDistContext,
60535 +                            target->EpCreditDistributionListHead->pNext,
60536 +                            target->TargetCredits);
60537 +
60538 +        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
60539 +            DumpCreditDistStates(target);
60540 +        }
60541 +
60542 +            /* the caller is done connecting to services, so we can indicate to the
60543 +            * target that the setup phase is complete */
60544 +        status = HTCSendSetupComplete(target);
60545 +
60546 +        if (A_FAILED(status)) {
60547 +            break;
60548 +        }
60549 +
60550 +            /* unmask interrupts */
60551 +        status = DevUnmaskInterrupts(&target->Device);
60552 +
60553 +        if (A_FAILED(status)) {
60554 +            HTCStop(target);
60555 +        }
60556 +
60557 +    } while (FALSE);
60558 +
60559 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
60560 +    return status;
60561 +}
60562 +
60563 +
60564 +/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
60565 +void HTCStop(HTC_HANDLE HTCHandle)
60566 +{
60567 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60568 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
60569 +
60570 +        /* mark that we are shutting down .. */
60571 +    target->HTCStateFlags |= HTC_STATE_STOPPING;
60572 +
60573 +        /* Masking interrupts is a synchronous operation, when this function returns
60574 +         * all pending HIF I/O has completed, we can safely flush the queues */
60575 +    DevMaskInterrupts(&target->Device);
60576 +
60577 +        /* flush all send packets */
60578 +    HTCFlushSendPkts(target);
60579 +        /* flush all recv buffers */
60580 +    HTCFlushRecvBuffers(target);
60581 +
60582 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
60583 +}
60584 +
60585 +/* undo what was done in HTCInit() */
60586 +void HTCShutDown(void)
60587 +{
60588 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCShutDown: \n"));
60589 +    HTCInitialized = FALSE;
60590 +        /* undo HTCInit */
60591 +    HIFShutDownDevice(NULL);
60592 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCShutDown: \n"));
60593 +}
60594 +
60595 +void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
60596 +{
60597 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60598 +
60599 +    LOCK_HTC_TX(target);
60600 +
60601 +    DumpCreditDistStates(target);
60602 +
60603 +    UNLOCK_HTC_TX(target);
60604 +}
60605 +
60606 +/* report a target failure from the device, this is a callback from the device layer
60607 + * which uses a mechanism to report errors from the target (i.e. special interrupts) */
60608 +static void HTCReportFailure(void *Context)
60609 +{
60610 +    HTC_TARGET *target = (HTC_TARGET *)Context;
60611 +
60612 +    target->TargetFailure = TRUE;
60613 +
60614 +    if ((target->pInstanceContext != NULL) && (HTCInitInfo.TargetFailure != NULL)) {
60615 +            /* let upper layer know, it needs to call HTCStop() */
60616 +        HTCInitInfo.TargetFailure(target->pInstanceContext, A_ERROR);
60617 +    }
60618 +}
60619 +
60620 +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
60621 +{
60622 +    A_CHAR stream[60];
60623 +    A_UINT32 i;
60624 +    A_UINT16 offset, count;
60625 +
60626 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<---------Dumping %d Bytes : %s ------>\n", length, pDescription));
60627 +
60628 +    count = 0;
60629 +    offset = 0;
60630 +    for(i = 0; i < length; i++) {
60631 +        sprintf(stream + offset, "%2.2X ", buffer[i]);
60632 +        count ++;
60633 +        offset += 3;
60634 +
60635 +        if(count == 16) {
60636 +            count = 0;
60637 +            offset = 0;
60638 +            AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream));
60639 +            A_MEMZERO(stream, 60);
60640 +        }
60641 +    }
60642 +
60643 +    if(offset != 0) {
60644 +        AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream));
60645 +    }
60646 +
60647 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------------------------->\n"));
60648 +}
60649 +
60650 +A_BOOL HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
60651 +                                HTC_ENDPOINT_ID          Endpoint,
60652 +                                HTC_ENDPOINT_STAT_ACTION Action,
60653 +                                HTC_ENDPOINT_STATS       *pStats)
60654 +{
60655 +
60656 +#ifdef HTC_EP_STAT_PROFILING
60657 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
60658 +    A_BOOL     clearStats = FALSE;
60659 +    A_BOOL     sample = FALSE;
60660 +
60661 +    switch (Action) {
60662 +        case HTC_EP_STAT_SAMPLE :
60663 +            sample = TRUE;
60664 +            break;
60665 +        case HTC_EP_STAT_SAMPLE_AND_CLEAR :
60666 +            sample = TRUE;
60667 +            clearStats = TRUE;
60668 +            break;
60669 +        case HTC_EP_STAT_CLEAR :
60670 +            clearStats = TRUE;
60671 +            break;
60672 +        default:
60673 +            break;
60674 +    }
60675 +
60676 +    A_ASSERT(Endpoint < ENDPOINT_MAX);
60677 +
60678 +        /* lock out TX and RX while we sample and/or clear */
60679 +    LOCK_HTC_TX(target);
60680 +    LOCK_HTC_RX(target);
60681 +
60682 +    if (sample) {
60683 +        A_ASSERT(pStats != NULL);
60684 +            /* return the stats to the caller */
60685 +        A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
60686 +    }
60687 +
60688 +    if (clearStats) {
60689 +            /* reset stats */
60690 +        A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
60691 +    }
60692 +
60693 +    UNLOCK_HTC_RX(target);
60694 +    UNLOCK_HTC_TX(target);
60695 +
60696 +    return TRUE;
60697 +#else
60698 +    return FALSE;
60699 +#endif
60700 +}
60701 Index: linux-2.6.28/drivers/ar6000/htc/htc_debug.h
60702 ===================================================================
60703 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
60704 +++ linux-2.6.28/drivers/ar6000/htc/htc_debug.h 2009-01-02 00:01:56.000000000 +0100
60705 @@ -0,0 +1,65 @@
60706 +#ifndef HTC_DEBUG_H_
60707 +#define HTC_DEBUG_H_
60708 +/*
60709 + *
60710 + * Copyright (c) 2004-2007 Atheros Communications Inc.
60711 + * All rights reserved.
60712 + *
60713 + *
60714 + *  This program is free software; you can redistribute it and/or modify
60715 + *  it under the terms of the GNU General Public License version 2 as
60716 + *  published by the Free Software Foundation;
60717 + *
60718 + *  Software distributed under the License is distributed on an "AS
60719 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60720 + *  implied. See the License for the specific language governing
60721 + *  rights and limitations under the License.
60722 + *
60723 + *
60724 + *
60725 + */
60726 +
60727 +/* ------- Debug related stuff ------- */
60728 +enum {
60729 +    ATH_DEBUG_SEND = 0x0001,
60730 +    ATH_DEBUG_RECV = 0x0002,
60731 +    ATH_DEBUG_SYNC = 0x0004,
60732 +    ATH_DEBUG_DUMP = 0x0008,
60733 +    ATH_DEBUG_IRQ  = 0x0010,
60734 +    ATH_DEBUG_TRC  = 0x0020,
60735 +    ATH_DEBUG_WARN = 0x0040,
60736 +    ATH_DEBUG_ERR  = 0x0080,
60737 +    ATH_DEBUG_ANY  = 0xFFFF,
60738 +};
60739 +
60740 +#ifdef DEBUG
60741 +
60742 +// TODO FIX usage of A_PRINTF!
60743 +#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl))
60744 +#define AR_DEBUG_PRINTBUF(buffer, length, desc) do {   \
60745 +    if (debughtc & ATH_DEBUG_DUMP) {             \
60746 +        DebugDumpBytes(buffer, length,desc);               \
60747 +    }                                            \
60748 +} while(0)
60749 +#define PRINTX_ARG(arg...) arg
60750 +#define AR_DEBUG_PRINTF(flags, args) do {        \
60751 +    if (debughtc & (flags)) {                    \
60752 +        A_PRINTF(KERN_ALERT PRINTX_ARG args);    \
60753 +    }                                            \
60754 +} while (0)
60755 +#define AR_DEBUG_ASSERT(test) do {               \
60756 +    if (!(test)) {                               \
60757 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test));         \
60758 +    }                                            \
60759 +} while(0)
60760 +extern int debughtc;
60761 +#else
60762 +#define AR_DEBUG_PRINTF(flags, args)
60763 +#define AR_DEBUG_PRINTBUF(buffer, length, desc)
60764 +#define AR_DEBUG_ASSERT(test)
60765 +#define AR_DEBUG_LVL_CHECK(lvl) 0
60766 +#endif
60767 +
60768 +void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
60769 +
60770 +#endif /*HTC_DEBUG_H_*/
60771 Index: linux-2.6.28/drivers/ar6000/htc/htc_internal.h
60772 ===================================================================
60773 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
60774 +++ linux-2.6.28/drivers/ar6000/htc/htc_internal.h      2009-01-02 00:01:56.000000000 +0100
60775 @@ -0,0 +1,168 @@
60776 +/*
60777 + *
60778 + * Copyright (c) 2007 Atheros Communications Inc.
60779 + * All rights reserved.
60780 + *
60781 + *
60782 + *  This program is free software; you can redistribute it and/or modify
60783 + *  it under the terms of the GNU General Public License version 2 as
60784 + *  published by the Free Software Foundation;
60785 + *
60786 + *  Software distributed under the License is distributed on an "AS
60787 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60788 + *  implied. See the License for the specific language governing
60789 + *  rights and limitations under the License.
60790 + *
60791 + *
60792 + *
60793 + */
60794 +
60795 +#ifndef _HTC_INTERNAL_H_
60796 +#define _HTC_INTERNAL_H_
60797 +
60798 +/* for debugging, uncomment this to capture the last frame header, on frame header
60799 + * processing errors, the last frame header is dump for comparison */
60800 +//#define HTC_CAPTURE_LAST_FRAME
60801 +
60802 +//#define HTC_EP_STAT_PROFILING
60803 +
60804 +#ifdef __cplusplus
60805 +extern "C" {
60806 +#endif /* __cplusplus */
60807 +
60808 +/* Header files */
60809 +#include "a_config.h"
60810 +#include "athdefs.h"
60811 +#include "a_types.h"
60812 +#include "a_osapi.h"
60813 +#include "a_debug.h"
60814 +#include "htc.h"
60815 +#include "htc_api.h"
60816 +#include "bmi_msg.h"
60817 +#include "hif.h"
60818 +#include "ar6k.h"
60819 +
60820 +/* HTC operational parameters */
60821 +#define HTC_TARGET_RESPONSE_TIMEOUT        2000 /* in ms */
60822 +#define HTC_TARGET_DEBUG_INTR_MASK         0x01
60823 +#define HTC_TARGET_CREDIT_INTR_MASK        0xF0
60824 +
60825 +typedef struct _HTC_ENDPOINT {
60826 +    HTC_SERVICE_ID              ServiceID;      /* service ID this endpoint is bound to
60827 +                                                   non-zero value means this endpoint is in use */
60828 +    HTC_PACKET_QUEUE            TxQueue;        /* HTC frame buffer TX queue */
60829 +    HTC_PACKET_QUEUE            RxBuffers;      /* HTC frame buffer RX list */
60830 +    HTC_ENDPOINT_CREDIT_DIST    CreditDist;     /* credit distribution structure (exposed to driver layer) */
60831 +    HTC_EP_CALLBACKS            EpCallBacks;    /* callbacks associated with this endpoint */
60832 +    int                         MaxTxQueueDepth;   /* max depth of the TX queue before we need to
60833 +                                                      call driver's full handler */
60834 +    int                         CurrentTxQueueDepth; /* current TX queue depth */
60835 +    int                         MaxMsgLength;        /* max length of endpoint message */
60836 +#ifdef HTC_EP_STAT_PROFILING
60837 +    HTC_ENDPOINT_STATS          EndPointStats;  /* endpoint statistics */
60838 +#endif
60839 +} HTC_ENDPOINT;
60840 +
60841 +#ifdef HTC_EP_STAT_PROFILING
60842 +#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
60843 +#else
60844 +#define INC_HTC_EP_STAT(p,stat,count)
60845 +#endif
60846 +
60847 +#define HTC_SERVICE_TX_PACKET_TAG  HTC_TX_PACKET_TAG_INTERNAL
60848 +
60849 +#define NUM_CONTROL_BUFFERS     8
60850 +#define NUM_CONTROL_TX_BUFFERS  2
60851 +#define NUM_CONTROL_RX_BUFFERS  (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
60852 +
60853 +#define HTC_CONTROL_BUFFER_SIZE (HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH)
60854 +
60855 +typedef struct HTC_CONTROL_BUFFER {
60856 +    HTC_PACKET    HtcPacket;
60857 +    A_UINT8       Buffer[HTC_CONTROL_BUFFER_SIZE];
60858 +} HTC_CONTROL_BUFFER;
60859 +
60860 +/* our HTC target state */
60861 +typedef struct _HTC_TARGET {
60862 +    HTC_ENDPOINT                EndPoint[ENDPOINT_MAX];
60863 +    HTC_CONTROL_BUFFER          HTCControlBuffers[NUM_CONTROL_BUFFERS];
60864 +    HTC_ENDPOINT_CREDIT_DIST   *EpCreditDistributionListHead;
60865 +    HTC_PACKET_QUEUE            ControlBufferTXFreeList;
60866 +    HTC_PACKET_QUEUE            ControlBufferRXFreeList;
60867 +    HTC_CREDIT_DIST_CALLBACK    DistributeCredits;
60868 +    HTC_CREDIT_INIT_CALLBACK    InitCredits;
60869 +    void                       *pCredDistContext;
60870 +    int                         TargetCredits;
60871 +    int                         TargetCreditSize;
60872 +    A_MUTEX_T                   HTCLock;
60873 +    A_MUTEX_T                   HTCRxLock;
60874 +    A_MUTEX_T                   HTCTxLock;
60875 +    AR6K_DEVICE                 Device;         /* AR6K - specific state */
60876 +    A_UINT32                    HTCStateFlags;
60877 +    HTC_ENDPOINT_ID             EpWaitingForBuffers;
60878 +    A_BOOL                      TargetFailure;
60879 +    void                       *pInstanceContext;
60880 +#define HTC_STATE_WAIT_BUFFERS  (1 << 0)
60881 +#define HTC_STATE_STOPPING      (1 << 1)
60882 +#ifdef HTC_CAPTURE_LAST_FRAME
60883 +    HTC_FRAME_HDR               LastFrameHdr;  /* useful for debugging */
60884 +    A_UINT8                     LastTrailer[256];
60885 +    A_UINT8                     LastTrailerLength;
60886 +#endif
60887 +} HTC_TARGET;
60888 +
60889 +#define HTC_STOPPING(t) ((t)->HTCStateFlags & HTC_STATE_STOPPING)
60890 +#define LOCK_HTC(t)      A_MUTEX_LOCK(&(t)->HTCLock);
60891 +#define UNLOCK_HTC(t)    A_MUTEX_UNLOCK(&(t)->HTCLock);
60892 +#define LOCK_HTC_RX(t)   A_MUTEX_LOCK(&(t)->HTCRxLock);
60893 +#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
60894 +#define LOCK_HTC_TX(t)   A_MUTEX_LOCK(&(t)->HTCTxLock);
60895 +#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
60896 +
60897 +#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
60898 +#define HTC_RECYCLE_RX_PKT(target,p)                \
60899 +{                                                   \
60900 +    HTC_PACKET_RESET_RX(pPacket);                   \
60901 +    HTCAddReceivePkt((HTC_HANDLE)(target),(p));     \
60902 +}
60903 +
60904 +/* internal HTC functions */
60905 +void        HTCControlTxComplete(void *Context, HTC_PACKET *pPacket);
60906 +void        HTCControlRecv(void *Context, HTC_PACKET *pPacket);
60907 +A_STATUS    HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket);
60908 +HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
60909 +void        HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
60910 +A_STATUS    HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 Flags);
60911 +A_STATUS    HTCIssueRecv(HTC_TARGET *target, HTC_PACKET *pPacket);
60912 +void        HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
60913 +A_STATUS    HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc);
60914 +void        HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
60915 +A_STATUS    HTCSendSetupComplete(HTC_TARGET *target);
60916 +void        HTCFlushRecvBuffers(HTC_TARGET *target);
60917 +void        HTCFlushSendPkts(HTC_TARGET *target);
60918 +void        DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist);
60919 +void        DumpCreditDistStates(HTC_TARGET *target);
60920 +void           DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
60921 +
60922 +static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) {
60923 +    HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
60924 +    if (pPacket != NULL) {
60925 +            /* set payload pointer area with some headroom */
60926 +        pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
60927 +    }
60928 +    return pPacket;
60929 +}
60930 +
60931 +#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
60932 +#define HTC_ALLOC_CONTROL_RX(t)  HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
60933 +#define HTC_FREE_CONTROL_RX(t,p) \
60934 +{                                                                \
60935 +    HTC_PACKET_RESET_RX(p);                                      \
60936 +    HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
60937 +}
60938 +
60939 +#ifdef __cplusplus
60940 +}
60941 +#endif
60942 +
60943 +#endif /* _HTC_INTERNAL_H_ */
60944 Index: linux-2.6.28/drivers/ar6000/htc/htc_recv.c
60945 ===================================================================
60946 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
60947 +++ linux-2.6.28/drivers/ar6000/htc/htc_recv.c  2009-01-02 00:01:56.000000000 +0100
60948 @@ -0,0 +1,703 @@
60949 +/*
60950 + *
60951 + * Copyright (c) 2007 Atheros Communications Inc.
60952 + * All rights reserved.
60953 + *
60954 + *
60955 + *  This program is free software; you can redistribute it and/or modify
60956 + *  it under the terms of the GNU General Public License version 2 as
60957 + *  published by the Free Software Foundation;
60958 + *
60959 + *  Software distributed under the License is distributed on an "AS
60960 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
60961 + *  implied. See the License for the specific language governing
60962 + *  rights and limitations under the License.
60963 + *
60964 + *
60965 + *
60966 + */
60967 +
60968 +#include "htc_internal.h"
60969 +
60970 +#define HTCIssueRecv(t, p) \
60971 +    DevRecvPacket(&(t)->Device,  \
60972 +                  (p),          \
60973 +                  (p)->ActualLength)
60974 +
60975 +#define DO_RCV_COMPLETION(t,p,e)            \
60976 +{                                           \
60977 +    if ((p)->ActualLength > 0) {            \
60978 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" completing packet 0x%X (%d bytes) on ep : %d \n", \
60979 +            (A_UINT32)(p), (p)->ActualLength, (p)->Endpoint));  \
60980 +        (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext,      \
60981 +                                (p));                           \
60982 +    } else {                                                    \
60983 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" recycling empty packet \n"));  \
60984 +        HTC_RECYCLE_RX_PKT((t), (p));                           \
60985 +    }                                                           \
60986 +}
60987 +
60988 +#ifdef HTC_EP_STAT_PROFILING
60989 +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)            \
60990 +{                                                      \
60991 +    LOCK_HTC_RX((t));                                  \
60992 +    INC_HTC_EP_STAT((ep), RxReceived, 1);              \
60993 +    if ((lookAhead) != 0) {                            \
60994 +        INC_HTC_EP_STAT((ep), RxLookAheads, 1);        \
60995 +    }                                                  \
60996 +    UNLOCK_HTC_RX((t));                                \
60997 +}
60998 +#else
60999 +#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
61000 +#endif
61001 +
61002 +static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target,
61003 +                                         A_UINT8    *pBuffer,
61004 +                                         int         Length,
61005 +                                         A_UINT32   *pNextLookAhead,
61006 +                                         HTC_ENDPOINT_ID FromEndpoint)
61007 +{
61008 +    HTC_RECORD_HDR          *pRecord;
61009 +    A_UINT8                 *pRecordBuf;
61010 +    HTC_LOOKAHEAD_REPORT    *pLookAhead;
61011 +    A_UINT8                 *pOrigBuffer;
61012 +    int                     origLength;
61013 +    A_STATUS                status;
61014 +
61015 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length));
61016 +
61017 +    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
61018 +        AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer");
61019 +    }
61020 +
61021 +    pOrigBuffer = pBuffer;
61022 +    origLength = Length;
61023 +    status = A_OK;
61024 +
61025 +    while (Length > 0) {
61026 +
61027 +        if (Length < sizeof(HTC_RECORD_HDR)) {
61028 +            status = A_EPROTO;
61029 +            break;
61030 +        }
61031 +            /* these are byte aligned structs */
61032 +        pRecord = (HTC_RECORD_HDR *)pBuffer;
61033 +        Length -= sizeof(HTC_RECORD_HDR);
61034 +        pBuffer += sizeof(HTC_RECORD_HDR);
61035 +
61036 +        if (pRecord->Length > Length) {
61037 +                /* no room left in buffer for record */
61038 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61039 +                (" invalid record length: %d (id:%d) buffer has: %d bytes left \n",
61040 +                        pRecord->Length, pRecord->RecordID, Length));
61041 +            status = A_EPROTO;
61042 +            break;
61043 +        }
61044 +            /* start of record follows the header */
61045 +        pRecordBuf = pBuffer;
61046 +
61047 +        switch (pRecord->RecordID) {
61048 +            case HTC_RECORD_CREDITS:
61049 +                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT));
61050 +                HTCProcessCreditRpt(target,
61051 +                                    (HTC_CREDIT_REPORT *)pRecordBuf,
61052 +                                    pRecord->Length / (sizeof(HTC_CREDIT_REPORT)),
61053 +                                    FromEndpoint);
61054 +                break;
61055 +            case HTC_RECORD_LOOKAHEAD:
61056 +                AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT));
61057 +                pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf;
61058 +                if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) &&
61059 +                    (pNextLookAhead != NULL)) {
61060 +
61061 +                    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
61062 +                                (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n",
61063 +                                pLookAhead->PreValid,
61064 +                                pLookAhead->PostValid));
61065 +
61066 +                        /* look ahead bytes are valid, copy them over */
61067 +                    ((A_UINT8 *)pNextLookAhead)[0] = pLookAhead->LookAhead[0];
61068 +                    ((A_UINT8 *)pNextLookAhead)[1] = pLookAhead->LookAhead[1];
61069 +                    ((A_UINT8 *)pNextLookAhead)[2] = pLookAhead->LookAhead[2];
61070 +                    ((A_UINT8 *)pNextLookAhead)[3] = pLookAhead->LookAhead[3];
61071 +
61072 +                    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
61073 +                        DebugDumpBytes((A_UINT8 *)pNextLookAhead,4,"Next Look Ahead");
61074 +                    }
61075 +                }
61076 +                break;
61077 +            default:
61078 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n",
61079 +                        pRecord->RecordID, pRecord->Length));
61080 +                break;
61081 +        }
61082 +
61083 +        if (A_FAILED(status)) {
61084 +            break;
61085 +        }
61086 +
61087 +            /* advance buffer past this record for next time around */
61088 +        pBuffer += pRecord->Length;
61089 +        Length -= pRecord->Length;
61090 +    }
61091 +
61092 +    if (A_FAILED(status)) {
61093 +        DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer");
61094 +    }
61095 +
61096 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n"));
61097 +    return status;
61098 +
61099 +}
61100 +
61101 +/* process a received message (i.e. strip off header, process any trailer data)
61102 + * note : locks must be released when this function is called */
61103 +static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT32 *pNextLookAhead)
61104 +{
61105 +    A_UINT8   temp;
61106 +    A_UINT8   *pBuf;
61107 +    A_STATUS  status = A_OK;
61108 +    A_UINT16  payloadLen;
61109 +    A_UINT32  lookAhead;
61110 +
61111 +    pBuf = pPacket->pBuffer;
61112 +
61113 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n"));
61114 +
61115 +    if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
61116 +        AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT");
61117 +    }
61118 +
61119 +    do {
61120 +        /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to
61121 +         * retrieve 16 bit fields */
61122 +        payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen);
61123 +
61124 +        ((A_UINT8 *)&lookAhead)[0] = pBuf[0];
61125 +        ((A_UINT8 *)&lookAhead)[1] = pBuf[1];
61126 +        ((A_UINT8 *)&lookAhead)[2] = pBuf[2];
61127 +        ((A_UINT8 *)&lookAhead)[3] = pBuf[3];
61128 +
61129 +        if (lookAhead != pPacket->HTCReserved) {
61130 +            /* somehow the lookahead that gave us the full read length did not
61131 +             * reflect the actual header in the pending message */
61132 +             AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61133 +                    ("HTCProcessRecvHeader, lookahead mismatch! \n"));
61134 +             DebugDumpBytes((A_UINT8 *)&pPacket->HTCReserved,4,"Expected Message LookAhead");
61135 +             DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header");
61136 +#ifdef HTC_CAPTURE_LAST_FRAME
61137 +            DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header");
61138 +            if (target->LastTrailerLength != 0) {
61139 +                DebugDumpBytes(target->LastTrailer,
61140 +                               target->LastTrailerLength,
61141 +                               "Last trailer");
61142 +            }
61143 +#endif
61144 +            status = A_EPROTO;
61145 +            break;
61146 +        }
61147 +
61148 +            /* get flags */
61149 +        temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags);
61150 +
61151 +        if (temp & HTC_FLAGS_RECV_TRAILER) {
61152 +            /* this packet has a trailer */
61153 +
61154 +                /* extract the trailer length in control byte 0 */
61155 +            temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]);
61156 +
61157 +            if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) {
61158 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61159 +                    ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n",
61160 +                        payloadLen, temp));
61161 +                status = A_EPROTO;
61162 +                break;
61163 +            }
61164 +
61165 +                /* process trailer data that follows HDR + application payload */
61166 +            status = HTCProcessTrailer(target,
61167 +                                       (pBuf + HTC_HDR_LENGTH + payloadLen - temp),
61168 +                                       temp,
61169 +                                       pNextLookAhead,
61170 +                                       pPacket->Endpoint);
61171 +
61172 +            if (A_FAILED(status)) {
61173 +                break;
61174 +            }
61175 +
61176 +#ifdef HTC_CAPTURE_LAST_FRAME
61177 +            A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp);
61178 +            target->LastTrailerLength = temp;
61179 +#endif
61180 +                /* trim length by trailer bytes */
61181 +            pPacket->ActualLength -= temp;
61182 +        }
61183 +#ifdef HTC_CAPTURE_LAST_FRAME
61184 +         else {
61185 +            target->LastTrailerLength = 0;
61186 +        }
61187 +#endif
61188 +
61189 +            /* if we get to this point, the packet is good */
61190 +            /* remove header and adjust length */
61191 +        pPacket->pBuffer += HTC_HDR_LENGTH;
61192 +        pPacket->ActualLength -= HTC_HDR_LENGTH;
61193 +
61194 +    } while (FALSE);
61195 +
61196 +    if (A_FAILED(status)) {
61197 +            /* dump the whole packet */
61198 +        DebugDumpBytes(pBuf,pPacket->ActualLength,"BAD HTC Recv PKT");
61199 +    } else {
61200 +#ifdef HTC_CAPTURE_LAST_FRAME
61201 +        A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR));
61202 +#endif
61203 +        if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
61204 +            if (pPacket->ActualLength > 0) {
61205 +                AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg");
61206 +            }
61207 +        }
61208 +    }
61209 +
61210 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n"));
61211 +    return status;
61212 +}
61213 +
61214 +/* asynchronous completion handler for recv packet fetching, when the device layer
61215 + * completes a read request, it will call this completion handler */
61216 +void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
61217 +{
61218 +    HTC_TARGET      *target = (HTC_TARGET *)Context;
61219 +    HTC_ENDPOINT    *pEndpoint;
61220 +    A_UINT32        nextLookAhead = 0;
61221 +    A_STATUS        status;
61222 +
61223 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (status:%d, ep:%d) \n",
61224 +                pPacket->Status, pPacket->Endpoint));
61225 +
61226 +    AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
61227 +    pEndpoint = &target->EndPoint[pPacket->Endpoint];
61228 +    pPacket->Completion = NULL;
61229 +
61230 +        /* get completion status */
61231 +    status = pPacket->Status;
61232 +
61233 +    do {
61234 +        if (A_FAILED(status)) {
61235 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n",
61236 +                pPacket->Status, pPacket->Endpoint));
61237 +            break;
61238 +        }
61239 +            /* process the header for any trailer data */
61240 +        status = HTCProcessRecvHeader(target,pPacket,&nextLookAhead);
61241 +
61242 +        if (A_FAILED(status)) {
61243 +            break;
61244 +        }
61245 +            /* was there a lookahead for the next packet? */
61246 +        if (nextLookAhead != 0) {
61247 +            A_STATUS nextStatus;
61248 +            AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
61249 +                            ("HTCRecvCompleteHandler - next look ahead was non-zero : 0x%X \n",
61250 +                             nextLookAhead));
61251 +                /* we have another packet, get the next packet fetch started (pipelined) before
61252 +                 * we call into the endpoint's callback, this will start another async request */
61253 +            nextStatus = HTCRecvMessagePendingHandler(target,nextLookAhead,NULL);
61254 +            if (A_EPROTO == nextStatus) {
61255 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61256 +                            ("Next look ahead from recv header was INVALID\n"));
61257 +                DebugDumpBytes((A_UINT8 *)&nextLookAhead,
61258 +                                4,
61259 +                                "BAD lookahead from lookahead report");
61260 +            }
61261 +        } else {
61262 +             AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
61263 +            ("HTCRecvCompleteHandler - rechecking for more messages...\n"));
61264 +            /* if we did not get anything on the look-ahead,
61265 +             * call device layer to asynchronously re-check for messages. If we can keep the async
61266 +             * processing going we get better performance.  If there is a pending message we will keep processing
61267 +             * messages asynchronously which should pipeline things nicely */
61268 +            DevCheckPendingRecvMsgsAsync(&target->Device);
61269 +        }
61270 +
61271 +        HTC_RX_STAT_PROFILE(target,pEndpoint,nextLookAhead);
61272 +        DO_RCV_COMPLETION(target,pPacket,pEndpoint);
61273 +
61274 +    } while (FALSE);
61275 +
61276 +    if (A_FAILED(status)) {
61277 +         AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61278 +                         ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n",
61279 +                         status));
61280 +            /* recyle this packet */
61281 +         HTC_RECYCLE_RX_PKT(target, pPacket);
61282 +    }
61283 +
61284 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n"));
61285 +}
61286 +
61287 +/* synchronously wait for a control message from the target,
61288 + * This function is used at initialization time ONLY.  At init messages
61289 + * on ENDPOINT 0 are expected. */
61290 +A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
61291 +{
61292 +    A_STATUS        status;
61293 +    A_UINT32        lookAhead;
61294 +    HTC_PACKET      *pPacket = NULL;
61295 +    HTC_FRAME_HDR   *pHdr;
61296 +
61297 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n"));
61298 +
61299 +    do  {
61300 +
61301 +        *ppControlPacket = NULL;
61302 +
61303 +            /* call the polling function to see if we have a message */
61304 +        status = DevPollMboxMsgRecv(&target->Device,
61305 +                                    &lookAhead,
61306 +                                    HTC_TARGET_RESPONSE_TIMEOUT);
61307 +
61308 +        if (A_FAILED(status)) {
61309 +            break;
61310 +        }
61311 +
61312 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
61313 +                ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead));
61314 +
61315 +            /* check the lookahead */
61316 +        pHdr = (HTC_FRAME_HDR *)&lookAhead;
61317 +
61318 +        if (pHdr->EndpointID != ENDPOINT_0) {
61319 +                /* unexpected endpoint number, should be zero */
61320 +            AR_DEBUG_ASSERT(FALSE);
61321 +            status = A_EPROTO;
61322 +            break;
61323 +        }
61324 +
61325 +        if (A_FAILED(status)) {
61326 +                /* bad message */
61327 +            AR_DEBUG_ASSERT(FALSE);
61328 +            status = A_EPROTO;
61329 +            break;
61330 +        }
61331 +
61332 +        pPacket = HTC_ALLOC_CONTROL_RX(target);
61333 +
61334 +        if (pPacket == NULL) {
61335 +            AR_DEBUG_ASSERT(FALSE);
61336 +            status = A_NO_MEMORY;
61337 +            break;
61338 +        }
61339 +
61340 +        pPacket->HTCReserved = lookAhead;
61341 +        pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
61342 +
61343 +        if (pPacket->ActualLength > pPacket->BufferLength) {
61344 +            AR_DEBUG_ASSERT(FALSE);
61345 +            status = A_EPROTO;
61346 +            break;
61347 +        }
61348 +
61349 +            /* we want synchronous operation */
61350 +        pPacket->Completion = NULL;
61351 +
61352 +            /* get the message from the device, this will block */
61353 +        status = HTCIssueRecv(target, pPacket);
61354 +
61355 +        if (A_FAILED(status)) {
61356 +            break;
61357 +        }
61358 +
61359 +            /* process receive header */
61360 +        status = HTCProcessRecvHeader(target,pPacket,NULL);
61361 +
61362 +        pPacket->Status = status;
61363 +
61364 +        if (A_FAILED(status)) {
61365 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61366 +                    ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n",
61367 +                     status));
61368 +            break;
61369 +        }
61370 +
61371 +            /* give the caller this control message packet, they are responsible to free */
61372 +        *ppControlPacket = pPacket;
61373 +
61374 +    } while (FALSE);
61375 +
61376 +    if (A_FAILED(status)) {
61377 +        if (pPacket != NULL) {
61378 +                /* cleanup buffer on error */
61379 +            HTC_FREE_CONTROL_RX(target,pPacket);
61380 +        }
61381 +    }
61382 +
61383 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n"));
61384 +
61385 +    return status;
61386 +}
61387 +
61388 +/* callback when device layer or lookahead report parsing detects a pending message */
61389 +A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc)
61390 +{
61391 +    HTC_TARGET      *target = (HTC_TARGET *)Context;
61392 +    A_STATUS         status = A_OK;
61393 +    HTC_PACKET      *pPacket = NULL;
61394 +    HTC_FRAME_HDR   *pHdr;
61395 +    HTC_ENDPOINT    *pEndpoint;
61396 +    A_BOOL          asyncProc = FALSE;
61397 +
61398 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler LookAhead:0x%X \n",LookAhead));
61399 +
61400 +    if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) {
61401 +            /* We use async mode to get the packets if the device layer supports it.
61402 +             * The device layer interfaces with HIF in which HIF may have restrictions on
61403 +             * how interrupts are processed */
61404 +        asyncProc = TRUE;
61405 +    }
61406 +
61407 +    if (pAsyncProc != NULL) {
61408 +            /* indicate to caller how we decided to process this */
61409 +        *pAsyncProc = asyncProc;
61410 +    }
61411 +
61412 +    while (TRUE) {
61413 +
61414 +        pHdr = (HTC_FRAME_HDR *)&LookAhead;
61415 +
61416 +        if (pHdr->EndpointID >= ENDPOINT_MAX) {
61417 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID));
61418 +                /* invalid endpoint */
61419 +            status = A_EPROTO;
61420 +            break;
61421 +        }
61422 +
61423 +        if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) {
61424 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n",
61425 +                    pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH));
61426 +            status = A_EPROTO;
61427 +            break;
61428 +        }
61429 +
61430 +        pEndpoint = &target->EndPoint[pHdr->EndpointID];
61431 +
61432 +        if (0 == pEndpoint->ServiceID) {
61433 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID));
61434 +                /* endpoint isn't even connected */
61435 +            status = A_EPROTO;
61436 +            break;
61437 +        }
61438 +
61439 +            /* lock RX to get a buffer */
61440 +        LOCK_HTC_RX(target);
61441 +
61442 +            /* get a packet from the endpoint recv queue */
61443 +        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
61444 +
61445 +        if (NULL == pPacket) {
61446 +                /* check for refill handler */
61447 +            if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) {
61448 +                UNLOCK_HTC_RX(target);
61449 +                    /* call the re-fill handler */
61450 +                pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
61451 +                                                    pHdr->EndpointID);
61452 +                LOCK_HTC_RX(target);
61453 +                    /* check if we have more buffers */
61454 +                pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
61455 +                    /* fall through */
61456 +            }
61457 +        }
61458 +
61459 +        if (NULL == pPacket) {
61460 +                /* this is not an error, we simply need to mark that we are waiting for buffers.*/
61461 +            target->HTCStateFlags |= HTC_STATE_WAIT_BUFFERS;
61462 +            target->EpWaitingForBuffers = pHdr->EndpointID;
61463 +            status = A_NO_MEMORY;
61464 +        }
61465 +
61466 +        UNLOCK_HTC_RX(target);
61467 +
61468 +        if (A_FAILED(status)) {
61469 +                /* no buffers */
61470 +            break;
61471 +        }
61472 +
61473 +        AR_DEBUG_ASSERT(pPacket->Endpoint == pHdr->EndpointID);
61474 +
61475 +            /* make sure this message can fit in the endpoint buffer */
61476 +        if ((pHdr->PayloadLen + HTC_HDR_LENGTH) > pPacket->BufferLength) {
61477 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61478 +                    ("Payload Length Error : header reports payload of: %d, endpoint buffer size: %d \n",
61479 +                    pHdr->PayloadLen, pPacket->BufferLength));
61480 +            status = A_EPROTO;
61481 +            break;
61482 +        }
61483 +
61484 +        pPacket->HTCReserved = LookAhead; /* set expected look ahead */
61485 +            /* set the amount of data to fetch */
61486 +        pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
61487 +
61488 +        if (asyncProc) {
61489 +                /* we use async mode to get the packet if the device layer supports it
61490 +                 * set our callback and context */
61491 +            pPacket->Completion = HTCRecvCompleteHandler;
61492 +            pPacket->pContext = target;
61493 +        } else {
61494 +                /* fully synchronous */
61495 +            pPacket->Completion = NULL;
61496 +        }
61497 +
61498 +            /* go fetch the packet */
61499 +        status = HTCIssueRecv(target, pPacket);
61500 +
61501 +        if (A_FAILED(status)) {
61502 +            break;
61503 +        }
61504 +
61505 +        if (asyncProc) {
61506 +                /* we did this asynchronously so we can get out of the loop, the asynch processing
61507 +                 * creates a chain of requests to continue processing pending messages in the
61508 +                 * context of callbacks  */
61509 +            break;
61510 +        }
61511 +
61512 +            /* in the sync case, we process the packet, check lookaheads and then repeat */
61513 +
61514 +        LookAhead = 0;
61515 +        status = HTCProcessRecvHeader(target,pPacket,&LookAhead);
61516 +
61517 +        if (A_FAILED(status)) {
61518 +            break;
61519 +        }
61520 +
61521 +        HTC_RX_STAT_PROFILE(target,pEndpoint,LookAhead);
61522 +        DO_RCV_COMPLETION(target,pPacket,pEndpoint);
61523 +
61524 +        pPacket = NULL;
61525 +
61526 +        if (0 == LookAhead) {
61527 +            break;
61528 +        }
61529 +
61530 +    }
61531 +
61532 +    if (A_NO_MEMORY == status) {
61533 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61534 +                (" Endpoint :%d has no buffers, blocking receiver to prevent overrun.. \n",
61535 +                pHdr->EndpointID));
61536 +            /* try to stop receive at the device layer */
61537 +        DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC);
61538 +        status = A_OK;
61539 +    } else if (A_FAILED(status)) {
61540 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61541 +                        ("Failed to get pending message : LookAhead Value: 0x%X (status = %d) \n",
61542 +                        LookAhead, status));
61543 +        if (pPacket != NULL) {
61544 +                /* clean up packet on error */
61545 +            HTC_RECYCLE_RX_PKT(target, pPacket);
61546 +        }
61547 +    }
61548 +
61549 +    AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n"));
61550 +
61551 +    return status;
61552 +}
61553 +
61554 +/* Makes a buffer available to the HTC module */
61555 +A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
61556 +{
61557 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
61558 +    HTC_ENDPOINT *pEndpoint;
61559 +    A_BOOL       unblockRecv = FALSE;
61560 +    A_STATUS     status = A_OK;
61561 +
61562 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
61563 +                    ("+- HTCAddReceivePkt: endPointId: %d, buffer: 0x%X, length: %d\n",
61564 +                    pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->BufferLength));
61565 +
61566 +    do {
61567 +
61568 +        if (HTC_STOPPING(target)) {
61569 +            status = A_ECANCELED;
61570 +            break;
61571 +        }
61572 +
61573 +        AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
61574 +
61575 +        pEndpoint = &target->EndPoint[pPacket->Endpoint];
61576 +
61577 +        LOCK_HTC_RX(target);
61578 +
61579 +            /* store receive packet */
61580 +        HTC_PACKET_ENQUEUE(&pEndpoint->RxBuffers, pPacket);
61581 +
61582 +            /* check if we are blocked waiting for a new buffer */
61583 +        if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) {
61584 +            if (target->EpWaitingForBuffers == pPacket->Endpoint) {
61585 +                AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n",
61586 +                    target->EpWaitingForBuffers));
61587 +                target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS;
61588 +                target->EpWaitingForBuffers = ENDPOINT_MAX;
61589 +                unblockRecv = TRUE;
61590 +            }
61591 +        }
61592 +
61593 +        UNLOCK_HTC_RX(target);
61594 +
61595 +        if (unblockRecv && !HTC_STOPPING(target)) {
61596 +                /* TODO : implement a buffer threshold count? */
61597 +            DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
61598 +        }
61599 +
61600 +    } while (FALSE);
61601 +
61602 +    return status;
61603 +}
61604 +
61605 +static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
61606 +{
61607 +    HTC_PACKET  *pPacket;
61608 +
61609 +    LOCK_HTC_RX(target);
61610 +
61611 +    while (1) {
61612 +        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
61613 +        if (NULL == pPacket) {
61614 +            break;
61615 +        }
61616 +        UNLOCK_HTC_RX(target);
61617 +        pPacket->Status = A_ECANCELED;
61618 +        pPacket->ActualLength = 0;
61619 +        AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("  Flushing RX packet:0x%X, length:%d, ep:%d \n",
61620 +                (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint));
61621 +            /* give the packet back */
61622 +        pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext,
61623 +                                      pPacket);
61624 +        LOCK_HTC_RX(target);
61625 +    }
61626 +
61627 +    UNLOCK_HTC_RX(target);
61628 +
61629 +
61630 +}
61631 +
61632 +void HTCFlushRecvBuffers(HTC_TARGET *target)
61633 +{
61634 +    HTC_ENDPOINT    *pEndpoint;
61635 +    int             i;
61636 +
61637 +        /* NOTE: no need to flush endpoint 0, these buffers were
61638 +         * allocated as part of the HTC struct */
61639 +    for (i = ENDPOINT_1; i < ENDPOINT_MAX; i++) {
61640 +        pEndpoint = &target->EndPoint[i];
61641 +        if (pEndpoint->ServiceID == 0) {
61642 +                /* not in use.. */
61643 +            continue;
61644 +        }
61645 +        HTCFlushEndpointRX(target,pEndpoint);
61646 +    }
61647 +
61648 +
61649 +}
61650 +
61651 +
61652 Index: linux-2.6.28/drivers/ar6000/htc/htc_send.c
61653 ===================================================================
61654 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
61655 +++ linux-2.6.28/drivers/ar6000/htc/htc_send.c  2009-01-02 00:01:56.000000000 +0100
61656 @@ -0,0 +1,543 @@
61657 +/*
61658 + *
61659 + * Copyright (c) 2007 Atheros Communications Inc.
61660 + * All rights reserved.
61661 + *
61662 + *
61663 + *  This program is free software; you can redistribute it and/or modify
61664 + *  it under the terms of the GNU General Public License version 2 as
61665 + *  published by the Free Software Foundation;
61666 + *
61667 + *  Software distributed under the License is distributed on an "AS
61668 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
61669 + *  implied. See the License for the specific language governing
61670 + *  rights and limitations under the License.
61671 + *
61672 + *
61673 + *
61674 + */
61675 +
61676 +#include "htc_internal.h"
61677 +
61678 +#define DO_EP_TX_COMPLETION(ep,p)                                    \
61679 +{                                                                    \
61680 +    (p)->Completion = NULL;                                          \
61681 +    (ep)->EpCallBacks.EpTxComplete((ep)->EpCallBacks.pContext,(p));  \
61682 +}
61683 +
61684 +
61685 +/* call the distribute credits callback with the distribution */
61686 +#define DO_DISTRIBUTION(t,reason,description,pList) \
61687 +{                                             \
61688 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,           \
61689 +        ("  calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \
61690 +                (description),                                           \
61691 +                (A_UINT32)(t)->DistributeCredits,                        \
61692 +                (A_UINT32)(t)->pCredDistContext,                         \
61693 +                (A_UINT32)pList));                                       \
61694 +    (t)->DistributeCredits((t)->pCredDistContext,                        \
61695 +                           (pList),                                      \
61696 +                           (reason));                                    \
61697 +}
61698 +
61699 +/* our internal send packet completion handler when packets are submited to the AR6K device
61700 + * layer */
61701 +static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket)
61702 +{
61703 +    HTC_TARGET      *target = (HTC_TARGET *)Context;
61704 +    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[pPacket->Endpoint];
61705 +
61706 +
61707 +    if (A_FAILED(pPacket->Status)) {
61708 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
61709 +            ("HTCSendPktCompletionHandler: request failed (status:%d, ep:%d) \n",
61710 +                pPacket->Status, pPacket->Endpoint));
61711 +    }
61712 +        /* first, fixup the head room we allocated */
61713 +    pPacket->pBuffer += HTC_HDR_LENGTH;
61714 +        /* do completion */
61715 +    DO_EP_TX_COMPLETION(pEndpoint,pPacket);
61716 +}
61717 +
61718 +A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 SendFlags)
61719 +{
61720 +    A_STATUS status;
61721 +    A_UINT8 *pHdrBuf;
61722 +    A_BOOL   sync = FALSE;
61723 +
61724 +        /* caller always provides headrooom */
61725 +    pPacket->pBuffer -= HTC_HDR_LENGTH;
61726 +    pHdrBuf = pPacket->pBuffer;
61727 +        /* setup frame header */
61728 +    A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)pPacket->ActualLength);
61729 +    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,SendFlags);
61730 +    A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)pPacket->Endpoint);
61731 +
61732 +    if (pPacket->Completion == NULL) {
61733 +            /* mark that this request was synchronously issued */
61734 +        sync = TRUE;
61735 +    }
61736 +
61737 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
61738 +                    ("+-HTCIssueSend: transmit length : %d (%s) \n",
61739 +                    pPacket->ActualLength + HTC_HDR_LENGTH,
61740 +                    sync ? "SYNC" : "ASYNC" ));
61741 +
61742 +        /* send message to device */
61743 +    status = DevSendPacket(&target->Device,
61744 +                           pPacket,
61745 +                           pPacket->ActualLength + HTC_HDR_LENGTH);
61746 +
61747 +    if (sync) {
61748 +            /* use local sync variable.  If this was issued asynchronously, pPacket is no longer
61749 +             * safe to access. */
61750 +        pPacket->pBuffer += HTC_HDR_LENGTH;
61751 +    }
61752 +
61753 +    /* if this request was asynchronous, the packet completion routine will be invoked by
61754 +     * the device layer when the HIF layer completes the request */
61755 +
61756 +    return status;
61757 +}
61758 +
61759 +/* try to send the current packet or a packet at the head of the TX queue,
61760 + * if there are no credits, the packet remains in the queue.
61761 + * this function always succeeds and returns a flag if the TX queue for
61762 + * the endpoint has hit the set limit */
61763 +static A_BOOL HTCTrySend(HTC_TARGET   *target,
61764 +                         HTC_ENDPOINT *pEndpoint,
61765 +                         HTC_PACKET   *pPacketToSend)
61766 +{
61767 +    HTC_PACKET  *pPacket;
61768 +    int         creditsRequired;
61769 +    int         remainder;
61770 +    A_UINT8     sendFlags;
61771 +    A_BOOL      epFull = FALSE;
61772 +
61773 +    LOCK_HTC_TX(target);
61774 +
61775 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (pPkt:0x%X)\n",(A_UINT32)pPacketToSend));
61776 +
61777 +    if (pPacketToSend != NULL) {
61778 +        /* caller supplied us a packet to queue to the tail of the HTC TX queue before
61779 +         * we check the tx queue */
61780 +        HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue,pPacketToSend);
61781 +        pEndpoint->CurrentTxQueueDepth++;
61782 +    }
61783 +
61784 +        /* now drain the TX queue for transmission as long as we have enough
61785 +         * credits */
61786 +
61787 +    while (1) {
61788 +
61789 +        if (HTC_QUEUE_EMPTY(&pEndpoint->TxQueue)) {
61790 +                /* nothing in the queue */
61791 +            break;
61792 +        }
61793 +
61794 +        sendFlags = 0;
61795 +
61796 +            /* get packet at head, but don't remove it */
61797 +        pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue);
61798 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n",
61799 +                (A_UINT32)pPacket, pEndpoint->CurrentTxQueueDepth));
61800 +
61801 +            /* figure out how many credits this message requires */
61802 +        creditsRequired = (pPacket->ActualLength + HTC_HDR_LENGTH) / target->TargetCreditSize;
61803 +        remainder = (pPacket->ActualLength + HTC_HDR_LENGTH) % target->TargetCreditSize;
61804 +
61805 +        if (remainder) {
61806 +            creditsRequired++;
61807 +        }
61808 +
61809 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d   Got:%d\n",
61810 +                            creditsRequired, pEndpoint->CreditDist.TxCredits));
61811 +
61812 +        if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
61813 +
61814 +            /* not enough credits */
61815 +
61816 +            if (pPacket->Endpoint == ENDPOINT_0) {
61817 +                    /* leave it in the queue */
61818 +                break;
61819 +            }
61820 +                /* invoke the registered distribution function only if this is not
61821 +                 * endpoint 0, we let the driver layer provide more credits if it can.
61822 +                 * We pass the credit distribution list starting at the endpoint in question
61823 +                 * */
61824 +
61825 +                /* set how many credits we need  */
61826 +            pEndpoint->CreditDist.TxCreditsSeek =
61827 +                                    creditsRequired - pEndpoint->CreditDist.TxCredits;
61828 +            DO_DISTRIBUTION(target,
61829 +                            HTC_CREDIT_DIST_SEEK_CREDITS,
61830 +                            "Seek Credits",
61831 +                            &pEndpoint->CreditDist);
61832 +
61833 +            pEndpoint->CreditDist.TxCreditsSeek = 0;
61834 +
61835 +            if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
61836 +                    /* still not enough credits to send, leave packet in the queue */
61837 +                AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
61838 +                    (" Not enough credits for ep %d leaving packet in queue..\n",
61839 +                    pPacket->Endpoint));
61840 +                break;
61841 +            }
61842 +
61843 +        }
61844 +
61845 +        pEndpoint->CreditDist.TxCredits -= creditsRequired;
61846 +        INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired);
61847 +
61848 +            /* check if we need credits */
61849 +        if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
61850 +            sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
61851 +            INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1);
61852 +            AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits  \n"));
61853 +        }
61854 +
61855 +            /* now we can fully dequeue */
61856 +        pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue);
61857 +        pEndpoint->CurrentTxQueueDepth--;
61858 +
61859 +        INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
61860 +
61861 +        UNLOCK_HTC_TX(target);
61862 +
61863 +        HTCIssueSend(target, pPacket, sendFlags);
61864 +
61865 +        LOCK_HTC_TX(target);
61866 +
61867 +        /* go back and check for more messages */
61868 +    }
61869 +
61870 +    if (pEndpoint->CurrentTxQueueDepth >= pEndpoint->MaxTxQueueDepth) {
61871 +            /* let caller know that this endpoint has reached the maximum depth */
61872 +        epFull = TRUE;
61873 +    }
61874 +
61875 +    UNLOCK_HTC_TX(target);
61876 +
61877 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend:  \n"));
61878 +    return epFull;
61879 +}
61880 +
61881 +/* HTC API - HTCSendPkt */
61882 +A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
61883 +{
61884 +    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
61885 +    HTC_ENDPOINT    *pEndpoint;
61886 +    HTC_ENDPOINT_ID ep;
61887 +    A_STATUS        status = A_OK;
61888 +
61889 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
61890 +                    ("+HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n",
61891 +                    pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength));
61892 +
61893 +    ep = pPacket->Endpoint;
61894 +    AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
61895 +    pEndpoint = &target->EndPoint[ep];
61896 +
61897 +    do {
61898 +
61899 +        if (HTC_STOPPING(target)) {
61900 +            status = A_ECANCELED;
61901 +            pPacket->Status = status;
61902 +            DO_EP_TX_COMPLETION(pEndpoint,pPacket);
61903 +            break;
61904 +        }
61905 +            /* everything sent through this interface is asynchronous */
61906 +            /* fill in HTC completion routines */
61907 +        pPacket->Completion = HTCSendPktCompletionHandler;
61908 +        pPacket->pContext = target;
61909 +
61910 +        if (HTCTrySend(target, pEndpoint, pPacket)) {
61911 +            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX queue is full, Depth:%d, Max:%d \n",
61912 +                    ep, pEndpoint->CurrentTxQueueDepth, pEndpoint->MaxTxQueueDepth));
61913 +                /* queue is now full, let caller know */
61914 +            if (pEndpoint->EpCallBacks.EpSendFull != NULL) {
61915 +                AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Calling driver's send full callback.... \n"));
61916 +                pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext,
61917 +                                                  ep);
61918 +            }
61919 +        }
61920 +
61921 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPkt \n"));
61922 +    } while (FALSE);
61923 +
61924 +    return status;
61925 +}
61926 +
61927 +
61928 +/* check TX queues to drain because of credit distribution update */
61929 +static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target)
61930 +{
61931 +    HTC_ENDPOINT                *pEndpoint;
61932 +    HTC_ENDPOINT_CREDIT_DIST    *pDistItem;
61933 +
61934 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n"));
61935 +    pDistItem = target->EpCreditDistributionListHead;
61936 +
61937 +        /* run through the credit distribution list to see
61938 +         * if there are packets queued
61939 +         * NOTE: no locks need to be taken since the distribution list
61940 +         * is not dynamic (cannot be re-ordered) and we are not modifying any state */
61941 +    while (pDistItem != NULL) {
61942 +        pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved;
61943 +
61944 +        if (pEndpoint->CurrentTxQueueDepth > 0) {
61945 +            AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n",
61946 +                    pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, pEndpoint->CurrentTxQueueDepth));
61947 +                /* try to start the stalled queue, this list is ordered by priority.
61948 +                 * Highest priority queue get's processed first, if there are credits available the
61949 +                 * highest priority queue will get a chance to reclaim credits from lower priority
61950 +                 * ones */
61951 +            HTCTrySend(target, pEndpoint, NULL);
61952 +        }
61953 +
61954 +        pDistItem = pDistItem->pNext;
61955 +    }
61956 +
61957 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n"));
61958 +}
61959 +
61960 +/* process credit reports and call distribution function */
61961 +void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint)
61962 +{
61963 +    int             i;
61964 +    HTC_ENDPOINT    *pEndpoint;
61965 +    int             totalCredits = 0;
61966 +    A_BOOL          doDist = FALSE;
61967 +
61968 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries));
61969 +
61970 +        /* lock out TX while we update credits */
61971 +    LOCK_HTC_TX(target);
61972 +
61973 +    for (i = 0; i < NumEntries; i++, pRpt++) {
61974 +        if (pRpt->EndpointID >= ENDPOINT_MAX) {
61975 +            AR_DEBUG_ASSERT(FALSE);
61976 +            break;
61977 +        }
61978 +
61979 +        pEndpoint = &target->EndPoint[pRpt->EndpointID];
61980 +
61981 +        AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Endpoint %d got %d credits \n",
61982 +                pRpt->EndpointID, pRpt->Credits));
61983 +
61984 +
61985 +#ifdef HTC_EP_STAT_PROFILING
61986 +
61987 +        INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
61988 +        INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
61989 +
61990 +        if (FromEndpoint == pRpt->EndpointID) {
61991 +                /* this credit report arrived on the same endpoint indicating it arrived in an RX
61992 +                 * packet */
61993 +            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits);
61994 +            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1);
61995 +        } else if (FromEndpoint == ENDPOINT_0) {
61996 +                /* this credit arrived on endpoint 0 as a NULL message */
61997 +            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits);
61998 +            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1);
61999 +        } else {
62000 +                /* arrived on another endpoint */
62001 +            INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits);
62002 +            INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
62003 +        }
62004 +
62005 +#endif
62006 +
62007 +        if (ENDPOINT_0 == pRpt->EndpointID) {
62008 +                /* always give endpoint 0 credits back */
62009 +            pEndpoint->CreditDist.TxCredits += pRpt->Credits;
62010 +        } else {
62011 +                /* for all other endpoints, update credits to distribute, the distribution function
62012 +                 * will handle giving out credits back to the endpoints */
62013 +            pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits;
62014 +                /* flag that we have to do the distribution */
62015 +            doDist = TRUE;
62016 +        }
62017 +
62018 +        totalCredits += pRpt->Credits;
62019 +    }
62020 +
62021 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("  Report indicated %d credits to distribute \n", totalCredits));
62022 +
62023 +    if (doDist) {
62024 +            /* this was a credit return based on a completed send operations
62025 +             * note, this is done with the lock held */
62026 +        DO_DISTRIBUTION(target,
62027 +                        HTC_CREDIT_DIST_SEND_COMPLETE,
62028 +                        "Send Complete",
62029 +                        target->EpCreditDistributionListHead->pNext);
62030 +    }
62031 +
62032 +    UNLOCK_HTC_TX(target);
62033 +
62034 +    if (totalCredits) {
62035 +        HTCCheckEndpointTxQueues(target);
62036 +    }
62037 +
62038 +    AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n"));
62039 +}
62040 +
62041 +/* flush endpoint TX queue */
62042 +static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag)
62043 +{
62044 +    HTC_PACKET          *pPacket;
62045 +    HTC_PACKET_QUEUE    discardQueue;
62046 +
62047 +        /* initialize the discard queue */
62048 +    INIT_HTC_PACKET_QUEUE(&discardQueue);
62049 +
62050 +    LOCK_HTC_TX(target);
62051 +
62052 +        /* interate from the front of the TX queue and flush out packets */
62053 +    ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue, pPacket, HTC_PACKET, ListLink) {
62054 +
62055 +            /* check for removal */
62056 +        if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) {
62057 +                /* remove from queue */
62058 +            HTC_PACKET_REMOVE(pPacket);
62059 +                /* add it to the discard pile */
62060 +            HTC_PACKET_ENQUEUE(&discardQueue, pPacket);
62061 +            pEndpoint->CurrentTxQueueDepth--;
62062 +        }
62063 +
62064 +    } ITERATE_END;
62065 +
62066 +    UNLOCK_HTC_TX(target);
62067 +
62068 +        /* empty the discard queue */
62069 +    while (1) {
62070 +        pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
62071 +        if (NULL == pPacket) {
62072 +            break;
62073 +        }
62074 +        pPacket->Status = A_ECANCELED;
62075 +        AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("  Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n",
62076 +                (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag));
62077 +        DO_EP_TX_COMPLETION(pEndpoint,pPacket);
62078 +    }
62079 +
62080 +}
62081 +
62082 +void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist)
62083 +{
62084 +#ifdef DEBUG
62085 +    HTC_ENDPOINT *pEndpoint = (HTC_ENDPOINT *)pEPDist->pHTCReserved;
62086 +#endif
62087 +
62088 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d  ServiceID: 0x%X    --------------\n",
62089 +                        pEPDist->Endpoint, pEPDist->ServiceID));
62090 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n",
62091 +                (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev));
62092 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags          : 0x%X \n", pEPDist->DistFlags));
62093 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm      : %d \n", pEPDist->TxCreditsNorm));
62094 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin       : %d \n", pEPDist->TxCreditsMin));
62095 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits          : %d \n", pEPDist->TxCredits));
62096 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned  : %d \n", pEPDist->TxCreditsAssigned));
62097 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek      : %d \n", pEPDist->TxCreditsSeek));
62098 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize       : %d \n", pEPDist->TxCreditSize));
62099 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg));
62100 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist    : %d \n", pEPDist->TxCreditsToDist));
62101 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth       : %d \n", pEndpoint->CurrentTxQueueDepth));
62102 +    AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n"));
62103 +}
62104 +
62105 +void DumpCreditDistStates(HTC_TARGET *target)
62106 +{
62107 +    HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead;
62108 +
62109 +    while (pEPList != NULL) {
62110 +        DumpCreditDist(pEPList);
62111 +        pEPList = pEPList->pNext;
62112 +    }
62113 +
62114 +    if (target->DistributeCredits != NULL) {
62115 +        DO_DISTRIBUTION(target,
62116 +                        HTC_DUMP_CREDIT_STATE,
62117 +                        "Dump State",
62118 +                        NULL);
62119 +    }
62120 +}
62121 +
62122 +/* flush all send packets from all endpoint queues */
62123 +void HTCFlushSendPkts(HTC_TARGET *target)
62124 +{
62125 +    HTC_ENDPOINT    *pEndpoint;
62126 +    int             i;
62127 +
62128 +    DumpCreditDistStates(target);
62129 +
62130 +    for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
62131 +        pEndpoint = &target->EndPoint[i];
62132 +        if (pEndpoint->ServiceID == 0) {
62133 +                /* not in use.. */
62134 +            continue;
62135 +        }
62136 +        HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL);
62137 +    }
62138 +
62139 +
62140 +}
62141 +
62142 +/* HTC API to flush an endpoint's TX queue*/
62143 +void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag)
62144 +{
62145 +    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
62146 +    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
62147 +
62148 +    if (pEndpoint->ServiceID == 0) {
62149 +        AR_DEBUG_ASSERT(FALSE);
62150 +        /* not in use.. */
62151 +        return;
62152 +    }
62153 +
62154 +    HTCFlushEndpointTX(target, pEndpoint, Tag);
62155 +}
62156 +
62157 +/* HTC API to indicate activity to the credit distribution function */
62158 +void HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
62159 +                               HTC_ENDPOINT_ID Endpoint,
62160 +                               A_BOOL          Active)
62161 +{
62162 +    HTC_TARGET      *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
62163 +    HTC_ENDPOINT    *pEndpoint = &target->EndPoint[Endpoint];
62164 +    A_BOOL          doDist = FALSE;
62165 +
62166 +    if (pEndpoint->ServiceID == 0) {
62167 +        AR_DEBUG_ASSERT(FALSE);
62168 +        /* not in use.. */
62169 +        return;
62170 +    }
62171 +
62172 +    LOCK_HTC_TX(target);
62173 +
62174 +    if (Active) {
62175 +        if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) {
62176 +                /* mark active now */
62177 +            pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE;
62178 +            doDist = TRUE;
62179 +        }
62180 +    } else {
62181 +        if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
62182 +                /* mark inactive now */
62183 +            pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE;
62184 +            doDist = TRUE;
62185 +        }
62186 +    }
62187 +
62188 +    if (doDist) {
62189 +        /* do distribution again based on activity change
62190 +         * note, this is done with the lock held */
62191 +        DO_DISTRIBUTION(target,
62192 +                        HTC_CREDIT_DIST_ACTIVITY_CHANGE,
62193 +                        "Activity Change",
62194 +                        target->EpCreditDistributionListHead->pNext);
62195 +    }
62196 +
62197 +    UNLOCK_HTC_TX(target);
62198 +
62199 +}
62200 Index: linux-2.6.28/drivers/ar6000/htc/htc_services.c
62201 ===================================================================
62202 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62203 +++ linux-2.6.28/drivers/ar6000/htc/htc_services.c      2009-01-02 00:01:56.000000000 +0100
62204 @@ -0,0 +1,403 @@
62205 +/*
62206 + *
62207 + * Copyright (c) 2007 Atheros Communications Inc.
62208 + * All rights reserved.
62209 + *
62210 + *
62211 + *  This program is free software; you can redistribute it and/or modify
62212 + *  it under the terms of the GNU General Public License version 2 as
62213 + *  published by the Free Software Foundation;
62214 + *
62215 + *  Software distributed under the License is distributed on an "AS
62216 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62217 + *  implied. See the License for the specific language governing
62218 + *  rights and limitations under the License.
62219 + *
62220 + *
62221 + *
62222 + */
62223 +
62224 +#include "htc_internal.h"
62225 +
62226 +void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket)
62227 +{
62228 +        /* not implemented
62229 +         * we do not send control TX frames during normal runtime, only during setup  */
62230 +    AR_DEBUG_ASSERT(FALSE);
62231 +}
62232 +
62233 +    /* callback when a control message arrives on this endpoint */
62234 +void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
62235 +{
62236 +    AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
62237 +
62238 +        /* the only control messages we are expecting are NULL messages (credit resports), which should
62239 +         * never get here */
62240 +    AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
62241 +                    ("HTCControlRecv, got message with length:%d \n",
62242 +                    pPacket->ActualLength + HTC_HDR_LENGTH));
62243 +
62244 +        /* dump header and message */
62245 +    DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
62246 +                   pPacket->ActualLength + HTC_HDR_LENGTH,
62247 +                   "Unexpected ENDPOINT 0 Message");
62248 +
62249 +    HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket);
62250 +}
62251 +
62252 +A_STATUS HTCSendSetupComplete(HTC_TARGET *target)
62253 +{
62254 +    HTC_PACKET             *pSendPacket = NULL;
62255 +    A_STATUS                status;
62256 +    HTC_SETUP_COMPLETE_MSG *pSetupComplete;
62257 +
62258 +    do {
62259 +           /* allocate a packet to send to the target */
62260 +        pSendPacket = HTC_ALLOC_CONTROL_TX(target);
62261 +
62262 +        if (NULL == pSendPacket) {
62263 +            status = A_NO_MEMORY;
62264 +            break;
62265 +        }
62266 +
62267 +            /* assemble setup complete message */
62268 +        pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
62269 +        A_MEMZERO(pSetupComplete,sizeof(HTC_SETUP_COMPLETE_MSG));
62270 +        pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;
62271 +
62272 +        SET_HTC_PACKET_INFO_TX(pSendPacket,
62273 +                               NULL,
62274 +                               (A_UINT8 *)pSetupComplete,
62275 +                               sizeof(HTC_SETUP_COMPLETE_MSG),
62276 +                               ENDPOINT_0,
62277 +                               HTC_SERVICE_TX_PACKET_TAG);
62278 +
62279 +            /* we want synchronous operation */
62280 +        pSendPacket->Completion = NULL;
62281 +            /* send the message */
62282 +        status = HTCIssueSend(target,pSendPacket,0);
62283 +
62284 +    } while (FALSE);
62285 +
62286 +    if (pSendPacket != NULL) {
62287 +        HTC_FREE_CONTROL_TX(target,pSendPacket);
62288 +    }
62289 +
62290 +    return status;
62291 +}
62292 +
62293 +
62294 +A_STATUS HTCConnectService(HTC_HANDLE               HTCHandle,
62295 +                           HTC_SERVICE_CONNECT_REQ  *pConnectReq,
62296 +                           HTC_SERVICE_CONNECT_RESP *pConnectResp)
62297 +{
62298 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
62299 +    A_STATUS                            status = A_OK;
62300 +    HTC_PACKET                          *pRecvPacket = NULL;
62301 +    HTC_PACKET                          *pSendPacket = NULL;
62302 +    HTC_CONNECT_SERVICE_RESPONSE_MSG    *pResponseMsg;
62303 +    HTC_CONNECT_SERVICE_MSG             *pConnectMsg;
62304 +    HTC_ENDPOINT_ID                     assignedEndpoint = ENDPOINT_MAX;
62305 +    HTC_ENDPOINT                        *pEndpoint;
62306 +    int                                 maxMsgSize = 0;
62307 +
62308 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n",
62309 +               (A_UINT32)target, pConnectReq->ServiceID));
62310 +
62311 +    do {
62312 +
62313 +        AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
62314 +
62315 +        if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
62316 +                /* special case for pseudo control service */
62317 +            assignedEndpoint = ENDPOINT_0;
62318 +            maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
62319 +        } else {
62320 +                /* allocate a packet to send to the target */
62321 +            pSendPacket = HTC_ALLOC_CONTROL_TX(target);
62322 +
62323 +            if (NULL == pSendPacket) {
62324 +                AR_DEBUG_ASSERT(FALSE);
62325 +                status = A_NO_MEMORY;
62326 +                break;
62327 +            }
62328 +                /* assemble connect service message */
62329 +            pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
62330 +            AR_DEBUG_ASSERT(pConnectMsg != NULL);
62331 +            A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
62332 +            pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
62333 +            pConnectMsg->ServiceID = pConnectReq->ServiceID;
62334 +            pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
62335 +                /* check caller if it wants to transfer meta data */
62336 +            if ((pConnectReq->pMetaData != NULL) &&
62337 +                (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
62338 +                    /* copy meta data into message buffer (after header ) */
62339 +                A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
62340 +                         pConnectReq->pMetaData,
62341 +                         pConnectReq->MetaDataLength);
62342 +                pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
62343 +            }
62344 +
62345 +            SET_HTC_PACKET_INFO_TX(pSendPacket,
62346 +                                   NULL,
62347 +                                   (A_UINT8 *)pConnectMsg,
62348 +                                   sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
62349 +                                   ENDPOINT_0,
62350 +                                   HTC_SERVICE_TX_PACKET_TAG);
62351 +
62352 +                /* we want synchronous operation */
62353 +            pSendPacket->Completion = NULL;
62354 +
62355 +            status = HTCIssueSend(target,pSendPacket,0);
62356 +
62357 +            if (A_FAILED(status)) {
62358 +                break;
62359 +            }
62360 +
62361 +                /* wait for response */
62362 +            status = HTCWaitforControlMessage(target, &pRecvPacket);
62363 +
62364 +            if (A_FAILED(status)) {
62365 +                break;
62366 +            }
62367 +                /* we controlled the buffer creation so it has to be properly aligned */
62368 +            pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
62369 +
62370 +            if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
62371 +                (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
62372 +                    /* this message is not valid */
62373 +                AR_DEBUG_ASSERT(FALSE);
62374 +                status = A_EPROTO;
62375 +                break;
62376 +            }
62377 +
62378 +            pConnectResp->ConnectRespCode = pResponseMsg->Status;
62379 +                /* check response status */
62380 +            if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
62381 +                AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
62382 +                    (" Target failed service 0x%X connect request (status:%d)\n",
62383 +                                pResponseMsg->ServiceID, pResponseMsg->Status));
62384 +                status = A_EPROTO;
62385 +                break;
62386 +            }
62387 +
62388 +            assignedEndpoint = pResponseMsg->EndpointID;
62389 +            maxMsgSize = pResponseMsg->MaxMsgSize;
62390 +
62391 +            if ((pConnectResp->pMetaData != NULL) &&
62392 +                (pResponseMsg->ServiceMetaLength > 0) &&
62393 +                (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
62394 +                    /* caller supplied a buffer and the target responded with data */
62395 +                int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
62396 +                    /* copy the meta data */
62397 +                A_MEMCPY(pConnectResp->pMetaData,
62398 +                         ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
62399 +                         copyLength);
62400 +                pConnectResp->ActualLength = copyLength;
62401 +            }
62402 +
62403 +        }
62404 +
62405 +            /* the rest of these are parameter checks so set the error status */
62406 +        status = A_EPROTO;
62407 +
62408 +        if (assignedEndpoint >= ENDPOINT_MAX) {
62409 +            AR_DEBUG_ASSERT(FALSE);
62410 +            break;
62411 +        }
62412 +
62413 +        if (0 == maxMsgSize) {
62414 +            AR_DEBUG_ASSERT(FALSE);
62415 +            break;
62416 +        }
62417 +
62418 +        pEndpoint = &target->EndPoint[assignedEndpoint];
62419 +
62420 +        if (pEndpoint->ServiceID != 0) {
62421 +            /* endpoint already in use! */
62422 +            AR_DEBUG_ASSERT(FALSE);
62423 +            break;
62424 +        }
62425 +
62426 +            /* return assigned endpoint to caller */
62427 +        pConnectResp->Endpoint = assignedEndpoint;
62428 +        pConnectResp->MaxMsgLength = maxMsgSize;
62429 +
62430 +            /* setup the endpoint */
62431 +        pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
62432 +        pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
62433 +        pEndpoint->MaxMsgLength = maxMsgSize;
62434 +            /* copy all the callbacks */
62435 +        pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
62436 +        INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
62437 +        INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
62438 +            /* set the credit distribution info for this endpoint, this information is
62439 +             * passed back to the credit distribution callback function */
62440 +        pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
62441 +        pEndpoint->CreditDist.pHTCReserved = pEndpoint;
62442 +        pEndpoint->CreditDist.Endpoint = assignedEndpoint;
62443 +        pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
62444 +        pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
62445 +
62446 +        if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
62447 +            pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
62448 +        }
62449 +
62450 +        status = A_OK;
62451 +
62452 +    } while (FALSE);
62453 +
62454 +    if (pSendPacket != NULL) {
62455 +        HTC_FREE_CONTROL_TX(target,pSendPacket);
62456 +    }
62457 +
62458 +    if (pRecvPacket != NULL) {
62459 +        HTC_FREE_CONTROL_RX(target,pRecvPacket);
62460 +    }
62461 +
62462 +    AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
62463 +
62464 +    return status;
62465 +}
62466 +
62467 +static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist)
62468 +{
62469 +    HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry;
62470 +
62471 +    if (NULL == target->EpCreditDistributionListHead) {
62472 +        target->EpCreditDistributionListHead = pEpDist;
62473 +        pEpDist->pNext = NULL;
62474 +        pEpDist->pPrev = NULL;
62475 +        return;
62476 +    }
62477 +
62478 +        /* queue to the end of the list, this does not have to be very
62479 +         * fast since this list is built at startup time */
62480 +    pCurEntry = target->EpCreditDistributionListHead;
62481 +
62482 +    while (pCurEntry) {
62483 +        pLastEntry = pCurEntry;
62484 +        pCurEntry = pCurEntry->pNext;
62485 +    }
62486 +
62487 +    pLastEntry->pNext = pEpDist;
62488 +    pEpDist->pPrev = pLastEntry;
62489 +    pEpDist->pNext = NULL;
62490 +}
62491 +
62492 +
62493 +
62494 +/* default credit init callback */
62495 +static void HTCDefaultCreditInit(void                     *Context,
62496 +                                 HTC_ENDPOINT_CREDIT_DIST *pEPList,
62497 +                                 int                      TotalCredits)
62498 +{
62499 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
62500 +    int                      totalEps = 0;
62501 +    int                      creditsPerEndpoint;
62502 +
62503 +    pCurEpDist = pEPList;
62504 +        /* first run through the list and figure out how many endpoints we are dealing with */
62505 +    while (pCurEpDist != NULL) {
62506 +        pCurEpDist = pCurEpDist->pNext;
62507 +        totalEps++;
62508 +    }
62509 +
62510 +        /* even distribution */
62511 +    creditsPerEndpoint = TotalCredits/totalEps;
62512 +
62513 +    pCurEpDist = pEPList;
62514 +        /* run through the list and set minimum and normal credits and
62515 +         * provide the endpoint with some credits to start */
62516 +    while (pCurEpDist != NULL) {
62517 +
62518 +        if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
62519 +                /* too many endpoints and not enough credits */
62520 +            AR_DEBUG_ASSERT(FALSE);
62521 +            break;
62522 +        }
62523 +            /* our minimum is set for at least 1 max message */
62524 +        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
62525 +            /* this value is ignored by our credit alg, since we do
62526 +             * not dynamically adjust credits, this is the policy of
62527 +             * the "default" credit distribution, something simple and easy */
62528 +        pCurEpDist->TxCreditsNorm = 0xFFFF;
62529 +            /* give the endpoint minimum credits */
62530 +        pCurEpDist->TxCredits = creditsPerEndpoint;
62531 +        pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
62532 +        pCurEpDist = pCurEpDist->pNext;
62533 +    }
62534 +
62535 +}
62536 +
62537 +/* default credit distribution callback, NOTE, this callback holds the TX lock */
62538 +void HTCDefaultCreditDist(void                     *Context,
62539 +                          HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
62540 +                          HTC_CREDIT_DIST_REASON   Reason)
62541 +{
62542 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
62543 +
62544 +    if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
62545 +        pCurEpDist = pEPDistList;
62546 +            /* simple distribution */
62547 +        while (pCurEpDist != NULL) {
62548 +            if (pCurEpDist->TxCreditsToDist > 0) {
62549 +                    /* just give the endpoint back the credits */
62550 +                pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
62551 +                pCurEpDist->TxCreditsToDist = 0;
62552 +            }
62553 +            pCurEpDist = pCurEpDist->pNext;
62554 +        }
62555 +    }
62556 +
62557 +    /* note we do not need to handle the other reason codes as this is a very
62558 +     * simple distribution scheme, no need to seek for more credits or handle inactivity */
62559 +}
62560 +
62561 +void HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
62562 +                              void                     *pCreditDistContext,
62563 +                              HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
62564 +                              HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
62565 +                              HTC_SERVICE_ID           ServicePriorityOrder[],
62566 +                              int                      ListLength)
62567 +{
62568 +    HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
62569 +    int i;
62570 +    int ep;
62571 +
62572 +    if (CreditInitFunc != NULL) {
62573 +            /* caller has supplied their own distribution functions */
62574 +        target->InitCredits = CreditInitFunc;
62575 +        AR_DEBUG_ASSERT(CreditDistFunc != NULL);
62576 +        target->DistributeCredits = CreditDistFunc;
62577 +        target->pCredDistContext = pCreditDistContext;
62578 +    } else {
62579 +        /* caller wants HTC to do distribution */
62580 +        /* if caller wants service to handle distributions then
62581 +         * it must set both of these to NULL! */
62582 +        AR_DEBUG_ASSERT(CreditDistFunc == NULL);
62583 +        target->InitCredits = HTCDefaultCreditInit;
62584 +        target->DistributeCredits = HTCDefaultCreditDist;
62585 +        target->pCredDistContext = target;
62586 +    }
62587 +
62588 +        /* always add HTC control endpoint first, we only expose the list after the
62589 +         * first one, this is added for TX queue checking */
62590 +    AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
62591 +
62592 +        /* build the list of credit distribution structures in priority order
62593 +         * supplied by the caller, these will follow endpoint 0 */
62594 +    for (i = 0; i < ListLength; i++) {
62595 +            /* match services with endpoints and add the endpoints to the distribution list
62596 +             * in FIFO order */
62597 +        for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
62598 +            if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
62599 +                    /* queue this one to the list */
62600 +                AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
62601 +                break;
62602 +            }
62603 +        }
62604 +        AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
62605 +    }
62606 +
62607 +}
62608 Index: linux-2.6.28/drivers/ar6000/include/a_config.h
62609 ===================================================================
62610 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62611 +++ linux-2.6.28/drivers/ar6000/include/a_config.h      2009-01-02 00:01:56.000000000 +0100
62612 @@ -0,0 +1,27 @@
62613 +#ifndef _A_CONFIG_H_
62614 +#define _A_CONFIG_H_
62615 +/*
62616 + * Copyright (c) 2004-2005 Atheros Communications Inc.
62617 + * All rights reserved.
62618 + *
62619 + *
62620 + *  This program is free software; you can redistribute it and/or modify
62621 + *  it under the terms of the GNU General Public License version 2 as
62622 + *  published by the Free Software Foundation;
62623 + *
62624 + *  Software distributed under the License is distributed on an "AS
62625 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62626 + *  implied. See the License for the specific language governing
62627 + *  rights and limitations under the License.
62628 + *
62629 + *
62630 + *
62631 + */
62632 +
62633 +/*
62634 + * This file contains software configuration options that enables
62635 + * specific software "features"
62636 + */
62637 +#include "../ar6000/config_linux.h"
62638 +
62639 +#endif
62640 Index: linux-2.6.28/drivers/ar6000/include/a_debug.h
62641 ===================================================================
62642 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62643 +++ linux-2.6.28/drivers/ar6000/include/a_debug.h       2009-01-02 00:01:56.000000000 +0100
62644 @@ -0,0 +1,41 @@
62645 +#ifndef _A_DEBUG_H_
62646 +#define _A_DEBUG_H_
62647 +/*
62648 + * Copyright (c) 2004-2006 Atheros Communications Inc.
62649 + * All rights reserved.
62650 + *
62651 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62652 + * All rights reserved.
62653 + *
62654 + *
62655 + *  This program is free software; you can redistribute it and/or modify
62656 + *  it under the terms of the GNU General Public License version 2 as
62657 + *  published by the Free Software Foundation;
62658 + *
62659 + *  Software distributed under the License is distributed on an "AS
62660 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62661 + *  implied. See the License for the specific language governing
62662 + *  rights and limitations under the License.
62663 + *
62664 + *
62665 + *
62666 + */
62667 +
62668 +#include <a_types.h>
62669 +#include <a_osapi.h>
62670 +
62671 +#define DBG_INFO               0x00000001
62672 +#define DBG_ERROR              0x00000002
62673 +#define DBG_WARNING            0x00000004
62674 +#define DBG_SDIO               0x00000008
62675 +#define DBG_HIF                        0x00000010
62676 +#define DBG_HTC                        0x00000020
62677 +#define DBG_WMI                        0x00000040
62678 +#define DBG_WMI2               0x00000080
62679 +#define DBG_DRIVER             0x00000100
62680 +
62681 +#define DBG_DEFAULTS   (DBG_ERROR|DBG_WARNING)
62682 +
62683 +#include "../ar6000/debug_linux.h"
62684 +
62685 +#endif
62686 Index: linux-2.6.28/drivers/ar6000/include/a_drv_api.h
62687 ===================================================================
62688 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62689 +++ linux-2.6.28/drivers/ar6000/include/a_drv_api.h     2009-01-02 00:01:56.000000000 +0100
62690 @@ -0,0 +1,185 @@
62691 +#ifndef _A_DRV_API_H_
62692 +#define _A_DRV_API_H_
62693 +/*
62694 + * Copyright (c) 2004-2006 Atheros Communications Inc.
62695 + * All rights reserved.
62696 + *
62697 + *
62698 + *  This program is free software; you can redistribute it and/or modify
62699 + *  it under the terms of the GNU General Public License version 2 as
62700 + *  published by the Free Software Foundation;
62701 + *
62702 + *  Software distributed under the License is distributed on an "AS
62703 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62704 + *  implied. See the License for the specific language governing
62705 + *  rights and limitations under the License.
62706 + *
62707 + *
62708 + *
62709 + */
62710 +
62711 +#ifdef __cplusplus
62712 +extern "C" {
62713 +#endif
62714 +
62715 +/****************************************************************************/
62716 +/****************************************************************************/
62717 +/**                                                                        **/
62718 +/** WMI related hooks                                                      **/
62719 +/**                                                                        **/
62720 +/****************************************************************************/
62721 +/****************************************************************************/
62722 +
62723 +#include <ar6000_api.h>
62724 +
62725 +#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList)  \
62726 +       ar6000_channelList_rx((devt), (numChan), (chanList))
62727 +
62728 +#define A_WMI_SET_NUMDATAENDPTS(devt, num)     \
62729 +       ar6000_set_numdataendpts((devt), (num))
62730 +
62731 +#define A_WMI_CONTROL_TX(devt, osbuf, streamID)        \
62732 +       ar6000_control_tx((devt), (osbuf), (streamID))
62733 +
62734 +#define A_WMI_TARGETSTATS_EVENT(devt, pStats)  \
62735 +       ar6000_targetStats_event((devt), (pStats))
62736 +
62737 +#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \
62738 +       ar6000_scanComplete_event((devt), (status))
62739 +
62740 +#ifdef CONFIG_HOST_DSET_SUPPORT
62741 +
62742 +#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg)      \
62743 +       ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
62744 +
62745 +#define A_WMI_DSET_CLOSE(devt, access_cookie)  \
62746 +       ar6000_dset_close((devt), (access_cookie))
62747 +
62748 +#endif
62749 +
62750 +#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
62751 +       ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
62752 +
62753 +#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
62754 +       ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
62755 +
62756 +#define A_WMI_REGDOMAIN_EVENT(devt, regCode)   \
62757 +       ar6000_regDomain_event((devt), (regCode))
62758 +
62759 +#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \
62760 +       ar6000_neighborReport_event((devt), (numAps), (info))
62761 +
62762 +#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus)     \
62763 +       ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
62764 +
62765 +#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast)  \
62766 +       ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
62767 +
62768 +#define A_WMI_BITRATE_RX(devt, rateKbps)       \
62769 +       ar6000_bitrate_rx((devt), (rateKbps))
62770 +
62771 +#define A_WMI_TXPWR_RX(devt, txPwr)    \
62772 +       ar6000_txPwr_rx((devt), (txPwr))
62773 +
62774 +#define A_WMI_READY_EVENT(devt, datap, phyCap) \
62775 +       ar6000_ready_event((devt), (datap), (phyCap))
62776 +
62777 +#define A_WMI_DBGLOG_INIT_DONE(ar) \
62778 +        ar6000_dbglog_init_done(ar);
62779 +
62780 +#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi)   \
62781 +       ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
62782 +
62783 +#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal)       \
62784 +       ar6000_reportError_event((devt), (errorVal))
62785 +
62786 +#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
62787 +       ar6000_roam_tbl_event((devt), (pTbl))
62788 +
62789 +#define A_WMI_ROAM_DATA_EVENT(devt, p) \
62790 +       ar6000_roam_data_event((devt), (p))
62791 +
62792 +#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters)   \
62793 +       ar6000_wow_list_event((devt), (num_filters), (wow_filters))
62794 +
62795 +#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion)  \
62796 +       ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
62797 +
62798 +#define A_WMI_IPTOS_TO_USERPRIORITY(pkt)    \
62799 +       ar6000_iptos_to_userPriority((pkt))
62800 +
62801 +#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list)    \
62802 +       ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list))
62803 +
62804 +#ifdef CONFIG_HOST_GPIO_SUPPORT
62805 +
62806 +#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
62807 +       ar6000_gpio_intr_rx((intr_mask), (input_values))
62808 +
62809 +#define A_WMI_GPIO_DATA_RX(reg_id, value) \
62810 +       ar6000_gpio_data_rx((reg_id), (value))
62811 +
62812 +#define A_WMI_GPIO_ACK_RX() \
62813 +       ar6000_gpio_ack_rx()
62814 +
62815 +#endif
62816 +
62817 +#ifdef SEND_EVENT_TO_APP
62818 +
62819 +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
62820 +       ar6000_send_event_to_app((ar), (eventId), (datap), (len))
62821 +
62822 +#else
62823 +
62824 +#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
62825 +
62826 +#endif
62827 +
62828 +#ifdef CONFIG_HOST_TCMD_SUPPORT
62829 +#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
62830 +       ar6000_tcmd_rx_report_event((devt), (results), (len))
62831 +#endif
62832 +
62833 +#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source)    \
62834 +    ar6000_hbChallengeResp_event((devt), (cookie), (source))
62835 +
62836 +#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
62837 +       ar6000_tx_retry_err_event((devt))
62838 +
62839 +#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
62840 +       ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
62841 +
62842 +#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
62843 +       ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
62844 +
62845 +#define A_WMI_RATEMASK_RX(devt, ratemask) \
62846 +       ar6000_ratemask_rx((devt), (ratemask))
62847 +
62848 +#define A_WMI_KEEPALIVE_RX(devt, configured)    \
62849 +        ar6000_keepalive_rx((devt), (configured))
62850 +
62851 +#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len)   \
62852 +        ar6000_bssInfo_event_rx((ar), (datap), (len))
62853 +
62854 +#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
62855 +        ar6000_dbglog_event((ar), (dropped), (buffer), (length));
62856 +
62857 +#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
62858 +    ar6000_indicate_tx_activity((devt),(trafficClass), TRUE)
62859 +
62860 +#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
62861 +    ar6000_indicate_tx_activity((devt),(trafficClass), FALSE)
62862 +
62863 +/****************************************************************************/
62864 +/****************************************************************************/
62865 +/**                                                                        **/
62866 +/** HTC related hooks                                                      **/
62867 +/**                                                                        **/
62868 +/****************************************************************************/
62869 +/****************************************************************************/
62870 +
62871 +#ifdef __cplusplus
62872 +}
62873 +#endif
62874 +
62875 +#endif
62876 Index: linux-2.6.28/drivers/ar6000/include/a_drv.h
62877 ===================================================================
62878 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62879 +++ linux-2.6.28/drivers/ar6000/include/a_drv.h 2009-01-02 00:01:56.000000000 +0100
62880 @@ -0,0 +1,28 @@
62881 +#ifndef _A_DRV_H_
62882 +#define _A_DRV_H_
62883 +/*
62884 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_drv.h#1 $
62885 + *
62886 + * This file contains the definitions of the basic atheros data types.
62887 + * It is used to map the data types in atheros files to a platform specific
62888 + * type.
62889 + *
62890 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
62891 + *
62892 + *
62893 + *  This program is free software; you can redistribute it and/or modify
62894 + *  it under the terms of the GNU General Public License version 2 as
62895 + *  published by the Free Software Foundation;
62896 + *
62897 + *  Software distributed under the License is distributed on an "AS
62898 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62899 + *  implied. See the License for the specific language governing
62900 + *  rights and limitations under the License.
62901 + *
62902 + *
62903 + *
62904 + */
62905 +
62906 +#include "../ar6000/athdrv_linux.h"
62907 +
62908 +#endif /* _ADRV_H_ */
62909 Index: linux-2.6.28/drivers/ar6000/include/a_osapi.h
62910 ===================================================================
62911 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62912 +++ linux-2.6.28/drivers/ar6000/include/a_osapi.h       2009-01-02 00:01:56.000000000 +0100
62913 @@ -0,0 +1,28 @@
62914 +#ifndef _A_OSAPI_H_
62915 +#define _A_OSAPI_H_
62916 +/*
62917 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_osapi.h#1 $
62918 + *
62919 + * This file contains the definitions of the basic atheros data types.
62920 + * It is used to map the data types in atheros files to a platform specific
62921 + * type.
62922 + *
62923 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
62924 + *
62925 + *
62926 + *  This program is free software; you can redistribute it and/or modify
62927 + *  it under the terms of the GNU General Public License version 2 as
62928 + *  published by the Free Software Foundation;
62929 + *
62930 + *  Software distributed under the License is distributed on an "AS
62931 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62932 + *  implied. See the License for the specific language governing
62933 + *  rights and limitations under the License.
62934 + *
62935 + *
62936 + *
62937 + */
62938 +
62939 +#include "../ar6000/osapi_linux.h"
62940 +
62941 +#endif /* _OSAPI_H_ */
62942 Index: linux-2.6.28/drivers/ar6000/include/ar6000_api.h
62943 ===================================================================
62944 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62945 +++ linux-2.6.28/drivers/ar6000/include/ar6000_api.h    2009-01-02 00:01:56.000000000 +0100
62946 @@ -0,0 +1,29 @@
62947 +#ifndef _AR6000_API_H_
62948 +#define _AR6000_API_H_
62949 +/*
62950 + * Copyright (c) 2004-2005 Atheros Communications Inc.
62951 + * All rights reserved.
62952 + *
62953 + * This file contains the API to access the OS dependent atheros host driver
62954 + * by the WMI or WLAN generic modules.
62955 + *
62956 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/ar6000_api.h#1 $
62957 + *
62958 + *
62959 + *  This program is free software; you can redistribute it and/or modify
62960 + *  it under the terms of the GNU General Public License version 2 as
62961 + *  published by the Free Software Foundation;
62962 + *
62963 + *  Software distributed under the License is distributed on an "AS
62964 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62965 + *  implied. See the License for the specific language governing
62966 + *  rights and limitations under the License.
62967 + *
62968 + *
62969 + *
62970 + */
62971 +
62972 +#include "../ar6000/ar6xapi_linux.h"
62973 +
62974 +#endif /* _AR6000_API_H */
62975 +
62976 Index: linux-2.6.28/drivers/ar6000/include/ar6000_diag.h
62977 ===================================================================
62978 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
62979 +++ linux-2.6.28/drivers/ar6000/include/ar6000_diag.h   2009-01-02 00:01:56.000000000 +0100
62980 @@ -0,0 +1,38 @@
62981 +/*
62982 + *
62983 + * Copyright (c) 2004-2007 Atheros Communications Inc.
62984 + * All rights reserved.
62985 + *
62986 + *
62987 + *  This program is free software; you can redistribute it and/or modify
62988 + *  it under the terms of the GNU General Public License version 2 as
62989 + *  published by the Free Software Foundation;
62990 + *
62991 + *  Software distributed under the License is distributed on an "AS
62992 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
62993 + *  implied. See the License for the specific language governing
62994 + *  rights and limitations under the License.
62995 + *
62996 + *
62997 + *
62998 + */
62999 +
63000 +#ifndef AR6000_DIAG_H_
63001 +#define AR6000_DIAG_H_
63002 +
63003 +
63004 +A_STATUS
63005 +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
63006 +
63007 +A_STATUS
63008 +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
63009 +
63010 +A_STATUS
63011 +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
63012 +                    A_UCHAR *data, A_UINT32 length);
63013 +
63014 +A_STATUS
63015 +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
63016 +                     A_UCHAR *data, A_UINT32 length);
63017 +
63018 +#endif /*AR6000_DIAG_H_*/
63019 Index: linux-2.6.28/drivers/ar6000/include/AR6001_regdump.h
63020 ===================================================================
63021 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63022 +++ linux-2.6.28/drivers/ar6000/include/AR6001_regdump.h        2009-01-02 00:01:56.000000000 +0100
63023 @@ -0,0 +1,100 @@
63024 +/*
63025 + * Copyright (c) 2006 Atheros Communications Inc.
63026 + * All rights reserved.
63027 + *
63028 + * $ATH_LICENSE_HOSTSDK0_C$
63029 + *
63030 + */
63031 +
63032 +#ifndef __AR6000_REGDUMP_H__
63033 +#define __AR6000_REGDUMP_H__
63034 +
63035 +#if !defined(__ASSEMBLER__)
63036 +/*
63037 + * Target CPU state at the time of failure is reflected
63038 + * in a register dump, which the Host can fetch through
63039 + * the diagnostic window.
63040 + */
63041 +
63042 +struct MIPS_exception_frame_s {
63043 +    A_UINT32 pc;        /* Program Counter */
63044 +    A_UINT32 at;        /* MIPS General Purpose registers */
63045 +    A_UINT32 v0;
63046 +    A_UINT32 v1;
63047 +    A_UINT32 a0;
63048 +    A_UINT32 a1;
63049 +    A_UINT32 a2;
63050 +    A_UINT32 a3;
63051 +    A_UINT32 t0;
63052 +    A_UINT32 t1;
63053 +    A_UINT32 t2;
63054 +    A_UINT32 t3;
63055 +    A_UINT32 t4;
63056 +    A_UINT32 t5;
63057 +    A_UINT32 t6;
63058 +    A_UINT32 t7;
63059 +    A_UINT32 s0;
63060 +    A_UINT32 s1;
63061 +    A_UINT32 s2;
63062 +    A_UINT32 s3;
63063 +    A_UINT32 s4;
63064 +    A_UINT32 s5;
63065 +    A_UINT32 s6;
63066 +    A_UINT32 s7;
63067 +    A_UINT32 t8;
63068 +    A_UINT32 t9;
63069 +    A_UINT32 k0;
63070 +    A_UINT32 k1;
63071 +    A_UINT32 gp;
63072 +    A_UINT32 sp;
63073 +    A_UINT32 s8;
63074 +    A_UINT32 ra;
63075 +    A_UINT32 cause; /* Selected coprocessor regs */
63076 +    A_UINT32 status;
63077 +};
63078 +typedef struct MIPS_exception_frame_s CPU_exception_frame_t;
63079 +
63080 +#endif
63081 +
63082 +/*
63083 + * Offsets into MIPS_exception_frame structure, for use in assembler code
63084 + * MUST MATCH C STRUCTURE ABOVE
63085 + */
63086 +#define RD_pc           0
63087 +#define RD_at           1
63088 +#define RD_v0           2
63089 +#define RD_v1           3
63090 +#define RD_a0           4
63091 +#define RD_a1           5
63092 +#define RD_a2           6
63093 +#define RD_a3           7
63094 +#define RD_t0           8
63095 +#define RD_t1           9
63096 +#define RD_t2           10
63097 +#define RD_t3           11
63098 +#define RD_t4           12
63099 +#define RD_t5           13
63100 +#define RD_t6           14
63101 +#define RD_t7           15
63102 +#define RD_s0           16
63103 +#define RD_s1           17
63104 +#define RD_s2           18
63105 +#define RD_s3           19
63106 +#define RD_s4           20
63107 +#define RD_s5           21
63108 +#define RD_s6           22
63109 +#define RD_s7           23
63110 +#define RD_t8           24
63111 +#define RD_t9           25
63112 +#define RD_k0           26
63113 +#define RD_k1           27
63114 +#define RD_gp           28
63115 +#define RD_sp           29
63116 +#define RD_s8           30
63117 +#define RD_ra           31
63118 +#define RD_cause        32
63119 +#define RD_status       33
63120 +
63121 +#define RD_SIZE         (34*4) /* Space for this number of words */
63122 +
63123 +#endif /* __AR6000_REGDUMP_H__ */
63124 Index: linux-2.6.28/drivers/ar6000/include/AR6Khwreg.h
63125 ===================================================================
63126 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63127 +++ linux-2.6.28/drivers/ar6000/include/AR6Khwreg.h     2009-01-02 00:01:56.000000000 +0100
63128 @@ -0,0 +1,147 @@
63129 +/*
63130 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63131 + * All rights reserved.
63132 + *
63133 + * $ATH_LICENSE_HOSTSDK0_C$
63134 + *
63135 + * This file contains the definitions for AR6001 registers
63136 + * that may be directly manipulated by Host software.
63137 + */
63138 +
63139 +#ifndef __AR6KHWREG_H__
63140 +#define __AR6KHWREG_H__
63141 +
63142 +#ifdef __cplusplus
63143 +extern "C" {
63144 +#endif
63145 +
63146 +/* Host registers */
63147 +#define HOST_INT_STATUS_ADDRESS                  0x00000400
63148 +#define CPU_INT_STATUS_ADDRESS                   0x00000401
63149 +#define ERROR_INT_STATUS_ADDRESS                 0x00000402
63150 +#define INT_STATUS_ENABLE_ADDRESS                0x00000418
63151 +#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
63152 +#define COUNT_ADDRESS                            0x00000420
63153 +#define COUNT_DEC_ADDRESS                        0x00000440
63154 +#define WINDOW_DATA_ADDRESS                      0x00000474
63155 +#define WINDOW_WRITE_ADDR_ADDRESS                0x00000478
63156 +#define WINDOW_READ_ADDR_ADDRESS                 0x0000047c
63157 +
63158 +/* Target addresses */
63159 +#define RESET_CONTROL_ADDRESS                    0x0c000000
63160 +#define MC_REMAP_VALID_ADDRESS                   0x0c004080
63161 +#define MC_REMAP_SIZE_ADDRESS                    0x0c004100
63162 +#define MC_REMAP_COMPARE_ADDRESS                 0x0c004180
63163 +#define MC_REMAP_TARGET_ADDRESS                  0x0c004200
63164 +#define LOCAL_COUNT_ADDRESS                      0x0c014080
63165 +#define LOCAL_SCRATCH_ADDRESS                    0x0c0140c0
63166 +
63167 +
63168 +#define INT_STATUS_ENABLE_ERROR_MSB              7
63169 +#define INT_STATUS_ENABLE_ERROR_LSB              7
63170 +#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
63171 +#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
63172 +#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
63173 +
63174 +#define INT_STATUS_ENABLE_CPU_MSB                6
63175 +#define INT_STATUS_ENABLE_CPU_LSB                6
63176 +#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
63177 +#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
63178 +#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
63179 +
63180 +#define INT_STATUS_ENABLE_COUNTER_MSB            4
63181 +#define INT_STATUS_ENABLE_COUNTER_LSB            4
63182 +#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
63183 +#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
63184 +#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
63185 +
63186 +#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
63187 +#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
63188 +#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
63189 +#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
63190 +#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
63191 +
63192 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
63193 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
63194 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
63195 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
63196 +#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
63197 +
63198 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
63199 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
63200 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
63201 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
63202 +#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
63203 +
63204 +
63205 +#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
63206 +#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
63207 +#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
63208 +#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
63209 +#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
63210 +
63211 +#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
63212 +#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
63213 +#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
63214 +#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
63215 +#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
63216 +
63217 +#define ERROR_INT_STATUS_WAKEUP_MSB              2
63218 +#define ERROR_INT_STATUS_WAKEUP_LSB              2
63219 +#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
63220 +#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
63221 +#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
63222 +
63223 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
63224 +#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
63225 +#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
63226 +#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
63227 +#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
63228 +
63229 +#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
63230 +#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
63231 +#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
63232 +#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
63233 +#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
63234 +
63235 +#define HOST_INT_STATUS_ERROR_MSB                7
63236 +#define HOST_INT_STATUS_ERROR_LSB                7
63237 +#define HOST_INT_STATUS_ERROR_MASK               0x00000080
63238 +#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
63239 +#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
63240 +
63241 +#define HOST_INT_STATUS_CPU_MSB                  6
63242 +#define HOST_INT_STATUS_CPU_LSB                  6
63243 +#define HOST_INT_STATUS_CPU_MASK                 0x00000040
63244 +#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
63245 +#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
63246 +
63247 +#define HOST_INT_STATUS_COUNTER_MSB              4
63248 +#define HOST_INT_STATUS_COUNTER_LSB              4
63249 +#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
63250 +#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
63251 +#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
63252 +
63253 +#define RESET_CONTROL_WARM_RST_MSB               7
63254 +#define RESET_CONTROL_WARM_RST_LSB               7
63255 +#define RESET_CONTROL_WARM_RST_MASK              0x00000080
63256 +#define RESET_CONTROL_WARM_RST_GET(x)            (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
63257 +#define RESET_CONTROL_WARM_RST_SET(x)            (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
63258 +
63259 +#define RESET_CONTROL_COLD_RST_MSB               8
63260 +#define RESET_CONTROL_COLD_RST_LSB               8
63261 +#define RESET_CONTROL_COLD_RST_MASK              0x00000100
63262 +#define RESET_CONTROL_COLD_RST_GET(x)            (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
63263 +#define RESET_CONTROL_COLD_RST_SET(x)            (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
63264 +
63265 +#define RESET_CAUSE_LAST_MSB                     2
63266 +#define RESET_CAUSE_LAST_LSB                     0
63267 +#define RESET_CAUSE_LAST_MASK                    0x00000007
63268 +#define RESET_CAUSE_LAST_GET(x)                  (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
63269 +#define RESET_CAUSE_LAST_SET(x)                  (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
63270 +
63271 +#ifdef __cplusplus
63272 +}
63273 +#endif
63274 +
63275 +#endif /* __AR6KHWREG_H__ */
63276 Index: linux-2.6.28/drivers/ar6000/include/AR6K_version.h
63277 ===================================================================
63278 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63279 +++ linux-2.6.28/drivers/ar6000/include/AR6K_version.h  2009-01-02 00:01:56.000000000 +0100
63280 @@ -0,0 +1,36 @@
63281 +#define __VER_MAJOR_ 2
63282 +#define __VER_MINOR_ 0
63283 +#define __VER_PATCH_ 0
63284 +
63285 +
63286 +/*
63287 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63288 + * All rights reserved.
63289 + *
63290 + * $ATH_LICENSE_HOSTSDK0_C$
63291 + *
63292 + * The makear6ksdk script (used for release builds) modifies the following line.
63293 + */
63294 +#define __BUILD_NUMBER_ 18
63295 +
63296 +
63297 +/* Format of the version number. */
63298 +#define VER_MAJOR_BIT_OFFSET           28
63299 +#define VER_MINOR_BIT_OFFSET           24
63300 +#define VER_PATCH_BIT_OFFSET           16
63301 +#define VER_BUILD_NUM_BIT_OFFSET       0
63302 +
63303 +
63304 +/*
63305 + * The version has the following format:
63306 + * Bits 28-31: Major version
63307 + * Bits 24-27: Minor version
63308 + * Bits 16-23: Patch version
63309 + * Bits 0-15:  Build number (automatically generated during build process )
63310 + * E.g. Build 1.1.3.7 would be represented as 0x11030007.
63311 + *
63312 + * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
63313 + */
63314 +#define AR6K_SW_VERSION        ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
63315 +
63316 +
63317 Index: linux-2.6.28/drivers/ar6000/include/AR6K_version.h.NEW
63318 ===================================================================
63319 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63320 +++ linux-2.6.28/drivers/ar6000/include/AR6K_version.h.NEW      2009-01-02 00:01:56.000000000 +0100
63321 @@ -0,0 +1,36 @@
63322 +#define __VER_MAJOR_ 2
63323 +#define __VER_MINOR_ 0
63324 +#define __VER_PATCH_ 0
63325 +
63326 +
63327 +/*
63328 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63329 + * All rights reserved.
63330 + *
63331 + * $ATH_LICENSE_HOSTSDK0_C$
63332 + *
63333 + * The makear6ksdk script (used for release builds) modifies the following line.
63334 + */
63335 +#define __BUILD_NUMBER_ 18
63336 +
63337 +
63338 +/* Format of the version number. */
63339 +#define VER_MAJOR_BIT_OFFSET           28
63340 +#define VER_MINOR_BIT_OFFSET           24
63341 +#define VER_PATCH_BIT_OFFSET           16
63342 +#define VER_BUILD_NUM_BIT_OFFSET       0
63343 +
63344 +
63345 +/*
63346 + * The version has the following format:
63347 + * Bits 28-31: Major version
63348 + * Bits 24-27: Minor version
63349 + * Bits 16-23: Patch version
63350 + * Bits 0-15:  Build number (automatically generated during build process )
63351 + * E.g. Build 1.1.3.7 would be represented as 0x11030007.
63352 + *
63353 + * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
63354 + */
63355 +#define AR6K_SW_VERSION        ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
63356 +
63357 +
63358 Index: linux-2.6.28/drivers/ar6000/include/athdefs.h
63359 ===================================================================
63360 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63361 +++ linux-2.6.28/drivers/ar6000/include/athdefs.h       2009-01-02 00:01:56.000000000 +0100
63362 @@ -0,0 +1,85 @@
63363 +#ifndef __ATHDEFS_H__
63364 +#define __ATHDEFS_H__
63365 +
63366 +/*
63367 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63368 + * All rights reserved.
63369 + *
63370 + * $ATH_LICENSE_HOSTSDK0_C$
63371 + *
63372 + * This file contains definitions that may be used across both
63373 + * Host and Target software.  Nothing here is module-dependent
63374 + * or platform-dependent.
63375 + */
63376 +
63377 +/*
63378 + * Generic error codes that can be used by hw, sta, ap, sim, dk
63379 + * and any other environments. Since these are enums, feel free to
63380 + * add any more codes that you need.
63381 + */
63382 +
63383 +typedef enum {
63384 +    A_ERROR = -1,               /* Generic error return */
63385 +    A_OK = 0,                   /* success */
63386 +                                /* Following values start at 1 */
63387 +    A_DEVICE_NOT_FOUND,         /* not able to find PCI device */
63388 +    A_NO_MEMORY,                /* not able to allocate memory, not available */
63389 +    A_MEMORY_NOT_AVAIL,         /* memory region is not free for mapping */
63390 +    A_NO_FREE_DESC,             /* no free descriptors available */
63391 +    A_BAD_ADDRESS,              /* address does not match descriptor */
63392 +    A_WIN_DRIVER_ERROR,         /* used in NT_HW version, if problem at init */
63393 +    A_REGS_NOT_MAPPED,          /* registers not correctly mapped */
63394 +    A_EPERM,                    /* Not superuser */
63395 +    A_EACCES,                   /* Access denied */
63396 +    A_ENOENT,                   /* No such entry, search failed, etc. */
63397 +    A_EEXIST,                   /* The object already exists (can't create) */
63398 +    A_EFAULT,                   /* Bad address fault */
63399 +    A_EBUSY,                    /* Object is busy */
63400 +    A_EINVAL,                   /* Invalid parameter */
63401 +    A_EMSGSIZE,                 /* Inappropriate message buffer length */
63402 +    A_ECANCELED,                /* Operation canceled */
63403 +    A_ENOTSUP,                  /* Operation not supported */
63404 +    A_ECOMM,                    /* Communication error on send */
63405 +    A_EPROTO,                   /* Protocol error */
63406 +    A_ENODEV,                   /* No such device */
63407 +    A_EDEVNOTUP,                /* device is not UP */
63408 +    A_NO_RESOURCE,              /* No resources for requested operation */
63409 +    A_HARDWARE,                 /* Hardware failure */
63410 +    A_PENDING,                  /* Asynchronous routine; will send up results la
63411 +ter (typically in callback) */
63412 +    A_EBADCHANNEL,              /* The channel cannot be used */
63413 +    A_DECRYPT_ERROR,            /* Decryption error */
63414 +    A_PHY_ERROR,                /* RX PHY error */
63415 +    A_CONSUMED                  /* Object was consumed */
63416 +} A_STATUS;
63417 +
63418 +#define A_SUCCESS(x)        (x == A_OK)
63419 +#define A_FAILED(x)         (!A_SUCCESS(x))
63420 +
63421 +#ifndef TRUE
63422 +#define TRUE 1
63423 +#endif
63424 +
63425 +#ifndef FALSE
63426 +#define FALSE 0
63427 +#endif
63428 +
63429 +/*
63430 + * The following definition is WLAN specific definition
63431 + */
63432 +typedef enum {
63433 +    MODE_11A = 0,   /* 11a Mode */
63434 +    MODE_11G = 1,   /* 11g + 11b Mode */
63435 +    MODE_11B = 2,   /* 11b Mode */
63436 +    MODE_11GONLY = 3, /* 11g only Mode */
63437 +    MODE_UNKNOWN = 4,
63438 +    MODE_MAX = 4
63439 +} WLAN_PHY_MODE;
63440 +
63441 +typedef enum {
63442 +    WLAN_11A_CAPABILITY   = 1,
63443 +    WLAN_11G_CAPABILITY   = 2,
63444 +    WLAN_11AG_CAPABILITY  = 3,
63445 +}WLAN_CAPABILITY;
63446 +
63447 +#endif /* __ATHDEFS_H__ */
63448 Index: linux-2.6.28/drivers/ar6000/include/athdrv.h
63449 ===================================================================
63450 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63451 +++ linux-2.6.28/drivers/ar6000/include/athdrv.h        2009-01-02 00:01:56.000000000 +0100
63452 @@ -0,0 +1,32 @@
63453 +/*
63454 + * Copyright (c) 2004-2006 Atheros Communications Inc.
63455 + * All rights reserved.
63456 + *
63457 + *
63458 + *
63459 + *  This program is free software; you can redistribute it and/or modify
63460 + *  it under the terms of the GNU General Public License version 2 as
63461 + *  published by the Free Software Foundation;
63462 + *
63463 + *  Software distributed under the License is distributed on an "AS
63464 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63465 + *  implied. See the License for the specific language governing
63466 + *  rights and limitations under the License.
63467 + *
63468 + *
63469 + *
63470 + */
63471 +
63472 +#ifndef _ATHDRV_H_
63473 +#define _ATHDRV_H_
63474 +
63475 +#ifdef __cplusplus
63476 +extern "C" {
63477 +#endif
63478 +
63479 +
63480 +#ifdef __cplusplus
63481 +}
63482 +#endif
63483 +
63484 +#endif /* _ATHDRV_H_ */
63485 Index: linux-2.6.28/drivers/ar6000/include/athendpack.h
63486 ===================================================================
63487 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63488 +++ linux-2.6.28/drivers/ar6000/include/athendpack.h    2009-01-02 00:01:56.000000000 +0100
63489 @@ -0,0 +1,41 @@
63490 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
63491 + * @file: athendpack.h
63492 + *
63493 + * @abstract: end compiler-specific structure packing
63494 + *
63495 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63496 + * All rights reserved.
63497 + *
63498 + *
63499 + *  This program is free software; you can redistribute it and/or modify
63500 + *  it under the terms of the GNU General Public License version 2 as
63501 + *  published by the Free Software Foundation;
63502 + *
63503 + *  Software distributed under the License is distributed on an "AS
63504 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63505 + *  implied. See the License for the specific language governing
63506 + *  rights and limitations under the License.
63507 + *
63508 + *
63509 + *
63510 + */
63511 +#ifdef VXWORKS
63512 +#endif /* VXWORKS */
63513 +
63514 +#ifdef LINUX
63515 +#endif /* LINUX */
63516 +
63517 +#ifdef QNX
63518 +#endif /* QNX */
63519 +
63520 +#ifdef INTEGRITY
63521 +#include "integrity/athendpack_integrity.h"
63522 +#endif /* INTEGRITY */
63523 +
63524 +#ifdef NUCLEUS
63525 +#endif /* NUCLEUS */
63526 +
63527 +#ifdef UNDER_CE
63528 +#include "../os/wince/include/athendpack_wince.h"
63529 +#endif /* WINCE */
63530 +
63531 Index: linux-2.6.28/drivers/ar6000/include/athstartpack.h
63532 ===================================================================
63533 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63534 +++ linux-2.6.28/drivers/ar6000/include/athstartpack.h  2009-01-02 00:01:56.000000000 +0100
63535 @@ -0,0 +1,42 @@
63536 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
63537 + * @file: athstartpack.h
63538 + *
63539 + * @abstract: start compiler-specific structure packing
63540 + *
63541 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63542 + * All rights reserved.
63543 + *
63544 + *
63545 + *  This program is free software; you can redistribute it and/or modify
63546 + *  it under the terms of the GNU General Public License version 2 as
63547 + *  published by the Free Software Foundation;
63548 + *
63549 + *  Software distributed under the License is distributed on an "AS
63550 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63551 + *  implied. See the License for the specific language governing
63552 + *  rights and limitations under the License.
63553 + *
63554 + *
63555 + *
63556 + */
63557 +
63558 +#ifdef VXWORKS
63559 +#endif /* VXWORKS */
63560 +
63561 +#ifdef LINUX
63562 +#endif /* LINUX */
63563 +
63564 +#ifdef QNX
63565 +#endif /* QNX */
63566 +
63567 +#ifdef INTEGRITY
63568 +#include "integrity/athstartpack_integrity.h"
63569 +#endif /* INTEGRITY */
63570 +
63571 +#ifdef NUCLEUS
63572 +#endif /* NUCLEUS */
63573 +
63574 +#ifdef UNDER_CE
63575 +#include "../os/wince/include/athstartpack_wince.h"
63576 +#endif /* WINCE */
63577 +
63578 Index: linux-2.6.28/drivers/ar6000/include/a_types.h
63579 ===================================================================
63580 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63581 +++ linux-2.6.28/drivers/ar6000/include/a_types.h       2009-01-02 00:01:56.000000000 +0100
63582 @@ -0,0 +1,28 @@
63583 +#ifndef _A_TYPES_H_
63584 +#define _A_TYPES_H_
63585 +/*
63586 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_types.h#1 $
63587 + *
63588 + * This file contains the definitions of the basic atheros data types.
63589 + * It is used to map the data types in atheros files to a platform specific
63590 + * type.
63591 + *
63592 + * Copyright 2003-2005 Atheros Communications, Inc.,  All Rights Reserved.
63593 + *
63594 + *
63595 + *  This program is free software; you can redistribute it and/or modify
63596 + *  it under the terms of the GNU General Public License version 2 as
63597 + *  published by the Free Software Foundation;
63598 + *
63599 + *  Software distributed under the License is distributed on an "AS
63600 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63601 + *  implied. See the License for the specific language governing
63602 + *  rights and limitations under the License.
63603 + *
63604 + *
63605 + *
63606 + */
63607 +
63608 +#include "../ar6000/athtypes_linux.h"
63609 +
63610 +#endif /* _ATHTYPES_H_ */
63611 Index: linux-2.6.28/drivers/ar6000/include/bmi.h
63612 ===================================================================
63613 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63614 +++ linux-2.6.28/drivers/ar6000/include/bmi.h   2009-01-02 00:01:56.000000000 +0100
63615 @@ -0,0 +1,100 @@
63616 +#ifndef _BMI_H_
63617 +#define _BMI_H_
63618 +/*
63619 + * Copyright (c) 2004-2005 Atheros Communications Inc.
63620 + * All rights reserved.
63621 + *
63622 + *
63623 + *  This program is free software; you can redistribute it and/or modify
63624 + *  it under the terms of the GNU General Public License version 2 as
63625 + *  published by the Free Software Foundation;
63626 + *
63627 + *  Software distributed under the License is distributed on an "AS
63628 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63629 + *  implied. See the License for the specific language governing
63630 + *  rights and limitations under the License.
63631 + *
63632 + *
63633 + *
63634 + * BMI declarations and prototypes
63635 + */
63636 +
63637 +#ifdef __cplusplus
63638 +extern "C" {
63639 +#endif /* __cplusplus */
63640 +
63641 +/* Header files */
63642 +#include "a_config.h"
63643 +#include "athdefs.h"
63644 +#include "a_types.h"
63645 +#include "hif.h"
63646 +#include "a_osapi.h"
63647 +#include "bmi_msg.h"
63648 +
63649 +void
63650 +BMIInit(void);
63651 +
63652 +A_STATUS
63653 +BMIDone(HIF_DEVICE *device);
63654 +
63655 +A_STATUS
63656 +BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
63657 +
63658 +A_STATUS
63659 +BMIReadMemory(HIF_DEVICE *device,
63660 +              A_UINT32 address,
63661 +              A_UCHAR *buffer,
63662 +              A_UINT32 length);
63663 +
63664 +A_STATUS
63665 +BMIWriteMemory(HIF_DEVICE *device,
63666 +               A_UINT32 address,
63667 +               A_UCHAR *buffer,
63668 +               A_UINT32 length);
63669 +
63670 +A_STATUS
63671 +BMIExecute(HIF_DEVICE *device,
63672 +           A_UINT32 address,
63673 +           A_UINT32 *param);
63674 +
63675 +A_STATUS
63676 +BMISetAppStart(HIF_DEVICE *device,
63677 +               A_UINT32 address);
63678 +
63679 +A_STATUS
63680 +BMIReadSOCRegister(HIF_DEVICE *device,
63681 +                   A_UINT32 address,
63682 +                   A_UINT32 *param);
63683 +
63684 +A_STATUS
63685 +BMIWriteSOCRegister(HIF_DEVICE *device,
63686 +                    A_UINT32 address,
63687 +                    A_UINT32 param);
63688 +
63689 +A_STATUS
63690 +BMIrompatchInstall(HIF_DEVICE *device,
63691 +                   A_UINT32 ROM_addr,
63692 +                   A_UINT32 RAM_addr,
63693 +                   A_UINT32 nbytes,
63694 +                   A_UINT32 do_activate,
63695 +                   A_UINT32 *patch_id);
63696 +
63697 +A_STATUS
63698 +BMIrompatchUninstall(HIF_DEVICE *device,
63699 +                     A_UINT32 rompatch_id);
63700 +
63701 +A_STATUS
63702 +BMIrompatchActivate(HIF_DEVICE *device,
63703 +                    A_UINT32 rompatch_count,
63704 +                    A_UINT32 *rompatch_list);
63705 +
63706 +A_STATUS
63707 +BMIrompatchDeactivate(HIF_DEVICE *device,
63708 +                      A_UINT32 rompatch_count,
63709 +                      A_UINT32 *rompatch_list);
63710 +
63711 +#ifdef __cplusplus
63712 +}
63713 +#endif
63714 +
63715 +#endif /* _BMI_H_ */
63716 Index: linux-2.6.28/drivers/ar6000/include/bmi_msg.h
63717 ===================================================================
63718 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63719 +++ linux-2.6.28/drivers/ar6000/include/bmi_msg.h       2009-01-02 00:01:56.000000000 +0100
63720 @@ -0,0 +1,199 @@
63721 +#ifndef __BMI_MSG_H__
63722 +#define __BMI_MSG_H__
63723 +/*
63724 + *
63725 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63726 + * All rights reserved.
63727 + *
63728 + *
63729 + *  This program is free software; you can redistribute it and/or modify
63730 + *  it under the terms of the GNU General Public License version 2 as
63731 + *  published by the Free Software Foundation;
63732 + *
63733 + *  Software distributed under the License is distributed on an "AS
63734 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63735 + *  implied. See the License for the specific language governing
63736 + *  rights and limitations under the License.
63737 + *
63738 + *
63739 + *
63740 + */
63741 +
63742 +/*
63743 + * Bootloader Messaging Interface (BMI)
63744 + *
63745 + * BMI is a very simple messaging interface used during initialization
63746 + * to read memory, write memory, execute code, and to define an
63747 + * application entry PC.
63748 + *
63749 + * It is used to download an application to AR6K, to provide
63750 + * patches to code that is already resident on AR6K, and generally
63751 + * to examine and modify state.  The Host has an opportunity to use
63752 + * BMI only once during bootup.  Once the Host issues a BMI_DONE
63753 + * command, this opportunity ends.
63754 + *
63755 + * The Host writes BMI requests to mailbox0, and reads BMI responses
63756 + * from mailbox0.   BMI requests all begin with a command
63757 + * (see below for specific commands), and are followed by
63758 + * command-specific data.
63759 + *
63760 + * Flow control:
63761 + * The Host can only issue a command once the Target gives it a
63762 + * "BMI Command Credit", using AR6K Counter #4.  As soon as the
63763 + * Target has completed a command, it issues another BMI Command
63764 + * Credit (so the Host can issue the next command).
63765 + *
63766 + * BMI handles all required Target-side cache flushing.
63767 + */
63768 +
63769 +
63770 +/* Maximum data size used for BMI transfers */
63771 +#define BMI_DATASZ_MAX                     32
63772 +
63773 +/* BMI Commands */
63774 +
63775 +#define BMI_NO_COMMAND                      0
63776 +
63777 +#define BMI_DONE                            1
63778 +        /*
63779 +         * Semantics: Host is done using BMI
63780 +         * Request format:
63781 +         *    A_UINT32      command (BMI_DONE)
63782 +         * Response format: none
63783 +         */
63784 +
63785 +#define BMI_READ_MEMORY                     2
63786 +        /*
63787 +         * Semantics: Host reads AR6K memory
63788 +         * Request format:
63789 +         *    A_UINT32      command (BMI_READ_MEMORY)
63790 +         *    A_UINT32      address
63791 +         *    A_UINT32      length, at most BMI_DATASZ_MAX
63792 +         * Response format:
63793 +         *    A_UINT8       data[length]
63794 +         */
63795 +
63796 +#define BMI_WRITE_MEMORY                    3
63797 +        /*
63798 +         * Semantics: Host writes AR6K memory
63799 +         * Request format:
63800 +         *    A_UINT32       command (BMI_WRITE_MEMORY)
63801 +         *    A_UINT32      address
63802 +         *    A_UINT32      length, at most BMI_DATASZ_MAX
63803 +         *    A_UINT8       data[length]
63804 +         * Response format: none
63805 +         */
63806 +
63807 +#define BMI_EXECUTE                         4
63808 +        /*
63809 +         * Semantics: Causes AR6K to execute code
63810 +         * Request format:
63811 +         *    A_UINT32      command (BMI_EXECUTE)
63812 +         *    A_UINT32      address
63813 +         *    A_UINT32      parameter
63814 +         * Response format:
63815 +         *    A_UINT32      return value
63816 +         */
63817 +
63818 +#define BMI_SET_APP_START                   5
63819 +        /*
63820 +         * Semantics: Set Target application starting address
63821 +         * Request format:
63822 +         *    A_UINT32      command (BMI_SET_APP_START)
63823 +         *    A_UINT32      address
63824 +         * Response format: none
63825 +         */
63826 +
63827 +#define BMI_READ_SOC_REGISTER               6
63828 +        /*
63829 +         * Semantics: Read a 32-bit Target SOC register.
63830 +         * Request format:
63831 +         *    A_UINT32      command (BMI_READ_REGISTER)
63832 +         *    A_UINT32      address
63833 +         * Response format:
63834 +         *    A_UINT32      value
63835 +         */
63836 +
63837 +#define BMI_WRITE_SOC_REGISTER              7
63838 +        /*
63839 +         * Semantics: Write a 32-bit Target SOC register.
63840 +         * Request format:
63841 +         *    A_UINT32      command (BMI_WRITE_REGISTER)
63842 +         *    A_UINT32      address
63843 +         *    A_UINT32      value
63844 +         *
63845 +         * Response format: none
63846 +         */
63847 +
63848 +#define BMI_GET_TARGET_ID                  8
63849 +#define BMI_GET_TARGET_INFO                8
63850 +        /*
63851 +         * Semantics: Fetch the 4-byte Target information
63852 +         * Request format:
63853 +         *    A_UINT32      command (BMI_GET_TARGET_ID/INFO)
63854 +         * Response format1 (old firmware):
63855 +         *    A_UINT32      TargetVersionID
63856 +         * Response format2 (newer firmware):
63857 +         *    A_UINT32      TARGET_VERSION_SENTINAL
63858 +         *    struct bmi_target_info;
63859 +         */
63860 +
63861 +struct bmi_target_info {
63862 +    A_UINT32 target_info_byte_count; /* size of this structure */
63863 +    A_UINT32 target_ver;             /* Target Version ID */
63864 +    A_UINT32 target_type;            /* Target type */
63865 +};
63866 +#define TARGET_VERSION_SENTINAL 0xffffffff
63867 +#define TARGET_TYPE_AR6001 1
63868 +#define TARGET_TYPE_AR6002 2
63869 +
63870 +
63871 +#define BMI_ROMPATCH_INSTALL               9
63872 +        /*
63873 +         * Semantics: Install a ROM Patch.
63874 +         * Request format:
63875 +         *    A_UINT32      command (BMI_ROMPATCH_INSTALL)
63876 +         *    A_UINT32      Target ROM Address
63877 +         *    A_UINT32      Target RAM Address
63878 +         *    A_UINT32      Size, in bytes
63879 +         *    A_UINT32      Activate? 1-->activate;
63880 +         *                            0-->install but do not activate
63881 +         * Response format:
63882 +         *    A_UINT32      PatchID
63883 +         */
63884 +
63885 +#define BMI_ROMPATCH_UNINSTALL             10
63886 +        /*
63887 +         * Semantics: Uninstall a previously-installed ROM Patch,
63888 +         * automatically deactivating, if necessary.
63889 +         * Request format:
63890 +         *    A_UINT32      command (BMI_ROMPATCH_UNINSTALL)
63891 +         *    A_UINT32      PatchID
63892 +         *
63893 +         * Response format: none
63894 +         */
63895 +
63896 +#define BMI_ROMPATCH_ACTIVATE              11
63897 +        /*
63898 +         * Semantics: Activate a list of previously-installed ROM Patches.
63899 +         * Request format:
63900 +         *    A_UINT32      command (BMI_ROMPATCH_ACTIVATE)
63901 +         *    A_UINT32      rompatch_count
63902 +         *    A_UINT32      PatchID[rompatch_count]
63903 +         *
63904 +         * Response format: none
63905 +         */
63906 +
63907 +#define BMI_ROMPATCH_DEACTIVATE            12
63908 +        /*
63909 +         * Semantics: Deactivate a list of active ROM Patches.
63910 +         * Request format:
63911 +         *    A_UINT32      command (BMI_ROMPATCH_DEACTIVATE)
63912 +         *    A_UINT32      rompatch_count
63913 +         *    A_UINT32      PatchID[rompatch_count]
63914 +         *
63915 +         * Response format: none
63916 +         */
63917 +
63918 +
63919 +#endif /* __BMI_MSG_H__ */
63920 Index: linux-2.6.28/drivers/ar6000/include/common_drv.h
63921 ===================================================================
63922 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63923 +++ linux-2.6.28/drivers/ar6000/include/common_drv.h    2009-01-02 00:01:56.000000000 +0100
63924 @@ -0,0 +1,61 @@
63925 +/*
63926 + *
63927 + * Copyright (c) 2004-2007 Atheros Communications Inc.
63928 + * All rights reserved.
63929 + *
63930 + *
63931 + *  This program is free software; you can redistribute it and/or modify
63932 + *  it under the terms of the GNU General Public License version 2 as
63933 + *  published by the Free Software Foundation;
63934 + *
63935 + *  Software distributed under the License is distributed on an "AS
63936 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
63937 + *  implied. See the License for the specific language governing
63938 + *  rights and limitations under the License.
63939 + *
63940 + *
63941 + *
63942 + */
63943 +
63944 +
63945 +#ifndef COMMON_DRV_H_
63946 +#define COMMON_DRV_H_
63947 +
63948 +#include "hif.h"
63949 +#include "htc_packet.h"
63950 +
63951 +
63952 +
63953 +/* structure that is the state information for the default credit distribution callback
63954 + * drivers should instantiate (zero-init as well) this structure in their driver instance
63955 + * and pass it as a context to the HTC credit distribution functions */
63956 +typedef struct _COMMON_CREDIT_STATE_INFO {
63957 +    int TotalAvailableCredits;      /* total credits in the system at startup */
63958 +    int CurrentFreeCredits;         /* credits available in the pool that have not been
63959 +                                       given out to endpoints */
63960 +    HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist;  /* pointer to the lowest priority endpoint dist struct */
63961 +} COMMON_CREDIT_STATE_INFO;
63962 +
63963 +
63964 +/* HTC TX packet tagging definitions */
63965 +#define AR6K_CONTROL_PKT_TAG    HTC_TX_PACKET_TAG_USER_DEFINED
63966 +#define AR6K_DATA_PKT_TAG       (AR6K_CONTROL_PKT_TAG + 1)
63967 +
63968 +#ifdef __cplusplus
63969 +extern "C" {
63970 +#endif
63971 +
63972 +/* OS-independent APIs */
63973 +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo);
63974 +A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
63975 +A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
63976 +A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,  A_UCHAR *data, A_UINT32 length);
63977 +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
63978 +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
63979 +A_STATUS ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice);
63980 +
63981 +#ifdef __cplusplus
63982 +}
63983 +#endif
63984 +
63985 +#endif /*COMMON_DRV_H_*/
63986 Index: linux-2.6.28/drivers/ar6000/include/dbglog_api.h
63987 ===================================================================
63988 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
63989 +++ linux-2.6.28/drivers/ar6000/include/dbglog_api.h    2009-01-02 00:01:56.000000000 +0100
63990 @@ -0,0 +1,46 @@
63991 +#ifndef _DBGLOG_API_H_
63992 +#define _DBGLOG_API_H_
63993 +/*
63994 + * Copyright (c) 2004-2006 Atheros Communications Inc.
63995 + * All rights reserved.
63996 + *
63997 + *
63998 + *  This program is free software; you can redistribute it and/or modify
63999 + *  it under the terms of the GNU General Public License version 2 as
64000 + *  published by the Free Software Foundation;
64001 + *
64002 + *  Software distributed under the License is distributed on an "AS
64003 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64004 + *  implied. See the License for the specific language governing
64005 + *  rights and limitations under the License.
64006 + *
64007 + *
64008 + *
64009 + * This file contains host side debug primitives.
64010 + */
64011 +
64012 +#ifdef __cplusplus
64013 +extern "C" {
64014 +#endif
64015 +
64016 +#include "dbglog.h"
64017 +
64018 +#define DBGLOG_HOST_LOG_BUFFER_SIZE            DBGLOG_LOG_BUFFER_SIZE
64019 +
64020 +#define DBGLOG_GET_DBGID(arg) \
64021 +    ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
64022 +
64023 +#define DBGLOG_GET_MODULEID(arg) \
64024 +    ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
64025 +
64026 +#define DBGLOG_GET_NUMARGS(arg) \
64027 +    ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
64028 +
64029 +#define DBGLOG_GET_TIMESTAMP(arg) \
64030 +    ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
64031 +
64032 +#ifdef __cplusplus
64033 +}
64034 +#endif
64035 +
64036 +#endif /* _DBGLOG_API_H_ */
64037 Index: linux-2.6.28/drivers/ar6000/include/dbglog.h
64038 ===================================================================
64039 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64040 +++ linux-2.6.28/drivers/ar6000/include/dbglog.h        2009-01-02 00:01:56.000000000 +0100
64041 @@ -0,0 +1,107 @@
64042 +/*
64043 + * Copyright (c) 2004-2007 Atheros Communications Inc.
64044 + * All rights reserved.
64045 + *
64046 + * $ATH_LICENSE_HOSTSDK0_C$
64047 + *
64048 + * This file contains the definitions and data structures associated with
64049 + * the log based debug mechanism.
64050 + *
64051 + */
64052 +
64053 +#ifndef _DBGLOG_H_
64054 +#define _DBGLOG_H_
64055 +
64056 +#ifdef __cplusplus
64057 +extern "C" {
64058 +#endif
64059 +
64060 +#define DBGLOG_TIMESTAMP_OFFSET          0
64061 +#define DBGLOG_TIMESTAMP_MASK            0x0000FFFF /* Bit 0-15. Contains bit
64062 +                                                       8-23 of the LF0 timer */
64063 +#define DBGLOG_DBGID_OFFSET              16
64064 +#define DBGLOG_DBGID_MASK                0x03FF0000 /* Bit 16-25 */
64065 +#define DBGLOG_DBGID_NUM_MAX             256 /* Upper limit is width of mask */
64066 +
64067 +#define DBGLOG_MODULEID_OFFSET           26
64068 +#define DBGLOG_MODULEID_MASK             0x3C000000 /* Bit 26-29 */
64069 +#define DBGLOG_MODULEID_NUM_MAX          16 /* Upper limit is width of mask */
64070 +
64071 +/*
64072 + * Please ensure that the definition of any new module intrduced is captured
64073 + * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The
64074 + * structure is required for the parser to correctly pick up the values for
64075 + * different modules.
64076 + */
64077 +#define DBGLOG_MODULEID_START
64078 +#define DBGLOG_MODULEID_INF                   0
64079 +#define DBGLOG_MODULEID_WMI                   1
64080 +#define DBGLOG_MODULEID_CSERV                 2
64081 +#define DBGLOG_MODULEID_PM                    3
64082 +#define DBGLOG_MODULEID_TXRX_MGMTBUF          4
64083 +#define DBGLOG_MODULEID_TXRX_TXBUF            5
64084 +#define DBGLOG_MODULEID_TXRX_RXBUF            6
64085 +#define DBGLOG_MODULEID_WOW                   7
64086 +#define DBGLOG_MODULEID_WHAL                  8
64087 +#define DBGLOG_MODULEID_END
64088 +
64089 +#define DBGLOG_NUM_ARGS_OFFSET             30
64090 +#define DBGLOG_NUM_ARGS_MASK               0xC0000000 /* Bit 30-31 */
64091 +#define DBGLOG_NUM_ARGS_MAX                2 /* Upper limit is width of mask */
64092 +
64093 +#define DBGLOG_MODULE_LOG_ENABLE_OFFSET    0
64094 +#define DBGLOG_MODULE_LOG_ENABLE_MASK      0x0000FFFF
64095 +
64096 +#define DBGLOG_REPORTING_ENABLED_OFFSET    16
64097 +#define DBGLOG_REPORTING_ENABLED_MASK      0x00010000
64098 +
64099 +#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
64100 +#define DBGLOG_TIMESTAMP_RESOLUTION_MASK   0x000E0000
64101 +
64102 +#define DBGLOG_REPORT_SIZE_OFFSET          20
64103 +#define DBGLOG_REPORT_SIZE_MASK            0x3FF00000
64104 +
64105 +#define DBGLOG_LOG_BUFFER_SIZE             1500
64106 +#define DBGLOG_DBGID_DEFINITION_LEN_MAX    64
64107 +
64108 +struct dbglog_buf_s {
64109 +    struct dbglog_buf_s *next;
64110 +    A_INT8              *buffer;
64111 +    A_UINT32             bufsize;
64112 +    A_UINT32             length;
64113 +    A_UINT32             count;
64114 +    A_UINT32             free;
64115 +};
64116 +
64117 +struct dbglog_hdr_s {
64118 +    struct dbglog_buf_s *dbuf;
64119 +    A_UINT32             dropped;
64120 +};
64121 +
64122 +struct dbglog_config_s {
64123 +    A_UINT32                    cfgvalid; /* Mask with valid config bits */
64124 +    union {
64125 +        /* TODO: Take care of endianness */
64126 +        struct {
64127 +            A_UINT32            mmask:16; /* Mask of modules with logging on */
64128 +            A_UINT32            rep:1; /* Reporting enabled or not */
64129 +            A_UINT32            tsr:3; /* Time stamp resolution. Def: 1 ms */
64130 +            A_UINT32            size:10; /* Report size in number of messages */
64131 +            A_UINT32            reserved:2;
64132 +        } dbglog_config;
64133 +
64134 +        A_UINT32                value;
64135 +    } u;
64136 +};
64137 +
64138 +#define cfgmmask                   u.dbglog_config.mmask
64139 +#define cfgrep                     u.dbglog_config.rep
64140 +#define cfgtsr                     u.dbglog_config.tsr
64141 +#define cfgsize                    u.dbglog_config.size
64142 +#define cfgvalue                   u.value
64143 +
64144 +#ifdef __cplusplus
64145 +}
64146 +#endif
64147 +
64148 +#endif /* _DBGLOG_H_ */
64149 Index: linux-2.6.28/drivers/ar6000/include/dbglog_id.h
64150 ===================================================================
64151 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64152 +++ linux-2.6.28/drivers/ar6000/include/dbglog_id.h     2009-01-02 00:01:56.000000000 +0100
64153 @@ -0,0 +1,307 @@
64154 +/*
64155 + *
64156 + * Copyright (c) 2004-2007 Atheros Communications Inc.
64157 + * All rights reserved.
64158 + *
64159 + * $ATH_LICENSE_HOSTSDK0_C$
64160 + *
64161 + * This file contains the definitions of the debug identifiers for different
64162 + * modules.
64163 + *
64164 + */
64165 +
64166 +#ifndef _DBGLOG_ID_H_
64167 +#define _DBGLOG_ID_H_
64168 +
64169 +#ifdef __cplusplus
64170 +extern "C" {
64171 +#endif
64172 +
64173 +/*
64174 + * The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
64175 + * Please ensure that the definition of any new debugid introduced is captured
64176 + * between the <MODULE>_DBGID_DEFINITION_START and
64177 + * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the
64178 + * parser to correctly pick up the values for different debug identifiers.
64179 + */
64180 +
64181 +/* INF debug identifier definitions */
64182 +#define INF_DBGID_DEFINITION_START
64183 +#define INF_ASSERTION_FAILED                          1
64184 +#define INF_TARGET_ID                                 2
64185 +#define INF_DBGID_DEFINITION_END
64186 +
64187 +/* WMI debug identifier definitions */
64188 +#define WMI_DBGID_DEFINITION_START
64189 +#define WMI_CMD_RX_XTND_PKT_TOO_SHORT                 1
64190 +#define WMI_EXTENDED_CMD_NOT_HANDLED                  2
64191 +#define WMI_CMD_RX_PKT_TOO_SHORT                      3
64192 +#define WMI_CALLING_WMI_EXTENSION_FN                  4
64193 +#define WMI_CMD_NOT_HANDLED                           5
64194 +#define WMI_IN_SYNC                                   6
64195 +#define WMI_TARGET_WMI_SYNC_CMD                       7
64196 +#define WMI_SET_SNR_THRESHOLD_PARAMS                  8
64197 +#define WMI_SET_RSSI_THRESHOLD_PARAMS                 9
64198 +#define WMI_SET_LQ_TRESHOLD_PARAMS                   10
64199 +#define WMI_TARGET_CREATE_PSTREAM_CMD                11
64200 +#define WMI_WI_DTM_INUSE                             12
64201 +#define WMI_TARGET_DELETE_PSTREAM_CMD                13
64202 +#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD       14
64203 +#define WMI_TARGET_GET_BIT_RATE_CMD                  15
64204 +#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS       16
64205 +#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD        17
64206 +#define WMI_TARGET_GET_TX_PWR_CMD                    18
64207 +#define WMI_FREE_EVBUF_WMIBUF                        19
64208 +#define WMI_FREE_EVBUF_DATABUF                       20
64209 +#define WMI_FREE_EVBUF_BADFLAG                       21
64210 +#define WMI_HTC_RX_ERROR_DATA_PACKET                 22
64211 +#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX             23
64212 +#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT      24
64213 +#define WMI_SENDING_READY_EVENT                      25
64214 +#define WMI_SETPOWER_MDOE_TO_MAXPERF                 26
64215 +#define WMI_SETPOWER_MDOE_TO_REC                     27
64216 +#define WMI_BSSINFO_EVENT_FROM                       28
64217 +#define WMI_TARGET_GET_STATS_CMD                     29
64218 +#define WMI_SENDING_SCAN_COMPLETE_EVENT              30
64219 +#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT        31
64220 +#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT       32
64221 +#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT     33
64222 +#define WMI_SENDING_ERROR_REPORT_EVENT               34
64223 +#define WMI_SENDING_CAC_EVENT                        35
64224 +#define WMI_TARGET_GET_ROAM_TABLE_CMD                36
64225 +#define WMI_TARGET_GET_ROAM_DATA_CMD                 37
64226 +#define WMI_SENDING_GPIO_INTR_EVENT                  38
64227 +#define WMI_SENDING_GPIO_ACK_EVENT                   39
64228 +#define WMI_SENDING_GPIO_DATA_EVENT                  40
64229 +#define WMI_CMD_RX                                   41
64230 +#define WMI_CMD_RX_XTND                              42
64231 +#define WMI_EVENT_SEND                               43
64232 +#define WMI_EVENT_SEND_XTND                          44
64233 +#define WMI_DBGID_DEFINITION_END
64234 +
64235 +/* CSERV debug identifier definitions */
64236 +#define CSERV_DBGID_DEFINITION_START
64237 +#define CSERV_BEGIN_SCAN1                             1
64238 +#define CSERV_BEGIN_SCAN2                             2
64239 +#define CSERV_END_SCAN1                               3
64240 +#define CSERV_END_SCAN2                               4
64241 +#define CSERV_CHAN_SCAN_START                         5
64242 +#define CSERV_CHAN_SCAN_STOP                          6
64243 +#define CSERV_CHANNEL_OPPPORTUNITY                    7
64244 +#define CSERV_NC_TIMEOUT                              8
64245 +#define CSERV_BACK_HOME                              10
64246 +#define CSERV_CHMGR_CH_CALLBACK1                     11
64247 +#define CSERV_CHMGR_CH_CALLBACK2                     12
64248 +#define CSERV_CHMGR_CH_CALLBACK3                     13
64249 +#define CSERV_SET_SCAN_PARAMS1                       14
64250 +#define CSERV_SET_SCAN_PARAMS2                       15
64251 +#define CSERV_SET_SCAN_PARAMS3                       16
64252 +#define CSERV_SET_SCAN_PARAMS4                       17
64253 +#define CSERV_ABORT_SCAN                             18
64254 +#define CSERV_NEWSTATE                               19
64255 +#define CSERV_MINCHMGR_OP_END                        20
64256 +#define CSERV_CHMGR_OP_END                           21
64257 +#define CSERV_DISCONNECT_TIMEOUT                     22
64258 +#define CSERV_ROAM_TIMEOUT                           23
64259 +#define CSERV_FORCE_SCAN1                            24
64260 +#define CSERV_FORCE_SCAN2                            25
64261 +#define CSERV_FORCE_SCAN3                            26
64262 +#define CSERV_UTIL_TIMEOUT                           27
64263 +#define CSERV_RSSIPOLLER                             28
64264 +#define CSERV_RETRY_CONNECT_TIMEOUT                  29
64265 +#define CSERV_RSSIINDBMPOLLER                        30
64266 +#define CSERV_BGSCAN_ENABLE                          31
64267 +#define CSERV_BGSCAN_DISABLE                         32
64268 +#define CSERV_WLAN_START_SCAN_CMD1                   33
64269 +#define CSERV_WLAN_START_SCAN_CMD2                   34
64270 +#define CSERV_WLAN_START_SCAN_CMD3                   35
64271 +#define CSERV_START_SCAN_CMD                         36
64272 +#define CSERV_START_FORCE_SCAN                       37
64273 +#define CSERV_NEXT_CHAN                              38
64274 +#define CSERV_SET_REGCODE                            39
64275 +#define CSERV_START_ADHOC                            40
64276 +#define CSERV_ADHOC_AT_HOME                          41
64277 +#define CSERV_OPT_AT_HOME                            42
64278 +#define CSERV_WLAN_CONNECT_CMD                       43
64279 +#define CSERV_WLAN_RECONNECT_CMD                     44
64280 +#define CSERV_WLAN_DISCONNECT_CMD                    45
64281 +#define CSERV_BSS_CHANGE_CHANNEL                     46
64282 +#define CSERV_BEACON_RX                              47
64283 +#define CSERV_KEEPALIVE_CHECK                        48
64284 +#define CSERV_RC_BEGIN_SCAN                          49
64285 +#define CSERV_RC_SCAN_START                          50
64286 +#define CSERV_RC_SCAN_STOP                           51
64287 +#define CSERV_RC_NEXT                                52
64288 +#define CSERV_RC_SCAN_END                            53
64289 +#define CSERV_PROBE_CALLBACK                         54
64290 +#define CSERV_ROAM1                                  55
64291 +#define CSERV_ROAM2                                  56
64292 +#define CSERV_ROAM3                                  57
64293 +#define CSERV_CONNECT_EVENT                          58
64294 +#define CSERV_DISCONNECT_EVENT                       59
64295 +#define CSERV_BMISS_HANDLER1                         60
64296 +#define CSERV_BMISS_HANDLER2                         61
64297 +#define CSERV_BMISS_HANDLER3                         62
64298 +#define CSERV_LOWRSSI_HANDLER                        63
64299 +#define CSERV_WLAN_SET_PMKID_CMD                     64
64300 +#define CSERV_RECONNECT_REQUEST                      65
64301 +#define CSERV_KEYSPLUMBED_EVENT                      66
64302 +#define CSERV_NEW_REG                                67
64303 +#define CSERV_SET_RSSI_THOLD                         68
64304 +#define CSERV_RSSITHRESHOLDCHECK                     69
64305 +#define CSERV_RSSIINDBMTHRESHOLDCHECK                70
64306 +#define CSERV_WLAN_SET_OPT_CMD1                      71
64307 +#define CSERV_WLAN_SET_OPT_CMD2                      72
64308 +#define CSERV_WLAN_SET_OPT_CMD3                      73
64309 +#define CSERV_WLAN_SET_OPT_CMD4                      74
64310 +#define CSERV_SCAN_CONNECT_STOP                      75
64311 +#define CSERV_BMISS_HANDLER4                         76
64312 +#define CSERV_INITIALIZE_TIMER                       77
64313 +#define CSERV_ARM_TIMER                              78
64314 +#define CSERV_DISARM_TIMER                           79
64315 +#define CSERV_UNINITIALIZE_TIMER                     80
64316 +#define CSERV_DISCONNECT_EVENT2                      81
64317 +#define CSERV_SCAN_CONNECT_START                     82
64318 +#define CSERV_BSSINFO_MEMORY_ALLOC_FAILED            83
64319 +#define CSERV_SET_SCAN_PARAMS5                       84
64320 +#define CSERV_DBGID_DEFINITION_END
64321 +
64322 +/* TXRX debug identifier definitions */
64323 +#define TXRX_TXBUF_DBGID_DEFINITION_START
64324 +#define TXRX_TXBUF_ALLOCATE_BUF                      1
64325 +#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX                 2
64326 +#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ                  3
64327 +#define TXRX_TXBUF_TXQ_DEPTH                         4
64328 +#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ                 5
64329 +#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ         6
64330 +#define TXRX_TXBUF_INITIALIZE_TIMER                  7
64331 +#define TXRX_TXBUF_ARM_TIMER                         8
64332 +#define TXRX_TXBUF_DISARM_TIMER                      9
64333 +#define TXRX_TXBUF_UNINITIALIZE_TIMER                10
64334 +#define TXRX_TXBUF_DBGID_DEFINITION_END
64335 +
64336 +#define TXRX_RXBUF_DBGID_DEFINITION_START
64337 +#define TXRX_RXBUF_ALLOCATE_BUF                      1
64338 +#define TXRX_RXBUF_QUEUE_TO_HOST                     2
64339 +#define TXRX_RXBUF_QUEUE_TO_WLAN                     3
64340 +#define TXRX_RXBUF_ZERO_LEN_BUF                      4
64341 +#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN  5
64342 +#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF        6
64343 +#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN         7
64344 +#define TXRX_RXBUF_SEND_TO_RECV_MGMT                 8
64345 +#define TXRX_RXBUF_SEND_TO_IEEE_LAYER                9
64346 +#define TXRX_RXBUF_DBGID_DEFINITION_END
64347 +
64348 +#define TXRX_MGMTBUF_DBGID_DEFINITION_START
64349 +#define TXRX_MGMTBUF_ALLOCATE_BUF                    1
64350 +#define TXRX_MGMTBUF_ALLOCATE_SM_BUF                 2
64351 +#define TXRX_MGMTBUF_ALLOCATE_RMBUF                  3
64352 +#define TXRX_MGMTBUF_GET_BUF                         4
64353 +#define TXRX_MGMTBUF_GET_SM_BUF                      5
64354 +#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ                6
64355 +#define TXRX_MGMTBUF_REAPED_BUF                      7
64356 +#define TXRX_MGMTBUF_REAPED_SM_BUF                   8
64357 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN              9
64358 +#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN          10
64359 +#define TXRX_MGMTBUF_ENQUEUE_INTO_SFQ                11
64360 +#define TXRX_MGMTBUF_DEQUEUE_FROM_SFQ                12
64361 +#define TXRX_MGMTBUF_PAUSE_TXQ                       13
64362 +#define TXRX_MGMTBUF_RESUME_TXQ                      14
64363 +#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT       15
64364 +#define TXRX_MGMTBUF_DRAINQ                          16
64365 +#define TXRX_MGMTBUF_INDICATE_Q_DRAINED              17
64366 +#define TXRX_MGMTBUF_DBGID_DEFINITION_END
64367 +
64368 +/* PM (Power Module) debug identifier definitions */
64369 +#define PM_DBGID_DEFINITION_START
64370 +#define PM_INIT                                      1
64371 +#define PM_ENABLE                                    2
64372 +#define PM_SET_STATE                                 3
64373 +#define PM_SET_POWERMODE                             4
64374 +#define PM_CONN_NOTIFY                               5
64375 +#define PM_REF_COUNT_NEGATIVE                        6
64376 +#define PM_APSD_ENABLE                               7
64377 +#define PM_UPDATE_APSD_STATE                         8
64378 +#define PM_CHAN_OP_REQ                               9
64379 +#define PM_SET_MY_BEACON_POLICY                      10
64380 +#define PM_SET_ALL_BEACON_POLICY                     11
64381 +#define PM_SET_PM_PARAMS1                            12
64382 +#define PM_SET_PM_PARAMS2                            13
64383 +#define PM_ADHOC_SET_PM_CAPS_FAIL                    14
64384 +#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID              15
64385 +#define PM_DBGID_DEFINITION_END
64386 +
64387 +/* Wake on Wireless debug identifier definitions */
64388 +#define WOW_DBGID_DEFINITION_START
64389 +#define WOW_INIT                                        1
64390 +#define WOW_GET_CONFIG_DSET                             2
64391 +#define WOW_NO_CONFIG_DSET                              3
64392 +#define WOW_INVALID_CONFIG_DSET                         4
64393 +#define WOW_USE_DEFAULT_CONFIG                          5
64394 +#define WOW_SETUP_GPIO                                  6
64395 +#define WOW_INIT_DONE                                   7
64396 +#define WOW_SET_GPIO_PIN                                8
64397 +#define WOW_CLEAR_GPIO_PIN                              9
64398 +#define WOW_SET_WOW_MODE_CMD                            10
64399 +#define WOW_SET_HOST_MODE_CMD                           11
64400 +#define WOW_ADD_WOW_PATTERN_CMD                         12
64401 +#define WOW_NEW_WOW_PATTERN_AT_INDEX                    13
64402 +#define WOW_DEL_WOW_PATTERN_CMD                         14
64403 +#define WOW_LIST_CONTAINS_PATTERNS                      15
64404 +#define WOW_GET_WOW_LIST_CMD                            16
64405 +#define WOW_INVALID_FILTER_ID                           17
64406 +#define WOW_INVALID_FILTER_LISTID                       18
64407 +#define WOW_NO_VALID_FILTER_AT_ID                       19
64408 +#define WOW_NO_VALID_LIST_AT_ID                         20
64409 +#define WOW_NUM_PATTERNS_EXCEEDED                       21
64410 +#define WOW_NUM_LISTS_EXCEEDED                          22
64411 +#define WOW_GET_WOW_STATS                               23
64412 +#define WOW_CLEAR_WOW_STATS                             24
64413 +#define WOW_WAKEUP_HOST                                 25
64414 +#define WOW_EVENT_WAKEUP_HOST                           26
64415 +#define WOW_EVENT_DISCARD                               27
64416 +#define WOW_PATTERN_MATCH                               28
64417 +#define WOW_PATTERN_NOT_MATCH                           29
64418 +#define WOW_PATTERN_NOT_MATCH_OFFSET                    30
64419 +#define WOW_DISABLED_HOST_ASLEEP                        31
64420 +#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS             32
64421 +#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND          33
64422 +#define WOW_DBGID_DEFINITION_END
64423 +
64424 +/* WHAL debug identifier definitions */
64425 +#define WHAL_DBGID_DEFINITION_START
64426 +#define WHAL_ERROR_ANI_CONTROL                      1
64427 +#define WHAL_ERROR_CHIP_TEST1                       2
64428 +#define WHAL_ERROR_CHIP_TEST2                       3
64429 +#define WHAL_ERROR_EEPROM_CHECKSUM                  4
64430 +#define WHAL_ERROR_EEPROM_MACADDR                   5
64431 +#define WHAL_ERROR_INTERRUPT_HIU                    6
64432 +#define WHAL_ERROR_KEYCACHE_RESET                   7
64433 +#define WHAL_ERROR_KEYCACHE_SET                     8
64434 +#define WHAL_ERROR_KEYCACHE_TYPE                    9
64435 +#define WHAL_ERROR_KEYCACHE_TKIPENTRY              10
64436 +#define WHAL_ERROR_KEYCACHE_WEPLENGTH              11
64437 +#define WHAL_ERROR_PHY_INVALID_CHANNEL             12
64438 +#define WHAL_ERROR_POWER_AWAKE                     13
64439 +#define WHAL_ERROR_POWER_SET                       14
64440 +#define WHAL_ERROR_RECV_STOPDMA                    15
64441 +#define WHAL_ERROR_RECV_STOPPCU                    16
64442 +#define WHAL_ERROR_RESET_CHANNF1                   17
64443 +#define WHAL_ERROR_RESET_CHANNF2                   18
64444 +#define WHAL_ERROR_RESET_PM                        19
64445 +#define WHAL_ERROR_RESET_OFFSETCAL                 20
64446 +#define WHAL_ERROR_RESET_RFGRANT                   21
64447 +#define WHAL_ERROR_RESET_RXFRAME                   22
64448 +#define WHAL_ERROR_RESET_STOPDMA                   23
64449 +#define WHAL_ERROR_RESET_RECOVER                   24
64450 +#define WHAL_ERROR_XMIT_COMPUTE                    25
64451 +#define WHAL_ERROR_XMIT_NOQUEUE                    26
64452 +#define WHAL_ERROR_XMIT_ACTIVEQUEUE                27
64453 +#define WHAL_ERROR_XMIT_BADTYPE                    28
64454 +#define WHAL_DBGID_DEFINITION_END
64455 +
64456 +#ifdef __cplusplus
64457 +}
64458 +#endif
64459 +
64460 +#endif /* _DBGLOG_ID_H_ */
64461 Index: linux-2.6.28/drivers/ar6000/include/dl_list.h
64462 ===================================================================
64463 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64464 +++ linux-2.6.28/drivers/ar6000/include/dl_list.h       2009-01-02 00:01:56.000000000 +0100
64465 @@ -0,0 +1,114 @@
64466 +/*
64467 + *
64468 + * Double-link list definitions (adapted from Atheros SDIO stack)
64469 + *
64470 + * Copyright (c) 2007 Atheros Communications Inc.
64471 + * All rights reserved.
64472 + *
64473 + *
64474 + *  This program is free software; you can redistribute it and/or modify
64475 + *  it under the terms of the GNU General Public License version 2 as
64476 + *  published by the Free Software Foundation;
64477 + *
64478 + *  Software distributed under the License is distributed on an "AS
64479 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64480 + *  implied. See the License for the specific language governing
64481 + *  rights and limitations under the License.
64482 + *
64483 + *
64484 + *
64485 + */
64486 +#ifndef __DL_LIST_H___
64487 +#define __DL_LIST_H___
64488 +
64489 +#define A_CONTAINING_STRUCT(address, struct_type, field_name)\
64490 +            ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name)))
64491 +
64492 +/* list functions */
64493 +/* pointers for the list */
64494 +typedef struct _DL_LIST {
64495 +    struct _DL_LIST *pPrev;
64496 +    struct _DL_LIST *pNext;
64497 +}DL_LIST, *PDL_LIST;
64498 +/*
64499 + * DL_LIST_INIT , initialize doubly linked list
64500 +*/
64501 +#define DL_LIST_INIT(pList)\
64502 +    {(pList)->pPrev = pList; (pList)->pNext = pList;}
64503 +
64504 +#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
64505 +#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
64506 +#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
64507 +/*
64508 + * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
64509 + * NOT: do not use this function if the items in the list are deleted inside the
64510 + * iteration loop
64511 +*/
64512 +#define ITERATE_OVER_LIST(pStart, pTemp) \
64513 +    for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
64514 +
64515 +
64516 +/* safe iterate macro that allows the item to be removed from the list
64517 + * the iteration continues to the next item in the list
64518 + */
64519 +#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset)  \
64520 +{                                                       \
64521 +    PDL_LIST  pTemp;                                     \
64522 +    pTemp = (pStart)->pNext;                            \
64523 +    while (pTemp != (pStart)) {                         \
64524 +        (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset);   \
64525 +         pTemp = pTemp->pNext;                          \
64526 +
64527 +#define ITERATE_END }}
64528 +
64529 +/*
64530 + * DL_ListInsertTail - insert pAdd to the end of the list
64531 +*/
64532 +static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) {
64533 +        /* insert at tail */
64534 +    pAdd->pPrev = pList->pPrev;
64535 +    pAdd->pNext = pList;
64536 +    pList->pPrev->pNext = pAdd;
64537 +    pList->pPrev = pAdd;
64538 +    return pAdd;
64539 +}
64540 +
64541 +/*
64542 + * DL_ListInsertHead - insert pAdd into the head of the list
64543 +*/
64544 +static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) {
64545 +        /* insert at head */
64546 +    pAdd->pPrev = pList;
64547 +    pAdd->pNext = pList->pNext;
64548 +    pList->pNext->pPrev = pAdd;
64549 +    pList->pNext = pAdd;
64550 +    return pAdd;
64551 +}
64552 +
64553 +#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem))
64554 +/*
64555 + * DL_ListRemove - remove pDel from list
64556 +*/
64557 +static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) {
64558 +    pDel->pNext->pPrev = pDel->pPrev;
64559 +    pDel->pPrev->pNext = pDel->pNext;
64560 +        /* point back to itself just to be safe, incase remove is called again */
64561 +    pDel->pNext = pDel;
64562 +    pDel->pPrev = pDel;
64563 +    return pDel;
64564 +}
64565 +
64566 +/*
64567 + * DL_ListRemoveItemFromHead - get a list item from the head
64568 +*/
64569 +static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) {
64570 +    PDL_LIST pItem = NULL;
64571 +    if (pList->pNext != pList) {
64572 +        pItem = pList->pNext;
64573 +            /* remove the first item from head */
64574 +        DL_ListRemove(pItem);
64575 +    }
64576 +    return pItem;
64577 +}
64578 +
64579 +#endif /* __DL_LIST_H___ */
64580 Index: linux-2.6.28/drivers/ar6000/include/dset_api.h
64581 ===================================================================
64582 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64583 +++ linux-2.6.28/drivers/ar6000/include/dset_api.h      2009-01-02 00:01:56.000000000 +0100
64584 @@ -0,0 +1,63 @@
64585 +/*
64586 + * Copyright (c) 2004-2006 Atheros Communications Inc.
64587 + * All rights reserved.
64588 + *
64589 + *
64590 + *  This program is free software; you can redistribute it and/or modify
64591 + *  it under the terms of the GNU General Public License version 2 as
64592 + *  published by the Free Software Foundation;
64593 + *
64594 + *  Software distributed under the License is distributed on an "AS
64595 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64596 + *  implied. See the License for the specific language governing
64597 + *  rights and limitations under the License.
64598 + *
64599 + *
64600 + *
64601 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/dset_api.h#1 $
64602 + *
64603 + * Host-side DataSet API.
64604 + *
64605 + */
64606 +
64607 +#ifndef _DSET_API_H_
64608 +#define _DSET_API_H_
64609 +
64610 +#ifdef __cplusplus
64611 +extern "C" {
64612 +#endif /* __cplusplus */
64613 +
64614 +/*
64615 + * Host-side DataSet support is optional, and is not
64616 + * currently required for correct operation.  To disable
64617 + * Host-side DataSet support, set this to 0.
64618 + */
64619 +#ifndef CONFIG_HOST_DSET_SUPPORT
64620 +#define CONFIG_HOST_DSET_SUPPORT 1
64621 +#endif
64622 +
64623 +/* Called to send a DataSet Open Reply back to the Target. */
64624 +A_STATUS wmi_dset_open_reply(struct wmi_t *wmip,
64625 +                             A_UINT32 status,
64626 +                             A_UINT32 access_cookie,
64627 +                             A_UINT32 size,
64628 +                             A_UINT32 version,
64629 +                             A_UINT32 targ_handle,
64630 +                             A_UINT32 targ_reply_fn,
64631 +                             A_UINT32 targ_reply_arg);
64632 +
64633 +/* Called to send a DataSet Data Reply back to the Target. */
64634 +A_STATUS wmi_dset_data_reply(struct wmi_t *wmip,
64635 +                             A_UINT32 status,
64636 +                             A_UINT8 *host_buf,
64637 +                             A_UINT32 length,
64638 +                             A_UINT32 targ_buf,
64639 +                             A_UINT32 targ_reply_fn,
64640 +                             A_UINT32 targ_reply_arg);
64641 +
64642 +#ifdef __cplusplus
64643 +}
64644 +#endif /* __cplusplus */
64645 +
64646 +
64647 +#endif /* _DSET_API_H_ */
64648 Index: linux-2.6.28/drivers/ar6000/include/dsetid.h
64649 ===================================================================
64650 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64651 +++ linux-2.6.28/drivers/ar6000/include/dsetid.h        2009-01-02 00:01:56.000000000 +0100
64652 @@ -0,0 +1,110 @@
64653 +/*
64654 + * Copyright (c) 2004-2007 Atheros Communications Inc.
64655 + * All rights reserved.
64656 + *
64657 + * $ATH_LICENSE_HOSTSDK0_C$
64658 + *
64659 + */
64660 +
64661 +#ifndef __DSETID_H__
64662 +#define __DSETID_H__
64663 +
64664 +/* Well-known DataSet IDs */
64665 +#define DSETID_UNUSED                     0x00000000
64666 +#define DSETID_BOARD_DATA                 0x00000001 /* Cal and board data */
64667 +#define DSETID_REGDB                      0x00000002 /* Regulatory Database */
64668 +#define DSETID_POWER_CONTROL              0x00000003 /* TX Pwr Lim & Ant Gain */
64669 +#define DSETID_USER_CONFIG                0x00000004 /* User Configuration */
64670 +
64671 +#define DSETID_ANALOG_CONTROL_DATA_START  0x00000005
64672 +#define DSETID_ANALOG_CONTROL_DATA_END    0x00000025
64673 +/*
64674 + * Get DSETID for various reference clock speeds.
64675 + * For each speed there are three DataSets that correspond
64676 + * to the three columns of bank6 data (addr, 11a, 11b/g).
64677 + * This macro returns the dsetid of the first of those
64678 + * three DataSets.
64679 + */
64680 +#define ANALOG_CONTROL_DATA_DSETID(refclk) \
64681 +        (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
64682 +
64683 +/*
64684 + * There are TWO STARTUP_PATCH DataSets.
64685 + * DSETID_STARTUP_PATCH is historical, and was applied before BMI on
64686 + * earlier systems.  On AR6002, it is applied after BMI, just like
64687 + * DSETID_STARTUP_PATCH2.
64688 + */
64689 +#define DSETID_STARTUP_PATCH              0x00000026
64690 +#define DSETID_GPIO_CONFIG_PATCH          0x00000027
64691 +#define DSETID_WLANREGS                   0x00000028 /* override wlan regs */
64692 +#define DSETID_STARTUP_PATCH2             0x00000029
64693 +
64694 +#define DSETID_WOW_CONFIG                 0x00000090 /* WoW Configuration */
64695 +
64696 +/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
64697 +#define DSETID_INI_DATA                   0x00000100
64698 +/* Reserved for WHAL INI Tables: 0x100..0x11f */
64699 +#define DSETID_INI_DATA_END               0x0000011f
64700 +
64701 +#define DSETID_VENDOR_START               0x00010000 /* Vendor-defined DataSets */
64702 +
64703 +#define DSETID_INDEX_END                  0xfffffffe /* Reserved to indicate the
64704 +                                                        end of a memory-based
64705 +                                                        DataSet Index */
64706 +#define DSETID_INDEX_FREE                 0xffffffff /* An unused index entry */
64707 +
64708 +/*
64709 + * PATCH DataSet format:
64710 + * A list of patches, terminated by a patch with
64711 + * address=PATCH_END.
64712 + *
64713 + * This allows for patches to be stored in flash.
64714 + */
64715 +struct patch_s {
64716 +    A_UINT32 *address;
64717 +    A_UINT32  data;
64718 +};
64719 +
64720 +/*
64721 + * Skip some patches.  Can be used to erase a single patch in a
64722 + * patch DataSet without having to re-write the DataSet.  May
64723 + * also be used to embed information for use by subsequent
64724 + * patch code.  The "data" in a PATCH_SKIP tells how many
64725 + * bytes of length "patch_s" to skip.
64726 + */
64727 +#define PATCH_SKIP      ((A_UINT32 *)0x00000000)
64728 +
64729 +/*
64730 + * Execute code at the address specified by "data".
64731 + * The address of the patch structure is passed as
64732 + * the one parameter.
64733 + */
64734 +#define PATCH_CODE_ABS  ((A_UINT32 *)0x00000001)
64735 +
64736 +/*
64737 + * Same as PATCH_CODE_ABS, but treat "data" as an
64738 + * offset from the start of the patch word.
64739 + */
64740 +#define PATCH_CODE_REL  ((A_UINT32 *)0x00000002)
64741 +
64742 +/* Mark the end of this patch DataSet. */
64743 +#define PATCH_END       ((A_UINT32 *)0xffffffff)
64744 +
64745 +/*
64746 + * A DataSet which contains a Binary Patch to some other DataSet
64747 + * uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
64748 + * Such a BPatch DataSet consists of BPatch metadata followed by
64749 + * the bdiff bytes.  BPatch metadata consists of a single 32-bit
64750 + * word that contains the size of the BPatched final image.
64751 + *
64752 + * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
64753 + * to create "diffs":
64754 + *  bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
64755 + * Then add BPatch metadata to the start of "diffs".
64756 + *
64757 + * NB: There are some implementation-induced restrictions
64758 + * on which DataSets can be BPatched.
64759 + */
64760 +#define DSETID_BPATCH_FLAG                0x80000000
64761 +
64762 +#endif /* __DSETID_H__ */
64763 Index: linux-2.6.28/drivers/ar6000/include/dset_internal.h
64764 ===================================================================
64765 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64766 +++ linux-2.6.28/drivers/ar6000/include/dset_internal.h 2009-01-02 00:01:56.000000000 +0100
64767 @@ -0,0 +1,39 @@
64768 +/*
64769 + * Copyright (c) 2007 Atheros Communications Inc.
64770 + * All rights reserved.
64771 + *
64772 + * $ATH_LICENSE_HOSTSDK0_C$
64773 + *
64774 + */
64775 +
64776 +#ifndef __DSET_INTERNAL_H__
64777 +#define __DSET_INTERNAL_H__
64778 +
64779 +/*
64780 + * Internal dset definitions, common for DataSet layer.
64781 + */
64782 +
64783 +#define DSET_TYPE_STANDARD      0
64784 +#define DSET_TYPE_BPATCHED      1
64785 +#define DSET_TYPE_COMPRESSED    2
64786 +
64787 +/* Dataset descriptor */
64788 +
64789 +typedef struct dset_descriptor_s {
64790 +  struct dset_descriptor_s  *next;         /* List link. NULL only at the last
64791 +                                              descriptor */
64792 +  A_UINT16                   id;           /* Dset ID */
64793 +  A_UINT16                   size;         /* Dset size. */
64794 +  void                      *DataPtr;      /* Pointer to raw data for standard
64795 +                                              DataSet or pointer to original
64796 +                                              dset_descriptor for patched
64797 +                                              DataSet */
64798 +  A_UINT32                   data_type;    /* DSET_TYPE_*, above */
64799 +
64800 +  void                      *AuxPtr;       /* Additional data that might
64801 +                                              needed for data_type. For
64802 +                                              example, pointer to patch
64803 +                                              Dataset descriptor for BPatch. */
64804 +} dset_descriptor_t;
64805 +
64806 +#endif /* __DSET_INTERNAL_H__ */
64807 Index: linux-2.6.28/drivers/ar6000/include/gpio_api.h
64808 ===================================================================
64809 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64810 +++ linux-2.6.28/drivers/ar6000/include/gpio_api.h      2009-01-02 00:01:56.000000000 +0100
64811 @@ -0,0 +1,57 @@
64812 +#ifndef _GPIO_API_H_
64813 +#define _GPIO_API_H_
64814 +/*
64815 + * Copyright 2005 Atheros Communications, Inc.,  All Rights Reserved.
64816 + *
64817 + *
64818 + *  This program is free software; you can redistribute it and/or modify
64819 + *  it under the terms of the GNU General Public License version 2 as
64820 + *  published by the Free Software Foundation;
64821 + *
64822 + *  Software distributed under the License is distributed on an "AS
64823 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64824 + *  implied. See the License for the specific language governing
64825 + *  rights and limitations under the License.
64826 + *
64827 + *
64828 + *
64829 + */
64830 +
64831 +/*
64832 + * Host-side General Purpose I/O API.
64833 + *
64834 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/gpio_api.h#1 $
64835 + */
64836 +
64837 +/*
64838 + * Send a command to the Target in order to change output on GPIO pins.
64839 + */
64840 +A_STATUS wmi_gpio_output_set(struct wmi_t *wmip,
64841 +                             A_UINT32 set_mask,
64842 +                             A_UINT32 clear_mask,
64843 +                             A_UINT32 enable_mask,
64844 +                             A_UINT32 disable_mask);
64845 +
64846 +/*
64847 + * Send a command to the Target requesting input state of GPIO pins.
64848 + */
64849 +A_STATUS wmi_gpio_input_get(struct wmi_t *wmip);
64850 +
64851 +/*
64852 + * Send a command to the Target to change the value of a GPIO register.
64853 + */
64854 +A_STATUS wmi_gpio_register_set(struct wmi_t *wmip,
64855 +                               A_UINT32 gpioreg_id,
64856 +                               A_UINT32 value);
64857 +
64858 +/*
64859 + * Send a command to the Target to fetch the value of a GPIO register.
64860 + */
64861 +A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
64862 +
64863 +/*
64864 + * Send a command to the Target, acknowledging some GPIO interrupts.
64865 + */
64866 +A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
64867 +
64868 +#endif /* _GPIO_API_H_ */
64869 Index: linux-2.6.28/drivers/ar6000/include/gpio.h
64870 ===================================================================
64871 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64872 +++ linux-2.6.28/drivers/ar6000/include/gpio.h  2009-01-02 00:01:56.000000000 +0100
64873 @@ -0,0 +1,34 @@
64874 +/*
64875 + * Copyright (c) 2005 Atheros Communications Inc.
64876 + * All rights reserved.
64877 + *
64878 + * $ATH_LICENSE_HOSTSDK0_C$
64879 + *
64880 + */
64881 +
64882 +#if defined(AR6001)
64883 +#define GPIO_PIN_COUNT 18
64884 +#else
64885 +#define GPIO_PIN_COUNT 18
64886 +#endif
64887 +
64888 +/*
64889 + * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
64890 + * NB: These match hardware order, so that addresses can
64891 + * easily be computed.
64892 + */
64893 +#define GPIO_ID_OUT             0x00000000
64894 +#define GPIO_ID_OUT_W1TS        0x00000001
64895 +#define GPIO_ID_OUT_W1TC        0x00000002
64896 +#define GPIO_ID_ENABLE          0x00000003
64897 +#define GPIO_ID_ENABLE_W1TS     0x00000004
64898 +#define GPIO_ID_ENABLE_W1TC     0x00000005
64899 +#define GPIO_ID_IN              0x00000006
64900 +#define GPIO_ID_STATUS          0x00000007
64901 +#define GPIO_ID_STATUS_W1TS     0x00000008
64902 +#define GPIO_ID_STATUS_W1TC     0x00000009
64903 +#define GPIO_ID_PIN0            0x0000000a
64904 +#define GPIO_ID_PIN(n)          (GPIO_ID_PIN0+(n))
64905 +
64906 +#define GPIO_LAST_REGISTER_ID   GPIO_ID_PIN(17)
64907 +#define GPIO_ID_NONE            0xffffffff
64908 Index: linux-2.6.28/drivers/ar6000/include/hif.h
64909 ===================================================================
64910 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
64911 +++ linux-2.6.28/drivers/ar6000/include/hif.h   2009-01-02 00:01:56.000000000 +0100
64912 @@ -0,0 +1,296 @@
64913 +/*
64914 + * Copyright (c) 2004-2007 Atheros Communications Inc.
64915 + * All rights reserved.
64916 + *
64917 + *
64918 + *  This program is free software; you can redistribute it and/or modify
64919 + *  it under the terms of the GNU General Public License version 2 as
64920 + *  published by the Free Software Foundation;
64921 + *
64922 + *  Software distributed under the License is distributed on an "AS
64923 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
64924 + *  implied. See the License for the specific language governing
64925 + *  rights and limitations under the License.
64926 + *
64927 + *
64928 + *
64929 + * HIF specific declarations and prototypes
64930 + */
64931 +
64932 +#ifndef _HIF_H_
64933 +#define _HIF_H_
64934 +
64935 +#ifdef __cplusplus
64936 +extern "C" {
64937 +#endif /* __cplusplus */
64938 +
64939 +/* Header files */
64940 +#include "a_config.h"
64941 +#include "athdefs.h"
64942 +#include "a_types.h"
64943 +#include "a_osapi.h"
64944 +
64945 +typedef struct htc_callbacks HTC_CALLBACKS;
64946 +typedef struct hif_device HIF_DEVICE;
64947 +
64948 +/*
64949 + * direction - Direction of transfer (HIF_READ/HIF_WRITE).
64950 + */
64951 +#define HIF_READ                    0x00000001
64952 +#define HIF_WRITE                   0x00000002
64953 +#define HIF_DIR_MASK                (HIF_READ | HIF_WRITE)
64954 +
64955 +/*
64956 + *     type - An interface may support different kind of read/write commands.
64957 + *            The command type is divided into a basic and an extended command
64958 + *            and can be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
64959 + */
64960 +#define HIF_BASIC_IO                0x00000004
64961 +#define HIF_EXTENDED_IO             0x00000008
64962 +#define HIF_TYPE_MASK               (HIF_BASIC_IO | HIF_EXTENDED_IO)
64963 +
64964 +/*
64965 + *     emode - This indicates the whether the command is to be executed in a
64966 + *             blocking or non-blocking fashion (HIF_SYNCHRONOUS/
64967 + *             HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
64968 + *             implemented using the asynchronous mode allowing the the bus
64969 + *             driver to indicate the completion of operation through the
64970 + *             registered callback routine. The requirement primarily comes
64971 + *             from the contexts these operations get called from (a driver's
64972 + *             transmit context or the ISR context in case of receive).
64973 + *             Support for both of these modes is essential.
64974 + */
64975 +#define HIF_SYNCHRONOUS             0x00000010
64976 +#define HIF_ASYNCHRONOUS            0x00000020
64977 +#define HIF_EMODE_MASK              (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
64978 +
64979 +/*
64980 + *     dmode - An interface may support different kinds of commands based on
64981 + *             the tradeoff between the amount of data it can carry and the
64982 + *             setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
64983 + *             HIF_BLOCK_BASIS). In case of latter, the data is rounded off
64984 + *             to the nearest block size by padding. The size of the block is
64985 + *             configurable at compile time using the HIF_BLOCK_SIZE and is
64986 + *             negotiated with the target during initialization after the
64987 + *             dragon interrupts are enabled.
64988 + */
64989 +#define HIF_BYTE_BASIS              0x00000040
64990 +#define HIF_BLOCK_BASIS             0x00000080
64991 +#define HIF_DMODE_MASK              (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
64992 +
64993 +/*
64994 + *     amode - This indicates if the address has to be incremented on dragon
64995 + *             after every read/write operation (HIF?FIXED_ADDRESS/
64996 + *             HIF_INCREMENTAL_ADDRESS).
64997 + */
64998 +#define HIF_FIXED_ADDRESS           0x00000100
64999 +#define HIF_INCREMENTAL_ADDRESS     0x00000200
65000 +#define HIF_AMODE_MASK              (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
65001 +
65002 +#define HIF_WR_ASYNC_BYTE_FIX   \
65003 +    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
65004 +#define HIF_WR_ASYNC_BYTE_INC   \
65005 +    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
65006 +#define HIF_WR_ASYNC_BLOCK_INC  \
65007 +    (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
65008 +#define HIF_WR_SYNC_BYTE_FIX    \
65009 +    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
65010 +#define HIF_WR_SYNC_BYTE_INC    \
65011 +    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
65012 +#define HIF_WR_SYNC_BLOCK_INC  \
65013 +    (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
65014 +#define HIF_RD_SYNC_BYTE_INC    \
65015 +    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
65016 +#define HIF_RD_SYNC_BYTE_FIX    \
65017 +    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
65018 +#define HIF_RD_ASYNC_BYTE_FIX   \
65019 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
65020 +#define HIF_RD_ASYNC_BLOCK_FIX  \
65021 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
65022 +#define HIF_RD_ASYNC_BYTE_INC   \
65023 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
65024 +#define HIF_RD_ASYNC_BLOCK_INC  \
65025 +    (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
65026 +#define HIF_RD_SYNC_BLOCK_INC  \
65027 +    (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
65028 +
65029 +
65030 +typedef enum {
65031 +    HIF_DEVICE_POWER_STATE = 0,
65032 +    HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
65033 +    HIF_DEVICE_GET_MBOX_ADDR,
65034 +    HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
65035 +    HIF_DEVICE_GET_IRQ_PROC_MODE,
65036 +    HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
65037 +} HIF_DEVICE_CONFIG_OPCODE;
65038 +
65039 +/*
65040 + * HIF CONFIGURE definitions:
65041 + *
65042 + *   HIF_DEVICE_GET_MBOX_BLOCK_SIZE
65043 + *   input : none
65044 + *   output : array of 4 A_UINT32s
65045 + *   notes: block size is returned for each mailbox (4)
65046 + *
65047 + *   HIF_DEVICE_GET_MBOX_ADDR
65048 + *   input : none
65049 + *   output : array of 4 A_UINT32
65050 + *   notes: address is returned for each mailbox (4) in the array
65051 + *
65052 + *   HIF_DEVICE_GET_PENDING_EVENTS_FUNC
65053 + *   input : none
65054 + *   output: HIF_PENDING_EVENTS_FUNC function pointer
65055 + *   notes: this is optional for the HIF layer, if the request is
65056 + *          not handled then it indicates that the upper layer can use
65057 + *          the standard device methods to get pending events (IRQs, mailbox messages etc..)
65058 + *          otherwise it can call the function pointer to check pending events.
65059 + *
65060 + *   HIF_DEVICE_GET_IRQ_PROC_MODE
65061 + *   input : none
65062 + *   output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
65063 + *   note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
65064 + *         layer can report whether IRQ processing is requires synchronous behavior or
65065 + *         can be processed using asynchronous bus requests (typically faster).
65066 + *
65067 + *   HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
65068 + *   input :
65069 + *   output : HIF_MASK_UNMASK_RECV_EVENT function pointer
65070 + *   notes: this is optional for the HIF layer.  The HIF layer may require a special mechanism
65071 + *          to mask receive message events.  The upper layer can call this pointer when it needs
65072 + *          to mask/unmask receive events (in case it runs out of buffers).
65073 + *
65074 + *
65075 + */
65076 +
65077 +typedef enum {
65078 +    HIF_DEVICE_IRQ_SYNC_ONLY,   /* for HIF implementations that require the DSR to process all
65079 +                                   interrupts before returning */
65080 +    HIF_DEVICE_IRQ_ASYNC_SYNC,  /* for HIF implementations that allow DSR to process interrupts
65081 +                                   using ASYNC I/O (that is HIFAckInterrupt can be called at a
65082 +                                   later time */
65083 +} HIF_DEVICE_IRQ_PROCESSING_MODE;
65084 +
65085 +#define HIF_MAX_DEVICES                 1
65086 +
65087 +struct htc_callbacks {
65088 +    A_UCHAR *name;
65089 +    A_UINT32 id;
65090 +    A_STATUS (* deviceInsertedHandler)(void *hif_handle);
65091 +    A_STATUS (* deviceRemovedHandler)(void *htc_handle, A_STATUS status);
65092 +    A_STATUS (* deviceSuspendHandler)(void *htc_handle);
65093 +    A_STATUS (* deviceResumeHandler)(void *htc_handle);
65094 +    A_STATUS (* deviceWakeupHandler)(void *htc_handle);
65095 +    A_STATUS (* rwCompletionHandler)(void *context, A_STATUS status);
65096 +    A_STATUS (* dsrHandler)(void *htc_handle);
65097 +};
65098 +
65099 +
65100 +#define HIF_OTHER_EVENTS     (1 << 0)   /* other interrupts (non-Recv) are pending, host
65101 +                                           needs to read the register table to figure out what */
65102 +#define HIF_RECV_MSG_AVAIL   (1 << 1)   /* pending recv packet */
65103 +
65104 +typedef struct _HIF_PENDING_EVENTS_INFO {
65105 +    A_UINT32 Events;
65106 +    A_UINT32 LookAhead;
65107 +} HIF_PENDING_EVENTS_INFO;
65108 +
65109 +    /* function to get pending events , some HIF modules use special mechanisms
65110 +     * to detect packet available and other interrupts */
65111 +typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE              *device,
65112 +                                             HIF_PENDING_EVENTS_INFO *pEvents,
65113 +                                             void                    *AsyncContext);
65114 +
65115 +#define HIF_MASK_RECV    TRUE
65116 +#define HIF_UNMASK_RECV  FALSE
65117 +    /* function to mask recv events */
65118 +typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE  *device,
65119 +                                                A_BOOL      Mask,
65120 +                                                void        *AsyncContext);
65121 +
65122 +
65123 +/*
65124 + * This API is used by the HTC layer to initialize the HIF layer and to
65125 + * register different callback routines. Support for following events has
65126 + * been captured - DSR, Read/Write completion, Device insertion/removal,
65127 + * Device suspension/resumption/wakeup. In addition to this, the API is
65128 + * also used to register the name and the revision of the chip. The latter
65129 + * can be used to verify the revision of the chip read from the device
65130 + * before reporting it to HTC.
65131 + */
65132 +int HIFInit(HTC_CALLBACKS *callbacks);
65133 +
65134 +/*
65135 + * This API is used to provide the read/write interface over the specific bus
65136 + * interface.
65137 + * address - Starting address in the dragon's address space. For mailbox
65138 + *           writes, it refers to the start of the mbox boundary. It should
65139 + *           be ensured that the last byte falls on the mailbox's EOM. For
65140 + *           mailbox reads, it refers to the end of the mbox boundary.
65141 + * buffer - Pointer to the buffer containg the data to be transmitted or
65142 + *          received.
65143 + * length - Amount of data to be transmitted or received.
65144 + * request - Characterizes the attributes of the command.
65145 + */
65146 +A_STATUS
65147 +HIFReadWrite(HIF_DEVICE    *device,
65148 +             A_UINT32       address,
65149 +             A_UCHAR       *buffer,
65150 +             A_UINT32       length,
65151 +             A_UINT32       request,
65152 +             void          *context);
65153 +
65154 +/*
65155 + * This can be initiated from the unload driver context ie when the HTCShutdown
65156 + * routine is called.
65157 + */
65158 +void HIFShutDownDevice(HIF_DEVICE *device);
65159 +
65160 +/*
65161 + * This should translate to an acknowledgment to the bus driver indicating that
65162 + * the previous interrupt request has been serviced and the all the relevant
65163 + * sources have been cleared. HTC is ready to process more interrupts.
65164 + * This should prevent the bus driver from raising an interrupt unless the
65165 + * previous one has been serviced and acknowledged using the previous API.
65166 + */
65167 +void HIFAckInterrupt(HIF_DEVICE *device);
65168 +
65169 +void HIFMaskInterrupt(HIF_DEVICE *device);
65170 +
65171 +void HIFUnMaskInterrupt(HIF_DEVICE *device);
65172 +
65173 +/*
65174 + * This set of functions are to be used by the bus driver to notify
65175 + * the HIF module about various events.
65176 + * These are not implemented if the bus driver provides an alternative
65177 + * way for this notification though callbacks for instance.
65178 + */
65179 +int HIFInsertEventNotify(void);
65180 +
65181 +int HIFRemoveEventNotify(void);
65182 +
65183 +int HIFIRQEventNotify(void);
65184 +
65185 +int HIFRWCompleteEventNotify(void);
65186 +
65187 +/*
65188 + * This function associates a opaque handle with the HIF layer
65189 + * to be used in communication with upper layer i.e. HTC.
65190 + * This would normaly be a pointer to htc_target data structure.
65191 + */
65192 +void HIFSetHandle(void *hif_handle, void *handle);
65193 +
65194 +A_STATUS
65195 +HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
65196 +                   void *config, A_UINT32 configLen);
65197 +
65198 +
65199 +struct device;
65200 +struct device*
65201 +HIFGetOSDevice(HIF_DEVICE *device);
65202 +
65203 +
65204 +#ifdef __cplusplus
65205 +}
65206 +#endif
65207 +
65208 +#endif /* _HIF_H_ */
65209 Index: linux-2.6.28/drivers/ar6000/include/host_version.h
65210 ===================================================================
65211 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
65212 +++ linux-2.6.28/drivers/ar6000/include/host_version.h  2009-01-02 00:01:56.000000000 +0100
65213 @@ -0,0 +1,49 @@
65214 +#ifndef _HOST_VERSION_H_
65215 +#define _HOST_VERSION_H_
65216 +/*
65217 + * Copyright (c) 2004-2005 Atheros Communications Inc.
65218 + * All rights reserved.
65219 + *
65220 + * This file contains version information for the sample host driver for the
65221 + * AR6000 chip
65222 + *
65223 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/host_version.h#2 $
65224 + *
65225 + *
65226 + *  This program is free software; you can redistribute it and/or modify
65227 + *  it under the terms of the GNU General Public License version 2 as
65228 + *  published by the Free Software Foundation;
65229 + *
65230 + *  Software distributed under the License is distributed on an "AS
65231 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
65232 + *  implied. See the License for the specific language governing
65233 + *  rights and limitations under the License.
65234 + *
65235 + *
65236 + *
65237 + */
65238 +
65239 +#ifdef __cplusplus
65240 +extern "C" {
65241 +#endif
65242 +
65243 +#include <AR6K_version.h>
65244 +
65245 +/*
65246 + * The version number is made up of major, minor, patch and build
65247 + * numbers. These are 16 bit numbers.  The build and release script will
65248 + * set the build number using a Perforce counter.  Here the build number is
65249 + * set to 9999 so that builds done without the build-release script are easily
65250 + * identifiable.
65251 + */
65252 +
65253 +#define ATH_SW_VER_MAJOR      __VER_MAJOR_
65254 +#define ATH_SW_VER_MINOR      __VER_MINOR_
65255 +#define ATH_SW_VER_PATCH      __VER_PATCH_
65256 +#define ATH_SW_VER_BUILD 9999
65257 +
65258 +#ifdef __cplusplus
65259 +}
65260 +#endif
65261 +
65262 +#endif /* _HOST_VERSION_H_ */
65263 Index: linux-2.6.28/drivers/ar6000/include/htc_api.h
65264 ===================================================================
65265 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
65266 +++ linux-2.6.28/drivers/ar6000/include/htc_api.h       2009-01-02 00:01:56.000000000 +0100
65267 @@ -0,0 +1,436 @@
65268 +/*
65269 + *
65270 + * Copyright (c) 2007 Atheros Communications Inc.
65271 + * All rights reserved.
65272 + *
65273 + *
65274 + *  This program is free software; you can redistribute it and/or modify
65275 + *  it under the terms of the GNU General Public License version 2 as
65276 + *  published by the Free Software Foundation;
65277 + *
65278 + *  Software distributed under the License is distributed on an "AS
65279 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
65280 + *  implied. See the License for the specific language governing
65281 + *  rights and limitations under the License.
65282 + *
65283 + *
65284 + *
65285 + */
65286 +
65287 +#ifndef _HTC_API_H_
65288 +#define _HTC_API_H_
65289 +
65290 +#include <htc.h>
65291 +#include <htc_services.h>
65292 +#include "htc_packet.h"
65293 +
65294 +#ifdef __cplusplus
65295 +extern "C" {
65296 +#endif /* __cplusplus */
65297 +
65298 +/* TODO.. for BMI */
65299 +#define ENDPOINT1 0
65300 +// TODO -remove me, but we have to fix BMI first
65301 +#define HTC_MAILBOX_NUM_MAX    4
65302 +
65303 +
65304 +/* ------ Endpoint IDS ------ */
65305 +typedef enum
65306 +{
65307 +    ENDPOINT_UNUSED = -1,
65308 +    ENDPOINT_0 = 0,
65309 +    ENDPOINT_1 = 1,
65310 +    ENDPOINT_2 = 2,
65311 +    ENDPOINT_3,
65312 +    ENDPOINT_4,
65313 +    ENDPOINT_5,
65314 +    ENDPOINT_6,
65315 +    ENDPOINT_7,
65316 +    ENDPOINT_8,
65317 +    ENDPOINT_MAX,
65318 +} HTC_ENDPOINT_ID;
65319 +
65320 +/* this is the amount of header room required by users of HTC */
65321 +#define HTC_HEADER_LEN         HTC_HDR_LENGTH
65322 +
65323 +typedef void *HTC_HANDLE;
65324 +
65325 +typedef A_UINT16 HTC_SERVICE_ID;
65326 +
65327 +typedef struct _HTC_INIT_INFO {
65328 +    void   (*AddInstance)(HTC_HANDLE);
65329 +    void   (*DeleteInstance)(void *Instance);
65330 +    void   (*TargetFailure)(void *Instance, A_STATUS Status);
65331 +} HTC_INIT_INFO;
65332 +
65333 +/* per service connection send completion */
65334 +typedef void   (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *);
65335 +/* per service connection pkt received */
65336 +typedef void   (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *);
65337 +
65338 +/* Optional per service connection receive buffer re-fill callback,
65339 + * On some OSes (like Linux) packets are allocated from a global pool and indicated up
65340 + * to the network stack.  The driver never gets the packets back from the OS.  For these OSes
65341 + * a refill callback can be used to allocate and re-queue buffers into HTC.
65342 + *
65343 + * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
65344 + * the driver can re-queue these buffers into HTC. In this regard a refill callback is
65345 + * unnecessary */
65346 +typedef void   (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
65347 +
65348 +/* Optional per service connection callback when a send queue is full. This can occur if the
65349 + * host continues queueing up TX packets faster than credits can arrive
65350 + * To prevent the host (on some Oses like Linux) from continuously queueing packets
65351 + * and consuming resources, this callback is provided so that that the host
65352 + * can disable TX in the subsystem (i.e. network stack)
65353 + * Other OSes require a "per-packet" indication_RAW_STREAM_NUM_MAX for each completed TX packet, this
65354 + * closed loop mechanism will prevent the network stack from overunning the NIC */
65355 +typedef void (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_ENDPOINT_ID Endpoint);
65356 +
65357 +typedef struct _HTC_EP_CALLBACKS {
65358 +    void                     *pContext;     /* context for each callback */
65359 +    HTC_EP_SEND_PKT_COMPLETE EpTxComplete;  /* tx completion callback for connected endpoint */
65360 +    HTC_EP_RECV_PKT          EpRecv;        /* receive callback for connected endpoint */
65361 +    HTC_EP_RECV_REFILL       EpRecvRefill;  /* OPTIONAL receive re-fill callback for connected endpoint */
65362 +    HTC_EP_SEND_QUEUE_FULL   EpSendFull;    /* OPTIONAL send full callback */
65363 +} HTC_EP_CALLBACKS;
65364 +
65365 +/* service connection information */
65366 +typedef struct _HTC_SERVICE_CONNECT_REQ {
65367 +    HTC_SERVICE_ID   ServiceID;                 /* service ID to connect to */
65368 +    A_UINT16         ConnectionFlags;           /* connection flags, see htc protocol definition */
65369 +    A_UINT8         *pMetaData;                 /* ptr to optional service-specific meta-data */
65370 +    A_UINT8          MetaDataLength;            /* optional meta data length */
65371 +    HTC_EP_CALLBACKS EpCallbacks;               /* endpoint callbacks */
65372 +    int              MaxSendQueueDepth;         /* maximum depth of any send queue */
65373 +} HTC_SERVICE_CONNECT_REQ;
65374 +
65375 +/* service connection response information */
65376 +typedef struct _HTC_SERVICE_CONNECT_RESP {
65377 +    A_UINT8     *pMetaData;             /* caller supplied buffer to optional meta-data */
65378 +    A_UINT8     BufferLength;           /* length of caller supplied buffer */
65379 +    A_UINT8     ActualLength;           /* actual length of meta data */
65380 +    HTC_ENDPOINT_ID Endpoint;           /* endpoint to communicate over */
65381 +    int         MaxMsgLength;           /* max length of all messages over this endpoint */
65382 +    A_UINT8     ConnectRespCode;        /* connect response code from target */
65383 +} HTC_SERVICE_CONNECT_RESP;
65384 +
65385 +/* endpoint distribution structure */
65386 +typedef struct _HTC_ENDPOINT_CREDIT_DIST {
65387 +    struct _HTC_ENDPOINT_CREDIT_DIST *pNext;
65388 +    struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
65389 +    HTC_SERVICE_ID      ServiceID;          /* Service ID (set by HTC) */
65390 +    HTC_ENDPOINT_ID     Endpoint;           /* endpoint for this distribution struct (set by HTC) */
65391 +    A_UINT32            DistFlags;          /* distribution flags, distribution function can
65392 +                                               set default activity using SET_EP_ACTIVE() macro */
65393 +    int                 TxCreditsNorm;      /* credits for normal operation, anything above this
65394 +                                               indicates the endpoint is over-subscribed, this field
65395 +                                               is only relevant to the credit distribution function */
65396 +    int                 TxCreditsMin;       /* floor for credit distribution, this field is
65397 +                                               only relevant to the credit distribution function */
65398 +    int                 TxCreditsAssigned;  /* number of credits assigned to this EP, this field
65399 +                                               is only relevant to the credit dist function */
65400 +    int                 TxCredits;          /* current credits available, this field is used by
65401 +                                               HTC to determine whether a message can be sent or
65402 +                                               must be queued */
65403 +    int                 TxCreditsToDist;    /* pending credits to distribute on this endpoint, this
65404 +                                               is set by HTC when credit reports arrive.
65405 +                                               The credit distribution functions sets this to zero
65406 +                                               when it distributes the credits */
65407 +    int                 TxCreditsSeek;      /* this is the number of credits that the current pending TX
65408 +                                               packet needs to transmit.  This is set by HTC when
65409 +                                               and endpoint needs credits in order to transmit */
65410 +    int                 TxCreditSize;       /* size in bytes of each credit (set by HTC) */
65411 +    int                 TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */
65412 +    void                *pHTCReserved;      /* reserved for HTC use */
65413 +} HTC_ENDPOINT_CREDIT_DIST;
65414 +
65415 +#define HTC_EP_ACTIVE                            (1 << 31)
65416 +
65417 +/* macro to check if an endpoint has gone active, useful for credit
65418 + * distributions */
65419 +#define IS_EP_ACTIVE(epDist)  ((epDist)->DistFlags & HTC_EP_ACTIVE)
65420 +#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
65421 +
65422 +    /* credit distibution code that is passed into the distrbution function,
65423 +     * there are mandatory and optional codes that must be handled */
65424 +typedef enum _HTC_CREDIT_DIST_REASON {
65425 +    HTC_CREDIT_DIST_SEND_COMPLETE = 0,     /* credits available as a result of completed
65426 +                                              send operations (MANDATORY) resulting in credit reports */
65427 +    HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1,   /* a change in endpoint activity occured (OPTIONAL) */
65428 +    HTC_CREDIT_DIST_SEEK_CREDITS,          /* an endpoint needs to "seek" credits (OPTIONAL) */
65429 +    HTC_DUMP_CREDIT_STATE                  /* for debugging, dump any state information that is kept by
65430 +                                              the distribution function */
65431 +} HTC_CREDIT_DIST_REASON;
65432 +
65433 +typedef void (*HTC_CREDIT_DIST_CALLBACK)(void                     *Context,
65434 +                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
65435 +                                         HTC_CREDIT_DIST_REASON   Reason);
65436 +
65437 +typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
65438 +                                         HTC_ENDPOINT_CREDIT_DIST *pEPList,
65439 +                                         int                      TotalCredits);
65440 +
65441 +    /* endpoint statistics action */
65442 +typedef enum _HTC_ENDPOINT_STAT_ACTION {
65443 +    HTC_EP_STAT_SAMPLE = 0,                /* only read statistics */
65444 +    HTC_EP_STAT_SAMPLE_AND_CLEAR = 1,      /* sample and immediately clear statistics */
65445 +    HTC_EP_STAT_CLEAR                      /* clear only */
65446 +} HTC_ENDPOINT_STAT_ACTION;
65447 +
65448 +    /* endpoint statistics */
65449 +typedef struct _HTC_ENDPOINT_STATS {
65450 +    A_UINT32  TxCreditLowIndications;  /* number of times the host set the credit-low flag in a send message on
65451 +                                        this endpoint */
65452 +    A_UINT32  TxIssued;               /* running count of TX packets issued */
65453 +    A_UINT32  TxCreditRpts;           /* running count of total credit reports received for this endpoint */
65454 +    A_UINT32  TxCreditRptsFromRx;
65455 +    A_UINT32  TxCreditRptsFromOther;
65456 +    A_UINT32  TxCreditRptsFromEp0;
65457 +    A_UINT32  TxCreditsFromRx;        /* count of credits received via Rx packets on this endpoint */
65458 +    A_UINT32  TxCreditsFromOther;     /* count of credits received via another endpoint */
65459 +    A_UINT32  TxCreditsFromEp0;       /* count of credits received via another endpoint */
65460 +    A_UINT32  TxCreditsConsummed;     /* count of consummed credits */
65461 +    A_UINT32  TxCreditsReturned;      /* count of credits returned */
65462 +    A_UINT32  RxReceived;             /* count of RX packets received */
65463 +    A_UINT32  RxLookAheads;           /* count of lookahead records
65464 +                                         found in messages received on this endpoint */
65465 +} HTC_ENDPOINT_STATS;
65466 +
65467 +/* ------ Function Prototypes ------ */
65468 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65469 +  @desc: Initialize HTC
65470 +  @function name: HTCInit
65471 +  @input:  pInfo - initialization information
65472 +  @output:
65473 +  @return: A_OK on success
65474 +  @notes: The caller initializes global HTC state and registers various instance
65475 +          notification callbacks (see HTC_INIT_INFO).
65476 +
65477 +  @example:
65478 +  @see also: HTCShutdown
65479 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65480 +A_STATUS    HTCInit(HTC_INIT_INFO *pInfo);
65481 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65482 +  @desc: Get the underlying HIF device handle
65483 +  @function name: HTCGetHifDevice
65484 +  @input:  HTCHandle - handle passed into the AddInstance callback
65485 +  @output:
65486 +  @return: opaque HIF device handle usable in HIF API calls.
65487 +  @notes:
65488 +  @example:
65489 +  @see also:
65490 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65491 +void       *HTCGetHifDevice(HTC_HANDLE HTCHandle);
65492 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65493 +  @desc: Set the associated instance for the HTC handle
65494 +  @function name: HTCSetInstance
65495 +  @input:  HTCHandle - handle passed into the AddInstance callback
65496 +           Instance - caller supplied instance object
65497 +  @output:
65498 +  @return:
65499 +  @notes:  Caller must set the instance information for the HTC handle in order to receive
65500 +           notifications for instance deletion (DeleteInstance callback is called) and for target
65501 +           failure notification.
65502 +  @example:
65503 +  @see also:
65504 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65505 +void        HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance);
65506 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65507 +  @desc: Set credit distribution parameters
65508 +  @function name: HTCSetCreditDistribution
65509 +  @input:  HTCHandle - HTC handle
65510 +           pCreditDistCont - caller supplied context to pass into distribution functions
65511 +           CreditDistFunc - Distribution function callback
65512 +           CreditDistInit - Credit Distribution initialization callback
65513 +           ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
65514 +                                  priority
65515 +           ListLength - number of elements in ServicePriorityOrder
65516 +  @output:
65517 +  @return:
65518 +  @notes:  The user can set a custom credit distribution function to handle special requirements
65519 +           for each endpoint.  A default credit distribution routine can be used by setting
65520 +           CreditInitFunc to NULL.  The default credit distribution is only provided for simple
65521 +           "fair" credit distribution without regard to any prioritization.
65522 +
65523 +  @example:
65524 +  @see also:
65525 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65526 +void        HTCSetCreditDistribution(HTC_HANDLE               HTCHandle,
65527 +                                     void                     *pCreditDistContext,
65528 +                                     HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
65529 +                                     HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
65530 +                                     HTC_SERVICE_ID           ServicePriorityOrder[],
65531 +                                     int                      ListLength);
65532 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65533 +  @desc: Wait for the target to indicate the HTC layer is ready
65534 +  @function name: HTCWaitTarget
65535 +  @input:  HTCHandle - HTC handle
65536 +  @output:
65537 +  @return:
65538 +  @notes:  This API blocks until the target responds with an HTC ready message.
65539 +           The caller should not connect services until the target has indicated it is
65540 +           ready.
65541 +  @example:
65542 +  @see also: HTCConnectService
65543 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65544 +A_STATUS    HTCWaitTarget(HTC_HANDLE HTCHandle);
65545 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65546 +  @desc: Start target service communications
65547 +  @function name: HTCStart
65548 +  @input:  HTCHandle - HTC handle
65549 +  @output:
65550 +  @return:
65551 +  @notes: This API indicates to the target that the service connection phase is complete
65552 +          and the target can freely start all connected services.  This API should only be
65553 +          called AFTER all service connections have been made.  TCStart will issue a
65554 +          SETUP_COMPLETE message to the target to indicate that all service connections
65555 +          have been made and the target can start communicating over the endpoints.
65556 +  @example:
65557 +  @see also: HTCConnectService
65558 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65559 +A_STATUS    HTCStart(HTC_HANDLE HTCHandle);
65560 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65561 +  @desc: Add receive packet to HTC
65562 +  @function name: HTCAddReceivePkt
65563 +  @input:  HTCHandle - HTC handle
65564 +           pPacket - HTC receive packet to add
65565 +  @output:
65566 +  @return: A_OK on success
65567 +  @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
65568 +           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
65569 +           macro.
65570 +  @example:
65571 +  @see also:
65572 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65573 +A_STATUS    HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
65574 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65575 +  @desc: Connect to an HTC service
65576 +  @function name: HTCConnectService
65577 +  @input:  HTCHandle - HTC handle
65578 +           pReq - connection details
65579 +  @output: pResp - connection response
65580 +  @return:
65581 +  @notes:  Service connections must be performed before HTCStart.  User provides callback handlers
65582 +           for various endpoint events.
65583 +  @example:
65584 +  @see also: HTCStart
65585 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65586 +A_STATUS    HTCConnectService(HTC_HANDLE HTCHandle,
65587 +                              HTC_SERVICE_CONNECT_REQ  *pReq,
65588 +                              HTC_SERVICE_CONNECT_RESP *pResp);
65589 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65590 +  @desc: Send an HTC packet
65591 +  @function name: HTCSendPkt
65592 +  @input:  HTCHandle - HTC handle
65593 +           pPacket - packet to send
65594 +  @output:
65595 +  @return: A_OK
65596 +  @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
65597 +           This interface is fully asynchronous.  On error, HTC SendPkt will
65598 +           call the registered Endpoint callback to cleanup the packet.
65599 +  @example:
65600 +  @see also: HTCFlushEndpoint
65601 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65602 +A_STATUS    HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
65603 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65604 +  @desc: Stop HTC service communications
65605 +  @function name: HTCStop
65606 +  @input:  HTCHandle - HTC handle
65607 +  @output:
65608 +  @return:
65609 +  @notes: HTC communications is halted.  All receive and pending TX packets will
65610 +          be flushed.
65611 +  @example:
65612 +  @see also:
65613 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65614 +void        HTCStop(HTC_HANDLE HTCHandle);
65615 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65616 +  @desc: Shutdown HTC
65617 +  @function name: HTCShutdown
65618 +  @input:
65619 +  @output:
65620 +  @return:
65621 +  @notes:  This cleans up all resources allocated by HTCInit().
65622 +  @example:
65623 +  @see also: HTCInit
65624 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65625 +void        HTCShutDown(void);
65626 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65627 +  @desc: Flush pending TX packets
65628 +  @function name: HTCFlushEndpoint
65629 +  @input:  HTCHandle - HTC handle
65630 +           Endpoint - Endpoint to flush
65631 +           Tag - flush tag
65632 +  @output:
65633 +  @return:
65634 +  @notes:  The Tag parameter is used to selectively flush packets with matching tags.
65635 +           The value of 0 forces all packets to be flush regardless of tag.
65636 +  @example:
65637 +  @see also: HTCSendPkt
65638 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65639 +void        HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag);
65640 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65641 +  @desc: Dump credit distribution state
65642 +  @function name: HTCDumpCreditStates
65643 +  @input:  HTCHandle - HTC handle
65644 +  @output:
65645 +  @return:
65646 +  @notes:  This dumps all credit distribution information to the debugger
65647 +  @example:
65648 +  @see also:
65649 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65650 +void        HTCDumpCreditStates(HTC_HANDLE HTCHandle);
65651 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65652 +  @desc: Indicate a traffic activity change on an endpoint
65653 +  @function name: HTCIndicateActivityChange
65654 +  @input:  HTCHandle - HTC handle
65655 +           Endpoint - endpoint in which activity has changed
65656 +           Active - TRUE if active, FALSE if it has become inactive
65657 +  @output:
65658 +  @return:
65659 +  @notes:  This triggers the registered credit distribution function to
65660 +           re-adjust credits for active/inactive endpoints.
65661 +  @example:
65662 +  @see also:
65663 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65664 +void        HTCIndicateActivityChange(HTC_HANDLE      HTCHandle,
65665 +                                      HTC_ENDPOINT_ID Endpoint,
65666 +                                      A_BOOL          Active);
65667 +
65668 +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
65669 +  @desc: Get endpoint statistics
65670 +  @function name: HTCGetEndpointStatistics
65671 +  @input:  HTCHandle - HTC handle
65672 +           Endpoint - Endpoint identifier
65673 +           Action - action to take with statistics
65674 +  @output:
65675 +           pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
65676 +
65677 +  @return: TRUE if statistics profiling is enabled, otherwise FALSE.
65678 +
65679 +  @notes:  Statistics is a compile-time option and this function may return FALSE
65680 +           if HTC is not compiled with profiling.
65681 +
65682 +           The caller can specify the statistic "action" to take when sampling
65683 +           the statistics.  This includes:
65684 +
65685 +           HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
65686 +           HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
65687 +                             are cleared.
65688 +           HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
65689 +                   pStats
65690 +
65691 +  @example:
65692 +  @see also:
65693 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
65694 +A_BOOL       HTCGetEndpointStatistics(HTC_HANDLE               HTCHandle,
65695 +                                      HTC_ENDPOINT_ID          Endpoint,
65696 +                                      HTC_ENDPOINT_STAT_ACTION Action,
65697 +                                      HTC_ENDPOINT_STATS       *pStats);
65698 +
65699 +#ifdef __cplusplus
65700 +}
65701 +#endif
65702 +
65703 +#endif /* _HTC_API_H_ */
65704 Index: linux-2.6.28/drivers/ar6000/include/htc.h
65705 ===================================================================
65706 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
65707 +++ linux-2.6.28/drivers/ar6000/include/htc.h   2009-01-02 00:01:56.000000000 +0100
65708 @@ -0,0 +1,190 @@
65709 +/*
65710 + * Copyright (c) 2007 Atheros Communications Inc.
65711 + * All rights reserved.
65712 + *
65713 + * $ATH_LICENSE_HOSTSDK0_C$
65714 + *
65715 + */
65716 +
65717 +
65718 +#ifndef __HTC_H__
65719 +#define __HTC_H__
65720 +
65721 +#ifndef ATH_TARGET
65722 +#include "athstartpack.h"
65723 +#endif
65724 +
65725 +#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
65726 +
65727 +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
65728 +        (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
65729 +
65730 +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
65731 + * structure using only the type and field name.
65732 + * Use these macros if there is the potential for unaligned buffer accesses. */
65733 +#define A_GET_UINT16_FIELD(p,type,field) \
65734 +    ASSEMBLE_UNALIGNED_UINT16(p,\
65735 +                              A_OFFSETOF(type,field) + 1, \
65736 +                              A_OFFSETOF(type,field))
65737 +
65738 +#define A_SET_UINT16_FIELD(p,type,field,value) \
65739 +{                                              \
65740 +    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value);        \
65741 +    ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
65742 +}
65743 +
65744 +#define A_GET_UINT8_FIELD(p,type,field) \
65745 +            ((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
65746 +
65747 +#define A_SET_UINT8_FIELD(p,type,field,value) \
65748 +    ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
65749 +
65750 +/****** DANGER DANGER ***************
65751 + *
65752 + *   The frame header length and message formats defined herein were
65753 + *   selected to accommodate optimal alignment for target processing.  This reduces code
65754 + *   size and improves performance.
65755 + *
65756 + *   Any changes to the header length may alter the alignment and cause exceptions
65757 + *   on the target. When adding to the message structures insure that fields are
65758 + *   properly aligned.
65759 + *
65760 + */
65761 +
65762 +/* HTC frame header */
65763 +typedef PREPACK struct _HTC_FRAME_HDR{
65764 +        /* do not remove or re-arrange these fields, these are minimally required
65765 +         * to take advantage of 4-byte lookaheads in some hardware implementations */
65766 +    A_UINT8   EndpointID;
65767 +    A_UINT8   Flags;
65768 +    A_UINT16  PayloadLen;       /* length of data (including trailer) that follows the header */
65769 +
65770 +    /***** end of 4-byte lookahead ****/
65771 +
65772 +    A_UINT8   ControlBytes[2];
65773 +
65774 +    /* message payload starts after the header */
65775 +
65776 +} POSTPACK HTC_FRAME_HDR;
65777 +
65778 +/* frame header flags */
65779 +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
65780 +#define HTC_FLAGS_RECV_TRAILER       (1 << 1)
65781 +
65782 +
65783 +#define HTC_HDR_LENGTH  (sizeof(HTC_FRAME_HDR))
65784 +#define HTC_MAX_TRAILER_LENGTH   255
65785 +#define HTC_MAX_PAYLOAD_LENGTH   (2048 - sizeof(HTC_FRAME_HDR))
65786 +
65787 +/* HTC control message IDs */
65788 +typedef enum {
65789 +    HTC_MSG_READY_ID = 1,
65790 +    HTC_MSG_CONNECT_SERVICE_ID = 2,
65791 +    HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3,
65792 +    HTC_MSG_SETUP_COMPLETE_ID = 4,
65793 +} HTC_MSG_IDS;
65794 +
65795 +#define HTC_MAX_CONTROL_MESSAGE_LENGTH  256
65796 +
65797 +/* base message ID header */
65798 +typedef PREPACK struct {
65799 +    A_UINT16 MessageID;
65800 +} POSTPACK HTC_UNKNOWN_MSG;
65801 +
65802 +/* HTC ready message
65803 + * direction : target-to-host  */
65804 +typedef PREPACK struct {
65805 +    A_UINT16  MessageID;    /* ID */
65806 +    A_UINT16  CreditCount;  /* number of credits the target can offer */
65807 +    A_UINT16  CreditSize;   /* size of each credit */
65808 +    A_UINT8   MaxEndpoints; /* maximum number of endpoints the target has resources for */
65809 +    A_UINT8   _Pad1;
65810 +} POSTPACK HTC_READY_MSG;
65811 +
65812 +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
65813 +
65814 +/* connect service
65815 + * direction : host-to-target */
65816 +typedef PREPACK struct {
65817 +    A_UINT16  MessageID;
65818 +    A_UINT16  ServiceID;           /* service ID of the service to connect to */
65819 +    A_UINT16  ConnectionFlags;     /* connection flags */
65820 +
65821 +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)  /* reduce credit dribbling when
65822 +                                                             the host needs credits */
65823 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK             (0x3)
65824 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH        0x0
65825 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF          0x1
65826 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS     0x2
65827 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY             0x3
65828 +
65829 +    A_UINT8   ServiceMetaLength;   /* length of meta data that follows */
65830 +    A_UINT8   _Pad1;
65831 +
65832 +    /* service-specific meta data starts after the header */
65833 +
65834 +} POSTPACK HTC_CONNECT_SERVICE_MSG;
65835 +
65836 +/* connect response
65837 + * direction : target-to-host */
65838 +typedef PREPACK struct {
65839 +    A_UINT16  MessageID;
65840 +    A_UINT16  ServiceID;            /* service ID that the connection request was made */
65841 +    A_UINT8   Status;               /* service connection status */
65842 +    A_UINT8   EndpointID;           /* assigned endpoint ID */
65843 +    A_UINT16  MaxMsgSize;           /* maximum expected message size on this endpoint */
65844 +    A_UINT8   ServiceMetaLength;    /* length of meta data that follows */
65845 +    A_UINT8   _Pad1;
65846 +
65847 +    /* service-specific meta data starts after the header */
65848 +
65849 +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
65850 +
65851 +typedef PREPACK struct {
65852 +    A_UINT16  MessageID;
65853 +    /* currently, no other fields */
65854 +} POSTPACK HTC_SETUP_COMPLETE_MSG;
65855 +
65856 +
65857 +/* connect response status codes */
65858 +#define HTC_SERVICE_SUCCESS      0  /* success */
65859 +#define HTC_SERVICE_NOT_FOUND    1  /* service could not be found */
65860 +#define HTC_SERVICE_FAILED       2  /* specific service failed the connect */
65861 +#define HTC_SERVICE_NO_RESOURCES 3  /* no resources (i.e. no more endpoints) */
65862 +#define HTC_SERVICE_NO_MORE_EP   4  /* specific service is not allowing any more
65863 +                                       endpoints */
65864 +
65865 +/* report record IDs */
65866 +typedef enum {
65867 +    HTC_RECORD_NULL  = 0,
65868 +    HTC_RECORD_CREDITS   = 1,
65869 +    HTC_RECORD_LOOKAHEAD = 2,
65870 +} HTC_RPT_IDS;
65871 +
65872 +typedef PREPACK struct {
65873 +    A_UINT8 RecordID;     /* Record ID */
65874 +    A_UINT8 Length;       /* Length of record */
65875 +} POSTPACK HTC_RECORD_HDR;
65876 +
65877 +typedef PREPACK struct {
65878 +    A_UINT8 EndpointID;     /* Endpoint that owns these credits */
65879 +    A_UINT8 Credits;        /* credits to report since last report */
65880 +} POSTPACK HTC_CREDIT_REPORT;
65881 +
65882 +typedef PREPACK struct {
65883 +    A_UINT8 PreValid;         /* pre valid guard */
65884 +    A_UINT8 LookAhead[4];     /* 4 byte lookahead */
65885 +    A_UINT8 PostValid;        /* post valid guard */
65886 +
65887 +   /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
65888 +    * The PreValid bytes must equal the inverse of the PostValid byte */
65889 +
65890 +} POSTPACK HTC_LOOKAHEAD_REPORT;
65891 +
65892 +#ifndef ATH_TARGET
65893 +#include "athendpack.h"
65894 +#endif
65895 +
65896 +
65897 +#endif /* __HTC_H__ */
65898 +
65899 Index: linux-2.6.28/drivers/ar6000/include/htc_packet.h
65900 ===================================================================
65901 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
65902 +++ linux-2.6.28/drivers/ar6000/include/htc_packet.h    2009-01-02 00:01:56.000000000 +0100
65903 @@ -0,0 +1,138 @@
65904 +/*
65905 + *
65906 + * Copyright (c) 2007 Atheros Communications Inc.
65907 + * All rights reserved.
65908 + *
65909 + *
65910 + *  This program is free software; you can redistribute it and/or modify
65911 + *  it under the terms of the GNU General Public License version 2 as
65912 + *  published by the Free Software Foundation;
65913 + *
65914 + *  Software distributed under the License is distributed on an "AS
65915 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
65916 + *  implied. See the License for the specific language governing
65917 + *  rights and limitations under the License.
65918 + *
65919 + *
65920 + *
65921 + */
65922 +
65923 +#ifndef HTC_PACKET_H_
65924 +#define HTC_PACKET_H_
65925 +
65926 +
65927 +#include "dl_list.h"
65928 +
65929 +struct _HTC_PACKET;
65930 +
65931 +typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *);
65932 +
65933 +typedef A_UINT16 HTC_TX_TAG;
65934 +
65935 +typedef struct _HTC_TX_PACKET_INFO {
65936 +    HTC_TX_TAG    Tag;            /* tag used to selective flush packets */
65937 +} HTC_TX_PACKET_INFO;
65938 +
65939 +#define HTC_TX_PACKET_TAG_ALL          0    /* a tag of zero is reserved and used to flush ALL packets */
65940 +#define HTC_TX_PACKET_TAG_INTERNAL     1                                /* internal tags start here */
65941 +#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
65942 +
65943 +typedef struct _HTC_RX_PACKET_INFO {
65944 +    A_UINT32    Unused;          /* for future use and to make compilers happy */
65945 +} HTC_RX_PACKET_INFO;
65946 +
65947 +/* wrapper around endpoint-specific packets */
65948 +typedef struct _HTC_PACKET {
65949 +    DL_LIST         ListLink;       /* double link */
65950 +    void            *pPktContext;   /* caller's per packet specific context */
65951 +
65952 +    A_UINT8         *pBufferStart;  /* the true buffer start , the caller can
65953 +                                       store the real buffer start here.  In
65954 +                                       receive callbacks, the HTC layer sets pBuffer
65955 +                                       to the start of the payload past the header. This
65956 +                                       field allows the caller to reset pBuffer when it
65957 +                                       recycles receive packets back to HTC */
65958 +    /*
65959 +     * Pointer to the start of the buffer. In the transmit
65960 +     * direction this points to the start of the payload. In the
65961 +     * receive direction, however, the buffer when queued up
65962 +     * points to the start of the HTC header but when returned
65963 +     * to the caller points to the start of the payload
65964 +     */
65965 +    A_UINT8         *pBuffer;       /* payload start (RX/TX) */
65966 +    A_UINT32        BufferLength;   /* length of buffer */
65967 +    A_UINT32        ActualLength;   /* actual length of payload */
65968 +    int             Endpoint;       /* endpoint that this packet was sent/recv'd from */
65969 +    A_STATUS        Status;         /* completion status */
65970 +    union {
65971 +        HTC_TX_PACKET_INFO  AsTx;   /* Tx Packet specific info */
65972 +        HTC_RX_PACKET_INFO  AsRx;   /* Rx Packet specific info */
65973 +    } PktInfo;
65974 +
65975 +    /* the following fields are for internal HTC use */
65976 +    HTC_PACKET_COMPLETION Completion;   /* completion */
65977 +    void                  *pContext;    /* HTC private completion context */
65978 +    A_UINT32              HTCReserved;  /* reserved */
65979 +} HTC_PACKET;
65980 +
65981 +
65982 +
65983 +#define COMPLETE_HTC_PACKET(p,status)        \
65984 +{                                            \
65985 +    (p)->Status = (status);                  \
65986 +    (p)->Completion((p)->pContext,(p));      \
65987 +}
65988 +
65989 +#define INIT_HTC_PACKET_INFO(p,b,len)             \
65990 +{                                                 \
65991 +    (p)->pBufferStart = (b);                      \
65992 +    (p)->BufferLength = (len);                    \
65993 +}
65994 +
65995 +/* macro to set an initial RX packet for refilling HTC */
65996 +#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
65997 +{                                                 \
65998 +    (p)->pPktContext = (c);                       \
65999 +    (p)->pBuffer = (b);                           \
66000 +    (p)->pBufferStart = (b);                      \
66001 +    (p)->BufferLength = (len);                    \
66002 +    (p)->Endpoint = (ep);                         \
66003 +}
66004 +
66005 +/* fast macro to recycle an RX packet that will be re-queued to HTC */
66006 +#define HTC_PACKET_RESET_RX(p)              \
66007 +    (p)->pBuffer = (p)->pBufferStart
66008 +
66009 +/* macro to set packet parameters for TX */
66010 +#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag)  \
66011 +{                                                 \
66012 +    (p)->pPktContext = (c);                       \
66013 +    (p)->pBuffer = (b);                           \
66014 +    (p)->ActualLength = (len);                    \
66015 +    (p)->Endpoint = (ep);                         \
66016 +    (p)->PktInfo.AsTx.Tag = (tag);                \
66017 +}
66018 +
66019 +/* HTC Packet Queueing Macros */
66020 +typedef DL_LIST HTC_PACKET_QUEUE;
66021 +/* initialize queue */
66022 +#define INIT_HTC_PACKET_QUEUE(pQ) DL_LIST_INIT((pQ))
66023 +/* enqueue HTC packet to the tail of the queue */
66024 +#define HTC_PACKET_ENQUEUE(pQ,p)  DL_ListInsertTail((pQ),&(p)->ListLink)
66025 +/* test if a queue is empty */
66026 +#define HTC_QUEUE_EMPTY(pQ)       DL_LIST_IS_EMPTY((pQ))
66027 +/* get packet at head without removing it */
66028 +#define HTC_GET_PKT_AT_HEAD(pQ)   A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(pQ)),HTC_PACKET,ListLink);
66029 +/* remove a packet from the current list it is linked to */
66030 +#define HTC_PACKET_REMOVE(p)      DL_ListRemove(&(p)->ListLink)
66031 +
66032 +/* dequeue an HTC packet from the head of the queue */
66033 +static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) {
66034 +    DL_LIST    *pItem = DL_ListRemoveItemFromHead(queue);
66035 +    if (pItem != NULL) {
66036 +        return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
66037 +    }
66038 +    return NULL;
66039 +}
66040 +
66041 +#endif /*HTC_PACKET_H_*/
66042 Index: linux-2.6.28/drivers/ar6000/include/htc_services.h
66043 ===================================================================
66044 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66045 +++ linux-2.6.28/drivers/ar6000/include/htc_services.h  2009-01-02 00:01:56.000000000 +0100
66046 @@ -0,0 +1,37 @@
66047 +/*
66048 + * Copyright (c) 2007 Atheros Communications Inc.
66049 + * All rights reserved.
66050 + *
66051 + * $ATH_LICENSE_HOSTSDK0_C$
66052 + *
66053 + */
66054 +
66055 +#ifndef __HTC_SERVICES_H__
66056 +#define __HTC_SERVICES_H__
66057 +
66058 +/* Current service IDs */
66059 +
66060 +typedef enum {
66061 +    RSVD_SERVICE_GROUP  = 0,
66062 +    WMI_SERVICE_GROUP   = 1,
66063 +
66064 +    HTC_TEST_GROUP = 254,
66065 +    HTC_SERVICE_GROUP_LAST = 255
66066 +}HTC_SERVICE_GROUP_IDS;
66067 +
66068 +#define MAKE_SERVICE_ID(group,index) \
66069 +            (int)(((int)group << 8) | (int)(index))
66070 +
66071 +/* NOTE: service ID of 0x0000 is reserved and should never be used */
66072 +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
66073 +#define WMI_CONTROL_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
66074 +#define WMI_DATA_BE_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
66075 +#define WMI_DATA_BK_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
66076 +#define WMI_DATA_VI_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
66077 +#define WMI_DATA_VO_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
66078 +#define WMI_MAX_SERVICES  5
66079 +
66080 +/* raw stream service (i.e. flash, tcmd, calibration apps) */
66081 +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
66082 +
66083 +#endif /*HTC_SERVICES_H_*/
66084 Index: linux-2.6.28/drivers/ar6000/include/ieee80211.h
66085 ===================================================================
66086 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66087 +++ linux-2.6.28/drivers/ar6000/include/ieee80211.h     2009-01-02 00:01:56.000000000 +0100
66088 @@ -0,0 +1,342 @@
66089 +/*-
66090 + * Copyright (c) 2001 Atsushi Onoe
66091 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
66092 + * Copyright (c) 2006 Atheros Communications, Inc.
66093 + *
66094 + * Wireless Network driver for Atheros AR6001
66095 + * All rights reserved.
66096 + *
66097 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
66098 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
66099 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
66100 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
66101 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
66102 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
66103 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
66104 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
66105 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66106 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66107 + *
66108 + */
66109 +#ifndef _NET80211_IEEE80211_H_
66110 +#define _NET80211_IEEE80211_H_
66111 +
66112 +#include "athstartpack.h"
66113 +
66114 +/*
66115 + * 802.11 protocol definitions.
66116 + */
66117 +
66118 +#define IEEE80211_ADDR_LEN  6       /* size of 802.11 address */
66119 +/* is 802.11 address multicast/broadcast? */
66120 +#define IEEE80211_IS_MULTICAST(_a)  (*(_a) & 0x01)
66121 +#define IEEE80211_ADDR_EQ(addr1, addr2)     \
66122 +    (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
66123 +
66124 +#define IEEE80211_KEYBUF_SIZE 16
66125 +#define IEEE80211_MICBUF_SIZE (8+8)  /* space for both tx and rx */
66126 +
66127 +/*
66128 + * NB: these values are ordered carefully; there are lots of
66129 + * of implications in any reordering.  In particular beware
66130 + * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
66131 + */
66132 +#define IEEE80211_CIPHER_WEP            0
66133 +#define IEEE80211_CIPHER_TKIP           1
66134 +#define IEEE80211_CIPHER_AES_OCB        2
66135 +#define IEEE80211_CIPHER_AES_CCM        3
66136 +#define IEEE80211_CIPHER_CKIP           5
66137 +#define IEEE80211_CIPHER_CCKM_KRK       6
66138 +#define IEEE80211_CIPHER_NONE           7       /* pseudo value */
66139 +
66140 +#define IEEE80211_CIPHER_MAX            (IEEE80211_CIPHER_NONE+1)
66141 +
66142 +#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
66143 +        (((len) == 5) || ((len) == 13) || ((len) == 16))
66144 +
66145 +
66146 +
66147 +/*
66148 + * generic definitions for IEEE 802.11 frames
66149 + */
66150 +PREPACK struct ieee80211_frame {
66151 +    A_UINT8    i_fc[2];
66152 +    A_UINT8    i_dur[2];
66153 +    A_UINT8    i_addr1[IEEE80211_ADDR_LEN];
66154 +    A_UINT8    i_addr2[IEEE80211_ADDR_LEN];
66155 +    A_UINT8    i_addr3[IEEE80211_ADDR_LEN];
66156 +    A_UINT8    i_seq[2];
66157 +    /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
66158 +    /* see below */
66159 +} POSTPACK;
66160 +
66161 +#define IEEE80211_FC0_VERSION_MASK          0x03
66162 +#define IEEE80211_FC0_VERSION_SHIFT         0
66163 +#define IEEE80211_FC0_VERSION_0             0x00
66164 +#define IEEE80211_FC0_TYPE_MASK             0x0c
66165 +#define IEEE80211_FC0_TYPE_SHIFT            2
66166 +#define IEEE80211_FC0_TYPE_MGT              0x00
66167 +#define IEEE80211_FC0_TYPE_CTL              0x04
66168 +#define IEEE80211_FC0_TYPE_DATA             0x08
66169 +
66170 +#define IEEE80211_FC0_SUBTYPE_MASK          0xf0
66171 +#define IEEE80211_FC0_SUBTYPE_SHIFT         4
66172 +/* for TYPE_MGT */
66173 +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ     0x00
66174 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP    0x10
66175 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ   0x20
66176 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP  0x30
66177 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ     0x40
66178 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP    0x50
66179 +#define IEEE80211_FC0_SUBTYPE_BEACON        0x80
66180 +#define IEEE80211_FC0_SUBTYPE_ATIM          0x90
66181 +#define IEEE80211_FC0_SUBTYPE_DISASSOC      0xa0
66182 +#define IEEE80211_FC0_SUBTYPE_AUTH          0xb0
66183 +#define IEEE80211_FC0_SUBTYPE_DEAUTH        0xc0
66184 +/* for TYPE_CTL */
66185 +#define IEEE80211_FC0_SUBTYPE_PS_POLL       0xa0
66186 +#define IEEE80211_FC0_SUBTYPE_RTS           0xb0
66187 +#define IEEE80211_FC0_SUBTYPE_CTS           0xc0
66188 +#define IEEE80211_FC0_SUBTYPE_ACK           0xd0
66189 +#define IEEE80211_FC0_SUBTYPE_CF_END        0xe0
66190 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK    0xf0
66191 +/* for TYPE_DATA (bit combination) */
66192 +#define IEEE80211_FC0_SUBTYPE_DATA          0x00
66193 +#define IEEE80211_FC0_SUBTYPE_CF_ACK        0x10
66194 +#define IEEE80211_FC0_SUBTYPE_CF_POLL       0x20
66195 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL       0x30
66196 +#define IEEE80211_FC0_SUBTYPE_NODATA        0x40
66197 +#define IEEE80211_FC0_SUBTYPE_CFACK         0x50
66198 +#define IEEE80211_FC0_SUBTYPE_CFPOLL        0x60
66199 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
66200 +#define IEEE80211_FC0_SUBTYPE_QOS           0x80
66201 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL      0xc0
66202 +
66203 +#define IEEE80211_FC1_DIR_MASK              0x03
66204 +#define IEEE80211_FC1_DIR_NODS              0x00    /* STA->STA */
66205 +#define IEEE80211_FC1_DIR_TODS              0x01    /* STA->AP  */
66206 +#define IEEE80211_FC1_DIR_FROMDS            0x02    /* AP ->STA */
66207 +#define IEEE80211_FC1_DIR_DSTODS            0x03    /* AP ->AP  */
66208 +
66209 +#define IEEE80211_FC1_MORE_FRAG             0x04
66210 +#define IEEE80211_FC1_RETRY                 0x08
66211 +#define IEEE80211_FC1_PWR_MGT               0x10
66212 +#define IEEE80211_FC1_MORE_DATA             0x20
66213 +#define IEEE80211_FC1_WEP                   0x40
66214 +#define IEEE80211_FC1_ORDER                 0x80
66215 +
66216 +#define IEEE80211_SEQ_FRAG_MASK             0x000f
66217 +#define IEEE80211_SEQ_FRAG_SHIFT            0
66218 +#define IEEE80211_SEQ_SEQ_MASK              0xfff0
66219 +#define IEEE80211_SEQ_SEQ_SHIFT             4
66220 +
66221 +#define IEEE80211_NWID_LEN                  32
66222 +
66223 +/*
66224 + * 802.11 rate set.
66225 + */
66226 +#define IEEE80211_RATE_SIZE     8       /* 802.11 standard */
66227 +#define IEEE80211_RATE_MAXSIZE  15      /* max rates we'll handle */
66228 +
66229 +#define WMM_NUM_AC                  4   /* 4 AC categories */
66230 +
66231 +#define WMM_PARAM_ACI_M         0x60    /* Mask for ACI field */
66232 +#define WMM_PARAM_ACI_S         5   /* Shift for ACI field */
66233 +#define WMM_PARAM_ACM_M         0x10    /* Mask for ACM bit */
66234 +#define WMM_PARAM_ACM_S         4       /* Shift for ACM bit */
66235 +#define WMM_PARAM_AIFSN_M       0x0f    /* Mask for aifsn field */
66236 +#define WMM_PARAM_LOGCWMIN_M    0x0f    /* Mask for CwMin field (in log) */
66237 +#define WMM_PARAM_LOGCWMAX_M    0xf0    /* Mask for CwMax field (in log) */
66238 +#define WMM_PARAM_LOGCWMAX_S    4   /* Shift for CwMax field */
66239 +
66240 +#define WMM_AC_TO_TID(_ac) (       \
66241 +    ((_ac) == WMM_AC_VO) ? 6 : \
66242 +    ((_ac) == WMM_AC_VI) ? 5 : \
66243 +    ((_ac) == WMM_AC_BK) ? 1 : \
66244 +    0)
66245 +
66246 +#define TID_TO_WMM_AC(_tid) (      \
66247 +    ((_tid) < 1) ? WMM_AC_BE : \
66248 +    ((_tid) < 3) ? WMM_AC_BK : \
66249 +    ((_tid) < 6) ? WMM_AC_VI : \
66250 +    WMM_AC_VO)
66251 +/*
66252 + * Management information element payloads.
66253 + */
66254 +
66255 +enum {
66256 +    IEEE80211_ELEMID_SSID       = 0,
66257 +    IEEE80211_ELEMID_RATES      = 1,
66258 +    IEEE80211_ELEMID_FHPARMS    = 2,
66259 +    IEEE80211_ELEMID_DSPARMS    = 3,
66260 +    IEEE80211_ELEMID_CFPARMS    = 4,
66261 +    IEEE80211_ELEMID_TIM        = 5,
66262 +    IEEE80211_ELEMID_IBSSPARMS  = 6,
66263 +    IEEE80211_ELEMID_COUNTRY    = 7,
66264 +    IEEE80211_ELEMID_CHALLENGE  = 16,
66265 +    /* 17-31 reserved for challenge text extension */
66266 +    IEEE80211_ELEMID_PWRCNSTR   = 32,
66267 +    IEEE80211_ELEMID_PWRCAP     = 33,
66268 +    IEEE80211_ELEMID_TPCREQ     = 34,
66269 +    IEEE80211_ELEMID_TPCREP     = 35,
66270 +    IEEE80211_ELEMID_SUPPCHAN   = 36,
66271 +    IEEE80211_ELEMID_CHANSWITCH = 37,
66272 +    IEEE80211_ELEMID_MEASREQ    = 38,
66273 +    IEEE80211_ELEMID_MEASREP    = 39,
66274 +    IEEE80211_ELEMID_QUIET      = 40,
66275 +    IEEE80211_ELEMID_IBSSDFS    = 41,
66276 +    IEEE80211_ELEMID_ERP        = 42,
66277 +    IEEE80211_ELEMID_RSN        = 48,
66278 +    IEEE80211_ELEMID_XRATES     = 50,
66279 +    IEEE80211_ELEMID_TPC        = 150,
66280 +    IEEE80211_ELEMID_CCKM       = 156,
66281 +    IEEE80211_ELEMID_VENDOR     = 221,  /* vendor private */
66282 +};
66283 +
66284 +#define ATH_OUI             0x7f0300        /* Atheros OUI */
66285 +#define ATH_OUI_TYPE        0x01
66286 +#define ATH_OUI_SUBTYPE     0x01
66287 +#define ATH_OUI_VERSION     0x00
66288 +
66289 +#define WPA_OUI             0xf25000
66290 +#define WPA_OUI_TYPE        0x01
66291 +#define WPA_VERSION         1          /* current supported version */
66292 +
66293 +#define WPA_CSE_NULL        0x00
66294 +#define WPA_CSE_WEP40       0x01
66295 +#define WPA_CSE_TKIP        0x02
66296 +#define WPA_CSE_CCMP        0x04
66297 +#define WPA_CSE_WEP104      0x05
66298 +
66299 +#define WPA_ASE_NONE        0x00
66300 +#define WPA_ASE_8021X_UNSPEC    0x01
66301 +#define WPA_ASE_8021X_PSK   0x02
66302 +
66303 +#define RSN_OUI         0xac0f00
66304 +#define RSN_VERSION     1       /* current supported version */
66305 +
66306 +#define RSN_CSE_NULL        0x00
66307 +#define RSN_CSE_WEP40       0x01
66308 +#define RSN_CSE_TKIP        0x02
66309 +#define RSN_CSE_WRAP        0x03
66310 +#define RSN_CSE_CCMP        0x04
66311 +#define RSN_CSE_WEP104      0x05
66312 +
66313 +#define RSN_ASE_NONE        0x00
66314 +#define RSN_ASE_8021X_UNSPEC    0x01
66315 +#define RSN_ASE_8021X_PSK   0x02
66316 +
66317 +#define RSN_CAP_PREAUTH     0x01
66318 +
66319 +#define WMM_OUI         0xf25000
66320 +#define WMM_OUI_TYPE        0x02
66321 +#define WMM_INFO_OUI_SUBTYPE    0x00
66322 +#define WMM_PARAM_OUI_SUBTYPE   0x01
66323 +#define WMM_VERSION     1
66324 +
66325 +/* WMM stream classes */
66326 +#define WMM_NUM_AC  4
66327 +#define WMM_AC_BE   0       /* best effort */
66328 +#define WMM_AC_BK   1       /* background */
66329 +#define WMM_AC_VI   2       /* video */
66330 +#define WMM_AC_VO   3       /* voice */
66331 +
66332 +/* TSPEC related */
66333 +#define ACTION_CATEGORY_CODE_TSPEC                 17
66334 +#define ACTION_CODE_TSPEC_ADDTS                    0
66335 +#define ACTION_CODE_TSPEC_ADDTS_RESP               1
66336 +#define ACTION_CODE_TSPEC_DELTS                    2
66337 +
66338 +typedef enum {
66339 +    TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
66340 +    TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
66341 +    TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
66342 +    TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
66343 +    TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
66344 +    TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
66345 +    TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
66346 +    TSPEC_STATUS_CODE_DELTS_SENT    = 0x30,
66347 +    TSPEC_STATUS_CODE_DELTS_RECV    = 0x31,
66348 +} TSPEC_STATUS_CODE;
66349 +
66350 +/*
66351 + * WMM/802.11e Tspec Element
66352 + */
66353 +typedef PREPACK struct wmm_tspec_ie_t {
66354 +    A_UINT8     elementId;
66355 +    A_UINT8     len;
66356 +    A_UINT8     oui[3];
66357 +    A_UINT8     ouiType;
66358 +    A_UINT8     ouiSubType;
66359 +    A_UINT8     version;
66360 +    A_UINT16    tsInfo_info;
66361 +    A_UINT8     tsInfo_reserved;
66362 +    A_UINT16    nominalMSDU;
66363 +    A_UINT16    maxMSDU;
66364 +    A_UINT32    minServiceInt;
66365 +    A_UINT32    maxServiceInt;
66366 +    A_UINT32    inactivityInt;
66367 +    A_UINT32    suspensionInt;
66368 +    A_UINT32    serviceStartTime;
66369 +    A_UINT32    minDataRate;
66370 +    A_UINT32    meanDataRate;
66371 +    A_UINT32    peakDataRate;
66372 +    A_UINT32    maxBurstSize;
66373 +    A_UINT32    delayBound;
66374 +    A_UINT32    minPhyRate;
66375 +    A_UINT16    sba;
66376 +    A_UINT16    mediumTime;
66377 +} POSTPACK WMM_TSPEC_IE;
66378 +
66379 +
66380 +/*
66381 + * BEACON management packets
66382 + *
66383 + *  octet timestamp[8]
66384 + *  octet beacon interval[2]
66385 + *  octet capability information[2]
66386 + *  information element
66387 + *      octet elemid
66388 + *      octet length
66389 + *      octet information[length]
66390 + */
66391 +
66392 +#define IEEE80211_BEACON_INTERVAL(beacon) \
66393 +    ((beacon)[8] | ((beacon)[9] << 8))
66394 +#define IEEE80211_BEACON_CAPABILITY(beacon) \
66395 +    ((beacon)[10] | ((beacon)[11] << 8))
66396 +
66397 +#define IEEE80211_CAPINFO_ESS               0x0001
66398 +#define IEEE80211_CAPINFO_IBSS              0x0002
66399 +#define IEEE80211_CAPINFO_CF_POLLABLE       0x0004
66400 +#define IEEE80211_CAPINFO_CF_POLLREQ        0x0008
66401 +#define IEEE80211_CAPINFO_PRIVACY           0x0010
66402 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE    0x0020
66403 +#define IEEE80211_CAPINFO_PBCC              0x0040
66404 +#define IEEE80211_CAPINFO_CHNL_AGILITY      0x0080
66405 +/* bits 8-9 are reserved */
66406 +#define IEEE80211_CAPINFO_SHORT_SLOTTIME    0x0400
66407 +#define IEEE80211_CAPINFO_APSD              0x0800
66408 +/* bit 12 is reserved */
66409 +#define IEEE80211_CAPINFO_DSSSOFDM          0x2000
66410 +/* bits 14-15 are reserved */
66411 +
66412 +/*
66413 + * Authentication Modes
66414 + */
66415 +
66416 +enum ieee80211_authmode {
66417 +    IEEE80211_AUTH_NONE     = 0,
66418 +    IEEE80211_AUTH_OPEN     = 1,
66419 +    IEEE80211_AUTH_SHARED   = 2,
66420 +    IEEE80211_AUTH_8021X    = 3,
66421 +    IEEE80211_AUTH_AUTO     = 4,   /* auto-select/accept */
66422 +    /* NB: these are used only for ioctls */
66423 +    IEEE80211_AUTH_WPA      = 5,  /* WPA/RSN  w/ 802.1x */
66424 +    IEEE80211_AUTH_WPA_PSK  = 6,  /* WPA/RSN  w/ PSK */
66425 +    IEEE80211_AUTH_WPA_CCKM = 7,  /* WPA/RSN IE  w/ CCKM */
66426 +};
66427 +
66428 +#include "athendpack.h"
66429 +
66430 +#endif /* _NET80211_IEEE80211_H_ */
66431 Index: linux-2.6.28/drivers/ar6000/include/ieee80211_ioctl.h
66432 ===================================================================
66433 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66434 +++ linux-2.6.28/drivers/ar6000/include/ieee80211_ioctl.h       2009-01-02 00:01:56.000000000 +0100
66435 @@ -0,0 +1,163 @@
66436 +/*
66437 + * Copyright (c) 2004-2005 Atheros Communications Inc.
66438 + * All rights reserved.
66439 + *
66440 + *
66441 + *  This program is free software; you can redistribute it and/or modify
66442 + *  it under the terms of the GNU General Public License version 2 as
66443 + *  published by the Free Software Foundation;
66444 + *
66445 + *  Software distributed under the License is distributed on an "AS
66446 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
66447 + *  implied. See the License for the specific language governing
66448 + *  rights and limitations under the License.
66449 + *
66450 + *
66451 + *
66452 + *
66453 + * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/ieee80211_ioctl.h#1 $
66454 + */
66455 +
66456 +#ifndef _IEEE80211_IOCTL_H_
66457 +#define _IEEE80211_IOCTL_H_
66458 +
66459 +#ifdef __cplusplus
66460 +extern "C" {
66461 +#endif
66462 +
66463 +/*
66464 + * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
66465 + */
66466 +
66467 +/*
66468 + * WPA/RSN get/set key request.  Specify the key/cipher
66469 + * type and whether the key is to be used for sending and/or
66470 + * receiving.  The key index should be set only when working
66471 + * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
66472 + * Otherwise a unicast/pairwise key is specified by the bssid
66473 + * (on a station) or mac address (on an ap).  They key length
66474 + * must include any MIC key data; otherwise it should be no
66475 + more than IEEE80211_KEYBUF_SIZE.
66476 + */
66477 +struct ieee80211req_key {
66478 +       u_int8_t        ik_type;        /* key/cipher type */
66479 +       u_int8_t        ik_pad;
66480 +       u_int16_t       ik_keyix;       /* key index */
66481 +       u_int8_t        ik_keylen;      /* key length in bytes */
66482 +       u_int8_t        ik_flags;
66483 +#define IEEE80211_KEY_XMIT  0x01
66484 +#define IEEE80211_KEY_RECV  0x02
66485 +#define        IEEE80211_KEY_DEFAULT   0x80    /* default xmit key */
66486 +       u_int8_t        ik_macaddr[IEEE80211_ADDR_LEN];
66487 +       u_int64_t       ik_keyrsc;      /* key receive sequence counter */
66488 +       u_int64_t       ik_keytsc;      /* key transmit sequence counter */
66489 +       u_int8_t        ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
66490 +};
66491 +/*
66492 + * Delete a key either by index or address.  Set the index
66493 + * to IEEE80211_KEYIX_NONE when deleting a unicast key.
66494 + */
66495 +struct ieee80211req_del_key {
66496 +       u_int8_t        idk_keyix;      /* key index */
66497 +       u_int8_t        idk_macaddr[IEEE80211_ADDR_LEN];
66498 +};
66499 +/*
66500 + * MLME state manipulation request.  IEEE80211_MLME_ASSOC
66501 + * only makes sense when operating as a station.  The other
66502 + * requests can be used when operating as a station or an
66503 + * ap (to effect a station).
66504 + */
66505 +struct ieee80211req_mlme {
66506 +       u_int8_t        im_op;          /* operation to perform */
66507 +#define        IEEE80211_MLME_ASSOC            1       /* associate station */
66508 +#define        IEEE80211_MLME_DISASSOC         2       /* disassociate station */
66509 +#define        IEEE80211_MLME_DEAUTH           3       /* deauthenticate station */
66510 +#define        IEEE80211_MLME_AUTHORIZE        4       /* authorize station */
66511 +#define        IEEE80211_MLME_UNAUTHORIZE      5       /* unauthorize station */
66512 +       u_int16_t       im_reason;      /* 802.11 reason code */
66513 +       u_int8_t        im_macaddr[IEEE80211_ADDR_LEN];
66514 +};
66515 +
66516 +struct ieee80211req_addpmkid {
66517 +    u_int8_t    pi_bssid[IEEE80211_ADDR_LEN];
66518 +    u_int8_t    pi_enable;
66519 +    u_int8_t    pi_pmkid[16];
66520 +};
66521 +
66522 +#define AUTH_ALG_OPEN_SYSTEM   0x01
66523 +#define AUTH_ALG_SHARED_KEY    0x02
66524 +#define AUTH_ALG_LEAP          0x04
66525 +
66526 +struct ieee80211req_authalg {
66527 +   u_int8_t auth_alg;
66528 +};
66529 +
66530 +/*
66531 + * Request to add an IE to a Management Frame
66532 + */
66533 +enum{
66534 +    IEEE80211_APPIE_FRAME_BEACON     = 0,
66535 +    IEEE80211_APPIE_FRAME_PROBE_REQ  = 1,
66536 +    IEEE80211_APPIE_FRAME_PROBE_RESP = 2,
66537 +    IEEE80211_APPIE_FRAME_ASSOC_REQ  = 3,
66538 +    IEEE80211_APPIE_FRAME_ASSOC_RESP = 4,
66539 +    IEEE80211_APPIE_NUM_OF_FRAME     = 5
66540 +};
66541 +
66542 +/*
66543 + * The Maximum length of the IE that can be added to a Management frame
66544 + */
66545 +#define IEEE80211_APPIE_FRAME_MAX_LEN  78
66546 +
66547 +struct ieee80211req_getset_appiebuf {
66548 +    u_int32_t app_frmtype; /* management frame type for which buffer is added */
66549 +    u_int32_t app_buflen;  /*application supplied buffer length */
66550 +    u_int8_t  app_buf[];
66551 +};
66552 +
66553 +/*
66554 + * The following definitions are used by an application to set filter
66555 + * for receiving management frames
66556 + */
66557 +enum {
66558 +     IEEE80211_FILTER_TYPE_BEACON      =   0x1,
66559 +     IEEE80211_FILTER_TYPE_PROBE_REQ   =   0x2,
66560 +     IEEE80211_FILTER_TYPE_PROBE_RESP  =   0x4,
66561 +     IEEE80211_FILTER_TYPE_ASSOC_REQ   =   0x8,
66562 +     IEEE80211_FILTER_TYPE_ASSOC_RESP  =   0x10,
66563 +     IEEE80211_FILTER_TYPE_AUTH        =   0x20,
66564 +     IEEE80211_FILTER_TYPE_DEAUTH      =   0x40,
66565 +     IEEE80211_FILTER_TYPE_DISASSOC    =   0x80,
66566 +     IEEE80211_FILTER_TYPE_ALL         =   0xFF  /* used to check the valid filter bits */
66567 +};
66568 +
66569 +struct ieee80211req_set_filter {
66570 +      u_int32_t app_filterype; /* management frame filter type */
66571 +};
66572 +
66573 +enum {
66574 +    IEEE80211_PARAM_AUTHMODE = 3,   /* Authentication Mode */
66575 +    IEEE80211_PARAM_MCASTCIPHER = 5,
66576 +    IEEE80211_PARAM_MCASTKEYLEN = 6,    /* multicast key length */
66577 +    IEEE80211_PARAM_UCASTCIPHER = 8,
66578 +    IEEE80211_PARAM_UCASTKEYLEN = 9,    /* unicast key length */
66579 +       IEEE80211_PARAM_WPA             = 10,   /* WPA mode (0,1,2) */
66580 +       IEEE80211_PARAM_ROAMING         = 12,   /* roaming mode */
66581 +       IEEE80211_PARAM_PRIVACY         = 13,   /* privacy invoked */
66582 +       IEEE80211_PARAM_COUNTERMEASURES = 14,   /* WPA/TKIP countermeasures */
66583 +       IEEE80211_PARAM_DROPUNENCRYPTED = 15,   /* discard unencrypted frames */
66584 +};
66585 +
66586 +/*
66587 + * Values for IEEE80211_PARAM_WPA
66588 + */
66589 +#define WPA_MODE_WPA1   1
66590 +#define WPA_MODE_WPA2   2
66591 +#define WPA_MODE_AUTO   3
66592 +#define WPA_MODE_NONE   4
66593 +
66594 +#ifdef __cplusplus
66595 +}
66596 +#endif
66597 +
66598 +#endif /* _IEEE80211_IOCTL_H_ */
66599 Index: linux-2.6.28/drivers/ar6000/include/ieee80211_node.h
66600 ===================================================================
66601 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66602 +++ linux-2.6.28/drivers/ar6000/include/ieee80211_node.h        2009-01-02 00:01:56.000000000 +0100
66603 @@ -0,0 +1,77 @@
66604 +/*-
66605 + * Copyright (c) 2001 Atsushi Onoe
66606 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
66607 + * Copyright (c) 2006 Atheros Communications, Inc.
66608 + *
66609 + * Wireless Network driver for Atheros AR6001
66610 + * All rights reserved.
66611 + *
66612 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
66613 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
66614 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
66615 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
66616 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
66617 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
66618 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
66619 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
66620 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66621 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66622 + *
66623 + */
66624 +#ifndef _IEEE80211_NODE_H_
66625 +#define _IEEE80211_NODE_H_
66626 +
66627 +/*
66628 + * Node locking definitions.
66629 + */
66630 +#define IEEE80211_NODE_LOCK_INIT(_nt)   A_MUTEX_INIT(&(_nt)->nt_nodelock)
66631 +#define IEEE80211_NODE_LOCK_DESTROY(_nt)
66632 +#define IEEE80211_NODE_LOCK(_nt)        A_MUTEX_LOCK(&(_nt)->nt_nodelock)
66633 +#define IEEE80211_NODE_UNLOCK(_nt)      A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
66634 +#define IEEE80211_NODE_LOCK_BH(_nt)     A_MUTEX_LOCK(&(_nt)->nt_nodelock)
66635 +#define IEEE80211_NODE_UNLOCK_BH(_nt)   A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
66636 +#define IEEE80211_NODE_LOCK_ASSERT(_nt)
66637 +
66638 +/*
66639 + * Node reference counting definitions.
66640 + *
66641 + * ieee80211_node_initref   initialize the reference count to 1
66642 + * ieee80211_node_incref    add a reference
66643 + * ieee80211_node_decref    remove a reference
66644 + * ieee80211_node_dectestref    remove a reference and return 1 if this
66645 + *              is the last reference, otherwise 0
66646 + * ieee80211_node_refcnt    reference count for printing (only)
66647 + */
66648 +#define ieee80211_node_initref(_ni)     ((_ni)->ni_refcnt = 1)
66649 +#define ieee80211_node_incref(_ni)      ((_ni)->ni_refcnt++)
66650 +#define ieee80211_node_decref(_ni)      ((_ni)->ni_refcnt--)
66651 +#define ieee80211_node_dectestref(_ni)  (((_ni)->ni_refcnt--) == 0)
66652 +#define ieee80211_node_refcnt(_ni)      ((_ni)->ni_refcnt)
66653 +
66654 +#define IEEE80211_NODE_HASHSIZE 32
66655 +/* simple hash is enough for variation of macaddr */
66656 +#define IEEE80211_NODE_HASH(addr)   \
66657 +    (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
66658 +        IEEE80211_NODE_HASHSIZE)
66659 +
66660 +/*
66661 + * Table of ieee80211_node instances.  Each ieee80211com
66662 + * has at least one for holding the scan candidates.
66663 + * When operating as an access point or in ibss mode there
66664 + * is a second table for associated stations or neighbors.
66665 + */
66666 +struct ieee80211_node_table {
66667 +    void                   *nt_wmip;       /* back reference */
66668 +    A_MUTEX_T               nt_nodelock;    /* on node table */
66669 +    struct bss              *nt_node_first; /* information of all nodes */
66670 +    struct bss              *nt_node_last;  /* information of all nodes */
66671 +    struct bss              *nt_hash[IEEE80211_NODE_HASHSIZE];
66672 +    const char              *nt_name;   /* for debugging */
66673 +    A_UINT32                nt_scangen; /* gen# for timeout scan */
66674 +    A_TIMER                 nt_inact_timer;
66675 +    A_UINT8                 isTimerArmed;   /* is the node timer armed */
66676 +};
66677 +
66678 +#define WLAN_NODE_INACT_TIMEOUT_MSEC            10000
66679 +
66680 +#endif /* _IEEE80211_NODE_H_ */
66681 Index: linux-2.6.28/drivers/ar6000/include/ini_dset.h
66682 ===================================================================
66683 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66684 +++ linux-2.6.28/drivers/ar6000/include/ini_dset.h      2009-01-02 00:01:56.000000000 +0100
66685 @@ -0,0 +1,40 @@
66686 +/*
66687 + * Copyright (c) 2004-2007 Atheros Communications Inc.
66688 + * All rights reserved.
66689 + *
66690 + * $ATH_LICENSE_HOSTSDK0_C$
66691 + *
66692 + */
66693 +#ifndef _INI_DSET_H_
66694 +#define _INI_DSET_H_
66695 +
66696 +/*
66697 + * Each of these represents a WHAL INI table, which consists
66698 + * of an "address column" followed by 1 or more "value columns".
66699 + *
66700 + * Software uses the base WHAL_INI_DATA_ID+column to access a
66701 + * DataSet that holds a particular column of data.
66702 + */
66703 +typedef enum {
66704 +    WHAL_INI_DATA_ID_NULL               =0,
66705 +    WHAL_INI_DATA_ID_MODE_SPECIFIC      =1,  /* 2,3 */
66706 +    WHAL_INI_DATA_ID_COMMON             =4,  /* 5 */
66707 +    WHAL_INI_DATA_ID_BB_RFGAIN          =6,  /* 7,8 */
66708 +    WHAL_INI_DATA_ID_ANALOG_BANK1       =9,  /* 10 */
66709 +    WHAL_INI_DATA_ID_ANALOG_BANK2       =11, /* 12 */
66710 +    WHAL_INI_DATA_ID_ANALOG_BANK3       =13, /* 14, 15 */
66711 +    WHAL_INI_DATA_ID_ANALOG_BANK6       =16, /* 17, 18 */
66712 +    WHAL_INI_DATA_ID_ANALOG_BANK7       =19, /* 20 */
66713 +    WHAL_INI_DATA_ID_MODE_OVERRIDES     =21, /* 22,23 */
66714 +    WHAL_INI_DATA_ID_COMMON_OVERRIDES   =24, /* 25 */
66715 +
66716 +    WHAL_INI_DATA_ID_MAX                =25
66717 +} WHAL_INI_DATA_ID;
66718 +
66719 +typedef PREPACK struct {
66720 +    A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
66721 +    A_UINT16 offset;
66722 +    A_UINT32 newValue;
66723 +} POSTPACK INI_DSET_REG_OVERRIDE;
66724 +
66725 +#endif
66726 Index: linux-2.6.28/drivers/ar6000/include/regDb.h
66727 ===================================================================
66728 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66729 +++ linux-2.6.28/drivers/ar6000/include/regDb.h 2009-01-02 00:01:56.000000000 +0100
66730 @@ -0,0 +1,19 @@
66731 +/*
66732 + * Copyright (c) 2005 Atheros Communications, Inc.
66733 + * All rights reserved.
66734 + *
66735 + *
66736 + * $ATH_LICENSE_HOSTSDK0_C$
66737 + *
66738 + * This module contains the header files for regulatory module,
66739 + * which include the DB schema and DB values.
66740 + * $Id:
66741 + */
66742 +
66743 +#ifndef __REG_DB_H__
66744 +#define __REG_DB_H__
66745 +
66746 +#include "./regulatory/reg_dbschema.h"
66747 +#include "./regulatory/reg_dbvalues.h"
66748 +
66749 +#endif  /* __REG_DB_H__ */
66750 Index: linux-2.6.28/drivers/ar6000/include/regdump.h
66751 ===================================================================
66752 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66753 +++ linux-2.6.28/drivers/ar6000/include/regdump.h       2009-01-02 00:01:56.000000000 +0100
66754 @@ -0,0 +1,33 @@
66755 +#ifndef __REGDUMP_H__
66756 +#define __REGDUMP_H__
66757 +/*
66758 + * Copyright (c) 2004-2007 Atheros Communications Inc.
66759 + * All rights reserved.
66760 + *
66761 + * $ATH_LICENSE_HOSTSDK0_C$
66762 + *
66763 + */
66764 +#if defined(AR6001)
66765 +#include "AR6001/AR6001_regdump.h"
66766 +#endif
66767 +#if defined(AR6002)
66768 +#include "AR6002/AR6002_regdump.h"
66769 +#endif
66770 +
66771 +#if !defined(__ASSEMBLER__)
66772 +/*
66773 + * Target CPU state at the time of failure is reflected
66774 + * in a register dump, which the Host can fetch through
66775 + * the diagnostic window.
66776 + */
66777 +struct register_dump_s {
66778 +    A_UINT32 target_id;               /* Target ID */
66779 +    A_UINT32 assline;                 /* Line number (if assertion failure) */
66780 +    A_UINT32 pc;                      /* Program Counter at time of exception */
66781 +    A_UINT32 badvaddr;                /* Virtual address causing exception */
66782 +    CPU_exception_frame_t exc_frame;  /* CPU-specific exception info */
66783 +
66784 +    /* Could copy top of stack here, too.... */
66785 +};
66786 +#endif /* __ASSEMBLER__ */
66787 +#endif /* __REGDUMP_H__ */
66788 Index: linux-2.6.28/drivers/ar6000/include/targaddrs.h
66789 ===================================================================
66790 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66791 +++ linux-2.6.28/drivers/ar6000/include/targaddrs.h     2009-01-02 00:01:56.000000000 +0100
66792 @@ -0,0 +1,158 @@
66793 +/*
66794 + * Copyright (c) 2004-2007 Atheros Communications Inc.
66795 + * All rights reserved.
66796 + *
66797 + * $ATH_LICENSE_HOSTSDK0_C$
66798 + *
66799 + */
66800 +
66801 +#ifndef __TARGADDRS_H__
66802 +#define __TARGADDRS_H__
66803 +#if defined(AR6001)
66804 +#include "AR6001/addrs.h"
66805 +#endif
66806 +#if defined(AR6002)
66807 +#include "AR6002/addrs.h"
66808 +#endif
66809 +
66810 +/*
66811 + * AR6K option bits, to enable/disable various features.
66812 + * By default, all option bits are 0.
66813 + * These bits can be set in LOCAL_SCRATCH register 0.
66814 + */
66815 +#define AR6K_OPTION_BMI_DISABLE      0x01 /* Disable BMI comm with Host */
66816 +#define AR6K_OPTION_SERIAL_ENABLE    0x02 /* Enable serial port msgs */
66817 +#define AR6K_OPTION_WDT_DISABLE      0x04 /* WatchDog Timer override */
66818 +#define AR6K_OPTION_SLEEP_DISABLE    0x08 /* Disable system sleep */
66819 +#define AR6K_OPTION_STOP_BOOT        0x10 /* Stop boot processes (for ATE) */
66820 +#define AR6K_OPTION_ENABLE_NOANI     0x20 /* Operate without ANI */
66821 +#define AR6K_OPTION_DSET_DISABLE     0x40 /* Ignore DataSets */
66822 +#define AR6K_OPTION_IGNORE_FLASH     0x80 /* Ignore flash during bootup */
66823 +
66824 +/*
66825 + * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
66826 + * host_interest structure.  It must match the address of the _host_interest
66827 + * symbol (see linker script).
66828 + *
66829 + * Host Interest is shared between Host and Target in order to coordinate
66830 + * between the two, and is intended to remain constant (with additions only
66831 + * at the end) across software releases.
66832 + */
66833 +#define AR6001_HOST_INTEREST_ADDRESS     0x80000600
66834 +#define AR6002_HOST_INTEREST_ADDRESS     0x00500400
66835 +
66836 +#define HOST_INTEREST_MAX_SIZE          0x100
66837 +
66838 +#if !defined(__ASSEMBLER__)
66839 +struct register_dump_s;
66840 +struct dbglog_hdr_s;
66841 +
66842 +/*
66843 + * These are items that the Host may need to access
66844 + * via BMI or via the Diagnostic Window. The position
66845 + * of items in this structure must remain constant
66846 + * across firmware revisions!
66847 + *
66848 + * Types for each item must be fixed size across
66849 + * target and host platforms.
66850 + *
66851 + * More items may be added at the end.
66852 + */
66853 +struct host_interest_s {
66854 +    /*
66855 +     * Pointer to application-defined area, if any.
66856 +     * Set by Target application during startup.
66857 +     */
66858 +    A_UINT32               hi_app_host_interest;                      /* 0x00 */
66859 +
66860 +    /* Pointer to register dump area, valid after Target crash. */
66861 +    A_UINT32               hi_failure_state;                          /* 0x04 */
66862 +
66863 +    /* Pointer to debug logging header */
66864 +    A_UINT32               hi_dbglog_hdr;                             /* 0x08 */
66865 +
66866 +    /* Indicates whether or not flash is present on Target.
66867 +     * NB: flash_is_present indicator is here not just
66868 +     * because it might be of interest to the Host; but
66869 +     * also because it's set early on by Target's startup
66870 +     * asm code and we need it to have a special RAM address
66871 +     * so that it doesn't get reinitialized with the rest
66872 +     * of data.
66873 +     */
66874 +    A_UINT32               hi_flash_is_present;                       /* 0x0c */
66875 +
66876 +    /*
66877 +     * General-purpose flag bits, similar to AR6000_OPTION_* flags.
66878 +     * Can be used by application rather than by OS.
66879 +     */
66880 +    A_UINT32               hi_option_flag;                            /* 0x10 */
66881 +
66882 +    /*
66883 +     * Boolean that determines whether or not to
66884 +     * display messages on the serial port.
66885 +     */
66886 +    A_UINT32               hi_serial_enable;                          /* 0x14 */
66887 +
66888 +    /* Start address of Flash DataSet index, if any */
66889 +    A_UINT32               hi_dset_list_head;                         /* 0x18 */
66890 +
66891 +    /* Override Target application start address */
66892 +    A_UINT32               hi_app_start;                              /* 0x1c */
66893 +
66894 +    /* Clock and voltage tuning */
66895 +    A_UINT32               hi_skip_clock_init;                        /* 0x20 */
66896 +    A_UINT32               hi_core_clock_setting;                     /* 0x24 */
66897 +    A_UINT32               hi_cpu_clock_setting;                      /* 0x28 */
66898 +    A_UINT32               hi_system_sleep_setting;                   /* 0x2c */
66899 +    A_UINT32               hi_xtal_control_setting;                   /* 0x30 */
66900 +    A_UINT32               hi_pll_ctrl_setting_24ghz;                 /* 0x34 */
66901 +    A_UINT32               hi_pll_ctrl_setting_5ghz;                  /* 0x38 */
66902 +    A_UINT32               hi_ref_voltage_trim_setting;               /* 0x3c */
66903 +    A_UINT32               hi_clock_info;                             /* 0x40 */
66904 +
66905 +    /*
66906 +     * Flash configuration overrides, used only
66907 +     * when firmware is not executing from flash.
66908 +     * (When using flash, modify the global variables
66909 +     * with equivalent names.)
66910 +     */
66911 +    A_UINT32               hi_bank0_addr_value;                       /* 0x44 */
66912 +    A_UINT32               hi_bank0_read_value;                       /* 0x48 */
66913 +    A_UINT32               hi_bank0_write_value;                      /* 0x4c */
66914 +    A_UINT32               hi_bank0_config_value;                     /* 0x50 */
66915 +
66916 +    /* Pointer to Board Data  */
66917 +    A_UINT32               hi_board_data;                             /* 0x54 */
66918 +    A_UINT32               hi_board_data_initialized;                 /* 0x58 */
66919 +
66920 +    A_UINT32               hi_dset_RAM_index_table;                   /* 0x5c */
66921 +
66922 +    A_UINT32               hi_desired_baud_rate;                      /* 0x60 */
66923 +    A_UINT32               hi_dbglog_config;                          /* 0x64 */
66924 +    A_UINT32               hi_end_RAM_reserve_sz;                     /* 0x68 */
66925 +    A_UINT32               hi_mbox_io_block_sz;                       /* 0x6c */
66926 +
66927 +    A_UINT32               hi_num_bpatch_streams;                     /* 0x70 */
66928 +    A_UINT32               hi_mbox_isr_yield_limit;                   /* 0x74 */
66929 +
66930 +    A_UINT32               hi_refclk_hz;                              /* 0x78 */
66931 +};
66932 +
66933 +/* Bits defined in hi_option_flag */
66934 +#define HI_OPTION_TIMER_WAR     1 /* not really used */
66935 +
66936 +/*
66937 + * Intended for use by Host software, this macro returns the Target RAM
66938 + * address of any item in the host_interest structure.
66939 + * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
66940 + */
66941 +#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \
66942 +    ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item)))
66943 +
66944 +#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
66945 +    ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
66946 +
66947 +
66948 +#endif /* !__ASSEMBLER__ */
66949 +
66950 +#endif /* __TARGADDRS_H__ */
66951 Index: linux-2.6.28/drivers/ar6000/include/testcmd.h
66952 ===================================================================
66953 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
66954 +++ linux-2.6.28/drivers/ar6000/include/testcmd.h       2009-01-02 00:01:56.000000000 +0100
66955 @@ -0,0 +1,144 @@
66956 +/*
66957 + * Copyright (c) 2004-2005 Atheros Communications Inc.
66958 + * All rights reserved.
66959 + *
66960 + *
66961 + * $ATH_LICENSE_HOSTSDK0_C$
66962 + *
66963 + */
66964 +
66965 +#ifndef  TESTCMD_H_
66966 +#define  TESTCMD_H_
66967 +
66968 +#ifdef __cplusplus
66969 +extern "C" {
66970 +#endif
66971 +
66972 +typedef enum {
66973 +    ZEROES_PATTERN = 0,
66974 +    ONES_PATTERN,
66975 +    REPEATING_10,
66976 +    PN7_PATTERN,
66977 +    PN9_PATTERN,
66978 +    PN15_PATTERN
66979 +}TX_DATA_PATTERN;
66980 +
66981 +/* Continous tx
66982 +   mode : TCMD_CONT_TX_OFF - Disabling continous tx
66983 +          TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
66984 +          TCMD_CONT_TX_FRAME- Enable continuous modulated tx
66985 +   freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
66986 +dataRate: 0 - 1 Mbps
66987 +          1 - 2 Mbps
66988 +          2 - 5.5 Mbps
66989 +          3 - 11 Mbps
66990 +          4 - 6 Mbps
66991 +          5 - 9 Mbps
66992 +          6 - 12 Mbps
66993 +          7 - 18 Mbps
66994 +          8 - 24 Mbps
66995 +          9 - 36 Mbps
66996 +         10 - 28 Mbps
66997 +         11 - 54 Mbps
66998 +  txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
66999 +antenna:  1 - one antenna
67000 +          2 - two antenna
67001 +Note : Enable/disable continuous tx test cmd works only when target is awake.
67002 +*/
67003 +
67004 +typedef enum {
67005 +    TCMD_CONT_TX_OFF = 0,
67006 +    TCMD_CONT_TX_SINE,
67007 +    TCMD_CONT_TX_FRAME,
67008 +    TCMD_CONT_TX_TX99,
67009 +    TCMD_CONT_TX_TX100
67010 +} TCMD_CONT_TX_MODE;
67011 +
67012 +typedef PREPACK struct {
67013 +    A_UINT32                 testCmdId;
67014 +    A_UINT32                mode;
67015 +    A_UINT32                freq;
67016 +    A_UINT32                dataRate;
67017 +    A_INT32                 txPwr;
67018 +    A_UINT32                antenna;
67019 +    A_UINT32                enANI;
67020 +    A_UINT32                scramblerOff;
67021 +    A_UINT32                aifsn;
67022 +    A_UINT16                pktSz;
67023 +    A_UINT16                txPattern;
67024 +} POSTPACK TCMD_CONT_TX;
67025 +
67026 +#define TCMD_TXPATTERN_ZERONE                 0x1
67027 +#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE    0x2
67028 +
67029 +/* Continuous Rx
67030 + act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
67031 +      TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
67032 +                                             address equal specified
67033 +                                             mac address (set via act =3)
67034 +      TCMD_CONT_RX_REPORT  off mode  (disable cont rx mode and get the
67035 +                                          report from the last cont
67036 +                                          Rx test)
67037 +
67038 +     TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
67039 +                                                 target. This Overrides
67040 +                                                 the default MAC address.)
67041 +
67042 +*/
67043 +typedef enum {
67044 +    TCMD_CONT_RX_PROMIS =0,
67045 +    TCMD_CONT_RX_FILTER,
67046 +    TCMD_CONT_RX_REPORT,
67047 +    TCMD_CONT_RX_SETMAC
67048 +} TCMD_CONT_RX_ACT;
67049 +
67050 +typedef PREPACK struct {
67051 +    A_UINT32         testCmdId;
67052 +    A_UINT32        act;
67053 +    A_UINT32        enANI;
67054 +    PREPACK union {
67055 +        struct PREPACK TCMD_CONT_RX_PARA {
67056 +            A_UINT32    freq;
67057 +            A_UINT32    antenna;
67058 +        } POSTPACK para;
67059 +        struct PREPACK TCMD_CONT_RX_REPORT {
67060 +            A_UINT32    totalPkt;
67061 +            A_INT32    rssiInDBm;
67062 +        } POSTPACK report;
67063 +        struct PREPACK TCMD_CONT_RX_MAC {
67064 +            A_UCHAR    addr[ATH_MAC_LEN];
67065 +        } POSTPACK mac;
67066 +    } POSTPACK u;
67067 +} POSTPACK TCMD_CONT_RX;
67068 +
67069 +/* Force sleep/wake  test cmd
67070 + mode: TCMD_PM_WAKEUP - Wakeup the target
67071 +       TCMD_PM_SLEEP - Force the target to sleep.
67072 + */
67073 +typedef enum {
67074 +    TCMD_PM_WAKEUP = 1, /* be consistent with target */
67075 +    TCMD_PM_SLEEP
67076 +} TCMD_PM_MODE;
67077 +
67078 +typedef PREPACK struct {
67079 +       A_UINT32  testCmdId;
67080 +    A_UINT32  mode;
67081 +} POSTPACK TCMD_PM;
67082 +
67083 +typedef enum{
67084 +    TCMD_CONT_TX_ID,
67085 +    TCMD_CONT_RX_ID,
67086 +    TCMD_PM_ID
67087 +   } TCMD_ID;
67088 +
67089 +typedef PREPACK union {
67090 +          TCMD_CONT_TX contTx;
67091 +          TCMD_CONT_RX contRx;
67092 +          TCMD_PM pm ;
67093 +} POSTPACK TEST_CMD;
67094 +
67095 +#ifdef __cplusplus
67096 +}
67097 +#endif
67098 +
67099 +#endif /* TESTCMD_H_ */
67100 Index: linux-2.6.28/drivers/ar6000/include/wlan_api.h
67101 ===================================================================
67102 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
67103 +++ linux-2.6.28/drivers/ar6000/include/wlan_api.h      2009-01-02 00:01:56.000000000 +0100
67104 @@ -0,0 +1,101 @@
67105 +#ifndef _HOST_WLAN_API_H_
67106 +#define _HOST_WLAN_API_H_
67107 +/*
67108 + * Copyright (c) 2004-2005 Atheros Communications Inc.
67109 + * All rights reserved.
67110 + *
67111 + * This file contains the API for the host wlan module
67112 + *
67113 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/wlan_api.h#1 $
67114 + *
67115 + *
67116 + *  This program is free software; you can redistribute it and/or modify
67117 + *  it under the terms of the GNU General Public License version 2 as
67118 + *  published by the Free Software Foundation;
67119 + *
67120 + *  Software distributed under the License is distributed on an "AS
67121 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
67122 + *  implied. See the License for the specific language governing
67123 + *  rights and limitations under the License.
67124 + *
67125 + *
67126 + *
67127 + */
67128 +
67129 +#ifdef __cplusplus
67130 +extern "C" {
67131 +#endif
67132 +
67133 +struct ieee80211_node_table;
67134 +struct ieee80211_frame;
67135 +
67136 +struct ieee80211_common_ie {
67137 +    A_UINT16    ie_chan;
67138 +    A_UINT8     *ie_tstamp;
67139 +    A_UINT8     *ie_ssid;
67140 +    A_UINT8     *ie_rates;
67141 +    A_UINT8     *ie_xrates;
67142 +    A_UINT8     *ie_country;
67143 +    A_UINT8     *ie_wpa;
67144 +    A_UINT8     *ie_rsn;
67145 +    A_UINT8     *ie_wmm;
67146 +    A_UINT8     *ie_ath;
67147 +    A_UINT16    ie_capInfo;
67148 +    A_UINT16    ie_beaconInt;
67149 +    A_UINT8     *ie_tim;
67150 +    A_UINT8     *ie_chswitch;
67151 +    A_UINT8     ie_erp;
67152 +    A_UINT8     *ie_wsc;
67153 +};
67154 +
67155 +typedef struct bss {
67156 +    A_UINT8                      ni_macaddr[6];
67157 +    A_UINT8                      ni_snr;
67158 +    A_INT16                      ni_rssi;
67159 +    struct bss                   *ni_list_next;
67160 +    struct bss                   *ni_list_prev;
67161 +    struct bss                   *ni_hash_next;
67162 +    struct bss                   *ni_hash_prev;
67163 +    struct ieee80211_common_ie   ni_cie;
67164 +    A_UINT8                     *ni_buf;
67165 +    struct ieee80211_node_table *ni_table;
67166 +    A_UINT32                     ni_refcnt;
67167 +    int                          ni_scangen;
67168 +    A_UINT32                     ni_tstamp;
67169 +} bss_t;
67170 +
67171 +typedef void wlan_node_iter_func(void *arg, bss_t *);
67172 +
67173 +bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
67174 +void wlan_node_free(bss_t *ni);
67175 +void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
67176 +                const A_UINT8 *macaddr);
67177 +bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr);
67178 +void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
67179 +void wlan_free_allnodes(struct ieee80211_node_table *nt);
67180 +void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
67181 +                        void *arg);
67182 +
67183 +void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
67184 +void wlan_node_table_reset(struct ieee80211_node_table *nt);
67185 +void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
67186 +
67187 +A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen,
67188 +                           struct ieee80211_common_ie *cie);
67189 +
67190 +A_UINT16 wlan_ieee2freq(int chan);
67191 +A_UINT32 wlan_freq2ieee(A_UINT16 freq);
67192 +
67193 +
67194 +bss_t *
67195 +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
67196 +                                       A_UINT32 ssidLength, A_BOOL bIsWPA2);
67197 +
67198 +void
67199 +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
67200 +
67201 +#ifdef __cplusplus
67202 +}
67203 +#endif
67204 +
67205 +#endif /* _HOST_WLAN_API_H_ */
67206 Index: linux-2.6.28/drivers/ar6000/include/wlan_dset.h
67207 ===================================================================
67208 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
67209 +++ linux-2.6.28/drivers/ar6000/include/wlan_dset.h     2009-01-02 00:01:56.000000000 +0100
67210 @@ -0,0 +1,20 @@
67211 +/*
67212 + * Copyright (c) 2007 Atheros Communications, Inc.
67213 + * All rights reserved.
67214 + *
67215 + *
67216 + * $ATH_LICENSE_HOSTSDK0_C$
67217 + *
67218 + */
67219 +
67220 +#ifndef __WLAN_DSET_H__
67221 +#define __WKAN_DSET_H__
67222 +
67223 +typedef PREPACK struct wow_config_dset {
67224 +
67225 +    A_UINT8 valid_dset;
67226 +    A_UINT8 gpio_enable;
67227 +    A_UINT16 gpio_pin;
67228 +} POSTPACK WOW_CONFIG_DSET;
67229 +
67230 +#endif
67231 Index: linux-2.6.28/drivers/ar6000/include/wmi_api.h
67232 ===================================================================
67233 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
67234 +++ linux-2.6.28/drivers/ar6000/include/wmi_api.h       2009-01-02 00:01:56.000000000 +0100
67235 @@ -0,0 +1,260 @@
67236 +#ifndef _WMI_API_H_
67237 +#define _WMI_API_H_
67238 +/*
67239 + * Copyright (c) 2004-2006 Atheros Communications Inc.
67240 + * All rights reserved.
67241 + *
67242 + * This file contains the definitions for the Wireless Module Interface (WMI).
67243 + *
67244 + * $Id: //depot/sw/releases/olca2.0-GPL/host/include/wmi_api.h#2 $
67245 + *
67246 + *
67247 + *  This program is free software; you can redistribute it and/or modify
67248 + *  it under the terms of the GNU General Public License version 2 as
67249 + *  published by the Free Software Foundation;
67250 + *
67251 + *  Software distributed under the License is distributed on an "AS
67252 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
67253 + *  implied. See the License for the specific language governing
67254 + *  rights and limitations under the License.
67255 + *
67256 + *
67257 + *
67258 + */
67259 +
67260 +#ifdef __cplusplus
67261 +extern "C" {
67262 +#endif
67263 +
67264 +/*
67265 + * IP QoS Field definitions according to 802.1p
67266 + */
67267 +#define BEST_EFFORT_PRI         0
67268 +#define BACKGROUND_PRI          1
67269 +#define EXCELLENT_EFFORT_PRI    3
67270 +#define CONTROLLED_LOAD_PRI     4
67271 +#define VIDEO_PRI               5
67272 +#define VOICE_PRI               6
67273 +#define NETWORK_CONTROL_PRI     7
67274 +#define MAX_NUM_PRI             8
67275 +
67276 +#define UNDEFINED_PRI           (0xff)
67277 +
67278 +/* simple mapping of IP TOS field to a WMI priority stream
67279 + * this mapping was taken from the original linux driver implementation
67280 + * The operation maps the following
67281 + *
67282 + *  */
67283 +#define IP_TOS_TO_WMI_PRI(tos)  \
67284 +    ((WMI_PRI_STREAM_ID)(((tos) >> 1) & 0x03))
67285 +
67286 +#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
67287 +
67288 +
67289 +struct wmi_t;
67290 +
67291 +void *wmi_init(void *devt);
67292 +
67293 +void wmi_qos_state_init(struct wmi_t *wmip);
67294 +void wmi_shutdown(struct wmi_t *wmip);
67295 +A_UINT16  wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8);
67296 +A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
67297 +A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType);
67298 +A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf);
67299 +A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
67300 +A_STATUS wmi_syncpoint(struct wmi_t *wmip);
67301 +A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip);
67302 +WMI_PRI_STREAM_ID wmi_get_stream_id(struct wmi_t *wmip, A_UINT8 trafficClass);
67303 +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir, A_UINT8 up);
67304 +
67305 +A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf);
67306 +void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
67307 +void wmi_free_allnodes(struct wmi_t *wmip);
67308 +bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
67309 +
67310 +
67311 +typedef enum {
67312 +    NO_SYNC_WMIFLAG = 0,
67313 +    SYNC_BEFORE_WMIFLAG,            /* transmit all queued data before cmd */
67314 +    SYNC_AFTER_WMIFLAG,             /* any new data waits until cmd execs */
67315 +    SYNC_BOTH_WMIFLAG,
67316 +    END_WMIFLAG                     /* end marker */
67317 +} WMI_SYNC_FLAG;
67318 +
67319 +A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
67320 +                      WMI_SYNC_FLAG flag);
67321 +A_STATUS wmi_connect_cmd(struct wmi_t *wmip,
67322 +                         NETWORK_TYPE netType,
67323 +                         DOT11_AUTH_MODE dot11AuthMode,
67324 +                         AUTH_MODE authMode,
67325 +                         CRYPTO_TYPE pairwiseCrypto,
67326 +                         A_UINT8 pairwiseCryptoLen,
67327 +                         CRYPTO_TYPE groupCrypto,
67328 +                         A_UINT8 groupCryptoLen,
67329 +                         int ssidLength,
67330 +                         A_UCHAR *ssid,
67331 +                         A_UINT8 *bssid,
67332 +                         A_UINT16 channel,
67333 +                         A_UINT32 ctrl_flags);
67334 +A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip,
67335 +                           A_UINT8 *bssid,
67336 +                           A_UINT16 channel);
67337 +A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip);
67338 +A_STATUS wmi_getrev_cmd(struct wmi_t *wmip);
67339 +A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
67340 +                           A_BOOL forceFgScan, A_BOOL isLegacy,
67341 +                           A_UINT32 homeDwellTime, A_UINT32 forceScanInterval);
67342 +A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
67343 +                            A_UINT16 fg_end_sec, A_UINT16 bg_sec,
67344 +                            A_UINT16 minact_chdw_msec,
67345 +                            A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec,
67346 +                            A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
67347 +                            A_UINT32 max_dfsch_act_time);
67348 +A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask);
67349 +A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
67350 +                            A_UINT8 ssidLength, A_UCHAR *ssid);
67351 +A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons);
67352 +A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons);
67353 +A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
67354 +                           A_UINT8 ieLen, A_UINT8 *ieInfo);
67355 +A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode);
67356 +A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
67357 +                            A_UINT16 atim_windows, A_UINT16 timeout_value);
67358 +A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
67359 +                           A_UINT16 psPollNum, A_UINT16 dtimPolicy);
67360 +A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout);
67361 +A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber);
67362 +A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
67363 +A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID);
67364 +A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate);
67365 +A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip);
67366 +A_INT8   wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate);
67367 +A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip);
67368 +A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip);
67369 +A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
67370 +                                   WMI_PHY_MODE mode, A_INT8 numChan,
67371 +                                   A_UINT16 *channelList);
67372 +
67373 +A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip,
67374 +                                       WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
67375 +A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip,
67376 +                                        WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
67377 +A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip);
67378 +A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip,
67379 +                                      WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd);
67380 +A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold);
67381 +A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status);
67382 +
67383 +A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
67384 +
67385 +A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie,
67386 +                                    A_UINT32 source);
67387 +A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
67388 +                                     A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
67389 +                                     A_UINT32 valid);
67390 +A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip);
67391 +A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex,
67392 +                        CRYPTO_TYPE keyType, A_UINT8 keyUsage,
67393 +                        A_UINT8 keyLength,A_UINT8 *keyRSC,
67394 +                        A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl,
67395 +                        WMI_SYNC_FLAG sync_flag);
67396 +A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk);
67397 +A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip);
67398 +A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex);
67399 +A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip,
67400 +                                 WMI_SET_AKMP_PARAMS_CMD *akmpParams);
67401 +A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip);
67402 +A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
67403 +                                WMI_SET_PMKID_LIST_CMD *pmkInfo);
67404 +A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM);
67405 +A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip);
67406 +A_STATUS wmi_switch_radio(struct wmi_t *wmip, A_UINT8 on);
67407 +A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid);
67408 +A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex);
67409 +A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en);
67410 +A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
67411 +                          A_BOOL set);
67412 +A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop,
67413 +                                   A_UINT8 eCWmin, A_UINT8 eCWmax,
67414 +                                   A_UINT8 aifsn);
67415 +A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
67416 +                                  A_UINT8 trafficClass, A_UINT8 maxRetries,
67417 +                                  A_UINT8 enableNotify);
67418 +
67419 +void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid);
67420 +
67421 +A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
67422 +A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType);
67423 +A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
67424 +                               A_UINT8 size);
67425 +A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
67426 +                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
67427 +                            A_UINT8 size);
67428 +
67429 +A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode);
67430 +A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
67431 +                              A_UINT8 frmType,
67432 +                              A_UINT8 *dstMacAddr,
67433 +                              A_UINT8 *bssid,
67434 +                              A_UINT16 optIEDataLen,
67435 +                              A_UINT8 *optIEData);
67436 +
67437 +A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl);
67438 +A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize);
67439 +A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen);
67440 +A_UINT8  convert_userPriority_to_trafficClass(A_UINT8 userPriority);
67441 +A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
67442 +A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance);
67443 +
67444 +#ifdef CONFIG_HOST_TCMD_SUPPORT
67445 +A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len);
67446 +#endif
67447 +
67448 +A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status);
67449 +A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd);
67450 +
67451 +
67452 +/*
67453 + *  This function is used to configure the fix rates mask to the target.
67454 + */
67455 +A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask);
67456 +A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip);
67457 +
67458 +A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
67459 +
67460 +A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
67461 +
67462 +A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status);
67463 +A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable);
67464 +
67465 +A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip);
67466 +A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip);
67467 +A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval);
67468 +
67469 +A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType,
67470 +                           A_UINT8 ieLen,A_UINT8 *ieInfo);
67471 +
67472 +A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen);
67473 +A_INT32 wmi_get_rate(A_INT8 rateindex);
67474 +
67475 +/*Wake on Wireless WMI commands*/
67476 +A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd);
67477 +A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd);
67478 +A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd);
67479 +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
67480 +                                 WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size);
67481 +A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
67482 +                                 WMI_DEL_WOW_PATTERN_CMD *cmd);
67483 +A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status);
67484 +
67485 +bss_t *
67486 +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
67487 +                                  A_UINT32 ssidLength, A_BOOL bIsWPA2);
67488 +
67489 +void
67490 +wmi_node_return (struct wmi_t *wmip, bss_t *bss);
67491 +#ifdef __cplusplus
67492 +}
67493 +#endif
67494 +
67495 +#endif /* _WMI_API_H_ */
67496 Index: linux-2.6.28/drivers/ar6000/include/wmi.h
67497 ===================================================================
67498 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
67499 +++ linux-2.6.28/drivers/ar6000/include/wmi.h   2009-01-02 00:01:56.000000000 +0100
67500 @@ -0,0 +1,1743 @@
67501 +/*
67502 + * Copyright (c) 2004-2006 Atheros Communications Inc.
67503 + * All rights reserved.
67504 + *
67505 + *
67506 + * $ATH_LICENSE_HOSTSDK0_C$
67507 + *
67508 + * This file contains the definitions of the WMI protocol specified in the
67509 + * Wireless Module Interface (WMI).  It includes definitions of all the
67510 + * commands and events. Commands are messages from the host to the WM.
67511 + * Events and Replies are messages from the WM to the host.
67512 + *
67513 + * Ownership of correctness in regards to WMI commands
67514 + * belongs to the host driver and the WM is not required to validate
67515 + * parameters for value, proper range, or any other checking.
67516 + *
67517 + */
67518 +
67519 +#ifndef _WMI_H_
67520 +#define _WMI_H_
67521 +
67522 +#ifndef ATH_TARGET
67523 +#include "athstartpack.h"
67524 +#endif
67525 +
67526 +#include "wmix.h"
67527 +
67528 +#ifdef __cplusplus
67529 +extern "C" {
67530 +#endif
67531 +
67532 +#define WMI_PROTOCOL_VERSION    0x0002
67533 +#define WMI_PROTOCOL_REVISION   0x0000
67534 +
67535 +#define ATH_MAC_LEN             6               /* length of mac in bytes */
67536 +#define WMI_CMD_MAX_LEN         100
67537 +#define WMI_CONTROL_MSG_MAX_LEN     256
67538 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
67539 +#define IS_ETHERTYPE(_typeOrLen)        ((_typeOrLen) >= 0x0600)
67540 +#define RFC1042OUI      {0x00, 0x00, 0x00}
67541 +
67542 +#define IP_ETHERTYPE 0x0800
67543 +
67544 +#define WMI_IMPLICIT_PSTREAM 0xFF
67545 +#define WMI_MAX_THINSTREAM 15
67546 +
67547 +struct host_app_area_s {
67548 +    A_UINT32 wmi_protocol_ver;
67549 +};
67550 +
67551 +/*
67552 + * Data Path
67553 + */
67554 +typedef PREPACK struct {
67555 +    A_UINT8     dstMac[ATH_MAC_LEN];
67556 +    A_UINT8     srcMac[ATH_MAC_LEN];
67557 +    A_UINT16    typeOrLen;
67558 +} POSTPACK ATH_MAC_HDR;
67559 +
67560 +typedef PREPACK struct {
67561 +    A_UINT8     dsap;
67562 +    A_UINT8     ssap;
67563 +    A_UINT8     cntl;
67564 +    A_UINT8     orgCode[3];
67565 +    A_UINT16    etherType;
67566 +} POSTPACK ATH_LLC_SNAP_HDR;
67567 +
67568 +typedef enum {
67569 +    DATA_MSGTYPE = 0x0,
67570 +    CNTL_MSGTYPE,
67571 +    SYNC_MSGTYPE
67572 +} WMI_MSG_TYPE;
67573 +
67574 +
67575 +typedef PREPACK struct {
67576 +    A_INT8      rssi;
67577 +    A_UINT8     info;            /* WMI_MSG_TYPE in lower 2 bits - b1b0 */
67578 +                                 /* UP in next 3 bits - b4b3b2 */
67579 +#define WMI_DATA_HDR_MSG_TYPE_MASK  0x03
67580 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
67581 +#define WMI_DATA_HDR_UP_MASK        0x07
67582 +#define WMI_DATA_HDR_UP_SHIFT       2
67583 +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t)  (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
67584 +} POSTPACK WMI_DATA_HDR;
67585 +
67586 +
67587 +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT))
67588 +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT))
67589 +
67590 +/*
67591 + * Control Path
67592 + */
67593 +typedef PREPACK struct {
67594 +    A_UINT16    commandId;
67595 +} POSTPACK WMI_CMD_HDR;        /* used for commands and events */
67596 +
67597 +/*
67598 + * List of Commnands
67599 + */
67600 +typedef enum {
67601 +    WMI_CONNECT_CMDID           = 0x0001,
67602 +    WMI_RECONNECT_CMDID,
67603 +    WMI_DISCONNECT_CMDID,
67604 +    WMI_SYNCHRONIZE_CMDID,
67605 +    WMI_CREATE_PSTREAM_CMDID,
67606 +    WMI_DELETE_PSTREAM_CMDID,
67607 +    WMI_START_SCAN_CMDID,
67608 +    WMI_SET_SCAN_PARAMS_CMDID,
67609 +    WMI_SET_BSS_FILTER_CMDID,
67610 +    WMI_SET_PROBED_SSID_CMDID,
67611 +    WMI_SET_LISTEN_INT_CMDID,
67612 +    WMI_SET_BMISS_TIME_CMDID,
67613 +    WMI_SET_DISC_TIMEOUT_CMDID,
67614 +    WMI_GET_CHANNEL_LIST_CMDID,
67615 +    WMI_SET_BEACON_INT_CMDID,
67616 +    WMI_GET_STATISTICS_CMDID,
67617 +    WMI_SET_CHANNEL_PARAMS_CMDID,
67618 +    WMI_SET_POWER_MODE_CMDID,
67619 +    WMI_SET_IBSS_PM_CAPS_CMDID,
67620 +    WMI_SET_POWER_PARAMS_CMDID,
67621 +    WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
67622 +    WMI_ADD_CIPHER_KEY_CMDID,
67623 +    WMI_DELETE_CIPHER_KEY_CMDID,
67624 +    WMI_ADD_KRK_CMDID,
67625 +    WMI_DELETE_KRK_CMDID,
67626 +    WMI_SET_PMKID_CMDID,
67627 +    WMI_SET_TX_PWR_CMDID,
67628 +    WMI_GET_TX_PWR_CMDID,
67629 +    WMI_SET_ASSOC_INFO_CMDID,
67630 +    WMI_ADD_BAD_AP_CMDID,
67631 +    WMI_DELETE_BAD_AP_CMDID,
67632 +    WMI_SET_TKIP_COUNTERMEASURES_CMDID,
67633 +    WMI_RSSI_THRESHOLD_PARAMS_CMDID,
67634 +    WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
67635 +    WMI_SET_ACCESS_PARAMS_CMDID,
67636 +    WMI_SET_RETRY_LIMITS_CMDID,
67637 +    WMI_SET_OPT_MODE_CMDID,
67638 +    WMI_OPT_TX_FRAME_CMDID,
67639 +    WMI_SET_VOICE_PKT_SIZE_CMDID,
67640 +    WMI_SET_MAX_SP_LEN_CMDID,
67641 +    WMI_SET_ROAM_CTRL_CMDID,
67642 +    WMI_GET_ROAM_TBL_CMDID,
67643 +    WMI_GET_ROAM_DATA_CMDID,
67644 +    WMI_ENABLE_RM_CMDID,
67645 +    WMI_SET_MAX_OFFHOME_DURATION_CMDID,
67646 +    WMI_EXTENSION_CMDID,                        /* Non-wireless extensions */
67647 +    WMI_SNR_THRESHOLD_PARAMS_CMDID,
67648 +    WMI_LQ_THRESHOLD_PARAMS_CMDID,
67649 +    WMI_SET_LPREAMBLE_CMDID,
67650 +    WMI_SET_RTS_CMDID,
67651 +    WMI_CLR_RSSI_SNR_CMDID,
67652 +    WMI_SET_FIXRATES_CMDID,
67653 +    WMI_GET_FIXRATES_CMDID,
67654 +    WMI_SET_AUTH_MODE_CMDID,
67655 +    WMI_SET_REASSOC_MODE_CMDID,
67656 +    WMI_SET_WMM_CMDID,
67657 +    WMI_SET_WMM_TXOP_CMDID,
67658 +    WMI_TEST_CMDID,
67659 +    WMI_SET_BT_STATUS_CMDID,
67660 +    WMI_SET_BT_PARAMS_CMDID,
67661 +
67662 +    WMI_SET_KEEPALIVE_CMDID,
67663 +    WMI_GET_KEEPALIVE_CMDID,
67664 +    WMI_SET_APPIE_CMDID,
67665 +    WMI_GET_APPIE_CMDID,
67666 +    WMI_SET_WSC_STATUS_CMDID,
67667 +
67668 +    /* Wake on Wireless */
67669 +    WMI_SET_HOST_SLEEP_MODE_CMDID,
67670 +    WMI_SET_WOW_MODE_CMDID,
67671 +    WMI_GET_WOW_LIST_CMDID,
67672 +    WMI_ADD_WOW_PATTERN_CMDID,
67673 +    WMI_DEL_WOW_PATTERN_CMDID,
67674 +    WMI_SET_MAC_ADDRESS_CMDID,
67675 +    WMI_SET_AKMP_PARAMS_CMDID,
67676 +    WMI_SET_PMKID_LIST_CMDID,
67677 +    WMI_GET_PMKID_LIST_CMDID,
67678 +
67679 +    /*
67680 +     * Developer commands starts at 0xF000
67681 +     */
67682 +    WMI_SET_BITRATE_CMDID = 0xF000,
67683 +    WMI_GET_BITRATE_CMDID,
67684 +    WMI_SET_WHALPARAM_CMDID,
67685 +
67686 +} WMI_COMMAND_ID;
67687 +
67688 +/*
67689 + * Frame Types
67690 + */
67691 +typedef enum {
67692 +    WMI_FRAME_BEACON        =   0,
67693 +    WMI_FRAME_PROBE_REQ,
67694 +    WMI_FRAME_PROBE_RESP,
67695 +    WMI_FRAME_ASSOC_REQ,
67696 +    WMI_FRAME_ASSOC_RESP,
67697 +    WMI_NUM_MGMT_FRAME
67698 +} WMI_MGMT_FRAME_TYPE;
67699 +
67700 +/*
67701 + * Connect Command
67702 + */
67703 +typedef enum {
67704 +    INFRA_NETWORK       = 0x01,
67705 +    ADHOC_NETWORK       = 0x02,
67706 +    ADHOC_CREATOR       = 0x04,
67707 +} NETWORK_TYPE;
67708 +
67709 +typedef enum {
67710 +    OPEN_AUTH           = 0x01,
67711 +    SHARED_AUTH         = 0x02,
67712 +    LEAP_AUTH           = 0x04,  /* different from IEEE_AUTH_MODE definitions */
67713 +} DOT11_AUTH_MODE;
67714 +
67715 +typedef enum {
67716 +    NONE_AUTH           = 0x01,
67717 +    WPA_AUTH            = 0x02,
67718 +    WPA_PSK_AUTH        = 0x03,
67719 +    WPA2_AUTH           = 0x04,
67720 +    WPA2_PSK_AUTH       = 0x05,
67721 +    WPA_AUTH_CCKM       = 0x06,
67722 +    WPA2_AUTH_CCKM      = 0x07,
67723 +} AUTH_MODE;
67724 +
67725 +typedef enum {
67726 +    NONE_CRYPT          = 0x01,
67727 +    WEP_CRYPT           = 0x02,
67728 +    TKIP_CRYPT          = 0x03,
67729 +    AES_CRYPT           = 0x04,
67730 +} CRYPTO_TYPE;
67731 +
67732 +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
67733 +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
67734 +
67735 +#define WMI_MIN_KEY_INDEX   0
67736 +#define WMI_MAX_KEY_INDEX   3
67737 +
67738 +#define WMI_MAX_KEY_LEN     32
67739 +
67740 +#define WMI_MAX_SSID_LEN    32
67741 +
67742 +typedef enum {
67743 +    CONNECT_ASSOC_POLICY_USER = 0x0001,
67744 +    CONNECT_SEND_REASSOC = 0x0002,
67745 +    CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004,
67746 +    CONNECT_PROFILE_MATCH_DONE = 0x0008,
67747 +    CONNECT_IGNORE_AAC_BEACON = 0x0010,
67748 +    CONNECT_CSA_FOLLOW_BSS = 0x0020,
67749 +} WMI_CONNECT_CTRL_FLAGS_BITS;
67750 +
67751 +#define DEFAULT_CONNECT_CTRL_FLAGS         (CONNECT_CSA_FOLLOW_BSS)
67752 +
67753 +typedef PREPACK struct {
67754 +    A_UINT8     networkType;
67755 +    A_UINT8     dot11AuthMode;
67756 +    A_UINT8     authMode;
67757 +    A_UINT8     pairwiseCryptoType;
67758 +    A_UINT8     pairwiseCryptoLen;
67759 +    A_UINT8     groupCryptoType;
67760 +    A_UINT8     groupCryptoLen;
67761 +    A_UINT8     ssidLength;
67762 +    A_UCHAR     ssid[WMI_MAX_SSID_LEN];
67763 +    A_UINT16    channel;
67764 +    A_UINT8     bssid[ATH_MAC_LEN];
67765 +    A_UINT32    ctrl_flags;
67766 +} POSTPACK WMI_CONNECT_CMD;
67767 +
67768 +/*
67769 + * WMI_RECONNECT_CMDID
67770 + */
67771 +typedef PREPACK struct {
67772 +    A_UINT16    channel;                    /* hint */
67773 +    A_UINT8     bssid[ATH_MAC_LEN];         /* mandatory if set */
67774 +} POSTPACK WMI_RECONNECT_CMD;
67775 +
67776 +/*
67777 + * WMI_ADD_CIPHER_KEY_CMDID
67778 + */
67779 +typedef enum {
67780 +    PAIRWISE_USAGE      = 0x00,
67781 +    GROUP_USAGE         = 0x01,
67782 +    TX_USAGE            = 0x02,     /* default Tx Key - Static WEP only */
67783 +} KEY_USAGE;
67784 +
67785 +/*
67786 + * Bit Flag
67787 + * Bit 0 - Initialise TSC - default is Initialize
67788 + */
67789 +#define KEY_OP_INIT_TSC       0x01
67790 +#define KEY_OP_INIT_RSC       0x02
67791 +
67792 +#define KEY_OP_INIT_VAL     0x03     /* Default Initialise the TSC & RSC */
67793 +#define KEY_OP_VALID_MASK   0x03
67794 +
67795 +typedef PREPACK struct {
67796 +    A_UINT8     keyIndex;
67797 +    A_UINT8     keyType;
67798 +    A_UINT8     keyUsage;           /* KEY_USAGE */
67799 +    A_UINT8     keyLength;
67800 +    A_UINT8     keyRSC[8];          /* key replay sequence counter */
67801 +    A_UINT8     key[WMI_MAX_KEY_LEN];
67802 +    A_UINT8     key_op_ctrl;       /* Additional Key Control information */
67803 +} POSTPACK WMI_ADD_CIPHER_KEY_CMD;
67804 +
67805 +/*
67806 + * WMI_DELETE_CIPHER_KEY_CMDID
67807 + */
67808 +typedef PREPACK struct {
67809 +    A_UINT8     keyIndex;
67810 +} POSTPACK WMI_DELETE_CIPHER_KEY_CMD;
67811 +
67812 +#define WMI_KRK_LEN     16
67813 +/*
67814 + * WMI_ADD_KRK_CMDID
67815 + */
67816 +typedef PREPACK struct {
67817 +    A_UINT8     krk[WMI_KRK_LEN];
67818 +} POSTPACK WMI_ADD_KRK_CMD;
67819 +
67820 +/*
67821 + * WMI_SET_TKIP_COUNTERMEASURES_CMDID
67822 + */
67823 +typedef enum {
67824 +    WMI_TKIP_CM_DISABLE = 0x0,
67825 +    WMI_TKIP_CM_ENABLE  = 0x1,
67826 +} WMI_TKIP_CM_CONTROL;
67827 +
67828 +typedef PREPACK struct {
67829 +    A_UINT8  cm_en;                     /* WMI_TKIP_CM_CONTROL */
67830 +} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
67831 +
67832 +/*
67833 + * WMI_SET_PMKID_CMDID
67834 + */
67835 +
67836 +#define WMI_PMKID_LEN 16
67837 +
67838 +typedef enum {
67839 +   PMKID_DISABLE = 0,
67840 +   PMKID_ENABLE  = 1,
67841 +} PMKID_ENABLE_FLG;
67842 +
67843 +typedef PREPACK struct {
67844 +    A_UINT8     bssid[ATH_MAC_LEN];
67845 +    A_UINT8     enable;                 /* PMKID_ENABLE_FLG */
67846 +    A_UINT8     pmkid[WMI_PMKID_LEN];
67847 +} POSTPACK WMI_SET_PMKID_CMD;
67848 +
67849 +/*
67850 + * WMI_START_SCAN_CMD
67851 + */
67852 +typedef enum {
67853 +    WMI_LONG_SCAN  = 0,
67854 +    WMI_SHORT_SCAN = 1,
67855 +} WMI_SCAN_TYPE;
67856 +
67857 +typedef PREPACK struct {
67858 +    A_BOOL   forceFgScan;
67859 +    A_BOOL   isLegacy;        /* For Legacy Cisco AP compatibility */
67860 +    A_UINT32 homeDwellTime;   /* Maximum duration in the home channel(milliseconds) */
67861 +    A_UINT32 forceScanInterval;    /* Time interval between scans (milliseconds)*/
67862 +    A_UINT8  scanType;           /* WMI_SCAN_TYPE */
67863 +} POSTPACK WMI_START_SCAN_CMD;
67864 +
67865 +/*
67866 + * WMI_SET_SCAN_PARAMS_CMDID
67867 + */
67868 +#define WMI_SHORTSCANRATIO_DEFAULT      3
67869 +typedef enum {
67870 +    CONNECT_SCAN_CTRL_FLAGS = 0x01,    /* set if can scan in the Connect cmd */
67871 +    SCAN_CONNECTED_CTRL_FLAGS = 0x02,  /* set if scan for the SSID it is */
67872 +                                       /* already connected to */
67873 +    ACTIVE_SCAN_CTRL_FLAGS = 0x04,     /* set if enable active scan */
67874 +    ROAM_SCAN_CTRL_FLAGS = 0x08,       /* set if enable roam scan when bmiss and lowrssi */
67875 +    REPORT_BSSINFO_CTRL_FLAGS = 0x10,   /* set if follows customer BSSINFO reporting rule */
67876 +    ENABLE_AUTO_CTRL_FLAGS = 0x20,      /* if disabled, target doesn't
67877 +                                          scan after a disconnect event  */
67878 +    ENABLE_SCAN_ABORT_EVENT = 0x40      /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */
67879 +
67880 +} WMI_SCAN_CTRL_FLAGS_BITS;
67881 +
67882 +#define CAN_SCAN_IN_CONNECT(flags)      (flags & CONNECT_SCAN_CTRL_FLAGS)
67883 +#define CAN_SCAN_CONNECTED(flags)       (flags & SCAN_CONNECTED_CTRL_FLAGS)
67884 +#define ENABLE_ACTIVE_SCAN(flags)       (flags & ACTIVE_SCAN_CTRL_FLAGS)
67885 +#define ENABLE_ROAM_SCAN(flags)         (flags & ROAM_SCAN_CTRL_FLAGS)
67886 +#define CONFIG_REPORT_BSSINFO(flags)     (flags & REPORT_BSSINFO_CTRL_FLAGS)
67887 +#define IS_AUTO_SCAN_ENABLED(flags)      (flags & ENABLE_AUTO_CTRL_FLAGS)
67888 +#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT)
67889 +
67890 +#define DEFAULT_SCAN_CTRL_FLAGS         (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS)
67891 +
67892 +
67893 +typedef PREPACK struct {
67894 +    A_UINT16    fg_start_period;        /* seconds */
67895 +    A_UINT16    fg_end_period;          /* seconds */
67896 +    A_UINT16    bg_period;              /* seconds */
67897 +    A_UINT16    maxact_chdwell_time;    /* msec */
67898 +    A_UINT16    pas_chdwell_time;       /* msec */
67899 +    A_UINT8     shortScanRatio;         /* how many shorts scan for one long */
67900 +    A_UINT8     scanCtrlFlags;
67901 +    A_UINT16    minact_chdwell_time;    /* msec */
67902 +    A_UINT32    max_dfsch_act_time;  /* msecs */
67903 +} POSTPACK WMI_SCAN_PARAMS_CMD;
67904 +
67905 +/*
67906 + * WMI_SET_BSS_FILTER_CMDID
67907 + */
67908 +typedef enum {
67909 +    NONE_BSS_FILTER = 0x0,              /* no beacons forwarded */
67910 +    ALL_BSS_FILTER,                     /* all beacons forwarded */
67911 +    PROFILE_FILTER,                     /* only beacons matching profile */
67912 +    ALL_BUT_PROFILE_FILTER,             /* all but beacons matching profile */
67913 +    CURRENT_BSS_FILTER,                 /* only beacons matching current BSS */
67914 +    ALL_BUT_BSS_FILTER,                 /* all but beacons matching BSS */
67915 +    PROBED_SSID_FILTER,                 /* beacons matching probed ssid */
67916 +    LAST_BSS_FILTER,                    /* marker only */
67917 +} WMI_BSS_FILTER;
67918 +
67919 +typedef PREPACK struct {
67920 +    A_UINT8    bssFilter;                      /* see WMI_BSS_FILTER */
67921 +    A_UINT32   ieMask;
67922 +} POSTPACK WMI_BSS_FILTER_CMD;
67923 +
67924 +/*
67925 + * WMI_SET_PROBED_SSID_CMDID
67926 + */
67927 +#define MAX_PROBED_SSID_INDEX   5
67928 +
67929 +typedef enum {
67930 +    DISABLE_SSID_FLAG  = 0,                  /* disables entry */
67931 +    SPECIFIC_SSID_FLAG = 0x01,               /* probes specified ssid */
67932 +    ANY_SSID_FLAG      = 0x02,               /* probes for any ssid */
67933 +} WMI_SSID_FLAG;
67934 +
67935 +typedef PREPACK struct {
67936 +    A_UINT8     entryIndex;                     /* 0 to MAX_PROBED_SSID_INDEX */
67937 +    A_UINT8     flag;                           /* WMI_SSID_FLG */
67938 +    A_UINT8     ssidLength;
67939 +    A_UINT8     ssid[32];
67940 +} POSTPACK WMI_PROBED_SSID_CMD;
67941 +
67942 +/*
67943 + * WMI_SET_LISTEN_INT_CMDID
67944 + * The Listen interval is between 15 and 3000 TUs
67945 + */
67946 +#define MIN_LISTEN_INTERVAL 15
67947 +#define MAX_LISTEN_INTERVAL 5000
67948 +#define MIN_LISTEN_BEACONS 1
67949 +#define MAX_LISTEN_BEACONS 50
67950 +
67951 +typedef PREPACK struct {
67952 +    A_UINT16     listenInterval;
67953 +    A_UINT16     numBeacons;
67954 +} POSTPACK WMI_LISTEN_INT_CMD;
67955 +
67956 +/*
67957 + * WMI_SET_BEACON_INT_CMDID
67958 + */
67959 +typedef PREPACK struct {
67960 +    A_UINT16     beaconInterval;
67961 +} POSTPACK WMI_BEACON_INT_CMD;
67962 +
67963 +/*
67964 + * WMI_SET_BMISS_TIME_CMDID
67965 + * valid values are between 1000 and 5000 TUs
67966 + */
67967 +
67968 +#define MIN_BMISS_TIME     1000
67969 +#define MAX_BMISS_TIME     5000
67970 +#define MIN_BMISS_BEACONS  1
67971 +#define MAX_BMISS_BEACONS  50
67972 +
67973 +typedef PREPACK struct {
67974 +    A_UINT16     bmissTime;
67975 +    A_UINT16     numBeacons;
67976 +} POSTPACK WMI_BMISS_TIME_CMD;
67977 +
67978 +/*
67979 + * WMI_SET_POWER_MODE_CMDID
67980 + */
67981 +typedef enum {
67982 +    REC_POWER = 0x01,
67983 +    MAX_PERF_POWER,
67984 +} WMI_POWER_MODE;
67985 +
67986 +typedef PREPACK struct {
67987 +    A_UINT8     powerMode;      /* WMI_POWER_MODE */
67988 +} POSTPACK WMI_POWER_MODE_CMD;
67989 +
67990 +/*
67991 + * WMI_SET_POWER_PARAMS_CMDID
67992 + */
67993 +typedef enum {
67994 +    IGNORE_DTIM = 0x01,
67995 +    NORMAL_DTIM = 0x02,
67996 +    STICK_DTIM  = 0x03,
67997 +} WMI_DTIM_POLICY;
67998 +
67999 +typedef PREPACK struct {
68000 +    A_UINT16    idle_period;             /* msec */
68001 +    A_UINT16    pspoll_number;
68002 +    A_UINT16    dtim_policy;
68003 +} POSTPACK WMI_POWER_PARAMS_CMD;
68004 +
68005 +typedef PREPACK struct {
68006 +    A_UINT8    power_saving;
68007 +    A_UINT8    ttl; /* number of beacon periods */
68008 +    A_UINT16   atim_windows;          /* msec */
68009 +    A_UINT16   timeout_value;         /* msec */
68010 +} POSTPACK WMI_IBSS_PM_CAPS_CMD;
68011 +
68012 +/*
68013 + * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID
68014 + */
68015 +typedef enum {
68016 +    IGNORE_TIM_ALL_QUEUES_APSD = 0,
68017 +    PROCESS_TIM_ALL_QUEUES_APSD = 1,
68018 +    IGNORE_TIM_SIMULATED_APSD = 2,
68019 +    PROCESS_TIM_SIMULATED_APSD = 3,
68020 +} APSD_TIM_POLICY;
68021 +
68022 +typedef PREPACK struct {
68023 +    A_UINT16    psPollTimeout;          /* msec */
68024 +    A_UINT16    triggerTimeout;         /* msec */
68025 +    A_UINT32    apsdTimPolicy;      /* TIM behavior with  ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */
68026 +    A_UINT32    simulatedAPSDTimPolicy;      /* TIM behavior with  simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */
68027 +} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD;
68028 +
68029 +/*
68030 + * WMI_SET_VOICE_PKT_SIZE_CMDID
68031 + */
68032 +typedef PREPACK struct {
68033 +    A_UINT16    voicePktSize;
68034 +} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD;
68035 +
68036 +/*
68037 + * WMI_SET_MAX_SP_LEN_CMDID
68038 + */
68039 +typedef enum {
68040 +    DELIVER_ALL_PKT = 0x0,
68041 +    DELIVER_2_PKT = 0x1,
68042 +    DELIVER_4_PKT = 0x2,
68043 +    DELIVER_6_PKT = 0x3,
68044 +} APSD_SP_LEN_TYPE;
68045 +
68046 +typedef PREPACK struct {
68047 +    A_UINT8    maxSPLen;
68048 +} POSTPACK WMI_SET_MAX_SP_LEN_CMD;
68049 +
68050 +/*
68051 + * WMI_SET_DISC_TIMEOUT_CMDID
68052 + */
68053 +typedef PREPACK struct {
68054 +    A_UINT8     disconnectTimeout;          /* seconds */
68055 +} POSTPACK WMI_DISC_TIMEOUT_CMD;
68056 +
68057 +typedef enum {
68058 +    UPLINK_TRAFFIC = 0,
68059 +    DNLINK_TRAFFIC = 1,
68060 +    BIDIR_TRAFFIC = 2,
68061 +} DIR_TYPE;
68062 +
68063 +typedef enum {
68064 +    DISABLE_FOR_THIS_AC = 0,
68065 +    ENABLE_FOR_THIS_AC  = 1,
68066 +    ENABLE_FOR_ALL_AC   = 2,
68067 +} VOICEPS_CAP_TYPE;
68068 +
68069 +typedef enum {
68070 +    TRAFFIC_TYPE_APERIODIC = 0,
68071 +    TRAFFIC_TYPE_PERIODIC = 1,
68072 +}TRAFFIC_TYPE;
68073 +
68074 +/*
68075 + * WMI_CREATE_PSTREAM_CMDID
68076 + */
68077 +typedef PREPACK struct {
68078 +    A_UINT32        minServiceInt;           /* in milli-sec */
68079 +    A_UINT32        maxServiceInt;           /* in milli-sec */
68080 +    A_UINT32        inactivityInt;           /* in milli-sec */
68081 +    A_UINT32        suspensionInt;           /* in milli-sec */
68082 +    A_UINT32        serviceStartTime;
68083 +    A_UINT32        minDataRate;             /* in bps */
68084 +    A_UINT32        meanDataRate;            /* in bps */
68085 +    A_UINT32        peakDataRate;            /* in bps */
68086 +    A_UINT32        maxBurstSize;
68087 +    A_UINT32        delayBound;
68088 +    A_UINT32        minPhyRate;              /* in bps */
68089 +    A_UINT32        sba;
68090 +    A_UINT32        mediumTime;
68091 +    A_UINT16        nominalMSDU;             /* in octects */
68092 +    A_UINT16        maxMSDU;                 /* in octects */
68093 +    A_UINT8         trafficClass;
68094 +    A_UINT8         trafficType;             /* TRAFFIC_TYPE */
68095 +    A_UINT8         trafficDirection;        /* TRAFFIC_DIR */
68096 +    A_UINT8         voicePSCapability;       /* VOICEPS_CAP_TYPE */
68097 +    A_UINT8         tsid;
68098 +    A_UINT8         userPriority;            /* 802.1D user priority */
68099 +} POSTPACK WMI_CREATE_PSTREAM_CMD;
68100 +
68101 +/*
68102 + * WMI_DELETE_PSTREAM_CMDID
68103 + */
68104 +typedef PREPACK struct {
68105 +    A_UINT8     trafficClass;
68106 +    A_UINT8     tsid;
68107 +} POSTPACK WMI_DELETE_PSTREAM_CMD;
68108 +
68109 +/*
68110 + * WMI_SET_CHANNEL_PARAMS_CMDID
68111 + */
68112 +typedef enum {
68113 +    WMI_11A_MODE  = 0x1,
68114 +    WMI_11G_MODE  = 0x2,
68115 +    WMI_11AG_MODE = 0x3,
68116 +    WMI_11B_MODE  = 0x4,
68117 +    WMI_11GONLY_MODE = 0x5,
68118 +} WMI_PHY_MODE;
68119 +
68120 +#define WMI_MAX_CHANNELS        32
68121 +
68122 +typedef PREPACK struct {
68123 +    A_UINT8     reserved1;
68124 +    A_UINT8     scanParam;              /* set if enable scan */
68125 +    A_UINT8     phyMode;                /* see WMI_PHY_MODE */
68126 +    A_UINT8     numChannels;            /* how many channels follow */
68127 +    A_UINT16    channelList[1];         /* channels in Mhz */
68128 +} POSTPACK WMI_CHANNEL_PARAMS_CMD;
68129 +
68130 +
68131 +/*
68132 + *  WMI_RSSI_THRESHOLD_PARAMS_CMDID
68133 + *  Setting the polltime to 0 would disable polling.
68134 + *  Threshold values are in the ascending order, and should agree to:
68135 + *  (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
68136 + *      < highThreshold_upperVal)
68137 + */
68138 +
68139 +typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{
68140 +    A_UINT32    pollTime;               /* Polling time as a factor of LI */
68141 +    A_INT16     thresholdAbove1_Val;          /* lowest of upper */
68142 +    A_INT16     thresholdAbove2_Val;
68143 +    A_INT16     thresholdAbove3_Val;
68144 +    A_INT16     thresholdAbove4_Val;
68145 +    A_INT16     thresholdAbove5_Val;
68146 +    A_INT16     thresholdAbove6_Val;          /* highest of upper */
68147 +    A_INT16     thresholdBelow1_Val;         /* lowest of bellow */
68148 +    A_INT16     thresholdBelow2_Val;
68149 +    A_INT16     thresholdBelow3_Val;
68150 +    A_INT16     thresholdBelow4_Val;
68151 +    A_INT16     thresholdBelow5_Val;
68152 +    A_INT16     thresholdBelow6_Val;         /* highest of bellow */
68153 +    A_UINT8     weight;                  /* "alpha" */
68154 +    A_UINT8     reserved[3];
68155 +} POSTPACK  WMI_RSSI_THRESHOLD_PARAMS_CMD;
68156 +
68157 +/*
68158 + *  WMI_SNR_THRESHOLD_PARAMS_CMDID
68159 + *  Setting the polltime to 0 would disable polling.
68160 + */
68161 +
68162 +typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{
68163 +    A_UINT32    pollTime;               /* Polling time as a factor of LI */
68164 +    A_UINT8     weight;                  /* "alpha" */
68165 +    A_UINT8     thresholdAbove1_Val;      /* lowest of uppper*/
68166 +    A_UINT8     thresholdAbove2_Val;
68167 +    A_UINT8     thresholdAbove3_Val;
68168 +    A_UINT8     thresholdAbove4_Val;      /* highest of upper */
68169 +    A_UINT8     thresholdBelow1_Val;     /* lowest of bellow */
68170 +    A_UINT8     thresholdBelow2_Val;
68171 +    A_UINT8     thresholdBelow3_Val;
68172 +    A_UINT8     thresholdBelow4_Val;     /* highest of bellow */
68173 +    A_UINT8     reserved[3];
68174 +} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD;
68175 +
68176 +/*
68177 + *  WMI_LQ_THRESHOLD_PARAMS_CMDID
68178 + */
68179 +typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS {
68180 +    A_UINT8     enable;
68181 +    A_UINT8     thresholdAbove1_Val;
68182 +    A_UINT8     thresholdAbove2_Val;
68183 +    A_UINT8     thresholdAbove3_Val;
68184 +    A_UINT8     thresholdAbove4_Val;
68185 +    A_UINT8     thresholdBelow1_Val;
68186 +    A_UINT8     thresholdBelow2_Val;
68187 +    A_UINT8     thresholdBelow3_Val;
68188 +    A_UINT8     thresholdBelow4_Val;
68189 +    A_UINT8     reserved[3];
68190 +} POSTPACK  WMI_LQ_THRESHOLD_PARAMS_CMD;
68191 +
68192 +typedef enum {
68193 +    WMI_LPREAMBLE_DISABLED = 0,
68194 +    WMI_LPREAMBLE_ENABLED
68195 +} WMI_LPREAMBLE_STATUS;
68196 +
68197 +typedef PREPACK struct {
68198 +    A_UINT8     status;
68199 +}POSTPACK WMI_SET_LPREAMBLE_CMD;
68200 +
68201 +typedef PREPACK struct {
68202 +    A_UINT16    threshold;
68203 +}POSTPACK WMI_SET_RTS_CMD;
68204 +
68205 +/*
68206 + *  WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
68207 + *  Sets the error reporting event bitmask in target. Target clears it
68208 + *  upon an error. Subsequent errors are counted, but not reported
68209 + *  via event, unless the bitmask is set again.
68210 + */
68211 +typedef PREPACK struct {
68212 +    A_UINT32    bitmask;
68213 +} POSTPACK  WMI_TARGET_ERROR_REPORT_BITMASK;
68214 +
68215 +/*
68216 + * WMI_SET_TX_PWR_CMDID
68217 + */
68218 +typedef PREPACK struct {
68219 +    A_UINT8     dbM;                  /* in dbM units */
68220 +} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
68221 +
68222 +/*
68223 + * WMI_SET_ASSOC_INFO_CMDID
68224 + *
68225 + * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
68226 + * A 3rd one, the CCX version IE can also be set from the host.
68227 + */
68228 +#define WMI_MAX_ASSOC_INFO_TYPE    2
68229 +#define WMI_CCX_VER_IE             2 /* ieType to set CCX Version IE */
68230 +
68231 +#define WMI_MAX_ASSOC_INFO_LEN     240
68232 +
68233 +typedef PREPACK struct {
68234 +    A_UINT8     ieType;
68235 +    A_UINT8     bufferSize;
68236 +    A_UINT8     assocInfo[1];       /* up to WMI_MAX_ASSOC_INFO_LEN */
68237 +} POSTPACK WMI_SET_ASSOC_INFO_CMD;
68238 +
68239 +
68240 +/*
68241 + * WMI_GET_TX_PWR_CMDID does not take any parameters
68242 + */
68243 +
68244 +/*
68245 + * WMI_ADD_BAD_AP_CMDID
68246 + */
68247 +#define WMI_MAX_BAD_AP_INDEX      1
68248 +
68249 +typedef PREPACK struct {
68250 +    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
68251 +    A_UINT8     bssid[ATH_MAC_LEN];
68252 +} POSTPACK WMI_ADD_BAD_AP_CMD;
68253 +
68254 +/*
68255 + * WMI_DELETE_BAD_AP_CMDID
68256 + */
68257 +typedef PREPACK struct {
68258 +    A_UINT8     badApIndex;         /* 0 to WMI_MAX_BAD_AP_INDEX */
68259 +} POSTPACK WMI_DELETE_BAD_AP_CMD;
68260 +
68261 +/*
68262 + * WMI_SET_ACCESS_PARAMS_CMDID
68263 + */
68264 +#define WMI_DEFAULT_TXOP_ACPARAM    0       /* implies one MSDU */
68265 +#define WMI_DEFAULT_ECWMIN_ACPARAM  4       /* corresponds to CWmin of 15 */
68266 +#define WMI_DEFAULT_ECWMAX_ACPARAM  10      /* corresponds to CWmax of 1023 */
68267 +#define WMI_MAX_CW_ACPARAM          15      /* maximum eCWmin or eCWmax */
68268 +#define WMI_DEFAULT_AIFSN_ACPARAM   2
68269 +#define WMI_MAX_AIFSN_ACPARAM       15
68270 +typedef PREPACK struct {
68271 +    A_UINT16 txop;                      /* in units of 32 usec */
68272 +    A_UINT8  eCWmin;
68273 +    A_UINT8  eCWmax;
68274 +    A_UINT8  aifsn;
68275 +} POSTPACK WMI_SET_ACCESS_PARAMS_CMD;
68276 +
68277 +
68278 +/*
68279 + * WMI_SET_RETRY_LIMITS_CMDID
68280 + *
68281 + * This command is used to customize the number of retries the
68282 + * wlan device will perform on a given frame.
68283 + */
68284 +#define WMI_MIN_RETRIES 2
68285 +#define WMI_MAX_RETRIES 13
68286 +typedef enum {
68287 +    MGMT_FRAMETYPE    = 0,
68288 +    CONTROL_FRAMETYPE = 1,
68289 +    DATA_FRAMETYPE    = 2
68290 +} WMI_FRAMETYPE;
68291 +
68292 +typedef PREPACK struct {
68293 +    A_UINT8 frameType;                      /* WMI_FRAMETYPE */
68294 +    A_UINT8 trafficClass;                   /* applies only to DATA_FRAMETYPE */
68295 +    A_UINT8 maxRetries;
68296 +    A_UINT8 enableNotify;
68297 +} POSTPACK WMI_SET_RETRY_LIMITS_CMD;
68298 +
68299 +/*
68300 + * WMI_SET_ROAM_CTRL_CMDID
68301 + *
68302 + * This command is used to influence the Roaming behaviour
68303 + * Set the host biases of the BSSs before setting the roam mode as bias
68304 + * based.
68305 + */
68306 +
68307 +/*
68308 + * Different types of Roam Control
68309 + */
68310 +
68311 +typedef enum {
68312 +        WMI_FORCE_ROAM          = 1,      /* Roam to the specified BSSID */
68313 +        WMI_SET_ROAM_MODE       = 2,      /* default ,progd bias, no roam */
68314 +        WMI_SET_HOST_BIAS       = 3,     /* Set the Host Bias */
68315 +        WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */
68316 +} WMI_ROAM_CTRL_TYPE;
68317 +
68318 +#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
68319 +#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS
68320 +
68321 +/*
68322 + * ROAM MODES
68323 + */
68324 +
68325 +typedef enum {
68326 +        WMI_DEFAULT_ROAM_MODE   = 1,  /* RSSI based ROAM */
68327 +        WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */
68328 +        WMI_LOCK_BSS_MODE  = 3  /* Lock to the Current BSS - no Roam */
68329 +} WMI_ROAM_MODE;
68330 +
68331 +/*
68332 + * BSS HOST BIAS INFO
68333 + */
68334 +
68335 +typedef PREPACK struct {
68336 +        A_UINT8 bssid[ATH_MAC_LEN];
68337 +        A_INT8  bias;
68338 +} POSTPACK WMI_BSS_BIAS;
68339 +
68340 +typedef PREPACK struct {
68341 +        A_UINT8 numBss;
68342 +        WMI_BSS_BIAS bssBias[1];
68343 +} POSTPACK WMI_BSS_BIAS_INFO;
68344 +
68345 +typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS {
68346 +        A_UINT16 lowrssi_scan_period;
68347 +        A_INT16  lowrssi_scan_threshold;
68348 +        A_INT16  lowrssi_roam_threshold;
68349 +        A_UINT8  roam_rssi_floor;
68350 +        A_UINT8  reserved[1];              /* For alignment */
68351 +} POSTPACK WMI_LOWRSSI_SCAN_PARAMS;
68352 +
68353 +typedef PREPACK struct {
68354 +    PREPACK union {
68355 +        A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */
68356 +        A_UINT8 roamMode;           /* WMI_SET_ROAM_MODE  */
68357 +        WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */
68358 +        WMI_LOWRSSI_SCAN_PARAMS lrScanParams;
68359 +    } POSTPACK info;
68360 +    A_UINT8   roamCtrlType ;
68361 +} POSTPACK WMI_SET_ROAM_CTRL_CMD;
68362 +
68363 +/*
68364 + * WMI_ENABLE_RM_CMDID
68365 + */
68366 +typedef PREPACK struct {
68367 +        A_BOOL enable_radio_measurements;
68368 +} POSTPACK WMI_ENABLE_RM_CMD;
68369 +
68370 +/*
68371 + * WMI_SET_MAX_OFFHOME_DURATION_CMDID
68372 + */
68373 +typedef PREPACK struct {
68374 +        A_UINT8 max_offhome_duration;
68375 +} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
68376 +
68377 +typedef PREPACK struct {
68378 +    A_UINT32 frequency;
68379 +    A_UINT8  threshold;
68380 +} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD;
68381 +
68382 +typedef enum {
68383 +    BT_STREAM_UNDEF = 0,
68384 +    BT_STREAM_SCO,             /* SCO stream */
68385 +    BT_STREAM_A2DP,            /* A2DP stream */
68386 +    BT_STREAM_MAX
68387 +} BT_STREAM_TYPE;
68388 +
68389 +typedef enum {
68390 +    BT_PARAM_SCO = 1,         /* SCO stream parameters */
68391 +    BT_PARAM_A2DP,            /* A2DP stream parameters */
68392 +    BT_PARAM_MISC,            /* miscellaneous parameters */
68393 +    BT_PARAM_REGS,            /* co-existence register parameters */
68394 +    BT_PARAM_MAX
68395 +} BT_PARAM_TYPE;
68396 +
68397 +typedef enum {
68398 +    BT_STATUS_UNDEF = 0,
68399 +    BT_STATUS_START,
68400 +    BT_STATUS_STOP,
68401 +    BT_STATUS_RESUME,
68402 +    BT_STATUS_SUSPEND,
68403 +    BT_STATUS_MAX
68404 +} BT_STREAM_STATUS;
68405 +
68406 +typedef PREPACK struct {
68407 +    A_UINT8 streamType;
68408 +    A_UINT8 status;
68409 +} POSTPACK WMI_SET_BT_STATUS_CMD;
68410 +
68411 +typedef PREPACK struct {
68412 +    A_UINT8 noSCOPkts;
68413 +    A_UINT8 pspollTimeout;
68414 +    A_UINT8 stompbt;
68415 +} POSTPACK BT_PARAMS_SCO;
68416 +
68417 +typedef PREPACK struct {
68418 +    A_UINT32 period;
68419 +    A_UINT32 dutycycle;
68420 +    A_UINT8  stompbt;
68421 +} POSTPACK BT_PARAMS_A2DP;
68422 +
68423 +typedef PREPACK struct {
68424 +    A_UINT32 mode;
68425 +    A_UINT32 scoWghts;
68426 +    A_UINT32 a2dpWghts;
68427 +    A_UINT32 genWghts;
68428 +    A_UINT32 mode2;
68429 +    A_UINT8  setVal;
68430 +} POSTPACK BT_COEX_REGS;
68431 +
68432 +typedef enum {
68433 +    WLAN_PROTECT_POLICY = 1,
68434 +    WLAN_COEX_CTRL_FLAGS
68435 +} BT_PARAMS_MISC_TYPE;
68436 +
68437 +typedef enum {
68438 +    WLAN_PROTECT_PER_STREAM = 0x01,   /* default */
68439 +    WLAN_PROTECT_ANY_TX = 0x02
68440 +} WLAN_PROTECT_FLAGS;
68441 +
68442 +
68443 +#define WLAN_DISABLE_COEX_IN_DISCONNECT   0x01 /* default */
68444 +#define WLAN_KEEP_COEX_IN_DISCONNECT      0x02
68445 +#define WLAN_STOMPBT_IN_DISCONNECT        0x04
68446 +
68447 +#define WLAN_DISABLE_COEX_IN_ROAM         0x10 /* default */
68448 +#define WLAN_KEEP_COEX_IN_ROAM            0x20
68449 +#define WLAN_STOMPBT_IN_ROAM              0x40
68450 +
68451 +#define WLAN_DISABLE_COEX_IN_SCAN        0x100 /* default */
68452 +#define WLAN_KEEP_COEX_IN_SCAN           0x200
68453 +#define WLAN_STOMPBT_IN_SCAN             0x400
68454 +
68455 +#define WLAN_DISABLE_COEX_BT_OFF        0x1000 /* default */
68456 +#define WLAN_KEEP_COEX_BT_OFF           0x2000
68457 +#define WLAN_STOMPBT_BT_OFF             0x4000
68458 +
68459 +typedef PREPACK struct {
68460 +    A_UINT32 period;
68461 +    A_UINT32 dutycycle;
68462 +    A_UINT8  stompbt;
68463 +    A_UINT8  policy;
68464 +} POSTPACK WLAN_PROTECT_POLICY_TYPE;
68465 +
68466 +typedef PREPACK struct {
68467 +    PREPACK union {
68468 +        WLAN_PROTECT_POLICY_TYPE protectParams;
68469 +        A_UINT16 wlanCtrlFlags;
68470 +    } POSTPACK info;
68471 +    A_UINT8 paramType;
68472 +} POSTPACK BT_PARAMS_MISC;
68473 +
68474 +typedef PREPACK struct {
68475 +    PREPACK union {
68476 +        BT_PARAMS_SCO scoParams;
68477 +        BT_PARAMS_A2DP a2dpParams;
68478 +        BT_PARAMS_MISC miscParams;
68479 +        BT_COEX_REGS regs;
68480 +    } POSTPACK info;
68481 +    A_UINT8 paramType;
68482 +} POSTPACK WMI_SET_BT_PARAMS_CMD;
68483 +
68484 +/*
68485 + * Command Replies
68486 + */
68487 +
68488 +/*
68489 + * WMI_GET_CHANNEL_LIST_CMDID reply
68490 + */
68491 +typedef PREPACK struct {
68492 +    A_UINT8     reserved1;
68493 +    A_UINT8     numChannels;            /* number of channels in reply */
68494 +    A_UINT16    channelList[1];         /* channel in Mhz */
68495 +} POSTPACK WMI_CHANNEL_LIST_REPLY;
68496 +
68497 +typedef enum {
68498 +    A_SUCCEEDED = A_OK,
68499 +    A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250,
68500 +    A_SUCCEEDED_MODIFY_STREAM=251,
68501 +    A_FAILED_INVALID_STREAM = 252,
68502 +    A_FAILED_MAX_THINSTREAMS = 253,
68503 +    A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
68504 +} PSTREAM_REPLY_STATUS;
68505 +
68506 +/*
68507 + * List of Events (target to host)
68508 + */
68509 +typedef enum {
68510 +    WMI_READY_EVENTID           = 0x1001,
68511 +    WMI_CONNECT_EVENTID,
68512 +    WMI_DISCONNECT_EVENTID,
68513 +    WMI_BSSINFO_EVENTID,
68514 +    WMI_CMDERROR_EVENTID,
68515 +    WMI_REGDOMAIN_EVENTID,
68516 +    WMI_PSTREAM_TIMEOUT_EVENTID,
68517 +    WMI_NEIGHBOR_REPORT_EVENTID,
68518 +    WMI_TKIP_MICERR_EVENTID,
68519 +    WMI_SCAN_COMPLETE_EVENTID,
68520 +    WMI_REPORT_STATISTICS_EVENTID,
68521 +    WMI_RSSI_THRESHOLD_EVENTID,
68522 +    WMI_ERROR_REPORT_EVENTID,
68523 +    WMI_OPT_RX_FRAME_EVENTID,
68524 +    WMI_REPORT_ROAM_TBL_EVENTID,
68525 +    WMI_EXTENSION_EVENTID,
68526 +    WMI_CAC_EVENTID,
68527 +    WMI_SNR_THRESHOLD_EVENTID,
68528 +    WMI_LQ_THRESHOLD_EVENTID,
68529 +    WMI_TX_RETRY_ERR_EVENTID,
68530 +    WMI_REPORT_ROAM_DATA_EVENTID,
68531 +    WMI_TEST_EVENTID,
68532 +    WMI_APLIST_EVENTID,
68533 +    WMI_GET_WOW_LIST_EVENTID,
68534 +    WMI_GET_PMKID_LIST_EVENTID
68535 +} WMI_EVENT_ID;
68536 +
68537 +typedef enum {
68538 +    WMI_11A_CAPABILITY   = 1,
68539 +    WMI_11G_CAPABILITY   = 2,
68540 +    WMI_11AG_CAPABILITY  = 3,
68541 +} WMI_PHY_CAPABILITY;
68542 +
68543 +typedef PREPACK struct {
68544 +    A_UINT8     macaddr[ATH_MAC_LEN];
68545 +    A_UINT8     phyCapability;              /* WMI_PHY_CAPABILITY */
68546 +} POSTPACK WMI_READY_EVENT;
68547 +
68548 +/*
68549 + * Connect Event
68550 + */
68551 +typedef PREPACK struct {
68552 +    A_UINT16    channel;
68553 +    A_UINT8     bssid[ATH_MAC_LEN];
68554 +    A_UINT16    listenInterval;
68555 +    A_UINT16    beaconInterval;
68556 +    A_UINT32    networkType;
68557 +    A_UINT8     beaconIeLen;
68558 +    A_UINT8     assocReqLen;
68559 +    A_UINT8     assocRespLen;
68560 +    A_UINT8     assocInfo[1];
68561 +} POSTPACK WMI_CONNECT_EVENT;
68562 +
68563 +/*
68564 + * Disconnect Event
68565 + */
68566 +typedef enum {
68567 +    NO_NETWORK_AVAIL   = 0x01,
68568 +    LOST_LINK          = 0x02,     /* bmiss */
68569 +    DISCONNECT_CMD     = 0x03,
68570 +    BSS_DISCONNECTED   = 0x04,
68571 +    AUTH_FAILED        = 0x05,
68572 +    ASSOC_FAILED       = 0x06,
68573 +    NO_RESOURCES_AVAIL = 0x07,
68574 +    CSERV_DISCONNECT   = 0x08,
68575 +    INVALID_PROFILE    = 0x0a,
68576 +    DOT11H_CHANNEL_SWITCH = 0x0b,
68577 +} WMI_DISCONNECT_REASON;
68578 +
68579 +typedef PREPACK struct {
68580 +    A_UINT16    protocolReasonStatus;  /* reason code, see 802.11 spec. */
68581 +    A_UINT8     bssid[ATH_MAC_LEN];    /* set if known */
68582 +    A_UINT8     disconnectReason ;      /* see WMI_DISCONNECT_REASON */
68583 +    A_UINT8     assocRespLen;
68584 +    A_UINT8     assocInfo[1];
68585 +} POSTPACK WMI_DISCONNECT_EVENT;
68586 +
68587 +/*
68588 + * BSS Info Event.
68589 + * Mechanism used to inform host of the presence and characteristic of
68590 + * wireless networks present.  Consists of bss info header followed by
68591 + * the beacon or probe-response frame body.  The 802.11 header is not included.
68592 + */
68593 +typedef enum {
68594 +    BEACON_FTYPE = 0x1,
68595 +    PROBERESP_FTYPE,
68596 +    ACTION_MGMT_FTYPE,
68597 +} WMI_BI_FTYPE;
68598 +
68599 +enum {
68600 +    BSS_ELEMID_CHANSWITCH = 0x01,
68601 +    BSS_ELEMID_ATHEROS = 0x02,
68602 +};
68603 +
68604 +typedef PREPACK struct {
68605 +    A_UINT16    channel;
68606 +    A_UINT8     frameType;          /* see WMI_BI_FTYPE */
68607 +    A_UINT8     snr;
68608 +    A_INT16     rssi;
68609 +    A_UINT8     bssid[ATH_MAC_LEN];
68610 +    A_UINT32    ieMask;
68611 +} POSTPACK WMI_BSS_INFO_HDR;
68612 +
68613 +/*
68614 + * Command Error Event
68615 + */
68616 +typedef enum {
68617 +    INVALID_PARAM  = 0x01,
68618 +    ILLEGAL_STATE  = 0x02,
68619 +    INTERNAL_ERROR = 0x03,
68620 +} WMI_ERROR_CODE;
68621 +
68622 +typedef PREPACK struct {
68623 +    A_UINT16    commandId;
68624 +    A_UINT8     errorCode;
68625 +} POSTPACK WMI_CMD_ERROR_EVENT;
68626 +
68627 +/*
68628 + * New Regulatory Domain Event
68629 + */
68630 +typedef PREPACK struct {
68631 +    A_UINT32    regDomain;
68632 +} POSTPACK WMI_REG_DOMAIN_EVENT;
68633 +
68634 +typedef PREPACK struct {
68635 +    A_UINT8     trafficClass;
68636 +} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT;
68637 +
68638 +/*
68639 + * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
68640 + * the host of BSS's it has found that matches the current profile.
68641 + * It can be used by the host to cache PMKs and/to initiate pre-authentication
68642 + * if the BSS supports it.  The first bssid is always the current associated
68643 + * BSS.
68644 + * The bssid and bssFlags information repeats according to the number
68645 + * or APs reported.
68646 + */
68647 +typedef enum {
68648 +    WMI_DEFAULT_BSS_FLAGS   = 0x00,
68649 +    WMI_PREAUTH_CAPABLE_BSS = 0x01,
68650 +    WMI_PMKID_VALID_BSS     = 0x02,
68651 +} WMI_BSS_FLAGS;
68652 +
68653 +typedef PREPACK struct {
68654 +    A_UINT8     bssid[ATH_MAC_LEN];
68655 +    A_UINT8     bssFlags;            /* see WMI_BSS_FLAGS */
68656 +} POSTPACK WMI_NEIGHBOR_INFO;
68657 +
68658 +typedef PREPACK struct {
68659 +    A_INT8      numberOfAps;
68660 +    WMI_NEIGHBOR_INFO neighbor[1];
68661 +} POSTPACK WMI_NEIGHBOR_REPORT_EVENT;
68662 +
68663 +/*
68664 + * TKIP MIC Error Event
68665 + */
68666 +typedef PREPACK struct {
68667 +    A_UINT8 keyid;
68668 +    A_UINT8 ismcast;
68669 +} POSTPACK WMI_TKIP_MICERR_EVENT;
68670 +
68671 +/*
68672 + * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new)
68673 + */
68674 +typedef PREPACK struct {
68675 +    A_STATUS status;
68676 +} POSTPACK WMI_SCAN_COMPLETE_EVENT;
68677 +
68678 +#define MAX_OPT_DATA_LEN 1400
68679 +
68680 +/*
68681 + * WMI_SET_ADHOC_BSSID_CMDID
68682 + */
68683 +typedef PREPACK struct {
68684 +    A_UINT8     bssid[ATH_MAC_LEN];
68685 +} POSTPACK WMI_SET_ADHOC_BSSID_CMD;
68686 +
68687 +/*
68688 + * WMI_SET_OPT_MODE_CMDID
68689 + */
68690 +typedef enum {
68691 +    SPECIAL_OFF,
68692 +    SPECIAL_ON,
68693 +} OPT_MODE_TYPE;
68694 +
68695 +typedef PREPACK struct {
68696 +    A_UINT8     optMode;
68697 +} POSTPACK WMI_SET_OPT_MODE_CMD;
68698 +
68699 +/*
68700 + * WMI_TX_OPT_FRAME_CMDID
68701 + */
68702 +typedef enum {
68703 +    OPT_PROBE_REQ   = 0x01,
68704 +    OPT_PROBE_RESP  = 0x02,
68705 +    OPT_CPPP_START  = 0x03,
68706 +    OPT_CPPP_STOP   = 0x04,
68707 +} WMI_OPT_FTYPE;
68708 +
68709 +typedef PREPACK struct {
68710 +    A_UINT16    optIEDataLen;
68711 +    A_UINT8     frmType;
68712 +    A_UINT8     dstAddr[ATH_MAC_LEN];
68713 +    A_UINT8     bssid[ATH_MAC_LEN];
68714 +    A_UINT8     reserved;               /* For alignment */
68715 +    A_UINT8     optIEData[1];
68716 +} POSTPACK WMI_OPT_TX_FRAME_CMD;
68717 +
68718 +/*
68719 + * Special frame receive Event.
68720 + * Mechanism used to inform host of the receiption of the special frames.
68721 + * Consists of special frame info header followed by special frame body.
68722 + * The 802.11 header is not included.
68723 + */
68724 +typedef PREPACK struct {
68725 +    A_UINT16    channel;
68726 +    A_UINT8     frameType;          /* see WMI_OPT_FTYPE */
68727 +    A_INT8      snr;
68728 +    A_UINT8     srcAddr[ATH_MAC_LEN];
68729 +    A_UINT8     bssid[ATH_MAC_LEN];
68730 +} POSTPACK WMI_OPT_RX_INFO_HDR;
68731 +
68732 +/*
68733 + * Reporting statistics.
68734 + */
68735 +typedef PREPACK struct {
68736 +    A_UINT32   tx_packets;
68737 +    A_UINT32   tx_bytes;
68738 +    A_UINT32   tx_unicast_pkts;
68739 +    A_UINT32   tx_unicast_bytes;
68740 +    A_UINT32   tx_multicast_pkts;
68741 +    A_UINT32   tx_multicast_bytes;
68742 +    A_UINT32   tx_broadcast_pkts;
68743 +    A_UINT32   tx_broadcast_bytes;
68744 +    A_UINT32   tx_rts_success_cnt;
68745 +    A_UINT32   tx_packet_per_ac[4];
68746 +    A_UINT32   tx_errors_per_ac[4];
68747 +
68748 +    A_UINT32   tx_errors;
68749 +    A_UINT32   tx_failed_cnt;
68750 +    A_UINT32   tx_retry_cnt;
68751 +    A_UINT32   tx_rts_fail_cnt;
68752 +    A_INT32    tx_unicast_rate;
68753 +}POSTPACK tx_stats_t;
68754 +
68755 +typedef PREPACK struct {
68756 +    A_UINT32   rx_packets;
68757 +    A_UINT32   rx_bytes;
68758 +    A_UINT32   rx_unicast_pkts;
68759 +    A_UINT32   rx_unicast_bytes;
68760 +    A_UINT32   rx_multicast_pkts;
68761 +    A_UINT32   rx_multicast_bytes;
68762 +    A_UINT32   rx_broadcast_pkts;
68763 +    A_UINT32   rx_broadcast_bytes;
68764 +    A_UINT32   rx_fragment_pkt;
68765 +
68766 +    A_UINT32   rx_errors;
68767 +    A_UINT32   rx_crcerr;
68768 +    A_UINT32   rx_key_cache_miss;
68769 +    A_UINT32   rx_decrypt_err;
68770 +    A_UINT32   rx_duplicate_frames;
68771 +    A_INT32    rx_unicast_rate;
68772 +}POSTPACK rx_stats_t;
68773 +
68774 +typedef PREPACK struct {
68775 +    A_UINT32   tkip_local_mic_failure;
68776 +    A_UINT32   tkip_counter_measures_invoked;
68777 +    A_UINT32   tkip_replays;
68778 +    A_UINT32   tkip_format_errors;
68779 +    A_UINT32   ccmp_format_errors;
68780 +    A_UINT32   ccmp_replays;
68781 +}POSTPACK tkip_ccmp_stats_t;
68782 +
68783 +typedef PREPACK struct {
68784 +    A_UINT32   power_save_failure_cnt;
68785 +}POSTPACK pm_stats_t;
68786 +
68787 +typedef PREPACK struct {
68788 +    A_UINT32    cs_bmiss_cnt;
68789 +    A_UINT32    cs_lowRssi_cnt;
68790 +    A_UINT16    cs_connect_cnt;
68791 +    A_UINT16    cs_disconnect_cnt;
68792 +    A_INT16     cs_aveBeacon_rssi;
68793 +    A_UINT16    cs_roam_count;
68794 +    A_UINT16    cs_rssi;
68795 +    A_UINT8     cs_snr;
68796 +    A_UINT8     cs_aveBeacon_snr;
68797 +    A_UINT8     cs_lastRoam_msec;
68798 +} POSTPACK cserv_stats_t;
68799 +
68800 +typedef PREPACK struct {
68801 +    tx_stats_t          tx_stats;
68802 +    rx_stats_t          rx_stats;
68803 +    tkip_ccmp_stats_t   tkipCcmpStats;
68804 +}POSTPACK wlan_net_stats_t;
68805 +
68806 +typedef PREPACK struct {
68807 +    A_UINT32    wow_num_pkts_dropped;
68808 +    A_UINT16    wow_num_events_discarded;
68809 +    A_UINT8     wow_num_host_pkt_wakeups;
68810 +    A_UINT8     wow_num_host_event_wakeups;
68811 +} POSTPACK wlan_wow_stats_t;
68812 +
68813 +typedef PREPACK struct {
68814 +    A_UINT32            lqVal;
68815 +    A_INT32             noise_floor_calibation;
68816 +    pm_stats_t          pmStats;
68817 +    wlan_net_stats_t    txrxStats;
68818 +    wlan_wow_stats_t    wowStats;
68819 +    cserv_stats_t       cservStats;
68820 +} POSTPACK WMI_TARGET_STATS;
68821 +
68822 +/*
68823 + * WMI_RSSI_THRESHOLD_EVENTID.
68824 + * Indicate the RSSI events to host. Events are indicated when we breach a
68825 + * thresold value.
68826 + */
68827 +typedef enum{
68828 +    WMI_RSSI_THRESHOLD1_ABOVE = 0,
68829 +    WMI_RSSI_THRESHOLD2_ABOVE,
68830 +    WMI_RSSI_THRESHOLD3_ABOVE,
68831 +    WMI_RSSI_THRESHOLD4_ABOVE,
68832 +    WMI_RSSI_THRESHOLD5_ABOVE,
68833 +    WMI_RSSI_THRESHOLD6_ABOVE,
68834 +    WMI_RSSI_THRESHOLD1_BELOW,
68835 +    WMI_RSSI_THRESHOLD2_BELOW,
68836 +    WMI_RSSI_THRESHOLD3_BELOW,
68837 +    WMI_RSSI_THRESHOLD4_BELOW,
68838 +    WMI_RSSI_THRESHOLD5_BELOW,
68839 +    WMI_RSSI_THRESHOLD6_BELOW
68840 +}WMI_RSSI_THRESHOLD_VAL;
68841 +
68842 +typedef PREPACK struct {
68843 +    A_INT16 rssi;
68844 +    A_UINT8 range;
68845 +}POSTPACK WMI_RSSI_THRESHOLD_EVENT;
68846 +
68847 +/*
68848 + *  WMI_ERROR_REPORT_EVENTID
68849 + */
68850 +typedef enum{
68851 +    WMI_TARGET_PM_ERR_FAIL      = 0x00000001,
68852 +    WMI_TARGET_KEY_NOT_FOUND    = 0x00000002,
68853 +    WMI_TARGET_DECRYPTION_ERR   = 0x00000004,
68854 +    WMI_TARGET_BMISS            = 0x00000008,
68855 +    WMI_PSDISABLE_NODE_JOIN     = 0x00000010,
68856 +    WMI_TARGET_COM_ERR          = 0x00000020,
68857 +    WMI_TARGET_FATAL_ERR        = 0x00000040
68858 +} WMI_TARGET_ERROR_VAL;
68859 +
68860 +typedef PREPACK struct {
68861 +    A_UINT32 errorVal;
68862 +}POSTPACK  WMI_TARGET_ERROR_REPORT_EVENT;
68863 +
68864 +typedef PREPACK struct {
68865 +    A_UINT8 retrys;
68866 +}POSTPACK  WMI_TX_RETRY_ERR_EVENT;
68867 +
68868 +typedef enum{
68869 +    WMI_SNR_THRESHOLD1_ABOVE = 1,
68870 +    WMI_SNR_THRESHOLD1_BELOW,
68871 +    WMI_SNR_THRESHOLD2_ABOVE,
68872 +    WMI_SNR_THRESHOLD2_BELOW,
68873 +    WMI_SNR_THRESHOLD3_ABOVE,
68874 +    WMI_SNR_THRESHOLD3_BELOW,
68875 +    WMI_SNR_THRESHOLD4_ABOVE,
68876 +    WMI_SNR_THRESHOLD4_BELOW
68877 +} WMI_SNR_THRESHOLD_VAL;
68878 +
68879 +typedef PREPACK struct {
68880 +    A_UINT8 range;  /* WMI_SNR_THRESHOLD_VAL */
68881 +    A_UINT8 snr;
68882 +}POSTPACK  WMI_SNR_THRESHOLD_EVENT;
68883 +
68884 +typedef enum{
68885 +    WMI_LQ_THRESHOLD1_ABOVE = 1,
68886 +    WMI_LQ_THRESHOLD1_BELOW,
68887 +    WMI_LQ_THRESHOLD2_ABOVE,
68888 +    WMI_LQ_THRESHOLD2_BELOW,
68889 +    WMI_LQ_THRESHOLD3_ABOVE,
68890 +    WMI_LQ_THRESHOLD3_BELOW,
68891 +    WMI_LQ_THRESHOLD4_ABOVE,
68892 +    WMI_LQ_THRESHOLD4_BELOW
68893 +} WMI_LQ_THRESHOLD_VAL;
68894 +
68895 +typedef PREPACK struct {
68896 +    A_INT32 lq;
68897 +    A_UINT8 range;  /* WMI_LQ_THRESHOLD_VAL */
68898 +}POSTPACK  WMI_LQ_THRESHOLD_EVENT;
68899 +/*
68900 + * WMI_REPORT_ROAM_TBL_EVENTID
68901 + */
68902 +#define MAX_ROAM_TBL_CAND   5
68903 +
68904 +typedef PREPACK struct {
68905 +    A_INT32 roam_util;
68906 +    A_UINT8 bssid[ATH_MAC_LEN];
68907 +    A_INT8  rssi;
68908 +    A_INT8  rssidt;
68909 +    A_INT8  last_rssi;
68910 +    A_INT8  util;
68911 +    A_INT8  bias;
68912 +    A_UINT8 reserved; /* For alignment */
68913 +} POSTPACK WMI_BSS_ROAM_INFO;
68914 +
68915 +
68916 +typedef PREPACK struct {
68917 +    A_UINT16  roamMode;
68918 +    A_UINT16  numEntries;
68919 +    WMI_BSS_ROAM_INFO bssRoamInfo[1];
68920 +} POSTPACK WMI_TARGET_ROAM_TBL;
68921 +
68922 +/*
68923 + *  WMI_CAC_EVENTID
68924 + */
68925 +typedef enum {
68926 +    CAC_INDICATION_ADMISSION = 0x00,
68927 +    CAC_INDICATION_ADMISSION_RESP = 0x01,
68928 +    CAC_INDICATION_DELETE = 0x02,
68929 +    CAC_INDICATION_NO_RESP = 0x03,
68930 +}CAC_INDICATION;
68931 +
68932 +#define WMM_TSPEC_IE_LEN   63
68933 +
68934 +typedef PREPACK struct {
68935 +    A_UINT8 ac;
68936 +    A_UINT8 cac_indication;
68937 +    A_UINT8 statusCode;
68938 +    A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN];
68939 +}POSTPACK  WMI_CAC_EVENT;
68940 +
68941 +/*
68942 + * WMI_APLIST_EVENTID
68943 + */
68944 +
68945 +typedef enum {
68946 +    APLIST_VER1 = 1,
68947 +} APLIST_VER;
68948 +
68949 +typedef PREPACK struct {
68950 +    A_UINT8     bssid[ATH_MAC_LEN];
68951 +    A_UINT16    channel;
68952 +} POSTPACK  WMI_AP_INFO_V1;
68953 +
68954 +typedef PREPACK union {
68955 +    WMI_AP_INFO_V1  apInfoV1;
68956 +} POSTPACK WMI_AP_INFO;
68957 +
68958 +typedef PREPACK struct {
68959 +    A_UINT8     apListVer;
68960 +    A_UINT8     numAP;
68961 +    WMI_AP_INFO apList[1];
68962 +} POSTPACK WMI_APLIST_EVENT;
68963 +
68964 +/*
68965 + * developer commands
68966 + */
68967 +
68968 +/*
68969 + * WMI_SET_BITRATE_CMDID
68970 + *
68971 + * Get bit rate cmd uses same definition as set bit rate cmd
68972 + */
68973 +typedef enum {
68974 +    RATE_AUTO   = -1,
68975 +    RATE_1Mb    = 0,
68976 +    RATE_2Mb    = 1,
68977 +    RATE_5_5Mb  = 2,
68978 +    RATE_11Mb   = 3,
68979 +    RATE_6Mb    = 4,
68980 +    RATE_9Mb    = 5,
68981 +    RATE_12Mb   = 6,
68982 +    RATE_18Mb   = 7,
68983 +    RATE_24Mb   = 8,
68984 +    RATE_36Mb   = 9,
68985 +    RATE_48Mb   = 10,
68986 +    RATE_54Mb   = 11,
68987 +} WMI_BIT_RATE;
68988 +
68989 +typedef PREPACK struct {
68990 +    A_INT8      rateIndex;          /* see WMI_BIT_RATE */
68991 +} POSTPACK WMI_BIT_RATE_CMD, WMI_BIT_RATE_REPLY;
68992 +
68993 +/*
68994 + * WMI_SET_FIXRATES_CMDID
68995 + *
68996 + * Get fix rates cmd uses same definition as set fix rates cmd
68997 + */
68998 +typedef enum {
68999 +    FIX_RATE_1Mb    = 0x1,
69000 +    FIX_RATE_2Mb    = 0x2,
69001 +    FIX_RATE_5_5Mb  = 0x4,
69002 +    FIX_RATE_11Mb   = 0x8,
69003 +    FIX_RATE_6Mb    = 0x10,
69004 +    FIX_RATE_9Mb    = 0x20,
69005 +    FIX_RATE_12Mb   = 0x40,
69006 +    FIX_RATE_18Mb   = 0x80,
69007 +    FIX_RATE_24Mb   = 0x100,
69008 +    FIX_RATE_36Mb   = 0x200,
69009 +    FIX_RATE_48Mb   = 0x400,
69010 +    FIX_RATE_54Mb   = 0x800,
69011 +} WMI_FIX_RATES_MASK;
69012 +
69013 +typedef PREPACK struct {
69014 +    A_UINT16      fixRateMask;          /* see WMI_BIT_RATE */
69015 +} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY;
69016 +
69017 +/*
69018 + * WMI_SET_RECONNECT_AUTH_MODE_CMDID
69019 + *
69020 + * Set authentication mode
69021 + */
69022 +typedef enum {
69023 +    RECONN_DO_AUTH = 0x00,
69024 +    RECONN_NOT_AUTH = 0x01
69025 +} WMI_AUTH_MODE;
69026 +
69027 +typedef PREPACK struct {
69028 +    A_UINT8 mode;
69029 +} POSTPACK WMI_SET_AUTH_MODE_CMD;
69030 +
69031 +/*
69032 + * WMI_SET_REASSOC_MODE_CMDID
69033 + *
69034 + * Set authentication mode
69035 + */
69036 +typedef enum {
69037 +    REASSOC_DO_DISASSOC = 0x00,
69038 +    REASSOC_DONOT_DISASSOC = 0x01
69039 +} WMI_REASSOC_MODE;
69040 +
69041 +typedef PREPACK struct {
69042 +    A_UINT8 mode;
69043 +}POSTPACK WMI_SET_REASSOC_MODE_CMD;
69044 +
69045 +typedef enum {
69046 +    ROAM_DATA_TIME = 1,            /* Get The Roam Time Data */
69047 +} ROAM_DATA_TYPE;
69048 +
69049 +typedef PREPACK struct {
69050 +    A_UINT32        disassoc_time;
69051 +    A_UINT32        no_txrx_time;
69052 +    A_UINT32        assoc_time;
69053 +    A_UINT32        allow_txrx_time;
69054 +    A_UINT32        last_data_txrx_time;
69055 +    A_UINT32        first_data_txrx_time;
69056 +    A_UINT8         disassoc_bssid[ATH_MAC_LEN];
69057 +    A_INT8          disassoc_bss_rssi;
69058 +    A_UINT8         assoc_bssid[ATH_MAC_LEN];
69059 +    A_INT8          assoc_bss_rssi;
69060 +} POSTPACK WMI_TARGET_ROAM_TIME;
69061 +
69062 +typedef PREPACK struct {
69063 +    PREPACK union {
69064 +        WMI_TARGET_ROAM_TIME roamTime;
69065 +    } POSTPACK u;
69066 +    A_UINT8 roamDataType ;
69067 +} POSTPACK WMI_TARGET_ROAM_DATA;
69068 +
69069 +typedef enum {
69070 +    WMI_WMM_DISABLED = 0,
69071 +    WMI_WMM_ENABLED
69072 +} WMI_WMM_STATUS;
69073 +
69074 +typedef PREPACK struct {
69075 +    A_UINT8    status;
69076 +}POSTPACK WMI_SET_WMM_CMD;
69077 +
69078 +typedef enum {
69079 +    WMI_TXOP_DISABLED = 0,
69080 +    WMI_TXOP_ENABLED
69081 +} WMI_TXOP_CFG;
69082 +
69083 +typedef PREPACK struct {
69084 +    A_UINT8    txopEnable;
69085 +}POSTPACK WMI_SET_WMM_TXOP_CMD;
69086 +
69087 +typedef PREPACK struct {
69088 +    A_UINT8 keepaliveInterval;
69089 +} POSTPACK WMI_SET_KEEPALIVE_CMD;
69090 +
69091 +typedef PREPACK struct {
69092 +    A_BOOL configured;
69093 +    A_UINT8 keepaliveInterval;
69094 +} POSTPACK WMI_GET_KEEPALIVE_CMD;
69095 +
69096 +/*
69097 + * Add Application specified IE to a management frame
69098 + */
69099 +#define WMI_MAX_IE_LEN  78
69100 +
69101 +typedef PREPACK struct {
69102 +    A_UINT8 mgmtFrmType;  /* one of WMI_MGMT_FRAME_TYPE */
69103 +    A_UINT8 ieLen;    /* Length  of the IE that should be added to the MGMT frame */
69104 +    A_UINT8 ieInfo[1];
69105 +} POSTPACK WMI_SET_APPIE_CMD;
69106 +
69107 +/*
69108 + * Notify the WSC registration status to the target
69109 + */
69110 +#define WSC_REG_ACTIVE     1
69111 +#define WSC_REG_INACTIVE   0
69112 +/* Generic Hal Interface for setting hal paramters. */
69113 +/* Add new Set HAL Param cmdIds here for newer params */
69114 +typedef enum {
69115 +   WHAL_SETCABTO_CMDID = 1,
69116 +}WHAL_CMDID;
69117 +
69118 +typedef PREPACK struct {
69119 +    A_UINT8 cabTimeOut;
69120 +} POSTPACK WHAL_SETCABTO_PARAM;
69121 +
69122 +typedef PREPACK struct {
69123 +    A_UINT8  whalCmdId;
69124 +    A_UINT8 data[1];
69125 +} POSTPACK WHAL_PARAMCMD;
69126 +
69127 +
69128 +#define WOW_MAX_FILTER_LISTS 1 /*4*/
69129 +#define WOW_MAX_FILTERS_PER_LIST 4
69130 +#define WOW_PATTERN_SIZE 64
69131 +#define WOW_MASK_SIZE 64
69132 +
69133 +typedef PREPACK struct {
69134 +    A_UINT8 wow_valid_filter;
69135 +    A_UINT8 wow_filter_id;
69136 +    A_UINT8 wow_filter_size;
69137 +    A_UINT8 wow_filter_offset;
69138 +    A_UINT8 wow_filter_mask[WOW_MASK_SIZE];
69139 +    A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE];
69140 +} POSTPACK WOW_FILTER;
69141 +
69142 +
69143 +typedef PREPACK struct {
69144 +    A_UINT8 wow_valid_list;
69145 +    A_UINT8 wow_list_id;
69146 +    A_UINT8 wow_num_filters;
69147 +    A_UINT8 wow_total_list_size;
69148 +    WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST];
69149 +} POSTPACK WOW_FILTER_LIST;
69150 +
69151 +typedef PREPACK struct {
69152 +    A_BOOL awake;
69153 +    A_BOOL asleep;
69154 +} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD;
69155 +
69156 +typedef PREPACK struct {
69157 +    A_BOOL enable_wow;
69158 +} POSTPACK WMI_SET_WOW_MODE_CMD;
69159 +
69160 +typedef PREPACK struct {
69161 +    A_UINT8 filter_list_id;
69162 +} POSTPACK WMI_GET_WOW_LIST_CMD;
69163 +
69164 +/*
69165 + * WMI_GET_WOW_LIST_CMD reply
69166 + */
69167 +typedef PREPACK struct {
69168 +    A_UINT8     num_filters;     /* number of patterns in reply */
69169 +    A_UINT8     this_filter_num; /*  this is filter # x of total num_filters */
69170 +    A_UINT8     wow_mode;
69171 +    A_UINT8     host_mode;
69172 +    WOW_FILTER  wow_filters[1];
69173 +} POSTPACK WMI_GET_WOW_LIST_REPLY;
69174 +
69175 +typedef PREPACK struct {
69176 +    A_UINT8 filter_list_id;
69177 +    A_UINT8 filter_size;
69178 +    A_UINT8 filter_offset;
69179 +    A_UINT8 filter[1];
69180 +} POSTPACK WMI_ADD_WOW_PATTERN_CMD;
69181 +
69182 +typedef PREPACK struct {
69183 +    A_UINT16 filter_list_id;
69184 +    A_UINT16 filter_id;
69185 +} POSTPACK WMI_DEL_WOW_PATTERN_CMD;
69186 +
69187 +typedef PREPACK struct {
69188 +    A_UINT8 macaddr[ATH_MAC_LEN];
69189 +} POSTPACK WMI_SET_MAC_ADDRESS_CMD;
69190 +
69191 +/*
69192 + * WMI_SET_AKMP_PARAMS_CMD
69193 + */
69194 +
69195 +#define WMI_AKMP_MULTI_PMKID_EN   0x000001
69196 +
69197 +typedef PREPACK struct {
69198 +    A_UINT32    akmpInfo;
69199 +} POSTPACK WMI_SET_AKMP_PARAMS_CMD;
69200 +
69201 +typedef PREPACK struct {
69202 +    A_UINT8 pmkid[WMI_PMKID_LEN];
69203 +} POSTPACK WMI_PMKID;
69204 +
69205 +/*
69206 + * WMI_SET_PMKID_LIST_CMD
69207 + */
69208 +#define WMI_MAX_PMKID_CACHE   8
69209 +
69210 +typedef PREPACK struct {
69211 +    A_UINT32    numPMKID;
69212 +    WMI_PMKID   pmkidList[WMI_MAX_PMKID_CACHE];
69213 +} POSTPACK WMI_SET_PMKID_LIST_CMD;
69214 +
69215 +/*
69216 + * WMI_GET_PMKID_LIST_CMD  Reply
69217 + * Following the Number of PMKIDs is the list of PMKIDs
69218 + */
69219 +typedef PREPACK struct {
69220 +    A_UINT32    numPMKID;
69221 +    WMI_PMKID   pmkidList[1];
69222 +} POSTPACK WMI_PMKID_LIST_REPLY;
69223 +
69224 +/* index used for priority streams */
69225 +typedef enum {
69226 +    WMI_NOT_MAPPED  = -1,
69227 +    WMI_CONTROL_PRI = 0,
69228 +    WMI_BEST_EFFORT_PRI = 1,
69229 +    WMI_LOW_PRI = 2,
69230 +    WMI_HIGH_PRI = 3,
69231 +    WMI_HIGHEST_PRI,
69232 +    WMI_PRI_MAX_COUNT
69233 +} WMI_PRI_STREAM_ID;
69234 +
69235 +#ifndef ATH_TARGET
69236 +#include "athendpack.h"
69237 +#endif
69238 +
69239 +#ifdef __cplusplus
69240 +}
69241 +#endif
69242 +
69243 +#endif /* _WMI_H_ */
69244 Index: linux-2.6.28/drivers/ar6000/include/wmix.h
69245 ===================================================================
69246 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
69247 +++ linux-2.6.28/drivers/ar6000/include/wmix.h  2009-01-02 00:01:56.000000000 +0100
69248 @@ -0,0 +1,233 @@
69249 +/*
69250 + * Copyright (c) 2004-2005 Atheros Communications Inc.
69251 + * All rights reserved.
69252 + *
69253 + *
69254 + * $ATH_LICENSE_HOSTSDK0_C$
69255 + *
69256 + * This file contains extensions of the WMI protocol specified in the
69257 + * Wireless Module Interface (WMI).  It includes definitions of all
69258 + * extended commands and events.  Extensions include useful commands
69259 + * that are not directly related to wireless activities.  They may
69260 + * be hardware-specific, and they might not be supported on all
69261 + * implementations.
69262 + *
69263 + * Extended WMIX commands are encapsulated in a WMI message with
69264 + * cmd=WMI_EXTENSION_CMD.
69265 + *
69266 + */
69267 +
69268 +#ifndef _WMIX_H_
69269 +#define _WMIX_H_
69270 +
69271 +#ifdef __cplusplus
69272 +extern "C" {
69273 +#endif
69274 +
69275 +#ifndef ATH_TARGET
69276 +#include "athstartpack.h"
69277 +#endif
69278 +
69279 +#include "dbglog.h"
69280 +
69281 +/*
69282 + * Extended WMI commands are those that are needed during wireless
69283 + * operation, but which are not really wireless commands.  This allows,
69284 + * for instance, platform-specific commands.  Extended WMI commands are
69285 + * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
69286 + * Extended WMI events are similarly embedded in a WMI event message with
69287 + * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
69288 + */
69289 +typedef PREPACK struct {
69290 +    A_UINT32    commandId;
69291 +} POSTPACK WMIX_CMD_HDR;
69292 +
69293 +typedef enum {
69294 +    WMIX_DSETOPEN_REPLY_CMDID           = 0x2001,
69295 +    WMIX_DSETDATA_REPLY_CMDID,
69296 +    WMIX_GPIO_OUTPUT_SET_CMDID,
69297 +    WMIX_GPIO_INPUT_GET_CMDID,
69298 +    WMIX_GPIO_REGISTER_SET_CMDID,
69299 +    WMIX_GPIO_REGISTER_GET_CMDID,
69300 +    WMIX_GPIO_INTR_ACK_CMDID,
69301 +    WMIX_HB_CHALLENGE_RESP_CMDID,
69302 +    WMIX_DBGLOG_CFG_MODULE_CMDID,
69303 +} WMIX_COMMAND_ID;
69304 +
69305 +typedef enum {
69306 +    WMIX_DSETOPENREQ_EVENTID            = 0x3001,
69307 +    WMIX_DSETCLOSE_EVENTID,
69308 +    WMIX_DSETDATAREQ_EVENTID,
69309 +    WMIX_GPIO_INTR_EVENTID,
69310 +    WMIX_GPIO_DATA_EVENTID,
69311 +    WMIX_GPIO_ACK_EVENTID,
69312 +    WMIX_HB_CHALLENGE_RESP_EVENTID,
69313 +    WMIX_DBGLOG_EVENTID,
69314 +} WMIX_EVENT_ID;
69315 +
69316 +/*
69317 + * =============DataSet support=================
69318 + */
69319 +
69320 +/*
69321 + * WMIX_DSETOPENREQ_EVENTID
69322 + * DataSet Open Request Event
69323 + */
69324 +typedef PREPACK struct {
69325 +    A_UINT32 dset_id;
69326 +    A_UINT32 targ_dset_handle;  /* echo'ed, not used by Host, */
69327 +    A_UINT32 targ_reply_fn;     /* echo'ed, not used by Host, */
69328 +    A_UINT32 targ_reply_arg;    /* echo'ed, not used by Host, */
69329 +} POSTPACK WMIX_DSETOPENREQ_EVENT;
69330 +
69331 +/*
69332 + * WMIX_DSETCLOSE_EVENTID
69333 + * DataSet Close Event
69334 + */
69335 +typedef PREPACK struct {
69336 +    A_UINT32 access_cookie;
69337 +} POSTPACK WMIX_DSETCLOSE_EVENT;
69338 +
69339 +/*
69340 + * WMIX_DSETDATAREQ_EVENTID
69341 + * DataSet Data Request Event
69342 + */
69343 +typedef PREPACK struct {
69344 +    A_UINT32 access_cookie;
69345 +    A_UINT32 offset;
69346 +    A_UINT32 length;
69347 +    A_UINT32 targ_buf;         /* echo'ed, not used by Host, */
69348 +    A_UINT32 targ_reply_fn;    /* echo'ed, not used by Host, */
69349 +    A_UINT32 targ_reply_arg;   /* echo'ed, not used by Host, */
69350 +} POSTPACK WMIX_DSETDATAREQ_EVENT;
69351 +
69352 +typedef PREPACK struct {
69353 +    A_UINT32              status;
69354 +    A_UINT32              targ_dset_handle;
69355 +    A_UINT32              targ_reply_fn;
69356 +    A_UINT32              targ_reply_arg;
69357 +    A_UINT32              access_cookie;
69358 +    A_UINT32              size;
69359 +    A_UINT32              version;
69360 +} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
69361 +
69362 +typedef PREPACK struct {
69363 +    A_UINT32              status;
69364 +    A_UINT32              targ_buf;
69365 +    A_UINT32              targ_reply_fn;
69366 +    A_UINT32              targ_reply_arg;
69367 +    A_UINT32              length;
69368 +    A_UINT8               buf[1];
69369 +} POSTPACK WMIX_DSETDATA_REPLY_CMD;
69370 +
69371 +
69372 +/*
69373 + * =============GPIO support=================
69374 + * All masks are 18-bit masks with bit N operating on GPIO pin N.
69375 + */
69376 +
69377 +#include "gpio.h"
69378 +
69379 +/*
69380 + * Set GPIO pin output state.
69381 + * In order for output to be driven, a pin must be enabled for output.
69382 + * This can be done during initialization through the GPIO Configuration
69383 + * DataSet, or during operation with the enable_mask.
69384 + *
69385 + * If a request is made to simultaneously set/clear or set/disable or
69386 + * clear/disable or disable/enable, results are undefined.
69387 + */
69388 +typedef PREPACK struct {
69389 +    A_UINT32              set_mask;             /* pins to set */
69390 +    A_UINT32              clear_mask;           /* pins to clear */
69391 +    A_UINT32              enable_mask;          /* pins to enable for output */
69392 +    A_UINT32              disable_mask;         /* pins to disable/tristate */
69393 +} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
69394 +
69395 +/*
69396 + * Set a GPIO register.  For debug/exceptional cases.
69397 + * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
69398 + * platform-dependent header.
69399 + */
69400 +typedef PREPACK struct {
69401 +    A_UINT32              gpioreg_id;           /* GPIO register ID */
69402 +    A_UINT32              value;                /* value to write */
69403 +} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
69404 +
69405 +/* Get a GPIO register.  For debug/exceptional cases. */
69406 +typedef PREPACK struct {
69407 +    A_UINT32              gpioreg_id;           /* GPIO register to read */
69408 +} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
69409 +
69410 +/*
69411 + * Host acknowledges and re-arms GPIO interrupts.  A single
69412 + * message should be used to acknowledge all interrupts that
69413 + * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
69414 + */
69415 +typedef PREPACK struct {
69416 +    A_UINT32              ack_mask;             /* interrupts to acknowledge */
69417 +} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
69418 +
69419 +/*
69420 + * Target informs Host of GPIO interrupts that have ocurred since the
69421 + * last WMIX_GIPO_INTR_ACK_CMD was received.  Additional information --
69422 + * the current GPIO input values is provided -- in order to support
69423 + * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
69424 + */
69425 +typedef PREPACK struct {
69426 +    A_UINT32              intr_mask;            /* pending GPIO interrupts */
69427 +    A_UINT32              input_values;         /* recent GPIO input values */
69428 +} POSTPACK WMIX_GPIO_INTR_EVENT;
69429 +
69430 +/*
69431 + * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
69432 + * using a GPIO_DATA_EVENT with
69433 + *   value set to the mask of GPIO pin inputs and
69434 + *   reg_id set to GPIO_ID_NONE
69435 + *
69436 + *
69437 + * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
69438 + * using a GPIO_DATA_EVENT with
69439 + *   value set to the value of the requested register and
69440 + *   reg_id identifying the register (reflects the original request)
69441 + * NB: reg_id supports the future possibility of unsolicited
69442 + * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
69443 + * simplify Host GPIO support.
69444 + */
69445 +typedef PREPACK struct {
69446 +    A_UINT32              value;
69447 +    A_UINT32              reg_id;
69448 +} POSTPACK WMIX_GPIO_DATA_EVENT;
69449 +
69450 +/*
69451 + * =============Error Detection support=================
69452 + */
69453 +
69454 +/*
69455 + * WMIX_HB_CHALLENGE_RESP_CMDID
69456 + * Heartbeat Challenge Response command
69457 + */
69458 +typedef PREPACK struct {
69459 +    A_UINT32              cookie;
69460 +    A_UINT32              source;
69461 +} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
69462 +
69463 +/*
69464 + * WMIX_HB_CHALLENGE_RESP_EVENTID
69465 + * Heartbeat Challenge Response Event
69466 + */
69467 +#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
69468 +
69469 +typedef PREPACK struct {
69470 +    struct dbglog_config_s config;
69471 +} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
69472 +
69473 +#ifndef ATH_TARGET
69474 +#include "athendpack.h"
69475 +#endif
69476 +
69477 +#ifdef __cplusplus
69478 +}
69479 +#endif
69480 +
69481 +#endif /* _WMIX_H_ */
69482 Index: linux-2.6.28/drivers/ar6000/Kconfig
69483 ===================================================================
69484 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
69485 +++ linux-2.6.28/drivers/ar6000/Kconfig 2009-01-02 00:01:56.000000000 +0100
69486 @@ -0,0 +1,7 @@
69487 +config AR6000_WLAN
69488 +        tristate "AR6000 wireless networking over SDIO"
69489 +       depends on MMC
69490 +        select WIRELESS_EXT
69491 +        default m
69492 +        help
69493 +          good luck.
69494 Index: linux-2.6.28/drivers/ar6000/Makefile
69495 ===================================================================
69496 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
69497 +++ linux-2.6.28/drivers/ar6000/Makefile        2009-01-02 00:01:56.000000000 +0100
69498 @@ -0,0 +1,38 @@
69499 +REV ?= 2
69500 +
69501 +PWD := $(shell pwd)
69502 +
69503 +EXTRA_CFLAGS += -I$(src)/include
69504 +
69505 +EXTRA_CFLAGS += -DLINUX -D__KERNEL__ -DHTC_RAW_INTERFACE\
69506 +                -DTCMD -DUSER_KEYS \
69507 +                -DNO_SYNC_FLUSH #\
69508 +                -DMULTIPLE_FRAMES_PER_INTERRUPT -DAR6000REV$(REV) \
69509 +                -DBLOCK_TX_PATH_FLAG \
69510 +               -DSDIO \
69511 +
69512 +EXTRA_CFLAGS += -DKERNEL_2_6
69513 +
69514 +obj-$(CONFIG_AR6000_WLAN) += ar6000.o
69515 +
69516 +ar6000-objs += htc/ar6k.o                         \
69517 +              htc/ar6k_events.o           \
69518 +               htc/htc_send.o             \
69519 +               htc/htc_recv.o             \
69520 +               htc/htc_services.o          \
69521 +               htc/htc.o                  \
69522 +               hif/hif2.o                 \
69523 +               bmi/bmi.o                   \
69524 +               ar6000/ar6000_drv.o         \
69525 +               ar6000/ar6000_raw_if.o     \
69526 +               ar6000/netbuf.o            \
69527 +               ar6000/wireless_ext.o      \
69528 +               ar6000/ioctl.o             \
69529 +               miscdrv/common_drv.o       \
69530 +               miscdrv/credit_dist.o      \
69531 +               wmi/wmi.o                   \
69532 +               wlan/wlan_node.o            \
69533 +               wlan/wlan_recv_beacon.o     \
69534 +               wlan/wlan_utils.o
69535 +
69536 +
69537 Index: linux-2.6.28/drivers/ar6000/miscdrv/common_drv.c
69538 ===================================================================
69539 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
69540 +++ linux-2.6.28/drivers/ar6000/miscdrv/common_drv.c    2009-01-02 00:01:56.000000000 +0100
69541 @@ -0,0 +1,467 @@
69542 +
69543 +/*
69544 + *
69545 + * Copyright (c) 2004-2007 Atheros Communications Inc.
69546 + * All rights reserved.
69547 + *
69548 + *
69549 + *  This program is free software; you can redistribute it and/or modify
69550 + *  it under the terms of the GNU General Public License version 2 as
69551 + *  published by the Free Software Foundation;
69552 + *
69553 + *  Software distributed under the License is distributed on an "AS
69554 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
69555 + *  implied. See the License for the specific language governing
69556 + *  rights and limitations under the License.
69557 + *
69558 + *
69559 + *
69560 + */
69561 +
69562 +#include "a_config.h"
69563 +#include "athdefs.h"
69564 +#include "a_types.h"
69565 +#include "AR6Khwreg.h"
69566 +#include "targaddrs.h"
69567 +#include "a_osapi.h"
69568 +#include "hif.h"
69569 +#include "htc_api.h"
69570 +#include "bmi.h"
69571 +#include "bmi_msg.h"
69572 +#include "common_drv.h"
69573 +#include "a_debug.h"
69574 +#include "targaddrs.h"
69575 +
69576 +#define HOST_INTEREST_ITEM_ADDRESS(target, item)    \
69577 +(((TargetType) == TARGET_TYPE_AR6001) ?     \
69578 +   AR6001_HOST_INTEREST_ITEM_ADDRESS(item) :    \
69579 +   AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
69580 +
69581 +
69582 +/* Compile the 4BYTE version of the window register setup routine,
69583 + * This mitigates host interconnect issues with non-4byte aligned bus requests, some
69584 + * interconnects use bus adapters that impose strict limitations.
69585 + * Since diag window access is not intended for performance critical operations, the 4byte mode should
69586 + * be satisfactory even though it generates 4X the bus activity. */
69587 +
69588 +#ifdef USE_4BYTE_REGISTER_ACCESS
69589 +
69590 +    /* set the window address register (using 4-byte register access ). */
69591 +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
69592 +{
69593 +    A_STATUS status;
69594 +    A_UINT8 addrValue[4];
69595 +    int i;
69596 +
69597 +        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
69598 +         * last to initiate the access cycle */
69599 +
69600 +    for (i = 1; i <= 3; i++) {
69601 +            /* fill the buffer with the address byte value we want to hit 4 times*/
69602 +        addrValue[0] = ((A_UINT8 *)&Address)[i];
69603 +        addrValue[1] = addrValue[0];
69604 +        addrValue[2] = addrValue[0];
69605 +        addrValue[3] = addrValue[0];
69606 +
69607 +            /* hit each byte of the register address with a 4-byte write operation to the same address,
69608 +             * this is a harmless operation */
69609 +        status = HIFReadWrite(hifDevice,
69610 +                              RegisterAddr+i,
69611 +                              addrValue,
69612 +                              4,
69613 +                              HIF_WR_SYNC_BYTE_FIX,
69614 +                              NULL);
69615 +        if (status != A_OK) {
69616 +            break;
69617 +        }
69618 +    }
69619 +
69620 +    if (status != A_OK) {
69621 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
69622 +             RegisterAddr, Address));
69623 +        return status;
69624 +    }
69625 +
69626 +        /* write the address register again, this time write the whole 4-byte value.
69627 +         * The effect here is that the LSB write causes the cycle to start, the extra
69628 +         * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
69629 +    status = HIFReadWrite(hifDevice,
69630 +                          RegisterAddr,
69631 +                          (A_UCHAR *)(&Address),
69632 +                          4,
69633 +                          HIF_WR_SYNC_BYTE_INC,
69634 +                          NULL);
69635 +
69636 +    if (status != A_OK) {
69637 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
69638 +            RegisterAddr, Address));
69639 +        return status;
69640 +    }
69641 +
69642 +    return A_OK;
69643 +
69644 +
69645 +
69646 +}
69647 +
69648 +
69649 +#else
69650 +
69651 +    /* set the window address register */
69652 +A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
69653 +{
69654 +    A_STATUS status;
69655 +
69656 +        /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
69657 +         * last to initiate the access cycle */
69658 +    status = HIFReadWrite(hifDevice,
69659 +                          RegisterAddr+1,  /* write upper 3 bytes */
69660 +                          ((A_UCHAR *)(&Address))+1,
69661 +                          sizeof(A_UINT32)-1,
69662 +                          HIF_WR_SYNC_BYTE_INC,
69663 +                          NULL);
69664 +
69665 +    if (status != A_OK) {
69666 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
69667 +             RegisterAddr, Address));
69668 +        return status;
69669 +    }
69670 +
69671 +        /* write the LSB of the register, this initiates the operation */
69672 +    status = HIFReadWrite(hifDevice,
69673 +                          RegisterAddr,
69674 +                          (A_UCHAR *)(&Address),
69675 +                          sizeof(A_UINT8),
69676 +                          HIF_WR_SYNC_BYTE_INC,
69677 +                          NULL);
69678 +
69679 +    if (status != A_OK) {
69680 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
69681 +            RegisterAddr, Address));
69682 +        return status;
69683 +    }
69684 +
69685 +    return A_OK;
69686 +}
69687 +
69688 +#endif
69689 +
69690 +/*
69691 + * Read from the AR6000 through its diagnostic window.
69692 + * No cooperation from the Target is required for this.
69693 + */
69694 +A_STATUS
69695 +ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
69696 +{
69697 +    A_STATUS status;
69698 +
69699 +        /* set window register to start read cycle */
69700 +    status = ar6000_SetAddressWindowRegister(hifDevice,
69701 +                                             WINDOW_READ_ADDR_ADDRESS,
69702 +                                             *address);
69703 +
69704 +    if (status != A_OK) {
69705 +        return status;
69706 +    }
69707 +
69708 +        /* read the data */
69709 +    status = HIFReadWrite(hifDevice,
69710 +                          WINDOW_DATA_ADDRESS,
69711 +                          (A_UCHAR *)data,
69712 +                          sizeof(A_UINT32),
69713 +                          HIF_RD_SYNC_BYTE_INC,
69714 +                          NULL);
69715 +    if (status != A_OK) {
69716 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
69717 +        return status;
69718 +    }
69719 +
69720 +    return status;
69721 +}
69722 +
69723 +
69724 +/*
69725 + * Write to the AR6000 through its diagnostic window.
69726 + * No cooperation from the Target is required for this.
69727 + */
69728 +A_STATUS
69729 +ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
69730 +{
69731 +    A_STATUS status;
69732 +
69733 +        /* set write data */
69734 +    status = HIFReadWrite(hifDevice,
69735 +                          WINDOW_DATA_ADDRESS,
69736 +                          (A_UCHAR *)data,
69737 +                          sizeof(A_UINT32),
69738 +                          HIF_WR_SYNC_BYTE_INC,
69739 +                          NULL);
69740 +    if (status != A_OK) {
69741 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
69742 +        return status;
69743 +    }
69744 +
69745 +        /* set window register, which starts the write cycle */
69746 +    return ar6000_SetAddressWindowRegister(hifDevice,
69747 +                                           WINDOW_WRITE_ADDR_ADDRESS,
69748 +                                           *address);
69749 +}
69750 +
69751 +A_STATUS
69752 +ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
69753 +                    A_UCHAR *data, A_UINT32 length)
69754 +{
69755 +    A_UINT32 count;
69756 +    A_STATUS status = A_OK;
69757 +
69758 +    for (count = 0; count < length; count += 4, address += 4) {
69759 +        if ((status = ar6000_ReadRegDiag(hifDevice, &address,
69760 +                                         (A_UINT32 *)&data[count])) != A_OK)
69761 +        {
69762 +            break;
69763 +        }
69764 +    }
69765 +
69766 +    return status;
69767 +}
69768 +
69769 +A_STATUS
69770 +ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
69771 +                     A_UCHAR *data, A_UINT32 length)
69772 +{
69773 +    A_UINT32 count;
69774 +    A_STATUS status = A_OK;
69775 +
69776 +    for (count = 0; count < length; count += 4, address += 4) {
69777 +        if ((status = ar6000_WriteRegDiag(hifDevice, &address,
69778 +                                          (A_UINT32 *)&data[count])) != A_OK)
69779 +        {
69780 +            break;
69781 +        }
69782 +    }
69783 +
69784 +    return status;
69785 +}
69786 +
69787 +A_STATUS
69788 +ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice)
69789 +{
69790 +    int i;
69791 +    struct forceROM_s {
69792 +        A_UINT32 addr;
69793 +        A_UINT32 data;
69794 +    };
69795 +    struct forceROM_s *ForceROM;
69796 +    int szForceROM;
69797 +    A_UINT32 instruction;
69798 +
69799 +    static struct forceROM_s ForceROM_REV2[] = {
69800 +        /* NB: This works for old REV2 ROM (old). */
69801 +        {0x00001ff0, 0x175b0027}, /* jump instruction at 0xa0001ff0 */
69802 +        {0x00001ff4, 0x00000000}, /* nop instruction at 0xa0001ff4 */
69803 +
69804 +        {MC_REMAP_TARGET_ADDRESS, 0x00001ff0}, /* remap to 0xa0001ff0 */
69805 +        {MC_REMAP_COMPARE_ADDRESS, 0x01000040},/* ...from 0xbfc00040 */
69806 +        {MC_REMAP_SIZE_ADDRESS, 0x00000000},   /* ...1 cache line */
69807 +        {MC_REMAP_VALID_ADDRESS, 0x00000001},  /* ...remap is valid */
69808 +
69809 +        {LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
69810 +
69811 +        {RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
69812 +    };
69813 +
69814 +    static struct forceROM_s ForceROM_NEW[] = {
69815 +        /* NB: This works for AR6000 ROM REV3 and beyond.  */
69816 +        {LOCAL_SCRATCH_ADDRESS, AR6K_OPTION_IGNORE_FLASH},
69817 +        {LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
69818 +        {RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
69819 +    };
69820 +
69821 +    /*
69822 +     * Examine a semi-arbitrary instruction that's different
69823 +     * in REV2 and other revisions.
69824 +     * NB: If a Host port does not require simultaneous support
69825 +     * for multiple revisions of Target ROM, this code can be elided.
69826 +     */
69827 +    (void)ar6000_ReadDataDiag(hifDevice, 0x01000040,
69828 +                              (A_UCHAR *)&instruction, 4);
69829 +
69830 +    AR_DEBUG_PRINTF(ATH_LOG_ERR, ("instruction=0x%x\n", instruction));
69831 +
69832 +    if (instruction == 0x3c1aa200) {
69833 +        /* It's an old ROM */
69834 +        ForceROM = ForceROM_REV2;
69835 +        szForceROM = sizeof(ForceROM_REV2)/sizeof(*ForceROM);
69836 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using OLD method\n"));
69837 +    } else {
69838 +        ForceROM = ForceROM_NEW;
69839 +        szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
69840 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using NEW method\n"));
69841 +    }
69842 +
69843 +    AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Force Target to execute from ROM....\n"));
69844 +    for (i = 0; i < szForceROM; i++)
69845 +    {
69846 +        if (ar6000_WriteRegDiag(hifDevice,
69847 +                                &ForceROM[i].addr,
69848 +                                &ForceROM[i].data) != A_OK)
69849 +        {
69850 +            AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
69851 +            return A_ERROR;
69852 +        }
69853 +    }
69854 +
69855 +    A_MDELAY(50); /* delay to allow dragon to come to BMI phase  */
69856 +    return A_OK;
69857 +}
69858 +
69859 +/* reset device */
69860 +A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
69861 +{
69862 +
69863 +#if !defined(DWSIM)
69864 +    A_STATUS status = A_OK;
69865 +    A_UINT32 address;
69866 +    A_UINT32 data;
69867 +
69868 +    do {
69869 +
69870 +        // address = RESET_CONTROL_ADDRESS;
69871 +        data = RESET_CONTROL_COLD_RST_MASK;
69872 +
69873 +          /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
69874 +        if (TargetType == TARGET_TYPE_AR6001) {
69875 +            address = 0x0C000000;
69876 +        } else {
69877 +            if (TargetType == TARGET_TYPE_AR6002) {
69878 +                address = 0x00004000;
69879 +            } else {
69880 +                A_ASSERT(0);
69881 +            }
69882 +        }
69883 +
69884 +        status = ar6000_WriteRegDiag(hifDevice, &address, &data);
69885 +
69886 +        if (A_FAILED(status)) {
69887 +            break;
69888 +        }
69889 +
69890 +        /*
69891 +         * Read back the RESET CAUSE register to ensure that the cold reset
69892 +         * went through.
69893 +         */
69894 +        A_MDELAY(2000); /* 2 second delay to allow things to settle down */
69895 +
69896 +
69897 +        // address = RESET_CAUSE_ADDRESS;
69898 +        /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
69899 +        if (TargetType == TARGET_TYPE_AR6001) {
69900 +            address = 0x0C0000CC;
69901 +        } else {
69902 +            if (TargetType == TARGET_TYPE_AR6002) {
69903 +                address = 0x000040C0;
69904 +            } else {
69905 +                A_ASSERT(0);
69906 +            }
69907 +        }
69908 +
69909 +        data = 0;
69910 +        status = ar6000_ReadRegDiag(hifDevice, &address, &data);
69911 +
69912 +        if (A_FAILED(status)) {
69913 +            break;
69914 +        }
69915 +
69916 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
69917 +        data &= RESET_CAUSE_LAST_MASK;
69918 +        if (data != 2) {
69919 +            AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
69920 +        }
69921 +
69922 +    } while (FALSE);
69923 +
69924 +    if (A_FAILED(status)) {
69925 +        AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
69926 +    }
69927 +#endif
69928 +    return A_OK;
69929 +}
69930 +
69931 +#define REG_DUMP_COUNT_AR6001   38  /* WORDs, derived from AR6001_regdump.h */
69932 +#define REG_DUMP_COUNT_AR6002   32  /* WORDs, derived from AR6002_regdump.h */
69933 +
69934 +
69935 +#if REG_DUMP_COUNT_AR6001 <= REG_DUMP_COUNT_AR6002
69936 +#define REGISTER_DUMP_LEN_MAX  REG_DUMP_COUNT_AR6002
69937 +#else
69938 +#define REGISTER_DUMP_LEN_MAX  REG_DUMP_COUNT_AR6001
69939 +#endif
69940 +
69941 +void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
69942 +{
69943 +    A_UINT32 address;
69944 +    A_UINT32 regDumpArea = 0;
69945 +    A_STATUS status;
69946 +    A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
69947 +    A_UINT32 regDumpCount = 0;
69948 +    A_UINT32 i;
69949 +
69950 +    do {
69951 +
69952 +            /* the reg dump pointer is copied to the host interest area */
69953 +        address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
69954 +
69955 +        if (TargetType == TARGET_TYPE_AR6001) {
69956 +                /* for AR6001, this is a fixed location because the ptr is actually stuck in cache,
69957 +                 * this may be fixed in later firmware versions */
69958 +            address = 0x18a0;
69959 +            regDumpCount = REG_DUMP_COUNT_AR6001;
69960 +
69961 +        } else  if (TargetType == TARGET_TYPE_AR6002) {
69962 +
69963 +            regDumpCount = REG_DUMP_COUNT_AR6002;
69964 +
69965 +        } else {
69966 +            A_ASSERT(0);
69967 +        }
69968 +
69969 +            /* read RAM location through diagnostic window */
69970 +        status = ar6000_ReadRegDiag(hifDevice, &address, &regDumpArea);
69971 +
69972 +        if (A_FAILED(status)) {
69973 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
69974 +            break;
69975 +        }
69976 +
69977 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
69978 +
69979 +        if (regDumpArea == 0) {
69980 +                /* no reg dump */
69981 +            break;
69982 +        }
69983 +
69984 +        if (TargetType == TARGET_TYPE_AR6001) {
69985 +            regDumpArea &= 0x0FFFFFFF;  /* convert to physical address in target memory */
69986 +        }
69987 +
69988 +            /* fetch register dump data */
69989 +        status = ar6000_ReadDataDiag(hifDevice,
69990 +                                     regDumpArea,
69991 +                                     (A_UCHAR *)&regDumpValues[0],
69992 +                                     regDumpCount * (sizeof(A_UINT32)));
69993 +
69994 +        if (A_FAILED(status)) {
69995 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
69996 +            break;
69997 +        }
69998 +
69999 +        AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
70000 +
70001 +        for (i = 0; i < regDumpCount; i++) {
70002 +            AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d :  0x%8.8X \n",i, regDumpValues[i]));
70003 +        }
70004 +
70005 +    } while (FALSE);
70006 +
70007 +}
70008 +
70009 Index: linux-2.6.28/drivers/ar6000/miscdrv/credit_dist.c
70010 ===================================================================
70011 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
70012 +++ linux-2.6.28/drivers/ar6000/miscdrv/credit_dist.c   2009-01-02 00:01:56.000000000 +0100
70013 @@ -0,0 +1,346 @@
70014 +
70015 +/*
70016 + *
70017 + * Copyright (c) 2004-2007 Atheros Communications Inc.
70018 + * All rights reserved.
70019 + *
70020 + *
70021 + *  This program is free software; you can redistribute it and/or modify
70022 + *  it under the terms of the GNU General Public License version 2 as
70023 + *  published by the Free Software Foundation;
70024 + *
70025 + *  Software distributed under the License is distributed on an "AS
70026 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
70027 + *  implied. See the License for the specific language governing
70028 + *  rights and limitations under the License.
70029 + *
70030 + *
70031 + *
70032 + */
70033 +
70034 +#include "a_config.h"
70035 +#include "athdefs.h"
70036 +#include "a_types.h"
70037 +#include "a_osapi.h"
70038 +#include "a_debug.h"
70039 +#include "htc_api.h"
70040 +#include "common_drv.h"
70041 +
70042 +/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/
70043 +
70044 +#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */
70045 +
70046 +#ifdef NO_VO_SERVICE
70047 +#define DATA_SVCS_USED 3
70048 +#else
70049 +#define DATA_SVCS_USED 4
70050 +#endif
70051 +
70052 +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
70053 +                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
70054 +
70055 +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
70056 +                        HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
70057 +
70058 +/* reduce an ep's credits back to a set limit */
70059 +static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
70060 +                                HTC_ENDPOINT_CREDIT_DIST  *pEpDist,
70061 +                                int                       Limit)
70062 +{
70063 +    int credits;
70064 +
70065 +        /* set the new limit */
70066 +    pEpDist->TxCreditsAssigned = Limit;
70067 +
70068 +    if (pEpDist->TxCredits <= Limit) {
70069 +        return;
70070 +    }
70071 +
70072 +        /* figure out how much to take away */
70073 +    credits = pEpDist->TxCredits - Limit;
70074 +        /* take them away */
70075 +    pEpDist->TxCredits -= credits;
70076 +    pCredInfo->CurrentFreeCredits += credits;
70077 +}
70078 +
70079 +/* give an endpoint some credits from the free credit pool */
70080 +#define GiveCredits(pCredInfo,pEpDist,credits)      \
70081 +{                                                   \
70082 +    (pEpDist)->TxCredits += (credits);              \
70083 +    (pEpDist)->TxCreditsAssigned += (credits);      \
70084 +    (pCredInfo)->CurrentFreeCredits -= (credits);   \
70085 +}
70086 +
70087 +
70088 +/* default credit init callback.
70089 + * This function is called in the context of HTCStart() to setup initial (application-specific)
70090 + * credit distributions */
70091 +static void ar6000_credit_init(void                     *Context,
70092 +                               HTC_ENDPOINT_CREDIT_DIST *pEPList,
70093 +                               int                      TotalCredits)
70094 +{
70095 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
70096 +    int                      count;
70097 +    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
70098 +
70099 +    pCredInfo->CurrentFreeCredits = TotalCredits;
70100 +    pCredInfo->TotalAvailableCredits = TotalCredits;
70101 +
70102 +    pCurEpDist = pEPList;
70103 +
70104 +        /* run through the list and initialize */
70105 +    while (pCurEpDist != NULL) {
70106 +
70107 +            /* set minimums for each endpoint */
70108 +        pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
70109 +
70110 +        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
70111 +                /* give control service some credits */
70112 +            GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
70113 +                /* control service is always marked active, it never goes inactive EVER */
70114 +            SET_EP_ACTIVE(pCurEpDist);
70115 +        } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) {
70116 +                /* this is the lowest priority data endpoint, save this off for easy access */
70117 +            pCredInfo->pLowestPriEpDist = pCurEpDist;
70118 +        }
70119 +
70120 +        /* Streams have to be created (explicit | implicit)for all kinds
70121 +         * of traffic. BE endpoints are also inactive in the beginning.
70122 +         * When BE traffic starts it creates implicit streams that
70123 +         * redistributes credits.
70124 +         */
70125 +
70126 +        /* note, all other endpoints have minimums set but are initially given NO credits.
70127 +         * Credits will be distributed as traffic activity demands */
70128 +        pCurEpDist = pCurEpDist->pNext;
70129 +    }
70130 +
70131 +    if (pCredInfo->CurrentFreeCredits <= 0) {
70132 +        AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits));
70133 +        A_ASSERT(FALSE);
70134 +        return;
70135 +    }
70136 +
70137 +        /* reset list */
70138 +    pCurEpDist = pEPList;
70139 +        /* now run through the list and set max operating credit limits for everyone */
70140 +    while (pCurEpDist != NULL) {
70141 +        if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
70142 +                /* control service max is just 1 max message */
70143 +            pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg;
70144 +        } else {
70145 +                /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are
70146 +                 * the same.
70147 +                 * We use a simple calculation here, we take the remaining credits and
70148 +                 * determine how many max messages this can cover and then set each endpoint's
70149 +                 * normal value equal to half this amount.
70150 +                 * */
70151 +            count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg;
70152 +            count = count >> 1;
70153 +            count = max(count,pCurEpDist->TxCreditsPerMaxMsg);
70154 +                /* set normal */
70155 +            pCurEpDist->TxCreditsNorm = count;
70156 +
70157 +        }
70158 +        pCurEpDist = pCurEpDist->pNext;
70159 +    }
70160 +
70161 +}
70162 +
70163 +
70164 +/* default credit distribution callback
70165 + * This callback is invoked whenever endpoints require credit distributions.
70166 + * A lock is held while this function is invoked, this function shall NOT block.
70167 + * The pEPDistList is a list of distribution structures in prioritized order as
70168 + * defined by the call to the HTCSetCreditDistribution() api.
70169 + *
70170 + */
70171 +static void ar6000_credit_distribute(void                     *Context,
70172 +                                     HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
70173 +                                     HTC_CREDIT_DIST_REASON   Reason)
70174 +{
70175 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
70176 +    COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
70177 +
70178 +    switch (Reason) {
70179 +        case HTC_CREDIT_DIST_SEND_COMPLETE :
70180 +            pCurEpDist = pEPDistList;
70181 +                /* we are given the start of the endpoint distribution list.
70182 +                 * There may be one or more endpoints to service.
70183 +                 * Run through the list and distribute credits */
70184 +            while (pCurEpDist != NULL) {
70185 +
70186 +                if (pCurEpDist->TxCreditsToDist > 0) {
70187 +                        /* return the credits back to the endpoint */
70188 +                    pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
70189 +                        /* always zero out when we are done */
70190 +                    pCurEpDist->TxCreditsToDist = 0;
70191 +
70192 +                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) {
70193 +                            /* reduce to the assigned limit, previous credit reductions
70194 +                             * could have caused the limit to change */
70195 +                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned);
70196 +                    }
70197 +
70198 +                    if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) {
70199 +                            /* oversubscribed endpoints need to reduce back to normal */
70200 +                        ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm);
70201 +                    }
70202 +                }
70203 +
70204 +                pCurEpDist = pCurEpDist->pNext;
70205 +            }
70206 +
70207 +            A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
70208 +
70209 +            break;
70210 +
70211 +        case HTC_CREDIT_DIST_ACTIVITY_CHANGE :
70212 +            RedistributeCredits(pCredInfo,pEPDistList);
70213 +            break;
70214 +        case HTC_CREDIT_DIST_SEEK_CREDITS :
70215 +            SeekCredits(pCredInfo,pEPDistList);
70216 +            break;
70217 +        case HTC_DUMP_CREDIT_STATE :
70218 +            AR_DEBUG_PRINTF(ATH_LOG_INF, ("Credit Distribution, total : %d, free : %d\n",
70219 +                                                                       pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits));
70220 +            break;
70221 +        default:
70222 +            break;
70223 +
70224 +    }
70225 +
70226 +}
70227 +
70228 +/* redistribute credits based on activity change */
70229 +static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
70230 +                                HTC_ENDPOINT_CREDIT_DIST *pEPDistList)
70231 +{
70232 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList;
70233 +
70234 +        /* walk through the list and remove credits from inactive endpoints */
70235 +    while (pCurEpDist != NULL) {
70236 +
70237 +        if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) {
70238 +            if (!IS_EP_ACTIVE(pCurEpDist)) {
70239 +                    /* EP is inactive, reduce credits back to zero */
70240 +                ReduceCredits(pCredInfo, pCurEpDist, 0);
70241 +            }
70242 +        }
70243 +
70244 +        /* NOTE in the active case, we do not need to do anything further,
70245 +         * when an EP goes active and needs credits, HTC will call into
70246 +         * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS  */
70247 +
70248 +        pCurEpDist = pCurEpDist->pNext;
70249 +    }
70250 +
70251 +    A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
70252 +
70253 +}
70254 +
70255 +/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */
70256 +static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
70257 +                        HTC_ENDPOINT_CREDIT_DIST *pEPDist)
70258 +{
70259 +    HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
70260 +    int                      credits = 0;
70261 +    int                      need;
70262 +
70263 +    do {
70264 +
70265 +        if (pEPDist->ServiceID == WMI_CONTROL_SVC) {
70266 +                /* we never oversubscribe on the control service, this is not
70267 +                 * a high performance path and the target never holds onto control
70268 +                 * credits for too long */
70269 +            break;
70270 +        }
70271 +
70272 +        /* for all other services, we follow a simple algorithm of
70273 +         * 1. checking the free pool for credits
70274 +         * 2. checking lower priority endpoints for credits to take */
70275 +
70276 +        if (pCredInfo->CurrentFreeCredits >= 2 * pEPDist->TxCreditsSeek) {
70277 +                /* try to give more credits than it needs */
70278 +            credits = 2 * pEPDist->TxCreditsSeek;
70279 +        } else {
70280 +                /* give what we can */
70281 +            credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
70282 +        }
70283 +
70284 +        if (credits >= pEPDist->TxCreditsSeek) {
70285 +                /* we found some to fullfill the seek request */
70286 +            break;
70287 +        }
70288 +
70289 +        /* we don't have enough in the free pool, try taking away from lower priority services
70290 +         *
70291 +         * The rule for taking away credits:
70292 +         *   1. Only take from lower priority endpoints
70293 +         *   2. Only take what is allocated above the minimum (never starve an endpoint completely)
70294 +         *   3. Only take what you need.
70295 +         *
70296 +         * */
70297 +
70298 +            /* starting at the lowest priority */
70299 +        pCurEpDist = pCredInfo->pLowestPriEpDist;
70300 +
70301 +            /* work backwards until we hit the endpoint again */
70302 +        while (pCurEpDist != pEPDist) {
70303 +                /* calculate how many we need so far */
70304 +            need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits;
70305 +
70306 +            if ((pCurEpDist->TxCreditsAssigned - need) > pCurEpDist->TxCreditsMin) {
70307 +                    /* the current one has been allocated more than it's minimum and it
70308 +                     * has enough credits assigned above it's minimum to fullfill our need
70309 +                     * try to take away just enough to fullfill our need */
70310 +                ReduceCredits(pCredInfo,
70311 +                              pCurEpDist,
70312 +                              pCurEpDist->TxCreditsAssigned - need);
70313 +
70314 +                if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) {
70315 +                        /* we have enough */
70316 +                    break;
70317 +                }
70318 +            }
70319 +
70320 +            pCurEpDist = pCurEpDist->pPrev;
70321 +        }
70322 +
70323 +            /* return what we can get */
70324 +        credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
70325 +
70326 +    } while (FALSE);
70327 +
70328 +        /* did we find some credits? */
70329 +    if (credits) {
70330 +            /* give what we can */
70331 +        GiveCredits(pCredInfo, pEPDist, credits);
70332 +    }
70333 +
70334 +}
70335 +
70336 +/* initialize and setup credit distribution */
70337 +A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo)
70338 +{
70339 +    HTC_SERVICE_ID servicepriority[5];
70340 +
70341 +    A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO));
70342 +
70343 +    servicepriority[0] = WMI_CONTROL_SVC;  /* highest */
70344 +    servicepriority[1] = WMI_DATA_VO_SVC;
70345 +    servicepriority[2] = WMI_DATA_VI_SVC;
70346 +    servicepriority[3] = WMI_DATA_BE_SVC;
70347 +    servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */
70348 +
70349 +        /* set callbacks and priority list */
70350 +    HTCSetCreditDistribution(HTCHandle,
70351 +                             pCredInfo,
70352 +                             ar6000_credit_distribute,
70353 +                             ar6000_credit_init,
70354 +                             servicepriority,
70355 +                             5);
70356 +
70357 +    return A_OK;
70358 +}
70359 +
70360 Index: linux-2.6.28/drivers/ar6000/wlan/wlan_node.c
70361 ===================================================================
70362 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
70363 +++ linux-2.6.28/drivers/ar6000/wlan/wlan_node.c        2009-01-02 00:01:56.000000000 +0100
70364 @@ -0,0 +1,371 @@
70365 +/*-
70366 + * Copyright (c) 2001 Atsushi Onoe
70367 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
70368 + * Copyright (c) 2004-2005 Atheros Communications
70369 + * All rights reserved.
70370 + *
70371 + * Redistribution and use in source and binary forms, with or without
70372 + * modification, are permitted provided that the following conditions
70373 + * are met:
70374 + * 1. Redistributions of source code must retain the above copyright
70375 + *    notice, this list of conditions and the following disclaimer.
70376 + * 2. Redistributions in binary form must reproduce the above copyright
70377 + *    notice, this list of conditions and the following disclaimer in the
70378 + *    documentation and/or other materials provided with the distribution.
70379 + * 3. The name of the author may not be used to endorse or promote products
70380 + *    derived from this software without specific prior written permission.
70381 + *
70382 + * Alternatively, this software may be distributed under the terms of the
70383 + * GNU General Public License ("GPL") version 2 as published by the Free
70384 + * Software Foundation.
70385 + *
70386 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
70387 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
70388 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
70389 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
70390 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
70391 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
70392 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
70393 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
70394 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
70395 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70396 + *
70397 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wlan/src/wlan_node.c#1 $
70398 + */
70399 +/*
70400 + * IEEE 802.11 node handling support.
70401 + */
70402 +#include <a_config.h>
70403 +#include <athdefs.h>
70404 +#include <a_types.h>
70405 +#include <a_osapi.h>
70406 +#include <a_debug.h>
70407 +#include <ieee80211.h>
70408 +#include <wlan_api.h>
70409 +#include <ieee80211_node.h>
70410 +#include <htc_api.h>
70411 +#include <wmi.h>
70412 +#include <wmi_api.h>
70413 +
70414 +static void wlan_node_timeout(A_ATH_TIMER arg);
70415 +static bss_t * _ieee80211_find_node(struct ieee80211_node_table *nt,
70416 +                                    const A_UINT8 *macaddr);
70417 +
70418 +bss_t *
70419 +wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
70420 +{
70421 +    bss_t *ni;
70422 +
70423 +    ni = A_MALLOC_NOWAIT(sizeof(bss_t));
70424 +
70425 +    if (ni != NULL) {
70426 +        ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
70427 +        if (ni->ni_buf == NULL) {
70428 +            A_FREE(ni);
70429 +            ni = NULL;
70430 +            return ni;
70431 +        }
70432 +    } else {
70433 +        return ni;
70434 +    }
70435 +
70436 +    /* Make sure our lists are clean */
70437 +    ni->ni_list_next = NULL;
70438 +    ni->ni_list_prev = NULL;
70439 +    ni->ni_hash_next = NULL;
70440 +    ni->ni_hash_prev = NULL;
70441 +
70442 +    //
70443 +    // ni_scangen never initialized before and during suspend/resume of winmobile, customer (LG/SEMCO) identified
70444 +    // that some junk has been stored in this, due to this scan list didn't properly updated
70445 +    //
70446 +    ni->ni_scangen      = 0;
70447 +
70448 +    return ni;
70449 +}
70450 +
70451 +void
70452 +wlan_node_free(bss_t *ni)
70453 +{
70454 +    if (ni->ni_buf != NULL) {
70455 +        A_FREE(ni->ni_buf);
70456 +    }
70457 +    A_FREE(ni);
70458 +}
70459 +
70460 +void
70461 +wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
70462 +                const A_UINT8 *macaddr)
70463 +{
70464 +    int hash;
70465 +
70466 +    A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
70467 +    hash = IEEE80211_NODE_HASH(macaddr);
70468 +    ieee80211_node_initref(ni);     /* mark referenced */
70469 +
70470 +    ni->ni_tstamp = A_GET_MS(WLAN_NODE_INACT_TIMEOUT_MSEC);
70471 +    IEEE80211_NODE_LOCK_BH(nt);
70472 +
70473 +    /* Insert at the end of the node list */
70474 +    ni->ni_list_next = NULL;
70475 +    ni->ni_list_prev = nt->nt_node_last;
70476 +    if(nt->nt_node_last != NULL)
70477 +    {
70478 +        nt->nt_node_last->ni_list_next = ni;
70479 +    }
70480 +    nt->nt_node_last = ni;
70481 +    if(nt->nt_node_first == NULL)
70482 +    {
70483 +        nt->nt_node_first = ni;
70484 +    }
70485 +
70486 +    /* Insert into the hash list i.e. the bucket */
70487 +    if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL)
70488 +    {
70489 +        nt->nt_hash[hash]->ni_hash_prev = ni;
70490 +    }
70491 +    ni->ni_hash_prev = NULL;
70492 +    nt->nt_hash[hash] = ni;
70493 +
70494 +    if (!nt->isTimerArmed) {
70495 +        A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
70496 +        nt->isTimerArmed = TRUE;
70497 +    }
70498 +
70499 +    IEEE80211_NODE_UNLOCK_BH(nt);
70500 +}
70501 +
70502 +static bss_t *
70503 +_ieee80211_find_node(struct ieee80211_node_table *nt,
70504 +    const A_UINT8 *macaddr)
70505 +{
70506 +    bss_t *ni;
70507 +    int hash;
70508 +
70509 +    IEEE80211_NODE_LOCK_ASSERT(nt);
70510 +
70511 +    hash = IEEE80211_NODE_HASH(macaddr);
70512 +    for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
70513 +        if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
70514 +            ieee80211_node_incref(ni);  /* mark referenced */
70515 +            return ni;
70516 +        }
70517 +    }
70518 +    return NULL;
70519 +}
70520 +
70521 +bss_t *
70522 +wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr)
70523 +{
70524 +    bss_t *ni;
70525 +
70526 +    IEEE80211_NODE_LOCK(nt);
70527 +    ni = _ieee80211_find_node(nt, macaddr);
70528 +    IEEE80211_NODE_UNLOCK(nt);
70529 +    return ni;
70530 +}
70531 +
70532 +/*
70533 + * Reclaim a node.  If this is the last reference count then
70534 + * do the normal free work.  Otherwise remove it from the node
70535 + * table and mark it gone by clearing the back-reference.
70536 + */
70537 +void
70538 +wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni)
70539 +{
70540 +    IEEE80211_NODE_LOCK(nt);
70541 +
70542 +    if(ni->ni_list_prev == NULL)
70543 +    {
70544 +        /* First in list so fix the list head */
70545 +        nt->nt_node_first = ni->ni_list_next;
70546 +    }
70547 +    else
70548 +    {
70549 +        ni->ni_list_prev->ni_list_next = ni->ni_list_next;
70550 +    }
70551 +
70552 +    if(ni->ni_list_next == NULL)
70553 +    {
70554 +        /* Last in list so fix list tail */
70555 +        nt->nt_node_last = ni->ni_list_prev;
70556 +    }
70557 +    else
70558 +    {
70559 +        ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
70560 +    }
70561 +
70562 +    if(ni->ni_hash_prev == NULL)
70563 +    {
70564 +        /* First in list so fix the list head */
70565 +        int hash;
70566 +        hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
70567 +        nt->nt_hash[hash] = ni->ni_hash_next;
70568 +    }
70569 +    else
70570 +    {
70571 +        ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
70572 +    }
70573 +
70574 +    if(ni->ni_hash_next != NULL)
70575 +    {
70576 +        ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
70577 +    }
70578 +    wlan_node_free(ni);
70579 +
70580 +    IEEE80211_NODE_UNLOCK(nt);
70581 +}
70582 +
70583 +static void
70584 +wlan_node_dec_free(bss_t *ni)
70585 +{
70586 +    if (ieee80211_node_dectestref(ni)) {
70587 +        wlan_node_free(ni);
70588 +    }
70589 +}
70590 +
70591 +void
70592 +wlan_free_allnodes(struct ieee80211_node_table *nt)
70593 +{
70594 +    bss_t *ni;
70595 +
70596 +    while ((ni = nt->nt_node_first) != NULL) {
70597 +        wlan_node_reclaim(nt, ni);
70598 +    }
70599 +}
70600 +
70601 +void
70602 +wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
70603 +                   void *arg)
70604 +{
70605 +    bss_t *ni;
70606 +    A_UINT32 gen;
70607 +
70608 +    gen = ++nt->nt_scangen;
70609 +
70610 +    IEEE80211_NODE_LOCK(nt);
70611 +    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
70612 +        if (ni->ni_scangen != gen) {
70613 +            ni->ni_scangen = gen;
70614 +            (void) ieee80211_node_incref(ni);
70615 +            (*f)(arg, ni);
70616 +            wlan_node_dec_free(ni);
70617 +        }
70618 +    }
70619 +    IEEE80211_NODE_UNLOCK(nt);
70620 +}
70621 +
70622 +/*
70623 + * Node table support.
70624 + */
70625 +void
70626 +wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
70627 +{
70628 +    int i;
70629 +
70630 +    AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt));
70631 +    IEEE80211_NODE_LOCK_INIT(nt);
70632 +
70633 +    nt->nt_node_first = nt->nt_node_last = NULL;
70634 +    for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++)
70635 +    {
70636 +        nt->nt_hash[i] = NULL;
70637 +    }
70638 +    A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
70639 +    nt->isTimerArmed = FALSE;
70640 +    nt->nt_wmip = wmip;
70641 +}
70642 +
70643 +static void
70644 +wlan_node_timeout(A_ATH_TIMER arg)
70645 +{
70646 +    struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
70647 +    bss_t *bss, *nextBss;
70648 +    A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE;
70649 +
70650 +    wmi_get_current_bssid(nt->nt_wmip, myBssid);
70651 +
70652 +    bss = nt->nt_node_first;
70653 +    while (bss != NULL)
70654 +    {
70655 +        nextBss = bss->ni_list_next;
70656 +        if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
70657 +        {
70658 +
70659 +            if (bss->ni_tstamp <= A_GET_MS(0))
70660 +            {
70661 +               /*
70662 +                * free up all but the current bss - if set
70663 +                */
70664 +                wlan_node_reclaim(nt, bss);
70665 +            }
70666 +            else
70667 +            {
70668 +                /*
70669 +                 * Re-arm timer, only when we have a bss other than
70670 +                 * current bss AND it is not aged-out.
70671 +                 */
70672 +                reArmTimer = TRUE;
70673 +            }
70674 +        }
70675 +        bss = nextBss;
70676 +    }
70677 +
70678 +    if(reArmTimer)
70679 +        A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
70680 +
70681 +    nt->isTimerArmed = reArmTimer;
70682 +}
70683 +
70684 +void
70685 +wlan_node_table_cleanup(struct ieee80211_node_table *nt)
70686 +{
70687 +    A_UNTIMEOUT(&nt->nt_inact_timer);
70688 +    A_DELETE_TIMER(&nt->nt_inact_timer);
70689 +    wlan_free_allnodes(nt);
70690 +    IEEE80211_NODE_LOCK_DESTROY(nt);
70691 +}
70692 +
70693 +bss_t *
70694 +wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
70695 +                                       A_UINT32 ssidLength, A_BOOL bIsWPA2)
70696 +{
70697 +    bss_t   *ni = NULL;
70698 +       A_UCHAR *pIESsid = NULL;
70699 +
70700 +    IEEE80211_NODE_LOCK (nt);
70701 +
70702 +    for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
70703 +               pIESsid = ni->ni_cie.ie_ssid;
70704 +               if (pIESsid[1] <= 32) {
70705 +
70706 +                       // Step 1 : Check SSID
70707 +                       if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
70708 +
70709 +                               // Step 2 : if SSID matches, check WPA or WPA2
70710 +                               if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) {
70711 +                                       ieee80211_node_incref (ni);  /* mark referenced */
70712 +                                       IEEE80211_NODE_UNLOCK (nt);
70713 +                                       return ni;
70714 +                               }
70715 +                               if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) {
70716 +                                       ieee80211_node_incref(ni);  /* mark referenced */
70717 +                                       IEEE80211_NODE_UNLOCK (nt);
70718 +                                       return ni;
70719 +                               }
70720 +                       }
70721 +               }
70722 +    }
70723 +
70724 +    IEEE80211_NODE_UNLOCK (nt);
70725 +
70726 +    return NULL;
70727 +}
70728 +
70729 +void
70730 +wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni)
70731 +{
70732 +       IEEE80211_NODE_LOCK (nt);
70733 +       wlan_node_dec_free (ni);
70734 +       IEEE80211_NODE_UNLOCK (nt);
70735 +}
70736 Index: linux-2.6.28/drivers/ar6000/wlan/wlan_recv_beacon.c
70737 ===================================================================
70738 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
70739 +++ linux-2.6.28/drivers/ar6000/wlan/wlan_recv_beacon.c 2009-01-02 00:01:56.000000000 +0100
70740 @@ -0,0 +1,192 @@
70741 +/*-
70742 + * Copyright (c) 2001 Atsushi Onoe
70743 + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
70744 + * All rights reserved.
70745 + *
70746 + * Redistribution and use in source and binary forms, with or without
70747 + * modification, are permitted provided that the following conditions
70748 + * are met:
70749 + * 1. Redistributions of source code must retain the above copyright
70750 + *    notice, this list of conditions and the following disclaimer.
70751 + * 2. Redistributions in binary form must reproduce the above copyright
70752 + *    notice, this list of conditions and the following disclaimer in the
70753 + *    documentation and/or other materials provided with the distribution.
70754 + * 3. The name of the author may not be used to endorse or promote products
70755 + *    derived from this software without specific prior written permission.
70756 + *
70757 + * Alternatively, this software may be distributed under the terms of the
70758 + * GNU General Public License ("GPL") version 2 as published by the Free
70759 + * Software Foundation.
70760 + *
70761 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
70762 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
70763 + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
70764 + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
70765 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
70766 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
70767 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
70768 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
70769 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
70770 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70771 + */
70772 +/*
70773 + * IEEE 802.11 input handling.
70774 + */
70775 +
70776 +#include "a_config.h"
70777 +#include "athdefs.h"
70778 +#include "a_types.h"
70779 +#include "a_osapi.h"
70780 +#include <wmi.h>
70781 +#include <ieee80211.h>
70782 +#include <wlan_api.h>
70783 +
70784 +#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do {         \
70785 +    if ((_len) < (_minlen)) {                   \
70786 +        return A_EINVAL;                         \
70787 +    }                               \
70788 +} while (0)
70789 +
70790 +#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do {         \
70791 +    if ((__elem) == NULL) {                     \
70792 +        return A_EINVAL;                         \
70793 +    }                               \
70794 +    if ((__elem)[1] > (__maxlen)) {                 \
70795 +        return A_EINVAL;                         \
70796 +    }                               \
70797 +} while (0)
70798 +
70799 +
70800 +/* unaligned little endian access */
70801 +#define LE_READ_2(p)                            \
70802 +    ((A_UINT16)                            \
70803 +     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8)))
70804 +
70805 +#define LE_READ_4(p)                            \
70806 +    ((A_UINT32)                            \
70807 +     ((((A_UINT8 *)(p))[0]      ) | (((A_UINT8 *)(p))[1] <<  8) | \
70808 +      (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
70809 +
70810 +
70811 +static int __inline
70812 +iswpaoui(const A_UINT8 *frm)
70813 +{
70814 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI);
70815 +}
70816 +
70817 +static int __inline
70818 +iswmmoui(const A_UINT8 *frm)
70819 +{
70820 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
70821 +}
70822 +
70823 +static int __inline
70824 +iswmmparam(const A_UINT8 *frm)
70825 +{
70826 +    return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
70827 +}
70828 +
70829 +static int __inline
70830 +iswmminfo(const A_UINT8 *frm)
70831 +{
70832 +    return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
70833 +}
70834 +
70835 +static int __inline
70836 +isatherosoui(const A_UINT8 *frm)
70837 +{
70838 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI);
70839 +}
70840 +
70841 +static int __inline
70842 +iswscoui(const A_UINT8 *frm)
70843 +{
70844 +    return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI);
70845 +}
70846 +
70847 +A_STATUS
70848 +wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie)
70849 +{
70850 +    A_UINT8 *frm, *efrm;
70851 +
70852 +    frm = buf;
70853 +    efrm = (A_UINT8 *) (frm + framelen);
70854 +
70855 +    /*
70856 +     * beacon/probe response frame format
70857 +     *  [8] time stamp
70858 +     *  [2] beacon interval
70859 +     *  [2] capability information
70860 +     *  [tlv] ssid
70861 +     *  [tlv] supported rates
70862 +     *  [tlv] country information
70863 +     *  [tlv] parameter set (FH/DS)
70864 +     *  [tlv] erp information
70865 +     *  [tlv] extended supported rates
70866 +     *  [tlv] WMM
70867 +     *  [tlv] WPA or RSN
70868 +     *  [tlv] Atheros Advanced Capabilities
70869 +     */
70870 +    IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
70871 +    A_MEMZERO(cie, sizeof(*cie));
70872 +
70873 +    cie->ie_tstamp = frm; frm += 8;
70874 +    cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
70875 +    cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm);  frm += 2;
70876 +    cie->ie_chan = 0;
70877 +
70878 +    while (frm < efrm) {
70879 +        switch (*frm) {
70880 +        case IEEE80211_ELEMID_SSID:
70881 +            cie->ie_ssid = frm;
70882 +            break;
70883 +        case IEEE80211_ELEMID_RATES:
70884 +            cie->ie_rates = frm;
70885 +            break;
70886 +        case IEEE80211_ELEMID_COUNTRY:
70887 +            cie->ie_country = frm;
70888 +            break;
70889 +        case IEEE80211_ELEMID_FHPARMS:
70890 +            break;
70891 +        case IEEE80211_ELEMID_DSPARMS:
70892 +            cie->ie_chan = frm[2];
70893 +            break;
70894 +        case IEEE80211_ELEMID_TIM:
70895 +            cie->ie_tim = frm;
70896 +            break;
70897 +        case IEEE80211_ELEMID_IBSSPARMS:
70898 +            break;
70899 +        case IEEE80211_ELEMID_XRATES:
70900 +            cie->ie_xrates = frm;
70901 +            break;
70902 +        case IEEE80211_ELEMID_ERP:
70903 +            if (frm[1] != 1) {
70904 +                //A_PRINTF("Discarding ERP Element - Bad Len\n");
70905 +                return A_EINVAL;
70906 +            }
70907 +            cie->ie_erp = frm[2];
70908 +            break;
70909 +        case IEEE80211_ELEMID_RSN:
70910 +            cie->ie_rsn = frm;
70911 +            break;
70912 +        case IEEE80211_ELEMID_VENDOR:
70913 +            if (iswpaoui(frm)) {
70914 +                cie->ie_wpa = frm;
70915 +            } else if (iswmmoui(frm)) {
70916 +                cie->ie_wmm = frm;
70917 +            } else if (isatherosoui(frm)) {
70918 +                cie->ie_ath = frm;
70919 +            } else if(iswscoui(frm)) {
70920 +                cie->ie_wsc = frm;
70921 +            }
70922 +            break;
70923 +        default:
70924 +            break;
70925 +        }
70926 +        frm += frm[1] + 2;
70927 +    }
70928 +    IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
70929 +    IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
70930 +
70931 +    return A_OK;
70932 +}
70933 Index: linux-2.6.28/drivers/ar6000/wlan/wlan_utils.c
70934 ===================================================================
70935 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
70936 +++ linux-2.6.28/drivers/ar6000/wlan/wlan_utils.c       2009-01-02 00:01:56.000000000 +0100
70937 @@ -0,0 +1,59 @@
70938 +/*
70939 + * Copyright (c) 2004-2005 Atheros Communications Inc.
70940 + * All rights reserved.
70941 + *
70942 + * This module implements frequently used wlan utilies
70943 + *
70944 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wlan/src/wlan_utils.c#1 $
70945 + *
70946 + *
70947 + *  This program is free software; you can redistribute it and/or modify
70948 + *  it under the terms of the GNU General Public License version 2 as
70949 + *  published by the Free Software Foundation;
70950 + *
70951 + *  Software distributed under the License is distributed on an "AS
70952 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
70953 + *  implied. See the License for the specific language governing
70954 + *  rights and limitations under the License.
70955 + *
70956 + *
70957 + *
70958 + */
70959 +
70960 +#include <a_config.h>
70961 +#include <athdefs.h>
70962 +#include <a_types.h>
70963 +#include <a_osapi.h>
70964 +
70965 +/*
70966 + * converts ieee channel number to frequency
70967 + */
70968 +A_UINT16
70969 +wlan_ieee2freq(int chan)
70970 +{
70971 +    if (chan == 14) {
70972 +        return 2484;
70973 +    }
70974 +    if (chan < 14) {    /* 0-13 */
70975 +        return (2407 + (chan*5));
70976 +    }
70977 +    if (chan < 27) {    /* 15-26 */
70978 +        return (2512 + ((chan-15)*20));
70979 +    }
70980 +    return (5000 + (chan*5));
70981 +}
70982 +
70983 +/*
70984 + * Converts MHz frequency to IEEE channel number.
70985 + */
70986 +A_UINT32
70987 +wlan_freq2ieee(A_UINT16 freq)
70988 +{
70989 +    if (freq == 2484)
70990 +        return 14;
70991 +    if (freq < 2484)
70992 +        return (freq - 2407) / 5;
70993 +    if (freq < 5000)
70994 +        return 15 + ((freq - 2512) / 20);
70995 +    return (freq - 5000) / 5;
70996 +}
70997 Index: linux-2.6.28/drivers/ar6000/wmi/wmi.c
70998 ===================================================================
70999 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
71000 +++ linux-2.6.28/drivers/ar6000/wmi/wmi.c       2009-01-02 00:01:56.000000000 +0100
71001 @@ -0,0 +1,3954 @@
71002 +/*
71003 + * Copyright (c) 2004-2007 Atheros Communications Inc.
71004 + * All rights reserved.
71005 + *
71006 + * This module implements the hardware independent layer of the
71007 + * Wireless Module Interface (WMI) protocol.
71008 + *
71009 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wmi/wmi.c#3 $
71010 + *
71011 + *
71012 + *  This program is free software; you can redistribute it and/or modify
71013 + *  it under the terms of the GNU General Public License version 2 as
71014 + *  published by the Free Software Foundation;
71015 + *
71016 + *  Software distributed under the License is distributed on an "AS
71017 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
71018 + *  implied. See the License for the specific language governing
71019 + *  rights and limitations under the License.
71020 + *
71021 + *
71022 + *
71023 + */
71024 +
71025 +#include <a_config.h>
71026 +#include <athdefs.h>
71027 +#include <a_types.h>
71028 +#include <a_osapi.h>
71029 +#include "htc.h"
71030 +#include "htc_api.h"
71031 +#include "wmi.h"
71032 +#include <ieee80211.h>
71033 +#include <ieee80211_node.h>
71034 +#include <wlan_api.h>
71035 +#include <wmi_api.h>
71036 +#include "dset_api.h"
71037 +#include "gpio_api.h"
71038 +#include "wmi_host.h"
71039 +#include "a_drv.h"
71040 +#include "a_drv_api.h"
71041 +#include "a_debug.h"
71042 +#include "dbglog_api.h"
71043 +
71044 +static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71045 +
71046 +static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71047 +                                     int len);
71048 +static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71049 +                                        int len);
71050 +static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71051 +                                        int len);
71052 +static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71053 +                                     int len);
71054 +static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71055 +                                       int len);
71056 +static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71057 +                                     int len);
71058 +static A_STATUS wmi_sync_point(struct wmi_t *wmip);
71059 +
71060 +static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
71061 +                                     int len);
71062 +static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
71063 +                                     int len);
71064 +static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
71065 +                                         int len);
71066 +static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71067 +                                       int len);
71068 +static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71069 +static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71070 +                                             int len);
71071 +
71072 +static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
71073 +                                     int len);
71074 +#ifdef CONFIG_HOST_DSET_SUPPORT
71075 +static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71076 +static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
71077 +                                     int len);
71078 +#endif /* CONFIG_HOST_DSET_SUPPORT */
71079 +
71080 +
71081 +static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap,
71082 +                                     int len);
71083 +static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71084 +static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71085 +static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71086 +static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71087 +static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71088 +static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71089 +static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71090 +                                      int len);
71091 +static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71092 +                                      int len);
71093 +static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
71094 +                                      int len);
71095 +static A_STATUS
71096 +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
71097 +
71098 +#ifdef CONFIG_HOST_GPIO_SUPPORT
71099 +static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71100 +static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71101 +static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71102 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
71103 +
71104 +#ifdef CONFIG_HOST_TCMD_SUPPORT
71105 +static A_STATUS
71106 +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71107 +#endif
71108 +
71109 +static A_STATUS
71110 +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71111 +
71112 +static A_STATUS
71113 +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71114 +
71115 +static A_STATUS
71116 +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71117 +
71118 +static A_BOOL
71119 +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_UINT32 rateIndex);
71120 +
71121 +static A_STATUS
71122 +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71123 +
71124 +static A_STATUS
71125 +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71126 +
71127 +static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
71128 +
71129 +int wps_enable;
71130 +static const A_INT32 wmi_rateTable[] = {
71131 +    1000,
71132 +    2000,
71133 +    5500,
71134 +    11000,
71135 +    6000,
71136 +    9000,
71137 +    12000,
71138 +    18000,
71139 +    24000,
71140 +    36000,
71141 +    48000,
71142 +    54000,
71143 +    0};
71144 +
71145 +#define MODE_A_SUPPORT_RATE_START       4
71146 +#define MODE_A_SUPPORT_RATE_STOP        11
71147 +
71148 +#define MODE_GONLY_SUPPORT_RATE_START   MODE_A_SUPPORT_RATE_START
71149 +#define MODE_GONLY_SUPPORT_RATE_STOP    MODE_A_SUPPORT_RATE_STOP
71150 +
71151 +#define MODE_B_SUPPORT_RATE_START       0
71152 +#define MODE_B_SUPPORT_RATE_STOP        3
71153 +
71154 +#define MODE_G_SUPPORT_RATE_START       0
71155 +#define MODE_G_SUPPORT_RATE_STOP        11
71156 +
71157 +#define MAX_NUMBER_OF_SUPPORT_RATES     (MODE_G_SUPPORT_RATE_STOP + 1)
71158 +
71159 +/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
71160 +const A_UINT8 up_to_ac[]= {
71161 +                WMM_AC_BE,
71162 +                WMM_AC_BK,
71163 +                WMM_AC_BK,
71164 +                WMM_AC_BE,
71165 +                WMM_AC_VI,
71166 +                WMM_AC_VI,
71167 +                WMM_AC_VO,
71168 +                WMM_AC_VO,
71169 +            };
71170 +
71171 +void *
71172 +wmi_init(void *devt)
71173 +{
71174 +    struct wmi_t *wmip;
71175 +
71176 +    wmip = A_MALLOC(sizeof(struct wmi_t));
71177 +    if (wmip == NULL) {
71178 +        return (NULL);
71179 +    }
71180 +    A_MEMZERO(wmip, sizeof(*wmip));
71181 +    A_MUTEX_INIT(&wmip->wmi_lock);
71182 +    wmip->wmi_devt = devt;
71183 +    wlan_node_table_init(wmip, &wmip->wmi_scan_table);
71184 +    wmi_qos_state_init(wmip);
71185 +    wmip->wmi_powerMode = REC_POWER;
71186 +    wmip->wmi_phyMode = WMI_11G_MODE;
71187 +
71188 +    return (wmip);
71189 +}
71190 +
71191 +void
71192 +wmi_qos_state_init(struct wmi_t *wmip)
71193 +{
71194 +    A_UINT8 i;
71195 +
71196 +    if (wmip == NULL) {
71197 +        return;
71198 +    }
71199 +    LOCK_WMI(wmip);
71200 +
71201 +    /* Initialize QoS States */
71202 +    wmip->wmi_numQoSStream = 0;
71203 +
71204 +    wmip->wmi_fatPipeExists = 0;
71205 +
71206 +    for (i=0; i < WMM_NUM_AC; i++) {
71207 +        wmip->wmi_streamExistsForAC[i]=0;
71208 +    }
71209 +
71210 +        /* Initialize the static Wmi stream Pri to WMM AC mappings Arrays */
71211 +    WMI_INIT_WMISTREAM_AC_MAP(wmip);
71212 +
71213 +    UNLOCK_WMI(wmip);
71214 +
71215 +    A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1);
71216 +}
71217 +
71218 +void
71219 +wmi_shutdown(struct wmi_t *wmip)
71220 +{
71221 +    if (wmip != NULL) {
71222 +        wlan_node_table_cleanup(&wmip->wmi_scan_table);
71223 +        if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) {
71224 +            A_MUTEX_DELETE(&wmip->wmi_lock);
71225 +        }
71226 +        A_FREE(wmip);
71227 +    }
71228 +}
71229 +
71230 +/*
71231 + *  performs DIX to 802.3 encapsulation for transmit packets.
71232 + *  uses passed in buffer.  Returns buffer or NULL if failed.
71233 + *  Assumes the entire DIX header is contigous and that there is
71234 + *  enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
71235 + */
71236 +A_STATUS
71237 +wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf)
71238 +{
71239 +    A_UINT8          *datap;
71240 +    A_UINT16         typeorlen;
71241 +    ATH_MAC_HDR      macHdr;
71242 +    ATH_LLC_SNAP_HDR *llcHdr;
71243 +
71244 +    A_ASSERT(osbuf != NULL);
71245 +
71246 +    if (A_NETBUF_HEADROOM(osbuf) <
71247 +        (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
71248 +    {
71249 +        return A_NO_MEMORY;
71250 +    }
71251 +
71252 +    datap = A_NETBUF_DATA(osbuf);
71253 +
71254 +    typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
71255 +
71256 +    if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
71257 +        /*
71258 +         * packet is already in 802.3 format - return success
71259 +         */
71260 +        A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
71261 +        return (A_OK);
71262 +    }
71263 +
71264 +    /*
71265 +     * Save mac fields and length to be inserted later
71266 +     */
71267 +    A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
71268 +    A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
71269 +    macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
71270 +                                  sizeof(ATH_LLC_SNAP_HDR));
71271 +
71272 +    /*
71273 +     * Make room for LLC+SNAP headers
71274 +     */
71275 +    if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
71276 +        return A_NO_MEMORY;
71277 +    }
71278 +
71279 +    datap = A_NETBUF_DATA(osbuf);
71280 +
71281 +    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
71282 +
71283 +    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
71284 +    llcHdr->dsap      = 0xAA;
71285 +    llcHdr->ssap      = 0xAA;
71286 +    llcHdr->cntl      = 0x03;
71287 +    llcHdr->orgCode[0] = 0x0;
71288 +    llcHdr->orgCode[1] = 0x0;
71289 +    llcHdr->orgCode[2] = 0x0;
71290 +    llcHdr->etherType = typeorlen;
71291 +
71292 +    return (A_OK);
71293 +}
71294 +
71295 +/*
71296 + * Adds a WMI data header
71297 + * Assumes there is enough room in the buffer to add header.
71298 + */
71299 +A_STATUS
71300 +wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType)
71301 +{
71302 +    WMI_DATA_HDR     *dtHdr;
71303 +
71304 +    A_ASSERT(osbuf != NULL);
71305 +
71306 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
71307 +        return A_NO_MEMORY;
71308 +    }
71309 +
71310 +    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
71311 +    dtHdr->info = msgType;
71312 +    dtHdr->rssi = 0;
71313 +
71314 +    return (A_OK);
71315 +}
71316 +
71317 +A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir, A_UINT8 up)
71318 +{
71319 +    A_UINT8         *datap;
71320 +    A_UINT8         trafficClass = WMM_AC_BE, userPriority = up;
71321 +    ATH_LLC_SNAP_HDR *llcHdr;
71322 +    A_UINT16        ipType = IP_ETHERTYPE;
71323 +    WMI_DATA_HDR     *dtHdr;
71324 +    WMI_CREATE_PSTREAM_CMD  cmd;
71325 +    A_BOOL           streamExists = FALSE;
71326 +
71327 +    A_ASSERT(osbuf != NULL);
71328 +
71329 +    datap = A_NETBUF_DATA(osbuf);
71330 +
71331 +    if (up == UNDEFINED_PRI) {
71332 +    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) +
71333 +                                  sizeof(ATH_MAC_HDR));
71334 +
71335 +        if (llcHdr->etherType == A_CPU2BE16(ipType)) {
71336 +        /* Extract the endpoint info from the TOS field in the IP header */
71337 +        userPriority = A_WMI_IPTOS_TO_USERPRIORITY(((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR));
71338 +        }
71339 +    }
71340 +
71341 +    if (userPriority < MAX_NUM_PRI) {
71342 +        trafficClass = convert_userPriority_to_trafficClass(userPriority);
71343 +    }
71344 +
71345 +    dtHdr = (WMI_DATA_HDR *)datap;
71346 +    if(dir==UPLINK_TRAFFIC)
71347 +        dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT;  /* lower 3-bits are 802.1d priority */
71348 +
71349 +    LOCK_WMI(wmip);
71350 +    streamExists = wmip->wmi_fatPipeExists;
71351 +    UNLOCK_WMI(wmip);
71352 +
71353 +    if (!(streamExists & (1 << trafficClass))) {
71354 +
71355 +        A_MEMZERO(&cmd, sizeof(cmd));
71356 +           cmd.trafficClass = trafficClass;
71357 +           cmd.userPriority = userPriority;
71358 +               cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
71359 +            /* Implicit streams are created with TSID 0xFF */
71360 +        cmd.tsid = WMI_IMPLICIT_PSTREAM;
71361 +        wmi_create_pstream_cmd(wmip, &cmd);
71362 +    }
71363 +
71364 +    return trafficClass;
71365 +}
71366 +
71367 +WMI_PRI_STREAM_ID
71368 +wmi_get_stream_id(struct wmi_t *wmip, A_UINT8 trafficClass)
71369 +{
71370 +    return WMI_ACCESSCATEGORY_WMISTREAM(wmip, trafficClass);
71371 +}
71372 +
71373 +/*
71374 + *  performs 802.3 to DIX encapsulation for received packets.
71375 + *  Assumes the entire 802.3 header is contigous.
71376 + */
71377 +A_STATUS
71378 +wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf)
71379 +{
71380 +    A_UINT8          *datap;
71381 +    ATH_MAC_HDR      macHdr;
71382 +    ATH_LLC_SNAP_HDR *llcHdr;
71383 +
71384 +    A_ASSERT(osbuf != NULL);
71385 +    datap = A_NETBUF_DATA(osbuf);
71386 +
71387 +    A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
71388 +    llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
71389 +    macHdr.typeOrLen = llcHdr->etherType;
71390 +
71391 +    if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
71392 +        return A_NO_MEMORY;
71393 +    }
71394 +
71395 +    datap = A_NETBUF_DATA(osbuf);
71396 +
71397 +    A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
71398 +
71399 +    return (A_OK);
71400 +}
71401 +
71402 +/*
71403 + * Removes a WMI data header
71404 + */
71405 +A_STATUS
71406 +wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf)
71407 +{
71408 +    A_ASSERT(osbuf != NULL);
71409 +
71410 +    return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR)));
71411 +}
71412 +
71413 +void
71414 +wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg)
71415 +{
71416 +    wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
71417 +}
71418 +
71419 +/*
71420 + * WMI Extended Event received from Target.
71421 + */
71422 +A_STATUS
71423 +wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf)
71424 +{
71425 +    WMIX_CMD_HDR *cmd;
71426 +    A_UINT16 id;
71427 +    A_UINT8 *datap;
71428 +    A_UINT32 len;
71429 +    A_STATUS status = A_OK;
71430 +
71431 +    if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) {
71432 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
71433 +        wmip->wmi_stats.cmd_len_err++;
71434 +        A_NETBUF_FREE(osbuf);
71435 +        return A_ERROR;
71436 +    }
71437 +
71438 +    cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
71439 +    id = cmd->commandId;
71440 +
71441 +    if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
71442 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
71443 +        wmip->wmi_stats.cmd_len_err++;
71444 +        A_NETBUF_FREE(osbuf);
71445 +        return A_ERROR;
71446 +    }
71447 +
71448 +    datap = A_NETBUF_DATA(osbuf);
71449 +    len = A_NETBUF_LEN(osbuf);
71450 +
71451 +    switch (id) {
71452 +    case (WMIX_DSETOPENREQ_EVENTID):
71453 +        status = wmi_dset_open_req_rx(wmip, datap, len);
71454 +        break;
71455 +#ifdef CONFIG_HOST_DSET_SUPPORT
71456 +    case (WMIX_DSETCLOSE_EVENTID):
71457 +        status = wmi_dset_close_rx(wmip, datap, len);
71458 +        break;
71459 +    case (WMIX_DSETDATAREQ_EVENTID):
71460 +        status = wmi_dset_data_req_rx(wmip, datap, len);
71461 +        break;
71462 +#endif /* CONFIG_HOST_DSET_SUPPORT */
71463 +#ifdef CONFIG_HOST_GPIO_SUPPORT
71464 +    case (WMIX_GPIO_INTR_EVENTID):
71465 +        wmi_gpio_intr_rx(wmip, datap, len);
71466 +        break;
71467 +    case (WMIX_GPIO_DATA_EVENTID):
71468 +        wmi_gpio_data_rx(wmip, datap, len);
71469 +        break;
71470 +    case (WMIX_GPIO_ACK_EVENTID):
71471 +        wmi_gpio_ack_rx(wmip, datap, len);
71472 +        break;
71473 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
71474 +    case (WMIX_HB_CHALLENGE_RESP_EVENTID):
71475 +        wmi_hbChallengeResp_rx(wmip, datap, len);
71476 +        break;
71477 +    case (WMIX_DBGLOG_EVENTID):
71478 +        wmi_dbglog_event_rx(wmip, datap, len);
71479 +        break;
71480 +    default:
71481 +        A_DPRINTF(DBG_WMI|DBG_ERROR,
71482 +            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
71483 +        wmip->wmi_stats.cmd_id_err++;
71484 +        status = A_ERROR;
71485 +        break;
71486 +    }
71487 +
71488 +    return status;
71489 +}
71490 +
71491 +/*
71492 + * Control Path
71493 + */
71494 +A_UINT32 cmdRecvNum;
71495 +
71496 +A_STATUS
71497 +wmi_control_rx(struct wmi_t *wmip, void *osbuf)
71498 +{
71499 +    WMI_CMD_HDR *cmd;
71500 +    A_UINT16 id;
71501 +    A_UINT8 *datap;
71502 +    A_UINT32 len, i, loggingReq;
71503 +    A_STATUS status = A_OK;
71504 +
71505 +    A_ASSERT(osbuf != NULL);
71506 +    if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) {
71507 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
71508 +        wmip->wmi_stats.cmd_len_err++;
71509 +        A_NETBUF_FREE(osbuf);
71510 +        return A_ERROR;
71511 +    }
71512 +
71513 +    cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
71514 +    id = cmd->commandId;
71515 +
71516 +    if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
71517 +        A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
71518 +        wmip->wmi_stats.cmd_len_err++;
71519 +        A_NETBUF_FREE(osbuf);
71520 +        return A_ERROR;
71521 +    }
71522 +
71523 +    datap = A_NETBUF_DATA(osbuf);
71524 +    len = A_NETBUF_LEN(osbuf);
71525 +
71526 +    ar6000_get_driver_cfg(wmip->wmi_devt,
71527 +                    AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS,
71528 +                    &loggingReq);
71529 +
71530 +    if(loggingReq) {
71531 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id));
71532 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum));
71533 +        for(i = 0; i < len; i++)
71534 +            AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i]));
71535 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n"));
71536 +    }
71537 +
71538 +    LOCK_WMI(wmip);
71539 +    cmdRecvNum++;
71540 +    UNLOCK_WMI(wmip);
71541 +
71542 +    switch (id) {
71543 +    case (WMI_GET_BITRATE_CMDID):
71544 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG));
71545 +        status = wmi_bitrate_reply_rx(wmip, datap, len);
71546 +        break;
71547 +    case (WMI_GET_CHANNEL_LIST_CMDID):
71548 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG));
71549 +        status = wmi_channelList_reply_rx(wmip, datap, len);
71550 +        break;
71551 +    case (WMI_GET_TX_PWR_CMDID):
71552 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG));
71553 +        status = wmi_txPwr_reply_rx(wmip, datap, len);
71554 +        break;
71555 +    case (WMI_READY_EVENTID):
71556 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG));
71557 +        status = wmi_ready_event_rx(wmip, datap, len);
71558 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71559 +        A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt);
71560 +        break;
71561 +    case (WMI_CONNECT_EVENTID):
71562 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG));
71563 +        status = wmi_connect_event_rx(wmip, datap, len);
71564 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71565 +        break;
71566 +    case (WMI_DISCONNECT_EVENTID):
71567 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG));
71568 +        status = wmi_disconnect_event_rx(wmip, datap, len);
71569 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71570 +        break;
71571 +    case (WMI_TKIP_MICERR_EVENTID):
71572 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG));
71573 +        status = wmi_tkip_micerr_event_rx(wmip, datap, len);
71574 +        break;
71575 +    case (WMI_BSSINFO_EVENTID):
71576 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG));
71577 +        status = wmi_bssInfo_event_rx(wmip, datap, len);
71578 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71579 +        break;
71580 +    case (WMI_REGDOMAIN_EVENTID):
71581 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG));
71582 +        status = wmi_regDomain_event_rx(wmip, datap, len);
71583 +        break;
71584 +    case (WMI_PSTREAM_TIMEOUT_EVENTID):
71585 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG));
71586 +        status = wmi_pstream_timeout_event_rx(wmip, datap, len);
71587 +            /* pstreams are fatpipe abstractions that get implicitly created.
71588 +             * User apps only deal with thinstreams. creation of a thinstream
71589 +             * by the user or data traffic flow in an AC triggers implicit
71590 +             * pstream creation. Do we need to send this event to App..?
71591 +             * no harm in sending it.
71592 +             */
71593 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71594 +        break;
71595 +    case (WMI_NEIGHBOR_REPORT_EVENTID):
71596 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG));
71597 +        status = wmi_neighborReport_event_rx(wmip, datap, len);
71598 +        break;
71599 +    case (WMI_SCAN_COMPLETE_EVENTID):
71600 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG));
71601 +        status = wmi_scanComplete_rx(wmip, datap, len);
71602 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71603 +        break;
71604 +    case (WMI_CMDERROR_EVENTID):
71605 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG));
71606 +        status = wmi_errorEvent_rx(wmip, datap, len);
71607 +        break;
71608 +    case (WMI_REPORT_STATISTICS_EVENTID):
71609 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG));
71610 +        status = wmi_statsEvent_rx(wmip, datap, len);
71611 +        break;
71612 +    case (WMI_RSSI_THRESHOLD_EVENTID):
71613 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG));
71614 +        status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
71615 +        break;
71616 +    case (WMI_ERROR_REPORT_EVENTID):
71617 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG));
71618 +        status = wmi_reportErrorEvent_rx(wmip, datap, len);
71619 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71620 +        break;
71621 +    case (WMI_OPT_RX_FRAME_EVENTID):
71622 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG));
71623 +        status = wmi_opt_frame_event_rx(wmip, datap, len);
71624 +        break;
71625 +    case (WMI_REPORT_ROAM_TBL_EVENTID):
71626 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG));
71627 +        status = wmi_roam_tbl_event_rx(wmip, datap, len);
71628 +        break;
71629 +    case (WMI_EXTENSION_EVENTID):
71630 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG));
71631 +        status = wmi_control_rx_xtnd(wmip, osbuf);
71632 +        break;
71633 +    case (WMI_CAC_EVENTID):
71634 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG));
71635 +        status = wmi_cac_event_rx(wmip, datap, len);
71636 +        break;
71637 +    case (WMI_REPORT_ROAM_DATA_EVENTID):
71638 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG));
71639 +        status = wmi_roam_data_event_rx(wmip, datap, len);
71640 +        break;
71641 +#ifdef CONFIG_HOST_TCMD_SUPPORT
71642 +    case (WMI_TEST_EVENTID):
71643 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG));
71644 +        status = wmi_tcmd_test_report_rx(wmip, datap, len);
71645 +        break;
71646 +#endif
71647 +    case (WMI_GET_FIXRATES_CMDID):
71648 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG));
71649 +        status = wmi_ratemask_reply_rx(wmip, datap, len);
71650 +        break;
71651 +    case (WMI_TX_RETRY_ERR_EVENTID):
71652 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG));
71653 +        status = wmi_txRetryErrEvent_rx(wmip, datap, len);
71654 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71655 +        break;
71656 +    case (WMI_SNR_THRESHOLD_EVENTID):
71657 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG));
71658 +        status = wmi_snrThresholdEvent_rx(wmip, datap, len);
71659 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71660 +        break;
71661 +    case (WMI_LQ_THRESHOLD_EVENTID):
71662 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG));
71663 +        status = wmi_lqThresholdEvent_rx(wmip, datap, len);
71664 +        A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
71665 +        break;
71666 +    case (WMI_APLIST_EVENTID):
71667 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n"));
71668 +        status = wmi_aplistEvent_rx(wmip, datap, len);
71669 +        break;
71670 +    case (WMI_GET_KEEPALIVE_CMDID):
71671 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG));
71672 +        status = wmi_keepalive_reply_rx(wmip, datap, len);
71673 +        break;
71674 +    case (WMI_GET_WOW_LIST_EVENTID):
71675 +        status = wmi_get_wow_list_event_rx(wmip, datap, len);
71676 +        break;
71677 +    case (WMI_GET_PMKID_LIST_EVENTID):
71678 +        A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG));
71679 +        status = wmi_get_pmkid_list_event_rx(wmip, datap, len);
71680 +        break;
71681 +    default:
71682 +        A_DPRINTF(DBG_WMI|DBG_ERROR,
71683 +            (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
71684 +        wmip->wmi_stats.cmd_id_err++;
71685 +        status = A_ERROR;
71686 +        break;
71687 +    }
71688 +
71689 +    A_NETBUF_FREE(osbuf);
71690 +
71691 +    return status;
71692 +}
71693 +
71694 +static A_STATUS
71695 +wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71696 +{
71697 +    WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap;
71698 +
71699 +    if (len < sizeof(WMI_READY_EVENT)) {
71700 +        return A_EINVAL;
71701 +    }
71702 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71703 +    wmip->wmi_ready = TRUE;
71704 +    A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability);
71705 +
71706 +    return A_OK;
71707 +}
71708 +
71709 +static A_STATUS
71710 +wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71711 +{
71712 +    WMI_CONNECT_EVENT *ev;
71713 +
71714 +    if (len < sizeof(WMI_CONNECT_EVENT)) {
71715 +        return A_EINVAL;
71716 +    }
71717 +    ev = (WMI_CONNECT_EVENT *)datap;
71718 +    A_DPRINTF(DBG_WMI,
71719 +        (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
71720 +        DBGARG, ev->channel,
71721 +        ev->bssid[0], ev->bssid[1], ev->bssid[2],
71722 +        ev->bssid[3], ev->bssid[4], ev->bssid[5]));
71723 +
71724 +    A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
71725 +
71726 +    A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid,
71727 +                         ev->listenInterval, ev->beaconInterval,
71728 +                         ev->networkType, ev->beaconIeLen,
71729 +                         ev->assocReqLen, ev->assocRespLen,
71730 +                         ev->assocInfo);
71731 +
71732 +    return A_OK;
71733 +}
71734 +
71735 +static A_STATUS
71736 +wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71737 +{
71738 +    WMI_REG_DOMAIN_EVENT *ev;
71739 +
71740 +    if (len < sizeof(*ev)) {
71741 +        return A_EINVAL;
71742 +    }
71743 +    ev = (WMI_REG_DOMAIN_EVENT *)datap;
71744 +
71745 +    A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain);
71746 +
71747 +    return A_OK;
71748 +}
71749 +
71750 +static A_STATUS
71751 +wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71752 +{
71753 +    WMI_NEIGHBOR_REPORT_EVENT *ev;
71754 +    int numAps;
71755 +
71756 +    if (len < sizeof(*ev)) {
71757 +        return A_EINVAL;
71758 +    }
71759 +    ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap;
71760 +    numAps = ev->numberOfAps;
71761 +
71762 +    if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
71763 +        return A_EINVAL;
71764 +    }
71765 +
71766 +    A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor);
71767 +
71768 +    return A_OK;
71769 +}
71770 +
71771 +static A_STATUS
71772 +wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71773 +{
71774 +    WMI_DISCONNECT_EVENT *ev;
71775 +
71776 +    if (len < sizeof(WMI_DISCONNECT_EVENT)) {
71777 +        return A_EINVAL;
71778 +    }
71779 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71780 +
71781 +    ev = (WMI_DISCONNECT_EVENT *)datap;
71782 +
71783 +    A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
71784 +
71785 +    A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid,
71786 +                            ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus);
71787 +
71788 +    return A_OK;
71789 +}
71790 +
71791 +static A_STATUS
71792 +wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71793 +{
71794 +    WMI_TKIP_MICERR_EVENT *ev;
71795 +
71796 +    if (len < sizeof(*ev)) {
71797 +        return A_EINVAL;
71798 +    }
71799 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
71800 +
71801 +    ev = (WMI_TKIP_MICERR_EVENT *)datap;
71802 +    A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast);
71803 +
71804 +    return A_OK;
71805 +}
71806 +
71807 +static A_STATUS
71808 +wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71809 +{
71810 +    bss_t *bss;
71811 +    WMI_BSS_INFO_HDR *bih;
71812 +    A_UINT8 *buf;
71813 +    A_UINT32 nodeCachingAllowed;
71814 +
71815 +    if (len <= sizeof(WMI_BSS_INFO_HDR)) {
71816 +        return A_EINVAL;
71817 +    }
71818 +
71819 +    A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len);
71820 +    /* What is driver config for wlan node caching? */
71821 +    if(ar6000_get_driver_cfg(wmip->wmi_devt,
71822 +                    AR6000_DRIVER_CFG_GET_WLANNODECACHING,
71823 +                    &nodeCachingAllowed) != A_OK) {
71824 +        return A_EINVAL;
71825 +    }
71826 +
71827 +    if(!nodeCachingAllowed) {
71828 +        return A_OK;
71829 +    }
71830 +
71831 +
71832 +    bih = (WMI_BSS_INFO_HDR *)datap;
71833 +    buf = datap + sizeof(WMI_BSS_INFO_HDR);
71834 +    len -= sizeof(WMI_BSS_INFO_HDR);
71835 +
71836 +    A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, "
71837 +              "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG,
71838 +              bih->channel, (unsigned char) bih->rssi, bih->bssid[0],
71839 +              bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4],
71840 +              bih->bssid[5]));
71841 +
71842 +    if(wps_enable && (bih->frameType == PROBERESP_FTYPE) ) {
71843 +           printk("%s() A_OK 2\n", __FUNCTION__);
71844 +               return A_OK;
71845 +    }
71846 +
71847 +    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
71848 +    if (bss != NULL) {
71849 +        /*
71850 +         * Free up the node.  Not the most efficient process given
71851 +         * we are about to allocate a new node but it is simple and should be
71852 +         * adequate.
71853 +         */
71854 +        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
71855 +    }
71856 +
71857 +    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
71858 +    if (bss == NULL) {
71859 +        return A_NO_MEMORY;
71860 +    }
71861 +
71862 +    bss->ni_snr        = bih->snr;
71863 +    bss->ni_rssi       = bih->rssi;
71864 +    A_ASSERT(bss->ni_buf != NULL);
71865 +    A_MEMCPY(bss->ni_buf, buf, len);
71866 +
71867 +    if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
71868 +        wlan_node_free(bss);
71869 +        return A_EINVAL;
71870 +    }
71871 +
71872 +    /*
71873 +     * Update the frequency in ie_chan, overwriting of channel number
71874 +     * which is done in wlan_parse_beacon
71875 +     */
71876 +    bss->ni_cie.ie_chan = bih->channel;
71877 +    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
71878 +
71879 +    return A_OK;
71880 +}
71881 +
71882 +static A_STATUS
71883 +wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71884 +{
71885 +    bss_t *bss;
71886 +    WMI_OPT_RX_INFO_HDR *bih;
71887 +    A_UINT8 *buf;
71888 +
71889 +    if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
71890 +        return A_EINVAL;
71891 +    }
71892 +
71893 +    bih = (WMI_OPT_RX_INFO_HDR *)datap;
71894 +    buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
71895 +    len -= sizeof(WMI_OPT_RX_INFO_HDR);
71896 +
71897 +    A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG,
71898 +        bih->bssid[4], bih->bssid[5]));
71899 +
71900 +    bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
71901 +    if (bss != NULL) {
71902 +        /*
71903 +         * Free up the node.  Not the most efficient process given
71904 +         * we are about to allocate a new node but it is simple and should be
71905 +         * adequate.
71906 +         */
71907 +        wlan_node_reclaim(&wmip->wmi_scan_table, bss);
71908 +    }
71909 +
71910 +    bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
71911 +    if (bss == NULL) {
71912 +        return A_NO_MEMORY;
71913 +    }
71914 +
71915 +    bss->ni_snr        = bih->snr;
71916 +    bss->ni_cie.ie_chan = bih->channel;
71917 +    A_ASSERT(bss->ni_buf != NULL);
71918 +    A_MEMCPY(bss->ni_buf, buf, len);
71919 +    wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
71920 +
71921 +    return A_OK;
71922 +}
71923 +
71924 +    /* This event indicates inactivity timeout of a fatpipe(pstream)
71925 +     * at the target
71926 +     */
71927 +static A_STATUS
71928 +wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71929 +{
71930 +    WMI_PSTREAM_TIMEOUT_EVENT *ev;
71931 +
71932 +    if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
71933 +        return A_EINVAL;
71934 +    }
71935 +
71936 +    A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG));
71937 +
71938 +    ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap;
71939 +
71940 +        /* When the pstream (fat pipe == AC) timesout, it means there were no
71941 +         * thinStreams within this pstream & it got implicitly created due to
71942 +         * data flow on this AC. We start the inactivity timer only for
71943 +         * implicitly created pstream. Just reset the host state.
71944 +         */
71945 +        /* Set the activeTsids for this AC to 0 */
71946 +    LOCK_WMI(wmip);
71947 +    wmip->wmi_streamExistsForAC[ev->trafficClass]=0;
71948 +    wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass);
71949 +    UNLOCK_WMI(wmip);
71950 +
71951 +        /*Indicate inactivity to driver layer for this fatpipe (pstream)*/
71952 +    A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass);
71953 +
71954 +    return A_OK;
71955 +}
71956 +
71957 +static A_STATUS
71958 +wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71959 +{
71960 +    WMI_BIT_RATE_CMD *reply;
71961 +    A_INT32 rate;
71962 +
71963 +    if (len < sizeof(WMI_BIT_RATE_CMD)) {
71964 +        return A_EINVAL;
71965 +    }
71966 +    reply = (WMI_BIT_RATE_CMD *)datap;
71967 +    A_DPRINTF(DBG_WMI,
71968 +        (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex));
71969 +
71970 +    if (reply->rateIndex == RATE_AUTO) {
71971 +        rate = RATE_AUTO;
71972 +    } else {
71973 +        rate = wmi_rateTable[(A_UINT32) reply->rateIndex];
71974 +    }
71975 +
71976 +    A_WMI_BITRATE_RX(wmip->wmi_devt, rate);
71977 +
71978 +    return A_OK;
71979 +}
71980 +
71981 +static A_STATUS
71982 +wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
71983 +{
71984 +    WMI_FIX_RATES_CMD *reply;
71985 +
71986 +    if (len < sizeof(WMI_BIT_RATE_CMD)) {
71987 +        return A_EINVAL;
71988 +    }
71989 +    reply = (WMI_FIX_RATES_CMD *)datap;
71990 +    A_DPRINTF(DBG_WMI,
71991 +        (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask));
71992 +
71993 +    A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask);
71994 +
71995 +    return A_OK;
71996 +}
71997 +
71998 +static A_STATUS
71999 +wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72000 +{
72001 +    WMI_CHANNEL_LIST_REPLY *reply;
72002 +
72003 +    if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
72004 +        return A_EINVAL;
72005 +    }
72006 +    reply = (WMI_CHANNEL_LIST_REPLY *)datap;
72007 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72008 +
72009 +    A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels,
72010 +                          reply->channelList);
72011 +
72012 +    return A_OK;
72013 +}
72014 +
72015 +static A_STATUS
72016 +wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72017 +{
72018 +    WMI_TX_PWR_REPLY *reply;
72019 +
72020 +    if (len < sizeof(*reply)) {
72021 +        return A_EINVAL;
72022 +    }
72023 +    reply = (WMI_TX_PWR_REPLY *)datap;
72024 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72025 +
72026 +    A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM);
72027 +
72028 +    return A_OK;
72029 +}
72030 +static A_STATUS
72031 +wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72032 +{
72033 +    WMI_GET_KEEPALIVE_CMD *reply;
72034 +
72035 +    if (len < sizeof(*reply)) {
72036 +        return A_EINVAL;
72037 +    }
72038 +    reply = (WMI_GET_KEEPALIVE_CMD *)datap;
72039 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72040 +
72041 +    A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured);
72042 +
72043 +    return A_OK;
72044 +}
72045 +
72046 +
72047 +static A_STATUS
72048 +wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72049 +{
72050 +    WMIX_DSETOPENREQ_EVENT *dsetopenreq;
72051 +
72052 +    if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
72053 +        return A_EINVAL;
72054 +    }
72055 +    dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap;
72056 +    A_DPRINTF(DBG_WMI,
72057 +        (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id));
72058 +    A_WMI_DSET_OPEN_REQ(wmip->wmi_devt,
72059 +                        dsetopenreq->dset_id,
72060 +                        dsetopenreq->targ_dset_handle,
72061 +                        dsetopenreq->targ_reply_fn,
72062 +                        dsetopenreq->targ_reply_arg);
72063 +
72064 +    return A_OK;
72065 +}
72066 +
72067 +#ifdef CONFIG_HOST_DSET_SUPPORT
72068 +static A_STATUS
72069 +wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72070 +{
72071 +    WMIX_DSETCLOSE_EVENT *dsetclose;
72072 +
72073 +    if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
72074 +        return A_EINVAL;
72075 +    }
72076 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72077 +
72078 +    dsetclose = (WMIX_DSETCLOSE_EVENT *)datap;
72079 +    A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie);
72080 +
72081 +    return A_OK;
72082 +}
72083 +
72084 +static A_STATUS
72085 +wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72086 +{
72087 +    WMIX_DSETDATAREQ_EVENT *dsetdatareq;
72088 +
72089 +    if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
72090 +        return A_EINVAL;
72091 +    }
72092 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72093 +
72094 +    dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap;
72095 +    A_WMI_DSET_DATA_REQ(wmip->wmi_devt,
72096 +                         dsetdatareq->access_cookie,
72097 +                         dsetdatareq->offset,
72098 +                         dsetdatareq->length,
72099 +                         dsetdatareq->targ_buf,
72100 +                         dsetdatareq->targ_reply_fn,
72101 +                         dsetdatareq->targ_reply_arg);
72102 +
72103 +    return A_OK;
72104 +}
72105 +#endif /* CONFIG_HOST_DSET_SUPPORT */
72106 +
72107 +static A_STATUS
72108 +wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72109 +{
72110 +    WMI_SCAN_COMPLETE_EVENT *ev;
72111 +
72112 +    ev = (WMI_SCAN_COMPLETE_EVENT *)datap;
72113 +    A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, ev->status);
72114 +
72115 +    return A_OK;
72116 +}
72117 +
72118 +/*
72119 + * Target is reporting a programming error.  This is for
72120 + * developer aid only.  Target only checks a few common violations
72121 + * and it is responsibility of host to do all error checking.
72122 + * Behavior of target after wmi error event is undefined.
72123 + * A reset is recommended.
72124 + */
72125 +static A_STATUS
72126 +wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72127 +{
72128 +    WMI_CMD_ERROR_EVENT *ev;
72129 +
72130 +    ev = (WMI_CMD_ERROR_EVENT *)datap;
72131 +    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId));
72132 +    switch (ev->errorCode) {
72133 +    case (INVALID_PARAM):
72134 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n"));
72135 +        break;
72136 +    case (ILLEGAL_STATE):
72137 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n"));
72138 +        break;
72139 +    case (INTERNAL_ERROR):
72140 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n"));
72141 +        break;
72142 +    }
72143 +
72144 +    return A_OK;
72145 +}
72146 +
72147 +
72148 +static A_STATUS
72149 +wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72150 +{
72151 +    WMI_TARGET_STATS *reply;
72152 +
72153 +    if (len < sizeof(*reply)) {
72154 +        return A_EINVAL;
72155 +    }
72156 +    reply = (WMI_TARGET_STATS *)datap;
72157 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72158 +
72159 +    A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, reply);
72160 +
72161 +    return A_OK;
72162 +}
72163 +
72164 +static A_STATUS
72165 +wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72166 +{
72167 +    WMI_RSSI_THRESHOLD_EVENT *reply;
72168 +
72169 +    if (len < sizeof(*reply)) {
72170 +        return A_EINVAL;
72171 +    }
72172 +    reply = (WMI_RSSI_THRESHOLD_EVENT *)datap;
72173 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72174 +
72175 +    A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, reply->range, reply->rssi);
72176 +
72177 +    return A_OK;
72178 +}
72179 +
72180 +
72181 +static A_STATUS
72182 +wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72183 +{
72184 +    WMI_TARGET_ERROR_REPORT_EVENT *reply;
72185 +
72186 +    if (len < sizeof(*reply)) {
72187 +        return A_EINVAL;
72188 +    }
72189 +    reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap;
72190 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72191 +
72192 +    A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, reply->errorVal);
72193 +
72194 +    return A_OK;
72195 +}
72196 +
72197 +static A_STATUS
72198 +wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72199 +{
72200 +    WMI_CAC_EVENT *reply;
72201 +
72202 +    if (len < sizeof(*reply)) {
72203 +        return A_EINVAL;
72204 +    }
72205 +    reply = (WMI_CAC_EVENT *)datap;
72206 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72207 +
72208 +    A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac,
72209 +                reply->cac_indication, reply->statusCode,
72210 +                reply->tspecSuggestion);
72211 +
72212 +    return A_OK;
72213 +}
72214 +
72215 +static A_STATUS
72216 +wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72217 +{
72218 +    WMIX_HB_CHALLENGE_RESP_EVENT *reply;
72219 +
72220 +    if (len < sizeof(*reply)) {
72221 +        return A_EINVAL;
72222 +    }
72223 +    reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap;
72224 +    A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG));
72225 +
72226 +    A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source);
72227 +
72228 +    return A_OK;
72229 +}
72230 +
72231 +static A_STATUS
72232 +wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72233 +{
72234 +    WMI_TARGET_ROAM_TBL *reply;
72235 +
72236 +    if (len < sizeof(*reply)) {
72237 +        return A_EINVAL;
72238 +    }
72239 +    reply = (WMI_TARGET_ROAM_TBL *)datap;
72240 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72241 +
72242 +    A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply);
72243 +
72244 +    return A_OK;
72245 +}
72246 +
72247 +static A_STATUS
72248 +wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72249 +{
72250 +    WMI_TARGET_ROAM_DATA *reply;
72251 +
72252 +    if (len < sizeof(*reply)) {
72253 +        return A_EINVAL;
72254 +    }
72255 +    reply = (WMI_TARGET_ROAM_DATA *)datap;
72256 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72257 +
72258 +    A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply);
72259 +
72260 +    return A_OK;
72261 +}
72262 +
72263 +static A_STATUS
72264 +wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72265 +{
72266 +    WMI_TX_RETRY_ERR_EVENT *reply;
72267 +
72268 +    if (len < sizeof(*reply)) {
72269 +        return A_EINVAL;
72270 +    }
72271 +    reply = (WMI_TX_RETRY_ERR_EVENT *)datap;
72272 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72273 +
72274 +    A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt);
72275 +
72276 +    return A_OK;
72277 +}
72278 +
72279 +static A_STATUS
72280 +wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72281 +{
72282 +    WMI_SNR_THRESHOLD_EVENT *reply;
72283 +
72284 +    if (len < sizeof(*reply)) {
72285 +        return A_EINVAL;
72286 +    }
72287 +    reply = (WMI_SNR_THRESHOLD_EVENT *)datap;
72288 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72289 +
72290 +    A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, reply->range, reply->snr);
72291 +
72292 +    return A_OK;
72293 +}
72294 +
72295 +static A_STATUS
72296 +wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72297 +{
72298 +    WMI_LQ_THRESHOLD_EVENT *reply;
72299 +
72300 +    if (len < sizeof(*reply)) {
72301 +        return A_EINVAL;
72302 +    }
72303 +    reply = (WMI_LQ_THRESHOLD_EVENT *)datap;
72304 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72305 +
72306 +    A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, reply->range, reply->lq);
72307 +
72308 +    return A_OK;
72309 +}
72310 +
72311 +static A_STATUS
72312 +wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72313 +{
72314 +    A_UINT16 ap_info_entry_size;
72315 +    WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap;
72316 +    WMI_AP_INFO_V1 *ap_info_v1;
72317 +    A_UINT8 i;
72318 +
72319 +    if (len < sizeof(WMI_APLIST_EVENT)) {
72320 +        return A_EINVAL;
72321 +    }
72322 +
72323 +    if (ev->apListVer == APLIST_VER1) {
72324 +        ap_info_entry_size = sizeof(WMI_AP_INFO_V1);
72325 +        ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList;
72326 +    } else {
72327 +        return A_EINVAL;
72328 +    }
72329 +
72330 +    AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP));
72331 +    if (len < (int)(sizeof(WMI_APLIST_EVENT) +
72332 +              (ev->numAP - 1) * ap_info_entry_size))
72333 +    {
72334 +        return A_EINVAL;
72335 +    }
72336 +
72337 +    /*
72338 +     * AP List Ver1 Contents
72339 +     */
72340 +    for (i = 0; i < ev->numAP; i++) {
72341 +        AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\
72342 +                    "Channel %d\n", i,
72343 +                   ap_info_v1->bssid[0], ap_info_v1->bssid[1],
72344 +                   ap_info_v1->bssid[2], ap_info_v1->bssid[3],
72345 +                   ap_info_v1->bssid[4], ap_info_v1->bssid[5],
72346 +                   ap_info_v1->channel));
72347 +        ap_info_v1++;
72348 +    }
72349 +    return A_OK;
72350 +}
72351 +
72352 +static A_STATUS
72353 +wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72354 +{
72355 +    A_UINT32 dropped;
72356 +
72357 +    dropped = *((A_UINT32 *)datap);
72358 +    datap += sizeof(dropped);
72359 +    len -= sizeof(dropped);
72360 +    A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, datap, len);
72361 +    return A_OK;
72362 +}
72363 +
72364 +#ifdef CONFIG_HOST_GPIO_SUPPORT
72365 +static A_STATUS
72366 +wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72367 +{
72368 +    WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
72369 +
72370 +    A_DPRINTF(DBG_WMI,
72371 +        (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG,
72372 +        gpio_intr->intr_mask, gpio_intr->input_values));
72373 +
72374 +    A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values);
72375 +
72376 +    return A_OK;
72377 +}
72378 +
72379 +static A_STATUS
72380 +wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72381 +{
72382 +    WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
72383 +
72384 +    A_DPRINTF(DBG_WMI,
72385 +        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG,
72386 +        gpio_data->reg_id, gpio_data->value));
72387 +
72388 +    A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value);
72389 +
72390 +    return A_OK;
72391 +}
72392 +
72393 +static A_STATUS
72394 +wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
72395 +{
72396 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
72397 +
72398 +    A_WMI_GPIO_ACK_RX();
72399 +
72400 +    return A_OK;
72401 +}
72402 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
72403 +
72404 +/*
72405 + * Called to send a wmi command. Command specific data is already built
72406 + * on osbuf and current osbuf->data points to it.
72407 + */
72408 +A_STATUS
72409 +wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
72410 +               WMI_SYNC_FLAG syncflag)
72411 +{
72412 +#define IS_LONG_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID) || (cmdId == WMI_ADD_WOW_PATTERN_CMDID))
72413 +    WMI_CMD_HDR         *cHdr;
72414 +    WMI_PRI_STREAM_ID   streamID = WMI_CONTROL_PRI;
72415 +
72416 +    A_ASSERT(osbuf != NULL);
72417 +
72418 +    if (syncflag >= END_WMIFLAG) {
72419 +        return A_EINVAL;
72420 +    }
72421 +
72422 +    if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
72423 +        /*
72424 +         * We want to make sure all data currently queued is transmitted before
72425 +         * the cmd execution.  Establish a new sync point.
72426 +         */
72427 +        wmi_sync_point(wmip);
72428 +    }
72429 +
72430 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
72431 +        return A_NO_MEMORY;
72432 +    }
72433 +
72434 +    cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
72435 +    cHdr->commandId = cmdId;
72436 +
72437 +    /*
72438 +     * Send cmd, some via control pipe, others via data pipe
72439 +     */
72440 +    if (IS_LONG_CMD(cmdId)) {
72441 +        wmi_data_hdr_add(wmip, osbuf, CNTL_MSGTYPE);
72442 +        // TODO ... these can now go through the control endpoint via HTC 2.0
72443 +        streamID = WMI_BEST_EFFORT_PRI;
72444 +    }
72445 +    A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, streamID);
72446 +
72447 +    if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
72448 +        /*
72449 +         * We want to make sure all new data queued waits for the command to
72450 +         * execute. Establish a new sync point.
72451 +         */
72452 +        wmi_sync_point(wmip);
72453 +    }
72454 +    return (A_OK);
72455 +#undef IS_LONG_CMD
72456 +}
72457 +
72458 +A_STATUS
72459 +wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
72460 +                  WMI_SYNC_FLAG syncflag)
72461 +{
72462 +    WMIX_CMD_HDR     *cHdr;
72463 +
72464 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
72465 +        return A_NO_MEMORY;
72466 +    }
72467 +
72468 +    cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
72469 +    cHdr->commandId = cmdId;
72470 +
72471 +    return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag);
72472 +}
72473 +
72474 +A_STATUS
72475 +wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
72476 +                DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
72477 +                CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen,
72478 +                CRYPTO_TYPE groupCrypto,A_UINT8 groupCryptoLen,
72479 +                int ssidLength, A_UCHAR *ssid,
72480 +                A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags)
72481 +{
72482 +    void *osbuf;
72483 +    WMI_CONNECT_CMD *cc;
72484 +
72485 +    if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
72486 +        return A_EINVAL;
72487 +    }
72488 +    if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
72489 +        return A_EINVAL;
72490 +    }
72491 +
72492 +    osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD));
72493 +    if (osbuf == NULL) {
72494 +        return A_NO_MEMORY;
72495 +    }
72496 +
72497 +    A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD));
72498 +
72499 +    cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
72500 +    A_MEMZERO(cc, sizeof(*cc));
72501 +
72502 +    A_MEMCPY(cc->ssid, ssid, ssidLength);
72503 +    cc->ssidLength          = ssidLength;
72504 +    cc->networkType         = netType;
72505 +    cc->dot11AuthMode       = dot11AuthMode;
72506 +    cc->authMode            = authMode;
72507 +    cc->pairwiseCryptoType  = pairwiseCrypto;
72508 +    cc->pairwiseCryptoLen   = pairwiseCryptoLen;
72509 +    cc->groupCryptoType     = groupCrypto;
72510 +    cc->groupCryptoLen      = groupCryptoLen;
72511 +    cc->channel             = channel;
72512 +    cc->ctrl_flags          = ctrl_flags;
72513 +
72514 +    if (bssid != NULL) {
72515 +        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
72516 +    }
72517 +    if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) {
72518 +        return(A_ERROR);
72519 +    }
72520 +
72521 +    return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
72522 +}
72523 +
72524 +A_STATUS
72525 +wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel)
72526 +{
72527 +    void *osbuf;
72528 +    WMI_RECONNECT_CMD *cc;
72529 +
72530 +    osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD));
72531 +    if (osbuf == NULL) {
72532 +        return A_NO_MEMORY;
72533 +    }
72534 +
72535 +    A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD));
72536 +
72537 +    cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf));
72538 +    A_MEMZERO(cc, sizeof(*cc));
72539 +
72540 +    cc->channel = channel;
72541 +
72542 +    if (bssid != NULL) {
72543 +        A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
72544 +    }
72545 +
72546 +    return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
72547 +}
72548 +
72549 +A_STATUS
72550 +wmi_disconnect_cmd(struct wmi_t *wmip)
72551 +{
72552 +    void *osbuf;
72553 +    A_STATUS status;
72554 +
72555 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
72556 +    if (osbuf == NULL) {
72557 +        return A_NO_MEMORY;
72558 +    }
72559 +
72560 +    /* Bug fix for 24817(elevator bug) - the disconnect command does not
72561 +       need to do a SYNC before.*/
72562 +    status = (wmi_cmd_send(wmip, osbuf, WMI_DISCONNECT_CMDID,
72563 +                         NO_SYNC_WMIFLAG));
72564 +
72565 +    return status;
72566 +}
72567 +
72568 +A_STATUS
72569 +wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
72570 +                  A_BOOL forceFgScan, A_BOOL isLegacy,
72571 +                  A_UINT32 homeDwellTime, A_UINT32 forceScanInterval)
72572 +{
72573 +    void *osbuf;
72574 +    WMI_START_SCAN_CMD *sc;
72575 +
72576 +    if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
72577 +        return A_EINVAL;
72578 +    }
72579 +
72580 +    osbuf = A_NETBUF_ALLOC(sizeof(*sc));
72581 +    if (osbuf == NULL) {
72582 +        return A_NO_MEMORY;
72583 +    }
72584 +
72585 +    A_NETBUF_PUT(osbuf, sizeof(*sc));
72586 +
72587 +    sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf));
72588 +    sc->scanType = scanType;
72589 +    sc->forceFgScan = forceFgScan;
72590 +    sc->isLegacy = isLegacy;
72591 +    sc->homeDwellTime = homeDwellTime;
72592 +    sc->forceScanInterval = forceScanInterval;
72593 +
72594 +    return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
72595 +}
72596 +
72597 +A_STATUS
72598 +wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
72599 +                   A_UINT16 fg_end_sec, A_UINT16 bg_sec,
72600 +                   A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec,
72601 +                   A_UINT16 pas_chdw_msec,
72602 +                   A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
72603 +                   A_UINT32 max_dfsch_act_time)
72604 +{
72605 +    void *osbuf;
72606 +    WMI_SCAN_PARAMS_CMD *sc;
72607 +
72608 +    osbuf = A_NETBUF_ALLOC(sizeof(*sc));
72609 +    if (osbuf == NULL) {
72610 +        return A_NO_MEMORY;
72611 +    }
72612 +
72613 +    A_NETBUF_PUT(osbuf, sizeof(*sc));
72614 +
72615 +    sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
72616 +    A_MEMZERO(sc, sizeof(*sc));
72617 +    sc->fg_start_period  = fg_start_sec;
72618 +    sc->fg_end_period    = fg_end_sec;
72619 +    sc->bg_period        = bg_sec;
72620 +    sc->minact_chdwell_time = minact_chdw_msec;
72621 +    sc->maxact_chdwell_time = maxact_chdw_msec;
72622 +    sc->pas_chdwell_time = pas_chdw_msec;
72623 +    sc->shortScanRatio   = shScanRatio;
72624 +    sc->scanCtrlFlags    = scanCtrlFlags;
72625 +    sc->max_dfsch_act_time = max_dfsch_act_time;
72626 +
72627 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID,
72628 +                         NO_SYNC_WMIFLAG));
72629 +}
72630 +
72631 +A_STATUS
72632 +wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask)
72633 +{
72634 +    void *osbuf;
72635 +    WMI_BSS_FILTER_CMD *cmd;
72636 +
72637 +    if (filter >= LAST_BSS_FILTER) {
72638 +        return A_EINVAL;
72639 +    }
72640 +
72641 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72642 +    if (osbuf == NULL) {
72643 +        return A_NO_MEMORY;
72644 +    }
72645 +
72646 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72647 +
72648 +    cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
72649 +    A_MEMZERO(cmd, sizeof(*cmd));
72650 +    cmd->bssFilter = filter;
72651 +    cmd->ieMask = ieMask;
72652 +
72653 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID,
72654 +                         NO_SYNC_WMIFLAG));
72655 +}
72656 +
72657 +A_STATUS
72658 +wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
72659 +                   A_UINT8 ssidLength, A_UCHAR *ssid)
72660 +{
72661 +    void *osbuf;
72662 +    WMI_PROBED_SSID_CMD *cmd;
72663 +
72664 +    if (index > MAX_PROBED_SSID_INDEX) {
72665 +        return A_EINVAL;
72666 +    }
72667 +    if (ssidLength > sizeof(cmd->ssid)) {
72668 +        return A_EINVAL;
72669 +    }
72670 +    if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
72671 +        return A_EINVAL;
72672 +    }
72673 +    if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
72674 +        return A_EINVAL;
72675 +    }
72676 +
72677 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72678 +    if (osbuf == NULL) {
72679 +        return A_NO_MEMORY;
72680 +    }
72681 +
72682 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72683 +
72684 +    cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf));
72685 +    A_MEMZERO(cmd, sizeof(*cmd));
72686 +    cmd->entryIndex = index;
72687 +    cmd->flag       = flag;
72688 +    cmd->ssidLength = ssidLength;
72689 +    A_MEMCPY(cmd->ssid, ssid, ssidLength);
72690 +
72691 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID,
72692 +                         NO_SYNC_WMIFLAG));
72693 +}
72694 +
72695 +A_STATUS
72696 +wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons)
72697 +{
72698 +    void *osbuf;
72699 +    WMI_LISTEN_INT_CMD *cmd;
72700 +
72701 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72702 +    if (osbuf == NULL) {
72703 +        return A_NO_MEMORY;
72704 +    }
72705 +
72706 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72707 +
72708 +    cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf));
72709 +    A_MEMZERO(cmd, sizeof(*cmd));
72710 +    cmd->listenInterval = listenInterval;
72711 +    cmd->numBeacons = listenBeacons;
72712 +
72713 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID,
72714 +                         NO_SYNC_WMIFLAG));
72715 +}
72716 +
72717 +A_STATUS
72718 +wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons)
72719 +{
72720 +    void *osbuf;
72721 +    WMI_BMISS_TIME_CMD *cmd;
72722 +
72723 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72724 +    if (osbuf == NULL) {
72725 +        return A_NO_MEMORY;
72726 +    }
72727 +
72728 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72729 +
72730 +    cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf));
72731 +    A_MEMZERO(cmd, sizeof(*cmd));
72732 +    cmd->bmissTime = bmissTime;
72733 +    cmd->numBeacons =  bmissBeacons;
72734 +
72735 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID,
72736 +                         NO_SYNC_WMIFLAG));
72737 +}
72738 +
72739 +A_STATUS
72740 +wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
72741 +                     A_UINT8 ieLen, A_UINT8 *ieInfo)
72742 +{
72743 +    void *osbuf;
72744 +    WMI_SET_ASSOC_INFO_CMD *cmd;
72745 +    A_UINT16 cmdLen;
72746 +
72747 +    cmdLen = sizeof(*cmd) + ieLen - 1;
72748 +    osbuf = A_NETBUF_ALLOC(cmdLen);
72749 +    if (osbuf == NULL) {
72750 +        return A_NO_MEMORY;
72751 +    }
72752 +
72753 +    A_NETBUF_PUT(osbuf, cmdLen);
72754 +
72755 +    cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf));
72756 +    A_MEMZERO(cmd, cmdLen);
72757 +    cmd->ieType = ieType;
72758 +    cmd->bufferSize = ieLen;
72759 +    A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
72760 +
72761 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID,
72762 +                         NO_SYNC_WMIFLAG));
72763 +}
72764 +
72765 +A_STATUS
72766 +wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode)
72767 +{
72768 +    void *osbuf;
72769 +    WMI_POWER_MODE_CMD *cmd;
72770 +
72771 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72772 +    if (osbuf == NULL) {
72773 +        return A_NO_MEMORY;
72774 +    }
72775 +
72776 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72777 +
72778 +    cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf));
72779 +    A_MEMZERO(cmd, sizeof(*cmd));
72780 +    cmd->powerMode = powerMode;
72781 +    wmip->wmi_powerMode = powerMode;
72782 +
72783 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID,
72784 +                         NO_SYNC_WMIFLAG));
72785 +}
72786 +
72787 +A_STATUS
72788 +wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
72789 +                   A_UINT16 atim_windows, A_UINT16 timeout_value)
72790 +{
72791 +    void *osbuf;
72792 +    WMI_IBSS_PM_CAPS_CMD *cmd;
72793 +
72794 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72795 +    if (osbuf == NULL) {
72796 +        return A_NO_MEMORY;
72797 +    }
72798 +
72799 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72800 +
72801 +    cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf));
72802 +    A_MEMZERO(cmd, sizeof(*cmd));
72803 +    cmd->power_saving = pmEnable;
72804 +    cmd->ttl = ttl;
72805 +    cmd->atim_windows = atim_windows;
72806 +    cmd->timeout_value = timeout_value;
72807 +
72808 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID,
72809 +                         NO_SYNC_WMIFLAG));
72810 +}
72811 +
72812 +A_STATUS
72813 +wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
72814 +                 A_UINT16 psPollNum, A_UINT16 dtimPolicy)
72815 +{
72816 +    void *osbuf;
72817 +    WMI_POWER_PARAMS_CMD *pm;
72818 +
72819 +    osbuf = A_NETBUF_ALLOC(sizeof(*pm));
72820 +    if (osbuf == NULL) {
72821 +        return A_NO_MEMORY;
72822 +    }
72823 +
72824 +    A_NETBUF_PUT(osbuf, sizeof(*pm));
72825 +
72826 +    pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
72827 +    A_MEMZERO(pm, sizeof(*pm));
72828 +    pm->idle_period   = idlePeriod;
72829 +    pm->pspoll_number = psPollNum;
72830 +    pm->dtim_policy   = dtimPolicy;
72831 +
72832 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID,
72833 +                         NO_SYNC_WMIFLAG));
72834 +}
72835 +
72836 +A_STATUS
72837 +wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout)
72838 +{
72839 +    void *osbuf;
72840 +    WMI_DISC_TIMEOUT_CMD *cmd;
72841 +
72842 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72843 +    if (osbuf == NULL) {
72844 +        return A_NO_MEMORY;
72845 +    }
72846 +
72847 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72848 +
72849 +    cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf));
72850 +    A_MEMZERO(cmd, sizeof(*cmd));
72851 +    cmd->disconnectTimeout = timeout;
72852 +
72853 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID,
72854 +                         NO_SYNC_WMIFLAG));
72855 +}
72856 +
72857 +A_STATUS
72858 +wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType,
72859 +               A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC,
72860 +               A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl,
72861 +               WMI_SYNC_FLAG sync_flag)
72862 +{
72863 +    void *osbuf;
72864 +    WMI_ADD_CIPHER_KEY_CMD *cmd;
72865 +
72866 +    if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
72867 +        (keyMaterial == NULL))
72868 +    {
72869 +        return A_EINVAL;
72870 +    }
72871 +
72872 +    if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
72873 +        return A_EINVAL;
72874 +    }
72875 +
72876 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72877 +    if (osbuf == NULL) {
72878 +        return A_NO_MEMORY;
72879 +    }
72880 +
72881 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72882 +
72883 +    cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
72884 +    A_MEMZERO(cmd, sizeof(*cmd));
72885 +    cmd->keyIndex = keyIndex;
72886 +    cmd->keyType  = keyType;
72887 +    cmd->keyUsage = keyUsage;
72888 +    cmd->keyLength = keyLength;
72889 +    A_MEMCPY(cmd->key, keyMaterial, keyLength);
72890 +    if (NULL != keyRSC) {
72891 +        A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
72892 +    }
72893 +    cmd->key_op_ctrl = key_op_ctrl;
72894 +
72895 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
72896 +}
72897 +
72898 +A_STATUS
72899 +wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk)
72900 +{
72901 +    void *osbuf;
72902 +    WMI_ADD_KRK_CMD *cmd;
72903 +
72904 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72905 +
72906 +    if (osbuf == NULL) {
72907 +        return A_NO_MEMORY;
72908 +    }
72909 +
72910 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72911 +
72912 +    cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf));
72913 +    A_MEMZERO(cmd, sizeof(*cmd));
72914 +    A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
72915 +
72916 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
72917 +}
72918 +
72919 +A_STATUS
72920 +wmi_delete_krk_cmd(struct wmi_t *wmip)
72921 +{
72922 +    void *osbuf;
72923 +
72924 +    osbuf = A_NETBUF_ALLOC(0);
72925 +
72926 +    if (osbuf == NULL) {
72927 +        return A_NO_MEMORY;
72928 +    }
72929 +
72930 +    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_KRK_CMDID, NO_SYNC_WMIFLAG));
72931 +}
72932 +
72933 +A_STATUS
72934 +wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex)
72935 +{
72936 +    void *osbuf;
72937 +    WMI_DELETE_CIPHER_KEY_CMD *cmd;
72938 +
72939 +    if (keyIndex > WMI_MAX_KEY_INDEX) {
72940 +        return A_EINVAL;
72941 +    }
72942 +
72943 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72944 +    if (osbuf == NULL) {
72945 +        return A_NO_MEMORY;
72946 +    }
72947 +
72948 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72949 +
72950 +    cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
72951 +    A_MEMZERO(cmd, sizeof(*cmd));
72952 +    cmd->keyIndex = keyIndex;
72953 +
72954 +    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID,
72955 +                         NO_SYNC_WMIFLAG));
72956 +}
72957 +
72958 +A_STATUS
72959 +wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
72960 +                 A_BOOL set)
72961 +{
72962 +    void *osbuf;
72963 +    WMI_SET_PMKID_CMD *cmd;
72964 +
72965 +    if (bssid == NULL) {
72966 +        return A_EINVAL;
72967 +    }
72968 +
72969 +    if ((set == TRUE) && (pmkId == NULL)) {
72970 +        return A_EINVAL;
72971 +    }
72972 +
72973 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
72974 +    if (osbuf == NULL) {
72975 +        return A_NO_MEMORY;
72976 +    }
72977 +
72978 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
72979 +
72980 +    cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf));
72981 +    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
72982 +    if (set == TRUE) {
72983 +        A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
72984 +        cmd->enable = PMKID_ENABLE;
72985 +    } else {
72986 +        A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
72987 +        cmd->enable = PMKID_DISABLE;
72988 +    }
72989 +
72990 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
72991 +}
72992 +
72993 +A_STATUS
72994 +wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en)
72995 +{
72996 +    void *osbuf;
72997 +    WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
72998 +
72999 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73000 +    if (osbuf == NULL) {
73001 +        return A_NO_MEMORY;
73002 +    }
73003 +
73004 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73005 +
73006 +    cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf));
73007 +    cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
73008 +
73009 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
73010 +            NO_SYNC_WMIFLAG));
73011 +}
73012 +
73013 +A_STATUS
73014 +wmi_set_akmp_params_cmd(struct wmi_t *wmip,
73015 +                        WMI_SET_AKMP_PARAMS_CMD *akmpParams)
73016 +{
73017 +    void *osbuf;
73018 +    WMI_SET_AKMP_PARAMS_CMD *cmd;
73019 +
73020 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73021 +    if (osbuf == NULL) {
73022 +        return A_NO_MEMORY;
73023 +    }
73024 +
73025 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73026 +    cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73027 +    cmd->akmpInfo = akmpParams->akmpInfo;
73028 +
73029 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID,
73030 +            NO_SYNC_WMIFLAG));
73031 +}
73032 +
73033 +A_STATUS
73034 +wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
73035 +                       WMI_SET_PMKID_LIST_CMD *pmkInfo)
73036 +{
73037 +    void *osbuf;
73038 +    WMI_SET_PMKID_LIST_CMD *cmd;
73039 +    A_UINT16 cmdLen;
73040 +    A_UINT8 i;
73041 +
73042 +    cmdLen = sizeof(pmkInfo->numPMKID) +
73043 +             pmkInfo->numPMKID * sizeof(WMI_PMKID);
73044 +
73045 +    osbuf = A_NETBUF_ALLOC(cmdLen);
73046 +
73047 +    if (osbuf == NULL) {
73048 +        return A_NO_MEMORY;
73049 +    }
73050 +
73051 +    A_NETBUF_PUT(osbuf, cmdLen);
73052 +    cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf));
73053 +    cmd->numPMKID = pmkInfo->numPMKID;
73054 +
73055 +    for (i = 0; i < cmd->numPMKID; i++) {
73056 +        A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i],
73057 +                 WMI_PMKID_LEN);
73058 +    }
73059 +
73060 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID,
73061 +            NO_SYNC_WMIFLAG));
73062 +}
73063 +
73064 +A_STATUS
73065 +wmi_get_pmkid_list_cmd(struct wmi_t *wmip)
73066 +{
73067 +    void *osbuf;
73068 +
73069 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73070 +    if (osbuf == NULL) {
73071 +        return A_NO_MEMORY;
73072 +    }
73073 +
73074 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_PMKID_LIST_CMDID,
73075 +                         NO_SYNC_WMIFLAG));
73076 +}
73077 +
73078 +A_STATUS
73079 +wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, WMI_PRI_STREAM_ID streamID)
73080 +{
73081 +    WMI_DATA_HDR     *dtHdr;
73082 +
73083 +    A_ASSERT(streamID != WMI_CONTROL_PRI);
73084 +    A_ASSERT(osbuf != NULL);
73085 +
73086 +    if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
73087 +        return A_NO_MEMORY;
73088 +    }
73089 +
73090 +    dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
73091 +    dtHdr->info =
73092 +      (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
73093 +
73094 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - streamID %d\n", DBGARG, streamID));
73095 +
73096 +    return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, streamID));
73097 +}
73098 +
73099 +typedef struct _WMI_DATA_SYNC_BUFS {
73100 +    A_UINT8            trafficClass;
73101 +    void               *osbuf;
73102 +}WMI_DATA_SYNC_BUFS;
73103 +
73104 +static A_STATUS
73105 +wmi_sync_point(struct wmi_t *wmip)
73106 +{
73107 +       void *cmd_osbuf;
73108 +    WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC];
73109 +       A_UINT8 i,numPriStreams=0;
73110 +       A_STATUS status;
73111 +
73112 +       A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
73113 +
73114 +    memset(dataSyncBufs,0,sizeof(dataSyncBufs));
73115 +
73116 +    /* lock out while we walk through the priority list and assemble our local array */
73117 +    LOCK_WMI(wmip);
73118 +
73119 +    for (i=0; i < WMM_NUM_AC ; i++) {
73120 +               if (wmip->wmi_fatPipeExists & (1 << i)) {
73121 +            numPriStreams++;
73122 +            dataSyncBufs[numPriStreams-1].trafficClass = i;
73123 +        }
73124 +    }
73125 +
73126 +    UNLOCK_WMI(wmip);
73127 +
73128 +    /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */
73129 +
73130 +    do {
73131 +           /*
73132 +            * We allocate all network buffers needed so we will be able to
73133 +            * send all required frames.
73134 +            */
73135 +           cmd_osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73136 +           if (cmd_osbuf == NULL) {
73137 +                   status = A_NO_MEMORY;
73138 +            break;
73139 +           }
73140 +
73141 +           for (i=0; i < numPriStreams ; i++) {
73142 +               dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0);
73143 +            if (dataSyncBufs[i].osbuf == NULL) {
73144 +                status = A_NO_MEMORY;
73145 +                break;
73146 +            }
73147 +           } //end for
73148 +
73149 +           /*
73150 +            * Send sync cmd followed by sync data messages on all endpoints being
73151 +            * used
73152 +            */
73153 +           status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID,
73154 +                                                 NO_SYNC_WMIFLAG);
73155 +
73156 +        if (A_FAILED(status)) {
73157 +            break;
73158 +        }
73159 +            /* cmd buffer sent, we no longer own it */
73160 +        cmd_osbuf = NULL;
73161 +
73162 +               for(i=0; i < numPriStreams; i++) {
73163 +            A_ASSERT(dataSyncBufs[i].osbuf != NULL);
73164 +
73165 +            status = wmi_dataSync_send(wmip, dataSyncBufs[i].osbuf,
73166 +                        WMI_ACCESSCATEGORY_WMISTREAM(wmip,dataSyncBufs[i].trafficClass));
73167 +
73168 +            if (A_FAILED(status)) {
73169 +                break;
73170 +            }
73171 +            /* we don't own this buffer anymore, NULL it out of the array so it
73172 +             * won't get cleaned up */
73173 +            dataSyncBufs[i].osbuf = NULL;
73174 +               } //end for
73175 +
73176 +    } while(FALSE);
73177 +
73178 +    /* free up any resources left over (possibly due to an error) */
73179 +
73180 +    if (cmd_osbuf != NULL) {
73181 +        A_NETBUF_FREE(cmd_osbuf);
73182 +    }
73183 +
73184 +    for (i = 0; i < numPriStreams; i++) {
73185 +        if (dataSyncBufs[i].osbuf != NULL) {
73186 +            A_NETBUF_FREE(dataSyncBufs[i].osbuf);
73187 +        }
73188 +    }
73189 +
73190 +       return (status);
73191 +}
73192 +
73193 +A_STATUS
73194 +wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params)
73195 +{
73196 +    void *osbuf;
73197 +    WMI_CREATE_PSTREAM_CMD *cmd;
73198 +       A_UINT16 activeTsids=0;
73199 +    A_UINT8 fatPipeExistsForAC=0;
73200 +
73201 +    /* Validate all the parameters. */
73202 +    if( !((params->userPriority < 8) &&
73203 +         (params->userPriority <= 0x7) &&
73204 +         (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass)  &&
73205 +         (params->trafficDirection == UPLINK_TRAFFIC ||
73206 +            params->trafficDirection == DNLINK_TRAFFIC ||
73207 +            params->trafficDirection == BIDIR_TRAFFIC) &&
73208 +         (params->trafficType == TRAFFIC_TYPE_APERIODIC ||
73209 +            params->trafficType == TRAFFIC_TYPE_PERIODIC ) &&
73210 +         (params->voicePSCapability == DISABLE_FOR_THIS_AC  ||
73211 +            params->voicePSCapability == ENABLE_FOR_THIS_AC ||
73212 +            params->voicePSCapability == ENABLE_FOR_ALL_AC) &&
73213 +         (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) )
73214 +    {
73215 +        return  A_EINVAL;
73216 +    }
73217 +
73218 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73219 +    if (osbuf == NULL) {
73220 +        return A_NO_MEMORY;
73221 +    }
73222 +
73223 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73224 +
73225 +    A_DPRINTF(DBG_WMI,
73226 +        (DBGFMT "Sending create_pstream_cmd: ac=%d    tsid:%d\n", DBGARG,
73227 +        params->trafficClass, params->tsid));
73228 +
73229 +    cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
73230 +    A_MEMZERO(cmd, sizeof(*cmd));
73231 +    A_MEMCPY(cmd, params, sizeof(*cmd));
73232 +
73233 +        /* this is an implicitly created Fat pipe */
73234 +    if (params->tsid == WMI_IMPLICIT_PSTREAM) {
73235 +        LOCK_WMI(wmip);
73236 +        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
73237 +        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
73238 +        UNLOCK_WMI(wmip);
73239 +    } else {
73240 +            /* this is an explicitly created thin stream within a fat pipe */
73241 +        LOCK_WMI(wmip);
73242 +        fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
73243 +        activeTsids = wmip->wmi_streamExistsForAC[params->trafficClass];
73244 +        wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<<params->tsid);
73245 +            /* if a thinstream becomes active, the fat pipe automatically
73246 +            * becomes active
73247 +            */
73248 +        wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
73249 +        UNLOCK_WMI(wmip);
73250 +    }
73251 +
73252 +        /* Indicate activty change to driver layer only if this is the
73253 +         * first TSID to get created in this AC explicitly or an implicit
73254 +         * fat pipe is getting created.
73255 +         */
73256 +    if (!fatPipeExistsForAC) {
73257 +        A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass);
73258 +    }
73259 +
73260 +    /* mike: should be SYNC_BEFORE_WMIFLAG */
73261 +    return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID,
73262 +                         NO_SYNC_WMIFLAG));
73263 +}
73264 +
73265 +A_STATUS
73266 +wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid)
73267 +{
73268 +    void *osbuf;
73269 +    WMI_DELETE_PSTREAM_CMD *cmd;
73270 +    A_STATUS status;
73271 +       A_UINT16 activeTsids=0;
73272 +
73273 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73274 +    if (osbuf == NULL) {
73275 +        return A_NO_MEMORY;
73276 +    }
73277 +
73278 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73279 +
73280 +    cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
73281 +    A_MEMZERO(cmd, sizeof(*cmd));
73282 +
73283 +    cmd->trafficClass = trafficClass;
73284 +    cmd->tsid = tsid;
73285 +
73286 +    LOCK_WMI(wmip);
73287 +    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
73288 +    UNLOCK_WMI(wmip);
73289 +
73290 +        /* Check if the tsid was created & exists */
73291 +    if (!(activeTsids & (1<<tsid))) {
73292 +
73293 +        A_DPRINTF(DBG_WMI,
73294 +        (DBGFMT "TSID %d does'nt exist for trafficClass: %d\n", DBGARG, tsid, trafficClass));
73295 +            /* TODO: return a more appropriate err code */
73296 +        return A_ERROR;
73297 +    }
73298 +
73299 +    A_DPRINTF(DBG_WMI,
73300 +        (DBGFMT "Sending delete_pstream_cmd: trafficClass: %d tsid=%d\n", DBGARG, trafficClass, tsid));
73301 +
73302 +    status = (wmi_cmd_send(wmip, osbuf, WMI_DELETE_PSTREAM_CMDID,
73303 +                         SYNC_BEFORE_WMIFLAG));
73304 +
73305 +    LOCK_WMI(wmip);
73306 +    wmip->wmi_streamExistsForAC[trafficClass] &= ~(1<<tsid);
73307 +    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
73308 +    UNLOCK_WMI(wmip);
73309 +
73310 +
73311 +        /* Indicate stream inactivity to driver layer only if all tsids
73312 +         * within this AC are deleted.
73313 +         */
73314 +    if(!activeTsids) {
73315 +        A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass);
73316 +        wmip->wmi_fatPipeExists &= ~(1<<trafficClass);
73317 +    }
73318 +
73319 +    return status;
73320 +}
73321 +
73322 +/*
73323 + * used to set the bit rate.  rate is in Kbps.  If rate == -1
73324 + * then auto selection is used.
73325 + */
73326 +A_STATUS
73327 +wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate)
73328 +{
73329 +    void *osbuf;
73330 +    WMI_BIT_RATE_CMD *cmd;
73331 +    A_INT8 index;
73332 +
73333 +    if (rate != -1) {
73334 +        index = wmi_validate_bitrate(wmip, rate);
73335 +        if(index == A_EINVAL){
73336 +            return A_EINVAL;
73337 +        }
73338 +    } else {
73339 +        index = -1;
73340 +    }
73341 +
73342 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73343 +    if (osbuf == NULL) {
73344 +        return A_NO_MEMORY;
73345 +    }
73346 +
73347 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73348 +
73349 +    cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf));
73350 +    A_MEMZERO(cmd, sizeof(*cmd));
73351 +
73352 +    cmd->rateIndex = index;
73353 +
73354 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
73355 +}
73356 +
73357 +A_STATUS
73358 +wmi_get_bitrate_cmd(struct wmi_t *wmip)
73359 +{
73360 +    void *osbuf;
73361 +
73362 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73363 +    if (osbuf == NULL) {
73364 +        return A_NO_MEMORY;
73365 +    }
73366 +
73367 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
73368 +}
73369 +
73370 +/*
73371 + * Returns TRUE iff the given rate index is legal in the current PHY mode.
73372 + */
73373 +A_BOOL
73374 +wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_UINT32 rateIndex)
73375 +{
73376 +    WMI_PHY_MODE phyMode = wmip->wmi_phyMode;
73377 +    A_BOOL isValid = TRUE;
73378 +    switch(phyMode) {
73379 +        case WMI_11A_MODE:
73380 +            if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) {
73381 +                isValid = FALSE;
73382 +            }
73383 +            break;
73384 +
73385 +        case WMI_11B_MODE:
73386 +            if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) {
73387 +                isValid = FALSE;
73388 +            }
73389 +            break;
73390 +
73391 +        case WMI_11GONLY_MODE:
73392 +            if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) {
73393 +                isValid = FALSE;
73394 +            }
73395 +            break;
73396 +
73397 +        case WMI_11G_MODE:
73398 +        case WMI_11AG_MODE:
73399 +            if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) {
73400 +                isValid = FALSE;
73401 +            }
73402 +            break;
73403 +
73404 +        default:
73405 +            A_ASSERT(FALSE);
73406 +            break;
73407 +    }
73408 +
73409 +    return isValid;
73410 +}
73411 +
73412 +A_INT8
73413 +wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate)
73414 +{
73415 +    A_INT8 i;
73416 +    if (rate != -1)
73417 +    {
73418 +        for (i=0;;i++)
73419 +        {
73420 +            if (wmi_rateTable[(A_UINT32) i] == 0) {
73421 +                return A_EINVAL;
73422 +            }
73423 +            if (wmi_rateTable[(A_UINT32) i] == rate) {
73424 +                break;
73425 +            }
73426 +        }
73427 +    }
73428 +    else{
73429 +     i = -1;
73430 +    }
73431 +
73432 +    if(wmi_is_bitrate_index_valid(wmip, i) != TRUE) {
73433 +        return A_EINVAL;
73434 +    }
73435 +
73436 +    return i;
73437 +}
73438 +
73439 +A_STATUS
73440 +wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask)
73441 +{
73442 +    void *osbuf;
73443 +    WMI_FIX_RATES_CMD *cmd;
73444 +    A_UINT32 rateIndex;
73445 +
73446 +    /* Make sure all rates in the mask are valid in the current PHY mode */
73447 +    for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) {
73448 +       if((1 << rateIndex) & (A_UINT32)fixRatesMask) {
73449 +            if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) {
73450 +                A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG));
73451 +                return A_EINVAL;
73452 +            }
73453 +       }
73454 +    }
73455 +
73456 +
73457 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73458 +    if (osbuf == NULL) {
73459 +        return A_NO_MEMORY;
73460 +    }
73461 +
73462 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73463 +
73464 +    cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf));
73465 +    A_MEMZERO(cmd, sizeof(*cmd));
73466 +
73467 +    cmd->fixRateMask = fixRatesMask;
73468 +
73469 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
73470 +}
73471 +
73472 +A_STATUS
73473 +wmi_get_ratemask_cmd(struct wmi_t *wmip)
73474 +{
73475 +    void *osbuf;
73476 +
73477 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73478 +    if (osbuf == NULL) {
73479 +        return A_NO_MEMORY;
73480 +    }
73481 +
73482 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
73483 +}
73484 +
73485 +A_STATUS
73486 +wmi_get_channelList_cmd(struct wmi_t *wmip)
73487 +{
73488 +    void *osbuf;
73489 +
73490 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73491 +    if (osbuf == NULL) {
73492 +        return A_NO_MEMORY;
73493 +    }
73494 +
73495 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_CHANNEL_LIST_CMDID,
73496 +                         NO_SYNC_WMIFLAG));
73497 +}
73498 +
73499 +/*
73500 + * used to generate a wmi sey channel Parameters cmd.
73501 + * mode should always be specified and corresponds to the phy mode of the
73502 + * wlan.
73503 + * numChan should alway sbe specified. If zero indicates that all available
73504 + * channels should be used.
73505 + * channelList is an array of channel frequencies (in Mhz) which the radio
73506 + * should limit its operation to.  It should be NULL if numChan == 0.  Size of
73507 + * array should correspond to numChan entries.
73508 + */
73509 +A_STATUS
73510 +wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
73511 +                          WMI_PHY_MODE mode, A_INT8 numChan,
73512 +                          A_UINT16 *channelList)
73513 +{
73514 +    void *osbuf;
73515 +    WMI_CHANNEL_PARAMS_CMD *cmd;
73516 +    A_INT8 size;
73517 +
73518 +    size = sizeof (*cmd);
73519 +
73520 +    if (numChan) {
73521 +        if (numChan > WMI_MAX_CHANNELS) {
73522 +            return A_EINVAL;
73523 +        }
73524 +        size += sizeof(A_UINT16) * (numChan - 1);
73525 +    }
73526 +
73527 +    osbuf = A_NETBUF_ALLOC(size);
73528 +    if (osbuf == NULL) {
73529 +        return A_NO_MEMORY;
73530 +    }
73531 +
73532 +    A_NETBUF_PUT(osbuf, size);
73533 +
73534 +    cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73535 +    A_MEMZERO(cmd, size);
73536 +
73537 +    wmip->wmi_phyMode = mode;
73538 +    cmd->scanParam   = scanParam;
73539 +    cmd->phyMode     = mode;
73540 +    cmd->numChannels = numChan;
73541 +    A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16));
73542 +
73543 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID,
73544 +                         NO_SYNC_WMIFLAG));
73545 +}
73546 +
73547 +A_STATUS
73548 +wmi_set_rssi_threshold_params(struct wmi_t *wmip,
73549 +                              WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
73550 +{
73551 +    void    *osbuf;
73552 +    A_INT8  size;
73553 +    WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
73554 +    /* These values are in ascending order */
73555 +    if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val ||
73556 +        rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val ||
73557 +        rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val ||
73558 +        rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val ||
73559 +        rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val ||
73560 +        rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val ||
73561 +        rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val ||
73562 +        rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val ||
73563 +        rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val ||
73564 +        rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) {
73565 +
73566 +        return A_EINVAL;
73567 +    }
73568 +
73569 +    size = sizeof (*cmd);
73570 +
73571 +    osbuf = A_NETBUF_ALLOC(size);
73572 +    if (osbuf == NULL) {
73573 +        return A_NO_MEMORY;
73574 +    }
73575 +
73576 +    A_NETBUF_PUT(osbuf, size);
73577 +
73578 +    cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73579 +    A_MEMZERO(cmd, size);
73580 +    A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD));
73581 +
73582 +    return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
73583 +                            NO_SYNC_WMIFLAG));
73584 +}
73585 +
73586 +A_STATUS
73587 +wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip,
73588 +                              WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd)
73589 +{
73590 +    void    *osbuf;
73591 +    A_INT8  size;
73592 +    WMI_SET_HOST_SLEEP_MODE_CMD *cmd;
73593 +
73594 +    if( hostModeCmd->awake == hostModeCmd->asleep) {
73595 +        return A_EINVAL;
73596 +    }
73597 +
73598 +    size = sizeof (*cmd);
73599 +
73600 +    osbuf = A_NETBUF_ALLOC(size);
73601 +    if (osbuf == NULL) {
73602 +        return A_NO_MEMORY;
73603 +    }
73604 +
73605 +    A_NETBUF_PUT(osbuf, size);
73606 +
73607 +    cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf));
73608 +    A_MEMZERO(cmd, size);
73609 +    A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD));
73610 +
73611 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID,
73612 +                            NO_SYNC_WMIFLAG));
73613 +}
73614 +
73615 +A_STATUS
73616 +wmi_set_wow_mode_cmd(struct wmi_t *wmip,
73617 +                              WMI_SET_WOW_MODE_CMD *wowModeCmd)
73618 +{
73619 +    void    *osbuf;
73620 +    A_INT8  size;
73621 +    WMI_SET_WOW_MODE_CMD *cmd;
73622 +
73623 +    size = sizeof (*cmd);
73624 +
73625 +    osbuf = A_NETBUF_ALLOC(size);
73626 +    if (osbuf == NULL) {
73627 +        return A_NO_MEMORY;
73628 +    }
73629 +
73630 +    A_NETBUF_PUT(osbuf, size);
73631 +
73632 +    cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf));
73633 +    A_MEMZERO(cmd, size);
73634 +    A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD));
73635 +
73636 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID,
73637 +                            NO_SYNC_WMIFLAG));
73638 +
73639 +}
73640 +
73641 +A_STATUS
73642 +wmi_get_wow_list_cmd(struct wmi_t *wmip,
73643 +                              WMI_GET_WOW_LIST_CMD *wowListCmd)
73644 +{
73645 +    void    *osbuf;
73646 +    A_INT8  size;
73647 +    WMI_GET_WOW_LIST_CMD *cmd;
73648 +
73649 +    size = sizeof (*cmd);
73650 +
73651 +    osbuf = A_NETBUF_ALLOC(size);
73652 +    if (osbuf == NULL) {
73653 +        return A_NO_MEMORY;
73654 +    }
73655 +
73656 +    A_NETBUF_PUT(osbuf, size);
73657 +
73658 +    cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf));
73659 +    A_MEMZERO(cmd, size);
73660 +    A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD));
73661 +
73662 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID,
73663 +                            NO_SYNC_WMIFLAG));
73664 +
73665 +}
73666 +
73667 +static A_STATUS
73668 +wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
73669 +{
73670 +    WMI_GET_WOW_LIST_REPLY *reply;
73671 +
73672 +    if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) {
73673 +        return A_EINVAL;
73674 +    }
73675 +    reply = (WMI_GET_WOW_LIST_REPLY *)datap;
73676 +
73677 +    A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters,
73678 +                          reply);
73679 +
73680 +    return A_OK;
73681 +}
73682 +
73683 +A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
73684 +                                 WMI_ADD_WOW_PATTERN_CMD *addWowCmd,
73685 +                                 A_UINT8* pattern, A_UINT8* mask,
73686 +                                 A_UINT8 pattern_size)
73687 +{
73688 +    void    *osbuf;
73689 +    A_INT8  size;
73690 +    WMI_ADD_WOW_PATTERN_CMD *cmd;
73691 +    A_UINT8 *filter_mask = NULL;
73692 +
73693 +    size = sizeof (*cmd);
73694 +
73695 +    size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8));
73696 +    osbuf = A_NETBUF_ALLOC(size);
73697 +    if (osbuf == NULL) {
73698 +        return A_NO_MEMORY;
73699 +    }
73700 +
73701 +    A_NETBUF_PUT(osbuf, size);
73702 +
73703 +    cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
73704 +    cmd->filter_list_id = addWowCmd->filter_list_id;
73705 +    cmd->filter_offset = addWowCmd->filter_offset;
73706 +    cmd->filter_size = addWowCmd->filter_size;
73707 +
73708 +    A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size);
73709 +
73710 +    filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size);
73711 +    A_MEMCPY(filter_mask, mask, addWowCmd->filter_size);
73712 +
73713 +
73714 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID,
73715 +                            NO_SYNC_WMIFLAG));
73716 +}
73717 +
73718 +A_STATUS
73719 +wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
73720 +                              WMI_DEL_WOW_PATTERN_CMD *delWowCmd)
73721 +{
73722 +    void    *osbuf;
73723 +    A_INT8  size;
73724 +    WMI_DEL_WOW_PATTERN_CMD *cmd;
73725 +
73726 +    size = sizeof (*cmd);
73727 +
73728 +    osbuf = A_NETBUF_ALLOC(size);
73729 +    if (osbuf == NULL) {
73730 +        return A_NO_MEMORY;
73731 +    }
73732 +
73733 +    A_NETBUF_PUT(osbuf, size);
73734 +
73735 +    cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
73736 +    A_MEMZERO(cmd, size);
73737 +    A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD));
73738 +
73739 +    return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID,
73740 +                            NO_SYNC_WMIFLAG));
73741 +
73742 +}
73743 +
73744 +A_STATUS
73745 +wmi_set_snr_threshold_params(struct wmi_t *wmip,
73746 +                             WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
73747 +{
73748 +    void    *osbuf;
73749 +    A_INT8  size;
73750 +    WMI_SNR_THRESHOLD_PARAMS_CMD *cmd;
73751 +    /* These values are in ascending order */
73752 +    if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val ||
73753 +        snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val ||
73754 +        snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val ||
73755 +        snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val ||
73756 +        snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val ||
73757 +        snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) {
73758 +
73759 +        return A_EINVAL;
73760 +    }
73761 +
73762 +    size = sizeof (*cmd);
73763 +
73764 +    osbuf = A_NETBUF_ALLOC(size);
73765 +    if (osbuf == NULL) {
73766 +        return A_NO_MEMORY;
73767 +    }
73768 +
73769 +    A_NETBUF_PUT(osbuf, size);
73770 +
73771 +    cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73772 +    A_MEMZERO(cmd, size);
73773 +    A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD));
73774 +
73775 +    return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID,
73776 +                            NO_SYNC_WMIFLAG));
73777 +}
73778 +
73779 +A_STATUS
73780 +wmi_clr_rssi_snr(struct wmi_t *wmip)
73781 +{
73782 +    void    *osbuf;
73783 +
73784 +    osbuf = A_NETBUF_ALLOC(sizeof(int));
73785 +    if (osbuf == NULL) {
73786 +        return A_NO_MEMORY;
73787 +    }
73788 +
73789 +    return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID,
73790 +                            NO_SYNC_WMIFLAG));
73791 +}
73792 +
73793 +A_STATUS
73794 +wmi_set_lq_threshold_params(struct wmi_t *wmip,
73795 +                             WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd)
73796 +{
73797 +    void    *osbuf;
73798 +    A_INT8  size;
73799 +    WMI_LQ_THRESHOLD_PARAMS_CMD *cmd;
73800 +    /* These values are in ascending order */
73801 +    if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val ||
73802 +        lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val ||
73803 +        lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val ||
73804 +        lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val ||
73805 +        lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val ||
73806 +        lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) {
73807 +
73808 +        return A_EINVAL;
73809 +    }
73810 +
73811 +    size = sizeof (*cmd);
73812 +
73813 +    osbuf = A_NETBUF_ALLOC(size);
73814 +    if (osbuf == NULL) {
73815 +        return A_NO_MEMORY;
73816 +    }
73817 +
73818 +    A_NETBUF_PUT(osbuf, size);
73819 +
73820 +    cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
73821 +    A_MEMZERO(cmd, size);
73822 +    A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD));
73823 +
73824 +    return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID,
73825 +                            NO_SYNC_WMIFLAG));
73826 +}
73827 +
73828 +A_STATUS
73829 +wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask)
73830 +{
73831 +    void    *osbuf;
73832 +    A_INT8  size;
73833 +    WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
73834 +
73835 +    size = sizeof (*cmd);
73836 +
73837 +    osbuf = A_NETBUF_ALLOC(size);
73838 +    if (osbuf == NULL) {
73839 +        return A_NO_MEMORY;
73840 +    }
73841 +
73842 +    A_NETBUF_PUT(osbuf, size);
73843 +
73844 +    cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf));
73845 +    A_MEMZERO(cmd, size);
73846 +
73847 +    cmd->bitmask = mask;
73848 +
73849 +    return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
73850 +                            NO_SYNC_WMIFLAG));
73851 +}
73852 +
73853 +A_STATUS
73854 +wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source)
73855 +{
73856 +    void *osbuf;
73857 +    WMIX_HB_CHALLENGE_RESP_CMD *cmd;
73858 +
73859 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73860 +    if (osbuf == NULL) {
73861 +        return A_NO_MEMORY;
73862 +    }
73863 +
73864 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73865 +
73866 +    cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf));
73867 +    cmd->cookie = cookie;
73868 +    cmd->source = source;
73869 +
73870 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID,
73871 +                              NO_SYNC_WMIFLAG));
73872 +}
73873 +
73874 +A_STATUS
73875 +wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
73876 +                            A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
73877 +                            A_UINT32 valid)
73878 +{
73879 +    void *osbuf;
73880 +    WMIX_DBGLOG_CFG_MODULE_CMD *cmd;
73881 +
73882 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73883 +    if (osbuf == NULL) {
73884 +        return A_NO_MEMORY;
73885 +    }
73886 +
73887 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73888 +
73889 +    cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf));
73890 +    cmd->config.cfgmmask = mmask;
73891 +    cmd->config.cfgtsr = tsr;
73892 +    cmd->config.cfgrep = rep;
73893 +    cmd->config.cfgsize = size;
73894 +    cmd->config.cfgvalid = valid;
73895 +
73896 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID,
73897 +                              NO_SYNC_WMIFLAG));
73898 +}
73899 +
73900 +A_STATUS
73901 +wmi_get_stats_cmd(struct wmi_t *wmip)
73902 +{
73903 +    void *osbuf;
73904 +
73905 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73906 +    if (osbuf == NULL) {
73907 +        return A_NO_MEMORY;
73908 +    }
73909 +
73910 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_STATISTICS_CMDID,
73911 +                         NO_SYNC_WMIFLAG));
73912 +}
73913 +
73914 +A_STATUS
73915 +wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid)
73916 +{
73917 +    void *osbuf;
73918 +    WMI_ADD_BAD_AP_CMD *cmd;
73919 +
73920 +    if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
73921 +        return A_EINVAL;
73922 +    }
73923 +
73924 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73925 +    if (osbuf == NULL) {
73926 +        return A_NO_MEMORY;
73927 +    }
73928 +
73929 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73930 +
73931 +    cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
73932 +    cmd->badApIndex = apIndex;
73933 +    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
73934 +
73935 +    return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, NO_SYNC_WMIFLAG));
73936 +}
73937 +
73938 +A_STATUS
73939 +wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex)
73940 +{
73941 +    void *osbuf;
73942 +    WMI_DELETE_BAD_AP_CMD *cmd;
73943 +
73944 +    if (apIndex > WMI_MAX_BAD_AP_INDEX) {
73945 +        return A_EINVAL;
73946 +    }
73947 +
73948 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73949 +    if (osbuf == NULL) {
73950 +        return A_NO_MEMORY;
73951 +    }
73952 +
73953 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73954 +
73955 +    cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
73956 +    cmd->badApIndex = apIndex;
73957 +
73958 +    return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID,
73959 +                         NO_SYNC_WMIFLAG));
73960 +}
73961 +
73962 +A_STATUS
73963 +wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM)
73964 +{
73965 +    void *osbuf;
73966 +    WMI_SET_TX_PWR_CMD *cmd;
73967 +
73968 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
73969 +    if (osbuf == NULL) {
73970 +        return A_NO_MEMORY;
73971 +    }
73972 +
73973 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
73974 +
73975 +    cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf));
73976 +    cmd->dbM = dbM;
73977 +
73978 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
73979 +}
73980 +
73981 +A_STATUS
73982 +wmi_get_txPwr_cmd(struct wmi_t *wmip)
73983 +{
73984 +    void *osbuf;
73985 +
73986 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
73987 +    if (osbuf == NULL) {
73988 +        return A_NO_MEMORY;
73989 +    }
73990 +
73991 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
73992 +}
73993 +
73994 +A_STATUS
73995 +wmi_switch_radio(struct wmi_t *wmip, A_UINT8 on)
73996 +{
73997 +       WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0,
73998 +                                       WMI_SHORTSCANRATIO_DEFAULT,
73999 +                                       DEFAULT_SCAN_CTRL_FLAGS,
74000 +                                       0};
74001 +
74002 +       if (on) {
74003 +               /* Enable foreground scanning */
74004 +                if (wmi_scanparams_cmd(wmip, scParams.fg_start_period,
74005 +                                       scParams.fg_end_period,
74006 +                                       scParams.bg_period,
74007 +                                       scParams.minact_chdwell_time,
74008 +                                       scParams.maxact_chdwell_time,
74009 +                                       scParams.pas_chdwell_time,
74010 +                                       scParams.shortScanRatio,
74011 +                                       scParams.scanCtrlFlags,
74012 +                                       scParams.max_dfsch_act_time) != A_OK) {
74013 +                       return -EIO;
74014 +               }
74015 +       } else {
74016 +               wmi_disconnect_cmd(wmip);
74017 +               if (wmi_scanparams_cmd(wmip, 0xFFFF, 0, 0, 0,
74018 +                                      0, 0, 0, 0xFF, 0) != A_OK) {
74019 +                       return -EIO;
74020 +               }
74021 +       }
74022 +
74023 +       return A_OK;
74024 +}
74025 +
74026 +
74027 +A_UINT16
74028 +wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass)
74029 +{
74030 +       A_UINT16 activeTsids=0;
74031 +
74032 +    LOCK_WMI(wmip);
74033 +    activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
74034 +    UNLOCK_WMI(wmip);
74035 +
74036 +    return activeTsids;
74037 +}
74038 +
74039 +A_STATUS
74040 +wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
74041 +{
74042 +    void *osbuf;
74043 +
74044 +    osbuf = A_NETBUF_ALLOC(0);      /* no payload */
74045 +    if (osbuf == NULL) {
74046 +        return A_NO_MEMORY;
74047 +    }
74048 +
74049 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_TBL_CMDID,
74050 +                         NO_SYNC_WMIFLAG));
74051 +}
74052 +
74053 +A_STATUS
74054 +wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType)
74055 +{
74056 +    void *osbuf;
74057 +    A_UINT32 size = sizeof(A_UINT8);
74058 +    WMI_TARGET_ROAM_DATA *cmd;
74059 +
74060 +    osbuf = A_NETBUF_ALLOC(size);      /* no payload */
74061 +    if (osbuf == NULL) {
74062 +        return A_NO_MEMORY;
74063 +    }
74064 +
74065 +    A_NETBUF_PUT(osbuf, size);
74066 +
74067 +    cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf));
74068 +    cmd->roamDataType = roamDataType;
74069 +
74070 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID,
74071 +                         NO_SYNC_WMIFLAG));
74072 +}
74073 +
74074 +A_STATUS
74075 +wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
74076 +                      A_UINT8 size)
74077 +{
74078 +    void *osbuf;
74079 +    WMI_SET_ROAM_CTRL_CMD *cmd;
74080 +
74081 +    osbuf = A_NETBUF_ALLOC(size);
74082 +    if (osbuf == NULL) {
74083 +        return A_NO_MEMORY;
74084 +    }
74085 +
74086 +    A_NETBUF_PUT(osbuf, size);
74087 +
74088 +    cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf));
74089 +    A_MEMZERO(cmd, size);
74090 +
74091 +    A_MEMCPY(cmd, p, size);
74092 +
74093 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID,
74094 +                         NO_SYNC_WMIFLAG));
74095 +}
74096 +
74097 +A_STATUS
74098 +wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
74099 +                            WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
74100 +                            A_UINT8 size)
74101 +{
74102 +    void *osbuf;
74103 +    WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd;
74104 +
74105 +    /* These timers can't be zero */
74106 +    if(!pCmd->psPollTimeout || !pCmd->triggerTimeout ||
74107 +       !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD ||
74108 +         pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) ||
74109 +       !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD ||
74110 +         pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD))
74111 +        return A_EINVAL;
74112 +
74113 +    osbuf = A_NETBUF_ALLOC(size);
74114 +    if (osbuf == NULL) {
74115 +        return A_NO_MEMORY;
74116 +    }
74117 +
74118 +    A_NETBUF_PUT(osbuf, size);
74119 +
74120 +    cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
74121 +    A_MEMZERO(cmd, size);
74122 +
74123 +    A_MEMCPY(cmd, pCmd, size);
74124 +
74125 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
74126 +                         NO_SYNC_WMIFLAG));
74127 +}
74128 +
74129 +#ifdef CONFIG_HOST_GPIO_SUPPORT
74130 +/* Send a command to Target to change GPIO output pins. */
74131 +A_STATUS
74132 +wmi_gpio_output_set(struct wmi_t *wmip,
74133 +                    A_UINT32 set_mask,
74134 +                    A_UINT32 clear_mask,
74135 +                    A_UINT32 enable_mask,
74136 +                    A_UINT32 disable_mask)
74137 +{
74138 +    void *osbuf;
74139 +    WMIX_GPIO_OUTPUT_SET_CMD *output_set;
74140 +    int size;
74141 +
74142 +    size = sizeof(*output_set);
74143 +
74144 +    A_DPRINTF(DBG_WMI,
74145 +        (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG,
74146 +        set_mask, clear_mask, enable_mask, disable_mask));
74147 +
74148 +    osbuf = A_NETBUF_ALLOC(size);
74149 +    if (osbuf == NULL) {
74150 +        return A_NO_MEMORY;
74151 +    }
74152 +    A_NETBUF_PUT(osbuf, size);
74153 +    output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf));
74154 +
74155 +    output_set->set_mask                   = set_mask;
74156 +    output_set->clear_mask                 = clear_mask;
74157 +    output_set->enable_mask                = enable_mask;
74158 +    output_set->disable_mask               = disable_mask;
74159 +
74160 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
74161 +                             NO_SYNC_WMIFLAG));
74162 +}
74163 +
74164 +/* Send a command to the Target requesting state of the GPIO input pins */
74165 +A_STATUS
74166 +wmi_gpio_input_get(struct wmi_t *wmip)
74167 +{
74168 +    void *osbuf;
74169 +
74170 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
74171 +
74172 +    osbuf = A_NETBUF_ALLOC(0);
74173 +    if (osbuf == NULL) {
74174 +        return A_NO_MEMORY;
74175 +    }
74176 +
74177 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INPUT_GET_CMDID,
74178 +                             NO_SYNC_WMIFLAG));
74179 +}
74180 +
74181 +/* Send a command to the Target that changes the value of a GPIO register. */
74182 +A_STATUS
74183 +wmi_gpio_register_set(struct wmi_t *wmip,
74184 +                      A_UINT32 gpioreg_id,
74185 +                      A_UINT32 value)
74186 +{
74187 +    void *osbuf;
74188 +    WMIX_GPIO_REGISTER_SET_CMD *register_set;
74189 +    int size;
74190 +
74191 +    size = sizeof(*register_set);
74192 +
74193 +    A_DPRINTF(DBG_WMI,
74194 +        (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value));
74195 +
74196 +    osbuf = A_NETBUF_ALLOC(size);
74197 +    if (osbuf == NULL) {
74198 +        return A_NO_MEMORY;
74199 +    }
74200 +    A_NETBUF_PUT(osbuf, size);
74201 +    register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf));
74202 +
74203 +    register_set->gpioreg_id               = gpioreg_id;
74204 +    register_set->value                    = value;
74205 +
74206 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
74207 +                             NO_SYNC_WMIFLAG));
74208 +}
74209 +
74210 +/* Send a command to the Target to fetch the value of a GPIO register. */
74211 +A_STATUS
74212 +wmi_gpio_register_get(struct wmi_t *wmip,
74213 +                      A_UINT32 gpioreg_id)
74214 +{
74215 +    void *osbuf;
74216 +    WMIX_GPIO_REGISTER_GET_CMD *register_get;
74217 +    int size;
74218 +
74219 +    size = sizeof(*register_get);
74220 +
74221 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id));
74222 +
74223 +    osbuf = A_NETBUF_ALLOC(size);
74224 +    if (osbuf == NULL) {
74225 +        return A_NO_MEMORY;
74226 +    }
74227 +    A_NETBUF_PUT(osbuf, size);
74228 +    register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf));
74229 +
74230 +    register_get->gpioreg_id               = gpioreg_id;
74231 +
74232 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
74233 +                             NO_SYNC_WMIFLAG));
74234 +}
74235 +
74236 +/* Send a command to the Target acknowledging some GPIO interrupts. */
74237 +A_STATUS
74238 +wmi_gpio_intr_ack(struct wmi_t *wmip,
74239 +                  A_UINT32 ack_mask)
74240 +{
74241 +    void *osbuf;
74242 +    WMIX_GPIO_INTR_ACK_CMD *intr_ack;
74243 +    int size;
74244 +
74245 +    size = sizeof(*intr_ack);
74246 +
74247 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask));
74248 +
74249 +    osbuf = A_NETBUF_ALLOC(size);
74250 +    if (osbuf == NULL) {
74251 +        return A_NO_MEMORY;
74252 +    }
74253 +    A_NETBUF_PUT(osbuf, size);
74254 +    intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf));
74255 +
74256 +    intr_ack->ack_mask               = ack_mask;
74257 +
74258 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
74259 +                             NO_SYNC_WMIFLAG));
74260 +}
74261 +#endif /* CONFIG_HOST_GPIO_SUPPORT */
74262 +
74263 +A_STATUS
74264 +wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin,
74265 +                          A_UINT8 eCWmax, A_UINT8 aifsn)
74266 +{
74267 +    void *osbuf;
74268 +    WMI_SET_ACCESS_PARAMS_CMD *cmd;
74269 +
74270 +    if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
74271 +        (aifsn > WMI_MAX_AIFSN_ACPARAM))
74272 +    {
74273 +        return A_EINVAL;
74274 +    }
74275 +
74276 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74277 +    if (osbuf == NULL) {
74278 +        return A_NO_MEMORY;
74279 +    }
74280 +
74281 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74282 +
74283 +    cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
74284 +    cmd->txop   = txop;
74285 +    cmd->eCWmin = eCWmin;
74286 +    cmd->eCWmax = eCWmax;
74287 +    cmd->aifsn  = aifsn;
74288 +
74289 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID,
74290 +                         NO_SYNC_WMIFLAG));
74291 +}
74292 +
74293 +A_STATUS
74294 +wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
74295 +                         A_UINT8 trafficClass, A_UINT8 maxRetries,
74296 +                         A_UINT8 enableNotify)
74297 +{
74298 +    void *osbuf;
74299 +    WMI_SET_RETRY_LIMITS_CMD *cmd;
74300 +
74301 +    if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) &&
74302 +        (frameType != DATA_FRAMETYPE))
74303 +    {
74304 +        return A_EINVAL;
74305 +    }
74306 +
74307 +    if (maxRetries > WMI_MAX_RETRIES) {
74308 +        return A_EINVAL;
74309 +    }
74310 +
74311 +    if (frameType != DATA_FRAMETYPE) {
74312 +        trafficClass = 0;
74313 +    }
74314 +
74315 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74316 +    if (osbuf == NULL) {
74317 +        return A_NO_MEMORY;
74318 +    }
74319 +
74320 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74321 +
74322 +    cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf));
74323 +    cmd->frameType    = frameType;
74324 +    cmd->trafficClass = trafficClass;
74325 +    cmd->maxRetries   = maxRetries;
74326 +    cmd->enableNotify = enableNotify;
74327 +
74328 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID,
74329 +                         NO_SYNC_WMIFLAG));
74330 +}
74331 +
74332 +void
74333 +wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid)
74334 +{
74335 +    if (bssid != NULL) {
74336 +        A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
74337 +    }
74338 +}
74339 +
74340 +A_STATUS
74341 +wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode)
74342 +{
74343 +    void *osbuf;
74344 +    WMI_SET_OPT_MODE_CMD *cmd;
74345 +
74346 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74347 +    if (osbuf == NULL) {
74348 +        return A_NO_MEMORY;
74349 +    }
74350 +
74351 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74352 +
74353 +    cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf));
74354 +    A_MEMZERO(cmd, sizeof(*cmd));
74355 +    cmd->optMode = optMode;
74356 +
74357 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID,
74358 +                         SYNC_BOTH_WMIFLAG));
74359 +}
74360 +
74361 +A_STATUS
74362 +wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
74363 +                      A_UINT8 frmType,
74364 +                      A_UINT8 *dstMacAddr,
74365 +                      A_UINT8 *bssid,
74366 +                      A_UINT16 optIEDataLen,
74367 +                      A_UINT8 *optIEData)
74368 +{
74369 +    void *osbuf;
74370 +    WMI_OPT_TX_FRAME_CMD *cmd;
74371 +    osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd));
74372 +    if (osbuf == NULL) {
74373 +        return A_NO_MEMORY;
74374 +    }
74375 +
74376 +    A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd)));
74377 +
74378 +    cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf));
74379 +    A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1));
74380 +
74381 +    cmd->frmType    = frmType;
74382 +    cmd->optIEDataLen   = optIEDataLen;
74383 +    //cmd->optIEData     = (A_UINT8 *)((int)cmd + sizeof(*cmd));
74384 +    A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
74385 +    A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
74386 +    A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen);
74387 +
74388 +    return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID,
74389 +                         NO_SYNC_WMIFLAG));
74390 +}
74391 +
74392 +A_STATUS
74393 +wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl)
74394 +{
74395 +    void *osbuf;
74396 +    WMI_BEACON_INT_CMD *cmd;
74397 +
74398 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74399 +    if (osbuf == NULL) {
74400 +        return A_NO_MEMORY;
74401 +    }
74402 +
74403 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74404 +
74405 +    cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf));
74406 +    A_MEMZERO(cmd, sizeof(*cmd));
74407 +    cmd->beaconInterval = intvl;
74408 +
74409 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID,
74410 +            NO_SYNC_WMIFLAG));
74411 +}
74412 +
74413 +
74414 +A_STATUS
74415 +wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize)
74416 +{
74417 +    void *osbuf;
74418 +    WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
74419 +
74420 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74421 +    if (osbuf == NULL) {
74422 +        return A_NO_MEMORY;
74423 +    }
74424 +
74425 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74426 +
74427 +    cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf));
74428 +    A_MEMZERO(cmd, sizeof(*cmd));
74429 +    cmd->voicePktSize = voicePktSize;
74430 +
74431 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID,
74432 +            NO_SYNC_WMIFLAG));
74433 +}
74434 +
74435 +
74436 +A_STATUS
74437 +wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen)
74438 +{
74439 +    void *osbuf;
74440 +    WMI_SET_MAX_SP_LEN_CMD *cmd;
74441 +
74442 +    /* maxSPLen is a two-bit value. If user trys to set anything
74443 +     * other than this, then its invalid
74444 +     */
74445 +    if(maxSPLen & ~0x03)
74446 +        return  A_EINVAL;
74447 +
74448 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74449 +    if (osbuf == NULL) {
74450 +        return A_NO_MEMORY;
74451 +    }
74452 +
74453 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74454 +
74455 +    cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf));
74456 +    A_MEMZERO(cmd, sizeof(*cmd));
74457 +    cmd->maxSPLen = maxSPLen;
74458 +
74459 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID,
74460 +            NO_SYNC_WMIFLAG));
74461 +}
74462 +
74463 +A_UINT8
74464 +convert_userPriority_to_trafficClass(A_UINT8 userPriority)
74465 +{
74466 +        return  (up_to_ac[userPriority & 0x7]);
74467 +}
74468 +
74469 +A_UINT8
74470 +wmi_get_power_mode_cmd(struct wmi_t *wmip)
74471 +{
74472 +    return wmip->wmi_powerMode;
74473 +}
74474 +
74475 +A_STATUS
74476 +wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance)
74477 +{
74478 +    return A_OK;
74479 +}
74480 +
74481 +#ifdef CONFIG_HOST_TCMD_SUPPORT
74482 +static A_STATUS
74483 +wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
74484 +{
74485 +
74486 +   A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
74487 +
74488 +   A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len);
74489 +
74490 +   return A_OK;
74491 +}
74492 +
74493 +#endif /* CONFIG_HOST_TCMD_SUPPORT*/
74494 +
74495 +A_STATUS
74496 +wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
74497 +{
74498 +    void *osbuf;
74499 +    WMI_SET_AUTH_MODE_CMD *cmd;
74500 +
74501 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74502 +    if (osbuf == NULL) {
74503 +        return A_NO_MEMORY;
74504 +    }
74505 +
74506 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74507 +
74508 +    cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf));
74509 +    A_MEMZERO(cmd, sizeof(*cmd));
74510 +    cmd->mode = mode;
74511 +
74512 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID,
74513 +            NO_SYNC_WMIFLAG));
74514 +}
74515 +
74516 +A_STATUS
74517 +wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
74518 +{
74519 +    void *osbuf;
74520 +    WMI_SET_REASSOC_MODE_CMD *cmd;
74521 +
74522 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74523 +    if (osbuf == NULL) {
74524 +        return A_NO_MEMORY;
74525 +    }
74526 +
74527 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74528 +
74529 +    cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf));
74530 +    A_MEMZERO(cmd, sizeof(*cmd));
74531 +    cmd->mode = mode;
74532 +
74533 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID,
74534 +            NO_SYNC_WMIFLAG));
74535 +}
74536 +
74537 +A_STATUS
74538 +wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status)
74539 +{
74540 +    void *osbuf;
74541 +    WMI_SET_LPREAMBLE_CMD *cmd;
74542 +
74543 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74544 +    if (osbuf == NULL) {
74545 +        return A_NO_MEMORY;
74546 +    }
74547 +
74548 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74549 +
74550 +    cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf));
74551 +    A_MEMZERO(cmd, sizeof(*cmd));
74552 +    cmd->status = status;
74553 +
74554 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID,
74555 +            NO_SYNC_WMIFLAG));
74556 +}
74557 +
74558 +A_STATUS
74559 +wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold)
74560 +{
74561 +    void *osbuf;
74562 +    WMI_SET_RTS_CMD *cmd;
74563 +
74564 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74565 +    if (osbuf == NULL) {
74566 +        return A_NO_MEMORY;
74567 +    }
74568 +
74569 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74570 +
74571 +    cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf));
74572 +    A_MEMZERO(cmd, sizeof(*cmd));
74573 +    cmd->threshold = threshold;
74574 +
74575 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID,
74576 +            NO_SYNC_WMIFLAG));
74577 +}
74578 +
74579 +A_STATUS
74580 +wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status)
74581 +{
74582 +    void *osbuf;
74583 +    WMI_SET_WMM_CMD *cmd;
74584 +
74585 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74586 +    if (osbuf == NULL) {
74587 +        return A_NO_MEMORY;
74588 +    }
74589 +
74590 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74591 +
74592 +    cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf));
74593 +    A_MEMZERO(cmd, sizeof(*cmd));
74594 +    cmd->status = status;
74595 +
74596 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID,
74597 +            NO_SYNC_WMIFLAG));
74598 +
74599 +}
74600 +
74601 +A_STATUS
74602 +wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg)
74603 +{
74604 +    void *osbuf;
74605 +    WMI_SET_WMM_TXOP_CMD *cmd;
74606 +
74607 +    if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) )
74608 +        return A_EINVAL;
74609 +
74610 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74611 +    if (osbuf == NULL) {
74612 +        return A_NO_MEMORY;
74613 +    }
74614 +
74615 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74616 +
74617 +    cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf));
74618 +    A_MEMZERO(cmd, sizeof(*cmd));
74619 +    cmd->txopEnable = cfg;
74620 +
74621 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID,
74622 +            NO_SYNC_WMIFLAG));
74623 +
74624 +}
74625 +
74626 +#ifdef CONFIG_HOST_TCMD_SUPPORT
74627 +/* WMI  layer doesn't need to know the data type of the test cmd.
74628 +   This would be beneficial for customers like Qualcomm, who might
74629 +   have different test command requirements from differnt manufacturers
74630 + */
74631 +A_STATUS
74632 +wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32  len)
74633 +{
74634 +    void *osbuf;
74635 +    char *data;
74636 +
74637 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
74638 +
74639 +    osbuf= A_NETBUF_ALLOC(len);
74640 +    if(osbuf == NULL)
74641 +    {
74642 +        return A_NO_MEMORY;
74643 +    }
74644 +    A_NETBUF_PUT(osbuf, len);
74645 +    data = A_NETBUF_DATA(osbuf);
74646 +    A_MEMCPY(data, buf, len);
74647 +
74648 +    return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID,
74649 +         NO_SYNC_WMIFLAG));
74650 +}
74651 +
74652 +#endif
74653 +
74654 +A_STATUS
74655 +wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status)
74656 +{
74657 +    void *osbuf;
74658 +    WMI_SET_BT_STATUS_CMD *cmd;
74659 +
74660 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74661 +    if (osbuf == NULL) {
74662 +        return A_NO_MEMORY;
74663 +    }
74664 +
74665 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74666 +
74667 +    cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
74668 +    A_MEMZERO(cmd, sizeof(*cmd));
74669 +    cmd->streamType = streamType;
74670 +    cmd->status = status;
74671 +
74672 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID,
74673 +            NO_SYNC_WMIFLAG));
74674 +}
74675 +
74676 +A_STATUS
74677 +wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd)
74678 +{
74679 +    void *osbuf;
74680 +    WMI_SET_BT_PARAMS_CMD* alloc_cmd;
74681 +
74682 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74683 +    if (osbuf == NULL) {
74684 +        return A_NO_MEMORY;
74685 +    }
74686 +
74687 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74688 +
74689 +    alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
74690 +    A_MEMZERO(alloc_cmd, sizeof(*cmd));
74691 +    A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
74692 +
74693 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID,
74694 +            NO_SYNC_WMIFLAG));
74695 +}
74696 +
74697 +A_STATUS
74698 +wmi_get_keepalive_configured(struct wmi_t *wmip)
74699 +{
74700 +    void *osbuf;
74701 +    WMI_GET_KEEPALIVE_CMD *cmd;
74702 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74703 +    if (osbuf == NULL) {
74704 +        return A_NO_MEMORY;
74705 +    }
74706 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74707 +    cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
74708 +    A_MEMZERO(cmd, sizeof(*cmd));
74709 +    return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID,
74710 +                         NO_SYNC_WMIFLAG));
74711 +}
74712 +
74713 +A_UINT8
74714 +wmi_get_keepalive_cmd(struct wmi_t *wmip)
74715 +{
74716 +    return wmip->wmi_keepaliveInterval;
74717 +}
74718 +
74719 +A_STATUS
74720 +wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval)
74721 +{
74722 +    void *osbuf;
74723 +    WMI_SET_KEEPALIVE_CMD *cmd;
74724 +
74725 +    osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
74726 +    if (osbuf == NULL) {
74727 +        return A_NO_MEMORY;
74728 +    }
74729 +
74730 +    A_NETBUF_PUT(osbuf, sizeof(*cmd));
74731 +
74732 +    cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
74733 +    A_MEMZERO(cmd, sizeof(*cmd));
74734 +    cmd->keepaliveInterval = keepaliveInterval;
74735 +    wmip->wmi_keepaliveInterval = keepaliveInterval;
74736 +
74737 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID,
74738 +                         NO_SYNC_WMIFLAG));
74739 +}
74740 +
74741 +A_STATUS
74742 +wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen,
74743 +                  A_UINT8 *ieInfo)
74744 +{
74745 +    void *osbuf;
74746 +    WMI_SET_APPIE_CMD *cmd;
74747 +    A_UINT16 cmdLen;
74748 +
74749 +    if (ieLen > WMI_MAX_IE_LEN) {
74750 +        return A_ERROR;
74751 +    }
74752 +    cmdLen = sizeof(*cmd) + ieLen - 1;
74753 +    osbuf = A_NETBUF_ALLOC(cmdLen);
74754 +    if (osbuf == NULL) {
74755 +        return A_NO_MEMORY;
74756 +    }
74757 +
74758 +    A_NETBUF_PUT(osbuf, cmdLen);
74759 +
74760 +    cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf));
74761 +    A_MEMZERO(cmd, cmdLen);
74762 +
74763 +    cmd->mgmtFrmType = mgmtFrmType;
74764 +    cmd->ieLen = ieLen;
74765 +    A_MEMCPY(cmd->ieInfo, ieInfo, ieLen);
74766 +
74767 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG));
74768 +}
74769 +
74770 +A_STATUS
74771 +wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen)
74772 +{
74773 +    void *osbuf;
74774 +    A_UINT8 *data;
74775 +
74776 +    osbuf = A_NETBUF_ALLOC(dataLen);
74777 +    if (osbuf == NULL) {
74778 +        return A_NO_MEMORY;
74779 +    }
74780 +
74781 +    A_NETBUF_PUT(osbuf, dataLen);
74782 +
74783 +    data = A_NETBUF_DATA(osbuf);
74784 +
74785 +    A_MEMCPY(data, cmd, dataLen);
74786 +
74787 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG));
74788 +}
74789 +
74790 +A_INT32
74791 +wmi_get_rate(A_INT8 rateindex)
74792 +{
74793 +    if (rateindex == RATE_AUTO) {
74794 +        return 0;
74795 +    } else {
74796 +        return(wmi_rateTable[(A_UINT32) rateindex]);
74797 +    }
74798 +}
74799 +
74800 +void
74801 +wmi_node_return (struct wmi_t *wmip, bss_t *bss)
74802 +{
74803 +       if (NULL != bss)
74804 +       {
74805 +               wlan_node_return (&wmip->wmi_scan_table, bss);
74806 +       }
74807 +}
74808 +
74809 +bss_t *
74810 +wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
74811 +                                  A_UINT32 ssidLength, A_BOOL bIsWPA2)
74812 +{
74813 +       bss_t *node = NULL;
74814 +    node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid,
74815 +                                                          ssidLength, bIsWPA2);
74816 +       return node;
74817 +}
74818 +
74819 +void
74820 +wmi_free_allnodes(struct wmi_t *wmip)
74821 +{
74822 +       wlan_free_allnodes(&wmip->wmi_scan_table);
74823 +}
74824 +
74825 +bss_t *
74826 +wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
74827 +{
74828 +       bss_t *ni=NULL;
74829 +       ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
74830 +       return ni;
74831 +}
74832 +
74833 +A_STATUS
74834 +wmi_dset_open_reply(struct wmi_t *wmip,
74835 +                    A_UINT32 status,
74836 +                    A_UINT32 access_cookie,
74837 +                    A_UINT32 dset_size,
74838 +                    A_UINT32 dset_version,
74839 +                    A_UINT32 targ_handle,
74840 +                    A_UINT32 targ_reply_fn,
74841 +                    A_UINT32 targ_reply_arg)
74842 +{
74843 +    void *osbuf;
74844 +    WMIX_DSETOPEN_REPLY_CMD *open_reply;
74845 +
74846 +    A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip));
74847 +
74848 +    osbuf = A_NETBUF_ALLOC(sizeof(*open_reply));
74849 +    if (osbuf == NULL) {
74850 +        return A_NO_MEMORY;
74851 +    }
74852 +
74853 +    A_NETBUF_PUT(osbuf, sizeof(*open_reply));
74854 +    open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
74855 +
74856 +    open_reply->status                   = status;
74857 +    open_reply->targ_dset_handle         = targ_handle;
74858 +    open_reply->targ_reply_fn            = targ_reply_fn;
74859 +    open_reply->targ_reply_arg           = targ_reply_arg;
74860 +    open_reply->access_cookie            = access_cookie;
74861 +    open_reply->size                     = dset_size;
74862 +    open_reply->version                  = dset_version;
74863 +
74864 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID,
74865 +                             NO_SYNC_WMIFLAG));
74866 +}
74867 +
74868 +static A_STATUS
74869 +wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
74870 +{
74871 +    WMI_PMKID_LIST_REPLY *reply;
74872 +    A_UINT32 expected_len;
74873 +
74874 +    if (len < sizeof(WMI_PMKID_LIST_REPLY)) {
74875 +        return A_EINVAL;
74876 +    }
74877 +    reply = (WMI_PMKID_LIST_REPLY *)datap;
74878 +    expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN;
74879 +
74880 +    if (len < expected_len) {
74881 +        return A_EINVAL;
74882 +    }
74883 +
74884 +    A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID,
74885 +                           reply->pmkidList);
74886 +
74887 +    return A_OK;
74888 +}
74889 +
74890 +#ifdef CONFIG_HOST_DSET_SUPPORT
74891 +A_STATUS
74892 +wmi_dset_data_reply(struct wmi_t *wmip,
74893 +                    A_UINT32 status,
74894 +                    A_UINT8 *user_buf,
74895 +                    A_UINT32 length,
74896 +                    A_UINT32 targ_buf,
74897 +                    A_UINT32 targ_reply_fn,
74898 +                    A_UINT32 targ_reply_arg)
74899 +{
74900 +    void *osbuf;
74901 +    WMIX_DSETDATA_REPLY_CMD *data_reply;
74902 +    int size;
74903 +
74904 +    size = sizeof(*data_reply) + length;
74905 +
74906 +    A_DPRINTF(DBG_WMI,
74907 +        (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status));
74908 +
74909 +    osbuf = A_NETBUF_ALLOC(size);
74910 +    if (osbuf == NULL) {
74911 +        return A_NO_MEMORY;
74912 +    }
74913 +    A_NETBUF_PUT(osbuf, size);
74914 +    data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
74915 +
74916 +    data_reply->status                     = status;
74917 +    data_reply->targ_buf                   = targ_buf;
74918 +    data_reply->targ_reply_fn              = targ_reply_fn;
74919 +    data_reply->targ_reply_arg             = targ_reply_arg;
74920 +    data_reply->length                     = length;
74921 +
74922 +    if (status == A_OK) {
74923 +        if (a_copy_from_user(data_reply->buf, user_buf, length)) {
74924 +            return A_ERROR;
74925 +        }
74926 +    }
74927 +
74928 +    return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID,
74929 +                             NO_SYNC_WMIFLAG));
74930 +}
74931 +#endif /* CONFIG_HOST_DSET_SUPPORT */
74932 +
74933 +A_STATUS
74934 +wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status)
74935 +{
74936 +    void *osbuf;
74937 +    char *cmd;
74938 +
74939 +       wps_enable = status;
74940 +
74941 +    osbuf = a_netbuf_alloc(sizeof(1));
74942 +    if (osbuf == NULL) {
74943 +        return A_NO_MEMORY;
74944 +    }
74945 +
74946 +    a_netbuf_put(osbuf, sizeof(1));
74947 +
74948 +    cmd = (char *)(a_netbuf_to_data(osbuf));
74949 +
74950 +    A_MEMZERO(cmd, sizeof(*cmd));
74951 +    cmd[0] = (status?1:0);
74952 +    return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID,
74953 +                         NO_SYNC_WMIFLAG));
74954 +}
74955 +
74956 Index: linux-2.6.28/drivers/ar6000/wmi/wmi_doc.h
74957 ===================================================================
74958 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
74959 +++ linux-2.6.28/drivers/ar6000/wmi/wmi_doc.h   2009-01-02 00:01:56.000000000 +0100
74960 @@ -0,0 +1,4421 @@
74961 +/*
74962 + *
74963 + * Copyright (c) 2004-2007 Atheros Communications Inc.
74964 + * All rights reserved.
74965 + *
74966 + *
74967 + *  This program is free software; you can redistribute it and/or modify
74968 + *  it under the terms of the GNU General Public License version 2 as
74969 + *  published by the Free Software Foundation;
74970 + *
74971 + *  Software distributed under the License is distributed on an "AS
74972 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
74973 + *  implied. See the License for the specific language governing
74974 + *  rights and limitations under the License.
74975 + *
74976 + *
74977 + *
74978 + */
74979 +
74980 +
74981 +#if 0
74982 +Wireless Module Interface (WMI) Documentaion
74983 +
74984 +   This section describes the format and the usage model for WMI control and
74985 +   data messages between the host and the AR6000-based targets. The header
74986 +   file include/wmi.h contains all command and event manifest constants as
74987 +   well as structure typedefs for each set of command and reply parameters.
74988 +
74989 +Data Frames
74990 +
74991 +   The data payload transmitted and received by the target follows RFC-1042
74992 +   encapsulation and thus starts with an 802.2-style LLC-SNAP header. The
74993 +   WLAN module completes 802.11 encapsulation of the payload, including the
74994 +   MAC header, FCS, and WLAN security related fields. At the interface to the
74995 +   message transport (HTC), a data frame is encapsulated in a WMI message.
74996 +
74997 +WMI Message Structure
74998 +
74999 +   The WMI protocol leverages an 802.3-style Ethernet header in communicating
75000 +   the source and destination information between the host and the AR6000
75001 +   modules using a 14-byte 802.3 header ahead of the 802.2-style payload. In
75002 +   addition, the WMI protocol adds a header to all data messages:
75003 +
75004 +    {
75005 +    INT8    rssi
75006 +                  The RSSI of the received packet and its units are shown in db above the
75007 +                      noise floor, and the noise floor is shown in dbm.
75008 +    UINT8   info
75009 +                      Contains information on message type and user priority. Message type
75010 +                      differentiates between a data packet and a synchronization message.
75011 +    } WMI_DATA_HDR
75012 +
75013 +   User priority contains the 802.1d user priority info from host to target. Host
75014 +   software translates the host Ethernet format to 802.3 format prior to Tx and
75015 +   802.3 format to host format in the Rx direction. The host does not transmit the
75016 +   FCS that follows the data. MsgType differentiates between a regular data
75017 +   packet (msgType=0) and a synchronization message (msgType=1).
75018 +
75019 +Data Endpoints
75020 +
75021 +   The AR6000 chipset provides several data endpoints to support quality of
75022 +   service (QoS) and maintains separate queues and separate DMA engines for
75023 +   each data endpoint. A data endpoint can be bi-directional.
75024 +
75025 +   Best effort (BE) class traffic uses the default data endpoint (2). The host can
75026 +   establish up to two additional data endpoints for other traffic classes. Once
75027 +   such a data endpoint is established, it sends and receives corresponding QoS
75028 +   traffic in a manner similar to the default data endpoint.
75029 +
75030 +   If QoS is desired over the interconnect, host software must classify each data
75031 +   packet and place it on the appropriate data endpoint. The information
75032 +   required to classify data is generally available in-band as an 802.1p/q style
75033 +   tag or as the ToS field in the IP header. The information may also be available
75034 +   out-of-band depending on the host DDI.
75035 +
75036 +Connection States
75037 +
75038 +   Table B-1 describes the AR6000 WLAN connection states:
75039 +
75040 +   Table B-1.  AR6000 Connection States
75041 +
75042 +Connection State
75043 +    Description
75044 +
75045 +   DISCONNECTED
75046 +    In this state, the AR6000 device is not connected to a wireless
75047 +   network. The device is in this state after reset when it sends the
75048 +   WIRELESS MODULE \93READY\94 EVENT, after it processes a
75049 +   DISCONNECT command, and when it loses its link with the
75050 +   access point (AP) that it was connected to. The device signals a
75051 +   transition to the DISCONNECTED state with a \93DISCONNECT\94
75052 +   event.
75053 +
75054 +CONNECTED
75055 +    In this state, the AR6000 device is connected to wireless networks.
75056 +   The device enters this state after successfully processing a
75057 +   CONNECT, which establishes a connection with a wireless
75058 +   network. The device signals a transition to the CONNECTED state
75059 +   with a \93CONNECT\94 event.
75060 +
75061 +
75062 +Message Types
75063 +
75064 +   WMI uses commands, replies, and events for the control and configuration of
75065 +   the AR6000 device. The control protocol is asynchronous. Table B-2 describes
75066 +   AR6000 message types:
75067 +
75068 +Table B-2.  AR6000 Message Types
75069 +
75070 +Message Type
75071 +    Description
75072 +
75073 +Commands
75074 +    Control messages that flow from the host to the device
75075 +
75076 +Replies/Events
75077 +    Control messages that flow from the device to the host.
75078 +
75079 +   The device issues a reply to some WMI commands, but not to others.
75080 +   The payload in a reply is command-specific, and some commands do
75081 +   not trigger a reply message at all. Events are control messages issued
75082 +   by the device to signal the occurrence of an asynchronous event.
75083 +
75084 +
75085 +WMI Message Format
75086 +
75087 +   All WMI control commands, replies and events use the header format:
75088 +
75089 +   WMI_CMD_HDR Header Format
75090 +   {
75091 +        UINT16 id
75092 +                 This 16-bit constant identifies which WMI command the host is issuing,
75093 +                 which command the target is replying to, or which event has occurred.
75094 +        WMI_CMD_HDR
75095 +   }
75096 +
75097 +
75098 +   A variable-size command-, reply-, or event-specific payload follows the
75099 +   header. Over the interconnect, all fields in control messages (including
75100 +   WMI_CMD_HDR and the command specific payload) use 32-bit little Endian
75101 +   byte ordering and fields are packed. The AR6000 device always executes
75102 +   commands in order, and the host may send multiple commands without
75103 +   waiting for previous commands to complete. A majority of commands are
75104 +   processed to completion once received. Other commands trigger a longer
75105 +   duration activity whose completion is signaled to the host through an event.
75106 +
75107 +Command Restrictions
75108 +
75109 +   Some commands may only be issued when the AR6000 device is in a certain
75110 +   state. The host is required to wait for an event signaling a state transition
75111 +   before such a command can be issued. For example, if a command requires
75112 +   the device to be in the CONNECTED state, then the host is required to wait
75113 +   for a \93CONNECT\94 event before it issues that command.
75114 +
75115 +   The device ignores any commands inappropriate for its current state. If the
75116 +   command triggers a reply, the device generates an error reply. Otherwise, the
75117 +   device silently ignores the inappropriate command.
75118 +
75119 +Command and Data Synchronization
75120 +
75121 +   WMI provides a mechanism for a host to advise the device of necessary
75122 +   synchronization between commands and data. The device implements
75123 +   synchronization; no implicit synchronization exists between endpoints.
75124 +
75125 +   The host controls synchronization using the \93SYNCHRONIZE\94 command
75126 +   over the control channel and synchronization messages over data channels.
75127 +   The device stops each data channel upon receiving a synchronization message
75128 +   on that channel, processing all data packets received prior to that message.
75129 +   After the device receives synchronization messages for each data endpoint
75130 +   and the \93SYNCHRONIZE\94 command, it resumes all channels.
75131 +
75132 +   When the host must guarantee a command executes before processing new
75133 +   data packets, it first issues the command, then issues the \93SYNCHRONIZE\94
75134 +   command and sends synchronization messages on data channels. When the
75135 +   host must guarantee the device has processed all old data packets before a
75136 +   processing a new command, it issues a \93SYNCHRONIZE\94 command and
75137 +   synchronization messages on all data channels, then issues the desired
75138 +   command.
75139 +
75140 +
75141 +
75142 +WMI Commands
75143 +
75144 +   ADD_BAD_AP
75145 +    Cause the AR6000 device to avoid a particular AP
75146 +   ADD_CIPHER_KEY
75147 +    Add or replace any of the four AR6000 encryption keys
75148 +   ADD_WOW_PATTERN
75149 +    Used to add a pattern to the WoW pattern list
75150 +   CLR_RSSI_SNR
75151 +    Clear the current calculated RSSI and SNR value
75152 +   CONNECT_CMD
75153 +    Request that the AR6000 device establish a wireless connection
75154 +        with the specified SSID
75155 +   CREATE_PSTREAM
75156 +    Create prioritized data endpoint between the host and device
75157 +   DELETE_BAD_AP
75158 +    Clear an entry in the bad AP table
75159 +   DELETE_CIPHER_KEY
75160 +    Delete a previously added cipher key
75161 +   DELETE_PSTREAM
75162 +    Delete a prioritized data endpoint
75163 +   DELETE_WOW_PATTERN
75164 +    Remove a pre-specified pattern from the WoW pattern list
75165 +   EXTENSION
75166 +    WMI message interface command
75167 +   GET_BIT_RATE
75168 +    Retrieve rate most recently used by the AR6000
75169 +   GET_CHANNEL_LIST
75170 +    Retrieve list of channels used by the AR6000
75171 +   GET_FIXRATES
75172 +    Retrieves the rate-mask set via the SET_FIXRATES command.
75173 +   GET_PMKID_LIST_CMD
75174 +    Retrieve the firmware list of PMKIDs
75175 +   GET_ROAM_DATA
75176 +    Internal use for data collection; available in special build only
75177 +   GET_ROAM_TBL
75178 +    Retrieve the roaming table maintained on the target
75179 +   GET_TARGET_STATS
75180 +    Request that the target send the statistics it maintains
75181 +   GET_TX_PWR
75182 +    Retrieve the current AR6000 device Tx power levels
75183 +   GET_WOW_LIST
75184 +    Retrieve the current list of WoW patterns
75185 +   LQ_THRESHOLD_PARAMS
75186 +    Set the link quality thresholds
75187 +   OPT_TX_FRAME
75188 +    Send a special frame (special feature)
75189 +   RECONNECT
75190 +    Request a reconnection to a BSS
75191 +   RSSI_THRESHOLD_PARAMS
75192 +    Configure how the AR6000 device monitors and reports signal
75193 +       strength (RSSI) of the connected BSS
75194 +   SCAN_PARAMS
75195 +    Determine dwell time and changes scanned channels
75196 +   SET_ACCESS_PARAMS
75197 +    Set access parameters for the wireless network
75198 +   SET_ADHOC_BSSID
75199 +    Set the BSSID for an ad hoc network
75200 +   SET_AKMP_PARAMS
75201 +    Set multiPMKID mode
75202 +   SET_APPIE
75203 +    Add application-specified IE to a management frame
75204 +   SET_ASSOC_INFO
75205 +    Specify the IEs the device should add to association or
75206 +        reassociation requests
75207 +   SET_AUTH_MODE
75208 +    Set 802.11 authentication mode of reconnection
75209 +   SET_BEACON_INT
75210 +    Set the beacon interval for an ad hoc network
75211 +   SET_BIT_RATE
75212 +    Set the AR6000 to a specific fixed bit rate
75213 +   SET_BMISS_TIME
75214 +    Set the beacon miss time
75215 +   SET_BSS_FILTER
75216 +    Inform the AR6000 of network types about which it wants to
75217 +        receive information using a \93BSSINFO\94 event
75218 +   SET_BT_PARAMS
75219 +    Set the status of a Bluetooth stream (SCO or A2DP) or set
75220 +        Bluetooth coexistence register parameters
75221 +   SET_BT_STATUS
75222 +    Set the status of a Bluetooth stream (SCO or A2DP)
75223 +   SET_CHANNEL_PARAMETERS
75224 +    Configure WLAN channel parameters
75225 +   SET_DISC_TIMEOUT
75226 +    Set the amount of time the AR6000 spends attempting to
75227 +        reestablish a connection
75228 +   SET_FIXRATES
75229 +    Set the device to a specific fixed PHY rate (supported subset)
75230 +   SET_HALPARAM
75231 +    Internal AR6000 command to set certain hardware parameters
75232 +   SET_HOST_SLEEP_MODE
75233 +    Set the host mode to asleep or awake
75234 +   SET_IBSS_PM_CAPS
75235 +    Support a non-standard power management scheme for an
75236 +        ad hoc network
75237 +   SET_LISTEN_INT
75238 +    Request a listen interval
75239 +   SET_LPREAMBLE
75240 +    Override the short preamble capability of the AR6000 device
75241 +   SET_MAX_SP_LEN
75242 +    Set the maximum service period
75243 +   SET_OPT_MODE
75244 +    Set the special mode on/off (special feature)
75245 +   SET_PMKID
75246 +    Set the pairwise master key ID (PMKID)
75247 +   SET_PMKID_LIST_CMD
75248 +    Configure the firmware list of PMKIDs
75249 +   SET_POWER_MODE
75250 +    Set guidelines on trade-off between power utilization
75251 +   SET_POWER_PARAMS
75252 +    Configure power parameters
75253 +   SET_POWERSAVE_PARAMS
75254 +    Set the two AR6000 power save timers
75255 +   SET_PROBED_SSID
75256 +    Provide list of SSIDs the device should seek
75257 +   SET_REASSOC_MODE
75258 +    Specify whether the disassociated frame should be sent upon
75259 +        reassociation
75260 +   SET_RETRY_LIMITS
75261 +    Limit how many times the device tries to send a frame
75262 +   SET_ROAM_CTRL
75263 +    Control roaming behavior
75264 +   SET_RTS
75265 +    Determine when RTS should be sent
75266 +   SET_SCAN_PARAMS
75267 +    Set the AR6000 scan parameters
75268 +   SET_TKIP_COUNTERMEASURES
75269 +    Enable/disable reports of TKIP MIC errors
75270 +   SET_TX_PWR
75271 +    Specify the AR6000 device Tx power levels
75272 +   SET_VOICE_PKT_SIZE
75273 +    Set voice packet size
75274 +   SET_WMM
75275 +    Override the AR6000 WMM capability
75276 +   SET_WMM_TXOP
75277 +    Configure TxOP bursting when sending traffic to a WMM-
75278 +    capable AP
75279 +   SET_WOW_MODE
75280 +    Enable/disable WoW mode
75281 +   SET_WSC_STATUS
75282 +    Enable/disable profile check in cserv when the WPS protocol
75283 +    is in progress
75284 +   SNR_THRESHOLD_PARAMS
75285 +    Configure how the device monitors and reports SNR of BSS
75286 +   START_SCAN
75287 +    Start a long or short channel scan
75288 +   SYNCHRONIZE
75289 +    Force a synchronization point between command and data
75290 +    paths
75291 +   TARGET_REPORT_ERROR_BITMASK
75292 +    Control \93ERROR_REPORT\94 events from the AR6000
75293 +
75294 +
75295 +
75296 +
75297 +Name
75298 +    ADD_BAD_AP
75299 +
75300 +Synopsis
75301 +    The host uses this command to cause the AR6000 to avoid a particular AP. The
75302 +    AR6000 maintain a table with up to two APs to avoid. An ADD_BAD_AP command
75303 +    adds or replaces the specified entry in this bad AP table.
75304 +
75305 +    If the AR6000 are currently connected to the AP specified in this command, they
75306 +    disassociate.
75307 +
75308 +Command
75309 +    wmiconfig eth1 --badap <bssid> <badApIndex>
75310 +
75311 +Command Parameters
75312 +    UINT8 badApIndex    Index [0...1] that identifies which entry in the
75313 +                        bad AP table to use
75314 +
75315 +
75316 +    UINT8 bssid[6]  MAC address of the AP to avoid
75317 +
75318 +Command Values
75319 +    badApIndex = 0, 1    Entry in the bad AP table to use
75320 +
75321 +Reset Value
75322 +    The bad AP table is cleared
75323 +
75324 +Restrictions
75325 +    None
75326 +
75327 +See Also
75328 +    \93DELETE_BAD_AP\94 on page B-13
75329 +
75330 +=====================================================================
75331 +Name
75332 +    ADD_CIPHER_KEY
75333 +
75334 +Synopsis
75335 +    The host uses this command to add/replace any of four encryption keys on the
75336 +    AR6000. The ADD_CIPHER_KEY command is issued after the CONNECT event
75337 +    has been received by the host for all dot11Auth modes except for SHARED_AUTH.
75338 +    When the dot11AuthMode is SHARED_AUTH, then the ADD_CIPHER_KEY
75339 +    command should be issued before the \93CONNECT\94 command.
75340 +
75341 +Command
75342 +    wmiconfig eth1 --cipherkey <keyIndex> <keyType> <keyUsage>
75343 +                            <keyLength> <keyopctrl> <keyRSC> <key>
75344 +
75345 +Command Parameters
75346 +    UINT8 keyIndex      Index (0...3) of the key to add/replace;
75347 +                        uniquely identifies the key
75348 +    UINT8 keyType    CRYPTO_TYPE
75349 +    UINT8 keyUsage   Specifies usage parameters of the key when
75350 +                     keyType = WEP_CRYPT
75351 +    UINT8 keyLength  Length of the key in bytes
75352 +    UINT8 keyOpCtrl  bit[0] = Initialize TSC (default),
75353 +                     bit[1] = Initialize RSC
75354 +    UINT8 keyRSC[8]  Key replay sequence counter (RSC) initial
75355 +                     value the device should use
75356 +    UINT8 key[32]    Key material used for this connection
75357 +    Command Values
75358 +    {
75359 +        NONE_CRYPT = 1
75360 +        WEP_CRYPT  = 2
75361 +        TKIP_CRYPT = 3
75362 +        AES_CRYPT  = 4
75363 +        KEY_OP_INIT_TSC   0x01
75364 +        KEY_OP_INIT_RSC   0x02
75365 +        KEY_OP_INIT_VAL   0x03
75366 +                Default is to Initialize the TSC
75367 +        KEY_OP_VALID_MASK 0x04
75368 +                Two operations defined
75369 +    } CRYPTO_TYPE
75370 +
75371 +    {
75372 +        PAIRWISE_USAGE  = 0  Set if the key is used for unicast traffic only
75373 +        GROUP_USAGE     = 1  Set if the key is used to receive multicast
75374 +                              traffic (also set for static WEP keys)
75375 +        TX_USAGE        = 2  Set for the GROUP key used to transmit frames
75376 +                All others are reserved
75377 +    } KEY_USAGE
75378 +
75379 +Reset Value
75380 +    The four available keys are disabled.
75381 +
75382 +Restrictions
75383 +    The cipher should correspond to the encryption mode specified in the \93CONNECT\94
75384 +    command.
75385 +
75386 +See Also
75387 +    \93DELETE_CIPHER_KEY\94
75388 +
75389 +=====================================================================
75390 +
75391 +
75392 +Name
75393 +    ADD_WOW_PATTERN
75394 +
75395 +Synopsis
75396 +    The host uses this command to add a pattern to the WoW pattern list; used for
75397 +    pattern-matching for host wakeups by the WoW module. If the host mode is asleep
75398 +    and WoW is enabled, all packets are matched against the existing WoW patterns. If a
75399 +    packet matches any of the patterns specified, the target will wake up the host. All
75400 +    non-matching packets are discarded by the target without being sent up to the host.
75401 +
75402 +Command
75403 +    wmiconfig \96addwowpattern <list-id> <filter-size> <filter-offset>
75404 +    <pattern> <mask>
75405 +
75406 +Command Parameters
75407 +    A_UINT8  filter_list_id    ID of the list that is to include the new pattern
75408 +    A_UINT8  filter_size       Size of the new pattern
75409 +    A_UINT8  filter_offset     Offset at which the pattern matching for this
75410 +                                new pattern should begin at
75411 +    A_UINT8  filter[1]         Byte stream that contains both the pattern and
75412 +                                the mask of the new WoW wake-up pattern
75413 +
75414 +Reply Parameters
75415 +    None
75416 +
75417 +Reset Value
75418 +    None defined (default host mode is awake)
75419 +
75420 +Restrictions
75421 +    None
75422 +
75423 +See Also
75424 +    \93DELETE_WOW_PATTERN\94
75425 +
75426 +=====================================================================
75427 +
75428 +
75429 +Name
75430 +    CLR_RSSI_SNR
75431 +
75432 +Synopsis
75433 +    Clears the current calculated RSSI and SNR value. RSSI and SNR are reported by
75434 +    running-average value. This command will clear the history and have a fresh start
75435 +    for the running-average mechanism.
75436 +
75437 +Command
75438 +    wmiconfig eth1 --cleanRssiSnr
75439 +
75440 +Command Parameters
75441 +    None
75442 +
75443 +Reply Parameters
75444 +    None
75445 +
75446 +Reset Value
75447 +    None defined
75448 +
75449 +Restrictions
75450 +    None
75451 +
75452 +=====================================================================
75453 +
75454 +Name
75455 +    CONNECT_CMD
75456 +
75457 +Synopsis
75458 +    New connect control information (connectCtrl) is added, with 32 possible modifiers.
75459 +
75460 +    CONNECT_SEND_REASSOC
75461 +        Valid only for a host-controlled connection to a
75462 +        particular AP. If this bit is set, a reassociation frame is
75463 +        sent. If this bit is clear, an association request frame is
75464 +        sent to the AP.
75465 +
75466 +    CONNECT_IGNORE_WPAx_GROUP_CIPHER
75467 +        No group key is issued in the CONNECT command,
75468 +        so use the group key advertised by the AP. In a target-
75469 +        initiated roaming situation this allows a STA to roam
75470 +        between APs that support different multicast ciphers.
75471 +
75472 +    CONNECT_PROFILE_MATCH_DONE
75473 +        In a host-controlled connection case, it is possible that
75474 +        during connect, firmware may not have the
75475 +        information for a profile match (e.g, when the AP
75476 +        supports hidden SSIDs and the device may not
75477 +        transmit probe requests during connect). By setting
75478 +        this bit in the connection control information, the
75479 +        firmware waits for a beacon from the AP with the
75480 +        BSSID supplied in the CONNECT command. No
75481 +        additional profile checks are done.
75482 +
75483 +    CONNECT_IGNORE_AAC_BEACON
75484 +        Ignore the Admission Capacity information in the
75485 +        beacon of the AP
75486 +
75487 +    CONNECT_ASSOC_POLICY_USER
75488 +        When set, the CONNECT_SEND_REASSOC setting
75489 +        determines if an Assoc or Reassoc is sent to an AP
75490 +
75491 +Command
75492 +    wmiconfig --setconnectctrl <ctrl flags bitmask>
75493 +
75494 +Command Parameters
75495 +    typedef struct{
75496 +    A_UINT8 networktype;
75497 +    A_UINT8 dot11authmode;
75498 +    A_UINT8 authmode;
75499 +    A_UINT8 pairwiseCryptoType; /*CRYPTO_TYPE*/
75500 +    A_UINT8 pairwiseCryptoLen;
75501 +    A_UINT8 groupCryptoType; /*CRYPTO_TYPE*/
75502 +    A_UINT8 groupCryptoLen;
75503 +    A_UINT8 ssidLength;
75504 +    A_UCHAR ssid[WMI_MAX_SSID_LEN];
75505 +    A_UINT16 channel;
75506 +    A_UINT8 bssid[AUTH_MAC_LEN];
75507 +    A_UINT8 ctrl_flags; /*WMI_CONNECT_CTRL_FLAGS_BITS*/
75508 +    } WMI_CONNECT_CMD;
75509 +
75510 +    ctrl flags bitmask
75511 +        = 0x0001 CONNECT_ASSOC_POLICY_USER
75512 +            Assoc frames are sent using the policy specified by
75513 +            the flag
75514 +        = 0x0002 CONNECT_SEND_REASSOC
75515 +            Send Reassoc frame while connecting, otherwise send
75516 +            assoc frames
75517 +        = 0x0004 CONNECT_IGNORE_WPAx_GROUP_CIPHER
75518 +            Ignore WPAx group cipher for WPA/WPA2
75519 +        = 0x0008 CONNECT_PROFILE_MATCH_DONE
75520 +            Ignore any profile check
75521 +        = 0x0010 CONNECT_IGNORE_AAC_BEACON
75522 +            Ignore the admission control information in the
75523 +            beacon
75524 +        ... CONNECT_CMD, continued
75525 +        Command Values
75526 +        typedef enum {
75527 +            INFRA_NETWORK       = 0x01,
75528 +            ADHOC_NETWORK       = 0x02,
75529 +            ADHOC_CREATOR       = 0x04,
75530 +        } NETWORK_TYPE;
75531 +
75532 +        typedef enum {
75533 +            OPEN_AUTH           = 0x01,
75534 +            SHARED_AUTH         = 0x02,
75535 +            LEAP_AUTH           = 0x04,
75536 +        } DOT11_AUTH_MODE;
75537 +        typedef enum {
75538 +            NONE_AUTH           = 0x01,
75539 +            WPA_AUTH            = 0x02,
75540 +            WPA_PSK_AUTH        = 0x03,
75541 +            WPA2_AUTH           = 0x04,
75542 +            WPA2_PSK_AUTH       = 0x05,
75543 +            WPA_AUTH_CCKM       = 0x06,
75544 +            WPA2_AUTH_CCKM      = 0x07,
75545 +        } AUTH_MODE;
75546 +        typedef enum {
75547 +            NONE_CRYPT          = 0x01,
75548 +            WEP_CRYPT           = 0x02,
75549 +            TKIP_CRYPT          = 0x03,
75550 +            AES_CRYPT           = 0x04,
75551 +        } CRYPTO_TYPE;
75552 +        typedef enum {
75553 +            CONNECT_ASSOC_POLICY_USER = 0x0001,
75554 +            CONNECT_SEND_REASSOC = 0x0002,
75555 +            CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004,
75556 +            CONNECT_PROFILE_MATCH_DONE = 0x0008,
75557 +            CONNECT_IGNORE_AAC_BEACON = 0x0010,
75558 +        } WMI_CONNECT_CTRL_FLAGS_BITS;
75559 +
75560 +    pairwiseCryptoLen and groupCryptoLen are valid when the respective
75561 +    CryptoTypesis WEP_CRYPT, otherwise this value should be 0. This is the length in
75562 +    bytes.
75563 +
75564 +Reset Value
75565 +    None defined
75566 +
75567 +Restrictions
75568 +    None
75569 +
75570 +=====================================================================
75571 +
75572 +
75573 +Name
75574 +    CREATE_PSTREAM
75575 +
75576 +Synopsis
75577 +    The host uses this command to create a new prioritized data endpoint between the
75578 +    host and the AR6000 device that carries a prioritized stream of data. If the AP that the
75579 +    device connects to requires TSPEC stream establishment, the device requests the
75580 +    corresponding TSPEC with the AP. The maximum and minimum service interval
75581 +    ranges from 0 \96 0x7FFFFFFF (ms), where 0 = disabled. The device does not send a
75582 +    reply event for this command, as it is always assumed the command has succeeded.
75583 +    An AP admission control response comes to the host via a WMI_CAC_INDICATION
75584 +    event, once the response for the ADDTS frame comes.
75585 +
75586 +    Examples of cases where reassociation is generated (when WMM) and cases where
75587 +    ADDTS is generated (when WMM and enabling ACM) are when:
75588 +        Changing UAPSD flags in WMM mode, reassociation is generated
75589 +        Changing the interval of sending auto QoS Null frame in WMM mode;
75590 +            reassociation is not generated
75591 +        Issuing a command with same previous parameters in WMM mode and enabling
75592 +            ACM, an ADDTS request is generated
75593 +        Changing the interval of a QoS null frame sending in WMM mode and enabling
75594 +            ACM, an ADDTS request is generated
75595 +        Issuing the command in disconnected state, reassociation or ADDTS is not
75596 +            generated but the parameters are available after (re)association
75597 +
75598 +Command
75599 +    --createqos <user priority> <direction> <traffic class>
75600 +<trafficType> <voice PS capability> <min service interval> <max
75601 +service interval> <inactivity interval> <suspension interval>
75602 +<service start time> <tsid> <nominal MSDU> <max MSDU> <min data
75603 +rate> <mean data rate> <peak data rate> <max burst size> <delay
75604 +bound> <min phy rate> <sba> <medium time> where:
75605 +
75606 +    <user priority>
75607 +    802.1D user priority range (0\967)
75608 +    <direction>
75609 +        = 0    Tx (uplink) traffic
75610 +        = 1    Rx (downlink) traffic
75611 +        = 2    Bi-directional traffic
75612 +    <traffic class>
75613 +        = 1    BK
75614 +        = 2    VI
75615 +        = 3    VO
75616 +    <trafficType>
75617 +        = 0    Aperiodic
75618 +        = 1    Periodic
75619 +    <voice PS capability>
75620 +        Specifies whether the voice power save mechanism
75621 +    (APSD if AP supports it or legacy/simulated APSD
75622 +    [using PS-Poll]) should be used
75623 +        = 0    Disable voice power save for traffic class
75624 +        = 1    Enable APSD voice power save for traffic class
75625 +        = 2    Enable voice power save for all traffic classes
75626 +    <min service interval>
75627 +        (In ms)
75628 +    <max service interval>
75629 +        Inactivity interval (in ms) (0 = Infinite)
75630 +    <suspension interval>
75631 +        (In ms)
75632 +    <service start time>
75633 +        Service start time
75634 +    <tsid>
75635 +        TSID range (0\9615)
75636 +    <nominal MSDU>
75637 +        Nominal MAC SDU size
75638 +    <max MSDU>
75639 +        Maximum MAC SDU size
75640 +    <min data rate>
75641 +        Minimum data rate (in bps)
75642 +    <mean data rate>
75643 +        Mean data rate (in bps)
75644 +    <peak data rate>
75645 +        Peak data rate (in bps)
75646 +    <max burst size>
75647 +        Maximum burst size (in bps)
75648 +    <delay bound>
75649 +        Delay bound
75650 +    <min phy rate>
75651 +        Minimum PHY rate (in bps)
75652 +    <sba>
75653 +        Surplus bandwidth allowance
75654 +    <medium time>
75655 +        Medium time in TU of 32-ms periods per sec
75656 +    ... CREATE_PSTREAM (continued)
75657 +
75658 +Command Parameters
75659 +    UINT8 trafficClass    TRAFFIC_CLASS value
75660 +    UINT8 traffic
75661 +    Direction
75662 +    DIR_TYPE value
75663 +    UINT8    rxQueueNum
75664 +        AR6000 device mailbox index (2 or 3)
75665 +        corresponding to the endpoint the host
75666 +        wishes to use to receive packets for the
75667 +        prioritized stream
75668 +    UINT8 trafficType  TRAFFIC_TYPE value
75669 +    UINT8 voicePS
75670 +Capability
75671 +    VOICEPS_CAP_TYPE value
75672 +    UINT8 tsid          Traffic stream ID
75673 +    UINT8 userPriority  802.1D user priority
75674 +    UINT16 nominalMSDU  Nominal MSDU in octets
75675 +    UINT16 maxMSDU      Maximum MSDU in octets
75676 +    UINT32 minServiceInt Minimum service interval: the min.
75677 +                            period of traffic specified (in ms)
75678 +    UINT32 maxServiceInt  Maximum service interval: the max.
75679 +                        period of traffic specified (in ms)
75680 +    UINT32 inactivityInt Indicates how many ms an established
75681 +                        stream is inactive before the prioritized
75682 +                        data endpoint is taken down and the
75683 +                        corresponding T-SPEC deleted
75684 +    UINT32 suspensionInt  Suspension interval (in ms)
75685 +    UINT32 service       StartTime Service start time
75686 +    UINT32 minDataRate  Minimum data rate (in bps)
75687 +    UINT32 meanDataRate Mean data rate (in bps)
75688 +    UINT32 peakDataRate Peak data rate (in bps)
75689 +    UINT32 maxBurstSize
75690 +    UINT32 delayBound
75691 +    UINT32 minPhyRate   Minimum PHY rate for TSPEC (in bps)
75692 +    UINT32 sba          Surplus bandwidth allowance
75693 +    UINT32 mediumTime   Medium TSPEC time (in units of 32 ms)
75694 +Command Values
75695 +    {
75696 +        WMM_AC_BE = 0   Best Effort
75697 +        WMM_AC_BK = 1   Background
75698 +        WMM_AC_VI = 2   Video
75699 +        WMM_AC_VO = 3   Voice
75700 +        All other values reserved
75701 +    } TRAFFIC_CLASS
75702 +    {
75703 +        UPLINK_TRAFFIC   = 0  From the AR6000 device to the AP
75704 +        DOWNLINK_TRAFFIC = 1  From the AP to the AR6000 device
75705 +        BIDIR_TRAFFIC    = 2  Bi-directional traffic
75706 +        All other values reserved
75707 +    } DIR_TYPE
75708 +    {
75709 +        DISABLE_FOR_THIS_AC = 0
75710 +        ENABLE_FOR_THIS_AC  = 1
75711 +        ENABLE_FOR_ALL_AC   = 2
75712 +        All other values reserved
75713 +    } VOICEPS_CAP_TYPE
75714 +
75715 +    ... CREATE_PSTREAM (continued)
75716 +
75717 +
75718 +        VI  BE   BK    Supported, Y/N?
75719 +   0    0    0    0    Y
75720 +   0    0    0    1    Y
75721 +   0    0    1    0    N
75722 +   0    0    1    1    N
75723 +   0    1    0    0    Y
75724 +   0    1    0    1    Y
75725 +   0    1    1    0    N
75726 +   0    1    1    1    N
75727 +   1    0    0    0    Y
75728 +   1    0    0    1    Y
75729 +   1    0    1    0    N
75730 +   1    1    0    0    N
75731 +   1    1    0    1    Y
75732 +   1    1    0    0    N
75733 +   1    1    1    0    N
75734 +   1    1    1    1    Y
75735 +
75736 +Reset Value
75737 +    No pstream is present after reset; each of the BE, BK, VI,VO pstreams must be created
75738 +    (either implicitly by data flow or explicitly by user)
75739 +
75740 +Restrictions
75741 +    This command can only be issued when the device is in the CONNECTED state. If
75742 +    the device receives the command while in DISCONNECTED state, it replies with a
75743 +    failure indication. At most four prioritized data endpoints can be created, one for
75744 +    each AC.
75745 +
75746 +See Also
75747 +    \93DELETE_PSTREAM\94
75748 +=====================================================================
75749 +
75750 +Name
75751 +    DELETE_BAD_AP
75752 +
75753 +Synopsis
75754 +    The host uses this command to clear a particular entry in the bad AP table
75755 +
75756 +Command
75757 +    wmiconfig eth1 --rmAP [--num=<index>] // used to clear a badAP
75758 +    entry. num is index from 0-3
75759 +
75760 +Command Parameters
75761 +    UINT8  badApIndex   Index [0...n] that identifies the entry in the bad
75762 +                        AP table to delete
75763 +
75764 +Command Values
75765 +    badApIndex   = 0, 1, 2, 3
75766 +            Entry in the bad AP table
75767 +
75768 +Reset Value
75769 +    None defined
75770 +
75771 +Restrictions
75772 +    None
75773 +
75774 +See Also
75775 +    \93ADD_BAD_AP\94
75776 +
75777 +=====================================================================
75778 +
75779 +
75780 +Name
75781 +    DELETE_CIPHER_KEY
75782 +
75783 +Synopsis
75784 +    The host uses this command to delete a key that was previously added with the
75785 +    \93ADD_CIPHER_KEY\94 command.
75786 +
75787 +Command
75788 +    TBD
75789 +
75790 +Command Parameters
75791 +    UINT8   keyIndex    Index (0...3) of the key to be deleted
75792 +
75793 +Command Values
75794 +    keyIndex    = 0, 1,2, 3    Key to delete
75795 +
75796 +Reset Value
75797 +    None
75798 +
75799 +Restrictions
75800 +    The host should not delete a key that is currently in use by the AR6000.
75801 +
75802 +See Also
75803 +    \93ADD_CIPHER_KEY\94
75804 +
75805 +=====================================================================
75806 +
75807 +Name
75808 +    DELETE_PSTREAM
75809 +
75810 +Synopsis
75811 +    The host uses this command to delete a prioritized data endpoint created by a
75812 +    previous \93CREATE_PSTREAM\94 command
75813 +
75814 +Command
75815 +    --deleteqos <trafficClass> <tsid>, where:
75816 +
75817 +    <traffic class>
75818 +        = 0    BE
75819 +        = 1    BK
75820 +        = 2    VI
75821 +        = 3    VO
75822 +    <tsid>
75823 +        The TSpec ID; use the -qosqueue option
75824 +        to get the active TSpec IDs for each traffic class
75825 +
75826 +Command Parameters
75827 +    A_UINT8    trafficClass    Indicate the traffic class of the stream
75828 +                            being deleted
75829 +
75830 +Command Values
75831 +    {
75832 +        WMM_AC_BE = 0    Best effort
75833 +        WMM_AC_BK = 1    Background
75834 +        WMM_AC_VI = 2    Video
75835 +        WMM_AC_VO = 3    Voice
75836 +    } TRAFFIC CLASS
75837 +
75838 +    0-15 for TSID
75839 +
75840 +Reply Values
75841 +    N/A
75842 +
75843 +Restrictions
75844 +    This command should only be issued after a \93CREATE_PSTREAM\94 command has
75845 +    successfully created a prioritized stream
75846 +
75847 +See Also
75848 +    \93CREATE_PSTREAM\94
75849 +
75850 +=====================================================================
75851 +
75852 +
75853 +Name
75854 +    DELETE_WOW_PATTERN
75855 +
75856 +Synopsis
75857 +    The host uses this command to remove a pre-specified pattern from the
75858 +    WoW pattern list.
75859 +
75860 +Command
75861 +    wmiconfig \96delwowpattern <list-id> <pattern-id>
75862 +
75863 +Command Parameters
75864 +    A_UINT8    filter_list_id    ID of the list that contains the WoW filter
75865 +                                 pattern to delete
75866 +    A_UINT8    filter_id    ID of the WoW filter pattern to delete
75867 +
75868 +Reply Parameters
75869 +    None
75870 +
75871 +
75872 +
75873 +Reset Value
75874 +    None defined
75875 +
75876 +Restrictions
75877 +    None
75878 +
75879 +See Also
75880 +    \93ADD_WOW_PATTERN\94
75881 +
75882 +=====================================================================
75883 +
75884 +
75885 +Name
75886 +    EXTENSION
75887 +
75888 +Synopsis
75889 +    The WMI message interface is used mostly for wireless control messages to a wireless
75890 +    module applicable to wireless module management regardless of the target platform
75891 +    implementation. However, some commands only peripherally related to wireless
75892 +    management are desired during operation. These wireless extension commands may
75893 +    be platform-specific or implementation-dependent.
75894 +
75895 +Command
75896 +    N/A
75897 +
75898 +Command Parameters
75899 +    Command-specific
75900 +
75901 +Command Values
75902 +    Command-specific
75903 +
75904 +Reply Parameters
75905 +    Command-specific
75906 +
75907 +Reset Values
75908 +    None defined
75909 +
75910 +Restrictions
75911 +    None defined
75912 +
75913 +=====================================================================
75914 +
75915 +
75916 +Name
75917 +    GET_BIT_RATE
75918 +
75919 +Synopsis
75920 +    Used by the host to obtain the rate most recently used by the AR6000 device
75921 +
75922 +Command
75923 +    wmiconfig eth1 --getfixrates
75924 +
75925 +Command Parameters
75926 +    None
75927 +
75928 +
75929 +
75930 +Reply Parameters
75931 +    INT8
75932 +    rateIndex
75933 +    See the \93SET_BIT_RATE\94 command
75934 +
75935 +Reset Values
75936 +    None
75937 +
75938 +Restrictions
75939 +    This command should only be used during development/debug; it is not intended
75940 +for use in production. It is only valid when the device is in the CONNECTED state
75941 +
75942 +See Also
75943 +    \93SET_BIT_RATE\94
75944 +
75945 +=====================================================================
75946 +
75947 +
75948 +Name
75949 +    GET_CHANNEL_LIST
75950 +
75951 +Synopsis
75952 +    Used by the host uses to retrieve the list of channels that can be used by the device
75953 +    while in the current wireless mode and in the current regulatory domain.
75954 +
75955 +Command
75956 +    TBD
75957 +
75958 +Command Parameters
75959 +    None
75960 +
75961 +Reply Parameters
75962 +    UINT8    reserved    Reserved
75963 +    UINT8    numberOfChannels    Number of channels the reply contains
75964 +    UINT16    channelList[numberOfChannels]  Array of channel frequencies (in MHz)
75965 +
75966 +Reset Values
75967 +    None defined
75968 +
75969 +Restrictions
75970 +    The maximum number of channels that can be reported are 32
75971 +
75972 +=====================================================================
75973 +
75974 +
75975 +Name
75976 +    GET_FIXRATES
75977 +
75978 +Synopsis
75979 +    Clears the current calculated RSSI and SNR value. RSSI and SNR are reported by
75980 +    running-average value. This command will clear the history and have a fresh start for
75981 +    the running-average mechanism.
75982 +
75983 +Synopsis
75984 +    This returns rate-mask set via WMI_SET_FIXRATES to retrieve the current fixed rate
75985 +    that the AR6001 or AR6001 is using. See \93SET_FIXRATES\94.
75986 +
75987 +Command
75988 +    wmiconfig eth1 --getfixrates
75989 +
75990 +Command Parameters
75991 +    A_UINT16    fixRateMask;    Note: if this command is used prior to
75992 +                using WMI_SET_FIXRATES, AR6000
75993 +                returns 0xffff as fixRateMask, indicating
75994 +                all the rates are enabled
75995 +
75996 +Reply Parameters
75997 +    None
75998 +
75999 +Reset Value
76000 +    None defined
76001 +
76002 +Restrictions
76003 +    None
76004 +
76005 +See Also
76006 +    \93SET_FIXRATES\94
76007 +
76008 +=====================================================================
76009 +
76010 +
76011 +
76012 +Name
76013 +    GET_PMKID_LIST_CMD
76014 +
76015 +Synopsis
76016 +    Retrieves the list of PMKIDs on the firmware. The
76017 +    WMI_GET_PMKID_LIST_EVENT is generated by the firmware.
76018 +
76019 +Command
76020 +    TBD
76021 +
76022 +Command Parameters
76023 +
76024 +Reset Values
76025 +    None
76026 +
76027 +Restrictions
76028 +    None
76029 +
76030 +See Also
76031 +    SET_PMKID_LIST_CMD GET_PMKID_LIST_EVENT
76032 +
76033 +=====================================================================
76034 +
76035 +
76036 +Name
76037 +    GET_ROAM_TBL
76038 +
76039 +Synopsis
76040 +    Retrieve the roaming table maintained on the target. The response is reported
76041 +    asynchronously through the ROAM_TBL_EVENT.
76042 +
76043 +Command
76044 +    wmiconfig --getroamtable <roamctrl> <info>
76045 +
76046 +Command Parameters
76047 +    A_UINT8    roamCtrlType;
76048 +    A_UINT16   roamMode
76049 +    A_UINT16   numEntries
76050 +    WMI_BSS_ROAM_INFO bssRoamInfo[1]
76051 +
76052 +Reply Value
76053 +    Reported asynchronously through the ROAM_TBL_EVENT
76054 +
76055 +Reset Value
76056 +    None defined
76057 +
76058 +Restrictions
76059 +    None
76060 +
76061 +See Also
76062 +    SET_KEEPALIVE
76063 +
76064 +=====================================================================
76065 +
76066 +
76067 +Name
76068 +    GET_TARGET_STATS
76069 +
76070 +Synopsis
76071 +    The host uses this command to request that the target send the statistics that it
76072 +    maintains. The statistics obtained from the target are accrued in the host every time
76073 +    the GET_TARGET_STATS command is issued. The --clearStats option is added to
76074 +    clear the target statistics maintained in the host.
76075 +
76076 +Command
76077 +    wmiconfig --getTargetStats --clearStats
76078 +
76079 +Command Parameters
76080 +    TARGET_STATS    targetStats
76081 +    WMI_TARGET_STATS
76082 +    UINT8   clearStats
76083 +
76084 +
76085 +Reply Value
76086 +    RSSI return value (0\96100)
76087 +
76088 +Reset Values
76089 +    All statistics are cleared (zeroed)
76090 +
76091 +Restrictions
76092 +    The --getTargetStats option must be used; the --clearStats option is also available also
76093 +
76094 +
76095 +=====================================================================
76096 +
76097 +Name
76098 +    GET_TX_PWR
76099 +
76100 +Synopsis
76101 +    The host uses this command to retrieve the current Tx power level
76102 +
76103 +Command
76104 +    wmiconfig -i eth1 --getpower
76105 +
76106 +Command Parameters
76107 +    None
76108 +
76109 +Reply Parameters
76110 +    UINT16 dbM    The current Tx power level specified in dbM
76111 +
76112 +Reset Values
76113 +    The maximum permitted by the regulatory domain
76114 +
76115 +Restrictions
76116 +    None
76117 +
76118 +See Also
76119 +    \93SET_TX_PWR\94
76120 +
76121 +=====================================================================
76122 +
76123 +
76124 +Name
76125 +    GET_WOW_LIST
76126 +
76127 +Synopsis
76128 +    The host uses this command to retrieve the current list of WoW patterns.
76129 +
76130 +Command
76131 +    wmiconfig \96getwowlist <list-id>
76132 +
76133 +Command Parameters
76134 +    A_UINT8 filter_list_id    ID of the list of WoW patterns to retrieve
76135 +
76136 +Reply Value(s)
76137 +    A_UINT16  num_filters    Number of WoW patterns contained in the list
76138 +    A_UINT8   wow_mode    Current mode of WoW (enabled or disabled)
76139 +    A_UINT8    host_mode    Current host mode (asleep or awake)
76140 +    WOW_FILTER    wow_filters[1]
76141 +        Contents of the WoW filter pattern list
76142 +        (contains mask, pattern, offset and size
76143 +    information for each of the patterns)
76144 +
76145 +Reset Value
76146 +    None defined
76147 +
76148 +Restrictions
76149 +    None
76150 +
76151 +See Also
76152 +    \93SET_WSC_STATUS\94
76153 +
76154 +=====================================================================
76155 +
76156 +
76157 +Name
76158 +    LQ_THRESHOLD_PARAMS
76159 +
76160 +Synopsis
76161 +    Sets Link Quality thresholds, the sampling will happen at every unicast data frame
76162 +    Tx if a certain threshold is met, and the corresponding event will be sent to the host.
76163 +
76164 +Command
76165 +    --lqThreshold <enable> <upper_threshold_1> ...
76166 +    <upper_threshold_4> <lower_threshold_1> ... <lower_threshold_4>
76167 +
76168 +Command Parameters
76169 +    <enable>    = 0    Disable link quality sampling
76170 +                = 1    Enable link quality sampling
76171 +    <upper_threshold_x>  Above thresholds (value in [0,100]), in
76172 +                    ascending order
76173 +    <lower_threshold_x> Below thresholds (value in [0,100]), in
76174 +                    ascending order
76175 +
76176 +Command Values
76177 +    See command parameters
76178 +
76179 +Reset Value
76180 +    None defined
76181 +
76182 +Restrictions
76183 +    None
76184 +
76185 +=====================================================================
76186 +
76187 +
76188 +Name
76189 +    OPT_TX_FRAME
76190 +
76191 +Synopsis
76192 +    Special feature, sends a special frame.
76193 +
76194 +Command
76195 +    wmiconfig --sendframe <frmType> <dstaddr> <bssid> <optIEDatalen>
76196 +    <optIEData>
76197 +
76198 +Command Parameters
76199 +    {
76200 +        A_UINT16    optIEDataLen;
76201 +        A_UINT8    frmType;
76202 +        A_UINT8    dstAddr[ATH_MAC_LEN];
76203 +        A_UINT8    bssid[ATH_MAC_LEN];
76204 +        A_UINT8    optIEData[1];
76205 +    } WMI_OPT_TX_FRAME_CMD;
76206 +
76207 +Command Values
76208 +    <frmtype>   = 1    Probe request frame
76209 +                = 2    Probe response frame
76210 +                = 3    CPPP start
76211 +                = 4    CPPP stop
76212 +
76213 +Reset Value
76214 +    None defined
76215 +
76216 +Restrictions
76217 +    Send a special frame only when special mode is on.
76218 +
76219 +=====================================================================
76220 +
76221 +
76222 +Name
76223 +    RECONNECT
76224 +
76225 +Synopsis
76226 +    This command requests a reconnection to a BSS to which the AR6000 device was
76227 +    formerly connected
76228 +
76229 +Command
76230 +    TBD
76231 +
76232 +Command Parameters
76233 +    UINT16    channel    Provides a hint as to which channel was
76234 +                        used for a previous connection
76235 +    UINT8    bssid[6]    If set, indicates which BSSID to connect to
76236 +
76237 +Command Values
76238 +    None
76239 +
76240 +Reset Values
76241 +    None
76242 +
76243 +Restrictions
76244 +    None
76245 +
76246 +See Also
76247 +    \93CONNECT_CMD\94
76248 +
76249 +=====================================================================
76250 +
76251 +
76252 +Name
76253 +    RSSI_THRESHOLD_PARAMS
76254 +
76255 +Synopsis
76256 +    Configures how the AR6000 device monitors and reports signal strength (RSSI) of the
76257 +    connected BSS, which is used as a link quality metric. The four RSSI threshold sets (in
76258 +    dbM) of the host specification divide the signal strength range into six segments.
76259 +    When signal strength increases or decreases across one of the boundaries, an
76260 +    RSSI_THRESHOLD event is signaled to the host. The host may then choose to take
76261 +    action (such as influencing roaming).
76262 +
76263 +Command
76264 +    wmiconfig eth1 --rssiThreshold <weight> <pollTime>
76265 +        <above_threshold_val_1> ... <above_threshold_tag_6>
76266 +        <above_threshold_val_6>
76267 +        <below_threshold_tag_1> <below_threshold_val_1> ...
76268 +        <below_threshold_tag_6> <below_threshold_val_6>
76269 +
76270 +Command Parameters
76271 +    UINT8    weight    Range in [1, 16] used to calculate average RSSI
76272 +    UINT32   pollTime   RSSI (signal strength) sampling frequency in
76273 +                seconds (if pollTime = 0, single strength
76274 +        sampling is disabled)
76275 +    USER_RSS__THOLD tholds[12]  Thresholds (6 x 2)
76276 +
76277 +Command Values
76278 +    None defined
76279 +
76280 +Reset Values
76281 +    pollTime is 0, and sampling is disabled
76282 +
76283 +Restrictions
76284 +    Can only be issued if the AR6000 device is connected
76285 +
76286 +
76287 +=====================================================================
76288 +
76289 +Name
76290 +    SCAN_PARAMS
76291 +
76292 +Synopsis
76293 +    The minact parameter determines the minimum active channel dwell time, within
76294 +    which if the STA receives any beacon, it remains on that channel until the maxact
76295 +    channel dwell time. If the STA does not receive a beacon within the minact dwell
76296 +    time, it switches to scan the next channel.
76297 +
76298 +Command
76299 +    wmiconfig -scan -minact=<ms> --maxact=<ms>
76300 +
76301 +Command Parameters
76302 +    UINT16    maxact    Channel dwell time (in ms), default = 0
76303 +    UINT16    minact    Channel dwell time (in ms), default = 105
76304 +
76305 +Command Values
76306 +    See channel parameters
76307 +
76308 +Reset Values
76309 +    None defined
76310 +
76311 +Restrictions
76312 +    The minact value should be greater than 0; maxact should be between 5\9665535 ms
76313 +    and greater than minact
76314 +
76315 +=====================================================================
76316 +
76317 +
76318 +Name
76319 +    SET_ACCESS_PARAMS
76320 +
76321 +Synopsis
76322 +    Allows the host to set access parameters for the wireless network. A thorough
76323 +    understanding of IEEE 802.11 is required to properly manipulate these parameters.
76324 +
76325 +Command
76326 +    wmiconfig eth1 --acparams --txop <limit> --cwmin <0-15>
76327 +    --cwmax <0-15> --aifsn<0-15>
76328 +
76329 +Command Parameters
76330 +    UINT16    txop    The maximum time (expressed in units of
76331 +                        32 ms) the device can spend transmitting
76332 +                        after acquiring the right to transmit
76333 +    UINT8    eCWmin    Minimum contention window
76334 +    UINT8    eCWmax    Maximum contention window
76335 +    UINT8    aifsn    The arbitration inter-frame space number
76336 +
76337 +Command Values
76338 +    None
76339 +
76340 +Reset Values
76341 +    Reasonable defaults that vary, between endpoints (prioritized streams)
76342 +
76343 +Restrictions
76344 +    None
76345 +
76346 +=====================================================================
76347 +
76348 +
76349 +Name
76350 +    SET_ADHOC_BSSID
76351 +
76352 +Synopsis
76353 +    Allows the host to set the BSSID for an ad hoc network. If a network with this BSSID
76354 +    is not found, the target creates an ad hoc network with this BSSID after the connect
76355 +    WMI command is triggered (e.g., by the SIOCSIWESSID IOCTL).
76356 +
76357 +Command
76358 +    wmiconfig eth1 --adhocbssid <bssid>
76359 +
76360 +Command Parameters
76361 +    A_UINT8     bssid[ATH_MAC_LEN]    BSSID is specified in xx:xx:xx:xx:xx:xx format
76362 +
76363 +Command Values
76364 +    None
76365 +
76366 +Reset Values
76367 +    None
76368 +
76369 +Restrictions
76370 +    None
76371 +
76372 +=====================================================================
76373 +
76374 +
76375 +Name
76376 +    SET_AKMP_PARAMS
76377 +
76378 +Synopsis
76379 +    Enables or disables multi PMKID mode.
76380 +
76381 +Command
76382 +    wmiconfig eth1 --setakmp --multipmkid=<on/off>
76383 +
76384 +Command Parameters
76385 +    typedef struct {
76386 +      A_UINT32    akmpInfo;
76387 +    } WMI_SET_AKMP_PARAMS_CMD;
76388 +
76389 +Command Values
76390 +    akmpInfo;
76391 +    bit[0] = 0
76392 +        MultiPMKID mode is disabled and PMKIDs that
76393 +        were set using the WMI_SET_PMKID_CMD are
76394 +        used in the [Re]AssocRequest frame.
76395 +     bit[0] = 1
76396 +        MultiPMKID mode is enabled and PMKIDs issued
76397 +        by the WMI_SET_PMKID_LIST_CMD are used in
76398 +        the next [Re]AssocRequest sent to the AP.
76399 +
76400 +Reset Values
76401 +    MultiPMKID mode is disabled
76402 +
76403 +Restrictions
76404 +    None
76405 +
76406 +=====================================================================
76407 +
76408 +
76409 +Name
76410 +    SET_APPIE
76411 +
76412 +Synopsis
76413 +    Add an application-specified IE to a management frame. The maximum length is
76414 +    76 bytes. Including the length and the element ID, this translates to 78 bytes.
76415 +
76416 +Command
76417 +    wmiconfig --setappie <frame> <IE>, where:
76418 +
76419 +    frame
76420 +        One of beacon, probe, respon, assoc
76421 +
76422 +    IE
76423 +        A hex string beginning with DD (if = 0, no
76424 +        IE is sent in the management frame)
76425 +
76426 +Command Parameters
76427 +    mgmtFrmType;
76428 +        A WMI_MGMT_FRAME_TYPE
76429 +
76430 +    ieLen;
76431 +        Length of the IE to add to the GMT frame
76432 +
76433 +Command Values
76434 +    None
76435 +
76436 +Reset Value
76437 +    None defined
76438 +
76439 +Restrictions
76440 +    Supported only for the probe request and association request management frame
76441 +types. Also, only one IE can be added per management frame type.
76442 +
76443 +=====================================================================
76444 +
76445 +
76446 +Name
76447 +    SET_ASSOC_INFO
76448 +
76449 +Synopsis
76450 +    The host uses this command to specify any information elements (IEs) it wishes the
76451 +    AR6000 device to add to all future association and reassociation requests. IEs must be
76452 +    correct and are used as is by the device. IEs specified through this command are
76453 +    cleared with a DISCONNECT.
76454 +
76455 +Command
76456 +    wmiconfig eth1 --setAssocIe <IE>
76457 +
76458 +Command Parameters
76459 +    UINT8    ieType    Used directly in 802.11 frames
76460 +    UINT8    bufferSize    Size of assocInfo (in bytes) ranging from
76461 +                        0\96240. If = 0, previously set IEs are cleared.
76462 +    UINT8    assocInfo[bufferSize]    Used directly in 802.11 frames
76463 +
76464 +Command Values
76465 +    None
76466 +
76467 +Reset Values
76468 +    IEs are cleared
76469 +
76470 +Restrictions
76471 +    This command can only be issued in the DISCONNECTED state
76472 +
76473 +=====================================================================
76474 +
76475 +
76476 +Name
76477 +    SET_AUTHMODE
76478 +
76479 +Synopsis
76480 +    Sets the 802.11 authentication mode of reconnection
76481 +
76482 +Command
76483 +    wmiconfig eth1 --setauthmode <mode>
76484 +
76485 +Command Parameters
76486 +    UINT8    mode
76487 +
76488 +Command Values
76489 +    mode    = 0x00    Proceed with authentication during reconnect
76490 +            = 0x01    Do not proceed with authentication during reconnect
76491 +
76492 +Reset Values
76493 +    Authentication
76494 +
76495 +Restrictions
76496 +    None
76497 +
76498 +=====================================================================
76499 +
76500 +
76501 +Name
76502 +    SET_BEACON_INT
76503 +
76504 +Synopsis
76505 +    Sets the beacon interval for an ad hoc network. Beacon interval selection may have an
76506 +    impact on power savings. To some degree, a longer interval reduces power
76507 +    consumption but also decreases throughput. A thorough understanding of IEEE
76508 +    802.11 ad hoc networks is required to use this command effectively.
76509 +
76510 +Command
76511 +    wmiconfig eth1 --ibssconintv
76512 +
76513 +Command Parameters
76514 +    UINT16    beaconInterval    Specifies the beacon interval in TU units (1024 ms)
76515 +
76516 +Command Values
76517 +    None
76518 +
76519 +Reset Values
76520 +    The default beacon interval is 100 TUs (102.4 ms)
76521 +
76522 +Restrictions
76523 +    This command can only be issued before the AR6000 device starts an ad hoc network
76524 +
76525 +See Also
76526 +    \93SET_IBSS_PM_CAPS\94
76527 +
76528 +=====================================================================
76529 +
76530 +
76531 +Name
76532 +    SET_BIT_RATE
76533 +
76534 +Synopsis
76535 +    The host uses this command to set the AR6000 device to a specific fixed rate.
76536 +
76537 +Command
76538 +    wmiconfig eth1 --setfixrates <rate_0> ... <rate_n>
76539 +
76540 +Command Parameters
76541 +    INT8    rateIndex
76542 +    A WMI_BIT_RATE value
76543 +    {
76544 +        RATE_AUTO    = -1
76545 +        RATE_1Mb     = 0
76546 +        RATE_2Mb     = 1
76547 +        RATE_5_5M    = 2
76548 +        RATE_11Mb    = 3
76549 +        RATE_6Mb     = 4
76550 +        RATE_9Mb     = 5
76551 +        RATE_12Mb    = 6
76552 +        RATE_18Mb    = 7
76553 +        RATE_24Mb    = 8
76554 +        RATE_36Mb    = 9
76555 +        RATE_48Mb    = 10
76556 +        RATE_54Mb    = 11
76557 +      } WMI_BIT_RATE
76558 +
76559 +
76560 +Command Values
76561 +    See command parameters
76562 +
76563 +Reset Values
76564 +    The dynamic rate is determined by the AR6000 device
76565 +
76566 +Restrictions
76567 +    This command is intended for use only during development/debug; it is not
76568 +intended for use in production
76569 +
76570 +See Also
76571 +    \93GET_BIT_RATE\94
76572 +
76573 +=====================================================================
76574 +
76575 +
76576 +Name
76577 +    SET_BMISS_TIME
76578 +
76579 +Synopsis
76580 +    This command sets the beacon miss (BMISS) time, which the AR6000 hardware use
76581 +    to recognize missed beacons. When an excessive number (15) of consecutive beacons
76582 +    are missed, the AR6000 consider switching to a different BSS. The time can be
76583 +    specified in number of beacons or in TUs.
76584 +
76585 +Command(s)
76586 +    wmiconfig eth1 --setbmissbeacons=<val>
76587 +    wmiconfig eth1 --setbmisstime=<val>
76588 +
76589 +Command Parameters
76590 +    UINT16    bmissTime    Specifies the beacon miss time
76591 +                            [1000...5000] in TUs (1024 ms)
76592 +    UINT16    bmissbeacons  Specifies the number of beacons [5...50]
76593 +
76594 +Command Values
76595 +    None
76596 +
76597 +Reset Values
76598 +    bmissTime is 1500 TUs (1536 ms)
76599 +
76600 +Restrictions
76601 +    None
76602 +
76603 +=====================================================================
76604 +
76605 +
76606 +Name
76607 +    SET_BSS_FILTER
76608 +
76609 +Synopsis
76610 +    The host uses this to inform the AR6000 device of the types of networks about which
76611 +    it wants to receive information from the \93BSSINFO\94 event. As the device performs
76612 +    either foreground or background scans, it applies the filter and sends \93BSSINFO\94
76613 +    events only for the networks that pass the filter. If any of the  bssFilter or the ieMask
76614 +    filter matches, a BSS Info is sent to the host. The ieMask currently is used as a match
76615 +    for the IEs in the beacons, probe reponses and channel switch action management
76616 +    frame. See also \93Scan and Roam\94 on page C-1.
76617 +
76618 +    The BSS filter command has been enhanced to support IE based filtering. The IEs can
76619 +    be specified as a bitmask through this command using this enum.
76620 +
76621 +Command
76622 +    wmiconfig eth1 \96filter = <filter> --ieMask 0x<mask>
76623 +
76624 +Command Parameters
76625 +    UINT8    BssFilter
76626 +
76627 + Command Values
76628 +    typedef struct {
76629 +        A_UINT8    bssFilter;    See WMI_BSS_FILTER
76630 +        A_UINT32    ieMask;
76631 +    } __ATTRIB_PACK WMI_BSS_FILTER_CMD;
76632 +
76633 +    The ieMask can take this combination of values:
76634 +
76635 +    enum {
76636 +        BSS_ELEMID_CHANSWITCH   = 0x01
76637 +        BSS_ELEMID_ATHEROS      = 0x02,
76638 +    }
76639 +
76640 +Reply Value
76641 +    None
76642 +
76643 +Reset Value
76644 +    BssFilter = NONE_BSS_FILTER (0)
76645 +
76646 +Restrictions
76647 +    None
76648 +
76649 +See Also
76650 +    \93CONNECT_CMD\94
76651 +
76652 +=====================================================================
76653 +
76654 +
76655 +Name
76656 +    SET_BT_PARAMS
76657 +
76658 +Synopsis
76659 +    This command is used to set the status of a Bluetooth stream or set Bluetooth
76660 +    coexistence register parameters. The stream may be an SCO or an A2DP stream and
76661 +    its status can be started/stopped/suspended/resumed.
76662 +
76663 +Command
76664 +    wmiconfig \96setBTparams <paramType> <params>
76665 +
76666 +Command Parameters
76667 +    struct {
76668 +       union {
76669 +            BT_PARAMS_SCO    scoParams;
76670 +            BT_PARAMS_A2DP   a2dpParams;
76671 +            BT_PARAMS_MISC   miscParams;
76672 +            BT_COEX_REGS     regs;
76673 +        } info;
76674 +         A_UINT8 paramType;
76675 +        struct {
76676 +            A_UINT8 noSCOPkts;    Number of SCO packets between consecutive PS-POLLs
76677 +            A_UINT8 pspollTimeout;
76678 +            A_UINT8 stompbt;
76679 +        } BT_PARAMS_SCO;
76680 +        struct {
76681 +            A2DP BT stream parameters
76682 +            A_UINT32   period;
76683 +            A_UINT32   dutycycle;
76684 +            A_UINT8    stompbt;
76685 +        } BT_PARAMS_A2DP;
76686 +        struct {
76687 +            union {
76688 +               WLAN_PROTECT_POLICY_TYPE   protectParams;
76689 +               A_UINT16    wlanCtrlFlags;
76690 +            }info;
76691 +        A_UINT8 paramType;
76692 +        } BT_PARAMS_MISC;
76693 +        struct {
76694 +            BT coexistence registers values
76695 +            A_UINT32    mode;     Coexistence mode
76696 +            A_UINT32    scoWghts; WLAN and BT weights
76697 +            A_UINT32    a2dpWghts;
76698 +            A_UINT32    genWghts;
76699 +            A_UINT32    mode2;    Coexistence mode2
76700 +            A_UINT8    setVal;
76701 +        } BT_COEX_REGS;
76702 +
76703 +Command Values
76704 +    None defined
76705 +
76706 +Reset Value
76707 +    None
76708 +
76709 +Restrictions
76710 +    None
76711 +
76712 +=====================================================================
76713 +
76714 +
76715 +Name
76716 +    SET_BT_STATUS
76717 +
76718 +Synopsis
76719 +    Sets the status of a Bluetooth stream. The stream may be a SCO or an A2DP stream
76720 +    and its status can be started/stopped/suspended/resumed.
76721 +
76722 +Command
76723 +    wmiconfig \96setBTstatus <streamType> <status>
76724 +
76725 +Command Parameters
76726 +    {
76727 +        A_UINT8        streamType;    Stream type
76728 +        A_UINT8        status;    Stream status
76729 +    }WMI_SET_BT_STATUS_CMD;
76730 +
76731 +Command Values
76732 +    {
76733 +        BT_STREAM_UNDEF    = 0
76734 +        BT_STREAM_SCO
76735 +        SCO stream
76736 +        BT_STREAM_A2DP
76737 +        A2DP stream
76738 +        BT_STREAM_MAX
76739 +    } BT_STREAM_TYPE;
76740 +
76741 +    {
76742 +        BT_STATUS_UNDEF    = 0
76743 +        BT_STATUS_START
76744 +        BT_STATUS_STOP
76745 +        BT_STATUS_RESUME
76746 +        BT_STATUS_SUSPEND
76747 +        BT_STATUS_MAX
76748 +    } BT_STREAM_STATUS;
76749 +
76750 +Reset Value
76751 +    None defined
76752 +
76753 +Restrictions
76754 +    None
76755 +
76756 +=====================================================================
76757 +
76758 +
76759 +Name
76760 +    SET_CHANNEL_PARAMETERS
76761 +
76762 +Synopsis
76763 +    Configures various WLAN parameters related to channels, sets the wireless mode,
76764 +    and can restrict the AR6000 device to a subset of available channels. The list of
76765 +    available channels varies depending on the wireless mode and the regulatory
76766 +    domain. The device never operates on a channel outside of its regulatory domain. The
76767 +    device starts to scan the list of channels right after this command.
76768 +
76769 +Command
76770 +    wmiconfig eth1 --wmode <mode> <list>
76771 +
76772 +Command Parameters
76773 +    UINT8    phyMode    See Values below.
76774 +    UINT8    numberOfChannels
76775 +        Number of channels in the channel array that
76776 +        follows. If = 0, then the device uses all of the
76777 +        channels permitted by the regulatory domain
76778 +        and by the specified phyMode.
76779 +    UINT16    channel[numberOfChannels]
76780 +        Array listing the subset of channels (expressed
76781 +        as frequencies in MHz) the host wants the
76782 +        device to use. Any channel not permitted by
76783 +        the specified phyMode or by the specified
76784 +        regulatory domain is ignored by the device.
76785 +
76786 +Command Values
76787 +    phyMode = {
76788 +        Wireless mode
76789 +        11a    = 0x01
76790 +        11g    = 0x02
76791 +        11ag   = 0x03
76792 +        11b    = 0x04
76793 +        11g only    = 0x05
76794 +        }
76795 +
76796 +Reset Values
76797 +    phyMode
76798 +    11ag
76799 +    802.11a/g modules
76800 +        11g
76801 +    802.11g module
76802 +    channels
76803 +        Defaults to all channels permitted by the
76804 +        current regulatory domain.
76805 +
76806 +Restrictions
76807 +    This command, if issued, should be issued soon after reset and prior to the first
76808 +    connection. This command should only be issued in the DISCONNECTED state.
76809 +
76810 +=====================================================================
76811 +
76812 +
76813 +Name
76814 +    SET_DISC_TIMEOUT
76815 +
76816 +Synopsis
76817 +    The host uses this command to configure the amount of time that the AR6000 should
76818 +    spend when it attempts to reestablish a connection after losing link with its current
76819 +    BSS. If this time limit is exceeded, the AR6000 send a \93DISCONNECT\94 event. After
76820 +    sending the \93DISCONNECT\94 event the AR6000 continues to attempt to reestablish a
76821 +    connection, but they do so at the interval corresponding to a foreground scan as
76822 +    established by the \93SET_SCAN_PARAMS\94 command.
76823 +
76824 +    A timeout value of 0 indicates that the AR6000 will disable all autonomous roaming,
76825 +    so that the AR6000 will not perform any scans after sending a \93DISCONNECT\94
76826 +    event to the host. The state is maintained until a shutdown or host sets different
76827 +    timeout value from 0.
76828 +
76829 +Command
76830 +    wmiconfig eth1 --disc=<timeout in seconds>
76831 +
76832 +Command Parameters
76833 +    UINT8    disconnectTimeout
76834 +        Specifies the time limit (in seconds) after
76835 +        which a failure to reestablish a connection
76836 +        results in a \93DISCONNECT\94 event
76837 +
76838 +Command Values
76839 +    None
76840 +
76841 +Reset Values
76842 +    disconnectTimeout is 10 seconds
76843 +
76844 +Restrictions
76845 +    This command can only be issued while in a DISCONNECTED state
76846 +
76847 +=====================================================================
76848 +
76849 +
76850 +Name
76851 +    SET_FIXRATES
76852 +
76853 +Synopsis
76854 +    By default, the AR6000 device uses all PHY rates based on mode of operation. If the
76855 +    host application requires the device to use subset of supported rates, it can set those
76856 +    rates with this command. In 802.11g mode, the AR6000 device takes the entire
76857 +    802.11g basic rate set and the rates specified with this command and uses it as the
76858 +    supported rate set.
76859 +
76860 +    This rate set is advertised in the probe request and the assoc/re-assoc request as
76861 +    supported rates. Upon successful association, the device modifies the rate set pool
76862 +    using the: intersection of AP-supported rates with the union of the 802.11g basic rate
76863 +    set and rates set using this command. The device picks transmission rates from this
76864 +    pool based on a rate control algorithm.
76865 +
76866 +Command
76867 +    TBD
76868 +
76869 +Command Parameters
76870 +    A_UINT16    fixRateMask;
76871 +        The individual bit is an index for rate table,
76872 +        and setting the that index to 1 would set that
76873 +        corresponding rate. E.g., fixRateMask = 9
76874 +        (1001) sets 1 Mbps and 11 Mbps.
76875 +
76876 +Command Values
76877 +    None
76878 +
76879 +Reset Value
76880 +    None defined
76881 +
76882 +Restrictions
76883 +    None
76884 +
76885 +See Also
76886 +    \93GET_FIXRATES\94
76887 +
76888 +=====================================================================
76889 +
76890 +
76891 +Name
76892 +    SET_WHAL_PARAM
76893 +
76894 +Synopsis
76895 +    An internal AR6000 command that is used to set certain hardware parameters. The
76896 +    description of this command is in $WORKAREA/include/halapi.h.
76897 +
76898 +Command
76899 +    TBD
76900 +
76901 +Command Parameters
76902 +    ATH_HAL_SETCABTO_CMDID
76903 +        Sets the timeout waiting for the multicast
76904 +        traffic after a DTIM beacon (in TUs).
76905 +
76906 +Command Values
76907 +    None
76908 +
76909 +Reset Value
76910 +    Default = 10 TUs
76911 +
76912 +Restrictions
76913 +    This command should be executed before issuing a connect command.
76914 +
76915 +=====================================================================
76916 +
76917 +
76918 +Name
76919 +    SET_HOST_SLEEP_MODE
76920 +
76921 +Synopsis
76922 +    The host uses this command to set the host mode to asleep or awake. All packets are
76923 +    delivered to the host when the host mode is awake. When host mode is asleep, only if
76924 +    WoW is enabled and the incoming packet matches one of the specified WoW
76925 +    patterns, will the packet be delivered to the host. The host will also be woken up by
76926 +    the target for pattern-matching packets and important events.
76927 +
76928 +Command
76929 +    wmiconfig \96sethostmode=<asleep/awake>
76930 +
76931 +Command Parameters
76932 +    A_BOOL    awake    Set the host mode to awake
76933 +    A_BOOL    asleep   Set the host mode to asleep
76934 +
76935 +Command Values
76936 +    1 = awake, 0 = asleep
76937 +
76938 +Reset Value
76939 +    None defined (default host mode is awake)
76940 +
76941 +Restrictions
76942 +    None
76943 +
76944 +
76945 +=====================================================================
76946 +
76947 +Name
76948 +    SET_IBSS_PM_CAPS
76949 +
76950 +Synopsis
76951 +    Used to support a non-standard power management scheme for an ad hoc wireless
76952 +    network consisting of up to eight stations (STAs) that support this form of power
76953 +    saving (e.g., Atheros-based STAs). A thorough understanding of IEEE 802.11 ad hoc
76954 +    networks is required to use this command effectively.
76955 +
76956 +Command
76957 +    wmiconfig eth1 --ibsspmcaps --ps=<enable/disable>
76958 +        --aw=<ATIM Windows in ms>
76959 +        --ttl=<Time to live in number of beacon periods>
76960 +        --to=<timeout in ms>
76961 +
76962 +Command Parameters
76963 +    UINT8    power_saving
76964 +        = 0
76965 +        The non-standard power saving scheme is
76966 +        disabled and maximum throughput (with no
76967 +        power saving) is obtained.
76968 +
76969 +        = 1
76970 +        Ad hoc power saving scheme is enabled (but
76971 +        throughput may be decreased)
76972 +
76973 +    UINT16    atim_windows
76974 +        Specifies the length (in ms) of the ad hoc traffic
76975 +        indication message (ATIM) windows used in an ad
76976 +        hoc network. All Atheros-based STAs that join the
76977 +        network use this duration ATIM window.
76978 +
76979 +    The duration is communicated between wireless
76980 +    STAs through an IE in beacons and probe responses.
76981 +
76982 +    The host sets atim_windows to control trade-offs
76983 +    between power use and throughput. The value
76984 +    chosen should be based on the beacon interval (see
76985 +    the \93SET_BEACON_INT\94 command) on the
76986 +    expected number of STAs in the IBSS, and on the
76987 +    amount of traffic and traffic patterns between STAs.
76988 +
76989 +    UINT16    timeout_value
76990 +        Specifies the timeout (in ms). The value is the same
76991 +        for all ad hoc connections, but tracks separately for
76992 +        each.
76993 +
76994 +        Applicable only for a beacon period and used to
76995 +        derive actual timeout values on the Tx and Rx sides.
76996 +        On the Tx side, the value defines a window during
76997 +        which the STA accepts the frame(s) from the host for a
76998 +        particular connection. Until closed, the window
76999 +        restarts with every frame received from the host. On
77000 +        the Rx side, indicates the time until which the STA
77001 +        continues accepting frames from a particular
77002 +        connection. The value resets with every frame
77003 +        received. The value can be used to determine the
77004 +        trade off between throughput and power.
77005 +        Default = 10 ms
77006 +
77007 +    UINT8    ttl
77008 +        Specifies the value in number of beacon periods. The
77009 +        value is used to set a limit on the time until which a
77010 +        frame is kept alive in the AR6001 before being
77011 +        discarded. Default = 5
77012 +
77013 +Command Values
77014 +    None
77015 +
77016 +Reset Values
77017 +    By default, power_saving is enabled with atim_window = 20 ms
77018 +
77019 +Restrictions
77020 +    Can only be issued before the AR6000 starts an ad hoc network
77021 +
77022 +See Also
77023 +    \93SET_BEACON_INT\94
77024 +
77025 +=====================================================================
77026 +
77027 +
77028 +
77029 +Name
77030 +    SET_LISTEN_INT
77031 +
77032 +Synopsis
77033 +    The host uses this command to request a listen interval, which determines how often
77034 +    the AR6000 device should wake up and listen for traffic. The listen interval can be set
77035 +    by the TUs or by the number of beacons. The device may not be able to comply with
77036 +    the request (e.g., if the beacon interval is greater than the requested listen interval, the
77037 +    device sets the listen interval to the beacon interval). The actual listen interval used
77038 +    by the device is available in the \93CONNECT\94 event.
77039 +
77040 +Command
77041 +    wmiconfig eth1 --listen=<#of TUs, can range from 15 to 3000>
77042 +
77043 +    --listenbeacons=<#of beacons, can range from 1 to 50>
77044 +
77045 +Command Parameters
77046 +    UINT16    listenInterval
77047 +        Specifies the listen interval in Kms
77048 +        (1024 ms), ranging from 100 to 1000
77049 +
77050 +    UINT16    listenbeacons
77051 +        Specifies the listen interval in beacons,
77052 +        ranging from 1 to 50
77053 +
77054 +Command Values
77055 +    None
77056 +
77057 +Reset Values
77058 +    The device sets the listen interval equal to the beacon interval of the AP it associates
77059 +    to.
77060 +
77061 +Restrictions
77062 +    None
77063 +
77064 +=====================================================================
77065 +
77066 +
77067 +Name
77068 +    SET_LPREAMBLE
77069 +
77070 +Synopsis
77071 +    Overrides the short preamble capability of the AR6000 device
77072 +
77073 +Command
77074 +    TBD
77075 +
77076 +Command Parameters
77077 +    WMI_LPREAMBLE_DISABLED
77078 +        The device is short-preamble capable
77079 +
77080 +    WMI_LPREAMBLE_ENABLED
77081 +        The device supports only the long-
77082 +    preamble mode
77083 +
77084 +Command Values
77085 +    None
77086 +
77087 +Reset Value
77088 +    None defined
77089 +
77090 +Restrictions
77091 +    None
77092 +
77093 +
77094 +=====================================================================
77095 +
77096 +Name
77097 +    SET_MAX_SP_LEN
77098 +
77099 +Synopsis
77100 +    Set the maximum service period; indicates the number of packets the AR6001 can
77101 +    receive from the AP when triggered
77102 +
77103 +Command
77104 +    wmiconfig eth1 --setMaxSPLength <maxSPLen>
77105 +
77106 +Command Parameters
77107 +    UINT8    maxSPLen
77108 +        An APSD_SP_LEN_TYPE value
77109 +
77110 +Command Values
77111 +    {
77112 +        DELIVER_ALL_PKT  = 0x0
77113 +        DELIVER_2_PKT    = 0x1
77114 +        DELIVER_4_PKT    = 0x2
77115 +        DELIVER_6_PKT    = 0x3
77116 +    }APSD_SP_LEN_TYPE
77117 +
77118 +
77119 +Reset Values
77120 +    maxSPLen is DELIVER_ALL_PKT
77121 +
77122 +Restrictions
77123 +    None
77124 +
77125 +=====================================================================
77126 +
77127 +
77128 +Name
77129 +    SET_OPT_MODE
77130 +
77131 +Synopsis
77132 +    Special feature, sets the special mode on/off
77133 +
77134 +Command
77135 +    wmiconfig eth1 --mode <mode>
77136 +    Set the optional mode, where mode is special or off
77137 +
77138 +Command Parameters
77139 +    enum {
77140 +        SPECIAL_OFF
77141 +        SPECIAL_ON
77142 +    } OPT_MODE_TYPE;
77143 +
77144 +Command Values
77145 +
77146 +Reset Value
77147 +    Mode = Off
77148 +
77149 +Restrictions
77150 +    None
77151 +
77152 +=====================================================================
77153 +
77154 +
77155 +Name
77156 +    SET_PMKID
77157 +
77158 +Synopsis
77159 +    The host uses this command to enable or disable a pairwise master key ID (PMKID)
77160 +    in the AR6000 PMKID cache. The AR6000 clears its PMKID cache on receipt of a
77161 +    DISCONNECT command from the host. Individual entries in the cache might be
77162 +    deleted as the AR6000 detect new APs and decides to remove old ones.
77163 +
77164 +Command
77165 +    wmiconfig eth1 --setbsspmkid --bssid=<aabbccddeeff>
77166 +    --bsspmkid=<pmkid>
77167 +
77168 +Command Parameters
77169 +    UINT8    bssid[6]
77170 +        The MAC address of the AP that the
77171 +        PMKID corresponds to (6 bytes in hex
77172 +        format)
77173 +
77174 +    UINT8    enable
77175 +        Either PMKID_DISABLE (0) to disable
77176 +        the PMKID or PMKID_ENABLE (1) to
77177 +        enable it (16 bytes in hex format)
77178 +
77179 +    UINT8    pmkid[16]
77180 +        Meaningful only if enable is
77181 +        PMKID_ENABLE, when it is the PMKID
77182 +        that the AR6000 should use on the next
77183 +        reassociation with the specified AP
77184 +
77185 +Command Values
77186 +    enable
77187 +    = 0 (disable), 1 (enable)
77188 +    PKMID enabled/disabled
77189 +
77190 +Reset Values
77191 +    None defined
77192 +
77193 +Restrictions
77194 +    Only supported in infrastructure networks
77195 +
77196 +=====================================================================
77197 +
77198 +
77199 +Name
77200 +    SET_PMKID_LIST_CMD
77201 +
77202 +Synopsis
77203 +    Configures the list of PMKIDs on the firmware.
77204 +
77205 +Command
77206 +    wmiconfig --setpmkidlist --numpmkid=<n> --pmkid=<pmkid_1>
77207 +    ... --pmkid=<pmkid_n>
77208 +
77209 +    Where n is the number of pmkids (maximum = 8) and pmkid_i is the ith pmkid (16
77210 +    bytes in hex format)
77211 +
77212 +Command Parameters
77213 +    {
77214 +        A_UINT8 pmkid[WMI_PMKID_LEN];
77215 +    } __ATTRIB_PACK WMI_PMKID;
77216 +
77217 +    {
77218 +        A_UINT32 numPMKID;
77219 +        WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE];
77220 +    } __ATTRIB_PACK WMI_SET_PMKID_LIST_CMD;
77221 +
77222 +Command Values
77223 +    None
77224 +
77225 +Reset Values
77226 +    None
77227 +
77228 +Restrictions
77229 +    Supported only in infrastructure modes
77230 +
77231 +=====================================================================
77232 +
77233 +
77234 +Name
77235 +    SET_POWER_MODE
77236 +
77237 +Synopsis
77238 +    The host uses this command to provide the AR6000 device with guidelines on the
77239 +    desired trade-off between power utilization and performance.
77240 +
77241 +        In normal power mode, the device enters a sleep state if they have nothing to do,
77242 +        which conserves power but may cost performance as it can take up to 2 ms to
77243 +        resume operation after leaving sleep state.
77244 +
77245 +        In maximum performance mode, the device never enters sleep state, thus no time
77246 +        is spent waking up, resulting in higher power consumption and better
77247 +        performance.
77248 +
77249 +Command
77250 +    TBD
77251 +
77252 +Command Parameters
77253 +    UINT8    powerMode
77254 +        WMI_POWER_MODE value
77255 +    {
77256 +        REC_POWER   = 1
77257 +            (Recommended setting) Tries to conserve
77258 +            power without sacrificing performance
77259 +        MAX_PERF_POWER    = 2
77260 +            Setting that maximizes performance at
77261 +            the expense of power
77262 +
77263 +            All other values are reserved
77264 +    } WMI_POWER_MODE
77265 +
77266 +Command Values
77267 +    See command parameters
77268 +
77269 +Reset Values
77270 +    powerMode is REC_POWER
77271 +
77272 +Restrictions
77273 +    This command should only be issued in the DISCONNECTED state for the
77274 +    infrastructure network.
77275 +
77276 +            For a PM-disabled ad hoc network, the power mode should remain in
77277 +            MAX_PERF_POWER.
77278 +
77279 +            For a PM-enabled ad hoc network, the device can have REC_POWER or
77280 +            MAX_PERF_POWER set, but either way it must follow the power save ad hoc
77281 +            protocol. The host can change power modes in the CONNECTED state.
77282 +
77283 +    Host changes to the PS setting when the STA is off the home channel take no effect
77284 +    and cause a TARGET_PM_FAIL event.
77285 +
77286 +=====================================================================
77287 +
77288 +
77289 +Name
77290 +    SET_POWER_PARAMS
77291 +
77292 +Synopsis
77293 +    The host uses this command to configure power parameters
77294 +
77295 +Command
77296 +    wmiconfig eth1 --pmparams --it=<ms> --np=<number of PS POLL>
77297 +    --dp=<DTIM policy: ignore/normal/stick>
77298 +
77299 +Command Parameters
77300 +    UINT16    idle_period
77301 +        Length of time (in ms) the AR6000 device
77302 +        remains awake after frame Rx/Tx before going
77303 +        to SLEEP state
77304 +
77305 +    UINT16    pspoll_number
77306 +            The number of PowerSavePoll (PS-poll)
77307 +            messages the device should send before
77308 +            notifying the AP it is awake
77309 +
77310 +    UINT16    dtim_policy
77311 +            A WMI_POWER_PARAMS_CMD value
77312 +
77313 +    {
77314 +        IGNORE_DTIM    =1
77315 +            The device does not listen to any content after
77316 +            beacon (CAB) traffic
77317 +        NORMAL_DTIM    = 2
77318 +            DTIM period follows the listen interval (e.g., if
77319 +            the listen interval is 4 and the DTIM period is 2,
77320 +            the device wakes up every fourth beacon)
77321 +        STICK_DTIM    = 3
77322 +            Device attempt to receive all CAB traffic (e.g., if
77323 +            the DTIM period is 2 and the listen interval is 4,
77324 +            the device wakes up every second beacon)
77325 +    } WMI_POWER_PARAMS_CMD
77326 +
77327 +Command Parameters
77328 +    See command parameters
77329 +
77330 +Reset Values
77331 +    idle_period
77332 +        200 ms
77333 +
77334 +    pspoll_number
77335 +    = 1
77336 +
77337 +    dtim_policy
77338 +    = NORMAL_DTIM
77339 +
77340 +Restrictions
77341 +    None
77342 +
77343 +=====================================================================
77344 +
77345 +
77346 +Name
77347 +    SET_POWERSAVE_PARAMS
77348 +
77349 +Synopsis
77350 +    Set the two AR6000 power save timers (PS-POLL timer and APSD trigger timer) and
77351 +    the two ASPD TIM policies
77352 +
77353 +Command
77354 +    wmiconfig eth1--psparams --psPollTimer=<psPollTimeout in ms>
77355 +    --triggerTimer=<triggerTimeout in ms> --apsdTimPolicy=<ignore/
77356 +    adhere> --simulatedAPSDTimPolicy=<ignore/adhere>
77357 +
77358 +Command Parameters
77359 +    typedef struct {
77360 +        A_UINT16    psPollTimeout;
77361 +            Timeout (in ms) after sending PS-POLL; the
77362 +            AR6000 device sleeps if it does not receive a
77363 +            data packet from the AP
77364 +
77365 +        A_UINT16    triggerTimeout;
77366 +            Timeout (in ms) after sending a trigger; the
77367 +            device sleeps if it does not receive any data
77368 +            or null frame from the AP
77369 +
77370 +        APSD_TIM_POLICY    apsdTimPolicy;
77371 +            TIM behavior with queue APSD enabled
77372 +
77373 +        APSD_TIM_POLICY    simulatedAPSD
77374 +
77375 +        TimPolicy;
77376 +            TIM behavior with simulated APSD
77377 +            enabled
77378 +
77379 +    typedef enum {
77380 +        IGNORE_TIM_ALL_QUEUES_APSD = 0,
77381 +        PROCESS_TIM_ALL_QUEUES_APSD = 1,
77382 +        IGNORE_TIM_SIMULATED_APSD = 2,
77383 +        POWERSAVE_TIMERS_POLICY = 3,
77384 +    } APSD_TIM_POLICY;
77385 +
77386 +Command Values
77387 +    None
77388 +
77389 +Reset Values
77390 +    psPollTimeout is 50 ms; triggerTimeout is 10 ms;
77391 +    apsdTimPolicy = IGNORE_TIM_ALL_QUEUES_APSD;
77392 +    simulatedAPSDTimPolicy = POWERSAVE_TIMERS_POLICY
77393 +
77394 +Restrictions
77395 +    When this command is used, all parameters must be set; this command does not
77396 +    allow setting only one parameter.
77397 +
77398 +=====================================================================
77399 +
77400 +
77401 +Name
77402 +    SET_PROBED_SSID
77403 +
77404 +Synopsis
77405 +    The host uses this command to provide a list of up to MAX_PROBED_SSID_INDEX
77406 +    (six) SSIDs that the AR6000 device should actively look for. It lists the active SSID
77407 +    table. By default, the device actively looks for only the SSID specified in the
77408 +    \93CONNECT_CMD\94 command, and only when the regulatory domain allows active
77409 +    probing. With this command, specified SSIDs are probed for, even if they are hidden.
77410 +
77411 +Command
77412 +    wmiconfig eth1 --ssid=<ssid> [--num=<index>]
77413 +
77414 +Command Parameters
77415 +    {
77416 +        A_UINT8    numSsids
77417 +            A number from 0 to
77418 +            MAX_PROBED_SSID_INDEX indicating
77419 +            the active SSID table entry index for this
77420 +            command (if the specified entry index
77421 +            already has an SSID, the SSID specified in
77422 +            this command replaces it)
77423 +
77424 +        WMI_PROBED_SSID_INFO    probedSSID[1]
77425 +    } WMI_PROBED_SSID_CMD
77426 +
77427 +    {
77428 +        A_UINT8    flag
77429 +            WMI_SSID_FLAG indicates the current
77430 +            entry in the active SSID table
77431 +        A_UINT8    ssidLength
77432 +            Length of the specified SSID in bytes.
77433 +            If = 0, the entry corresponding to the
77434 +            index is erased
77435 +        A_UINT8    ssid[32]
77436 +            SSID string actively probed for when
77437 +            permitted by the regulatory domain
77438 +    } WMI_PROBED_SSID_INFO
77439 +
77440 +Command Values
77441 +    WMI_SSID_FLAG
77442 +    {
77443 +         DISABLE_SSID_FLAG    = 0
77444 +            Disables entry
77445 +        SPECIFIC_SSID_FLAG    = 1
77446 +            Probes specified SSID
77447 +        ANY_SSID_FLAG    = 2
77448 +            Probes for any SSID
77449 +    } WMI_SSID_FLAG
77450 +
77451 +Reset Value
77452 +    The entries are unused.
77453 +
77454 +Restrictions
77455 +    None
77456 +
77457 +=====================================================================
77458 +
77459 +
77460 +Name
77461 +    SET_REASSOC_MODE
77462 +
77463 +Synopsis
77464 +    Specify whether the disassociated frame should be sent or not upon reassociation.
77465 +
77466 +Command
77467 +    wmiconfig eth1 --setreassocmode <mode>
77468 +
77469 +Command Parameters
77470 +    UINT8    mode
77471 +
77472 +Command Values
77473 +    mode
77474 +        = 0x00
77475 +        Send disassoc to a previously connected AP
77476 +        upon reassociation
77477 +        = 0x01
77478 +        Do not send disassoc to previously connected
77479 +        AP upon reassociation
77480 +
77481 +Reset Values
77482 +    None defined
77483 +
77484 +Restrictions
77485 +    None
77486 +
77487 +
77488 +=====================================================================
77489 +
77490 +Name
77491 +    SET_RETRY_LIMITS
77492 +
77493 +Synopsis
77494 +    Allows the host to influence the number of times that the AR6000 device should
77495 +    attempt to send a frame before they give up.
77496 +
77497 +Command
77498 +    wmiconfig --setretrylimits <frameType> <trafficClass> <maxRetries>
77499 +    <enableNotify>
77500 +
77501 +Command Parameters
77502 +    {
77503 +        UINT8    frameType
77504 +            A WMI_FRAMETYPE specifying
77505 +            which type of frame is of interest.
77506 +        UINT8    trafficClass
77507 +            Specifies a traffic class (see
77508 +            \93CREATE_PSTREAM\94). This
77509 +            parameter is only significant when
77510 +            frameType = DATA_FRAMETYPE.
77511 +        UINT8    maxRetries
77512 +            Maximum number of times the
77513 +            device attempts to retry a frame Tx,
77514 +            ranging from WMI_MIN_RETRIES
77515 +            (2) to WMI_MAX_RETRIES (15). If
77516 +            the special value 0 is used,
77517 +            maxRetries is set to 15.
77518 +        A_UINT8    enableNotify
77519 +            Notify when enabled
77520 +    } WMI_RETRY_LIMIT_INFO
77521 +
77522 +    {
77523 +        A_UINT8    numEntries
77524 +        WMI_RETRY_LIMIT_INFO  retryLimitInfo[1]
77525 +    } WMI_SET_RETRY_LIMITS_CMD
77526 +
77527 +Command Values
77528 +    {
77529 +        MGMT_FRAMETYPE    = 0    Management frame
77530 +        CONTROL_FRAMETYPE = 1    Control frame
77531 +        DATA_FRAMETYPE    = 2    Data frame
77532 +    } WMI_FRAMETYPE
77533 +
77534 +Reset Values
77535 +    Retries are set to 15
77536 +
77537 +Restrictions
77538 +    None
77539 +
77540 +=====================================================================
77541 +
77542 +
77543 +Name
77544 +    SET_ROAM_CTRL
77545 +
77546 +Synopsis
77547 +    Affects how the AR6000 device selects a BSS. The host uses this command to set and
77548 +    enable low RSSI scan parameters. The time period of low RSSI background scan is
77549 +    mentioned in scan period. Low RSSI scan is triggered when the current RSSI
77550 +    threshold (75% of current RSSI) is equal to or less than scan threshold.
77551 +
77552 +    Low RSSI roam is triggered when the current RSSI threshold falls below the roam
77553 +    threshold and roams to a better AP by the end of the scan cycle. During Low RSSI
77554 +    roam, if the STA finds a new AP with an RSSI greater than roam RSSI to floor, during
77555 +    scan, it roams immediately to it instead of waiting for the end of the scan cycle. See
77556 +    also \93Scan and Roam\94 on page C-1.
77557 +
77558 +Command
77559 +    wmiconfig --roam <roamctrl> <info>, where info is <scan period>
77560 +    <scan threshold> <roam threshold> <roam rssi floor>
77561 +
77562 +Command Parameters
77563 +    A_UINT8    roamCtrlType;
77564 +
77565 +Command Values
77566 +    WMI_FORCE_ROAM     = 1
77567 +    Roam to the specified BSSID
77568 +
77569 +    WMI_SET_ROAM_MODE  = 2
77570 +    Default, progd bias, no roam
77571 +
77572 +    WMI_SET_HOST_BIAS  = 3
77573 +    Set the host bias
77574 +
77575 +    WMI_SET_LOWRSSI_SCAN_PARAMS  = 4
77576 +    Info parameters
77577 +
77578 +    A_UINT8    bssid[ATH_MAC_LEN];
77579 +    WMI_FORCE_ROAM
77580 +
77581 +    A_UINT8    roamMode;
77582 +    WMI_SET_ROAM_MODE
77583 +
77584 +    A_UINT8    bssBiasInfo;
77585 +    WMI_SET_HOST_BIAS
77586 +
77587 +    A_UINT16    lowrssi_scan_period;
77588 +    WMI_SET_LOWRSSI_SCAN_PARAMS
77589 +
77590 +    A_INT16
77591 +    lowrssi_scan_threshold;
77592 +    WMI_SET_LOWRSSI_SCAN_PARAMS
77593 +
77594 +    A_INT16    lowrssi_roam_threshold;
77595 +    WMI_SET_LOWRSSI_SCAN_PARAMS
77596 +
77597 +    A_UINT8    roam_rssi_floor;
77598 +    WMI_SET_LOWRSSI_SCAN_PARAMS
77599 +
77600 +Reset Value
77601 +    None defined (default lowrssi scan is disabled. Enabled only when scan period is set.)
77602 +
77603 +Restrictions
77604 +    None
77605 +
77606 +=====================================================================
77607 +
77608 +
77609 +Name
77610 +    SET_RTS
77611 +
77612 +Synopsis
77613 +    Decides when RTS should be sent.
77614 +
77615 +Command
77616 +    wmiconfig eth1 --setRTS <pkt length threshold>
77617 +
77618 +Command Parameters
77619 +    A_UINT16
77620 +    threshold;
77621 +    Command parameter threshold in bytes. An RTS is
77622 +    sent if the data length is more than this threshold.
77623 +    The default is to NOT send RTS.
77624 +
77625 +Command Values
77626 +    None
77627 +
77628 +Reset Value
77629 +    Not to send RTS.
77630 +
77631 +Restrictions
77632 +    None
77633 +
77634 +
77635 +=====================================================================
77636 +
77637 +Name
77638 +    SET_SCAN_PARAMS
77639 +
77640 +Synopsis
77641 +    The host uses this command to set the AR6000 scan parameters, including the duty
77642 +    cycle for both foreground and background scanning. Foreground scanning takes
77643 +    place when the AR6000 device is not connected, and discovers all available wireless
77644 +    networks to find the best BSS to join. Background scanning takes place when the
77645 +    device is already connected to a network and scans for potential roaming candidates
77646 +    and maintains them in order of best to worst. A second priority of background
77647 +    scanning is to find new wireless networks.
77648 +
77649 +    The device initiates a scan when necessary. For example, a foreground scan is always
77650 +    started on receipt of a \93CONNECT_CMD\94 command or when the device cannot find
77651 +    a BSS to connect to. Foreground scanning is disabled by default until receipt of a
77652 +    CONNECT command. Background scanning is enabled by default and occurs every
77653 +    60 seconds after the device is connected.
77654 +
77655 +    The device implements a binary backoff interval for foreground scanning when it
77656 +    enters the DISCONNECTED state after losing connectivity with an AP or when a
77657 +    CONNECT command is received. The first interval is ForegroundScanStartPeriod,
77658 +    which doubles after each scan until the interval reaches ForegroundScanEndPeriod.
77659 +    If the host terminates a connection with DISCONNECT, the foreground scan period
77660 +    is ForegroundScanEndPeriod. All scan intervals are measured from the time a full
77661 +    scan ends to the time the next full scan starts. The host starts a scan by issuing a
77662 +    \93START_SCAN\94 command. See also \93Scan and Roam\94 on page C-1.
77663 +
77664 +Command
77665 +    wmiconfig eth1 --scan --fgstart=<sec> --fgend=<sec> --bg=<sec> --
77666 +    act=<msec> --pas=<msec> --sr=<short scan ratio> --scanctrlflags
77667 +    <connScan> <scanConnected> <activeScan> <reportBSSINFO>
77668 +
77669 +Command Parameters
77670 +    UINT16    fgStartPeriod
77671 +        First interval used by the device when it
77672 +        disconnects from an AP or receives a
77673 +        CONNECT command, specified in seconds (0\96
77674 +        65535). If = 0, the device uses the reset value.
77675 +        If = 65535, the device disables foreground
77676 +        scanning.
77677 +
77678 +    UINT16    fgEndPeriod
77679 +        The maximum interval the device waits between
77680 +        foreground scans specified in seconds (from
77681 +        ForegroundScanStartPeriod to 65535). If = 0, the
77682 +        device uses the reset value.
77683 +
77684 +    UINT16    bgScanPeriod
77685 +        The period of background scan specified in
77686 +        seconds (0\9665535). By default, it is set to the reset
77687 +        value of 60 seconds. If 0 or 65535 is specified, the
77688 +        device disables background scanning.
77689 +
77690 +    UINT16    maxactChDwellTime
77691 +        The period of time the device stays on a
77692 +        particular channel while active scanning. It is
77693 +        specified in ms (10\9665535). If the special value of
77694 +        0 is specified, the device uses the reset value.
77695 +
77696 +    UINT16    PasChDwellTime
77697 +        The period of time the device remains on a
77698 +        particular channel while passive scanning. It is
77699 +        specified in ms (10\9665535). If the special value of
77700 +        0 is specified, the device uses the reset value.
77701 +
77702 +    UINT8    shortScanRatio
77703 +        Number of short scans to perform for each
77704 +        long scan.
77705 +
77706 +    UINT8    scanCtrlFlasgs
77707 +
77708 +    UINT16    minactChDwellTime
77709 +        Specified in ms
77710 +
77711 +    UINT32    maxDFSchActTime
77712 +        The maximum time a DFS channel can stay
77713 +        active before being marked passive, specified in
77714 +        ms.
77715 +
77716 +Command Values
77717 +    None
77718 +
77719 +Reset Values
77720 +    ForegroundScanStart
77721 +Period
77722 +        1 sec
77723 +
77724 +    ForegroundScanEndPeriod
77725 +        60 sec
77726 +
77727 +    BackgroundScanPeriod
77728 +        60 sec
77729 +
77730 +    ActiveChannelDwellTime
77731 +        105 ms
77732 +
77733 +=====================================================================
77734 +
77735 +
77736 +Name
77737 +    SET_TKIP_COUNTERMEASURES
77738 +
77739 +Synopsis
77740 +    The host issues this command to tell the target whether to enable or disable TKIP
77741 +    countermeasures.
77742 +
77743 +Command
77744 +    TBD
77745 +
77746 +Command Parameters
77747 +    UINT8    WMI_TKIP_CM_ENABLE
77748 +        Enables the countermeasures
77749 +
77750 +
77751 +    UINT8    TKIP_CM_DISABLE
77752 +        Disables the countermeasures
77753 +
77754 +Command Values
77755 +    None
77756 +
77757 +Reset Values
77758 +    By default, TKIP MIC reporting is disabled
77759 +
77760 +Restrictions
77761 +    None
77762 +
77763 +=====================================================================
77764 +
77765 +
77766 +Name
77767 +    SET_TX_PWR
77768 +
77769 +Synopsis
77770 +    The host uses this command to specify the Tx power level of the AR6000. Cannot be
77771 +    used to exceed the power limit permitted by the regulatory domain. The maximum
77772 +    output power is limited in the chip to 31.5 dBm; the range is 0 \96 31.5 dbm.
77773 +
77774 +Command
77775 +    wmiconfig --power <dbM>
77776 +
77777 +Command Parameters
77778 +    UINT8    dbM
77779 +        The desired Tx power specified in dbM.
77780 +        If = 0, the device chooses the maximum
77781 +        permitted by the regulatory domain.
77782 +
77783 +Command Values
77784 +    None
77785 +
77786 +Reset Values
77787 +    The maximum permitted by the regulatory domain
77788 +
77789 +Restrictions
77790 +    None
77791 +
77792 +See Also
77793 +    \93GET_TX_PWR\94
77794 +
77795 +
77796 +=====================================================================
77797 +
77798 +Name
77799 +    SET_VOICE_PKT_SIZE
77800 +
77801 +Synopsis
77802 +    If an AP does not support WMM, it has no way to differentiate voice from data.
77803 +    Because the voice packet is typically small, packet in size less than voicePktSize are
77804 +    assumed to be voice, otherwise it is treated as data.
77805 +
77806 +Command
77807 +    wmiconfig eth1 --setVoicePktSize <size-in-bytes>
77808 +
77809 +Command Parameters
77810 +    UINT16    voicePktSize
77811 +        Packet size in octets
77812 +
77813 +Command Values
77814 +    None
77815 +
77816 +Reset Values
77817 +    voicePktSize default is 400 bytes
77818 +
77819 +Restrictions
77820 +    No effect if WMM is unavailable
77821 +
77822 +
77823 +=====================================================================
77824 +
77825 +Name
77826 +    SET_WMM
77827 +
77828 +Synopsis
77829 +    Overrides the AR6000 device WMM capability
77830 +
77831 +Command
77832 +    wmiconfig eth1 --setwmm <enable>
77833 +
77834 +Command Parameters
77835 +    WMI_WMM_ENABLED
77836 +        Enables WMM
77837 +
77838 +    WMI_WMM_DISABLED
77839 +        Disables WMM support
77840 +
77841 +Command Values
77842 +    0 = disabled
77843 +    1 = enabled
77844 +
77845 +Reset Value
77846 +    WMM Disabled
77847 +
77848 +Restrictions
77849 +    None
77850 +
77851 +
77852 +=====================================================================
77853 +
77854 +Name
77855 +    SET_WMM_TXOP
77856 +
77857 +Synopsis
77858 +    Configures TxOP Bursting when sending traffic to a WMM capable AP
77859 +
77860 +Command
77861 +    wmiconfig eth1 --txopbursting <burstEnable>
77862 +
77863 +    <burstEnable>
77864 +        = 0
77865 +    Disallow TxOp bursting
77866 +
77867 +        = 1
77868 +    Allow TxOp bursting
77869 +
77870 +Command Parameters
77871 +    txopEnable
77872 +        = WMI_TXOP_DISABLED
77873 +        Disabled
77874 +
77875 +        = WMI_TXOP_ENABLED
77876 +        Enabled
77877 +
77878 +Command Values
77879 +    txopEnable
77880 +        = 0    Disabled
77881 +
77882 +        = 1    Enabled
77883 +
77884 +Reset Value
77885 +    Bursting is off by default
77886 +
77887 +Restrictions
77888 +    None
77889 +
77890 +=====================================================================
77891 +
77892 +
77893 +Name
77894 +    SET_WOW_MODE
77895 +
77896 +Synopsis
77897 +    The host uses this command to enable or disable the WoW mode. When WoW mode
77898 +    is enabled and the host is asleep, pattern matching takes place at the target level.
77899 +    Only packets that match any of the pre-specified WoW filter patterns, will be passed
77900 +    up to the host. The host will also be woken up by the target. Packets which do not
77901 +    match any of the WoW patterns are discarded.
77902 +
77903 +Command
77904 +    wmiconfig \96setwowmode <enable/disable>
77905 +
77906 +Command Parameters
77907 +    A_BOOL    enable_wow
77908 +        Enable or disable WoW:
77909 +
77910 +Command Values
77911 +        = 0
77912 +    Disable WoW
77913 +
77914 +        = 1
77915 +    Enable WoW
77916 +
77917 +Reset Value
77918 +    None defined (default WoW mode is disabled).
77919 +
77920 +Restrictions
77921 +    None
77922 +
77923 +See Also
77924 +    \93GET_WOW_LIST\94
77925 +
77926 +
77927 +=====================================================================
77928 +
77929 +Name
77930 +    SET_WSC_STATUS
77931 +
77932 +Synopsis
77933 +    The supplicant uses this command to inform the target about the status of the WSC
77934 +    registration protocol. During the WSC registration protocol, a flag is set so the target
77935 +    bypasses some of the checks in the CSERV module. At the end of the registration, this
77936 +    flag is reset.
77937 +
77938 +Command
77939 +    N/A
77940 +
77941 +Command Parameters
77942 +    A_BOOL status
77943 +        = 1    WSC registration in progress
77944 +        = 0    WSC protocol not running
77945 +
77946 +Reply Parameters
77947 +    None
77948 +
77949 +Reset Value
77950 +    None defined (default = 0)
77951 +
77952 +Restrictions
77953 +    None
77954 +
77955 +
77956 +=====================================================================
77957 +
77958 +Name
77959 +    SNR_THRESHOLD_PARAMS
77960 +
77961 +Synopsis
77962 +    Configures how the AR6000 device monitors and reports SNR of the connected BSS,
77963 +    used as a link quality metric.
77964 +
77965 +Command
77966 +    --snrThreshold <weight> <upper_threshold_1> ...
77967 +    <upper_threshold_4> <lower_threshold_1> ... <lower_threshold_4>
77968 +    <pollTimer>
77969 +
77970 +Command Parameters
77971 +    <weight>
77972 +        Share with rssiThreshold. Range in [1, 16], used
77973 +        in the formula to calculate average RSSI
77974 +
77975 +    <upper_threshold_x>
77976 +        Above thresholds expressed in db, in ascending
77977 +        order
77978 +
77979 +    <lower_threshold_x>
77980 +        Below thresholds expressed in db, in ascending
77981 +        order
77982 +
77983 +    <pollTimer>
77984 +        The signal strength sampling frequency in
77985 +        seconds. If polltime = 0, signal strength
77986 +        sampling is disabled
77987 +
77988 +Command Values
77989 +    None
77990 +
77991 +Reset Value
77992 +    None defined
77993 +
77994 +Restrictions
77995 +    None
77996 +
77997 +=====================================================================
77998 +
77999 +
78000 +Name
78001 +    START_SCAN
78002 +
78003 +Synopsis
78004 +    The host uses this command to start a long or short channel scan. All future scans are
78005 +    relative to the time the AR6000 device processes this command. The device performs
78006 +    a channel scan on receipt of this command, even if a scan was already in progress.
78007 +    The host uses this command when it wishes to refresh its cached database of wireless
78008 +    networks. The isLegacy field will be removed (0 for now) because it is achieved by
78009 +    setting CONNECT_PROFILE_MATCH_DONE in the CONNECT command. See also
78010 +    \93Scan and Roam\94
78011 +
78012 +Command
78013 +    wmiconfig eth1 --startscan <scan type> <forcefgscan> 0
78014 +    <homeDwellTime> <forceScanInterval>
78015 +
78016 +Command Parameters
78017 +    UINT8    scanType
78018 +        WMI_SCAN_TYPE
78019 +
78020 +Command Values
78021 +    {
78022 +        WMI_LONG_SCAN    =0x0
78023 +            Requests a full scan
78024 +        WMI_SHORT_SCAN   =0x1
78025 +            Requests a short scan
78026 +    } WMI_SCAN_TYPE
78027 +
78028 +    A_BOOL    forceFgScan
78029 +        forceFgScan
78030 +        = 0
78031 +        Disable the foreground scan
78032 +
78033 +        forceFgScan
78034 +        = 1
78035 +        Forces a foreground scan
78036 +
78037 +    A_UINT32    homeDwellTime
78038 +        Maximum duration in the home
78039 +        channel (in ms)
78040 +
78041 +    A_UINT32     forceScanInterval
78042 +        Time interval between scans (in ms)
78043 +
78044 +    A_UINT32     scanType
78045 +        WMI_SCAN_TYPE
78046 +
78047 +Reset Value
78048 +    Disable forcing foreground scan
78049 +
78050 +Restrictions
78051 +    isLegacy field will no longer be supported (pass as 0 for now)
78052 +
78053 +
78054 +=====================================================================
78055 +
78056 +Name
78057 +    SYNCHRONIZE
78058 +
78059 +Synopsis
78060 +    The host uses this command to force a synchronization point between the command
78061 +    and data paths
78062 +
78063 +Command
78064 +    TBD
78065 +
78066 +Command Parameters
78067 +    None
78068 +
78069 +
78070 +
78071 +Command Values
78072 +    None
78073 +
78074 +
78075 +
78076 +Reset Values
78077 +    None
78078 +
78079 +
78080 +
78081 +Restrictions
78082 +    None
78083 +
78084 +
78085 +=====================================================================
78086 +
78087 +Name
78088 +    TARGET_ERROR_REPORT_BITMASK
78089 +
78090 +Synopsis
78091 +    Allows the host to control \93ERROR_REPORT\94 events from the AR6000 device.
78092 +
78093 +        If error reporting is disabled for an error type, a count of errors of that type is
78094 +        maintained by the device.
78095 +
78096 +        If error reporting is enabled for an error type, an \93ERROR_REPORT\94 event is
78097 +        sent when an error occurs and the error report bit is cleared.
78098 +
78099 +    Error counts for each error type are available through the \93GET_TARGET_STATS\94
78100 +    command.
78101 +
78102 +Command
78103 +    wmiconfig eth1 --setErrorReportingBitmask
78104 +
78105 +Command Parameters
78106 +    UINT32    bitmask
78107 +        Represents the set of
78108 +        WMI_TARGET_ERROR_VAL error types
78109 +        enabled for reporting
78110 +
78111 +Command Values
78112 +    {
78113 +        WMI_TARGET_PM_ERR_FAIL    = 0x00000001
78114 +            Power save fails (only two cases):
78115 +               Retry out of null function/QoS null
78116 +               function to associated AP for PS
78117 +               indication'
78118 +               Host changes the PS setting when
78119 +               STA is off home channel
78120 +
78121 +        WMI_TARGET_KEY_NOT_FOUND    = 0x00000002
78122 +            No cipher key
78123 +        WMI_TARGET_DECRYPTION_ERR   = 0x00000004
78124 +            Decryption error
78125 +        WMI_TARGET_BMISS            = 0x00000008
78126 +            Beacon miss
78127 +        WMI_PSDISABLE_NODE_JOIN     = 0x00000010
78128 +            A non-PS-enabled STA joined the
78129 +            PS-enabled network
78130 +        WMI_TARGET_COM_ERR          = 0x00000020
78131 +            Host/target communication error
78132 +        WMI_TARGET_FATAL_ERR        = 0x00000040
78133 +            Fatal error
78134 +    } WMI_TARGET_ERROR_VAL
78135 +
78136 +Reset Values
78137 +    Bitmask is 0, and all error reporting is disabled
78138 +
78139 +Restrictions
78140 +    None
78141 +
78142 +
78143 +=====================================================================
78144 +WMI Events
78145 +
78146 +Event
78147 +    Description
78148 +    Page
78149 +
78150 +
78151 +BSSINFO
78152 +    Contains information describing BSSs collected during a scan
78153 +
78154 +CAC_EVENTID
78155 +    Indicates signalling events in admission control
78156 +
78157 +CMDERROR
78158 +    The AR6000 device encounters an error while attempting to process
78159 +    a command
78160 +
78161 +CONNECT
78162 +    The device has connected to a wireless network
78163 +
78164 +DISCONNECT
78165 +    The device lost connectivity with a wireless network
78166 +
78167 +ERROR_REPORT
78168 +    An error has occurred for which the host previously requested
78169 +    notification with the command
78170 +    \93TARGET_ERROR_REPORT_BITMASK\94
78171 +
78172 +EXTENSION
78173 +    WMI extension event
78174 +
78175 +GET_PMKID_LIST_EVENT
78176 +    Created in response to a \93GET_PMKID_LIST_CMD\94 command
78177 +
78178 +GET_WOW_LIST_EVENT
78179 +    Response to the wmiconfig \93GET_WOW_LIST\94 command to
78180 +    retrieve the configured WoW patterns
78181 +
78182 +NEIGHBOR_REPORT
78183 +    Neighbor APs that match the current profile were detected
78184 +
78185 +OPT_RX_FRAME_EVENT
78186 +    (Special feature) informs the host of the reception of a special frame
78187 +
78188 +PSTREAM_TIMEOUT
78189 +    A prioritized stream has been idle for a specified interval
78190 +
78191 +READY
78192 +    The AR6000 device is ready to accept commands
78193 +
78194 +REGDOMAIN
78195 +    The regulatory domain has changed
78196 +
78197 +REPORT_ROAM_DATA_EVENT
78198 +    Reports the roam time calculations made by the device
78199 +    (generated with a special build)
78200 +    \97
78201 +
78202 +REPORT_STATISTICS
78203 +    Reply to a \93GET_TARGET_STATS\94 command
78204 +
78205 +ROAM_TBL_EVENT
78206 +    Reports the roam table
78207 +
78208 +RSSI_THRESHOLD
78209 +    Signal strength from the connected AP has crossed the threshold
78210 +    defined in the \93RSSI_THRESHOLD_PARAMS\94 command
78211 +
78212 +SCAN_COMPLETE_EVENT
78213 +    A scan has completed (added status SCAN_ABORTED in release 2.0)
78214 +
78215 +TEST_EVENT
78216 +    Event generated by the TCMD
78217 +
78218 +TKIP_MICERROR
78219 +    TKIP MIC errors were detected
78220 +
78221 +=====================================================================
78222 +
78223 +Name
78224 +    BSSINFO
78225 +
78226 +Synopsis
78227 +    Contains information describing one or more BSSs as collected during a scan.
78228 +    Information includes the BSSID, SSID, RSSI, network type, channel, supported rates,
78229 +    and IEs. BSSINFO events are sent only after the device receives a beacon or probe-
78230 +    response frame that pass the filter specified in the \93SET_BSS_FILTER\94 command.
78231 +    BSSINFO events consist of a small header followed by a copy of the beacon or probe
78232 +    response frame. The 802.11 header is not present. For formats of beacon and probe-
78233 +    response frames please consult the IEEE 802.11 specification.
78234 +
78235 +    The beacons or probe responses containing the IE specified by the
78236 +    WMI_BSS_FILTER_CMD are passed to the host through the
78237 +    WMI_BSSINFO_EVENT. The event carries a 32-bit bitmask that indicates the IEs that
78238 +    were detected in the management frame. The frame type field has been extended to
78239 +    indicate action management frames. This would be helpful to route these frames
78240 +    through the same event mechanism as used by the beacon processing function.
78241 +
78242 +    If the bssFilter in the SET_BSS_FILTER matches, then the ieMask is not relevant
78243 +    because the BSSINFO event is sent to the host. If the bssFilter doesnot match in the
78244 +    beacons/probe respones, then the ieMask match dictates whether the BSSINFO
78245 +    event is sent to the host. In the case of action management frames, the ieMask is the
78246 +    filter that is applied.
78247 +
78248 +Event ID
78249 +    0x1004
78250 +
78251 +Event Parameters
78252 +    typedef struct {
78253 +        A_UINT16    channel;
78254 +            Specifies the frequency (in MHz) where the
78255 +            frame was received
78256 +        A_UINT8    frameType;
78257 +            A WMI_BI_FTYPE value
78258 +        A_UINT8    snr;
78259 +        A_INT16    rssi;
78260 +            Indicates signal strength
78261 +        A_UINT8    bssid[ATH_MAC_LEN];
78262 +        A_UINT32    ieMask;
78263 +    } _ATTRIB_PACK_WMI_BSS_INFO_HDR;
78264 +
78265 +    Beacon or Probe Response Frame
78266 +
78267 +Event Values
78268 +    {
78269 +        BEACON_FTYPE    = 0x1
78270 +            Indicates a beacon frame
78271 +        PROBERESP_FTYPE
78272 +            Indicates a probe response frame
78273 +        ACTION_MGMT_FTYPE
78274 +     } WMI_BI_FTYPE
78275 +
78276 +=====================================================================
78277 +
78278 +Name
78279 +    CAC_EVENTID
78280 +
78281 +Synopsis
78282 +    Indicates signalling events in admission control. Events are generated when
78283 +    admission is accepted, rejected, or deleted by either the host or the AP. If the AP does
78284 +    not respond to an admission request within a timeout of 500 ms, an event is
78285 +    generated to the host.
78286 +
78287 +Event ID
78288 +    0x1011
78289 +
78290 +Event Parameters
78291 +    UINT8
78292 +    ac
78293 +    Access class pertaining to the
78294 +signalling
78295 +
78296 +    UINT8    cac_indication
78297 +        Type of indication; indications are
78298 +        listed in WMI_CAC_INDICATION
78299 +
78300 +    UINT8    statusCode
78301 +        AP response status code for a
78302 +        request
78303 +
78304 +    UINT8    tspecSuggestion[63]
78305 +        Suggested TSPEC from AP
78306 +
78307 +Event Values
78308 +    {
78309 +        CAC_INDICATION_ADMISSION = 0x00
78310 +        CAC_INDICATION_ADMISSION_RESP    = 0x01
78311 +        CAC_INDICATION_DELETE    = 0x02
78312 +        CAC_INDICATION_NO_RESP   = 0x03
78313 +    } WMI_CAC_INDICATION
78314 +
78315 +
78316 +=====================================================================
78317 +
78318 +
78319 +Name
78320 +    CMDERROR
78321 +
78322 +Synopsis
78323 +    Indicates that the AR6000 device encountered an error while attempting to process a
78324 +    command. This error is fatal and indicates that the device requires a reset.
78325 +
78326 +Event ID
78327 +    0x1005
78328 +
78329 +Event Parameters
78330 +    UINT16    commandId
78331 +        Corresponds to the command which generated
78332 +        the error
78333 +    UINT8    errorCode
78334 +        A WMI_ERROR_CODE value
78335 +
78336 +Event Values
78337 +    {
78338 +        INVALID_PARAM    = 1
78339 +            Invalid parameter
78340 +        ILLEGAL_STATE    = 2
78341 +            Illegal state
78342 +        INTERNAL_ERROR   = 3
78343 +            Internal Error
78344 +        All other values reserved
78345 +    } WMI_ERROR_CODE
78346 +
78347 +
78348 +=====================================================================
78349 +
78350 +
78351 +Name
78352 +    CONNECT
78353 +
78354 +Synopsis
78355 +    Signals that the AR6000 connected to a wireless network. Connection occurs due to a
78356 +    \93CONNECT\94 command or roaming to a new AP. For infrastructure networks, shows
78357 +    that the AR6000 successfully performed 802.11 authentication and AP association.
78358 +
78359 +Event ID
78360 +    0x1002
78361 +
78362 +Event Parameters
78363 +    UINT16    channel
78364 +        Channel frequency (in MHz) of the network the
78365 +        AR6000 are connected to
78366 +
78367 +    UINT8    bssid[6]
78368 +        MAC address of the AP the AR6000 are
78369 +        connected to or the BSSID of the ad hoc
78370 +        network
78371 +
78372 +    UINT16    listenInterval
78373 +        Listen interval (in Kms) that the AR6000 are
78374 +        using
78375 +
78376 +    UINT 8    beaconIeLen
78377 +        Length (in bytes) of the beacon IEs
78378 +
78379 +    UINT8    assocInfo
78380 +        Pointer to an array containing beacon IEs,
78381 +        followed first by association request IEs then by
78382 +        association response IEs
78383 +
78384 +    UINT8    assocReqLen
78385 +        Length (in bytes) of the assocReqIEs array
78386 +
78387 +    UINT8    assocRespLen
78388 +        Length (in bytes) of the assocRespIEs array
78389 +
78390 +Event Values
78391 +    None defined
78392 +
78393 +=====================================================================
78394 +
78395 +
78396 +Name
78397 +    DISCONNECT
78398 +
78399 +Synopsis
78400 +    Signals that the AR6000 device lost connectivity with the wireless network.
78401 +    DISCONENCT is generated when the device fails to complete a \93CONNECT\94
78402 +    command or as a result of a transition from a connected state to disconnected state.
78403 +
78404 +    After sending the \93DISCONNECT\94 event the device continually tries to re-establish
78405 +    a connection. A LOST_LINK occurs when STA cannot receive beacons within the
78406 +    specified time for the SET_BMISS_TIME command.
78407 +
78408 +Event ID
78409 +    0x1003
78410 +
78411 +Event Parameters
78412 +    UINT8    disconnect
78413 +        Reason
78414 +        A WMI_DISCONNECT_REASON value
78415 +
78416 +    UINT8    bssid[6]
78417 +        Indicates which BSS the device was connected to
78418 +
78419 +    UINT8    assocRespLen
78420 +        Length of the 802.11 association response frame
78421 +        that triggered this event, or 0 if not applicable
78422 +
78423 +    UINT8    assocInfo[assocRespLen]
78424 +        Copy of the 802.11 association response frame
78425 +
78426 +Event Values
78427 +    {
78428 +        NO_NETWORK_AVAIL    =0x01
78429 +            Indicates that the device was unable to
78430 +            establish or find the desired network
78431 +        LOST_LINK    =0x02
78432 +            Indicates the devices is no longer receiving
78433 +            beacons from the BSS it was previously
78434 +            connected to
78435 +
78436 +        DISCONNECT_CMD  =0x03
78437 +            Indicates a \93DISCONNECT\94 command was
78438 +            processed
78439 +        BSS_DISCONNECTED =0x04
78440 +            Indicates the BSS explicitly disconnected the
78441 +            device. Possible mechanisms include the AP
78442 +            sending 802.11 management frames
78443 +            (e.g., disassociate or deauthentication
78444 +            messages).
78445 +        AUTH_FAILED    =0x05
78446 +            Indicates that the device failed 802.11
78447 +            authentication with the BSS
78448 +        ASSOC_FAILED    =0x06
78449 +            Indicates that the device failed 802.11
78450 +            association with the BSS
78451 +        NO_RESOURCES_AVAIL    =0x07
78452 +            Indicates that a connection failed because the
78453 +            AP had insufficient resources to complete the
78454 +            connection
78455 +        CSERV_DISCONNECT    =0x08
78456 +            Indicates that the device\92s connection services
78457 +            module decided to disconnect from a BSS,
78458 +            which can happen for a variety of reasons (e.g.,
78459 +            the host marks the current connected AP as a
78460 +            bad AP).
78461 +        INVALID_PROFILE    =0x0A
78462 +            Indicates that an attempt was made to
78463 +            reconnect to a BSS that no longer matches the
78464 +            current profile
78465 +        All other values are reserved
78466 +    } WMI_DISCONNECT_REASON
78467 +
78468 +
78469 +=====================================================================
78470 +
78471 +
78472 +Name
78473 +    ERROR_REPORT
78474 +
78475 +Synopsis
78476 +    Signals that a type of error has occurred for which the host previously requested
78477 +    notification through the \93TARGET_ERROR_REPORT_BITMASK\94 command.
78478 +
78479 +Event ID
78480 +    0x100D
78481 +
78482 +Event Parameters
78483 +    UINT32    errorVal
78484 +            WMI_TARGET_ERROR_VAL value. See
78485 +            \93TARGET_ERROR_REPORT_BITMASK\94.
78486 +
78487 +Event Values
78488 +    errorVal
78489 +    = 0x00000001
78490 +    Power save fails
78491 +
78492 +        = 0x00000002
78493 +    No cipher key
78494 +
78495 +        = 0x00000004
78496 +    Decryption error
78497 +
78498 +        = 0x00000008
78499 +    Beacon miss
78500 +
78501 +        = 0x00000010
78502 +    A non-power save disabled node has joined
78503 +    the PS-enabled network
78504 +
78505 +
78506 +=====================================================================
78507 +
78508 +
78509 +Name
78510 +    EXTENSION
78511 +
78512 +Synopsis
78513 +    The WMI is used mostly for wireless control messages to a wireless module that
78514 +    apply to wireless module management regardless of the target platform
78515 +    implementation. However, some events peripherally related to wireless management
78516 +    are desired during operation. These wireless extension events may be platform-
78517 +    specific or implementation-dependent. See \93WMI Extension Commands\94
78518 +
78519 +
78520 +Event ID
78521 +    0x1010
78522 +
78523 +
78524 +=====================================================================
78525 +
78526 +
78527 +Name
78528 +    GET_PMKID_LIST_EVENT
78529 +
78530 +Synopsis
78531 +    Generated by firmware in response to a \93GET_PMKID_LIST_CMD\94 command.
78532 +
78533 +Event Parameters
78534 +    typedef struct {
78535 +        A_UINT32    numPMKID;
78536 +            Contains the number of PMKIDs in the reply
78537 +        WMI_PMKID   pmkidList[1];
78538 +    } __ATTRIB_PACK WMI_PMKID_LIST_REPLY;
78539 +
78540 +Event Values
78541 +    None
78542 +
78543 +
78544 +=====================================================================
78545 +
78546 +
78547 +Name
78548 +    GET_WOW_LIST_EVENT
78549 +
78550 +Synopsis
78551 +    Response to the wmiconfig \96getwowlist command to retrieve the configured Wake on
78552 +    Wireless patterns
78553 +
78554 +Event ID
78555 +    0x10018
78556 +
78557 +Event Parameters
78558 +    {
78559 +
78560 +    A_UINT8    num_filters
78561 +        Total number of patterns in the list
78562 +    A_UINT8    this_filter_num
78563 +        The filter number
78564 +    A_UINT8    wow_mode
78565 +        Shows whether WoW is enabled or disabled
78566 +    A_UINT8    host_mode
78567 +        Shows whether the host is asleep or awake
78568 +    WOW_FILTER    wow_filters[1]
78569 +        List of WoW filters (pattern and mask data bytes)
78570 +    } WMI_GET_WOW_LIST_REPLY;
78571 +
78572 +    {
78573 +        Each wow_filter_list element shows:
78574 +    A_UINT8    wow_valid_filter
78575 +        Whether the filter is valid
78576 +    A_UINT8    wow_filter_list_id
78577 +        Filter List ID (23 = default)
78578 +    A_UINT8    wow_filter_size
78579 +        Size in bytes of the filter
78580 +    A_UINT8    wow_filter_offset
78581 +        Offset of the pattern to search in the data packet
78582 +    A_UINT8    wow_filter_mask[MASK_SIZE]
78583 +        The mask to be applied to the pattern
78584 +    A_UINT8    wow_filter_pattern[WOW_PATTERN_SIZE]
78585 +        The pattern that to match to wake up the host
78586 +    } WOW_FILTER
78587 +
78588 +Event Values
78589 +    None
78590 +
78591 +=====================================================================
78592 +
78593 +
78594 +
78595 +Name
78596 +    NEIGHBOR_REPORT
78597 +
78598 +Synopsis
78599 +    Indicates the existence of neighbor APs that match the current profile. The host uses
78600 +    this event to populate the PMKID cache on the AR6000 and/or to perform
78601 +    preauthentication. This event is only generated in infrastructure mode.
78602 +
78603 +    A total of numberOfAps pairs of bssid/bssFlags exist, one pair for each AP.
78604 +
78605 +Event ID
78606 +    0x1008
78607 +
78608 +Event Parameters
78609 +    UINT8    numberOfAps
78610 +        The number of APs reported about in
78611 +        this event
78612 +    {
78613 +        UINT8    bssid[6]
78614 +            MAC address of a neighbor AP
78615 +        UINT8    bssFlags
78616 +            A WMI_BSS_FLAGS value
78617 +    }[numberOfAps]
78618 +
78619 +
78620 +Event Values
78621 +    {
78622 +        WMI_DEFAULT_BSS_FLAGS    = 0
78623 +            Logical OR of 1 or more
78624 +        WMI_BSS_FLAGS
78625 +        WMI_PREAUTH_CAPABLE_BSS
78626 +            = 1
78627 +            Indicates that this AP is capable of
78628 +            preauthentication
78629 +        WMI_PMKID_VALID_BSS
78630 +            = 2
78631 +            Indicates that the AR6000 have a
78632 +            valid pairwise master key for this AP
78633 +    } WMI_BSS_FLAGS
78634 +
78635 +
78636 +=====================================================================
78637 +
78638 +
78639 +
78640 +Name
78641 +    OPT_RX_FRAME_EVENT
78642 +
78643 +Synopsis
78644 +    Special feature, informs host of the reception of a special frame.
78645 +
78646 +Event ID
78647 +    0x100E
78648 +
78649 +Event Parameters
78650 +    {
78651 +        A_UINT16    channel;
78652 +        A_UINT8    frameType;
78653 +        A_INT8    snr;
78654 +        A_UINT8    srcAddr[ATH_MAC_LEN];
78655 +        A_UINT8    bssid[ATH_MAC_LEN];
78656 +        }WMI_OPT_RX_INFO_HDR
78657 +
78658 +Event Values
78659 +    None
78660 +
78661 +=====================================================================
78662 +
78663 +
78664 +
78665 +Name
78666 +    PSTREAM_TIMEOUT
78667 +
78668 +Synopsis
78669 +    Indicates that a priority stream that got created as a result of priority-marked data
78670 +    flow (priority marked in IP TOS) being idle for the default inactivity interval period
78671 +    (specified in the \93CREATE_PSTREAM\94 command) used for priority streams created
78672 +    implicitly by the driver. This event is not indicated for user-created priority streams.
78673 +    User-created priority streams exist until the users delete them explicitly. They do not
78674 +    timeout due to data inactivity.
78675 +
78676 +Event ID
78677 +    0x1007
78678 +
78679 +Event Parameters
78680 +    A_UINT8
78681 +    trafficClass
78682 +    Indicated the traffic class of priority
78683 +    stream that timed out
78684 +
78685 +Event Values
78686 +    {
78687 +        WMM_AC_BE    = 0
78688 +            Best effort
78689 +        WMM_AC_BK    = 1
78690 +            Background
78691 +        WMM_AC_VI    = 2
78692 +            Video
78693 +        WMM_AC_VO     = 3
78694 +            Voice
78695 +    } TRAFFIC CLASS
78696 +
78697 +
78698 +=====================================================================
78699 +
78700 +Name
78701 +    READY
78702 +
78703 +Synopsis
78704 +    Indicates that the AR6000 device is prepared to accept commands. It is sent once after
78705 +    power on or reset. It also indicates the MAC address of the device.
78706 +
78707 +Event ID
78708 +    0x1001
78709 +
78710 +Event Parameters
78711 +    UINT8    macAddr[6]
78712 +        Device MAC address
78713 +    UINT8    phyCapability
78714 +        A WMI_PHY_CAPABILITY value. Indicates the
78715 +        capabilities of the device wireless module\92s radio
78716 +
78717 +Event Values
78718 +    {
78719 +        WMI_11A_CAPABILITY       = 1
78720 +        WMI_11G_CAPABILITY       = 2
78721 +        WMI_11AG_CAPABILITY      = 3
78722 +    } WMI_PHY_CAPABILITY
78723 +
78724 +
78725 +=====================================================================
78726 +
78727 +Name
78728 +    REGDOMAIN
78729 +
78730 +Synopsis
78731 +    Indicates that the regulatory domain has changed. It initially occurs when the
78732 +    AR6000 device reads the board data information. The regulatory domain can also
78733 +    change when the device is a world-mode SKU. In this case, the regulatory domain is
78734 +    based on the country advertised by APs per the IEEE 802.11d specification. A
78735 +    potential side effect of a regulatory domain change is a change in the list of available
78736 +    channels. Any channel restrictions that exist as a result of a previous
78737 +    \93SET_CHANNEL_PARAMETERS\94 command are lifted.
78738 +
78739 +Event ID
78740 +    0x1006
78741 +
78742 +Event Parameters
78743 +    UINT32    regDomain
78744 +        The range of 0x0000 \96 0x00FF
78745 +        corresponds to an ISO country code.
78746 +
78747 +    Other regCodes are reserved for world
78748 +    mode settings and specific regulatory
78749 +    domains.
78750 +
78751 +Event Values
78752 +    None
78753 +
78754 +
78755 +=====================================================================
78756 +
78757 +
78758 +
78759 +Name
78760 +    REPORT_STATISTICS
78761 +
78762 +Synopsis
78763 +    A reply to a \93GET_TARGET_STATS\94 command.
78764 +
78765 +Event ID
78766 +    0x100B
78767 +
78768 +Event Parameters
78769 +    When the statistics are sent to the host, the AR6001 clear them so that a new set of
78770 +    statistics are collected for the next report.
78771 +
78772 +    UINT32    tx_packets
78773 +    UINT32    tx_bytes
78774 +    UINT32    tx_unicast_pkts
78775 +    UINT32    tx_unicast_bytes
78776 +    UINT32    tx_multicast_pkts
78777 +    UINT32    tx_multicast_bytes
78778 +    UINT32    tx_broadcast_pkts
78779 +    UINT32    tx_broadcast_bytes
78780 +    UINT32    tx_rts_success_cnt
78781 +    UINT32    tx_packet_per_ac[4]
78782 +        Tx packets per AC: [0] = BE, [1] = BK,
78783 +        [2] = VI, [3] = VO
78784 +    UINT32    tx_errors
78785 +        Number of packets which failed Tx, due
78786 +        to all failures
78787 +    ... REPORT_STATISTICS, continued
78788 +    UINT32    tx_failed_cnt
78789 +        Number of data packets that failed Tx
78790 +    UINT32    tx_retry_cnt
78791 +        Number of Tx retries for all packets
78792 +    UINT32    tx_rts_fail_cnt
78793 +        Number of RTS Tx failed count
78794 +    UINT32    rx_packets
78795 +    UINT32    rx_bytes
78796 +    UINT32    rx_unicast_pkts
78797 +    UINT32    rx_unicast_bytes
78798 +    UINT32    rx_multicast_pkts
78799 +    UINT32    rx_multicast_bytes
78800 +    UINT32    rx_broadcast_pkts
78801 +    UINT32    rx_broadcast_bytes
78802 +    UINT32    rx_fragment_pkt
78803 +        Number of fragmented packets received
78804 +    UINT32    rx_errors
78805 +        Number of Rx errors due to all failures
78806 +    UINT32    rx_crcerr
78807 +        Number of Rx errors due to CRC errors
78808 +    UINT32    rx_key_cache_miss
78809 +        Number of Rx errors due to a key not
78810 +        being plumbed
78811 +    UINT32    rx_decrypt_err
78812 +        Number of Rx errors due to decryption
78813 +        failure
78814 +    UINT32    rx_duplicate_frames
78815 +        Number of duplicate frames received
78816 +    UINT32    tkip_local_mic_failure
78817 +        Number of TKIP MIC errors detected
78818 +    UINT32    tkip_counter_measures_invoked
78819 +        Number of times TKIP countermeasures
78820 +        were invoked
78821 +    UINT32    tkip_replays
78822 +        Number of frames that replayed a TKIP
78823 +        encrypted frame received earlier
78824 +    UINT32    tkip_format_errors
78825 +        Number of frames that did not conform
78826 +        to the TKIP frame format
78827 +    UINT32    ccmp_format_errors
78828 +        Number of frames that did not conform
78829 +        to the CCMP frame format
78830 +    UINT32    ccmp_replays
78831 +        Number of frames that replayed a CCMP
78832 +        encrypted frame received earlier
78833 +    UINT32    power_save_failure_cnt
78834 +        Number of failures that occurred when
78835 +        the AR6001 could not go to sleep
78836 +    UINT32    cs_bmiss_cnt
78837 +        Number of BMISS interrupts since
78838 +    connection
78839 +    UINT32    cs_lowRssi_cnt
78840 +        Number of the times the RSSI went below
78841 +        the low RSSI threshold
78842 +    UINT16    cs_connect_cnt
78843 +        Number of connection times
78844 +    UINT16    cs_disconnect_cnt
78845 +        Number of disconnection times
78846 +    UINT8    cs_aveBeacon_rssi
78847 +        The current averaged value of the RSSI
78848 +        from the beacons of the connected BSS
78849 +    UINT8    cs_lastRoam_msec
78850 +        Time that the last roaming took, in ms.
78851 +        This time is the difference between
78852 +        roaming start and actual connection.
78853 +
78854 +Event Values
78855 +    None defined
78856 +
78857 +
78858 +=====================================================================
78859 +
78860 +Name
78861 +    ROAM_TBL_EVENT
78862 +
78863 +Synopsis
78864 +    Reports the roam table, which contains the current roam mode and this information
78865 +    for every BSS:
78866 +
78867 +Event ID
78868 +    0x100F
78869 +
78870 +Event Parameters
78871 +    A_UINT8     bssid[ATH_MAC_LEN];
78872 +        BSSID
78873 +    A_UINT8     rssi
78874 +        Averaged RSSI
78875 +    A_UINT8     rssidt
78876 +        Change in RSSI
78877 +    A_UINT8     last_rssi
78878 +        Last recorded RSSI
78879 +    A_UINT8     roam_util
78880 +        Utility value used in roaming decision
78881 +    A_UINT8     util
78882 +        Base utility with the BSS
78883 +    A_UINT8     bias
78884 +        Host configured for this BSS
78885 +
78886 +Event Values
78887 +    roamMode
78888 +        Current roam mode
78889 +
78890 +        = 1
78891 +    RSSI based roam
78892 +
78893 +        = 2
78894 +    Host bias-based roam
78895 +
78896 +        = 3
78897 +    Lock to the current BSS
78898 +
78899 +        = 4
78900 +    Autonomous roaming disabled
78901 +
78902 +
78903 +=====================================================================
78904 +
78905 +Name
78906 +    RSSI_THRESHOLD
78907 +
78908 +Synopsis
78909 +    Alerts the host that the signal strength from the connected AP has crossed a
78910 +    interesting threshold as defined in a previous \93RSSI_THRESHOLD_PARAMS\94
78911 +    command.
78912 +
78913 +Event ID
78914 +    0x100C
78915 +
78916 +Event Parameters
78917 +    UINT8    range
78918 +        A WMI_RSSI_THRESHOLD_VAL
78919 +        value, which indicates the range of
78920 +        the average signal strength
78921 +
78922 +Event Values
78923 +    {
78924 +        WMI_RSSI_LOWTHRESHOLD_BELOW_LOWERVAL  = 1
78925 +        WMI_RSSI_LOWTHRESHOLD_LOWERVAL        = 2
78926 +        WMI_RSSI_LOWTHRESHOLD_UPPERVAL        = 3
78927 +        WMI_RSSI_HIGHTHRESHOLD_LOWERVAL       = 4
78928 +        WMI_RSSI_HIGHTHRESHOLD_HIGHERVAL      = 5
78929 +    } WMI_RSSI_THRESHOLD_VAL
78930 +
78931 +
78932 +=====================================================================
78933 +
78934 +Name
78935 +    SCAN_COMPLETE_EVENT
78936 +
78937 +Synopsis
78938 +    Indicates the scan status. if the Scan was not completed, this event is generated with
78939 +    the status A_ECANCELED.
78940 +
78941 +Event ID
78942 +    0x100A
78943 +
78944 +Event Parameters
78945 +    A_UINT8    scanStatus
78946 +
78947 +Event Values
78948 +    {
78949 +        #define     SCAN_ABORTED 16
78950 +        #define     SCAN_COMPLETED 0
78951 +        A_UINT8     scanStatus
78952 +            A_OK or A_ECANCELED
78953 +    } WMI_SCAN_COMPLETE_EVENT;
78954 +
78955 +
78956 +=====================================================================
78957 +
78958 +Name
78959 +    TEST_EVENT
78960 +
78961 +Synopsis
78962 +    The TCMD application uses a single WMI event (WMI_TEST_EVENTID) to
78963 +    communicate events from target to host. The events are parsed by the TCMD
78964 +    application and WMI layer is oblivious of it.
78965 +
78966 +Event ID
78967 +    0x1016
78968 +
78969 +Event Parameters
78970 +    WMI_TEST_EVENTID
78971 +
78972 +
78973 +Event Values
78974 +    None
78975 +
78976 +
78977 +=====================================================================
78978 +
78979 +
78980 +
78981 +Name
78982 +    TKIP_MICERR
78983 +
78984 +Synopsis
78985 +    Indicates that TKIP MIC errors were detected.
78986 +
78987 +Event ID
78988 +    0x1009
78989 +
78990 +Event Parameters
78991 +    UINT8    keyid
78992 +        Indicates the TKIP key ID
78993 +
78994 +    UINT8    ismcast
78995 +        0 = Unicast
78996 +        1 = Multicast
78997 +
78998 +Event Values
78999 +    See event parameters
79000 +
79001 +=====================================================================
79002 +
79003 +WMI Extension Commands
79004 +
79005 +The WMI EXTENSION command is used to multiplex a collection of
79006 +commands that:
79007 +
79008 +        Are not generic wireless commands
79009 +        May be implementation-specific
79010 +        May be target platform-specific
79011 +        May be optional for a host implementation
79012 +
79013 +    An extension command is sent to the AR6000 targets like any other WMI
79014 +command message and uses the WMI_EXTENSION. The first field of the
79015 +payload for this EXTENSION command is another commandId, sometimes
79016 +called the subcommandId, which indicates which extension command is
79017 +being used. A subcommandId-specific payload follows the subcommandId.
79018 +
79019 +All extensions (subcommandIds) are listed in the header file include/wmix.h.
79020 +See also \93WMI Extension Events\94 on page B-58.
79021 +
79022 +
79023 +WMI Extension Commands
79024 +
79025 +
79026 +GPIO_INPUT_GET
79027 +    Read GPIO pins configured for input
79028 +
79029 +GPIO_INTR_ACK
79030 +    Acknowledge and re-arm GPIO interrupts reported earlier
79031 +
79032 +GPIO_OUTPUT_SET
79033 +    Manage output on GPIO pins configured for output
79034 +
79035 +GPIO_REGISTER_GET
79036 +    Read an arbitrary GPIO register
79037 +
79038 +GPIO_REGISTER_SET
79039 +    Dynamically change GPIO configuration
79040 +
79041 +SET_LQTHRESHOLD
79042 +    Set link quality thresholds; the sampling happens at every unicast
79043 +    data frame Tx, if certain thresholds are met, and corresponding
79044 +    events are sent to the host
79045 +
79046 +
79047 +=====================================================================
79048 +
79049 +Name
79050 +    GPIO_INPUT_GET
79051 +
79052 +Synopsis
79053 +    Allows the host to read GPIO pins that are configured for input. The values read are
79054 +    returned through a \93GPIO_DATA\94 extension event.
79055 +
79056 +NOTE: Support for GPIO is optional.
79057 +
79058 +Command
79059 +    N/A
79060 +
79061 +Command Parameters
79062 +    None
79063 +
79064 +
79065 +
79066 +Reply Parameters
79067 +    None
79068 +
79069 +
79070 +Reset Value
79071 +    None
79072 +
79073 +
79074 +
79075 +Restrictions
79076 +    None
79077 +
79078 +=====================================================================
79079 +
79080 +
79081 +Name
79082 +    GPIO_INTR_ACK
79083 +
79084 +Synopsis
79085 +    The host uses this command to acknowledge and to re-arm GPIO interrupts reported
79086 +    through an earlier \93GPIO_INTR\94 extension event. A single \93GPIO_INTR_ACK\94
79087 +    command should be used to acknowledge all GPIO interrupts that the host knows to
79088 +    be outstanding (if pending interrupts are not acknowledged through
79089 +    \93GPIO_INTR_ACK\94, another \93GPIO_INTR\94 extension event is raised).
79090 +
79091 +NOTE: Support for GPIO is optional.
79092 +
79093 +Command
79094 +    N/A
79095 +
79096 +Command Parameters
79097 +    UINT32    ack_mask
79098 +        A mask of interrupting GPIO pins (e.g., ack_mask
79099 +        bit [3] acknowledges an interrupt from the pin GPIO3).
79100 +
79101 +Command Values
79102 +    None
79103 +
79104 +Reset Value
79105 +    None
79106 +
79107 +Restrictions
79108 +    The host should acknowledge only interrupts about which it was notified.
79109 +
79110 +
79111 +=====================================================================
79112 +
79113 +Name
79114 +    GPIO_OUTPUT_SET
79115 +
79116 +Synopsis
79117 +    Manages output on GPIO pins configured for output.
79118 +
79119 +    Conflicts between set_mask and clear_mask or enable_mask and disable_mask result
79120 +    in undefined behavior.
79121 +
79122 +NOTE: Support for GPIO is optional.
79123 +
79124 +Command
79125 +    N/A
79126 +
79127 +Command Parameters
79128 +    UINT32    set_mask
79129 +        Specifies which pins should drive a 1 out
79130 +    UINT32    clear_mask
79131 +        Specifies which pins should drive a 0 out
79132 +    UINT32    enable_mask
79133 +        Specifies which pins should be enabled for output
79134 +    UINT32    disable_mask
79135 +        Specifies which pins should be disabled for output
79136 +
79137 +Command Values
79138 +    None
79139 +
79140 +
79141 +Reset Value
79142 +    None
79143 +
79144 +
79145 +Restrictions
79146 +    None
79147 +
79148 +
79149 +
79150 +=====================================================================
79151 +
79152 +
79153 +Name
79154 +    GPIO_REGISTER_GET
79155 +
79156 +Synopsis
79157 +    Allows the host to read an arbitrary GPIO register. It is intended for use during
79158 +    bringup/debug. The target responds to this command with a \93GPIO_DATA\94 event.
79159 +
79160 +NOTE: Support for GPIO is optional.
79161 +
79162 +Command
79163 +    N/A
79164 +
79165 +Command Parameters
79166 +    UINT32
79167 +    gpioreg_id
79168 +    Specifies a GPIO register identifier, as defined
79169 +in include/AR6000/AR6000_gpio.h
79170 +
79171 +Reply Parameters
79172 +    None
79173 +
79174 +Reset Value
79175 +    N/A
79176 +
79177 +Restrictions
79178 +    None
79179 +
79180 +
79181 +=====================================================================
79182 +
79183 +Name
79184 +    GPIO_REGISTER_SET
79185 +
79186 +Synopsis
79187 +    Allows the host to dynamically change GPIO configuration (usually handled
79188 +    statically through the GPIO configuration DataSet).
79189 +
79190 +NOTE: Support for GPIO is optional.
79191 +
79192 +Command
79193 +    N/A
79194 +
79195 +Command Parameters
79196 +    UINT32    gpioreg_id
79197 +        Specifies a GPIO register identifier, as defined in
79198 +        include/AR6000/AR6000_gpio.h
79199 +    UINT32    value
79200 +        Specifies a value to write to the specified
79201 +        GPIO register
79202 +
79203 +Command Values
79204 +    None
79205 +
79206 +
79207 +Reset Value
79208 +    Initial hardware configuration is as defined in the AR6001 or AR6002 ROCmTM
79209 +    Single-Chip MAC/BB/Radio for 2.4/5 GHz Embedded WLAN Applications data sheet. This
79210 +    configuration is modified by the GPIO Configuration DataSet, if one exists.
79211 +
79212 +Restrictions
79213 +    None
79214 +
79215 +
79216 +=====================================================================
79217 +
79218 +
79219 +Name
79220 +    SET_LQTHRESHOLD
79221 +
79222 +Synopsis
79223 +    Set link quality thresholds, the sampling happens at every unicast data frame Tx, if
79224 +    certain threshold is met, corresponding event will be sent to host.
79225 +
79226 +Command
79227 +    wmiconfig eth1 --lqThreshold <enable> <upper_threshold_1>...
79228 +    <upper_threshold_4> <lower_threshold_1>... <lower_threshold_4>
79229 +
79230 +Command Parameters
79231 +    A_UINT8   enable;
79232 +    A_UINT8   thresholdAbove1_Val;
79233 +    A_UINT8   thresholdAbove2_Val;
79234 +    A_UINT8   thresholdAbove3_Val;
79235 +    A_UINT8   thresholdAbove4_Val;
79236 +    A_UINT8   thresholdBelow1_Val;
79237 +    A_UINT8   thresholdBelow2_Val;
79238 +    A_UINT8   thresholdBelow3_Val;
79239 +    A_UINT8   thresholdBelow4_Val;
79240 +
79241 +Command Values
79242 +    enable
79243 +    = 0
79244 +    Disable link quality sampling
79245 +
79246 +        = 1
79247 +    Enable link quality sampling
79248 +
79249 +
79250 +    thresholdAbove_Val
79251 +    [1...4]
79252 +    Above thresholds (value in [0,100]), in ascending
79253 +    order threshold
79254 +
79255 +    Below_Val [1...4] = below thresholds (value
79256 +    in [0,100]), in ascending order
79257 +
79258 +Reset Values
79259 +    None
79260 +
79261 +Restrictions
79262 +    None
79263 +
79264 +=====================================================================
79265 +WMI Extension Events
79266 +
79267 +The WMI EXTENSION event is used for a collection of events that:
79268 +
79269 +    Are not generic wireless events
79270 +    May be implementation-specific
79271 +    May be target platform-specific
79272 +    May be optional for a host implementation
79273 +
79274 +    An extension event is sent from the AR6000 device targets to the host just like
79275 +any other WMI event message, using the WMI_EXTENSION_EVENTID. The
79276 +first field of the payload for this \93EXTENSION\94 event is another commandId
79277 +(sometimes called the subcommandId) that indicates which \93EXTENSION\94
79278 +event is being used. A subcommandId-specific payload follows the
79279 +subcommandId.
79280 +
79281 +All extensions (subcommandIds) are listed in the header file include/wmix.h.
79282 +See also \93WMI Extension Commands\94 on page B-55.
79283 +
79284 +
79285 +WMI Extension Events
79286 +
79287 +
79288 +GPIO_ACK
79289 +    Acknowledges a host set command has been processed by the device
79290 +
79291 +GPIO_DATA
79292 +    Response to a host\92s request for data
79293 +
79294 +GPIO_INTR
79295 +    Signals that GPIO interrupts are pending
79296 +
79297 +
79298 +=====================================================================
79299 +
79300 +Name
79301 +    GPIO_ACK
79302 +
79303 +Synopsis
79304 +    Acknowledges that a host set command (either \93GPIO_OUTPUT_SET\94 or
79305 +    \93GPIO_REGISTER_SET\94) has been processed by the AR6000 device.
79306 +
79307 +NOTE: Support for GPIO is optional.
79308 +
79309 +Event ID
79310 +    N/A
79311 +
79312 +Event Parameters
79313 +    None
79314 +
79315 +
79316 +Event Values
79317 +    None
79318 +
79319 +=====================================================================
79320 +
79321 +
79322 +Name
79323 +    GPIO_DATA
79324 +
79325 +Synopsis
79326 +    The AR6000 device uses this event to respond to the host\92s earlier request for data
79327 +    (through either a \93GPIO_REGISTER_GET\94 or a \93GPIO_INPUT_GET\94 command).
79328 +
79329 +NOTE: Support for GPIO is optional.
79330 +
79331 +Event ID
79332 +    N/A
79333 +
79334 +Event Parameters
79335 +    UINT32    value
79336 +        Holds the data of interest, which is either a register value
79337 +        (in the case of \93GPIO_REGISTER_GET\94) or a mask of
79338 +        pin inputs (in the case of \93GPIO_INPUT_GET\94).
79339 +    UINT32    reg_id
79340 +        Indicates which register was read (in the case of
79341 +        \93GPIO_REGISTER_GET\94) or is GPIO_ID_NONE (in the
79342 +        case of \93GPIO_INPUT_GET\94)
79343 +
79344 +Event Values
79345 +    None
79346 +
79347 +
79348 +=====================================================================
79349 +
79350 +
79351 +
79352 +Name
79353 +    GPIO_INTR
79354 +
79355 +Synopsis
79356 +    The AR6000 device raises this event to signal that GPIO interrupts are pending.
79357 +    These GPIOs may be interrupts that occurred after the last \93GPIO_INTR_ACK\94
79358 +    command was issued, or may be GPIO interrupts that the host failed to acknowledge
79359 +    in the last \93GPIO_INTR_ACK\94. The AR6000 will not raise another GPIO_INTR
79360 +    event until this event is acknowledged through a \93GPIO_INTR_ACK\94 command.
79361 +
79362 +NOTE: Support for GPIO is optional.
79363 +
79364 +Event ID
79365 +    N/A
79366 +
79367 +Event Parameters
79368 +    UINT32    intr_mask
79369 +        Indicates which GPIO interrupts are currently pending
79370 +
79371 +    UINT32    input_values
79372 +        A recent copy of the GPIO input values, taken at the
79373 +        time the most recent GPIO interrupt was processed
79374 +
79375 +Event Values
79376 +    None
79377 +
79378 +
79379 +
79380 +=====================================================================
79381 +#endif
79382 Index: linux-2.6.28/drivers/ar6000/wmi/wmi_host.h
79383 ===================================================================
79384 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
79385 +++ linux-2.6.28/drivers/ar6000/wmi/wmi_host.h  2009-01-02 00:01:56.000000000 +0100
79386 @@ -0,0 +1,71 @@
79387 +#ifndef _WMI_HOST_H_
79388 +#define _WMI_HOST_H_
79389 +/*
79390 + * Copyright (c) 2004-2006 Atheros Communications Inc.
79391 + * All rights reserved.
79392 + *
79393 + * This file contains local definitios for the wmi host module.
79394 + *
79395 + * $Id: //depot/sw/releases/olca2.0-GPL/host/wmi/wmi_host.h#1 $
79396 + *
79397 + *
79398 + *  This program is free software; you can redistribute it and/or modify
79399 + *  it under the terms of the GNU General Public License version 2 as
79400 + *  published by the Free Software Foundation;
79401 + *
79402 + *  Software distributed under the License is distributed on an "AS
79403 + *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
79404 + *  implied. See the License for the specific language governing
79405 + *  rights and limitations under the License.
79406 + *
79407 + *
79408 + *
79409 + */
79410 +
79411 +#ifdef __cplusplus
79412 +extern "C" {
79413 +#endif
79414 +
79415 +struct wmi_stats {
79416 +    A_UINT32    cmd_len_err;
79417 +    A_UINT32    cmd_id_err;
79418 +};
79419 +
79420 +struct wmi_t {
79421 +    A_BOOL                          wmi_ready;
79422 +    A_BOOL                          wmi_numQoSStream;
79423 +    A_UINT8                         wmi_wmiStream2AcMapping[WMI_PRI_MAX_COUNT];
79424 +    WMI_PRI_STREAM_ID               wmi_ac2WmiStreamMapping[WMM_NUM_AC];
79425 +    A_UINT16                        wmi_streamExistsForAC[WMM_NUM_AC];
79426 +    A_UINT8                         wmi_fatPipeExists;
79427 +    void                           *wmi_devt;
79428 +    struct wmi_stats                wmi_stats;
79429 +    struct ieee80211_node_table     wmi_scan_table;
79430 +    A_UINT8                         wmi_bssid[ATH_MAC_LEN];
79431 +    A_UINT8                         wmi_powerMode;
79432 +    A_UINT8                         wmi_phyMode;
79433 +    A_UINT8                         wmi_keepaliveInterval;
79434 +    A_MUTEX_T                       wmi_lock;
79435 +};
79436 +
79437 +#define WMI_INIT_WMISTREAM_AC_MAP(w) \
79438 +{  (w)->wmi_wmiStream2AcMapping[WMI_BEST_EFFORT_PRI] = WMM_AC_BE; \
79439 +   (w)->wmi_wmiStream2AcMapping[WMI_LOW_PRI] = WMM_AC_BK; \
79440 +   (w)->wmi_wmiStream2AcMapping[WMI_HIGH_PRI] = WMM_AC_VI; \
79441 +   (w)->wmi_wmiStream2AcMapping[WMI_HIGHEST_PRI] = WMM_AC_VO; \
79442 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_BE] = WMI_BEST_EFFORT_PRI; \
79443 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_BK] = WMI_LOW_PRI; \
79444 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_VI] = WMI_HIGH_PRI; \
79445 +   (w)->wmi_ac2WmiStreamMapping[WMM_AC_VO] = WMI_HIGHEST_PRI; }
79446 +
79447 +#define WMI_WMISTREAM_ACCESSCATEGORY(w,s)      (w)->wmi_wmiStream2AcMapping[s]
79448 +#define WMI_ACCESSCATEGORY_WMISTREAM(w,ac)       (w)->wmi_ac2WmiStreamMapping[ac]
79449 +
79450 +#define LOCK_WMI(w)     A_MUTEX_LOCK(&(w)->wmi_lock);
79451 +#define UNLOCK_WMI(w)   A_MUTEX_UNLOCK(&(w)->wmi_lock);
79452 +
79453 +#ifdef __cplusplus
79454 +}
79455 +#endif
79456 +
79457 +#endif /* _WMI_HOST_H_ */
79458 Index: linux-2.6.28/drivers/base/bus.c
79459 ===================================================================
79460 --- linux-2.6.28.orig/drivers/base/bus.c        2008-12-25 00:26:37.000000000 +0100
79461 +++ linux-2.6.28/drivers/base/bus.c     2009-01-02 00:01:56.000000000 +0100
79462 @@ -141,6 +141,29 @@ void bus_remove_file(struct bus_type *bu
79463  }
79464  EXPORT_SYMBOL_GPL(bus_remove_file);
79465
79466 +int bus_create_device_link(struct bus_type *bus, struct kobject *target,
79467 +                          const char *name)
79468 +{
79469 +       int error;
79470 +       if (bus_get(bus)) {
79471 +               error = sysfs_create_link(&bus->p->devices_kset->kobj, target,
79472 +                                         name);
79473 +               bus_put(bus);
79474 +       } else
79475 +               error = -EINVAL;
79476 +       return error;
79477 +}
79478 +EXPORT_SYMBOL_GPL(bus_create_device_link);
79479 +
79480 +void bus_remove_device_link(struct bus_type *bus, const char *name)
79481 +{
79482 +       if (bus_get(bus)) {
79483 +               sysfs_remove_link(&bus->p->devices_kset->kobj, name);
79484 +               bus_put(bus);
79485 +       }
79486 +}
79487 +EXPORT_SYMBOL_GPL(bus_remove_device_link);
79488 +
79489  static struct kobj_type bus_ktype = {
79490         .sysfs_ops      = &bus_sysfs_ops,
79491  };
79492 Index: linux-2.6.28/drivers/base/core.c
79493 ===================================================================
79494 --- linux-2.6.28.orig/drivers/base/core.c       2008-12-25 00:26:37.000000000 +0100
79495 +++ linux-2.6.28/drivers/base/core.c    2009-01-02 00:01:56.000000000 +0100
79496 @@ -55,6 +55,11 @@ static inline int device_is_not_partitio
79497   */
79498  const char *dev_driver_string(const struct device *dev)
79499  {
79500 +       if (!dev) {
79501 +               printk(KERN_ERR"Null dev to dev_driver_string\n");
79502 +               dump_stack();
79503 +               return "*NULL*";
79504 +       }
79505         return dev->driver ? dev->driver->name :
79506                         (dev->bus ? dev->bus->name :
79507                         (dev->class ? dev->class->name : ""));
79508 Index: linux-2.6.28/drivers/base/power/main.c
79509 ===================================================================
79510 --- linux-2.6.28.orig/drivers/base/power/main.c 2008-12-25 00:26:37.000000000 +0100
79511 +++ linux-2.6.28/drivers/base/power/main.c      2009-01-02 00:01:56.000000000 +0100
79512 @@ -69,9 +69,9 @@ void device_pm_unlock(void)
79513   */
79514  void device_pm_add(struct device *dev)
79515  {
79516 -       pr_debug("PM: Adding info for %s:%s\n",
79517 +       /* pr_debug("PM: Adding info for %s:%s\n",
79518                  dev->bus ? dev->bus->name : "No Bus",
79519 -                kobject_name(&dev->kobj));
79520 +                kobject_name(&dev->kobj)); */
79521         mutex_lock(&dpm_list_mtx);
79522         if (dev->parent) {
79523                 if (dev->parent->power.status >= DPM_SUSPENDING)
79524 Index: linux-2.6.28/drivers/char/Kconfig
79525 ===================================================================
79526 --- linux-2.6.28.orig/drivers/char/Kconfig      2009-01-02 00:00:02.000000000 +0100
79527 +++ linux-2.6.28/drivers/char/Kconfig   2009-01-02 00:01:56.000000000 +0100
79528 @@ -66,6 +66,18 @@ config VT_CONSOLE
79529
79530           If unsure, say Y.
79531
79532 +config NR_TTY_DEVICES
79533 +       int "Maximum tty device number"
79534 +       depends on VT
79535 +       default 63
79536 +       ---help---
79537 +         This is the highest numbered device created in /dev. You will actually have
79538 +         NR_TTY_DEVICES+1 devices in /dev. The default is 63, which will result in
79539 +         64 /dev entries. The lowest number you can set is 11, anything below that,
79540 +         and it will default to 11. 63 is also the upper limit so we don't overrun
79541 +         the serial consoles.
79542 +
79543 +
79544  config HW_CONSOLE
79545         bool
79546         depends on VT && !S390 && !UML
79547 Index: linux-2.6.28/drivers/gpio/gpiolib.c
79548 ===================================================================
79549 --- linux-2.6.28.orig/drivers/gpio/gpiolib.c    2008-12-25 00:26:37.000000000 +0100
79550 +++ linux-2.6.28/drivers/gpio/gpiolib.c 2009-01-02 00:01:56.000000000 +0100
79551 @@ -6,8 +6,7 @@
79552  #include <linux/err.h>
79553  #include <linux/debugfs.h>
79554  #include <linux/seq_file.h>
79555 -#include <linux/gpio.h>
79556 -
79557 +#include <mach/gpio.h>
79558
79559  /* Optional implementation infrastructure for GPIO interfaces.
79560   *
79561 Index: linux-2.6.28/drivers/i2c/busses/i2c-s3c2410.c
79562 ===================================================================
79563 --- linux-2.6.28.orig/drivers/i2c/busses/i2c-s3c2410.c  2008-12-25 00:26:37.000000000 +0100
79564 +++ linux-2.6.28/drivers/i2c/busses/i2c-s3c2410.c       2009-01-02 00:51:37.000000000 +0100
79565 @@ -34,14 +34,12 @@
79566  #include <linux/platform_device.h>
79567  #include <linux/clk.h>
79568  #include <linux/cpufreq.h>
79569 +#include <linux/io.h>
79570
79571 -#include <mach/hardware.h>
79572  #include <asm/irq.h>
79573 -#include <asm/io.h>
79574
79575 -#include <mach/regs-gpio.h>
79576 -#include <asm/plat-s3c/regs-iic.h>
79577 -#include <asm/plat-s3c/iic.h>
79578 +#include <plat/regs-iic.h>
79579 +#include <plat/iic.h>
79580
79581  /* i2c controller state */
79582
79583 @@ -64,6 +62,7 @@ struct s3c24xx_i2c {
79584         unsigned int            msg_ptr;
79585
79586         unsigned int            tx_setup;
79587 +       unsigned int            irq;
79588
79589         enum s3c24xx_i2c_state  state;
79590         unsigned long           clkrate;
79591 @@ -71,7 +70,6 @@ struct s3c24xx_i2c {
79592         void __iomem            *regs;
79593         struct clk              *clk;
79594         struct device           *dev;
79595 -       struct resource         *irq;
79596         struct resource         *ioarea;
79597         struct i2c_adapter      adap;
79598
79599 @@ -80,16 +78,7 @@ struct s3c24xx_i2c {
79600  #endif
79601  };
79602
79603 -/* default platform data to use if not supplied in the platform_device
79604 -*/
79605 -
79606 -static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
79607 -       .flags          = 0,
79608 -       .slave_addr     = 0x10,
79609 -       .bus_freq       = 100*1000,
79610 -       .max_freq       = 400*1000,
79611 -       .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
79612 -};
79613 +/* default platform data removed, dev should always carry data. */
79614
79615  /* s3c24xx_i2c_is2440()
79616   *
79617 @@ -103,21 +92,6 @@ static inline int s3c24xx_i2c_is2440(str
79618         return !strcmp(pdev->name, "s3c2440-i2c");
79619  }
79620
79621 -
79622 -/* s3c24xx_i2c_get_platformdata
79623 - *
79624 - * get the platform data associated with the given device, or return
79625 - * the default if there is none
79626 -*/
79627 -
79628 -static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
79629 -{
79630 -       if (dev->platform_data != NULL)
79631 -               return (struct s3c2410_platform_i2c *)dev->platform_data;
79632 -
79633 -       return &s3c24xx_i2c_default_platform;
79634 -}
79635 -
79636  /* s3c24xx_i2c_master_complete
79637   *
79638   * complete the message and wake up the caller, using the given return code,
79639 @@ -130,7 +104,7 @@ static inline void s3c24xx_i2c_master_co
79640
79641         i2c->msg_ptr = 0;
79642         i2c->msg = NULL;
79643 -       i2c->msg_idx ++;
79644 +       i2c->msg_idx++;
79645         i2c->msg_num = 0;
79646         if (ret)
79647                 i2c->msg_idx = ret;
79648 @@ -141,19 +115,17 @@ static inline void s3c24xx_i2c_master_co
79649  static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
79650  {
79651         unsigned long tmp;
79652 -
79653 +
79654         tmp = readl(i2c->regs + S3C2410_IICCON);
79655         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
79656 -
79657  }
79658
79659  static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
79660  {
79661         unsigned long tmp;
79662 -
79663 +
79664         tmp = readl(i2c->regs + S3C2410_IICCON);
79665         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
79666 -
79667  }
79668
79669  /* irq enable/disable functions */
79670 @@ -161,15 +133,23 @@ static inline void s3c24xx_i2c_enable_ac
79671  static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
79672  {
79673         unsigned long tmp;
79674 -
79675 +
79676         tmp = readl(i2c->regs + S3C2410_IICCON);
79677 +
79678 +/* S3c2442 datasheet
79679 + *
79680 + * If the IICCON[5]=0, IICCON[4] does not operate correctly.
79681 + * So, It is recommended that you should set IICCON[5]=1,
79682 + * although you does not use the IIC interrupt.
79683 + */
79684 +
79685         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
79686  }
79687
79688  static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
79689  {
79690         unsigned long tmp;
79691 -
79692 +
79693         tmp = readl(i2c->regs + S3C2410_IICCON);
79694         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
79695  }
79696 @@ -177,10 +157,10 @@ static inline void s3c24xx_i2c_enable_ir
79697
79698  /* s3c24xx_i2c_message_start
79699   *
79700 - * put the start of a message onto the bus
79701 + * put the start of a message onto the bus
79702  */
79703
79704 -static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
79705 +static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
79706                                       struct i2c_msg *msg)
79707  {
79708         unsigned int addr = (msg->addr & 0x7f) << 1;
79709 @@ -199,15 +179,15 @@ static void s3c24xx_i2c_message_start(st
79710         if (msg->flags & I2C_M_REV_DIR_ADDR)
79711                 addr ^= 1;
79712
79713 -       // todo - check for wether ack wanted or not
79714 +       /* todo - check for wether ack wanted or not */
79715         s3c24xx_i2c_enable_ack(i2c);
79716
79717         iiccon = readl(i2c->regs + S3C2410_IICCON);
79718         writel(stat, i2c->regs + S3C2410_IICSTAT);
79719 -
79720 +
79721         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
79722         writeb(addr, i2c->regs + S3C2410_IICDS);
79723 -
79724 +
79725         /* delay here to ensure the data byte has gotten onto the bus
79726          * before the transaction is started */
79727
79728 @@ -215,8 +195,8 @@ static void s3c24xx_i2c_message_start(st
79729
79730         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
79731         writel(iiccon, i2c->regs + S3C2410_IICCON);
79732 -
79733 -       stat |=  S3C2410_IICSTAT_START;
79734 +
79735 +       stat |= S3C2410_IICSTAT_START;
79736         writel(stat, i2c->regs + S3C2410_IICSTAT);
79737  }
79738
79739 @@ -227,11 +207,11 @@ static inline void s3c24xx_i2c_stop(stru
79740         dev_dbg(i2c->dev, "STOP\n");
79741
79742         /* stop the transfer */
79743 -       iicstat &= ~ S3C2410_IICSTAT_START;
79744 +       iicstat &= ~S3C2410_IICSTAT_START;
79745         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
79746 -
79747 +
79748         i2c->state = STATE_STOP;
79749 -
79750 +
79751         s3c24xx_i2c_master_complete(i2c, ret);
79752         s3c24xx_i2c_disable_irq(i2c);
79753  }
79754 @@ -241,7 +221,7 @@ static inline void s3c24xx_i2c_stop(stru
79755
79756  /* is_lastmsg()
79757   *
79758 - * returns TRUE if the current message is the last in the set
79759 + * returns TRUE if the current message is the last in the set
79760  */
79761
79762  static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
79763 @@ -289,14 +269,14 @@ static int i2s_s3c_irq_nextbyte(struct s
79764
79765         case STATE_STOP:
79766                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
79767 -               s3c24xx_i2c_disable_irq(i2c);
79768 +               s3c24xx_i2c_disable_irq(i2c);
79769                 goto out_ack;
79770
79771         case STATE_START:
79772                 /* last thing we did was send a start condition on the
79773                  * bus, or started a new i2c message
79774                  */
79775 -
79776 +
79777                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
79778                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
79779                         /* ack was not received... */
79780 @@ -322,7 +302,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79781                 if (i2c->state == STATE_READ)
79782                         goto prepare_read;
79783
79784 -               /* fall through to the write state, as we will need to
79785 +               /* fall through to the write state, as we will need to
79786                  * send a byte as well */
79787
79788         case STATE_WRITE:
79789 @@ -339,7 +319,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79790                         }
79791                 }
79792
79793 -       retry_write:
79794 + retry_write:
79795
79796                 if (!is_msgend(i2c)) {
79797                         byte = i2c->msg->buf[i2c->msg_ptr++];
79798 @@ -359,9 +339,9 @@ static int i2s_s3c_irq_nextbyte(struct s
79799                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
79800
79801                         i2c->msg_ptr = 0;
79802 -                       i2c->msg_idx ++;
79803 +                       i2c->msg_idx++;
79804                         i2c->msg++;
79805 -
79806 +
79807                         /* check to see if we need to do another message */
79808                         if (i2c->msg->flags & I2C_M_NOSTART) {
79809
79810 @@ -375,7 +355,6 @@ static int i2s_s3c_irq_nextbyte(struct s
79811
79812                                 goto retry_write;
79813                         } else {
79814 -
79815                                 /* send the new start */
79816                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
79817                                 i2c->state = STATE_START;
79818 @@ -389,7 +368,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79819                 break;
79820
79821         case STATE_READ:
79822 -               /* we have a byte of data in the data register, do
79823 +               /* we have a byte of data in the data register, do
79824                  * something with it, and then work out wether we are
79825                  * going to do any more read/write
79826                  */
79827 @@ -397,13 +376,13 @@ static int i2s_s3c_irq_nextbyte(struct s
79828                 byte = readb(i2c->regs + S3C2410_IICDS);
79829                 i2c->msg->buf[i2c->msg_ptr++] = byte;
79830
79831 -       prepare_read:
79832 + prepare_read:
79833                 if (is_msglast(i2c)) {
79834                         /* last byte of buffer */
79835
79836                         if (is_lastmsg(i2c))
79837                                 s3c24xx_i2c_disable_ack(i2c);
79838 -
79839 +
79840                 } else if (is_msgend(i2c)) {
79841                         /* ok, we've read the entire buffer, see if there
79842                          * is anything else we need to do */
79843 @@ -429,7 +408,7 @@ static int i2s_s3c_irq_nextbyte(struct s
79844         /* acknowlegde the IRQ and get back on with the work */
79845
79846   out_ack:
79847 -       tmp = readl(i2c->regs + S3C2410_IICCON);
79848 +       tmp = readl(i2c->regs + S3C2410_IICCON);
79849         tmp &= ~S3C2410_IICCON_IRQPEND;
79850         writel(tmp, i2c->regs + S3C2410_IICCON);
79851   out:
79852 @@ -450,19 +429,19 @@ static irqreturn_t s3c24xx_i2c_irq(int i
79853         status = readl(i2c->regs + S3C2410_IICSTAT);
79854
79855         if (status & S3C2410_IICSTAT_ARBITR) {
79856 -               // deal with arbitration loss
79857 +               /* deal with arbitration loss */
79858                 dev_err(i2c->dev, "deal with arbitration loss\n");
79859         }
79860
79861         if (i2c->state == STATE_IDLE) {
79862                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
79863
79864 -               tmp = readl(i2c->regs + S3C2410_IICCON);
79865 +               tmp = readl(i2c->regs + S3C2410_IICCON);
79866                 tmp &= ~S3C2410_IICCON_IRQPEND;
79867                 writel(tmp, i2c->regs +  S3C2410_IICCON);
79868                 goto out;
79869         }
79870 -
79871 +
79872         /* pretty much this leaves us with the fact that we've
79873          * transmitted or received whatever byte we last sent */
79874
79875 @@ -485,16 +464,13 @@ static int s3c24xx_i2c_set_master(struct
79876
79877         while (timeout-- > 0) {
79878                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
79879 -
79880 +
79881                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
79882                         return 0;
79883
79884                 msleep(1);
79885         }
79886
79887 -       dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
79888 -               __raw_readl(S3C2410_GPEDAT));
79889 -
79890         return -ETIMEDOUT;
79891  }
79892
79893 @@ -503,7 +479,8 @@ static int s3c24xx_i2c_set_master(struct
79894   * this starts an i2c transfer
79895  */
79896
79897 -static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
79898 +static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
79899 +                             struct i2c_msg *msgs, int num)
79900  {
79901         unsigned long timeout;
79902         int ret;
79903 @@ -511,6 +488,15 @@ static int s3c24xx_i2c_doxfer(struct s3c
79904         if (i2c->suspended)
79905                 return -EIO;
79906
79907 +       if (i2c->suspended) {
79908 +               dev_err(i2c->dev,
79909 +                   "Hey I am still asleep (suspended: %d), retry later\n",
79910 +                   i2c->suspended);
79911 +               dump_stack();
79912 +               ret = -EAGAIN;
79913 +               goto out;
79914 +       }
79915 +
79916         ret = s3c24xx_i2c_set_master(i2c);
79917         if (ret != 0) {
79918                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
79919 @@ -529,12 +515,12 @@ static int s3c24xx_i2c_doxfer(struct s3c
79920         s3c24xx_i2c_enable_irq(i2c);
79921         s3c24xx_i2c_message_start(i2c, msgs);
79922         spin_unlock_irq(&i2c->lock);
79923 -
79924 +
79925         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
79926
79927         ret = i2c->msg_idx;
79928
79929 -       /* having these next two as dev_err() makes life very
79930 +       /* having these next two as dev_err() makes life very
79931          * noisy when doing an i2cdetect */
79932
79933         if (timeout == 0)
79934 @@ -591,19 +577,6 @@ static const struct i2c_algorithm s3c24x
79935         .functionality          = s3c24xx_i2c_func,
79936  };
79937
79938 -static struct s3c24xx_i2c s3c24xx_i2c = {
79939 -       .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
79940 -       .wait           = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
79941 -       .tx_setup       = 50,
79942 -       .adap           = {
79943 -               .name                   = "s3c2410-i2c",
79944 -               .owner                  = THIS_MODULE,
79945 -               .algo                   = &s3c24xx_i2c_algorithm,
79946 -               .retries                = 2,
79947 -               .class                  = I2C_CLASS_HWMON | I2C_CLASS_SPD,
79948 -       },
79949 -};
79950 -
79951  /* s3c24xx_i2c_calcdivisor
79952   *
79953   * return the divisor settings for a given frequency
79954 @@ -643,7 +616,7 @@ static inline int freq_acceptable(unsign
79955  {
79956         int diff = freq - wanted;
79957
79958 -       return (diff >= -2 && diff <= 2);
79959 +       return diff >= -2 && diff <= 2;
79960  }
79961
79962  /* s3c24xx_i2c_clockrate
79963 @@ -655,7 +628,7 @@ static inline int freq_acceptable(unsign
79964
79965  static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
79966  {
79967 -       struct s3c2410_platform_i2c *pdata;
79968 +       struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
79969         unsigned long clkin = clk_get_rate(i2c->clk);
79970         unsigned int divs, div1;
79971         u32 iiccon;
79972 @@ -663,10 +636,8 @@ static int s3c24xx_i2c_clockrate(struct
79973         int start, end;
79974
79975         i2c->clkrate = clkin;
79976 -
79977 -       pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
79978         clkin /= 1000;          /* clkin now in KHz */
79979 -
79980 +
79981         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
79982                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
79983
79984 @@ -774,7 +745,7 @@ static inline void s3c24xx_i2c_deregiste
79985
79986  /* s3c24xx_i2c_init
79987   *
79988 - * initialise the controller, set the IO lines and frequency
79989 + * initialise the controller, set the IO lines and frequency
79990  */
79991
79992  static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
79993 @@ -785,15 +756,15 @@ static int s3c24xx_i2c_init(struct s3c24
79994
79995         /* get the plafrom data */
79996
79997 -       pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
79998 +       pdata = i2c->dev->platform_data;
79999
80000         /* inititalise the gpio */
80001
80002 -       s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
80003 -       s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
80004 +       if (pdata->cfg_gpio)
80005 +               pdata->cfg_gpio(to_platform_device(i2c->dev));
80006
80007         /* write slave address */
80008 -
80009 +
80010         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
80011
80012         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
80013 @@ -831,12 +802,32 @@ static int s3c24xx_i2c_init(struct s3c24
80014
80015  static int s3c24xx_i2c_probe(struct platform_device *pdev)
80016  {
80017 -       struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
80018 +       struct s3c24xx_i2c *i2c;
80019         struct s3c2410_platform_i2c *pdata;
80020         struct resource *res;
80021         int ret;
80022
80023 -       pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
80024 +       pdata = pdev->dev.platform_data;
80025 +       if (!pdata) {
80026 +               dev_err(&pdev->dev, "no platform data\n");
80027 +               return -EINVAL;
80028 +       }
80029 +
80030 +       i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
80031 +       if (!i2c) {
80032 +               dev_err(&pdev->dev, "no memory for state\n");
80033 +               return -ENOMEM;
80034 +       }
80035 +
80036 +       strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
80037 +       i2c->adap.owner   = THIS_MODULE;
80038 +       i2c->adap.algo    = &s3c24xx_i2c_algorithm;
80039 +       i2c->adap.retries = 2;
80040 +       i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
80041 +       i2c->tx_setup     = 50;
80042 +
80043 +       spin_lock_init(&i2c->lock);
80044 +       init_waitqueue_head(&i2c->wait);
80045
80046         /* find the clock and enable it */
80047
80048 @@ -878,7 +869,8 @@ static int s3c24xx_i2c_probe(struct plat
80049                 goto err_ioarea;
80050         }
80051
80052 -       dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
80053 +       dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
80054 +               i2c->regs, i2c->ioarea, res);
80055
80056         /* setup info block for the i2c core */
80057
80058 @@ -892,29 +884,23 @@ static int s3c24xx_i2c_probe(struct plat
80059                 goto err_iomap;
80060
80061         /* find the IRQ for this unit (note, this relies on the init call to
80062 -        * ensure no current IRQs pending
80063 +        * ensure no current IRQs pending
80064          */
80065
80066 -       res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
80067 -       if (res == NULL) {
80068 +       i2c->irq = ret = platform_get_irq(pdev, 0);
80069 +       if (ret <= 0) {
80070                 dev_err(&pdev->dev, "cannot find IRQ\n");
80071 -               ret = -ENOENT;
80072                 goto err_iomap;
80073         }
80074
80075 -       ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
80076 -                         pdev->name, i2c);
80077 +       ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
80078 +                         dev_name(&pdev->dev), i2c);
80079
80080         if (ret != 0) {
80081 -               dev_err(&pdev->dev, "cannot claim IRQ\n");
80082 +               dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
80083                 goto err_iomap;
80084         }
80085
80086 -       i2c->irq = res;
80087 -
80088 -       dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
80089 -               (unsigned long)res->start);
80090 -
80091         ret = s3c24xx_i2c_register_cpufreq(i2c);
80092         if (ret < 0) {
80093                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
80094 @@ -944,7 +930,7 @@ static int s3c24xx_i2c_probe(struct plat
80095         s3c24xx_i2c_deregister_cpufreq(i2c);
80096
80097   err_irq:
80098 -       free_irq(i2c->irq->start, i2c);
80099 +       free_irq(i2c->irq, i2c);
80100
80101   err_iomap:
80102         iounmap(i2c->regs);
80103 @@ -958,6 +944,7 @@ static int s3c24xx_i2c_probe(struct plat
80104         clk_put(i2c->clk);
80105
80106   err_noclk:
80107 +       kfree(i2c);
80108         return ret;
80109  }
80110
80111 @@ -973,7 +960,7 @@ static int s3c24xx_i2c_remove(struct pla
80112         s3c24xx_i2c_deregister_cpufreq(i2c);
80113
80114         i2c_del_adapter(&i2c->adap);
80115 -       free_irq(i2c->irq->start, i2c);
80116 +       free_irq(i2c->irq, i2c);
80117
80118         clk_disable(i2c->clk);
80119         clk_put(i2c->clk);
80120 @@ -982,6 +969,7 @@ static int s3c24xx_i2c_remove(struct pla
80121
80122         release_resource(i2c->ioarea);
80123         kfree(i2c->ioarea);
80124 +       kfree(i2c);
80125
80126         return 0;
80127  }
80128 Index: linux-2.6.28/drivers/i2c/busses/Kconfig
80129 ===================================================================
80130 --- linux-2.6.28.orig/drivers/i2c/busses/Kconfig        2008-12-25 00:26:37.000000000 +0100
80131 +++ linux-2.6.28/drivers/i2c/busses/Kconfig     2009-01-02 00:01:56.000000000 +0100
80132 @@ -455,11 +455,12 @@ config I2C_PXA_SLAVE
80133           I2C bus.
80134
80135  config I2C_S3C2410
80136 -       tristate "S3C2410 I2C Driver"
80137 -       depends on ARCH_S3C2410
80138 +       tristate "Samsung SoC I2C Driver (S3C24XX and S3C64XX series)"
80139 +       depends on ARCH_S3C2410 || ARCH_S3C64XX
80140         help
80141           Say Y here to include support for I2C controller in the
80142 -         Samsung S3C2410 based System-on-Chip devices.
80143 +         Samsung S3C based System-on-Chip devices such as the S3C2410,
80144 +         S3C2440, S3C2442, S3C2443 and S3C6410.
80145
80146  config I2C_SH7760
80147         tristate "Renesas SH7760 I2C Controller"
80148 Index: linux-2.6.28/drivers/i2c/chips/Kconfig
80149 ===================================================================
80150 --- linux-2.6.28.orig/drivers/i2c/chips/Kconfig 2008-12-25 00:26:37.000000000 +0100
80151 +++ linux-2.6.28/drivers/i2c/chips/Kconfig      2009-01-02 00:01:56.000000000 +0100
80152 @@ -53,6 +53,26 @@ config SENSORS_EEPROM
80153           This driver can also be built as a module.  If so, the module
80154           will be called eeprom.
80155
80156 +config SENSORS_PCF50606
80157 +       tristate "Philips/NXP PCF50606"
80158 +       depends on I2C
80159 +       help
80160 +         If you say yes here you get support for Philips/NXP PCF50606
80161 +         PMU (Power Management Unit) chips.
80162 +
80163 +         This driver can also be built as a module.  If so, the module
80164 +         will be called pcf50606.
80165 +
80166 +config SENSORS_PCF50633
80167 +       tristate "Philips PCF50633"
80168 +       depends on I2C
80169 +       help
80170 +         If you say yes here you get support for Philips PCF50633
80171 +         PMU (Power Management Unit) chips.
80172 +
80173 +         This driver can also be built as a module.  If so, the module
80174 +         will be called pcf50633.
80175 +
80176  config SENSORS_PCF8574
80177         tristate "Philips PCF8574 and PCF8574A (DEPRECATED)"
80178         depends on EXPERIMENTAL && GPIO_PCF857X = "n"
80179 @@ -185,4 +205,23 @@ config MCU_MPC8349EMITX
80180           also register MCU GPIOs with the generic GPIO API, so you'll able
80181           to use MCU pins as GPIOs.
80182
80183 +config SENSORS_TSL256X
80184 +       tristate "Texas TSL256X Ambient Light Sensor"
80185 +       depends on I2C
80186 +       help
80187 +         If you say yes here you get support for the Texas TSL256X
80188 +         ambient light sensor chip.
80189 +
80190 +         This driver can also be built as a module.  If so, the module
80191 +         will be called tsl256x.
80192 +
80193 +config PCA9632
80194 +       tristate "Philips/NXP PCA9632 low power LED driver"
80195 +       depends on I2C
80196 +       help
80197 +         If you say yes here you get support for the Philips/NXP PCA9632
80198 +         LED driver.
80199 +
80200 +         This driver can also be built as a module.  If so, the module
80201 +         will be called pca9632.
80202  endmenu
80203 Index: linux-2.6.28/drivers/i2c/chips/Makefile
80204 ===================================================================
80205 --- linux-2.6.28.orig/drivers/i2c/chips/Makefile        2008-12-25 00:26:37.000000000 +0100
80206 +++ linux-2.6.28/drivers/i2c/chips/Makefile     2009-01-02 00:01:56.000000000 +0100
80207 @@ -15,6 +15,8 @@ obj-$(CONFIG_AT24)            += at24.o
80208  obj-$(CONFIG_SENSORS_EEPROM)   += eeprom.o
80209  obj-$(CONFIG_SENSORS_MAX6875)  += max6875.o
80210  obj-$(CONFIG_SENSORS_PCA9539)  += pca9539.o
80211 +obj-$(CONFIG_SENSORS_PCF50606) += pcf50606.o
80212 +obj-$(CONFIG_SENSORS_PCF50633) += pcf50633.o
80213  obj-$(CONFIG_SENSORS_PCF8574)  += pcf8574.o
80214  obj-$(CONFIG_PCF8575)          += pcf8575.o
80215  obj-$(CONFIG_SENSORS_PCF8591)  += pcf8591.o
80216 @@ -23,6 +25,8 @@ obj-$(CONFIG_TPS65010)                += tps65010.o
80217  obj-$(CONFIG_MENELAUS)         += menelaus.o
80218  obj-$(CONFIG_SENSORS_TSL2550)  += tsl2550.o
80219  obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o
80220 +obj-$(CONFIG_SENSORS_TSL256X)  += tsl256x.o
80221 +obj-$(CONFIG_PCA9632)          += pca9632.o
80222
80223  ifeq ($(CONFIG_I2C_DEBUG_CHIP),y)
80224  EXTRA_CFLAGS += -DDEBUG
80225 Index: linux-2.6.28/drivers/i2c/chips/pca9632.c
80226 ===================================================================
80227 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
80228 +++ linux-2.6.28/drivers/i2c/chips/pca9632.c    2009-01-02 00:01:56.000000000 +0100
80229 @@ -0,0 +1,551 @@
80230 +/*
80231 + *  Philips/NXP PCA9632 low power LED driver.
80232 + *  Copyright (C) 2008 Matt Hsu <matt_hsu@openmoko.org>
80233 + *
80234 + *  low_level implementation are based on pcf50606 driver
80235 + *
80236 + *  This program is free software; you can redistribute it and/or modify
80237 + *  it under the terms of the GNU General Public License as published by
80238 + *  the Free Software Foundation; version 2 of the License.
80239 + *
80240 + *  TODO:
80241 + *  - attach ledclass??
80242 + *  - add platform data
80243 + *
80244 + */
80245 +
80246 +#include <linux/module.h>
80247 +#include <linux/init.h>
80248 +#include <linux/i2c.h>
80249 +#include <linux/platform_device.h>
80250 +
80251 +#include "pca9632.h"
80252 +
80253 +/* Addresses to scan */
80254 +static unsigned short normal_i2c[] = { 0x62, I2C_CLIENT_END };
80255 +
80256 +/* Insmod parameters */
80257 +I2C_CLIENT_INSMOD_1(pca9632);
80258 +
80259 +enum pca9632_pwr_state {
80260 +       PCA9632_NORMAL,
80261 +       PCA9632_SLEEP,
80262 +};
80263 +
80264 +enum pca9632_led_output {
80265 +       PCA9632_OFF,
80266 +       PCA9632_ON,
80267 +       PCA9632_CTRL_BY_PWM,
80268 +       PCA9632_CTRL_BY_PWM_GRPPWM,
80269 +};
80270 +
80271 +static const char *led_output_name[] = {
80272 +       [PCA9632_OFF]                   = "off",
80273 +       [PCA9632_ON]                    = "fully-on",
80274 +       [PCA9632_CTRL_BY_PWM]           = "ctrl-by-pwm",
80275 +       [PCA9632_CTRL_BY_PWM_GRPPWM]    = "ctrl-by-pwm-grppwm",
80276 +};
80277 +
80278 +struct pca9632_data {
80279 +       struct i2c_client client;
80280 +       struct mutex lock;
80281 +};
80282 +
80283 +static struct i2c_driver pca9632_driver;
80284 +static struct platform_device *pca9632_pdev;
80285 +
80286 +static int pca9632_attach_adapter(struct i2c_adapter *adapter);
80287 +static int pca9632_detach_client(struct i2c_client *client);
80288 +
80289 +static int __reg_write(struct pca9632_data *pca, u_int8_t reg, u_int8_t val)
80290 +{
80291 +       return i2c_smbus_write_byte_data(&pca->client, reg, val);
80292 +}
80293 +
80294 +static int reg_write(struct pca9632_data *pca, u_int8_t reg, u_int8_t val)
80295 +{
80296 +       int ret;
80297 +
80298 +       mutex_lock(&pca->lock);
80299 +       ret = __reg_write(pca, reg, val);
80300 +       mutex_unlock(&pca->lock);
80301 +
80302 +       return ret;
80303 +}
80304 +
80305 +static int32_t __reg_read(struct pca9632_data *pca, u_int8_t reg)
80306 +{
80307 +       int32_t ret;
80308 +
80309 +       ret = i2c_smbus_read_byte_data(&pca->client, reg);
80310 +
80311 +       return ret;
80312 +}
80313 +
80314 +static u_int8_t reg_read(struct pca9632_data *pca, u_int8_t reg)
80315 +{
80316 +       int32_t ret;
80317 +
80318 +       mutex_lock(&pca->lock);
80319 +       ret = __reg_read(pca, reg);
80320 +       mutex_unlock(&pca->lock);
80321 +
80322 +       return ret & 0xff;
80323 +}
80324 +
80325 +static int reg_set_bit_mask(struct pca9632_data *pca,
80326 +                           u_int8_t reg, u_int8_t mask, u_int8_t val)
80327 +{
80328 +       int ret;
80329 +       u_int8_t tmp;
80330 +
80331 +       val &= mask;
80332 +
80333 +       mutex_lock(&pca->lock);
80334 +
80335 +       tmp = __reg_read(pca, reg);
80336 +       tmp &= ~mask;
80337 +       tmp |= val;
80338 +       ret = __reg_write(pca, reg, tmp);
80339 +
80340 +       mutex_unlock(&pca->lock);
80341 +
80342 +       return ret;
80343 +}
80344 +
80345 +static inline int calc_dc(uint8_t idc)
80346 +{
80347 +       return (idc * 100) / 256;
80348 +}
80349 +
80350 +/*
80351 + * Software reset
80352 + */
80353 +static int software_rst(struct i2c_adapter *adapter)
80354 +{
80355 +       u8 buf[] = { 0xa5, 0x5a };
80356 +
80357 +       struct i2c_msg msg[] = {
80358 +               {
80359 +                       .addr = 0x3,
80360 +                       .flags = 0,
80361 +                       .buf = &buf,
80362 +                       .len = sizeof(buf)
80363 +               }
80364 +       };
80365 +
80366 +       return i2c_transfer(adapter, msg, 1);
80367 +}
80368 +
80369 +/*
80370 + * Group dmblnk control
80371 + */
80372 +static void config_group_dmblnk(struct pca9632_data *pca, int group_dmblnk_mode)
80373 +{
80374 +       reg_set_bit_mask(pca, PCA9632_REG_MODE2, 0x20,
80375 +                       group_dmblnk_mode << PCA9632_DMBLNK_SHIFT);
80376 +}
80377 +
80378 +static int get_group_dmblnk(struct pca9632_data *pca)
80379 +{
80380 +       return reg_read(pca, PCA9632_REG_MODE2) >> PCA9632_DMBLNK_SHIFT;
80381 +}
80382 +
80383 +static ssize_t show_group_dmblnk(struct device *dev, struct device_attribute
80384 +                                       *attr, char *buf)
80385 +{
80386 +       struct i2c_client *client = to_i2c_client(dev);
80387 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80388 +
80389 +       if (get_group_dmblnk(pca))
80390 +               return sprintf(buf, "blinking\n");
80391 +       else
80392 +               return sprintf(buf, "dimming\n");
80393 +}
80394 +
80395 +static ssize_t set_group_dmblnk(struct device *dev, struct device_attribute
80396 +                                       *attr, const char *buf, size_t count)
80397 +{
80398 +       struct i2c_client *client = to_i2c_client(dev);
80399 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80400 +       unsigned int mode = simple_strtoul(buf, NULL, 10);
80401 +
80402 +       if (mode)
80403 +               dev_info(&pca->client.dev, "blinking\n");
80404 +       else
80405 +               dev_info(&pca->client.dev, "dimming\n");
80406 +
80407 +       config_group_dmblnk(pca, mode);
80408 +
80409 +       return count;
80410 +}
80411 +
80412 +static DEVICE_ATTR(group_dmblnk, S_IRUGO | S_IWUSR, show_group_dmblnk,
80413 +                                                       set_group_dmblnk);
80414 +
80415 +static int reg_id_by_name(const char *name)
80416 +{
80417 +       int reg_id = -1;
80418 +
80419 +       if (!strncmp(name, "led0", 4))
80420 +               reg_id = PCA9632_REG_PWM0;
80421 +       else if (!strncmp(name, "led1", 4))
80422 +               reg_id = PCA9632_REG_PWM1;
80423 +       else if (!strncmp(name, "led2", 4))
80424 +               reg_id = PCA9632_REG_PWM2;
80425 +       else if (!strncmp(name, "led3", 4))
80426 +               reg_id = PCA9632_REG_PWM3;
80427 +
80428 +       return reg_id;
80429 +}
80430 +
80431 +static int get_led_output(struct pca9632_data *pca, int ldrx)
80432 +{
80433 +       u_int8_t led_state;
80434 +
80435 +       ldrx = ldrx - 2;
80436 +       led_state = reg_read(pca, PCA9632_REG_LEDOUT);
80437 +       led_state = (led_state >> (2 * ldrx)) & 0x03;
80438 +
80439 +       return led_state;
80440 +}
80441 +
80442 +static void config_led_output(struct pca9632_data *pca, int ldrx,
80443 +                                       enum pca9632_led_output led_output)
80444 +{
80445 +       u_int8_t mask;
80446 +       int tmp;
80447 +
80448 +       ldrx = ldrx - 2;
80449 +       mask = 0x03 << (2 * ldrx);
80450 +       tmp = reg_set_bit_mask(pca, PCA9632_REG_LEDOUT,
80451 +                                       mask, led_output << (2 * ldrx));
80452 +}
80453 +
80454 +/*
80455 + * Individual brightness control
80456 + */
80457 +static ssize_t show_brightness(struct device *dev, struct device_attribute
80458 +                                       *attr, char *buf)
80459 +{
80460 +       struct i2c_client *client = to_i2c_client(dev);
80461 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80462 +       int ldrx;
80463 +
80464 +       ldrx = reg_id_by_name(attr->attr.name);
80465 +
80466 +       switch (get_led_output(pca, ldrx)) {
80467 +
80468 +       case PCA9632_OFF:
80469 +       case PCA9632_ON:
80470 +               return sprintf(buf, "%s",
80471 +                       led_output_name[get_led_output(pca, ldrx)]);
80472 +
80473 +       case PCA9632_CTRL_BY_PWM:
80474 +               return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca, ldrx)));
80475 +
80476 +       case PCA9632_CTRL_BY_PWM_GRPPWM:
80477 +               /* check group dmblnk */
80478 +               if (get_group_dmblnk(pca))
80479 +                       return sprintf(buf, "%d%% \n",
80480 +                               calc_dc(reg_read(pca, ldrx)));
80481 +               return sprintf(buf, "%d%% \n",
80482 +                                        calc_dc((reg_read(pca, ldrx) & 0xfc)));
80483 +       default:
80484 +               break;
80485 +       }
80486 +
80487 +       return sprintf(buf, "invalid argument\n");
80488 +}
80489 +
80490 +static ssize_t set_brightness(struct device *dev, struct device_attribute *attr,
80491 +                       const char *buf, size_t count)
80492 +{
80493 +       struct i2c_client *client = to_i2c_client(dev);
80494 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80495 +       unsigned int pwm = simple_strtoul(buf, NULL, 10);
80496 +       int ldrx;
80497 +
80498 +       ldrx = reg_id_by_name(attr->attr.name);
80499 +       reg_set_bit_mask(pca, ldrx, 0xff, pwm);
80500 +
80501 +       return count;
80502 +}
80503 +
80504 +static
80505 +DEVICE_ATTR(led0_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
80506 +static
80507 +DEVICE_ATTR(led1_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
80508 +static
80509 +DEVICE_ATTR(led2_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
80510 +static
80511 +DEVICE_ATTR(led3_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
80512 +
80513 +/*
80514 + * Group frequency control
80515 + */
80516 +static ssize_t show_group_freq(struct device *dev, struct device_attribute
80517 +                               *attr, char *buf)
80518 +{
80519 +       uint32_t period;
80520 +       struct i2c_client *client = to_i2c_client(dev);
80521 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80522 +
80523 +       period = ((reg_read(pca, PCA9632_REG_GRPFREQ) + 1) * 1000) / 24;
80524 +
80525 +       return sprintf(buf, "%d ms\n", period);
80526 +}
80527 +
80528 +static ssize_t set_group_freq(struct device *dev, struct device_attribute *attr,
80529 +                       const char *buf, size_t count)
80530 +{
80531 +       struct i2c_client *client = to_i2c_client(dev);
80532 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80533 +
80534 +       unsigned int freq = simple_strtoul(buf, NULL, 10);
80535 +       reg_write(pca, PCA9632_REG_GRPFREQ, freq);
80536 +       return count;
80537 +}
80538 +
80539 +static
80540 +DEVICE_ATTR(group_freq, S_IRUGO | S_IWUSR, show_group_freq, set_group_freq);
80541 +
80542 +/*
80543 + * Group duty cycle tonrol*
80544 + */
80545 +static ssize_t show_group_dc(struct device *dev, struct device_attribute *attr,
80546 +                            char *buf)
80547 +{
80548 +       struct i2c_client *client = to_i2c_client(dev);
80549 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80550 +
80551 +       if (get_group_dmblnk(pca)) {
80552 +
80553 +               if (reg_read(pca, PCA9632_REG_GRPFREQ) <= 0x03)
80554 +                       return sprintf(buf, "%d%% \n",
80555 +                            calc_dc(reg_read(pca, PCA9632_REG_GRPPWM) & 0xfc));
80556 +
80557 +               return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca,
80558 +                                                         PCA9632_REG_GRPPWM)));
80559 +       }
80560 +
80561 +       return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca,
80562 +                                                  PCA9632_REG_GRPPWM) & 0xf0));
80563 +}
80564 +
80565 +static ssize_t set_group_dc(struct device *dev, struct device_attribute *attr,
80566 +                       const char *buf, size_t count)
80567 +{
80568 +       struct i2c_client *client = to_i2c_client(dev);
80569 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80570 +
80571 +       unsigned int dc = simple_strtoul(buf, NULL, 10);
80572 +
80573 +       reg_set_bit_mask(pca, PCA9632_REG_GRPPWM, 0xff, dc);
80574 +
80575 +       return count;
80576 +}
80577 +
80578 +static DEVICE_ATTR(group_dc, S_IRUGO | S_IWUSR, show_group_dc, set_group_dc);
80579 +
80580 +/*
80581 + * LED driver output
80582 + */
80583 +static ssize_t show_led_output(struct device *dev, struct device_attribute
80584 +                                       *attr, char *buf)
80585 +{
80586 +       struct i2c_client *client = to_i2c_client(dev);
80587 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80588 +       int ldrx;
80589 +
80590 +       ldrx = reg_id_by_name(attr->attr.name);
80591 +
80592 +       return sprintf(buf, "%s \n",
80593 +                                   led_output_name[get_led_output(pca, ldrx)]);
80594 +
80595 +}
80596 +static ssize_t set_led_output(struct device *dev, struct device_attribute *attr,
80597 +                       const char *buf, size_t count)
80598 +{
80599 +       struct i2c_client *client = to_i2c_client(dev);
80600 +       struct pca9632_data *pca = i2c_get_clientdata(client);
80601 +       enum pca9632_led_output led_output;
80602 +       int ldrx;
80603 +
80604 +       led_output = simple_strtoul(buf, NULL, 10);
80605 +       ldrx = reg_id_by_name(attr->attr.name);
80606 +       config_led_output(pca, ldrx, led_output);
80607 +
80608 +       return count;
80609 +}
80610 +
80611 +static
80612 +DEVICE_ATTR(led0_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
80613 +static
80614 +DEVICE_ATTR(led1_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
80615 +static
80616 +DEVICE_ATTR(led2_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
80617 +static
80618 +DEVICE_ATTR(led3_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
80619 +
80620 +static struct attribute *pca_sysfs_entries[] = {
80621 +       &dev_attr_group_dmblnk.attr,
80622 +       &dev_attr_led0_pwm.attr,
80623 +       &dev_attr_led1_pwm.attr,
80624 +       &dev_attr_led2_pwm.attr,
80625 +       &dev_attr_led3_pwm.attr,
80626 +       &dev_attr_group_dc.attr,
80627 +       &dev_attr_group_freq.attr,
80628 +       &dev_attr_led0_output.attr,
80629 +       &dev_attr_led1_output.attr,
80630 +       &dev_attr_led2_output.attr,
80631 +       &dev_attr_led3_output.attr,
80632 +       NULL
80633 +};
80634 +
80635 +static struct attribute_group pca_attr_group = {
80636 +       .name   = NULL,                 /* put in device directory */
80637 +       .attrs  = pca_sysfs_entries,
80638 +};
80639 +
80640 +#ifdef CONFIG_PM
80641 +static int pca9632_suspend(struct device *dev, pm_message_t state)
80642 +{
80643 +       /* FIXME: Not implemented */
80644 +       return 0;
80645 +}
80646 +
80647 +static int pca9632_resume(struct device *dev)
80648 +{
80649 +       /* FIXME: Not implemented */
80650 +       return 0;
80651 +}
80652 +#else
80653 +#define pca9632_suspend NULL
80654 +#define pca9632_resume NULL
80655 +#endif
80656 +
80657 +static struct i2c_driver pca9632_driver = {
80658 +       .driver = {
80659 +               .name    = "pca9632",
80660 +               .suspend = pca9632_suspend,
80661 +               .resume  = pca9632_resume,
80662 +       },
80663 +       .id             = I2C_DRIVERID_PCA9632,
80664 +       .attach_adapter = pca9632_attach_adapter,
80665 +       .detach_client  = pca9632_detach_client,
80666 +};
80667 +
80668 +static int pca9632_detect(struct i2c_adapter *adapter, int address, int kind)
80669 +{
80670 +       struct i2c_client *new_client;
80671 +       struct pca9632_data *pca;
80672 +       int err;
80673 +
80674 +       pca = kzalloc(sizeof(struct pca9632_data), GFP_KERNEL);
80675 +       if (!pca)
80676 +               return -ENOMEM;
80677 +
80678 +       mutex_init(&pca->lock);
80679 +
80680 +       new_client = &pca->client;
80681 +       i2c_set_clientdata(new_client, pca);
80682 +       new_client->addr = address;
80683 +       new_client->adapter = adapter;
80684 +       new_client->driver = &pca9632_driver;
80685 +       new_client->flags = 0;
80686 +
80687 +       strlcpy(new_client->name, "pca9632", I2C_NAME_SIZE);
80688 +
80689 +       /* register with i2c core */
80690 +       err = i2c_attach_client(new_client);
80691 +       if (err)
80692 +               goto exit_kfree;
80693 +
80694 +       err = sysfs_create_group(&new_client->dev.kobj, &pca_attr_group);
80695 +       if (err)
80696 +               goto exit_detach;
80697 +
80698 +       /* software reset */
80699 +       if (!software_rst(adapter))
80700 +               dev_info(&pca->client.dev, "pca9632 sw-rst done\n");
80701 +
80702 +       /* enter normal mode */
80703 +       reg_set_bit_mask(pca, PCA9632_REG_MODE1, 0x10, PCA9632_NORMAL);
80704 +
80705 +       return 0;
80706 +
80707 +exit_detach:
80708 +       i2c_detach_client(new_client);
80709 +exit_kfree:
80710 +       kfree(pca);
80711 +
80712 +       return err;
80713 +}
80714 +
80715 +static int pca9632_attach_adapter(struct i2c_adapter *adapter)
80716 +{
80717 +       return i2c_probe(adapter, &addr_data, pca9632_detect);
80718 +}
80719 +
80720 +static int pca9632_detach_client(struct i2c_client *client)
80721 +{
80722 +       int err;
80723 +
80724 +       sysfs_remove_group(&client->dev.kobj, &pca_attr_group);
80725 +       err = i2c_detach_client(client);
80726 +
80727 +       if (err)
80728 +               return err;
80729 +
80730 +       kfree(i2c_get_clientdata(client));
80731 +
80732 +       return 0;
80733 +}
80734 +
80735 +static int __init pca9632_plat_probe(struct platform_device *pdev)
80736 +{
80737 +       /* FIXME: platform data should be attached here */
80738 +       pca9632_pdev = pdev;
80739 +
80740 +       return 0;
80741 +}
80742 +
80743 +static int pca9632_plat_remove(struct platform_device *pdev)
80744 +{
80745 +       return 0;
80746 +}
80747 +
80748 +static struct platform_driver pca9632_plat_driver = {
80749 +       .probe  = pca9632_plat_probe,
80750 +       .remove = pca9632_plat_remove,
80751 +       .driver = {
80752 +               .owner  = THIS_MODULE,
80753 +               .name   = "pca9632",
80754 +       },
80755 +};
80756 +
80757 +static int __init pca9632_init(void)
80758 +{
80759 +       int rc;
80760 +
80761 +       rc = platform_driver_register(&pca9632_plat_driver);
80762 +       if (!rc)
80763 +               i2c_add_driver(&pca9632_driver);
80764 +
80765 +       return rc;
80766 +}
80767 +
80768 +static void __exit pca9632_exit(void)
80769 +{
80770 +       i2c_del_driver(&pca9632_driver);
80771 +
80772 +       platform_driver_unregister(&pca9632_plat_driver);
80773 +}
80774 +
80775 +MODULE_AUTHOR("Matt Hsu <matt_hsu@openmoko.org>");
80776 +MODULE_DESCRIPTION("NXP PCA9632 driver");
80777 +MODULE_LICENSE("GPL");
80778 +
80779 +module_init(pca9632_init);
80780 +module_exit(pca9632_exit);
80781 Index: linux-2.6.28/drivers/i2c/chips/pca9632.h
80782 ===================================================================
80783 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
80784 +++ linux-2.6.28/drivers/i2c/chips/pca9632.h    2009-01-02 00:01:56.000000000 +0100
80785 @@ -0,0 +1,24 @@
80786 +#ifndef _PCA9632_H
80787 +#define _PCA9632_H
80788 +
80789 +
80790 +enum pca9632_regs{
80791 +
80792 +       PCA9632_REG_MODE1       = 0x00,
80793 +       PCA9632_REG_MODE2       = 0x01,
80794 +       PCA9632_REG_PWM0        = 0x02,
80795 +       PCA9632_REG_PWM1        = 0x03,
80796 +       PCA9632_REG_PWM2        = 0x04,
80797 +       PCA9632_REG_PWM3        = 0x05,
80798 +       PCA9632_REG_GRPPWM      = 0x06,
80799 +       PCA9632_REG_GRPFREQ     = 0x07,
80800 +       PCA9632_REG_LEDOUT      = 0x08,
80801 +       PCA9632_REG_SUBADDR1    = 0x09,
80802 +       PCA9632_REG_SUBADDR2    = 0x0a,
80803 +       PCA9632_REG_SUBADDR3    = 0x0b,
80804 +       PCA9632_REG_ALLCALLADR1 = 0x0c,
80805 +};
80806 +
80807 +#define PCA9632_DMBLNK_SHIFT   5
80808 +
80809 +#endif /* _PCA9632_H */
80810 Index: linux-2.6.28/drivers/i2c/chips/pcf50606.c
80811 ===================================================================
80812 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
80813 +++ linux-2.6.28/drivers/i2c/chips/pcf50606.c   2009-01-02 00:01:56.000000000 +0100
80814 @@ -0,0 +1,2193 @@
80815 +/* Philips/NXP PCF50606 Power Management Unit (PMU) driver
80816 + *
80817 + * (C) 2006-2007 by Openmoko, Inc.
80818 + * Authors: Harald Welte <laforge@openmoko.org>,
80819 + *         Matt Hsu <matt@openmoko.org>
80820 + * All rights reserved.
80821 + *
80822 + * This program is free software; you can redistribute it and/or
80823 + * modify it under the terms of the GNU General Public License as
80824 + * published by the Free Software Foundation; either version 2 of
80825 + * the License, or (at your option) any later version.
80826 + *
80827 + * This program is distributed in the hope that it will be useful,
80828 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
80829 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
80830 + * GNU General Public License for more details.
80831 + *
80832 + * You should have received a copy of the GNU General Public License
80833 + * along with this program; if not, write to the Free Software
80834 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
80835 + * MA 02111-1307 USA
80836 + *
80837 + * This driver is a monster ;) It provides the following features
80838 + * - voltage control for a dozen different voltage domains
80839 + * - charging control for main and backup battery
80840 + * - rtc / alarm
80841 + * - watchdog
80842 + * - adc driver (hw_sensors like)
80843 + * - pwm driver
80844 + * - backlight
80845 + *
80846 + */
80847 +
80848 +#include <linux/module.h>
80849 +#include <linux/init.h>
80850 +#include <linux/i2c.h>
80851 +#include <linux/types.h>
80852 +#include <linux/interrupt.h>
80853 +#include <linux/irq.h>
80854 +#include <linux/workqueue.h>
80855 +#include <linux/delay.h>
80856 +#include <linux/rtc.h>
80857 +#include <linux/bcd.h>
80858 +#include <linux/watchdog.h>
80859 +#include <linux/miscdevice.h>
80860 +#include <linux/input.h>
80861 +#include <linux/fb.h>
80862 +#include <linux/backlight.h>
80863 +#include <linux/sched.h>
80864 +#include <linux/platform_device.h>
80865 +#include <linux/pcf50606.h>
80866 +#include <linux/apm-emulation.h>
80867 +
80868 +#include <asm/mach-types.h>
80869 +#include <mach/gta01.h>
80870 +
80871 +#include "pcf50606.h"
80872 +
80873 +/* we use dev_dbg() throughout the code, but sometimes don't want to
80874 + * write an entire line of debug related information.  This DEBUGPC
80875 + * macro is a continuation for dev_dbg() */
80876 +#ifdef DEBUG
80877 +#define DEBUGPC(x, args ...) printk(x, ## args)
80878 +#else
80879 +#define DEBUGPC(x, args ...)
80880 +#endif
80881 +
80882 +/***********************************************************************
80883 + * Static data / structures
80884 + ***********************************************************************/
80885 +
80886 +static unsigned short normal_i2c[] = { 0x08, I2C_CLIENT_END };
80887 +
80888 +I2C_CLIENT_INSMOD_1(pcf50606);
80889 +
80890 +#define PCF50606_B_CHG_FAST    0       /* Charger Fast allowed */
80891 +#define PCF50606_B_CHG_PRESENT 1       /* Charger present */
80892 +#define PCF50606_B_CHG_FOK     2       /* Fast OK for battery */
80893 +#define PCF50606_B_CHG_ERR     3       /* Charger Error */
80894 +#define PCF50606_B_CHG_PROT    4       /* Charger Protection */
80895 +#define PCF50606_B_CHG_READY   5       /* Charging completed */
80896 +
80897 +#define PCF50606_F_CHG_FAST    (1<<PCF50606_B_CHG_FAST)
80898 +#define PCF50606_F_CHG_PRESENT (1<<PCF50606_B_CHG_PRESENT)
80899 +#define PCF50606_F_CHG_FOK     (1<<PCF50606_B_CHG_FOK)
80900 +#define PCF50606_F_CHG_ERR     (1<<PCF50606_B_CHG_ERR)
80901 +#define PCF50606_F_CHG_PROT    (1<<PCF50606_B_CHG_PROT)
80902 +#define PCF50606_F_CHG_READY   (1<<PCF50606_B_CHG_READY)
80903 +#define PCF50606_F_CHG_MASK    0x000000fc
80904 +
80905 +#define PCF50606_F_PWR_PRESSED 0x00000100
80906 +#define PCF50606_F_RTC_SECOND  0x00000200
80907 +
80908 +enum close_state {
80909 +       CLOSE_STATE_NOT,
80910 +       CLOSE_STATE_ALLOW = 0x2342,
80911 +};
80912 +
80913 +enum pcf50606_suspend_states {
80914 +       PCF50606_SS_RUNNING,
80915 +       PCF50606_SS_STARTING_SUSPEND,
80916 +       PCF50606_SS_COMPLETED_SUSPEND,
80917 +       PCF50606_SS_RESUMING_BUT_NOT_US_YET,
80918 +       PCF50606_SS_STARTING_RESUME,
80919 +       PCF50606_SS_COMPLETED_RESUME,
80920 +};
80921 +
80922 +struct pcf50606_data {
80923 +       struct i2c_client client;
80924 +       struct pcf50606_platform_data *pdata;
80925 +       struct backlight_device *backlight;
80926 +       struct mutex lock;
80927 +       unsigned int flags;
80928 +       unsigned int working;
80929 +       struct mutex working_lock;
80930 +       struct work_struct work;
80931 +       struct rtc_device *rtc;
80932 +       struct input_dev *input_dev;
80933 +       int allow_close;
80934 +       int onkey_seconds;
80935 +       int irq;
80936 +       int coldplug_done;
80937 +       int suppress_onkey_events;
80938 +       enum pcf50606_suspend_states suspend_state;
80939 +#ifdef CONFIG_PM
80940 +       struct {
80941 +               u_int8_t dcdc1, dcdc2;
80942 +               u_int8_t dcdec1;
80943 +               u_int8_t dcudc1;
80944 +               u_int8_t ioregc;
80945 +               u_int8_t d1regc1;
80946 +               u_int8_t d2regc1;
80947 +               u_int8_t d3regc1;
80948 +               u_int8_t lpregc1;
80949 +               u_int8_t adcc1, adcc2;
80950 +               u_int8_t pwmc1;
80951 +               u_int8_t int1m, int2m, int3m;
80952 +       } standby_regs;
80953 +#endif
80954 +};
80955 +
80956 +static struct i2c_driver pcf50606_driver;
80957 +
80958 +/* This is an ugly construct on how to access the (currently single/global)
80959 + * pcf50606 handle from other code in the kernel.  I didn't really come up with
80960 + * a more decent method of dynamically resolving this */
80961 +struct pcf50606_data *pcf50606_global;
80962 +EXPORT_SYMBOL_GPL(pcf50606_global);
80963 +
80964 +static struct platform_device *pcf50606_pdev;
80965 +
80966 +/* This is a 10k, B=3370 NTC Thermistor -10..79 centigrade */
80967 +/* Table entries are offset by +0.5C so a properly rounded value is generated */
80968 +static const u_int16_t ntc_table_10k_3370B[] = {
80969 +       /* -10 */
80970 +       43888, 41819, 39862, 38010, 36257, 34596, 33024, 31534, 30121, 28781,
80971 +       27510, 26304, 25159, 24071, 23038, 22056, 21122, 20234, 19390, 18586,
80972 +       17821, 17093, 16399, 15738, 15107, 14506, 13933, 13387, 12865, 12367,
80973 +       11891, 11437, 11003, 10588, 10192, 9813, 9450, 9103, 8771, 8453,
80974 +       8149, 7857, 7578, 7310, 7054, 6808, 6572, 6346, 6129, 5920,
80975 +       5720, 5528, 5344, 5167, 4996, 4833, 4675, 4524, 4379, 4239,
80976 +       4104, 3975, 3850, 3730, 3614, 3503, 3396, 3292, 3193, 3097,
80977 +       3004, 2915, 2829, 2745, 2665, 2588, 2513, 2441, 2371, 2304,
80978 +       2239, 2176, 2116, 2057, 2000, 1945, 1892, 1841, 1791, 1743,
80979 +};
80980 +
80981 +
80982 +/***********************************************************************
80983 + * Low-Level routines
80984 + ***********************************************************************/
80985 +
80986 +static inline int __reg_write(struct pcf50606_data *pcf, u_int8_t reg,
80987 +                             u_int8_t val)
80988 +{
80989 +       if (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND) {
80990 +               dev_err(&pcf->client.dev, "__reg_write while suspended.\n");
80991 +               dump_stack();
80992 +       }
80993 +       return i2c_smbus_write_byte_data(&pcf->client, reg, val);
80994 +}
80995 +
80996 +static int reg_write(struct pcf50606_data *pcf, u_int8_t reg, u_int8_t val)
80997 +{
80998 +       int ret;
80999 +
81000 +       mutex_lock(&pcf->lock);
81001 +       ret = __reg_write(pcf, reg, val);
81002 +       mutex_unlock(&pcf->lock);
81003 +
81004 +       return ret;
81005 +}
81006 +
81007 +static inline int32_t __reg_read(struct pcf50606_data *pcf, u_int8_t reg)
81008 +{
81009 +       int32_t ret;
81010 +
81011 +       if (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND) {
81012 +               dev_err(&pcf->client.dev, "__reg_read while suspended.\n");
81013 +               dump_stack();
81014 +       }
81015 +       ret = i2c_smbus_read_byte_data(&pcf->client, reg);
81016 +
81017 +       return ret;
81018 +}
81019 +
81020 +static u_int8_t reg_read(struct pcf50606_data *pcf, u_int8_t reg)
81021 +{
81022 +       int32_t ret;
81023 +
81024 +       mutex_lock(&pcf->lock);
81025 +       ret = __reg_read(pcf, reg);
81026 +       mutex_unlock(&pcf->lock);
81027 +
81028 +       return ret & 0xff;
81029 +}
81030 +
81031 +static int reg_set_bit_mask(struct pcf50606_data *pcf,
81032 +                           u_int8_t reg, u_int8_t mask, u_int8_t val)
81033 +{
81034 +       int ret;
81035 +       u_int8_t tmp;
81036 +
81037 +       val &= mask;
81038 +
81039 +       mutex_lock(&pcf->lock);
81040 +
81041 +       tmp = __reg_read(pcf, reg);
81042 +       tmp &= ~mask;
81043 +       tmp |= val;
81044 +       ret = __reg_write(pcf, reg, tmp);
81045 +
81046 +       mutex_unlock(&pcf->lock);
81047 +
81048 +       return ret;
81049 +}
81050 +
81051 +static int reg_clear_bits(struct pcf50606_data *pcf, u_int8_t reg, u_int8_t val)
81052 +{
81053 +       int ret;
81054 +       u_int8_t tmp;
81055 +
81056 +       mutex_lock(&pcf->lock);
81057 +
81058 +       tmp = __reg_read(pcf, reg);
81059 +       tmp &= ~val;
81060 +       ret = __reg_write(pcf, reg, tmp);
81061 +
81062 +       mutex_unlock(&pcf->lock);
81063 +
81064 +       return ret;
81065 +}
81066 +
81067 +/* synchronously read one ADC channel (busy-wait for result to be complete) */
81068 +static u_int16_t adc_read(struct pcf50606_data *pcf,  int channel,
81069 +                         u_int16_t *data2)
81070 +{
81071 +       u_int8_t adcs2, adcs1;
81072 +       u_int16_t ret;
81073 +
81074 +       dev_dbg(&pcf->client.dev, "entering (pcf=%p, channel=%u, data2=%p)\n",
81075 +               pcf, channel, data2);
81076 +
81077 +       channel &= PCF50606_ADCC2_ADCMUX_MASK;
81078 +
81079 +       mutex_lock(&pcf->lock);
81080 +
81081 +       /* start ADC conversion of selected channel */
81082 +       __reg_write(pcf, PCF50606_REG_ADCC2, channel |
81083 +                   PCF50606_ADCC2_ADCSTART | PCF50606_ADCC2_RES_10BIT);
81084 +
81085 +       do {
81086 +               adcs2 = __reg_read(pcf, PCF50606_REG_ADCS2);
81087 +       } while (!(adcs2 & PCF50606_ADCS2_ADCRDY));
81088 +
81089 +       adcs1 = __reg_read(pcf, PCF50606_REG_ADCS1);
81090 +       ret = (adcs1 << 2) | (adcs2 & 0x03);
81091 +
81092 +       if (data2) {
81093 +               adcs1 = __reg_read(pcf, PCF50606_REG_ADCS3);
81094 +               *data2 = (adcs1 << 2) | ((adcs2 & 0x0c) >> 2);
81095 +       }
81096 +
81097 +       mutex_unlock(&pcf->lock);
81098 +
81099 +       dev_dbg(&pcf->client.dev, "returning %u %u\n", ret,
81100 +               data2 ? *data2 : 0);
81101 +
81102 +       return ret;
81103 +}
81104 +
81105 +/***********************************************************************
81106 + * Voltage / ADC
81107 + ***********************************************************************/
81108 +
81109 +static u_int8_t dcudc_voltage(unsigned int millivolts)
81110 +{
81111 +       if (millivolts < 900)
81112 +               return 0;
81113 +       if (millivolts > 5500)
81114 +               return 0x1f;
81115 +       if (millivolts <= 3300) {
81116 +               millivolts -= 900;
81117 +               return millivolts/300;
81118 +       }
81119 +       if (millivolts < 4000)
81120 +               return 0x0f;
81121 +       else {
81122 +               millivolts -= 4000;
81123 +               return millivolts/100;
81124 +       }
81125 +}
81126 +
81127 +static unsigned int dcudc_2voltage(u_int8_t bits)
81128 +{
81129 +       bits &= 0x1f;
81130 +       if (bits < 0x08)
81131 +               return 900 + bits * 300;
81132 +       else if (bits < 0x10)
81133 +               return 3300;
81134 +       else
81135 +               return 4000 + bits * 100;
81136 +}
81137 +
81138 +static u_int8_t dcdec_voltage(unsigned int millivolts)
81139 +{
81140 +       if (millivolts < 900)
81141 +               return 0;
81142 +       else if (millivolts > 3300)
81143 +               return 0x0f;
81144 +
81145 +       millivolts -= 900;
81146 +       return millivolts/300;
81147 +}
81148 +
81149 +static unsigned int dcdec_2voltage(u_int8_t bits)
81150 +{
81151 +       bits &= 0x0f;
81152 +       return 900 + bits*300;
81153 +}
81154 +
81155 +static u_int8_t dcdc_voltage(unsigned int millivolts)
81156 +{
81157 +       if (millivolts < 900)
81158 +               return 0;
81159 +       else if (millivolts > 3600)
81160 +               return 0x1f;
81161 +
81162 +       if (millivolts < 1500) {
81163 +               millivolts -= 900;
81164 +               return millivolts/25;
81165 +       } else {
81166 +               millivolts -= 1500;
81167 +               return 0x18 + millivolts/300;
81168 +       }
81169 +}
81170 +
81171 +static unsigned int dcdc_2voltage(u_int8_t bits)
81172 +{
81173 +       bits &= 0x1f;
81174 +       if ((bits & 0x18) == 0x18)
81175 +               return 1500 + ((bits & 0x7) * 300);
81176 +       else
81177 +               return 900 + (bits * 25);
81178 +}
81179 +
81180 +static u_int8_t dx_voltage(unsigned int millivolts)
81181 +{
81182 +       if (millivolts < 900)
81183 +               return 0;
81184 +       else if (millivolts > 3300)
81185 +               return 0x18;
81186 +
81187 +       millivolts -= 900;
81188 +       return millivolts/100;
81189 +}
81190 +
81191 +static unsigned int dx_2voltage(u_int8_t bits)
81192 +{
81193 +       bits &= 0x1f;
81194 +       return 900 + (bits * 100);
81195 +}
81196 +
81197 +static const u_int8_t regulator_registers[__NUM_PCF50606_REGULATORS] = {
81198 +       [PCF50606_REGULATOR_DCD]        = PCF50606_REG_DCDC1,
81199 +       [PCF50606_REGULATOR_DCDE]       = PCF50606_REG_DCDEC1,
81200 +       [PCF50606_REGULATOR_DCUD]       = PCF50606_REG_DCUDC1,
81201 +       [PCF50606_REGULATOR_D1REG]      = PCF50606_REG_D1REGC1,
81202 +       [PCF50606_REGULATOR_D2REG]      = PCF50606_REG_D2REGC1,
81203 +       [PCF50606_REGULATOR_D3REG]      = PCF50606_REG_D3REGC1,
81204 +       [PCF50606_REGULATOR_LPREG]      = PCF50606_REG_LPREGC1,
81205 +       [PCF50606_REGULATOR_IOREG]      = PCF50606_REG_IOREGC,
81206 +};
81207 +
81208 +int pcf50606_onoff_set(struct pcf50606_data *pcf,
81209 +                      enum pcf50606_regulator_id reg, int on)
81210 +{
81211 +       u_int8_t addr;
81212 +
81213 +       if (reg >= __NUM_PCF50606_REGULATORS)
81214 +               return -EINVAL;
81215 +
81216 +       /* IOREG cannot be powered off since it powers the PMU I2C */
81217 +       if (reg == PCF50606_REGULATOR_IOREG)
81218 +               return -EIO;
81219 +
81220 +       addr = regulator_registers[reg];
81221 +
81222 +       if (on == 0)
81223 +               reg_set_bit_mask(pcf, addr, 0xe0, 0x00);
81224 +       else
81225 +               reg_set_bit_mask(pcf, addr, 0xe0, 0xe0);
81226 +
81227 +       return 0;
81228 +}
81229 +EXPORT_SYMBOL_GPL(pcf50606_onoff_set);
81230 +
81231 +int pcf50606_onoff_get(struct pcf50606_data *pcf,
81232 +                      enum pcf50606_regulator_id reg)
81233 +{
81234 +       u_int8_t val, addr;
81235 +
81236 +       if (reg >= __NUM_PCF50606_REGULATORS)
81237 +               return -EINVAL;
81238 +
81239 +       addr = regulator_registers[reg];
81240 +       val = (reg_read(pcf, addr) & 0xe0) >> 5;
81241 +
81242 +       /* PWREN1 = 1, PWREN2 = 1, see table 16 of datasheet */
81243 +       switch (val) {
81244 +       case 0:
81245 +       case 5:
81246 +               return 0;
81247 +       default:
81248 +               return 1;
81249 +       }
81250 +}
81251 +EXPORT_SYMBOL_GPL(pcf50606_onoff_get);
81252 +
81253 +int pcf50606_voltage_set(struct pcf50606_data *pcf,
81254 +                        enum pcf50606_regulator_id reg,
81255 +                        unsigned int millivolts)
81256 +{
81257 +       u_int8_t volt_bits;
81258 +       u_int8_t regnr;
81259 +       int rc;
81260 +
81261 +       dev_dbg(&pcf->client.dev, "pcf=%p, reg=%d, mvolts=%d\n", pcf, reg,
81262 +               millivolts);
81263 +
81264 +       if (reg >= __NUM_PCF50606_REGULATORS)
81265 +               return -EINVAL;
81266 +
81267 +       if (millivolts > pcf->pdata->rails[reg].voltage.max)
81268 +               return -EINVAL;
81269 +
81270 +       switch (reg) {
81271 +       case PCF50606_REGULATOR_DCD:
81272 +               volt_bits = dcdc_voltage(millivolts);
81273 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_DCDC1, 0x1f,
81274 +                                     volt_bits);
81275 +               break;
81276 +       case PCF50606_REGULATOR_DCDE:
81277 +               volt_bits = dcdec_voltage(millivolts);
81278 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_DCDEC1, 0x0f,
81279 +                                     volt_bits);
81280 +               break;
81281 +       case PCF50606_REGULATOR_DCUD:
81282 +               volt_bits = dcudc_voltage(millivolts);
81283 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_DCUDC1, 0x1f,
81284 +                                     volt_bits);
81285 +               break;
81286 +       case PCF50606_REGULATOR_D1REG:
81287 +       case PCF50606_REGULATOR_D2REG:
81288 +       case PCF50606_REGULATOR_D3REG:
81289 +               regnr = PCF50606_REG_D1REGC1 + (reg - PCF50606_REGULATOR_D1REG);
81290 +               volt_bits = dx_voltage(millivolts);
81291 +               rc = reg_set_bit_mask(pcf, regnr, 0x1f, volt_bits);
81292 +               break;
81293 +       case PCF50606_REGULATOR_LPREG:
81294 +               volt_bits = dx_voltage(millivolts);
81295 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_LPREGC1, 0x1f,
81296 +                                     volt_bits);
81297 +               break;
81298 +       case PCF50606_REGULATOR_IOREG:
81299 +               if (millivolts < 1800)
81300 +                       return -EINVAL;
81301 +               volt_bits = dx_voltage(millivolts);
81302 +               rc = reg_set_bit_mask(pcf, PCF50606_REG_IOREGC, 0x1f,
81303 +                                     volt_bits);
81304 +               break;
81305 +       default:
81306 +               return -EINVAL;
81307 +       }
81308 +
81309 +       return rc;
81310 +}
81311 +EXPORT_SYMBOL_GPL(pcf50606_voltage_set);
81312 +
81313 +unsigned int pcf50606_voltage_get(struct pcf50606_data *pcf,
81314 +                        enum pcf50606_regulator_id reg)
81315 +{
81316 +       u_int8_t volt_bits;
81317 +       u_int8_t regnr;
81318 +       unsigned int rc = 0;
81319 +
81320 +       if (reg >= __NUM_PCF50606_REGULATORS)
81321 +               return -EINVAL;
81322 +
81323 +       switch (reg) {
81324 +       case PCF50606_REGULATOR_DCD:
81325 +               volt_bits = reg_read(pcf, PCF50606_REG_DCDC1) & 0x1f;
81326 +               rc = dcdc_2voltage(volt_bits);
81327 +               break;
81328 +       case PCF50606_REGULATOR_DCDE:
81329 +               volt_bits = reg_read(pcf, PCF50606_REG_DCDEC1) & 0x0f;
81330 +               rc = dcdec_2voltage(volt_bits);
81331 +               break;
81332 +       case PCF50606_REGULATOR_DCUD:
81333 +               volt_bits = reg_read(pcf, PCF50606_REG_DCUDC1) & 0x1f;
81334 +               rc = dcudc_2voltage(volt_bits);
81335 +               break;
81336 +       case PCF50606_REGULATOR_D1REG:
81337 +       case PCF50606_REGULATOR_D2REG:
81338 +       case PCF50606_REGULATOR_D3REG:
81339 +               regnr = PCF50606_REG_D1REGC1 + (reg - PCF50606_REGULATOR_D1REG);
81340 +               volt_bits = reg_read(pcf, regnr) & 0x1f;
81341 +               if (volt_bits > 0x18)
81342 +                       volt_bits = 0x18;
81343 +               rc = dx_2voltage(volt_bits);
81344 +               break;
81345 +       case PCF50606_REGULATOR_LPREG:
81346 +               volt_bits = reg_read(pcf, PCF50606_REG_LPREGC1) & 0x1f;
81347 +               if (volt_bits > 0x18)
81348 +                       volt_bits = 0x18;
81349 +               rc = dx_2voltage(volt_bits);
81350 +               break;
81351 +       case PCF50606_REGULATOR_IOREG:
81352 +               volt_bits = reg_read(pcf, PCF50606_REG_IOREGC) & 0x1f;
81353 +               if (volt_bits > 0x18)
81354 +                       volt_bits = 0x18;
81355 +               rc = dx_2voltage(volt_bits);
81356 +               break;
81357 +       default:
81358 +               return -EINVAL;
81359 +       }
81360 +
81361 +       return rc;
81362 +}
81363 +EXPORT_SYMBOL_GPL(pcf50606_voltage_get);
81364 +
81365 +/* go into 'STANDBY' mode, i.e. power off the main CPU and peripherals */
81366 +void pcf50606_go_standby(void)
81367 +{
81368 +       reg_write(pcf50606_global, PCF50606_REG_OOCC1,
81369 +                 PCF50606_OOCC1_GOSTDBY);
81370 +}
81371 +EXPORT_SYMBOL_GPL(pcf50606_go_standby);
81372 +
81373 +void pcf50606_gpo0_set(struct pcf50606_data *pcf, int on)
81374 +{
81375 +       u_int8_t val;
81376 +
81377 +       if (on)
81378 +               val = 0x07;
81379 +       else
81380 +               val = 0x0f;
81381 +
81382 +       reg_set_bit_mask(pcf, PCF50606_REG_GPOC1, 0x0f, val);
81383 +}
81384 +EXPORT_SYMBOL_GPL(pcf50606_gpo0_set);
81385 +
81386 +int pcf50606_gpo0_get(struct pcf50606_data *pcf)
81387 +{
81388 +       u_int8_t reg = reg_read(pcf, PCF50606_REG_GPOC1) & 0x0f;
81389 +
81390 +       if (reg == 0x07 || reg == 0x08)
81391 +               return 1;
81392 +
81393 +       return 0;
81394 +}
81395 +EXPORT_SYMBOL_GPL(pcf50606_gpo0_get);
81396 +
81397 +static void pcf50606_work(struct work_struct *work)
81398 +{
81399 +       struct pcf50606_data *pcf =
81400 +                       container_of(work, struct pcf50606_data, work);
81401 +       u_int8_t pcfirq[3];
81402 +       int ret;
81403 +
81404 +       mutex_lock(&pcf->working_lock);
81405 +       pcf->working = 1;
81406 +
81407 +       /* sanity */
81408 +       if (!&pcf->client.dev)
81409 +               goto bail;
81410 +
81411 +       /*
81412 +        * if we are presently suspending, we are not in a position to deal
81413 +        * with pcf50606 interrupts at all.
81414 +        *
81415 +        * Because we didn't clear the int pending registers, there will be
81416 +        * no edge / interrupt waiting for us when we wake.  But it is OK
81417 +        * because at the end of our resume, we call this workqueue function
81418 +        * gratuitously, clearing the pending register and re-enabling
81419 +        * servicing this interrupt.
81420 +        */
81421 +
81422 +       if ((pcf->suspend_state == PCF50606_SS_STARTING_SUSPEND) ||
81423 +           (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND))
81424 +               goto bail;
81425 +
81426 +       /*
81427 +        * If we are inside suspend -> resume completion time we don't attempt
81428 +        * service until we have fully resumed.  Although we could talk to the
81429 +        * device as soon as I2C is up, the regs in the device which we might
81430 +        * choose to modify as part of the service action have not been
81431 +        * reloaded with their pre-suspend states yet.  Therefore we will
81432 +        * defer our service if we are called like that until our resume has
81433 +        * completed.
81434 +        *
81435 +        * This shouldn't happen any more because we disable servicing this
81436 +        * interrupt in suspend and don't re-enable it until resume is
81437 +        * completed.
81438 +        */
81439 +
81440 +       if (pcf->suspend_state &&
81441 +               (pcf->suspend_state != PCF50606_SS_COMPLETED_RESUME))
81442 +               goto reschedule;
81443 +
81444 +       /* this is the case early in resume! Sanity check! */
81445 +       if (i2c_get_clientdata(&pcf->client) == NULL)
81446 +               goto reschedule;
81447 +
81448 +       /*
81449 +        * p35 pcf50606 datasheet rev 2.2:
81450 +        * ''The system controller shall read all interrupt registers in
81451 +        *   one I2C read action''
81452 +        * because if you don't INT# gets stuck asserted forever after a
81453 +        * while
81454 +        */
81455 +       ret = i2c_smbus_read_i2c_block_data(&pcf->client, PCF50606_REG_INT1,
81456 +                                           sizeof(pcfirq), pcfirq);
81457 +       if (ret != sizeof(pcfirq)) {
81458 +               DEBUGPC("Oh crap PMU IRQ register read failed %d\n", ret);
81459 +               /*
81460 +                * it shouldn't fail, we no longer attempt to use
81461 +                * I2C while it can be suspended.  But we don't have
81462 +                * much option but to retry if if it ever did fail,
81463 +                * because if we don't service the interrupt to clear
81464 +                * it, we will never see another PMU interrupt edge.
81465 +                */
81466 +               goto reschedule;
81467 +       }
81468 +
81469 +       /* hey did we just resume? (because we don't get here unless we are
81470 +        * running normally or the first call after resumption)
81471 +        *
81472 +        * pcf50606 resume is really really over now then.
81473 +        */
81474 +       if (pcf->suspend_state != PCF50606_SS_RUNNING) {
81475 +               pcf->suspend_state = PCF50606_SS_RUNNING;
81476 +
81477 +               /* peek at the IRQ reason, if power button then set a flag
81478 +                * so that we do not signal the event to userspace
81479 +                */
81480 +               if (pcfirq[0] & (PCF50606_INT1_ONKEYF | PCF50606_INT1_ONKEYR)) {
81481 +                       pcf->suppress_onkey_events = 1;
81482 +                       dev_dbg(&pcf->client.dev,
81483 +                               "Wake by ONKEY, suppressing ONKEY events");
81484 +               } else {
81485 +                       pcf->suppress_onkey_events = 0;
81486 +               }
81487 +       }
81488 +
81489 +       if (!pcf->coldplug_done) {
81490 +               DEBUGPC("PMU Coldplug init\n");
81491 +
81492 +               /* we used SECOND to kick ourselves started -- turn it off */
81493 +               pcfirq[0] &= ~PCF50606_INT1_SECOND;
81494 +               reg_set_bit_mask(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND,
81495 +                                PCF50606_INT1_SECOND);
81496 +
81497 +               /* coldplug the USB if present */
81498 +               if (__reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON) {
81499 +                       /* Charger inserted */
81500 +                       DEBUGPC("COLD CHGINS ");
81501 +                       input_report_key(pcf->input_dev, KEY_BATTERY, 1);
81502 +                       apm_queue_event(APM_POWER_STATUS_CHANGE);
81503 +                       pcf->flags |= PCF50606_F_CHG_PRESENT;
81504 +                       if (pcf->pdata->cb)
81505 +                               pcf->pdata->cb(&pcf->client.dev,
81506 +                                               PCF50606_FEAT_MBC,
81507 +                                               PMU_EVT_INSERT);
81508 +               }
81509 +
81510 +               pcf->coldplug_done = 1;
81511 +       }
81512 +
81513 +
81514 +       dev_dbg(&pcf->client.dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x:",
81515 +               pcfirq[0], pcfirq[1], pcfirq[2]);
81516 +
81517 +       if (pcfirq[0] & PCF50606_INT1_ONKEYF) {
81518 +               /* ONKEY falling edge (start of button press) */
81519 +               pcf->flags |= PCF50606_F_PWR_PRESSED;
81520 +               if (!pcf->suppress_onkey_events) {
81521 +                       DEBUGPC("ONKEYF ");
81522 +                       input_report_key(pcf->input_dev, KEY_POWER, 1);
81523 +               } else {
81524 +                       DEBUGPC("ONKEYF(unreported) ");
81525 +               }
81526 +       }
81527 +       if (pcfirq[0] & PCF50606_INT1_ONKEY1S) {
81528 +               /* ONKEY pressed for more than 1 second */
81529 +               pcf->onkey_seconds = 0;
81530 +               DEBUGPC("ONKEY1S ");
81531 +               /* Tell PMU we are taking care of this */
81532 +               reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
81533 +                                PCF50606_OOCC1_TOTRST,
81534 +                                PCF50606_OOCC1_TOTRST);
81535 +               /* enable SECOND interrupt (hz tick) */
81536 +               reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND);
81537 +       }
81538 +       if (pcfirq[0] & PCF50606_INT1_ONKEYR) {
81539 +               /* ONKEY rising edge (end of button press) */
81540 +               pcf->flags &= ~PCF50606_F_PWR_PRESSED;
81541 +               pcf->onkey_seconds = -1;
81542 +               if (!pcf->suppress_onkey_events) {
81543 +                       DEBUGPC("ONKEYR ");
81544 +                       input_report_key(pcf->input_dev, KEY_POWER, 0);
81545 +               } else {
81546 +                       DEBUGPC("ONKEYR(suppressed) ");
81547 +                       /* don't suppress any more power button events */
81548 +                       pcf->suppress_onkey_events = 0;
81549 +               }
81550 +               /* disable SECOND interrupt in case RTC didn't
81551 +                * request it */
81552 +               if (!(pcf->flags & PCF50606_F_RTC_SECOND))
81553 +                       reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
81554 +                                        PCF50606_INT1_SECOND,
81555 +                                        PCF50606_INT1_SECOND);
81556 +       }
81557 +       if (pcfirq[0] & PCF50606_INT1_EXTONR) {
81558 +               DEBUGPC("EXTONR ");
81559 +               input_report_key(pcf->input_dev, KEY_POWER2, 1);
81560 +       }
81561 +       if (pcfirq[0] & PCF50606_INT1_EXTONF) {
81562 +               DEBUGPC("EXTONF ");
81563 +               input_report_key(pcf->input_dev, KEY_POWER2, 0);
81564 +       }
81565 +       if (pcfirq[0] & PCF50606_INT1_SECOND) {
81566 +               DEBUGPC("SECOND ");
81567 +               if (pcf->flags & PCF50606_F_RTC_SECOND)
81568 +                       rtc_update_irq(pcf->rtc, 1,
81569 +                                      RTC_PF | RTC_IRQF);
81570 +
81571 +               if (pcf->onkey_seconds >= 0 &&
81572 +                   pcf->flags & PCF50606_F_PWR_PRESSED) {
81573 +                       DEBUGPC("ONKEY_SECONDS(%u, OOCC1=0x%02x) ",
81574 +                               pcf->onkey_seconds,
81575 +                               reg_read(pcf, PCF50606_REG_OOCC1));
81576 +                       pcf->onkey_seconds++;
81577 +                       if (pcf->onkey_seconds >=
81578 +                           pcf->pdata->onkey_seconds_required) {
81579 +                               /* Ask init to do 'ctrlaltdel' */
81580 +                               /*
81581 +                                * currently Linux reacts badly to issuing a
81582 +                                * signal to PID #1 before init is started.
81583 +                                * What happens is that the next kernel thread
81584 +                                * to start, which is the JFFS2 Garbage
81585 +                                * collector in our case, gets the signal
81586 +                                * instead and proceeds to fail to fork --
81587 +                                * which is very bad.  Therefore we confirm
81588 +                                * PID #1 exists before issuing the signal
81589 +                                */
81590 +                               if (find_task_by_pid_ns(1, &init_pid_ns)) {
81591 +                                       kill_pid(task_pid(find_task_by_pid_ns(1,
81592 +                                                       &init_pid_ns)), SIGINT, 1);
81593 +                                       DEBUGPC("SIGINT(init) ");
81594 +                               }
81595 +                               /* FIXME: what to do if userspace doesn't
81596 +                                * shut down? Do we want to force it? */
81597 +                       }
81598 +               }
81599 +       }
81600 +       if (pcfirq[0] & PCF50606_INT1_ALARM) {
81601 +               DEBUGPC("ALARM ");
81602 +               if (pcf->pdata->used_features & PCF50606_FEAT_RTC)
81603 +                       rtc_update_irq(pcf->rtc, 1,
81604 +                                      RTC_AF | RTC_IRQF);
81605 +       }
81606 +
81607 +       if (pcfirq[1] & PCF50606_INT2_CHGINS) {
81608 +               /* Charger inserted */
81609 +               DEBUGPC("CHGINS ");
81610 +               input_report_key(pcf->input_dev, KEY_BATTERY, 1);
81611 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
81612 +               pcf->flags |= PCF50606_F_CHG_PRESENT;
81613 +               if (pcf->pdata->cb)
81614 +                       pcf->pdata->cb(&pcf->client.dev,
81615 +                                      PCF50606_FEAT_MBC, PMU_EVT_INSERT);
81616 +               /* FIXME: how to signal this to userspace */
81617 +       }
81618 +       if (pcfirq[1] & PCF50606_INT2_CHGRM) {
81619 +               /* Charger removed */
81620 +               DEBUGPC("CHGRM ");
81621 +               input_report_key(pcf->input_dev, KEY_BATTERY, 0);
81622 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
81623 +               pcf->flags &= ~(PCF50606_F_CHG_MASK|PCF50606_F_CHG_PRESENT);
81624 +               if (pcf->pdata->cb)
81625 +                       pcf->pdata->cb(&pcf->client.dev,
81626 +                                      PCF50606_FEAT_MBC, PMU_EVT_INSERT);
81627 +               /* FIXME: how signal this to userspace */
81628 +       }
81629 +       if (pcfirq[1] & PCF50606_INT2_CHGFOK) {
81630 +               /* Battery ready for fast charging */
81631 +               DEBUGPC("CHGFOK ");
81632 +               pcf->flags |= PCF50606_F_CHG_FOK;
81633 +               /* FIXME: how to signal this to userspace */
81634 +       }
81635 +       if (pcfirq[1] & PCF50606_INT2_CHGERR) {
81636 +               /* Error in charge mode */
81637 +               DEBUGPC("CHGERR ");
81638 +               pcf->flags |= PCF50606_F_CHG_ERR;
81639 +               pcf->flags &= ~(PCF50606_F_CHG_FOK|PCF50606_F_CHG_READY);
81640 +               /* FIXME: how to signal this to userspace */
81641 +       }
81642 +       if (pcfirq[1] & PCF50606_INT2_CHGFRDY) {
81643 +               /* Fast charge completed */
81644 +               DEBUGPC("CHGFRDY ");
81645 +               pcf->flags |= PCF50606_F_CHG_READY;
81646 +               pcf->flags &= ~PCF50606_F_CHG_FOK;
81647 +               /* FIXME: how to signal this to userspace */
81648 +       }
81649 +       if (pcfirq[1] & PCF50606_INT2_CHGPROT) {
81650 +               /* Charging protection interrupt */
81651 +               DEBUGPC("CHGPROT ");
81652 +               pcf->flags &= ~(PCF50606_F_CHG_FOK|PCF50606_F_CHG_READY);
81653 +               /* FIXME: signal this to userspace */
81654 +       }
81655 +       if (pcfirq[1] & PCF50606_INT2_CHGWD10S) {
81656 +               /* Charger watchdog will expire in 10 seconds */
81657 +               DEBUGPC("CHGWD10S ");
81658 +               reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
81659 +                                PCF50606_OOCC1_WDTRST,
81660 +                                PCF50606_OOCC1_WDTRST);
81661 +       }
81662 +       if (pcfirq[1] & PCF50606_INT2_CHGWDEXP) {
81663 +               /* Charger watchdog expires */
81664 +               DEBUGPC("CHGWDEXP ");
81665 +               /* FIXME: how to signal this to userspace */
81666 +       }
81667 +
81668 +       if (pcfirq[2] & PCF50606_INT3_ADCRDY) {
81669 +               /* ADC result ready */
81670 +               DEBUGPC("ADCRDY ");
81671 +       }
81672 +       if (pcfirq[2] & PCF50606_INT3_ACDINS) {
81673 +               /* Accessory insertion detected */
81674 +               DEBUGPC("ACDINS ");
81675 +               if (pcf->pdata->cb)
81676 +                       pcf->pdata->cb(&pcf->client.dev,
81677 +                                      PCF50606_FEAT_ACD, PMU_EVT_INSERT);
81678 +       }
81679 +       if (pcfirq[2] & PCF50606_INT3_ACDREM) {
81680 +               /* Accessory removal detected */
81681 +               DEBUGPC("ACDREM ");
81682 +               if (pcf->pdata->cb)
81683 +                       pcf->pdata->cb(&pcf->client.dev,
81684 +                                      PCF50606_FEAT_ACD, PMU_EVT_REMOVE);
81685 +       }
81686 +       /* FIXME: TSCPRES */
81687 +       if (pcfirq[2] & PCF50606_INT3_LOWBAT) {
81688 +               if (__reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON) {
81689 +                       /*
81690 +                        * hey no need to freak out, we have some kind of
81691 +                        * valid charger power
81692 +                        */
81693 +                       DEBUGPC("(NO)BAT ");
81694 +               } else {
81695 +                       /* Really low battery voltage, we have 8 seconds left */
81696 +                       DEBUGPC("LOWBAT ");
81697 +                       /*
81698 +                        * currently Linux reacts badly to issuing a signal to
81699 +                        * PID #1 before init is started.  What happens is that
81700 +                        * the next kernel thread to start, which is the JFFS2
81701 +                        * Garbage collector in our case, gets the signal
81702 +                        * instead and proceeds to fail to fork -- which is
81703 +                        * very bad.  Therefore we confirm PID #1 exists
81704 +                        * before issuing SPIGPWR
81705 +                        */
81706 +                       if (find_task_by_pid_ns(1, &init_pid_ns)) {
81707 +                               apm_queue_event(APM_LOW_BATTERY);
81708 +                               DEBUGPC("SIGPWR(init) ");
81709 +                               kill_pid(task_pid(find_task_by_pid_ns(1, &init_pid_ns)), SIGPWR, 1);
81710 +                       } else
81711 +                               /*
81712 +                                * well, our situation is like this:  we do not
81713 +                                * have any external power, we have a low
81714 +                                * battery and since PID #1 doesn't exist yet,
81715 +                                * we are early in the boot, likely before
81716 +                                * rootfs mount.  We should just call it a day
81717 +                                */
81718 +                               apm_queue_event(APM_CRITICAL_SUSPEND);
81719 +               }
81720 +               /* Tell PMU we are taking care of this */
81721 +               reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
81722 +                                PCF50606_OOCC1_TOTRST,
81723 +                                PCF50606_OOCC1_TOTRST);
81724 +       }
81725 +       if (pcfirq[2] & PCF50606_INT3_HIGHTMP) {
81726 +               /* High temperature */
81727 +               DEBUGPC("HIGHTMP ");
81728 +               apm_queue_event(APM_CRITICAL_SUSPEND);
81729 +       }
81730 +
81731 +       DEBUGPC("\n");
81732 +
81733 +bail:
81734 +       pcf->working = 0;
81735 +       input_sync(pcf->input_dev);
81736 +       put_device(&pcf->client.dev);
81737 +       mutex_unlock(&pcf->working_lock);
81738 +
81739 +       return;
81740 +
81741 +reschedule:
81742 +
81743 +       if ((pcf->suspend_state != PCF50606_SS_STARTING_SUSPEND) &&
81744 +           (pcf->suspend_state != PCF50606_SS_COMPLETED_SUSPEND)) {
81745 +               msleep(10);
81746 +               dev_info(&pcf->client.dev, "rescheduling interrupt service\n");
81747 +       }
81748 +       if (!schedule_work(&pcf->work))
81749 +               dev_err(&pcf->client.dev, "int service reschedule failed\n");
81750 +
81751 +       /* we don't put the device here, hold it for next time */
81752 +       mutex_unlock(&pcf->working_lock);
81753 +}
81754 +
81755 +static irqreturn_t pcf50606_irq(int irq, void *_pcf)
81756 +{
81757 +       struct pcf50606_data *pcf = _pcf;
81758 +
81759 +       dev_dbg(&pcf->client.dev, "entering(irq=%u, pcf=%p): scheduling work\n",
81760 +               irq, _pcf);
81761 +       get_device(&pcf->client.dev);
81762 +       if (!schedule_work(&pcf->work) && !pcf->working)
81763 +               dev_err(&pcf->client.dev, "pcf irq work already queued.\n");
81764 +
81765 +       return IRQ_HANDLED;
81766 +}
81767 +
81768 +static u_int16_t adc_to_batt_millivolts(u_int16_t adc)
81769 +{
81770 +       u_int16_t mvolts;
81771 +
81772 +       mvolts = (adc * 6000) / 1024;
81773 +
81774 +       return mvolts;
81775 +}
81776 +
81777 +#define BATTVOLT_SCALE_START 2800
81778 +#define BATTVOLT_SCALE_END 4200
81779 +#define BATTVOLT_SCALE_DIVIDER ((BATTVOLT_SCALE_END - BATTVOLT_SCALE_START)/100)
81780 +
81781 +static u_int8_t battvolt_scale(u_int16_t battvolt)
81782 +{
81783 +       /* FIXME: this linear scale is completely bogus */
81784 +       u_int16_t battvolt_relative = battvolt - BATTVOLT_SCALE_START;
81785 +       unsigned int percent = battvolt_relative / BATTVOLT_SCALE_DIVIDER;
81786 +
81787 +       return percent;
81788 +}
81789 +
81790 +u_int16_t pcf50606_battvolt(struct pcf50606_data *pcf)
81791 +{
81792 +       u_int16_t adc;
81793 +       adc = adc_read(pcf, PCF50606_ADCMUX_BATVOLT_RES, NULL);
81794 +
81795 +       return adc_to_batt_millivolts(adc);
81796 +}
81797 +EXPORT_SYMBOL_GPL(pcf50606_battvolt);
81798 +
81799 +static ssize_t show_battvolt(struct device *dev, struct device_attribute *attr,
81800 +                            char *buf)
81801 +{
81802 +       struct i2c_client *client = to_i2c_client(dev);
81803 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81804 +
81805 +       return sprintf(buf, "%u\n", pcf50606_battvolt(pcf));
81806 +}
81807 +static DEVICE_ATTR(battvolt, S_IRUGO | S_IWUSR, show_battvolt, NULL);
81808 +
81809 +static int reg_id_by_name(const char *name)
81810 +{
81811 +       int reg_id;
81812 +
81813 +       if (!strcmp(name, "voltage_dcd"))
81814 +               reg_id = PCF50606_REGULATOR_DCD;
81815 +       else if (!strcmp(name, "voltage_dcde"))
81816 +               reg_id = PCF50606_REGULATOR_DCDE;
81817 +       else if (!strcmp(name, "voltage_dcud"))
81818 +               reg_id = PCF50606_REGULATOR_DCUD;
81819 +       else if (!strcmp(name, "voltage_d1reg"))
81820 +               reg_id = PCF50606_REGULATOR_D1REG;
81821 +       else if (!strcmp(name, "voltage_d2reg"))
81822 +               reg_id = PCF50606_REGULATOR_D2REG;
81823 +       else if (!strcmp(name, "voltage_d3reg"))
81824 +               reg_id = PCF50606_REGULATOR_D3REG;
81825 +       else if (!strcmp(name, "voltage_lpreg"))
81826 +               reg_id = PCF50606_REGULATOR_LPREG;
81827 +       else if (!strcmp(name, "voltage_ioreg"))
81828 +               reg_id = PCF50606_REGULATOR_IOREG;
81829 +       else
81830 +               reg_id = -1;
81831 +
81832 +       return reg_id;
81833 +}
81834 +
81835 +static ssize_t show_vreg(struct device *dev, struct device_attribute *attr,
81836 +                        char *buf)
81837 +{
81838 +       struct i2c_client *client = to_i2c_client(dev);
81839 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81840 +       unsigned int reg_id;
81841 +
81842 +       reg_id = reg_id_by_name(attr->attr.name);
81843 +       if (reg_id < 0)
81844 +               return 0;
81845 +
81846 +       if (pcf50606_onoff_get(pcf, reg_id) > 0)
81847 +               return sprintf(buf, "%u\n", pcf50606_voltage_get(pcf, reg_id));
81848 +       else
81849 +               return strlcpy(buf, "0\n", PAGE_SIZE);
81850 +}
81851 +
81852 +static ssize_t set_vreg(struct device *dev, struct device_attribute *attr,
81853 +                       const char *buf, size_t count)
81854 +{
81855 +       struct i2c_client *client = to_i2c_client(dev);
81856 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81857 +       unsigned long mvolts = simple_strtoul(buf, NULL, 10);
81858 +       unsigned int reg_id;
81859 +
81860 +       reg_id = reg_id_by_name(attr->attr.name);
81861 +       if (reg_id < 0)
81862 +               return -EIO;
81863 +
81864 +       dev_dbg(dev, "attempting to set %s(%d) to %lu mvolts\n",
81865 +               attr->attr.name, reg_id, mvolts);
81866 +
81867 +       if (mvolts == 0) {
81868 +               pcf50606_onoff_set(pcf, reg_id, 0);
81869 +       } else {
81870 +               if (pcf50606_voltage_set(pcf, reg_id, mvolts) < 0) {
81871 +                       dev_warn(dev, "refusing to set %s(%d) to %lu mvolts "
81872 +                                "(max=%u)\n", attr->attr.name, reg_id, mvolts,
81873 +                                pcf->pdata->rails[reg_id].voltage.max);
81874 +                       return -EINVAL;
81875 +               }
81876 +               pcf50606_onoff_set(pcf, reg_id, 1);
81877 +       }
81878 +
81879 +       return count;
81880 +}
81881 +
81882 +static DEVICE_ATTR(voltage_dcd, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81883 +static DEVICE_ATTR(voltage_dcde, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81884 +static DEVICE_ATTR(voltage_dcud, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81885 +static DEVICE_ATTR(voltage_d1reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81886 +static DEVICE_ATTR(voltage_d2reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81887 +static DEVICE_ATTR(voltage_d3reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81888 +static DEVICE_ATTR(voltage_lpreg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81889 +static DEVICE_ATTR(voltage_ioreg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
81890 +
81891 +/***********************************************************************
81892 + * Charger Control
81893 + ***********************************************************************/
81894 +
81895 +/* Enable/disable fast charging (500mA in the GTA01) */
81896 +void pcf50606_charge_fast(struct pcf50606_data *pcf, int on)
81897 +{
81898 +       if (!(pcf->pdata->used_features & PCF50606_FEAT_MBC))
81899 +               return;
81900 +
81901 +       if (on) {
81902 +               /* We can allow PCF to automatically charge
81903 +                * using Ifast */
81904 +               pcf->flags |= PCF50606_F_CHG_FAST;
81905 +               reg_set_bit_mask(pcf, PCF50606_REG_MBCC1,
81906 +                                PCF50606_MBCC1_AUTOFST,
81907 +                                PCF50606_MBCC1_AUTOFST);
81908 +       } else {
81909 +               pcf->flags &= ~PCF50606_F_CHG_FAST;
81910 +               /* disable automatic fast-charge */
81911 +               reg_clear_bits(pcf, PCF50606_REG_MBCC1,
81912 +                               PCF50606_MBCC1_AUTOFST);
81913 +               /* switch to idle mode to abort existing charge
81914 +                * process */
81915 +               reg_set_bit_mask(pcf, PCF50606_REG_MBCC1,
81916 +                                PCF50606_MBCC1_CHGMOD_MASK,
81917 +                                PCF50606_MBCC1_CHGMOD_IDLE);
81918 +       }
81919 +}
81920 +EXPORT_SYMBOL_GPL(pcf50606_charge_fast);
81921 +
81922 +static inline u_int16_t adc_to_rntc(struct pcf50606_data *pcf, u_int16_t adc)
81923 +{
81924 +       u_int32_t r_ntc = (adc * (u_int32_t)pcf->pdata->r_fix_batt)
81925 +               / (1023 - adc);
81926 +
81927 +       return r_ntc;
81928 +}
81929 +
81930 +static inline int16_t rntc_to_temp(u_int16_t rntc)
81931 +{
81932 +       int i;
81933 +
81934 +       for (i = 0; i < ARRAY_SIZE(ntc_table_10k_3370B); i++) {
81935 +               if (rntc > ntc_table_10k_3370B[i])
81936 +                       return i - 10;  /* First element is -10 */
81937 +       }
81938 +       return -99;     /* Below our range */
81939 +}
81940 +
81941 +static ssize_t show_battemp(struct device *dev, struct device_attribute *attr,
81942 +                           char *buf)
81943 +{
81944 +       struct i2c_client *client = to_i2c_client(dev);
81945 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81946 +       u_int16_t adc;
81947 +
81948 +       adc = adc_read(pcf, PCF50606_ADCMUX_BATTEMP, NULL);
81949 +
81950 +       return sprintf(buf, "%d\n", rntc_to_temp(adc_to_rntc(pcf, adc)));
81951 +}
81952 +static DEVICE_ATTR(battemp, S_IRUGO | S_IWUSR, show_battemp, NULL);
81953 +
81954 +static inline int16_t adc_to_chg_milliamps(struct pcf50606_data *pcf,
81955 +                                            u_int16_t adc_adcin1,
81956 +                                            u_int16_t adc_batvolt)
81957 +{
81958 +       int32_t res = (adc_adcin1 - adc_batvolt) * 2400;
81959 +       return (res * 1000) / (pcf->pdata->r_sense_milli * 1024);
81960 +}
81961 +
81962 +static ssize_t show_chgcur(struct device *dev, struct device_attribute *attr,
81963 +                          char *buf)
81964 +{
81965 +       struct i2c_client *client = to_i2c_client(dev);
81966 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81967 +       u_int16_t adc_batvolt, adc_adcin1;
81968 +       int16_t ma;
81969 +
81970 +       adc_batvolt = adc_read(pcf, PCF50606_ADCMUX_BATVOLT_ADCIN1,
81971 +                              &adc_adcin1);
81972 +       ma = adc_to_chg_milliamps(pcf, adc_adcin1, adc_batvolt);
81973 +
81974 +       return sprintf(buf, "%d\n", ma);
81975 +}
81976 +static DEVICE_ATTR(chgcur, S_IRUGO | S_IWUSR, show_chgcur, NULL);
81977 +
81978 +static const char *chgmode_names[] = {
81979 +       [PCF50606_MBCC1_CHGMOD_QUAL]            = "qualification",
81980 +       [PCF50606_MBCC1_CHGMOD_PRE]             = "pre",
81981 +       [PCF50606_MBCC1_CHGMOD_TRICKLE]         = "trickle",
81982 +       [PCF50606_MBCC1_CHGMOD_FAST_CCCV]       = "fast_cccv",
81983 +       [PCF50606_MBCC1_CHGMOD_FAST_NOCC]       = "fast_nocc",
81984 +       [PCF50606_MBCC1_CHGMOD_FAST_NOCV]       = "fast_nocv",
81985 +       [PCF50606_MBCC1_CHGMOD_FAST_SW]         = "fast_switch",
81986 +       [PCF50606_MBCC1_CHGMOD_IDLE]            = "idle",
81987 +};
81988 +
81989 +static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
81990 +                           char *buf)
81991 +{
81992 +       struct i2c_client *client = to_i2c_client(dev);
81993 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
81994 +       u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
81995 +       u_int8_t chgmod = (mbcc1 & PCF50606_MBCC1_CHGMOD_MASK);
81996 +
81997 +       return sprintf(buf, "%s\n", chgmode_names[chgmod]);
81998 +}
81999 +
82000 +static ssize_t set_chgmode(struct device *dev, struct device_attribute *attr,
82001 +                          const char *buf, size_t count)
82002 +{
82003 +       struct i2c_client *client = to_i2c_client(dev);
82004 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82005 +       u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
82006 +
82007 +       mbcc1 &= ~PCF50606_MBCC1_CHGMOD_MASK;
82008 +
82009 +       if (!strcmp(buf, "qualification"))
82010 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_QUAL;
82011 +       else if (!strcmp(buf, "pre"))
82012 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_PRE;
82013 +       else if (!strcmp(buf, "trickle"))
82014 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_TRICKLE;
82015 +       else if (!strcmp(buf, "fast_cccv"))
82016 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_FAST_CCCV;
82017 +       /* We don't allow the other fast modes for security reasons */
82018 +       else if (!strcmp(buf, "idle"))
82019 +               mbcc1 |= PCF50606_MBCC1_CHGMOD_IDLE;
82020 +       else
82021 +               return -EINVAL;
82022 +
82023 +       reg_write(pcf, PCF50606_REG_MBCC1, mbcc1);
82024 +
82025 +       return count;
82026 +}
82027 +
82028 +static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, set_chgmode);
82029 +
82030 +static const char *chgstate_names[] = {
82031 +       [PCF50606_B_CHG_FAST]                   = "fast_enabled",
82032 +       [PCF50606_B_CHG_PRESENT]                = "present",
82033 +       [PCF50606_B_CHG_FOK]                    = "fast_ok",
82034 +       [PCF50606_B_CHG_ERR]                    = "error",
82035 +       [PCF50606_B_CHG_PROT]                   = "protection",
82036 +       [PCF50606_B_CHG_READY]                  = "ready",
82037 +};
82038 +
82039 +static ssize_t show_chgstate(struct device *dev, struct device_attribute *attr,
82040 +                           char *buf)
82041 +{
82042 +       struct i2c_client *client = to_i2c_client(dev);
82043 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82044 +       char *b = buf;
82045 +       int i;
82046 +
82047 +       for (i = 0; i < 32; i++)
82048 +               if (pcf->flags & (1 << i) && i < ARRAY_SIZE(chgstate_names))
82049 +                       b += sprintf(b, "%s ", chgstate_names[i]);
82050 +
82051 +       if (b > buf)
82052 +               b += sprintf(b, "\n");
82053 +
82054 +       return b - buf;
82055 +}
82056 +static DEVICE_ATTR(chgstate, S_IRUGO | S_IWUSR, show_chgstate, NULL);
82057 +
82058 +/***********************************************************************
82059 + * APM emulation
82060 + ***********************************************************************/
82061 +
82062 +static void pcf50606_get_power_status(struct apm_power_info *info)
82063 +{
82064 +       struct pcf50606_data *pcf = pcf50606_global;
82065 +       u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
82066 +       u_int8_t chgmod = mbcc1 & PCF50606_MBCC1_CHGMOD_MASK;
82067 +       u_int16_t battvolt = pcf50606_battvolt(pcf);
82068 +
82069 +       if (reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON)
82070 +               info->ac_line_status = APM_AC_ONLINE;
82071 +       else
82072 +               info->ac_line_status = APM_AC_OFFLINE;
82073 +
82074 +       switch (chgmod) {
82075 +       case PCF50606_MBCC1_CHGMOD_QUAL:
82076 +       case PCF50606_MBCC1_CHGMOD_PRE:
82077 +       case PCF50606_MBCC1_CHGMOD_IDLE:
82078 +               info->battery_life = battvolt_scale(battvolt);
82079 +               break;
82080 +       default:
82081 +               info->battery_status = APM_BATTERY_STATUS_CHARGING;
82082 +               info->battery_flag = APM_BATTERY_FLAG_CHARGING;
82083 +               break;
82084 +       }
82085 +}
82086 +
82087 +/***********************************************************************
82088 + * RTC
82089 + ***********************************************************************/
82090 +
82091 +struct pcf50606_time {
82092 +       u_int8_t sec;
82093 +       u_int8_t min;
82094 +       u_int8_t hour;
82095 +       u_int8_t wkday;
82096 +       u_int8_t day;
82097 +       u_int8_t month;
82098 +       u_int8_t year;
82099 +};
82100 +
82101 +static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50606_time *pcf)
82102 +{
82103 +       rtc->tm_sec = bcd2bin(pcf->sec);
82104 +       rtc->tm_min = bcd2bin(pcf->min);
82105 +       rtc->tm_hour = bcd2bin(pcf->hour);
82106 +       rtc->tm_wday = bcd2bin(pcf->wkday);
82107 +       rtc->tm_mday = bcd2bin(pcf->day);
82108 +       rtc->tm_mon = bcd2bin(pcf->month);
82109 +       rtc->tm_year = bcd2bin(pcf->year) + 100;
82110 +}
82111 +
82112 +static void rtc2pcf_time(struct pcf50606_time *pcf, struct rtc_time *rtc)
82113 +{
82114 +       pcf->sec = bin2bcd(rtc->tm_sec);
82115 +       pcf->min = bin2bcd(rtc->tm_min);
82116 +       pcf->hour = bin2bcd(rtc->tm_hour);
82117 +       pcf->wkday = bin2bcd(rtc->tm_wday);
82118 +       pcf->day = bin2bcd(rtc->tm_mday);
82119 +       pcf->month = bin2bcd(rtc->tm_mon);
82120 +       pcf->year = bin2bcd(rtc->tm_year - 100);
82121 +}
82122 +
82123 +static int pcf50606_rtc_ioctl(struct device *dev, unsigned int cmd,
82124 +                             unsigned long arg)
82125 +{
82126 +       struct i2c_client *client = to_i2c_client(dev);
82127 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82128 +
82129 +       switch (cmd) {
82130 +       case RTC_AIE_OFF:
82131 +               /* disable the alarm interrupt */
82132 +               reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
82133 +                                PCF50606_INT1_ALARM, PCF50606_INT1_ALARM);
82134 +               return 0;
82135 +       case RTC_AIE_ON:
82136 +               /* enable the alarm interrupt */
82137 +               reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_ALARM);
82138 +               return 0;
82139 +       case RTC_PIE_OFF:
82140 +               /* disable periodic interrupt (hz tick) */
82141 +               pcf->flags &= ~PCF50606_F_RTC_SECOND;
82142 +               reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
82143 +                                PCF50606_INT1_SECOND, PCF50606_INT1_SECOND);
82144 +               return 0;
82145 +       case RTC_PIE_ON:
82146 +               /* ensable periodic interrupt (hz tick) */
82147 +               pcf->flags |= PCF50606_F_RTC_SECOND;
82148 +               reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND);
82149 +               return 0;
82150 +       }
82151 +       return -ENOIOCTLCMD;
82152 +}
82153 +
82154 +static int pcf50606_rtc_read_time(struct device *dev, struct rtc_time *tm)
82155 +{
82156 +       struct i2c_client *client = to_i2c_client(dev);
82157 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82158 +       struct pcf50606_time pcf_tm;
82159 +
82160 +       mutex_lock(&pcf->lock);
82161 +       pcf_tm.sec = __reg_read(pcf, PCF50606_REG_RTCSC);
82162 +       pcf_tm.min = __reg_read(pcf, PCF50606_REG_RTCMN);
82163 +       pcf_tm.hour = __reg_read(pcf, PCF50606_REG_RTCHR);
82164 +       pcf_tm.wkday = __reg_read(pcf, PCF50606_REG_RTCWD);
82165 +       pcf_tm.day = __reg_read(pcf, PCF50606_REG_RTCDT);
82166 +       pcf_tm.month = __reg_read(pcf, PCF50606_REG_RTCMT);
82167 +       pcf_tm.year = __reg_read(pcf, PCF50606_REG_RTCYR);
82168 +       mutex_unlock(&pcf->lock);
82169 +
82170 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
82171 +               pcf_tm.day, pcf_tm.month, pcf_tm.year,
82172 +               pcf_tm.hour, pcf_tm.min, pcf_tm.sec);
82173 +
82174 +       pcf2rtc_time(tm, &pcf_tm);
82175 +
82176 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
82177 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
82178 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
82179 +
82180 +       return 0;
82181 +}
82182 +
82183 +static int pcf50606_rtc_set_time(struct device *dev, struct rtc_time *tm)
82184 +{
82185 +       struct i2c_client *client = to_i2c_client(dev);
82186 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82187 +       struct pcf50606_time pcf_tm;
82188 +       u_int8_t int1m;
82189 +
82190 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
82191 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
82192 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
82193 +       rtc2pcf_time(&pcf_tm, tm);
82194 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
82195 +               pcf_tm.day, pcf_tm.month, pcf_tm.year,
82196 +               pcf_tm.hour, pcf_tm.min, pcf_tm.sec);
82197 +
82198 +       mutex_lock(&pcf->lock);
82199 +
82200 +       /* disable SECOND interrupt */
82201 +       int1m = __reg_read(pcf, PCF50606_REG_INT1M);
82202 +       __reg_write(pcf, PCF50606_REG_INT1M, int1m | PCF50606_INT1_SECOND);
82203 +
82204 +       __reg_write(pcf, PCF50606_REG_RTCSC, pcf_tm.sec);
82205 +       __reg_write(pcf, PCF50606_REG_RTCMN, pcf_tm.min);
82206 +       __reg_write(pcf, PCF50606_REG_RTCHR, pcf_tm.hour);
82207 +       __reg_write(pcf, PCF50606_REG_RTCWD, pcf_tm.wkday);
82208 +       __reg_write(pcf, PCF50606_REG_RTCDT, pcf_tm.day);
82209 +       __reg_write(pcf, PCF50606_REG_RTCMT, pcf_tm.month);
82210 +       __reg_write(pcf, PCF50606_REG_RTCYR, pcf_tm.year);
82211 +
82212 +       /* restore INT1M, potentially re-enable SECOND interrupt */
82213 +       __reg_write(pcf, PCF50606_REG_INT1M, int1m);
82214 +
82215 +       mutex_unlock(&pcf->lock);
82216 +
82217 +       return 0;
82218 +}
82219 +
82220 +static int pcf50606_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
82221 +{
82222 +       struct i2c_client *client = to_i2c_client(dev);
82223 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82224 +       struct pcf50606_time pcf_tm;
82225 +
82226 +       mutex_lock(&pcf->lock);
82227 +       alrm->enabled =
82228 +               __reg_read(pcf, PCF50606_REG_INT1M) & PCF50606_INT1_ALARM
82229 +               ? 0 : 1;
82230 +       pcf_tm.sec = __reg_read(pcf, PCF50606_REG_RTCSCA);
82231 +       pcf_tm.min = __reg_read(pcf, PCF50606_REG_RTCMNA);
82232 +       pcf_tm.hour = __reg_read(pcf, PCF50606_REG_RTCHRA);
82233 +       pcf_tm.wkday = __reg_read(pcf, PCF50606_REG_RTCWDA);
82234 +       pcf_tm.day = __reg_read(pcf, PCF50606_REG_RTCDTA);
82235 +       pcf_tm.month = __reg_read(pcf, PCF50606_REG_RTCMTA);
82236 +       pcf_tm.year = __reg_read(pcf, PCF50606_REG_RTCYRA);
82237 +       mutex_unlock(&pcf->lock);
82238 +
82239 +       pcf2rtc_time(&alrm->time, &pcf_tm);
82240 +
82241 +       return 0;
82242 +}
82243 +
82244 +static int pcf50606_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
82245 +{
82246 +       struct i2c_client *client = to_i2c_client(dev);
82247 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82248 +       struct pcf50606_time pcf_tm;
82249 +       u_int8_t irqmask;
82250 +
82251 +       rtc2pcf_time(&pcf_tm, &alrm->time);
82252 +
82253 +       mutex_lock(&pcf->lock);
82254 +
82255 +       /* disable alarm interrupt */
82256 +       irqmask = __reg_read(pcf, PCF50606_REG_INT1M);
82257 +       irqmask |= PCF50606_INT1_ALARM;
82258 +       __reg_write(pcf, PCF50606_REG_INT1M, irqmask);
82259 +
82260 +       __reg_write(pcf, PCF50606_REG_RTCSCA, pcf_tm.sec);
82261 +       __reg_write(pcf, PCF50606_REG_RTCMNA, pcf_tm.min);
82262 +       __reg_write(pcf, PCF50606_REG_RTCHRA, pcf_tm.hour);
82263 +       __reg_write(pcf, PCF50606_REG_RTCWDA, pcf_tm.wkday);
82264 +       __reg_write(pcf, PCF50606_REG_RTCDTA, pcf_tm.day);
82265 +       __reg_write(pcf, PCF50606_REG_RTCMTA, pcf_tm.month);
82266 +       __reg_write(pcf, PCF50606_REG_RTCYRA, pcf_tm.year);
82267 +
82268 +       if (alrm->enabled) {
82269 +               /* (re-)enaable alarm interrupt */
82270 +               irqmask = __reg_read(pcf, PCF50606_REG_INT1M);
82271 +               irqmask &= ~PCF50606_INT1_ALARM;
82272 +               __reg_write(pcf, PCF50606_REG_INT1M, irqmask);
82273 +       }
82274 +
82275 +       mutex_unlock(&pcf->lock);
82276 +
82277 +       /* FIXME */
82278 +       return 0;
82279 +}
82280 +
82281 +static struct rtc_class_ops pcf50606_rtc_ops = {
82282 +       .ioctl          = pcf50606_rtc_ioctl,
82283 +       .read_time      = pcf50606_rtc_read_time,
82284 +       .set_time       = pcf50606_rtc_set_time,
82285 +       .read_alarm     = pcf50606_rtc_read_alarm,
82286 +       .set_alarm      = pcf50606_rtc_set_alarm,
82287 +};
82288 +
82289 +/***********************************************************************
82290 + * Watchdog
82291 + ***********************************************************************/
82292 +
82293 +static void pcf50606_wdt_start(struct pcf50606_data *pcf)
82294 +{
82295 +       reg_set_bit_mask(pcf, PCF50606_REG_OOCC1, PCF50606_OOCC1_WDTRST,
82296 +                        PCF50606_OOCC1_WDTRST);
82297 +}
82298 +
82299 +static void pcf50606_wdt_stop(struct pcf50606_data *pcf)
82300 +{
82301 +       reg_clear_bits(pcf, PCF50606_REG_OOCS, PCF50606_OOCS_WDTEXP);
82302 +}
82303 +
82304 +static void pcf50606_wdt_keepalive(struct pcf50606_data *pcf)
82305 +{
82306 +       pcf50606_wdt_start(pcf);
82307 +}
82308 +
82309 +static int pcf50606_wdt_open(struct inode *inode, struct file *file)
82310 +{
82311 +       struct pcf50606_data *pcf = pcf50606_global;
82312 +
82313 +       file->private_data = pcf;
82314 +
82315 +       /* start the timer */
82316 +       pcf50606_wdt_start(pcf);
82317 +
82318 +       return nonseekable_open(inode, file);
82319 +}
82320 +
82321 +static int pcf50606_wdt_release(struct inode *inode, struct file *file)
82322 +{
82323 +       struct pcf50606_data *pcf = file->private_data;
82324 +
82325 +       if (pcf->allow_close == CLOSE_STATE_ALLOW)
82326 +               pcf50606_wdt_stop(pcf);
82327 +       else {
82328 +               printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n");
82329 +               pcf50606_wdt_keepalive(pcf);
82330 +       }
82331 +
82332 +       pcf->allow_close = CLOSE_STATE_NOT;
82333 +
82334 +       return 0;
82335 +}
82336 +
82337 +static ssize_t pcf50606_wdt_write(struct file *file, const char __user *data,
82338 +                                 size_t len, loff_t *ppos)
82339 +{
82340 +       struct pcf50606_data *pcf = file->private_data;
82341 +       if (len) {
82342 +               size_t i;
82343 +
82344 +               for (i = 0; i != len; i++) {
82345 +                       char c;
82346 +                       if (get_user(c, data + i))
82347 +                               return -EFAULT;
82348 +                       if (c == 'V')
82349 +                               pcf->allow_close = CLOSE_STATE_ALLOW;
82350 +               }
82351 +               pcf50606_wdt_keepalive(pcf);
82352 +       }
82353 +
82354 +       return len;
82355 +}
82356 +
82357 +static struct watchdog_info pcf50606_wdt_ident = {
82358 +       .options        = WDIOF_MAGICCLOSE,
82359 +       .firmware_version = 0,
82360 +       .identity       = "PCF50606 Watchdog",
82361 +};
82362 +
82363 +static int pcf50606_wdt_ioctl(struct inode *inode, struct file *file,
82364 +                             unsigned int cmd, unsigned long arg)
82365 +{
82366 +       struct pcf50606_data *pcf = file->private_data;
82367 +       void __user *argp = (void __user *)arg;
82368 +       int __user *p = argp;
82369 +
82370 +       switch (cmd) {
82371 +       case WDIOC_GETSUPPORT:
82372 +               return copy_to_user(argp, &pcf50606_wdt_ident,
82373 +                                   sizeof(pcf50606_wdt_ident)) ? -EFAULT : 0;
82374 +               break;
82375 +       case WDIOC_GETSTATUS:
82376 +       case WDIOC_GETBOOTSTATUS:
82377 +               return put_user(0, p);
82378 +       case WDIOC_KEEPALIVE:
82379 +               pcf50606_wdt_keepalive(pcf);
82380 +               return 0;
82381 +       case WDIOC_GETTIMEOUT:
82382 +               return put_user(8, p);
82383 +       default:
82384 +               return -ENOIOCTLCMD;
82385 +       }
82386 +}
82387 +
82388 +static struct file_operations pcf50606_wdt_fops = {
82389 +       .owner          = THIS_MODULE,
82390 +       .llseek         = no_llseek,
82391 +       .write          = &pcf50606_wdt_write,
82392 +       .ioctl          = &pcf50606_wdt_ioctl,
82393 +       .open           = &pcf50606_wdt_open,
82394 +       .release        = &pcf50606_wdt_release,
82395 +};
82396 +
82397 +static struct miscdevice pcf50606_wdt_miscdev = {
82398 +       .minor          = WATCHDOG_MINOR,
82399 +       .name           = "watchdog",
82400 +       .fops           = &pcf50606_wdt_fops,
82401 +};
82402 +
82403 +/***********************************************************************
82404 + * PWM
82405 + ***********************************************************************/
82406 +
82407 +static const char *pwm_dc_table[] = {
82408 +       "0/16", "1/16", "2/16", "3/16",
82409 +       "4/16", "5/16", "6/16", "7/16",
82410 +       "8/16", "9/16", "10/16", "11/16",
82411 +       "12/16", "13/16", "14/16", "15/16",
82412 +};
82413 +
82414 +static ssize_t show_pwm_dc(struct device *dev, struct device_attribute *attr,
82415 +                          char *buf)
82416 +{
82417 +       struct i2c_client *client = to_i2c_client(dev);
82418 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82419 +       u_int8_t val;
82420 +
82421 +       val = reg_read(pcf, PCF50606_REG_PWMC1) >> PCF50606_PWMC1_DC_SHIFT;
82422 +       val &= 0xf;
82423 +
82424 +       return sprintf(buf, "%s\n", pwm_dc_table[val]);
82425 +}
82426 +
82427 +static ssize_t set_pwm_dc(struct device *dev, struct device_attribute *attr,
82428 +                         const char *buf, size_t count)
82429 +{
82430 +       struct i2c_client *client = to_i2c_client(dev);
82431 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82432 +       u_int8_t i;
82433 +
82434 +       for (i = 0; i < ARRAY_SIZE(pwm_dc_table); i++) {
82435 +               if (!strncmp(buf, pwm_dc_table[i], strlen(pwm_dc_table[i]))) {
82436 +                       dev_dbg(dev, "setting pwm dc %s\n\r", pwm_dc_table[i]);
82437 +                       reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0x1e,
82438 +                                        (i << PCF50606_PWMC1_DC_SHIFT));
82439 +               }
82440 +       }
82441 +       return count;
82442 +}
82443 +
82444 +static DEVICE_ATTR(pwm_dc, S_IRUGO | S_IWUSR, show_pwm_dc, set_pwm_dc);
82445 +
82446 +static const char *pwm_clk_table[] = {
82447 +       "512", "256", "128", "64",
82448 +       "56300", "28100", "14100", "7000",
82449 +};
82450 +
82451 +static ssize_t show_pwm_clk(struct device *dev, struct device_attribute *attr,
82452 +                           char *buf)
82453 +{
82454 +       struct i2c_client *client = to_i2c_client(dev);
82455 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82456 +       u_int8_t val;
82457 +
82458 +       val = reg_read(pcf, PCF50606_REG_PWMC1) >> PCF50606_PWMC1_CLK_SHIFT;
82459 +       val &= 0x7;
82460 +
82461 +       return sprintf(buf, "%s\n", pwm_clk_table[val]);
82462 +}
82463 +
82464 +static ssize_t set_pwm_clk(struct device *dev, struct device_attribute *attr,
82465 +                          const char *buf, size_t count)
82466 +{
82467 +       struct i2c_client *client = to_i2c_client(dev);
82468 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82469 +       u_int8_t i;
82470 +
82471 +       for (i = 0; i < ARRAY_SIZE(pwm_clk_table); i++) {
82472 +               if (!strncmp(buf, pwm_clk_table[i], strlen(pwm_clk_table[i]))) {
82473 +                       dev_dbg(dev, "setting pwm clk %s\n\r",
82474 +                               pwm_clk_table[i]);
82475 +                       reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0xe0,
82476 +                                        (i << PCF50606_PWMC1_CLK_SHIFT));
82477 +               }
82478 +       }
82479 +       return count;
82480 +}
82481 +
82482 +static DEVICE_ATTR(pwm_clk, S_IRUGO | S_IWUSR, show_pwm_clk, set_pwm_clk);
82483 +
82484 +static int pcf50606bl_get_intensity(struct backlight_device *bd)
82485 +{
82486 +       struct pcf50606_data *pcf = bl_get_data(bd);
82487 +       int intensity = reg_read(pcf, PCF50606_REG_PWMC1);
82488 +       intensity = (intensity >> PCF50606_PWMC1_DC_SHIFT);
82489 +
82490 +       return intensity & 0xf;
82491 +}
82492 +
82493 +static int pcf50606bl_set_intensity(struct backlight_device *bd)
82494 +{
82495 +       struct pcf50606_data *pcf = bl_get_data(bd);
82496 +       int intensity = bd->props.brightness;
82497 +
82498 +       if (bd->props.power != FB_BLANK_UNBLANK)
82499 +               intensity = 0;
82500 +       if (bd->props.fb_blank != FB_BLANK_UNBLANK)
82501 +               intensity = 0;
82502 +
82503 +       return reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0x1e,
82504 +                               (intensity << PCF50606_PWMC1_DC_SHIFT));
82505 +}
82506 +
82507 +static struct backlight_ops pcf50606bl_ops = {
82508 +       .get_brightness = pcf50606bl_get_intensity,
82509 +       .update_status  = pcf50606bl_set_intensity,
82510 +};
82511 +
82512 +/***********************************************************************
82513 + * Driver initialization
82514 + ***********************************************************************/
82515 +
82516 +#ifdef CONFIG_MACH_NEO1973_GTA01
82517 +/* We currently place those platform devices here to make sure the device
82518 + * suspend/resume order is correct */
82519 +static struct platform_device gta01_pm_gps_dev = {
82520 +       .name           = "neo1973-pm-gps",
82521 +};
82522 +
82523 +static struct platform_device gta01_pm_bt_dev = {
82524 +       .name           = "neo1973-pm-bt",
82525 +};
82526 +#endif
82527 +
82528 +static struct attribute *pcf_sysfs_entries[16] = {
82529 +       &dev_attr_voltage_dcd.attr,
82530 +       &dev_attr_voltage_dcde.attr,
82531 +       &dev_attr_voltage_dcud.attr,
82532 +       &dev_attr_voltage_d1reg.attr,
82533 +       &dev_attr_voltage_d2reg.attr,
82534 +       &dev_attr_voltage_d3reg.attr,
82535 +       &dev_attr_voltage_lpreg.attr,
82536 +       &dev_attr_voltage_ioreg.attr,
82537 +       NULL
82538 +};
82539 +
82540 +static struct attribute_group pcf_attr_group = {
82541 +       .name   = NULL,                 /* put in device directory */
82542 +       .attrs  = pcf_sysfs_entries,
82543 +};
82544 +
82545 +static void populate_sysfs_group(struct pcf50606_data *pcf)
82546 +{
82547 +       int i = 0;
82548 +       struct attribute **attr;
82549 +
82550 +       for (attr = pcf_sysfs_entries; *attr; attr++)
82551 +               i++;
82552 +
82553 +       if (pcf->pdata->used_features & PCF50606_FEAT_MBC) {
82554 +               pcf_sysfs_entries[i++] = &dev_attr_chgstate.attr;
82555 +               pcf_sysfs_entries[i++] = &dev_attr_chgmode.attr;
82556 +       }
82557 +
82558 +       if (pcf->pdata->used_features & PCF50606_FEAT_CHGCUR)
82559 +               pcf_sysfs_entries[i++] = &dev_attr_chgcur.attr;
82560 +
82561 +       if (pcf->pdata->used_features & PCF50606_FEAT_BATVOLT)
82562 +               pcf_sysfs_entries[i++] = &dev_attr_battvolt.attr;
82563 +
82564 +       if (pcf->pdata->used_features & PCF50606_FEAT_BATTEMP)
82565 +               pcf_sysfs_entries[i++] = &dev_attr_battemp.attr;
82566 +
82567 +       if (pcf->pdata->used_features & PCF50606_FEAT_PWM) {
82568 +               pcf_sysfs_entries[i++] = &dev_attr_pwm_dc.attr;
82569 +               pcf_sysfs_entries[i++] = &dev_attr_pwm_clk.attr;
82570 +       }
82571 +}
82572 +
82573 +static int pcf50606_detect(struct i2c_adapter *adapter, int address, int kind)
82574 +{
82575 +       struct i2c_client *new_client;
82576 +       struct pcf50606_data *data;
82577 +       int err = 0;
82578 +       int irq;
82579 +
82580 +       if (!pcf50606_pdev) {
82581 +               printk(KERN_ERR "pcf50606: driver needs a platform_device!\n");
82582 +               return -EIO;
82583 +       }
82584 +
82585 +       irq = platform_get_irq(pcf50606_pdev, 0);
82586 +       if (irq < 0) {
82587 +               dev_err(&pcf50606_pdev->dev, "no irq in platform resources!\n");
82588 +               return -EIO;
82589 +       }
82590 +
82591 +       /* At the moment, we only support one PCF50606 in a system */
82592 +       if (pcf50606_global) {
82593 +               dev_err(&pcf50606_pdev->dev,
82594 +                       "currently only one chip supported\n");
82595 +               return -EBUSY;
82596 +       }
82597 +
82598 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
82599 +       if (!data)
82600 +               return -ENOMEM;
82601 +
82602 +       mutex_init(&data->lock);
82603 +       mutex_init(&data->working_lock);
82604 +       INIT_WORK(&data->work, pcf50606_work);
82605 +       data->irq = irq;
82606 +       data->working = 0;
82607 +       data->suppress_onkey_events = 0;
82608 +       data->onkey_seconds = -1;
82609 +       data->pdata = pcf50606_pdev->dev.platform_data;
82610 +
82611 +       new_client = &data->client;
82612 +       i2c_set_clientdata(new_client, data);
82613 +       new_client->addr = address;
82614 +       new_client->adapter = adapter;
82615 +       new_client->driver = &pcf50606_driver;
82616 +       new_client->flags = 0;
82617 +       strlcpy(new_client->name, "pcf50606", I2C_NAME_SIZE);
82618 +
82619 +       /* now we try to detect the chip */
82620 +
82621 +       /* register with i2c core */
82622 +       err = i2c_attach_client(new_client);
82623 +       if (err) {
82624 +               dev_err(&new_client->dev,
82625 +                       "error during i2c_attach_client()\n");
82626 +               goto exit_free;
82627 +       }
82628 +
82629 +       populate_sysfs_group(data);
82630 +
82631 +       err = sysfs_create_group(&new_client->dev.kobj, &pcf_attr_group);
82632 +       if (err) {
82633 +               dev_err(&new_client->dev, "error creating sysfs group\n");
82634 +               goto exit_detach;
82635 +       }
82636 +
82637 +       /* create virtual charger 'device' */
82638 +
82639 +       /* input device registration */
82640 +       data->input_dev = input_allocate_device();
82641 +       if (!data->input_dev)
82642 +               goto exit_sysfs;
82643 +
82644 +       data->input_dev->name = "FIC Neo1973 PMU events";
82645 +       data->input_dev->phys = "I2C";
82646 +       data->input_dev->id.bustype = BUS_I2C;
82647 +
82648 +       data->input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
82649 +       set_bit(KEY_POWER, data->input_dev->keybit);
82650 +       set_bit(KEY_POWER2, data->input_dev->keybit);
82651 +       set_bit(KEY_BATTERY, data->input_dev->keybit);
82652 +
82653 +       err = input_register_device(data->input_dev);
82654 +       if (err)
82655 +               goto exit_sysfs;
82656 +
82657 +       /* register power off handler with core power management */
82658 +       pm_power_off = &pcf50606_go_standby;
82659 +
82660 +       /* configure interrupt mask */
82661 +       /* we don't mask SECOND here, because we want one to do coldplug with */
82662 +       reg_write(data, PCF50606_REG_INT1M, 0x00);
82663 +       reg_write(data, PCF50606_REG_INT2M, 0x00);
82664 +       reg_write(data, PCF50606_REG_INT3M, PCF50606_INT3_TSCPRES);
82665 +
82666 +       err = request_irq(irq, pcf50606_irq, IRQF_TRIGGER_FALLING,
82667 +                         "pcf50606", data);
82668 +       if (err < 0)
82669 +               goto exit_input;
82670 +
82671 +       if (enable_irq_wake(irq) < 0)
82672 +               dev_err(&new_client->dev, "IRQ %u cannot be enabled as wake-up"
82673 +                       "source in this hardware revision!", irq);
82674 +
82675 +       pcf50606_global = data;
82676 +
82677 +       if (data->pdata->used_features & PCF50606_FEAT_RTC) {
82678 +               data->rtc = rtc_device_register("pcf50606", &new_client->dev,
82679 +                                               &pcf50606_rtc_ops, THIS_MODULE);
82680 +               if (IS_ERR(data->rtc)) {
82681 +                       err = PTR_ERR(data->rtc);
82682 +                       goto exit_irq;
82683 +               }
82684 +       }
82685 +
82686 +       if (data->pdata->used_features & PCF50606_FEAT_WDT) {
82687 +               err = misc_register(&pcf50606_wdt_miscdev);
82688 +               if (err) {
82689 +                       dev_err(&new_client->dev, "cannot register miscdev on "
82690 +                              "minor=%d (%d)\n", WATCHDOG_MINOR, err);
82691 +                       goto exit_rtc;
82692 +               }
82693 +       }
82694 +
82695 +       if (data->pdata->used_features & PCF50606_FEAT_PWM) {
82696 +               /* enable PWM controller */
82697 +               reg_set_bit_mask(data, PCF50606_REG_PWMC1,
82698 +                                PCF50606_PWMC1_ACTSET,
82699 +                                PCF50606_PWMC1_ACTSET);
82700 +       }
82701 +
82702 +       if (data->pdata->used_features & PCF50606_FEAT_PWM_BL) {
82703 +               data->backlight = backlight_device_register("pcf50606-bl",
82704 +                                                           &new_client->dev,
82705 +                                                           data,
82706 +                                                           &pcf50606bl_ops);
82707 +               if (!data->backlight)
82708 +                       goto exit_misc;
82709 +               data->backlight->props.max_brightness = 16;
82710 +               data->backlight->props.power = FB_BLANK_UNBLANK;
82711 +               data->backlight->props.brightness =
82712 +                                       data->pdata->init_brightness;
82713 +               backlight_update_status(data->backlight);
82714 +       }
82715 +
82716 +       apm_get_power_status = pcf50606_get_power_status;
82717 +
82718 +#ifdef CONFIG_MACH_NEO1973_GTA01
82719 +       if (machine_is_neo1973_gta01()) {
82720 +               gta01_pm_gps_dev.dev.parent = &new_client->dev;
82721 +               switch (system_rev) {
82722 +               case GTA01Bv2_SYSTEM_REV:
82723 +               case GTA01Bv3_SYSTEM_REV:
82724 +               case GTA01Bv4_SYSTEM_REV:
82725 +                       gta01_pm_bt_dev.dev.parent = &new_client->dev;
82726 +                       platform_device_register(&gta01_pm_bt_dev);
82727 +                       break;
82728 +               }
82729 +               platform_device_register(&gta01_pm_gps_dev);
82730 +               /* a link for gllin compatibility */
82731 +               err = bus_create_device_link(&platform_bus_type,
82732 +                       &gta01_pm_gps_dev.dev.kobj, "gta01-pm-gps.0");
82733 +               if (err)
82734 +                       printk(KERN_ERR
82735 +                           "sysfs_create_link (gta01-pm-gps.0): %d\n", err);
82736 +       }
82737 +#endif
82738 +
82739 +       if (data->pdata->used_features & PCF50606_FEAT_ACD)
82740 +               reg_set_bit_mask(data, PCF50606_REG_ACDC1,
82741 +                                PCF50606_ACDC1_ACDAPE, PCF50606_ACDC1_ACDAPE);
82742 +       else
82743 +               reg_clear_bits(data, PCF50606_REG_ACDC1,
82744 +                              PCF50606_ACDC1_ACDAPE);
82745 +
82746 +       return 0;
82747 +
82748 +exit_misc:
82749 +       if (data->pdata->used_features & PCF50606_FEAT_WDT)
82750 +               misc_deregister(&pcf50606_wdt_miscdev);
82751 +exit_rtc:
82752 +       if (data->pdata->used_features & PCF50606_FEAT_RTC)
82753 +               rtc_device_unregister(pcf50606_global->rtc);
82754 +exit_irq:
82755 +       free_irq(pcf50606_global->irq, pcf50606_global);
82756 +       pcf50606_global = NULL;
82757 +exit_input:
82758 +       pm_power_off = NULL;
82759 +       input_unregister_device(data->input_dev);
82760 +exit_sysfs:
82761 +       sysfs_remove_group(&new_client->dev.kobj, &pcf_attr_group);
82762 +exit_detach:
82763 +       i2c_detach_client(new_client);
82764 +exit_free:
82765 +       kfree(data);
82766 +       return err;
82767 +}
82768 +
82769 +static int pcf50606_attach_adapter(struct i2c_adapter *adapter)
82770 +{
82771 +       return i2c_probe(adapter, &addr_data, &pcf50606_detect);
82772 +}
82773 +
82774 +static int pcf50606_detach_client(struct i2c_client *client)
82775 +{
82776 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82777 +
82778 +       apm_get_power_status = NULL;
82779 +       input_unregister_device(pcf->input_dev);
82780 +
82781 +       if (pcf->pdata->used_features & PCF50606_FEAT_PWM_BL)
82782 +               backlight_device_unregister(pcf->backlight);
82783 +
82784 +       if (pcf->pdata->used_features & PCF50606_FEAT_WDT)
82785 +               misc_deregister(&pcf50606_wdt_miscdev);
82786 +
82787 +       if (pcf->pdata->used_features & PCF50606_FEAT_RTC)
82788 +               rtc_device_unregister(pcf->rtc);
82789 +
82790 +       free_irq(pcf->irq, pcf);
82791 +
82792 +       sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
82793 +
82794 +       pm_power_off = NULL;
82795 +
82796 +       kfree(pcf);
82797 +
82798 +       return 0;
82799 +}
82800 +
82801 +#ifdef CONFIG_PM
82802 +#define INT1M_RESUMERS (PCF50606_INT1_ALARM | \
82803 +                        PCF50606_INT1_ONKEYF | \
82804 +                        PCF50606_INT1_EXTONR)
82805 +#define INT2M_RESUMERS (PCF50606_INT2_CHGWD10S | \
82806 +                        PCF50606_INT2_CHGPROT | \
82807 +                        PCF50606_INT2_CHGERR)
82808 +#define INT3M_RESUMERS (PCF50606_INT3_LOWBAT | \
82809 +                        PCF50606_INT3_HIGHTMP | \
82810 +                        PCF50606_INT3_ACDINS)
82811 +static int pcf50606_suspend(struct device *dev, pm_message_t state)
82812 +{
82813 +       struct i2c_client *client = to_i2c_client(dev);
82814 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82815 +       int i;
82816 +
82817 +       /* we suspend once (!) as late as possible in the suspend sequencing */
82818 +
82819 +       if ((state.event != PM_EVENT_SUSPEND) ||
82820 +           (pcf->suspend_state != PCF50606_SS_RUNNING))
82821 +               return -EBUSY;
82822 +
82823 +       /* The general idea is to power down all unused power supplies,
82824 +        * and then mask all PCF50606 interrup sources but EXTONR, ONKEYF
82825 +        * and ALARM */
82826 +
82827 +       mutex_lock(&pcf->lock);
82828 +
82829 +       pcf->suspend_state = PCF50606_SS_STARTING_SUSPEND;
82830 +
82831 +       /* we are not going to service any further interrupts until we
82832 +        * resume.  If the IRQ workqueue is still pending in the background,
82833 +        * it will bail when it sees we set suspend state above.
82834 +        */
82835 +
82836 +       disable_irq(pcf->irq);
82837 +
82838 +       /* Save all registers that don't "survive" standby state */
82839 +       pcf->standby_regs.dcdc1 = __reg_read(pcf, PCF50606_REG_DCDC1);
82840 +       pcf->standby_regs.dcdc2 = __reg_read(pcf, PCF50606_REG_DCDC2);
82841 +       pcf->standby_regs.dcdec1 = __reg_read(pcf, PCF50606_REG_DCDEC1);
82842 +       pcf->standby_regs.dcudc1 = __reg_read(pcf, PCF50606_REG_DCUDC1);
82843 +       pcf->standby_regs.ioregc = __reg_read(pcf, PCF50606_REG_IOREGC);
82844 +       pcf->standby_regs.d1regc1 = __reg_read(pcf, PCF50606_REG_D1REGC1);
82845 +       pcf->standby_regs.d2regc1 = __reg_read(pcf, PCF50606_REG_D2REGC1);
82846 +       pcf->standby_regs.d3regc1 = __reg_read(pcf, PCF50606_REG_D3REGC1);
82847 +       pcf->standby_regs.lpregc1 = __reg_read(pcf, PCF50606_REG_LPREGC1);
82848 +       pcf->standby_regs.adcc1 = __reg_read(pcf, PCF50606_REG_ADCC1);
82849 +       pcf->standby_regs.adcc2 = __reg_read(pcf, PCF50606_REG_ADCC2);
82850 +       pcf->standby_regs.pwmc1 = __reg_read(pcf, PCF50606_REG_PWMC1);
82851 +
82852 +       /* switch off power supplies that are not needed during suspend */
82853 +       for (i = 0; i < __NUM_PCF50606_REGULATORS; i++) {
82854 +               if (!(pcf->pdata->rails[i].flags & PMU_VRAIL_F_SUSPEND_ON)) {
82855 +                       u_int8_t tmp;
82856 +
82857 +                       /* IOREG powers the I@C interface so we cannot switch
82858 +                        * it off */
82859 +                       if (i == PCF50606_REGULATOR_IOREG)
82860 +                               continue;
82861 +
82862 +                       dev_dbg(dev, "disabling pcf50606 regulator %u\n", i);
82863 +                       /* we cannot use pcf50606_onoff_set() because we're
82864 +                        * already under the mutex */
82865 +                       tmp = __reg_read(pcf, regulator_registers[i]);
82866 +                       tmp &= 0x1f;
82867 +                       __reg_write(pcf, regulator_registers[i], tmp);
82868 +               }
82869 +       }
82870 +
82871 +       pcf->standby_regs.int1m = __reg_read(pcf, PCF50606_REG_INT1M);
82872 +       pcf->standby_regs.int2m = __reg_read(pcf, PCF50606_REG_INT2M);
82873 +       pcf->standby_regs.int3m = __reg_read(pcf, PCF50606_REG_INT3M);
82874 +       __reg_write(pcf, PCF50606_REG_INT1M, ~INT1M_RESUMERS & 0xff);
82875 +       __reg_write(pcf, PCF50606_REG_INT2M, ~INT2M_RESUMERS & 0xff);
82876 +       __reg_write(pcf, PCF50606_REG_INT3M, ~INT3M_RESUMERS & 0xff);
82877 +
82878 +       pcf->suspend_state = PCF50606_SS_COMPLETED_SUSPEND;
82879 +
82880 +       mutex_unlock(&pcf->lock);
82881 +
82882 +       return 0;
82883 +}
82884 +
82885 +static int pcf50606_resume(struct device *dev)
82886 +{
82887 +       struct i2c_client *client = to_i2c_client(dev);
82888 +       struct pcf50606_data *pcf = i2c_get_clientdata(client);
82889 +
82890 +       mutex_lock(&pcf->lock);
82891 +
82892 +       pcf->suspend_state = PCF50606_SS_STARTING_RESUME;
82893 +
82894 +       /* Resume all saved registers that don't "survive" standby state */
82895 +       __reg_write(pcf, PCF50606_REG_INT1M, pcf->standby_regs.int1m);
82896 +       __reg_write(pcf, PCF50606_REG_INT2M, pcf->standby_regs.int2m);
82897 +       __reg_write(pcf, PCF50606_REG_INT3M, pcf->standby_regs.int3m);
82898 +
82899 +       __reg_write(pcf, PCF50606_REG_DCDC1, pcf->standby_regs.dcdc1);
82900 +       __reg_write(pcf, PCF50606_REG_DCDC2, pcf->standby_regs.dcdc2);
82901 +       __reg_write(pcf, PCF50606_REG_DCDEC1, pcf->standby_regs.dcdec1);
82902 +       __reg_write(pcf, PCF50606_REG_DCUDC1, pcf->standby_regs.dcudc1);
82903 +       __reg_write(pcf, PCF50606_REG_IOREGC, pcf->standby_regs.ioregc);
82904 +       __reg_write(pcf, PCF50606_REG_D1REGC1, pcf->standby_regs.d1regc1);
82905 +       __reg_write(pcf, PCF50606_REG_D2REGC1, pcf->standby_regs.d2regc1);
82906 +       __reg_write(pcf, PCF50606_REG_D3REGC1, pcf->standby_regs.d3regc1);
82907 +       __reg_write(pcf, PCF50606_REG_LPREGC1, pcf->standby_regs.lpregc1);
82908 +       __reg_write(pcf, PCF50606_REG_ADCC1, pcf->standby_regs.adcc1);
82909 +       __reg_write(pcf, PCF50606_REG_ADCC2, pcf->standby_regs.adcc2);
82910 +       __reg_write(pcf, PCF50606_REG_PWMC1, pcf->standby_regs.pwmc1);
82911 +
82912 +       pcf->suspend_state = PCF50606_SS_COMPLETED_RESUME;
82913 +
82914 +       enable_irq(pcf->irq);
82915 +
82916 +       mutex_unlock(&pcf->lock);
82917 +
82918 +       /* Call PCF work function; this fixes an issue on the gta01 where
82919 +        * the power button "goes away" if it is used to wake the device.
82920 +        */
82921 +       get_device(&pcf->client.dev);
82922 +       pcf50606_work(&pcf->work);
82923 +
82924 +       return 0;
82925 +}
82926 +#else
82927 +#define pcf50606_suspend NULL
82928 +#define pcf50606_resume NULL
82929 +#endif
82930 +
82931 +static struct i2c_driver pcf50606_driver = {
82932 +       .driver = {
82933 +               .name    = "pcf50606",
82934 +               .suspend = pcf50606_suspend,
82935 +               .resume  = pcf50606_resume,
82936 +       },
82937 +       .id             = I2C_DRIVERID_PCF50606,
82938 +       .attach_adapter = pcf50606_attach_adapter,
82939 +       .detach_client  = pcf50606_detach_client,
82940 +};
82941 +
82942 +/* platform driver, since i2c devices don't have platform_data */
82943 +static int __init pcf50606_plat_probe(struct platform_device *pdev)
82944 +{
82945 +       struct pcf50606_platform_data *pdata = pdev->dev.platform_data;
82946 +
82947 +       if (!pdata)
82948 +               return -ENODEV;
82949 +
82950 +       pcf50606_pdev = pdev;
82951 +
82952 +       return 0;
82953 +}
82954 +
82955 +static int pcf50606_plat_remove(struct platform_device *pdev)
82956 +{
82957 +       return 0;
82958 +}
82959 +
82960 +/* We have this purely to capture an early indication that we are coming out
82961 + * of suspend, before our device resume got called; async interrupt service is
82962 + * interested in this.
82963 + */
82964 +
82965 +static int pcf50606_plat_resume(struct platform_device *pdev)
82966 +{
82967 +       /* i2c_get_clientdata(to_i2c_client(&pdev->dev)) returns NULL at this
82968 +        * early resume time so we have to use pcf50606_global
82969 +        */
82970 +       pcf50606_global->suspend_state = PCF50606_SS_RESUMING_BUT_NOT_US_YET;
82971 +
82972 +       return 0;
82973 +}
82974 +
82975 +static struct platform_driver pcf50606_plat_driver = {
82976 +       .probe  = pcf50606_plat_probe,
82977 +       .remove = pcf50606_plat_remove,
82978 +       .resume_early = pcf50606_plat_resume,
82979 +       .driver = {
82980 +               .owner  = THIS_MODULE,
82981 +               .name   = "pcf50606",
82982 +       },
82983 +};
82984 +
82985 +static int __init pcf50606_init(void)
82986 +{
82987 +       int rc;
82988 +
82989 +       rc = platform_driver_register(&pcf50606_plat_driver);
82990 +       if (!rc)
82991 +               rc = i2c_add_driver(&pcf50606_driver);
82992 +
82993 +       return rc;
82994 +}
82995 +
82996 +static void pcf50606_exit(void)
82997 +{
82998 +       i2c_del_driver(&pcf50606_driver);
82999 +       platform_driver_unregister(&pcf50606_plat_driver);
83000 +}
83001 +
83002 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50606 power management unit");
83003 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
83004 +MODULE_LICENSE("GPL");
83005 +
83006 +module_init(pcf50606_init);
83007 +module_exit(pcf50606_exit);
83008 Index: linux-2.6.28/drivers/i2c/chips/pcf50606.h
83009 ===================================================================
83010 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
83011 +++ linux-2.6.28/drivers/i2c/chips/pcf50606.h   2009-01-02 00:01:56.000000000 +0100
83012 @@ -0,0 +1,302 @@
83013 +#ifndef _PCF50606_H
83014 +#define _PCF50606_H
83015 +
83016 +/* Philips PCF50606 Power Managemnt Unit (PMU) driver
83017 + * (C) 2006-2007 by Openmoko, Inc.
83018 + * Author: Harald Welte <laforge@openmoko.org>
83019 + *
83020 + */
83021 +
83022 +enum pfc50606_regs {
83023 +       PCF50606_REG_ID         = 0x00,
83024 +       PCF50606_REG_OOCS       = 0x01,
83025 +       PCF50606_REG_INT1       = 0x02, /* Interrupt Status */
83026 +       PCF50606_REG_INT2       = 0x03, /* Interrupt Status */
83027 +       PCF50606_REG_INT3       = 0x04, /* Interrupt Status */
83028 +       PCF50606_REG_INT1M      = 0x05, /* Interrupt Mask */
83029 +       PCF50606_REG_INT2M      = 0x06, /* Interrupt Mask */
83030 +       PCF50606_REG_INT3M      = 0x07, /* Interrupt Mask */
83031 +       PCF50606_REG_OOCC1      = 0x08,
83032 +       PCF50606_REG_OOCC2      = 0x09,
83033 +       PCF50606_REG_RTCSC      = 0x0a, /* Second */
83034 +       PCF50606_REG_RTCMN      = 0x0b, /* Minute */
83035 +       PCF50606_REG_RTCHR      = 0x0c, /* Hour */
83036 +       PCF50606_REG_RTCWD      = 0x0d, /* Weekday */
83037 +       PCF50606_REG_RTCDT      = 0x0e, /* Day */
83038 +       PCF50606_REG_RTCMT      = 0x0f, /* Month */
83039 +       PCF50606_REG_RTCYR      = 0x10, /* Year */
83040 +       PCF50606_REG_RTCSCA     = 0x11, /* Alarm Second */
83041 +       PCF50606_REG_RTCMNA     = 0x12, /* Alarm Minute */
83042 +       PCF50606_REG_RTCHRA     = 0x13, /* Alarm Hour */
83043 +       PCF50606_REG_RTCWDA     = 0x14, /* Alarm Weekday */
83044 +       PCF50606_REG_RTCDTA     = 0x15, /* Alarm Day */
83045 +       PCF50606_REG_RTCMTA     = 0x16, /* Alarm Month */
83046 +       PCF50606_REG_RTCYRA     = 0x17, /* Alarm Year */
83047 +       PCF50606_REG_PSSC       = 0x18, /* Power sequencing */
83048 +       PCF50606_REG_PWROKM     = 0x19, /* PWROK mask */
83049 +       PCF50606_REG_PWROKS     = 0x1a, /* PWROK status */
83050 +       PCF50606_REG_DCDC1      = 0x1b,
83051 +       PCF50606_REG_DCDC2      = 0x1c,
83052 +       PCF50606_REG_DCDC3      = 0x1d,
83053 +       PCF50606_REG_DCDC4      = 0x1e,
83054 +       PCF50606_REG_DCDEC1     = 0x1f,
83055 +       PCF50606_REG_DCDEC2     = 0x20,
83056 +       PCF50606_REG_DCUDC1     = 0x21,
83057 +       PCF50606_REG_DCUDC2     = 0x22,
83058 +       PCF50606_REG_IOREGC     = 0x23,
83059 +       PCF50606_REG_D1REGC1    = 0x24,
83060 +       PCF50606_REG_D2REGC1    = 0x25,
83061 +       PCF50606_REG_D3REGC1    = 0x26,
83062 +       PCF50606_REG_LPREGC1    = 0x27,
83063 +       PCF50606_REG_LPREGC2    = 0x28,
83064 +       PCF50606_REG_MBCC1      = 0x29,
83065 +       PCF50606_REG_MBCC2      = 0x2a,
83066 +       PCF50606_REG_MBCC3      = 0x2b,
83067 +       PCF50606_REG_MBCS1      = 0x2c,
83068 +       PCF50606_REG_BBCC       = 0x2d,
83069 +       PCF50606_REG_ADCC1      = 0x2e,
83070 +       PCF50606_REG_ADCC2      = 0x2f,
83071 +       PCF50606_REG_ADCS1      = 0x30,
83072 +       PCF50606_REG_ADCS2      = 0x31,
83073 +       PCF50606_REG_ADCS3      = 0x32,
83074 +       PCF50606_REG_ACDC1      = 0x33,
83075 +       PCF50606_REG_BVMC       = 0x34,
83076 +       PCF50606_REG_PWMC1      = 0x35,
83077 +       PCF50606_REG_LEDC1      = 0x36,
83078 +       PCF50606_REG_LEDC2      = 0x37,
83079 +       PCF50606_REG_GPOC1      = 0x38,
83080 +       PCF50606_REG_GPOC2      = 0x39,
83081 +       PCF50606_REG_GPOC3      = 0x3a,
83082 +       PCF50606_REG_GPOC4      = 0x3b,
83083 +       PCF50606_REG_GPOC5      = 0x3c,
83084 +       __NUM_PCF50606_REGS
83085 +};
83086 +
83087 +enum pcf50606_reg_oocs {
83088 +       PFC50606_OOCS_ONKEY     = 0x01,
83089 +       PCF50606_OOCS_EXTON     = 0x02,
83090 +       PCF50606_OOCS_PWROKRST  = 0x04,
83091 +       PCF50606_OOCS_BATOK     = 0x08,
83092 +       PCF50606_OOCS_BACKOK    = 0x10,
83093 +       PCF50606_OOCS_CHGOK     = 0x20,
83094 +       PCF50606_OOCS_TEMPOK    = 0x40,
83095 +       PCF50606_OOCS_WDTEXP    = 0x80,
83096 +};
83097 +
83098 +enum pcf50606_reg_oocc1 {
83099 +       PCF50606_OOCC1_GOSTDBY  = 0x01,
83100 +       PCF50606_OOCC1_TOTRST   = 0x02,
83101 +       PCF50606_OOCC1_CLK32ON  = 0x04,
83102 +       PCF50606_OOCC1_WDTRST   = 0x08,
83103 +       PCF50606_OOCC1_RTCWAK   = 0x10,
83104 +       PCF50606_OOCC1_CHGWAK   = 0x20,
83105 +       PCF50606_OOCC1_EXTONWAK_HIGH    = 0x40,
83106 +       PCF50606_OOCC1_EXTONWAK_LOW     = 0x80,
83107 +};
83108 +
83109 +enum pcf50606_reg_oocc2 {
83110 +       PCF50606_OOCC2_ONKEYDB_NONE     = 0x00,
83111 +       PCF50606_OOCC2_ONKEYDB_14ms     = 0x01,
83112 +       PCF50606_OOCC2_ONKEYDB_62ms     = 0x02,
83113 +       PCF50606_OOCC2_ONKEYDB_500ms    = 0x03,
83114 +       PCF50606_OOCC2_EXTONDB_NONE     = 0x00,
83115 +       PCF50606_OOCC2_EXTONDB_14ms     = 0x04,
83116 +       PCF50606_OOCC2_EXTONDB_62ms     = 0x08,
83117 +       PCF50606_OOCC2_EXTONDB_500ms    = 0x0c,
83118 +};
83119 +
83120 +enum pcf50606_reg_int1 {
83121 +       PCF50606_INT1_ONKEYR    = 0x01, /* ONKEY rising edge */
83122 +       PCF50606_INT1_ONKEYF    = 0x02, /* ONKEY falling edge */
83123 +       PCF50606_INT1_ONKEY1S   = 0x04, /* OMKEY at least 1sec low */
83124 +       PCF50606_INT1_EXTONR    = 0x08, /* EXTON rising edge */
83125 +       PCF50606_INT1_EXTONF    = 0x10, /* EXTON falling edge */
83126 +       PCF50606_INT1_SECOND    = 0x40, /* RTC periodic second interrupt */
83127 +       PCF50606_INT1_ALARM     = 0x80, /* RTC alarm time is reached */
83128 +};
83129 +
83130 +enum pcf50606_reg_int2 {
83131 +       PCF50606_INT2_CHGINS    = 0x01, /* Charger inserted */
83132 +       PCF50606_INT2_CHGRM     = 0x02, /* Charger removed */
83133 +       PCF50606_INT2_CHGFOK    = 0x04, /* Fast charging OK */
83134 +       PCF50606_INT2_CHGERR    = 0x08, /* Error in charging mode */
83135 +       PCF50606_INT2_CHGFRDY   = 0x10, /* Fast charge completed */
83136 +       PCF50606_INT2_CHGPROT   = 0x20, /* Charging protection interrupt */
83137 +       PCF50606_INT2_CHGWD10S  = 0x40, /* Charger watchdig expires in 10s */
83138 +       PCF50606_INT2_CHGWDEXP  = 0x80, /* Charger watchdog expires */
83139 +};
83140 +
83141 +enum pcf50606_reg_int3 {
83142 +       PCF50606_INT3_ADCRDY    = 0x01, /* ADC conversion finished */
83143 +       PCF50606_INT3_ACDINS    = 0x02, /* Accessory inserted */
83144 +       PCF50606_INT3_ACDREM    = 0x04, /* Accessory removed */
83145 +       PCF50606_INT3_TSCPRES   = 0x08, /* Touch screen pressed */
83146 +       PCF50606_INT3_LOWBAT    = 0x40, /* Low battery voltage */
83147 +       PCF50606_INT3_HIGHTMP   = 0x80, /* High temperature */
83148 +};
83149 +
83150 +/* used by PSSC, PWROKM, PWROKS, */
83151 +enum pcf50606_regu {
83152 +       PCF50606_REGU_DCD       = 0x01, /* DCD in phase 2 */
83153 +       PCF50606_REGU_DCDE      = 0x02, /* DCDE in phase 2 */
83154 +       PCF50606_REGU_DCUD      = 0x04, /* DCDU in phase 2 */
83155 +       PCF50606_REGU_IO        = 0x08, /* IO in phase 2 */
83156 +       PCF50606_REGU_D1        = 0x10, /* D1 in phase 2 */
83157 +       PCF50606_REGU_D2        = 0x20, /* D2 in phase 2 */
83158 +       PCF50606_REGU_D3        = 0x40, /* D3 in phase 2 */
83159 +       PCF50606_REGU_LP        = 0x80, /* LP in phase 2 */
83160 +};
83161 +
83162 +enum pcf50606_reg_dcdc4 {
83163 +       PCF50606_DCDC4_MODE_AUTO        = 0x00,
83164 +       PCF50606_DCDC4_MODE_PWM         = 0x01,
83165 +       PCF50606_DCDC4_MODE_PCF         = 0x02,
83166 +       PCF50606_DCDC4_OFF_FLOAT        = 0x00,
83167 +       PCF50606_DCDC4_OFF_BYPASS       = 0x04,
83168 +       PCF50606_DCDC4_OFF_PULLDOWN     = 0x08,
83169 +       PCF50606_DCDC4_CURLIM_500mA     = 0x00,
83170 +       PCF50606_DCDC4_CURLIM_750mA     = 0x10,
83171 +       PCF50606_DCDC4_CURLIM_1000mA    = 0x20,
83172 +       PCF50606_DCDC4_CURLIM_1250mA    = 0x30,
83173 +       PCF50606_DCDC4_TOGGLE           = 0x40,
83174 +       PCF50606_DCDC4_REGSEL_DCDC2     = 0x80,
83175 +};
83176 +
83177 +enum pcf50606_reg_dcdec2 {
83178 +       PCF50606_DCDEC2_MODE_AUTO       = 0x00,
83179 +       PCF50606_DCDEC2_MODE_PWM        = 0x01,
83180 +       PCF50606_DCDEC2_MODE_PCF        = 0x02,
83181 +       PCF50606_DCDEC2_OFF_FLOAT       = 0x00,
83182 +       PCF50606_DCDEC2_OFF_BYPASS      = 0x04,
83183 +};
83184 +
83185 +enum pcf50606_reg_dcudc2 {
83186 +       PCF50606_DCUDC2_MODE_AUTO       = 0x00,
83187 +       PCF50606_DCUDC2_MODE_PWM        = 0x01,
83188 +       PCF50606_DCUDC2_MODE_PCF        = 0x02,
83189 +       PCF50606_DCUDC2_OFF_FLOAT       = 0x00,
83190 +       PCF50606_DCUDC2_OFF_BYPASS      = 0x04,
83191 +};
83192 +
83193 +enum pcf50606_reg_adcc1 {
83194 +       PCF50606_ADCC1_TSCMODACT        = 0x01,
83195 +       PCF50606_ADCC1_TSCMODSTB        = 0x02,
83196 +       PCF50606_ADCC1_TRATSET          = 0x04,
83197 +       PCF50606_ADCC1_NTCSWAPE         = 0x08,
83198 +       PCF50606_ADCC1_NTCSWAOFF        = 0x10,
83199 +       PCF50606_ADCC1_EXTSYNCBREAK     = 0x20,
83200 +       /* reserved */
83201 +       PCF50606_ADCC1_TSCINT           = 0x80,
83202 +};
83203 +
83204 +enum pcf50606_reg_adcc2 {
83205 +       PCF50606_ADCC2_ADCSTART         = 0x01,
83206 +       /* see enum pcf50606_adcc2_adcmux */
83207 +       PCF50606_ADCC2_SYNC_NONE        = 0x00,
83208 +       PCF50606_ADCC2_SYNC_TXON        = 0x20,
83209 +       PCF50606_ADCC2_SYNC_PWREN1      = 0x40,
83210 +       PCF50606_ADCC2_SYNC_PWREN2      = 0x60,
83211 +       PCF50606_ADCC2_RES_10BIT        = 0x00,
83212 +       PCF50606_ADCC2_RES_8BIT         = 0x80,
83213 +};
83214 +
83215 +#define PCF50606_ADCC2_ADCMUX_MASK     (0xf << 1)
83216 +
83217 +#define ADCMUX_SHIFT   1
83218 +enum pcf50606_adcc2_adcmux {
83219 +       PCF50606_ADCMUX_BATVOLT_RES     = 0x0 << ADCMUX_SHIFT,
83220 +       PCF50606_ADCMUX_BATVOLT_SUBTR   = 0x1 << ADCMUX_SHIFT,
83221 +       PCF50606_ADCMUX_ADCIN1_RES      = 0x2 << ADCMUX_SHIFT,
83222 +       PCF50606_ADCMUX_ADCIN1_SUBTR    = 0x3 << ADCMUX_SHIFT,
83223 +       PCF50606_ADCMUX_BATTEMP         = 0x4 << ADCMUX_SHIFT,
83224 +       PCF50606_ADCMUX_ADCIN2          = 0x5 << ADCMUX_SHIFT,
83225 +       PCF50606_ADCMUX_ADCIN3          = 0x6 << ADCMUX_SHIFT,
83226 +       PCF50606_ADCMUX_ADCIN3_RATIO    = 0x7 << ADCMUX_SHIFT,
83227 +       PCF50606_ADCMUX_XPOS            = 0x8 << ADCMUX_SHIFT,
83228 +       PCF50606_ADCMUX_YPOS            = 0x9 << ADCMUX_SHIFT,
83229 +       PCF50606_ADCMUX_P1              = 0xa << ADCMUX_SHIFT,
83230 +       PCF50606_ADCMUX_P2              = 0xb << ADCMUX_SHIFT,
83231 +       PCF50606_ADCMUX_BATVOLT_ADCIN1  = 0xc << ADCMUX_SHIFT,
83232 +       PCF50606_ADCMUX_XY_SEQUENCE     = 0xe << ADCMUX_SHIFT,
83233 +       PCF50606_P1_P2_RESISTANCE       = 0xf << ADCMUX_SHIFT,
83234 +};
83235 +
83236 +enum pcf50606_adcs2 {
83237 +       PCF50606_ADCS2_ADCRDY           = 0x80,
83238 +};
83239 +
83240 +enum pcf50606_reg_mbcc1 {
83241 +       PCF50606_MBCC1_CHGAPE           = 0x01,
83242 +       PCF50606_MBCC1_AUTOFST          = 0x02,
83243 +#define        PCF50606_MBCC1_CHGMOD_MASK        0x1c
83244 +#define        PCF50606_MBCC1_CHGMOD_SHIFT       2
83245 +       PCF50606_MBCC1_CHGMOD_QUAL      = 0x00,
83246 +       PCF50606_MBCC1_CHGMOD_PRE       = 0x04,
83247 +       PCF50606_MBCC1_CHGMOD_TRICKLE   = 0x08,
83248 +       PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c,
83249 +       PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10,
83250 +       PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14,
83251 +       PCF50606_MBCC1_CHGMOD_FAST_SW   = 0x18,
83252 +       PCF50606_MBCC1_CHGMOD_IDLE      = 0x1c,
83253 +       PCF50606_MBCC1_DETMOD_LOWCHG    = 0x20,
83254 +       PCF50606_MBCC1_DETMOD_WDRST     = 0x40,
83255 +};
83256 +
83257 +enum pcf50606_reg_acdc1 {
83258 +       PCF50606_ACDC1_ACDDET           = 0x01,
83259 +       PCF50606_ACDC1_THRSHLD_1V0      = 0x00,
83260 +       PCF50606_ACDC1_THRSHLD_1V2      = 0x02,
83261 +       PCF50606_ACDC1_THRSHLD_1V4      = 0x04,
83262 +       PCF50606_ACDC1_THRSHLD_1V6      = 0x06,
83263 +       PCF50606_ACDC1_THRSHLD_1V8      = 0x08,
83264 +       PCF50606_ACDC1_THRSHLD_2V0      = 0x0a,
83265 +       PCF50606_ACDC1_THRSHLD_2V2      = 0x0c,
83266 +       PCF50606_ACDC1_THRSHLD_2V4      = 0x0e,
83267 +       PCF50606_ACDC1_DISDB            = 0x10,
83268 +       PCF50606_ACDC1_ACDAPE           = 0x80,
83269 +};
83270 +
83271 +enum pcf50606_reg_bvmc {
83272 +       PCF50606_BVMC_LOWBAT            = 0x01,
83273 +       PCF50606_BVMC_THRSHLD_NULL      = 0x00,
83274 +       PCF50606_BVMC_THRSHLD_2V8       = 0x02,
83275 +       PCF50606_BVMC_THRSHLD_2V9       = 0x04,
83276 +       PCF50606_BVMC_THRSHLD_3V        = 0x08,
83277 +       PCF50606_BVMC_THRSHLD_3V1       = 0x08,
83278 +       PCF50606_BVMC_THRSHLD_3V2       = 0x0a,
83279 +       PCF50606_BVMC_THRSHLD_3V3       = 0x0c,
83280 +       PCF50606_BVMC_THRSHLD_3V4       = 0x0e,
83281 +       PCF50606_BVMC_DISDB             = 0x10,
83282 +};
83283 +
83284 +enum pcf50606_reg_pwmc1 {
83285 +       PCF50606_PWMC1_ACTSET           = 0x01,
83286 +       PCF50606_PWMC1_PWMDC_0_16       = 0x00,
83287 +       PCF50606_PWMC1_PWMDC_1_16       = 0x02,
83288 +       PCF50606_PWMC1_PWMDC_2_16       = 0x04,
83289 +       PCF50606_PWMC1_PWMDC_3_16       = 0x06,
83290 +       PCF50606_PWMC1_PWMDC_4_16       = 0x08,
83291 +       PCF50606_PWMC1_PWMDC_5_16       = 0x0a,
83292 +       PCF50606_PWMC1_PWMDC_6_16       = 0x0c,
83293 +       PCF50606_PWMC1_PWMDC_7_16       = 0x0e,
83294 +       PCF50606_PWMC1_PWMDC_8_16       = 0x10,
83295 +       PCF50606_PWMC1_PWMDC_9_16       = 0x12,
83296 +       PCF50606_PWMC1_PWMDC_10_16      = 0x14,
83297 +       PCF50606_PWMC1_PWMDC_11_16      = 0x16,
83298 +       PCF50606_PWMC1_PWMDC_12_16      = 0x18,
83299 +       PCF50606_PWMC1_PWMDC_13_16      = 0x1a,
83300 +       PCF50606_PWMC1_PWMDC_14_16      = 0x1c,
83301 +       PCF50606_PWMC1_PWMDC_15_16      = 0x1e,
83302 +       PCF50606_PWMC1_PRESC_512Hz      = 0x20,
83303 +       PCF50606_PWMC1_PRESC_256Hz      = 0x40,
83304 +       PCF50606_PWMC1_PRESC_64Hz       = 0x60,
83305 +       PCF50606_PWMC1_PRESC_56kHz      = 0x80,
83306 +       PCF50606_PWMC1_PRESC_28kHz      = 0xa0,
83307 +       PCF50606_PWMC1_PRESC_14kHz      = 0xc0,
83308 +       PCF50606_PWMC1_PRESC_7kHz       = 0xe0,
83309 +};
83310 +#define PCF50606_PWMC1_CLK_SHIFT       5
83311 +#define PCF50606_PWMC1_DC_SHIFT                1
83312 +
83313 +#endif /* _PCF50606_H */
83314 +
83315 Index: linux-2.6.28/drivers/i2c/chips/pcf50633.c
83316 ===================================================================
83317 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
83318 +++ linux-2.6.28/drivers/i2c/chips/pcf50633.c   2009-01-02 00:01:56.000000000 +0100
83319 @@ -0,0 +1,1883 @@
83320 +/* Philips PCF50633 Power Management Unit (PMU) driver
83321 + *
83322 + * (C) 2006-2007 by Openmoko, Inc.
83323 + * Author: Harald Welte <laforge@openmoko.org>
83324 + * All rights reserved.
83325 + *
83326 + * This program is free software; you can redistribute it and/or
83327 + * modify it under the terms of the GNU General Public License as
83328 + * published by the Free Software Foundation; either version 2 of
83329 + * the License, or (at your option) any later version.
83330 + *
83331 + * This program is distributed in the hope that it will be useful,
83332 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
83333 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
83334 + * GNU General Public License for more details.
83335 + *
83336 + * You should have received a copy of the GNU General Public License
83337 + * along with this program; if not, write to the Free Software
83338 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
83339 + * MA 02111-1307 USA
83340 + *
83341 + * This driver is a monster ;) It provides the following features
83342 + * - voltage control for a dozen different voltage domains
83343 + * - charging control for main and backup battery
83344 + * - adc driver (hw_sensors like)
83345 + *
83346 + */
83347 +
83348 +#include <linux/module.h>
83349 +#include <linux/init.h>
83350 +#include <linux/i2c.h>
83351 +#include <linux/types.h>
83352 +#include <linux/interrupt.h>
83353 +#include <linux/irq.h>
83354 +#include <linux/workqueue.h>
83355 +#include <linux/delay.h>
83356 +#include <linux/rtc.h>
83357 +#include <linux/bcd.h>
83358 +#include <linux/watchdog.h>
83359 +#include <linux/miscdevice.h>
83360 +#include <linux/input.h>
83361 +#include <linux/fb.h>
83362 +#include <linux/sched.h>
83363 +#include <linux/platform_device.h>
83364 +#include <linux/pcf50633.h>
83365 +#include <linux/apm-emulation.h>
83366 +#include <linux/jiffies.h>
83367 +
83368 +#include <asm/mach-types.h>
83369 +
83370 +#include <linux/pcf50633.h>
83371 +#include <linux/regulator/pcf50633.h>
83372 +#include <linux/rtc/pcf50633.h>
83373 +
83374 +#if 0
83375 +#define DEBUGP(x, args ...) printk("%s: " x, __FUNCTION__, ## args)
83376 +#define DEBUGPC(x, args ...) printk(x, ## args)
83377 +#else
83378 +#define DEBUGP(x, args ...)
83379 +#define DEBUGPC(x, args ...)
83380 +#endif
83381 +
83382 +/***********************************************************************
83383 + * Static data / structures
83384 + ***********************************************************************/
83385 +
83386 +static unsigned short normal_i2c[] = { 0x73, I2C_CLIENT_END };
83387 +
83388 +I2C_CLIENT_INSMOD_1(pcf50633);
83389 +
83390 +enum close_state {
83391 +       CLOSE_STATE_NOT,
83392 +       CLOSE_STATE_ALLOW = 0x2342,
83393 +};
83394 +
83395 +static struct i2c_driver pcf50633_driver;
83396 +
83397 +static void pcf50633_usb_curlim_set(struct pcf50633_data *pcf, int ma);
83398 +static void pcf50633_charge_enable(struct pcf50633_data *pcf, int on);
83399 +
83400 +
83401 +/***********************************************************************
83402 + * Low-Level routines
83403 + ***********************************************************************/
83404 +
83405 +/* Read a block of upto 32 regs
83406 + *
83407 + * Locks assumed to be held by caller
83408 + */
83409 +int pcf50633_read(struct pcf50633_data *pcf, u_int8_t reg, int nr_regs, u_int8_t *data)
83410 +{
83411 +       return i2c_smbus_read_i2c_block_data(pcf->client, reg, nr_regs, data);
83412 +}
83413 +EXPORT_SYMBOL(pcf50633_read);
83414 +
83415 +/* Read a block of upto 32 regs
83416 + *
83417 + * Locks assumed to be held by caller
83418 + */
83419 +int pcf50633_write(struct pcf50633_data *pcf, u_int8_t reg, int nr_regs, u_int8_t *data)
83420 +{
83421 +       return i2c_smbus_write_i2c_block_data(pcf->client, reg, nr_regs, data);
83422 +}
83423 +EXPORT_SYMBOL(pcf50633_write);
83424 +
83425 +static int __reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
83426 +{
83427 +       if (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND) {
83428 +               dev_err(&pcf->client->dev, "__reg_write while suspended\n");
83429 +               dump_stack();
83430 +       }
83431 +       return i2c_smbus_write_byte_data(pcf->client, reg, val);
83432 +}
83433 +
83434 +int pcf50633_reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
83435 +{
83436 +       int ret;
83437 +
83438 +       mutex_lock(&pcf->lock);
83439 +       ret = __reg_write(pcf, reg, val);
83440 +       mutex_unlock(&pcf->lock);
83441 +
83442 +       return ret;
83443 +}
83444 +EXPORT_SYMBOL(pcf50633_reg_write);
83445 +
83446 +static int32_t __reg_read(struct pcf50633_data *pcf, u_int8_t reg)
83447 +{
83448 +       int32_t ret;
83449 +
83450 +       if (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND) {
83451 +               dev_err(&pcf->client->dev, "__reg_read while suspended\n");
83452 +               dump_stack();
83453 +       }
83454 +       ret = i2c_smbus_read_byte_data(pcf->client, reg);
83455 +
83456 +       return ret;
83457 +}
83458 +
83459 +u_int8_t pcf50633_reg_read(struct pcf50633_data *pcf, u_int8_t reg)
83460 +{
83461 +       int32_t ret;
83462 +
83463 +       mutex_lock(&pcf->lock);
83464 +       ret = __reg_read(pcf, reg);
83465 +       mutex_unlock(&pcf->lock);
83466 +
83467 +       return ret & 0xff;
83468 +}
83469 +EXPORT_SYMBOL(pcf50633_reg_read);
83470 +
83471 +int pcf50633_reg_set_bit_mask(struct pcf50633_data *pcf,
83472 +                           u_int8_t reg, u_int8_t mask, u_int8_t val)
83473 +{
83474 +       int ret;
83475 +       u_int8_t tmp;
83476 +
83477 +       val &= mask;
83478 +
83479 +       mutex_lock(&pcf->lock);
83480 +
83481 +       tmp = __reg_read(pcf, reg);
83482 +       tmp &= ~mask;
83483 +       tmp |= val;
83484 +       ret = __reg_write(pcf, reg, tmp);
83485 +
83486 +       mutex_unlock(&pcf->lock);
83487 +
83488 +       return ret;
83489 +}
83490 +EXPORT_SYMBOL(pcf50633_reg_set_bit_mask);
83491 +
83492 +int pcf50633_reg_clear_bits(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
83493 +{
83494 +       int ret;
83495 +       u_int8_t tmp;
83496 +
83497 +       mutex_lock(&pcf->lock);
83498 +
83499 +       tmp = __reg_read(pcf, reg);
83500 +       tmp &= ~val;
83501 +       ret = __reg_write(pcf, reg, tmp);
83502 +
83503 +       mutex_unlock(&pcf->lock);
83504 +
83505 +       return ret;
83506 +}
83507 +EXPORT_SYMBOL(pcf50633_reg_clear_bits);
83508 +
83509 +/* asynchronously setup reading one ADC channel */
83510 +static void async_adc_read_setup(struct pcf50633_data *pcf,
83511 +                                int channel, int avg)
83512 +{
83513 +       channel &= PCF50633_ADCC1_ADCMUX_MASK;
83514 +
83515 +       /* kill ratiometric, but enable ACCSW biasing */
83516 +       __reg_write(pcf, PCF50633_REG_ADCC2, 0x00);
83517 +       __reg_write(pcf, PCF50633_REG_ADCC3, 0x01);
83518 +
83519 +       /* start ADC conversion of selected channel */
83520 +       __reg_write(pcf, PCF50633_REG_ADCC1, channel | avg |
83521 +                   PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT);
83522 +
83523 +}
83524 +
83525 +static u_int16_t adc_read_result(struct pcf50633_data *pcf)
83526 +{
83527 +       u_int16_t ret = (__reg_read(pcf, PCF50633_REG_ADCS1) << 2) |
83528 +                       (__reg_read(pcf, PCF50633_REG_ADCS3) &
83529 +                                                 PCF50633_ADCS3_ADCDAT1L_MASK);
83530 +
83531 +       DEBUGPC("adc result = %d\n", ret);
83532 +
83533 +       return ret;
83534 +}
83535 +
83536 +/* go into 'STANDBY' mode, i.e. power off the main CPU and peripherals */
83537 +void pcf50633_go_standby(struct pcf50633_data *pcf)
83538 +{
83539 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
83540 +                 PCF50633_OOCSHDWN_GOSTDBY, PCF50633_OOCSHDWN_GOSTDBY);
83541 +}
83542 +EXPORT_SYMBOL_GPL(pcf50633_go_standby);
83543 +
83544 +void pcf50633_gpio_set(struct pcf50633_data *pcf, enum pcf50633_gpio gpio,
83545 +                       int on)
83546 +{
83547 +       u_int8_t reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
83548 +
83549 +       if (on)
83550 +               pcf50633_reg_set_bit_mask(pcf, reg, 0x0f, 0x07);
83551 +       else
83552 +               pcf50633_reg_set_bit_mask(pcf, reg, 0x0f, 0x00);
83553 +}
83554 +EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
83555 +
83556 +int pcf50633_gpio_get(struct pcf50633_data *pcf, enum pcf50633_gpio gpio)
83557 +{
83558 +       u_int8_t reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
83559 +       u_int8_t val = pcf50633_reg_read(pcf, reg) & 0x0f;
83560 +
83561 +       if (val == PCF50633_GPOCFG_GPOSEL_1 ||
83562 +           val == (PCF50633_GPOCFG_GPOSEL_0|PCF50633_GPOCFG_GPOSEL_INVERSE))
83563 +               return 1;
83564 +
83565 +       return 0;
83566 +}
83567 +EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
83568 +
83569 +static int interpret_charger_type_from_adc(struct pcf50633_data *pcf,
83570 +                                          int sample)
83571 +{
83572 +       /* 1A capable charger? */
83573 +
83574 +       if (sample < ((ADC_NOM_CHG_DETECT_NONE + ADC_NOM_CHG_DETECT_1A) / 2))
83575 +               return CHARGER_TYPE_1A;
83576 +
83577 +       /* well then, nothing in the USB hole, or USB host / unk adapter */
83578 +
83579 +       if (pcf->flags & PCF50633_F_USB_PRESENT) /* ooh power is in there */
83580 +               return CHARGER_TYPE_HOSTUSB; /* HOSTUSB is the catchall */
83581 +
83582 +       return CHARGER_TYPE_NONE; /* no really -- nothing in there */
83583 +}
83584 +
83585 +
83586 +
83587 +static void
83588 +configure_pmu_for_charger(struct pcf50633_data *pcf,
83589 +                                       void *unused, int adc_result_raw)
83590 +{
83591 +       int type;
83592 +
83593 +       type = interpret_charger_type_from_adc(
83594 +                                            pcf, adc_result_raw);
83595 +       switch (type) {
83596 +       case CHARGER_TYPE_NONE:
83597 +               pcf50633_usb_curlim_set(pcf, 0);
83598 +               break;
83599 +       /*
83600 +        * the PCF50633 has a feature that it will supply only excess current
83601 +        * from the charger that is not used to power the device.  So this
83602 +        * 500mA setting is "up to 500mA" according to that.
83603 +        */
83604 +       case CHARGER_TYPE_HOSTUSB:
83605 +               /* USB subsystem should call pcf50633_usb_curlim_set to set
83606 +                * what was negotiated with the host when it is enumerated
83607 +                * successfully.  If we get called again after a good
83608 +                * negotiation, we keep what was negotiated.  (Removal of
83609 +                * USB plug destroys pcf->last_curlim_set to 0)
83610 +                */
83611 +               if (pcf->last_curlim_set > 100)
83612 +                       pcf50633_usb_curlim_set(pcf, pcf->last_curlim_set);
83613 +               else
83614 +                       pcf50633_usb_curlim_set(pcf, 100);
83615 +               break;
83616 +       case CHARGER_TYPE_1A:
83617 +               pcf50633_usb_curlim_set(pcf, 1000);
83618 +               /*
83619 +                * stop GPO / EN_HOSTUSB power driving out on the same
83620 +                * USB power pins we have a 1A charger on right now!
83621 +                */
83622 +               dev_dbg(&pcf->client->dev, "Charger -> CHARGER_TYPE_1A\n");
83623 +               __reg_write(pcf, PCF50633_GPO - PCF50633_GPIO1 +
83624 +                                PCF50633_REG_GPIO1CFG,
83625 +                                __reg_read(pcf, PCF50633_GPO - PCF50633_GPIO1 +
83626 +                                                PCF50633_REG_GPIO1CFG) & 0xf0);
83627 +               break;
83628 +       }
83629 +
83630 +       /* max out USB fast charge current -- actual current drawn is
83631 +        * additionally limited by USB limit so no worries
83632 +        */
83633 +       __reg_write(pcf, PCF50633_REG_MBCC5, 0xff);
83634 +
83635 +}
83636 +
83637 +static void trigger_next_adc_job_if_any(struct pcf50633_data *pcf)
83638 +{
83639 +       if (pcf->adc_queue_head == pcf->adc_queue_tail)
83640 +               return;
83641 +       async_adc_read_setup(pcf,
83642 +                            pcf->adc_queue[pcf->adc_queue_tail]->mux,
83643 +                            pcf->adc_queue[pcf->adc_queue_tail]->avg);
83644 +}
83645 +
83646 +
83647 +static void
83648 +adc_add_request_to_queue(struct pcf50633_data *pcf, struct adc_request *req)
83649 +{
83650 +       int old_head = pcf->adc_queue_head;
83651 +       pcf->adc_queue[pcf->adc_queue_head] = req;
83652 +
83653 +       pcf->adc_queue_head = (pcf->adc_queue_head + 1) &
83654 +                             (MAX_ADC_FIFO_DEPTH - 1);
83655 +
83656 +       /* it was idle before we just added this?  we need to kick it then */
83657 +       if (old_head == pcf->adc_queue_tail)
83658 +               trigger_next_adc_job_if_any(pcf);
83659 +}
83660 +
83661 +static void
83662 +__pcf50633_adc_sync_read_callback(struct pcf50633_data *pcf, void *param, int result)
83663 +{
83664 +       struct adc_request *req;
83665 +
83666 +       /*We know here that the passed param is an adc_request object */
83667 +       req = (struct adc_request *)param;
83668 +
83669 +       req->result = result;
83670 +       complete(&req->completion);
83671 +}
83672 +
83673 +int pcf50633_adc_sync_read(struct pcf50633_data *pcf, int mux, int avg)
83674 +{
83675 +
83676 +       struct adc_request *req;
83677 +       int result;
83678 +
83679 +       /* req is freed when the result is ready, in pcf50633_work*/
83680 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
83681 +       if (!req)
83682 +               return -ENOMEM;
83683 +
83684 +       req->mux = mux;
83685 +       req->avg = avg;
83686 +       req->callback =  __pcf50633_adc_sync_read_callback;
83687 +       req->callback_param = req;
83688 +       init_completion(&req->completion);
83689 +
83690 +       adc_add_request_to_queue(pcf, req);
83691 +
83692 +       wait_for_completion(&req->completion);
83693 +       result = req->result;
83694 +
83695 +       return result;
83696 +}
83697 +
83698 +int pcf50633_adc_async_read(struct pcf50633_data *pcf, int mux, int avg,
83699 +                            void (*callback)(struct pcf50633_data *, void *,int),
83700 +                            void *callback_param)
83701 +{
83702 +       struct adc_request *req;
83703 +
83704 +       /* req is freed when the result is ready, in pcf50633_work*/
83705 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
83706 +       if (!req)
83707 +               return -ENOMEM;
83708 +
83709 +       req->mux = mux;
83710 +       req->avg = avg;
83711 +       req->callback = callback;
83712 +       req->callback_param = callback_param;
83713 +
83714 +       adc_add_request_to_queue(pcf, req);
83715 +
83716 +       return 0;
83717 +}
83718 +
83719 +/*
83720 + * we get run to handle servicing the async notification from USB stack that
83721 + * we got enumerated and allowed to draw a particular amount of current
83722 + */
83723 +
83724 +static void pcf50633_work_usbcurlim(struct work_struct *work)
83725 +{
83726 +       struct pcf50633_data *pcf =
83727 +                   container_of(work, struct pcf50633_data, work_usb_curlimit);
83728 +
83729 +       mutex_lock(&pcf->working_lock_usb_curlimit);
83730 +
83731 +       /* just can't cope with it if we are suspending, don't reschedule */
83732 +       if ((pcf->suspend_state == PCF50633_SS_STARTING_SUSPEND) ||
83733 +           (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND))
83734 +               goto bail;
83735 +
83736 +       dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim\n");
83737 +
83738 +       if (!pcf->probe_completed)
83739 +               goto reschedule;
83740 +
83741 +       /* we got a notification from USB stack before we completed resume...
83742 +        * that can only make trouble, reschedule for a retry
83743 +        */
83744 +       if (pcf->suspend_state &&
83745 +                    (pcf->suspend_state < PCF50633_SS_COMPLETED_RESUME))
83746 +               goto reschedule;
83747 +
83748 +       /*
83749 +        * did he pull USB before we managed to set the limit?
83750 +        */
83751 +       if (pcf->usb_removal_count_usb_curlimit != pcf->usb_removal_count)
83752 +               goto bail;
83753 +
83754 +       /* OK let's set the requested limit and finish */
83755 +
83756 +       dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim setting %dmA\n",
83757 +                                                        pcf->pending_curlimit);
83758 +       pcf50633_usb_curlim_set(pcf, pcf->pending_curlimit);
83759 +
83760 +bail:
83761 +       mutex_unlock(&pcf->working_lock_usb_curlimit);
83762 +       return;
83763 +
83764 +reschedule:
83765 +       dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim rescheduling\n");
83766 +       if (!schedule_work(&pcf->work_usb_curlimit))
83767 +               dev_err(&pcf->client->dev, "curlim reschedule work "
83768 +                                                           "already queued\n");
83769 +
83770 +       mutex_unlock(&pcf->working_lock_usb_curlimit);
83771 +       /* don't spew, delaying whatever else is happening */
83772 +       msleep(1);
83773 +}
83774 +
83775 +
83776 +/* this is an export to allow machine to set USB current limit according to
83777 + * notifications of USB stack about enumeration state.  We spawn a work
83778 + * function to handle the actual setting, because suspend / resume and such
83779 + * can be in a bad state since this gets called externally asychronous to
83780 + * anything else going on in pcf50633.
83781 + */
83782 +
83783 +int pcf50633_notify_usb_current_limit_change(struct pcf50633_data *pcf,
83784 +                                                               unsigned int ma)
83785 +{
83786 +       /* can happen if he calls before probe
83787 +        * have to bail with error since we can't even schedule the work
83788 +        */
83789 +       if (!pcf) {
83790 +               printk(KERN_ERR "pcf50633_notify_usb_current_limit called with NULL pcf\n");
83791 +               return -EBUSY;
83792 +       }
83793 +
83794 +       dev_dbg(&pcf->client->dev,
83795 +                "pcf50633_notify_usb_current_limit_change %dmA\n", ma);
83796 +
83797 +       /* prepare to detect USB power removal before we complete */
83798 +       pcf->usb_removal_count_usb_curlimit = pcf->usb_removal_count;
83799 +
83800 +       pcf->pending_curlimit = ma;
83801 +
83802 +       if (!schedule_work(&pcf->work_usb_curlimit))
83803 +               dev_err(&pcf->client->dev, "curlim work item already queued\n");
83804 +
83805 +       return 0;
83806 +}
83807 +EXPORT_SYMBOL_GPL(pcf50633_notify_usb_current_limit_change);
83808 +
83809 +
83810 +/* we are run when we see a NOBAT situation, because there is no interrupt
83811 + * source in pcf50633 that triggers on resuming charging.  It watches to see
83812 + * if charging resumes, it reassesses the charging source if it does.  If the
83813 + * USB power disappears, it is also a sign there must be a battery and it is
83814 + * NOT being charged, so it exits since the next move must be USB insertion for
83815 + * change of charger state
83816 + */
83817 +
83818 +static void pcf50633_work_nobat(struct work_struct *work)
83819 +{
83820 +       struct pcf50633_data *pcf =
83821 +                       container_of(work, struct pcf50633_data, work_nobat);
83822 +
83823 +       mutex_lock(&pcf->working_lock_nobat);
83824 +       pcf->working_nobat = 1;
83825 +       mutex_unlock(&pcf->working_lock_nobat);
83826 +
83827 +       while (1) {
83828 +               msleep(1000);
83829 +
83830 +               if (pcf->suspend_state != PCF50633_SS_RUNNING)
83831 +                       continue;
83832 +
83833 +               /* there's a battery in there now? */
83834 +               if (pcf50633_reg_read(pcf, PCF50633_REG_MBCS3) & 0x40) {
83835 +
83836 +                       pcf->jiffies_last_bat_ins = jiffies;
83837 +
83838 +                       /* figure out our charging stance */
83839 +                       (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83840 +                                                    PCF50633_ADCC1_AVERAGE_16,
83841 +                                                    configure_pmu_for_charger,
83842 +                                                    NULL);
83843 +                       goto bail;
83844 +               }
83845 +
83846 +               /* he pulled USB cable since we were started?  exit then */
83847 +               if (pcf->usb_removal_count_nobat != pcf->usb_removal_count)
83848 +                       goto bail;
83849 +       }
83850 +
83851 +bail:
83852 +       mutex_lock(&pcf->working_lock_nobat);
83853 +       pcf->working_nobat = 0;
83854 +       mutex_unlock(&pcf->working_lock_nobat);
83855 +}
83856 +
83857 +
83858 +static void pcf50633_work(struct work_struct *work)
83859 +{
83860 +       struct pcf50633_data *pcf =
83861 +                       container_of(work, struct pcf50633_data, work);
83862 +       u_int8_t pcfirq[5];
83863 +       int ret;
83864 +       int tail;
83865 +       struct adc_request *req;
83866 +
83867 +       mutex_lock(&pcf->working_lock);
83868 +       pcf->working = 1;
83869 +
83870 +       /* sanity */
83871 +       if (!&pcf->client->dev)
83872 +               goto bail;
83873 +
83874 +       /*
83875 +        * if we are presently suspending, we are not in a position to deal
83876 +        * with pcf50633 interrupts at all.
83877 +        *
83878 +        * Because we didn't clear the int pending registers, there will be
83879 +        * no edge / interrupt waiting for us when we wake.  But it is OK
83880 +        * because at the end of our resume, we call this workqueue function
83881 +        * gratuitously, clearing the pending register and re-enabling
83882 +        * servicing this interrupt.
83883 +        */
83884 +
83885 +       if ((pcf->suspend_state == PCF50633_SS_STARTING_SUSPEND) ||
83886 +           (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND))
83887 +               goto bail;
83888 +
83889 +       /*
83890 +        * If we are inside suspend -> resume completion time we don't attempt
83891 +        * service until we have fully resumed.  Although we could talk to the
83892 +        * device as soon as I2C is up, the regs in the device which we might
83893 +        * choose to modify as part of the service action have not been
83894 +        * reloaded with their pre-suspend states yet.  Therefore we will
83895 +        * defer our service if we are called like that until our resume has
83896 +        * completed.
83897 +        *
83898 +        * This shouldn't happen any more because we disable servicing this
83899 +        * interrupt in suspend and don't re-enable it until resume is
83900 +        * completed.
83901 +        */
83902 +
83903 +       if (pcf->suspend_state &&
83904 +               (pcf->suspend_state != PCF50633_SS_COMPLETED_RESUME))
83905 +               goto reschedule;
83906 +
83907 +       /* this is the case early in resume! Sanity check! */
83908 +       if (i2c_get_clientdata(pcf->client) == NULL)
83909 +               goto reschedule;
83910 +
83911 +       /*
83912 +       * datasheet says we have to read the five IRQ
83913 +       * status regs in one transaction
83914 +       */
83915 +       ret = pcf50633_read(pcf, PCF50633_REG_INT1,
83916 +                                               sizeof(pcfirq), pcfirq);
83917 +       if (ret != sizeof(pcfirq)) {
83918 +               dev_info(&pcf->client->dev,
83919 +                        "Oh crap PMU IRQ register read failed -- "
83920 +                        "retrying later %d\n", ret);
83921 +               /*
83922 +                * it shouldn't fail, we no longer attempt to use
83923 +                * I2C while it can be suspended.  But we don't have
83924 +                * much option but to retry if if it ever did fail,
83925 +                * because if we don't service the interrupt to clear
83926 +                * it, we will never see another PMU interrupt edge.
83927 +                */
83928 +               goto reschedule;
83929 +       }
83930 +
83931 +       /* hey did we just resume? (because we don't get here unless we are
83932 +        * running normally or the first call after resumption)
83933 +        */
83934 +
83935 +       if (pcf->suspend_state != PCF50633_SS_RUNNING) {
83936 +               /*
83937 +               * grab a copy of resume interrupt reasons
83938 +               * from pcf50633 POV
83939 +               */
83940 +               memcpy(pcf->pcfirq_resume, pcfirq, sizeof(pcf->pcfirq_resume));
83941 +
83942 +               /* pcf50633 resume is really really over now then */
83943 +               pcf->suspend_state = PCF50633_SS_RUNNING;
83944 +
83945 +               /* peek at the IRQ reason, if power button then set a flag
83946 +                * so that we do not signal the event to userspace
83947 +                */
83948 +               if (pcfirq[1] & (PCF50633_INT2_ONKEYF | PCF50633_INT2_ONKEYR)) {
83949 +                       pcf->suppress_onkey_events = 1;
83950 +                       DEBUGP("Wake by ONKEY, suppressing ONKEY event");
83951 +               } else {
83952 +                       pcf->suppress_onkey_events = 0;
83953 +               }
83954 +       }
83955 +
83956 +       if (!pcf->coldplug_done) {
83957 +               DEBUGP("PMU Coldplug init\n");
83958 +
83959 +               /* we used SECOND to kick ourselves started -- turn it off */
83960 +               pcfirq[0] &= ~PCF50633_INT1_SECOND;
83961 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_INT1M,
83962 +                                       PCF50633_INT1_SECOND,
83963 +                                       PCF50633_INT1_SECOND);
83964 +
83965 +               /* coldplug the USB if present */
83966 +               if ((__reg_read(pcf, PCF50633_REG_MBCS1) &
83967 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) ==
83968 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) {
83969 +                       DEBUGPC("COLD USBINS\n");
83970 +                       input_report_key(pcf->input_dev, KEY_POWER2, 1);
83971 +                       apm_queue_event(APM_POWER_STATUS_CHANGE);
83972 +                       pcf->flags |= PCF50633_F_USB_PRESENT;
83973 +                       if (pcf->pdata->cb)
83974 +                               pcf->pdata->cb(&pcf->client->dev,
83975 +                                       PCF50633_FEAT_MBC, PMU_EVT_USB_INSERT);
83976 +               }
83977 +
83978 +               /* figure out our initial charging stance */
83979 +               (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
83980 +                                             PCF50633_ADCC1_AVERAGE_16,
83981 +                                            configure_pmu_for_charger, NULL);
83982 +
83983 +               pcf->coldplug_done = 1;
83984 +       }
83985 +
83986 +       DEBUGP("INT1=0x%02x INT2=0x%02x INT3=0x%02x INT4=0x%02x INT5=0x%02x\n",
83987 +               pcfirq[0], pcfirq[1], pcfirq[2], pcfirq[3], pcfirq[4]);
83988 +
83989 +       if (pcfirq[0] & PCF50633_INT1_ADPINS) {
83990 +               /* Charger inserted */
83991 +               DEBUGPC("ADPINS ");
83992 +               input_report_key(pcf->input_dev, KEY_BATTERY, 1);
83993 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
83994 +               pcf->flags |= PCF50633_F_CHG_PRESENT;
83995 +               if (pcf->pdata->cb)
83996 +                       pcf->pdata->cb(&pcf->client->dev,
83997 +                                      PCF50633_FEAT_MBC, PMU_EVT_INSERT);
83998 +       }
83999 +       if (pcfirq[0] & PCF50633_INT1_ADPREM) {
84000 +               /* Charger removed */
84001 +               DEBUGPC("ADPREM ");
84002 +               input_report_key(pcf->input_dev, KEY_BATTERY, 0);
84003 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
84004 +               pcf->flags &= ~PCF50633_F_CHG_PRESENT;
84005 +               if (pcf->pdata->cb)
84006 +                       pcf->pdata->cb(&pcf->client->dev,
84007 +                                      PCF50633_FEAT_MBC, PMU_EVT_REMOVE);
84008 +       }
84009 +       if (pcfirq[0] & PCF50633_INT1_USBINS) {
84010 +               DEBUGPC("USBINS ");
84011 +               input_report_key(pcf->input_dev, KEY_POWER2, 1);
84012 +               apm_queue_event(APM_POWER_STATUS_CHANGE);
84013 +               pcf->flags |= PCF50633_F_USB_PRESENT;
84014 +               if (pcf->pdata->cb)
84015 +                       pcf->pdata->cb(&pcf->client->dev,
84016 +                                      PCF50633_FEAT_MBC, PMU_EVT_USB_INSERT);
84017 +               msleep(500); /* debounce, allow to see any ID resistor */
84018 +               /* completion irq will figure out our charging stance */
84019 +               (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
84020 +                                    PCF50633_ADCC1_AVERAGE_16,
84021 +                                    configure_pmu_for_charger, NULL);
84022 +       }
84023 +       if (pcfirq[0] & PCF50633_INT1_USBREM &&
84024 +                               !(pcfirq[0] & PCF50633_INT1_USBINS)) {
84025 +               /* the occurrence of USBINS and USBREM
84026 +                * should be exclusive in one schedule work
84027 +                */
84028 +               DEBUGPC("USBREM ");
84029 +
84030 +               pcf->usb_removal_count++;
84031 +
84032 +               /* only deal if we had understood it was in */
84033 +               if (pcf->flags & PCF50633_F_USB_PRESENT) {
84034 +                       input_report_key(pcf->input_dev, KEY_POWER2, 0);
84035 +                       apm_queue_event(APM_POWER_STATUS_CHANGE);
84036 +                       pcf->flags &= ~PCF50633_F_USB_PRESENT;
84037 +
84038 +                       if (pcf->pdata->cb)
84039 +                               pcf->pdata->cb(&pcf->client->dev,
84040 +                                       PCF50633_FEAT_MBC, PMU_EVT_USB_REMOVE);
84041 +
84042 +                       /* destroy any memory of grant of power from host */
84043 +                       pcf->last_curlim_set = 0;
84044 +
84045 +                       /* completion irq will figure out our charging stance */
84046 +                       (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
84047 +                                       PCF50633_ADCC1_AVERAGE_16,
84048 +                                       configure_pmu_for_charger, NULL);
84049 +               }
84050 +       }
84051 +       if (pcfirq[0] & PCF50633_INT1_ALARM) {
84052 +               DEBUGPC("ALARM ");
84053 +               if (pcf->pdata->used_features & PCF50633_FEAT_RTC)
84054 +                       pcf50633_rtc_handle_event(pcf,
84055 +                                       PCF50633_RTC_EVENT_ALARM);
84056 +       }
84057 +       if (pcfirq[0] & PCF50633_INT1_SECOND) {
84058 +               DEBUGPC("SECOND ");
84059 +               if (pcf->flags & PCF50633_F_RTC_SECOND)
84060 +                       pcf50633_rtc_handle_event(pcf,
84061 +                                       PCF50633_RTC_EVENT_SECOND);
84062 +
84063 +               if (pcf->onkey_seconds >= 0 &&
84064 +                   pcf->flags & PCF50633_F_PWR_PRESSED) {
84065 +                       DEBUGP("ONKEY_SECONDS(%u, OOCSTAT=0x%02x) ",
84066 +                               pcf->onkey_seconds,
84067 +                               pcf50633_reg_read(pcf, PCF50633_REG_OOCSTAT));
84068 +                       pcf->onkey_seconds++;
84069 +                       if (pcf->onkey_seconds >=
84070 +                           pcf->pdata->onkey_seconds_sig_init) {
84071 +                               /* Ask init to do 'ctrlaltdel' */
84072 +                               /*
84073 +                                * currently Linux reacts badly to issuing a
84074 +                                * signal to PID #1 before init is started.
84075 +                                * What happens is that the next kernel thread
84076 +                                * to start, which is the JFFS2 Garbage
84077 +                                * collector in our case, gets the signal
84078 +                                * instead and proceeds to fail to fork --
84079 +                                * which is very bad.  Therefore we confirm
84080 +                                * PID #1 exists before issuing the signal
84081 +                                */
84082 +                               if (find_task_by_pid_ns(1, &init_pid_ns)) {
84083 +                                       kill_pid(task_pid(find_task_by_pid_ns(1,
84084 +                                                       &init_pid_ns)), SIGPWR, 1);
84085 +                                       DEBUGPC("SIGINT(init) ");
84086 +                               }
84087 +                               /* FIXME: what if userspace doesn't shut down? */
84088 +                       }
84089 +                       if (pcf->onkey_seconds >=
84090 +                               pcf->pdata->onkey_seconds_shutdown) {
84091 +                               DEBUGPC("Power Off ");
84092 +                               pcf50633_go_standby(pcf);
84093 +                       }
84094 +               }
84095 +       }
84096 +
84097 +       if (pcfirq[1] & PCF50633_INT2_ONKEYF) {
84098 +               /* ONKEY falling edge (start of button press) */
84099 +               pcf->flags |= PCF50633_F_PWR_PRESSED;
84100 +               if (!pcf->suppress_onkey_events) {
84101 +                       DEBUGPC("ONKEYF ");
84102 +                       input_report_key(pcf->input_dev, KEY_POWER, 1);
84103 +               } else {
84104 +                       DEBUGPC("ONKEYF(unreported) ");
84105 +               }
84106 +       }
84107 +       if (pcfirq[1] & PCF50633_INT2_ONKEYR) {
84108 +               /* ONKEY rising edge (end of button press) */
84109 +               pcf->flags &= ~PCF50633_F_PWR_PRESSED;
84110 +               pcf->onkey_seconds = -1;
84111 +               if (!pcf->suppress_onkey_events) {
84112 +                       DEBUGPC("ONKEYR ");
84113 +                       input_report_key(pcf->input_dev, KEY_POWER, 0);
84114 +               } else {
84115 +                       DEBUGPC("ONKEYR(unreported) ");
84116 +                       /* don't suppress any more power button events */
84117 +                       pcf->suppress_onkey_events = 0;
84118 +               }
84119 +               /* disable SECOND interrupt in case RTC didn't
84120 +                * request it */
84121 +               if (!(pcf->flags & PCF50633_F_RTC_SECOND))
84122 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_INT1M,
84123 +                                        PCF50633_INT1_SECOND,
84124 +                                        PCF50633_INT1_SECOND);
84125 +       }
84126 +       /* FIXME: we don't use EXTON1/2/3. thats why we skip it */
84127 +
84128 +       if (pcfirq[2] & PCF50633_INT3_BATFULL) {
84129 +               DEBUGPC("BATFULL ");
84130 +
84131 +               /* the problem is, we get a false BATFULL if we inserted battery
84132 +                * while USB powered.  Defeat BATFULL if we recently inserted
84133 +                * battery
84134 +                */
84135 +
84136 +               if ((jiffies - pcf->jiffies_last_bat_ins) < (HZ * 2)) {
84137 +
84138 +                       DEBUGPC("*** Ignoring BATFULL ***\n");
84139 +
84140 +                       ret = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
84141 +                                       PCF56033_MBCC7_USB_MASK;
84142 +
84143 +
84144 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
84145 +                                        PCF56033_MBCC7_USB_MASK,
84146 +                                        PCF50633_MBCC7_USB_SUSPEND);
84147 +
84148 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
84149 +                                        PCF56033_MBCC7_USB_MASK,
84150 +                                        ret);
84151 +               } else {
84152 +                       if (pcf->pdata->cb)
84153 +                               pcf->pdata->cb(&pcf->client->dev,
84154 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
84155 +               }
84156 +
84157 +               /* FIXME: signal this to userspace */
84158 +       }
84159 +       if (pcfirq[2] & PCF50633_INT3_CHGHALT) {
84160 +               DEBUGPC("CHGHALT ");
84161 +               /*
84162 +                * this is really "battery not pulling current" -- it can
84163 +                * appear with no battery attached
84164 +                */
84165 +               if (pcf->pdata->cb)
84166 +                       pcf->pdata->cb(&pcf->client->dev,
84167 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
84168 +       }
84169 +       if (pcfirq[2] & PCF50633_INT3_THLIMON) {
84170 +               DEBUGPC("THLIMON ");
84171 +               pcf->flags |= PCF50633_F_CHG_PROT;
84172 +               if (pcf->pdata->cb)
84173 +                       pcf->pdata->cb(&pcf->client->dev,
84174 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
84175 +       }
84176 +       if (pcfirq[2] & PCF50633_INT3_THLIMOFF) {
84177 +               DEBUGPC("THLIMOFF ");
84178 +               pcf->flags &= ~PCF50633_F_CHG_PROT;
84179 +               if (pcf->pdata->cb)
84180 +                       pcf->pdata->cb(&pcf->client->dev,
84181 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
84182 +       }
84183 +       if (pcfirq[2] & PCF50633_INT3_USBLIMON) {
84184 +               DEBUGPC("USBLIMON ");
84185 +               if (pcf->pdata->cb)
84186 +                       pcf->pdata->cb(&pcf->client->dev,
84187 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
84188 +       }
84189 +       if (pcfirq[2] & PCF50633_INT3_USBLIMOFF) {
84190 +               DEBUGPC("USBLIMOFF ");
84191 +               if (pcf->pdata->cb)
84192 +                       pcf->pdata->cb(&pcf->client->dev,
84193 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
84194 +       }
84195 +       if (pcfirq[2] & PCF50633_INT3_ADCRDY) {
84196 +               /* ADC result ready */
84197 +               DEBUGPC("ADCRDY ");
84198 +               tail = pcf->adc_queue_tail;
84199 +               pcf->adc_queue_tail = (pcf->adc_queue_tail + 1) &
84200 +                                     (MAX_ADC_FIFO_DEPTH - 1);
84201 +               req = pcf->adc_queue[tail];
84202 +               req->callback(pcf, req->callback_param,
84203 +                                       adc_read_result(pcf));
84204 +               kfree(req);
84205 +
84206 +               trigger_next_adc_job_if_any(pcf);
84207 +       }
84208 +       if (pcfirq[2] & PCF50633_INT3_ONKEY1S) {
84209 +               /* ONKEY pressed for more than 1 second */
84210 +               pcf->onkey_seconds = 0;
84211 +               DEBUGPC("ONKEY1S ");
84212 +               /* Tell PMU we are taking care of this */
84213 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
84214 +                                PCF50633_OOCSHDWN_TOTRST,
84215 +                                PCF50633_OOCSHDWN_TOTRST);
84216 +               /* enable SECOND interrupt (hz tick) */
84217 +               pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, PCF50633_INT1_SECOND);
84218 +       }
84219 +
84220 +       if (pcfirq[3] & (PCF50633_INT4_LOWBAT|PCF50633_INT4_LOWSYS)) {
84221 +               if ((__reg_read(pcf, PCF50633_REG_MBCS1) &
84222 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) ==
84223 +                   (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) {
84224 +                       /*
84225 +                        * hey no need to freak out, we have some kind of
84226 +                        * valid charger power to keep us going -- but note that
84227 +                        * we are not actually charging anything
84228 +                        */
84229 +                       if (pcf->pdata->cb)
84230 +                               pcf->pdata->cb(&pcf->client->dev,
84231 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
84232 +
84233 +                       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
84234 +                                       PCF50633_MBCC1_RESUME,
84235 +                                       PCF50633_MBCC1_RESUME);
84236 +
84237 +                       /*
84238 +                        * Well, we are not charging anything right this second
84239 +                        * ... however in the next ~30s before we get the next
84240 +                        * NOBAT, he might insert a battery.  So we schedule a
84241 +                        * work function checking to see if
84242 +                        * we started charging something during that time.
84243 +                        * USB removal as well as charging terminates the work
84244 +                        * function so we can't get terminally confused
84245 +                        */
84246 +                       mutex_lock(&pcf->working_lock_nobat);
84247 +                       if (!pcf->working_nobat) {
84248 +                               pcf->usb_removal_count_nobat =
84249 +                                                       pcf->usb_removal_count;
84250 +
84251 +                               if (!schedule_work(&pcf->work_nobat))
84252 +                                       DEBUGPC("failed to schedule nobat\n");
84253 +                       }
84254 +                       mutex_unlock(&pcf->working_lock_nobat);
84255 +
84256 +
84257 +                       DEBUGPC("(NO)BAT ");
84258 +               } else {
84259 +                       /* Really low battery voltage, we have 8 seconds left */
84260 +                       DEBUGPC("LOWBAT ");
84261 +                       /*
84262 +                        * currently Linux reacts badly to issuing a signal to
84263 +                        * PID #1 before init is started.  What happens is that
84264 +                        * the next kernel thread to start, which is the JFFS2
84265 +                        * Garbage collector in our case, gets the signal
84266 +                        * instead and proceeds to fail to fork -- which is
84267 +                        * very bad.  Therefore we confirm PID #1 exists
84268 +                        * before issuing SPIGPWR
84269 +                        */
84270 +
84271 +                        if (find_task_by_pid_ns(1, &init_pid_ns)) {
84272 +                                apm_queue_event(APM_LOW_BATTERY);
84273 +                                DEBUGPC("SIGPWR(init) ");
84274 +                                kill_pid(task_pid(find_task_by_pid_ns(1, &init_pid_ns)), SIGPWR, 1);
84275 +                       } else
84276 +                               /*
84277 +                                * well, our situation is like this:  we do not
84278 +                                * have any external power, we have a low
84279 +                                * battery and since PID #1 doesn't exist yet,
84280 +                                * we are early in the boot, likely before
84281 +                                * rootfs mount.  We should just call it a day
84282 +                                */
84283 +                               apm_queue_event(APM_CRITICAL_SUSPEND);
84284 +               }
84285 +
84286 +               /* Tell PMU we are taking care of this */
84287 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
84288 +                                PCF50633_OOCSHDWN_TOTRST,
84289 +                                PCF50633_OOCSHDWN_TOTRST);
84290 +       }
84291 +       if (pcfirq[3] & PCF50633_INT4_HIGHTMP) {
84292 +               /* High temperature */
84293 +               DEBUGPC("HIGHTMP ");
84294 +               apm_queue_event(APM_CRITICAL_SUSPEND);
84295 +       }
84296 +       if (pcfirq[3] & PCF50633_INT4_AUTOPWRFAIL) {
84297 +               DEBUGPC("PCF50633_INT4_AUTOPWRFAIL ");
84298 +               /* FIXME: deal with this */
84299 +       }
84300 +       if (pcfirq[3] & PCF50633_INT4_DWN1PWRFAIL) {
84301 +               DEBUGPC("PCF50633_INT4_DWN1PWRFAIL ");
84302 +               /* FIXME: deal with this */
84303 +       }
84304 +       if (pcfirq[3] & PCF50633_INT4_DWN2PWRFAIL) {
84305 +               DEBUGPC("PCF50633_INT4_DWN2PWRFAIL ");
84306 +               /* FIXME: deal with this */
84307 +       }
84308 +       if (pcfirq[3] & PCF50633_INT4_LEDPWRFAIL) {
84309 +               DEBUGPC("PCF50633_INT4_LEDPWRFAIL ");
84310 +               /* FIXME: deal with this */
84311 +       }
84312 +       if (pcfirq[3] & PCF50633_INT4_LEDOVP) {
84313 +               DEBUGPC("PCF50633_INT4_LEDOVP ");
84314 +               /* FIXME: deal with this */
84315 +       }
84316 +
84317 +       DEBUGPC("\n");
84318 +
84319 +bail:
84320 +       pcf->working = 0;
84321 +       input_sync(pcf->input_dev);
84322 +       put_device(&pcf->client->dev);
84323 +       mutex_unlock(&pcf->working_lock);
84324 +
84325 +       return;
84326 +
84327 +reschedule:
84328 +       /* don't spew, delaying whatever else is happening */
84329 +       /* EXCEPTION: if we are in the middle of suspending, we don't have
84330 +        * time to hang around since we may be turned off core 1V3 already
84331 +        */
84332 +       if ((pcf->suspend_state != PCF50633_SS_STARTING_SUSPEND) &&
84333 +           (pcf->suspend_state != PCF50633_SS_COMPLETED_SUSPEND)) {
84334 +               msleep(10);
84335 +               dev_dbg(&pcf->client->dev, "rescheduling interrupt service\n");
84336 +       }
84337 +       if (!schedule_work(&pcf->work))
84338 +               dev_err(&pcf->client->dev, "int service reschedule failed\n");
84339 +
84340 +       /* we don't put the device here, hold it for next time */
84341 +       mutex_unlock(&pcf->working_lock);
84342 +}
84343 +
84344 +static irqreturn_t pcf50633_irq(int irq, void *_pcf)
84345 +{
84346 +       struct pcf50633_data *pcf = _pcf;
84347 +
84348 +       DEBUGP("entering(irq=%u, pcf=%p): scheduling work\n", irq, _pcf);
84349 +       dev_dbg(&pcf->client->dev, "pcf50633_irq scheduling work\n");
84350 +
84351 +       get_device(&pcf->client->dev);
84352 +       if (!schedule_work(&pcf->work) && !pcf->working)
84353 +               dev_err(&pcf->client->dev, "pcf irq work already queued\n");
84354 +
84355 +       return IRQ_HANDLED;
84356 +}
84357 +
84358 +static u_int16_t adc_to_batt_millivolts(u_int16_t adc)
84359 +{
84360 +       u_int16_t mvolts;
84361 +
84362 +       mvolts = (adc * 6000) / 1024;
84363 +
84364 +       return mvolts;
84365 +}
84366 +
84367 +#define BATTVOLT_SCALE_START 2800
84368 +#define BATTVOLT_SCALE_END 4200
84369 +#define BATTVOLT_SCALE_DIVIDER ((BATTVOLT_SCALE_END - BATTVOLT_SCALE_START)/100)
84370 +
84371 +static u_int8_t battvolt_scale(u_int16_t battvolt)
84372 +{
84373 +       /* FIXME: this linear scale is completely bogus */
84374 +       u_int16_t battvolt_relative = battvolt - BATTVOLT_SCALE_START;
84375 +       unsigned int percent = battvolt_relative / BATTVOLT_SCALE_DIVIDER;
84376 +
84377 +       return percent;
84378 +}
84379 +
84380 +u_int16_t pcf50633_battvolt(struct pcf50633_data *pcf)
84381 +{
84382 +       int ret;
84383 +
84384 +       ret = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_BATSNS_RES,
84385 +                                     PCF50633_ADCC1_AVERAGE_16);
84386 +
84387 +       if (ret < 0)
84388 +               return ret;
84389 +
84390 +       return adc_to_batt_millivolts(ret);
84391 +}
84392 +
84393 +EXPORT_SYMBOL_GPL(pcf50633_battvolt);
84394 +
84395 +static ssize_t show_battvolt(struct device *dev, struct device_attribute *attr,
84396 +                            char *buf)
84397 +{
84398 +       struct i2c_client *client = to_i2c_client(dev);
84399 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84400 +
84401 +       return sprintf(buf, "%u\n", pcf50633_battvolt(pcf));
84402 +}
84403 +static DEVICE_ATTR(battvolt, S_IRUGO | S_IWUSR, show_battvolt, NULL);
84404 +
84405 +/***********************************************************************
84406 + * Charger Control
84407 + ***********************************************************************/
84408 +
84409 +/* Set maximum USB current limit */
84410 +static void pcf50633_usb_curlim_set(struct pcf50633_data *pcf, int ma)
84411 +{
84412 +       u_int8_t bits;
84413 +       int active = 0;
84414 +
84415 +       pcf->last_curlim_set = ma;
84416 +
84417 +       dev_dbg(&pcf->client->dev, "setting usb current limit to %d ma", ma);
84418 +
84419 +       if (ma >= 1000) {
84420 +               bits = PCF50633_MBCC7_USB_1000mA;
84421 +       }
84422 +       else if (ma >= 500)
84423 +               bits = PCF50633_MBCC7_USB_500mA;
84424 +       else if (ma >= 100)
84425 +               bits = PCF50633_MBCC7_USB_100mA;
84426 +       else
84427 +               bits = PCF50633_MBCC7_USB_SUSPEND;
84428 +
84429 +       /* set the nearest charging limit */
84430 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7, PCF56033_MBCC7_USB_MASK,
84431 +                        bits);
84432 +
84433 +       /* with this charging limit, is charging actually meaningful? */
84434 +       switch (bits) {
84435 +       case PCF50633_MBCC7_USB_500mA:
84436 +       case PCF50633_MBCC7_USB_1000mA:
84437 +               /* yes with this charging limit, we can do real charging */
84438 +               active = 1;
84439 +               break;
84440 +       default: /* right charging context that if there is power, we charge */
84441 +               if (pcf->flags & PCF50633_F_USB_PRESENT)
84442 +                       pcf->pdata->cb(&pcf->client->dev,
84443 +                              PCF50633_FEAT_MBC, PMU_EVT_CHARGER_ACTIVE);
84444 +               break;
84445 +       }
84446 +       /*
84447 +        * enable or disable charging according to current limit -- this will
84448 +        * also throw a platform notification callback about it
84449 +        */
84450 +       pcf50633_charge_enable(pcf, active);
84451 +
84452 +       /* clear batfull */
84453 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
84454 +                               PCF50633_MBCC1_AUTORES,
84455 +                               0);
84456 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
84457 +                               PCF50633_MBCC1_RESUME,
84458 +                               PCF50633_MBCC1_RESUME);
84459 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
84460 +                               PCF50633_MBCC1_AUTORES,
84461 +                               PCF50633_MBCC1_AUTORES);
84462 +
84463 +}
84464 +
84465 +static ssize_t show_usblim(struct device *dev, struct device_attribute *attr,
84466 +                          char *buf)
84467 +{
84468 +       struct i2c_client *client = to_i2c_client(dev);
84469 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84470 +       u_int8_t usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
84471 +                                               PCF56033_MBCC7_USB_MASK;
84472 +       unsigned int ma;
84473 +
84474 +       if (usblim == PCF50633_MBCC7_USB_1000mA)
84475 +               ma = 1000;
84476 +       else if (usblim == PCF50633_MBCC7_USB_500mA)
84477 +               ma = 500;
84478 +       else if (usblim == PCF50633_MBCC7_USB_100mA)
84479 +               ma = 100;
84480 +       else
84481 +               ma = 0;
84482 +
84483 +       return sprintf(buf, "%u\n", ma);
84484 +}
84485 +static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, NULL);
84486 +
84487 +/* Enable/disable charging */
84488 +static void pcf50633_charge_enable(struct pcf50633_data *pcf, int on)
84489 +{
84490 +       u_int8_t bits;
84491 +       u_int8_t usblim;
84492 +
84493 +       if (!(pcf->pdata->used_features & PCF50633_FEAT_MBC))
84494 +               return;
84495 +
84496 +       DEBUGPC("pcf50633_charge_enable %d\n", on);
84497 +
84498 +       if (on) {
84499 +               pcf->flags |= PCF50633_F_CHG_ENABLED;
84500 +               bits = PCF50633_MBCC1_CHGENA;
84501 +               usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
84502 +                                                       PCF56033_MBCC7_USB_MASK;
84503 +               switch (usblim) {
84504 +               case PCF50633_MBCC7_USB_1000mA:
84505 +               case PCF50633_MBCC7_USB_500mA:
84506 +                       if (pcf->flags & PCF50633_F_USB_PRESENT)
84507 +                               if (pcf->pdata->cb)
84508 +                                       pcf->pdata->cb(&pcf->client->dev,
84509 +                                                      PCF50633_FEAT_MBC,
84510 +                                                      PMU_EVT_CHARGER_ACTIVE);
84511 +                       break;
84512 +               default:
84513 +                       break;
84514 +               }
84515 +       } else {
84516 +               pcf->flags &= ~PCF50633_F_CHG_ENABLED;
84517 +               bits = 0;
84518 +               if (pcf->pdata->cb)
84519 +                       pcf->pdata->cb(&pcf->client->dev,
84520 +                                      PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
84521 +       }
84522 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1, PCF50633_MBCC1_CHGENA,
84523 +                        bits);
84524 +}
84525 +
84526 +#if 0
84527 +#define ONE                    1000000
84528 +static u_int16_t adc_to_rntc(struct pcf50633_data *pcf, u_int16_t adc)
84529 +{
84530 +       u_int32_t r_batt = (adc * pcf->pdata->r_fix_batt) / (1023 - adc);
84531 +       u_int16_t r_ntc;
84532 +
84533 +       /* The battery NTC has a parallell 10kOhms resistor */
84534 +       r_ntc = ONE / ((ONE/r_batt) - (ONE/pcf->pdata->r_fix_batt_par));
84535 +
84536 +       return r_ntc;
84537 +}
84538 +#endif
84539 +static ssize_t show_battemp(struct device *dev, struct device_attribute *attr,
84540 +                           char *buf)
84541 +{
84542 +       return sprintf(buf, "\n");
84543 +}
84544 +static DEVICE_ATTR(battemp, S_IRUGO | S_IWUSR, show_battemp, NULL);
84545 +#if 0
84546 +static u_int16_t adc_to_chg_milliamps(struct pcf50633_data *pcf,
84547 +                                            u_int16_t adc_adcin1,
84548 +                                            u_int16_t adc_batvolt)
84549 +{
84550 +       u_int32_t res = ((adc_adcin1 - adc_batvolt) * 6000);
84551 +       return res / (pcf->pdata->r_sense_milli * 1024 / 1000);
84552 +}
84553 +#endif
84554 +static ssize_t show_chgcur(struct device *dev, struct device_attribute *attr,
84555 +                          char *buf)
84556 +{
84557 +       return sprintf(buf, "\n");
84558 +}
84559 +static DEVICE_ATTR(chgcur, S_IRUGO | S_IWUSR, show_chgcur, NULL);
84560 +
84561 +static const char *chgmode_names[] = {
84562 +       [PCF50633_MBCS2_MBC_PLAY]               = "play-only",
84563 +       [PCF50633_MBCS2_MBC_USB_PRE]            = "pre",
84564 +       [PCF50633_MBCS2_MBC_ADP_PRE]            = "pre",
84565 +       [PCF50633_MBCS2_MBC_USB_PRE_WAIT]       = "pre-wait",
84566 +       [PCF50633_MBCS2_MBC_ADP_PRE_WAIT]       = "pre-wait",
84567 +       [PCF50633_MBCS2_MBC_USB_FAST]           = "fast",
84568 +       [PCF50633_MBCS2_MBC_ADP_FAST]           = "fast",
84569 +       [PCF50633_MBCS2_MBC_USB_FAST_WAIT]      = "fast-wait",
84570 +       [PCF50633_MBCS2_MBC_ADP_FAST_WAIT]      = "fast-wait",
84571 +       [PCF50633_MBCS2_MBC_ADP_FAST_WAIT]      = "bat-full",
84572 +};
84573 +
84574 +static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
84575 +                           char *buf)
84576 +{
84577 +       struct i2c_client *client = to_i2c_client(dev);
84578 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84579 +       u_int8_t mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
84580 +       u_int8_t chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
84581 +
84582 +       return sprintf(buf, "%s\n", chgmode_names[chgmod]);
84583 +}
84584 +
84585 +static ssize_t set_chgmode(struct device *dev, struct device_attribute *attr,
84586 +                          const char *buf, size_t count)
84587 +{
84588 +       struct i2c_client *client = to_i2c_client(dev);
84589 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84590 +
84591 +       /* As opposed to the PCF50606, we can only enable or disable
84592 +        * charging and not directly jump into a certain mode! */
84593 +
84594 +       if (!strcmp(buf, "0\n"))
84595 +               pcf50633_charge_enable(pcf, 0);
84596 +       else
84597 +               pcf50633_charge_enable(pcf, 1);
84598 +
84599 +       return count;
84600 +}
84601 +
84602 +static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, set_chgmode);
84603 +
84604 +static const char *chgstate_names[] = {
84605 +       [PCF50633_FIDX_CHG_ENABLED]             = "enabled",
84606 +       [PCF50633_FIDX_CHG_PRESENT]             = "charger_present",
84607 +       [PCF50633_FIDX_USB_PRESENT]             = "usb_present",
84608 +       [PCF50633_FIDX_CHG_ERR]                 = "error",
84609 +       [PCF50633_FIDX_CHG_PROT]                = "protection",
84610 +       [PCF50633_FIDX_CHG_READY]               = "ready",
84611 +};
84612 +
84613 +static ssize_t show_chgstate(struct device *dev, struct device_attribute *attr,
84614 +                           char *buf)
84615 +{
84616 +       struct i2c_client *client = to_i2c_client(dev);
84617 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84618 +
84619 +       char *b = buf;
84620 +       int i;
84621 +
84622 +       for (i = 0; i < 32; i++)
84623 +               if (pcf->flags & (1 << i) && i < ARRAY_SIZE(chgstate_names))
84624 +                       b += sprintf(b, "%s ", chgstate_names[i]);
84625 +
84626 +       if (b > buf)
84627 +               b += sprintf(b, "\n");
84628 +
84629 +       return b - buf;
84630 +}
84631 +static DEVICE_ATTR(chgstate, S_IRUGO | S_IWUSR, show_chgstate, NULL);
84632 +
84633 +/*
84634 + * Charger type
84635 + */
84636 +
84637 +static ssize_t show_charger_type(struct device *dev,
84638 +                                struct device_attribute *attr, char *buf)
84639 +{
84640 +       struct i2c_client *client = to_i2c_client(dev);
84641 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84642 +       int adc_raw_result, charger_type;
84643 +
84644 +       static const char *names_charger_type[] = {
84645 +               [CHARGER_TYPE_NONE]     = "none",
84646 +               [CHARGER_TYPE_HOSTUSB]  = "host/500mA usb",
84647 +               [CHARGER_TYPE_1A]       = "charger 1A",
84648 +       };
84649 +       static const char *names_charger_modes[] = {
84650 +               [PCF50633_MBCC7_USB_1000mA]     = "1A",
84651 +               [PCF50633_MBCC7_USB_500mA]      = "500mA",
84652 +               [PCF50633_MBCC7_USB_100mA]      = "100mA",
84653 +               [PCF50633_MBCC7_USB_SUSPEND]    = "suspend",
84654 +       };
84655 +       int mode = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) & PCF56033_MBCC7_USB_MASK;
84656 +
84657 +       adc_raw_result = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
84658 +                                                    PCF50633_ADCC1_AVERAGE_16);
84659 +       charger_type = interpret_charger_type_from_adc(pcf, adc_raw_result);
84660 +       return sprintf(buf, "%s mode %s\n",
84661 +                           names_charger_type[charger_type],
84662 +                           names_charger_modes[mode]);
84663 +}
84664 +
84665 +static DEVICE_ATTR(charger_type, 0444, show_charger_type, NULL);
84666 +
84667 +static ssize_t force_usb_limit_dangerous(struct device *dev,
84668 +                  struct device_attribute *attr, const char *buf, size_t count)
84669 +{
84670 +       struct i2c_client *client = to_i2c_client(dev);
84671 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84672 +       int ma = simple_strtoul(buf, NULL, 10);
84673 +
84674 +       pcf50633_usb_curlim_set(pcf, ma);
84675 +       return count;
84676 +}
84677 +
84678 +static DEVICE_ATTR(force_usb_limit_dangerous, 0600,
84679 +                                              NULL, force_usb_limit_dangerous);
84680 +
84681 +/*
84682 + * Charger adc
84683 + */
84684 +
84685 +static ssize_t show_charger_adc(struct device *dev,
84686 +                               struct device_attribute *attr, char *buf)
84687 +{
84688 +       struct i2c_client *client = to_i2c_client(dev);
84689 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84690 +       int result;
84691 +
84692 +       result = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
84693 +                                            PCF50633_ADCC1_AVERAGE_16);
84694 +       if (result < 0)
84695 +               return result;
84696 +
84697 +       return sprintf(buf, "%d\n", result);
84698 +}
84699 +
84700 +static DEVICE_ATTR(charger_adc, 0444, show_charger_adc, NULL);
84701 +
84702 +/*
84703 + * Dump regs
84704 + */
84705 +
84706 +static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
84707 +                           char *buf)
84708 +{
84709 +       struct i2c_client *client = to_i2c_client(dev);
84710 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84711 +       u8 dump[16];
84712 +       int n, n1, idx = 0;
84713 +       char *buf1 = buf;
84714 +       static u8 address_no_read[] = { /* must be ascending */
84715 +               PCF50633_REG_INT1,
84716 +               PCF50633_REG_INT2,
84717 +               PCF50633_REG_INT3,
84718 +               PCF50633_REG_INT4,
84719 +               PCF50633_REG_INT5,
84720 +               0 /* terminator */
84721 +       };
84722 +
84723 +       for (n = 0; n < 256; n += sizeof(dump)) {
84724 +
84725 +               for (n1 = 0; n1 < sizeof(dump); n1++)
84726 +                       if (n == address_no_read[idx]) {
84727 +                               idx++;
84728 +                               dump[n1] = 0x00;
84729 +                       } else
84730 +                               dump[n1] = pcf50633_reg_read(pcf, n + n1);
84731 +
84732 +               hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
84733 +               buf1 += strlen(buf1);
84734 +               *buf1++ = '\n';
84735 +               *buf1 = '\0';
84736 +       }
84737 +
84738 +       return buf1 - buf;
84739 +}
84740 +
84741 +static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
84742 +
84743 +
84744 +/***********************************************************************
84745 + * Driver initialization
84746 + ***********************************************************************/
84747 +
84748 +/*
84749 + * CARE!  This table is modified at runtime!
84750 + */
84751 +static struct attribute *pcf_sysfs_entries[] = {
84752 +       &dev_attr_charger_type.attr,
84753 +       &dev_attr_force_usb_limit_dangerous.attr,
84754 +       &dev_attr_charger_adc.attr,
84755 +       &dev_attr_dump_regs.attr,
84756 +       NULL, /* going to add things at this point! */
84757 +       NULL,
84758 +       NULL,
84759 +       NULL,
84760 +       NULL,
84761 +       NULL,
84762 +       NULL,
84763 +};
84764 +
84765 +static struct attribute_group pcf_attr_group = {
84766 +       .name   = NULL,                 /* put in device directory */
84767 +       .attrs  = pcf_sysfs_entries,
84768 +};
84769 +
84770 +static void populate_sysfs_group(struct pcf50633_data *pcf)
84771 +{
84772 +       int i = 0;
84773 +       struct attribute **attr;
84774 +
84775 +       for (attr = pcf_sysfs_entries; *attr; attr++)
84776 +               i++;
84777 +
84778 +       if (pcf->pdata->used_features & PCF50633_FEAT_MBC) {
84779 +               pcf_sysfs_entries[i++] = &dev_attr_chgstate.attr;
84780 +               pcf_sysfs_entries[i++] = &dev_attr_chgmode.attr;
84781 +               pcf_sysfs_entries[i++] = &dev_attr_usb_curlim.attr;
84782 +       }
84783 +
84784 +       if (pcf->pdata->used_features & PCF50633_FEAT_CHGCUR)
84785 +               pcf_sysfs_entries[i++] = &dev_attr_chgcur.attr;
84786 +
84787 +       if (pcf->pdata->used_features & PCF50633_FEAT_BATVOLT)
84788 +               pcf_sysfs_entries[i++] = &dev_attr_battvolt.attr;
84789 +
84790 +       if (pcf->pdata->used_features & PCF50633_FEAT_BATTEMP)
84791 +               pcf_sysfs_entries[i++] = &dev_attr_battemp.attr;
84792 +
84793 +}
84794 +
84795 +static struct platform_device pcf50633_rtc_pdev = {
84796 +       .name   = "pcf50633-rtc",
84797 +       .id     = -1,
84798 +};
84799 +
84800 +static int pcf50633_probe(struct i2c_client *client, const struct i2c_device_id *ids)
84801 +{
84802 +       struct pcf50633_data *pcf;
84803 +       struct pcf50633_platform_data *pdata;
84804 +       int err = 0;
84805 +       int irq;
84806 +       int i;
84807 +
84808 +       DEBUGP("entering probe\n");
84809 +
84810 +       pdata = client->dev.platform_data;
84811 +
84812 +       pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
84813 +       if (!pcf)
84814 +               return -ENOMEM;
84815 +
84816 +       i2c_set_clientdata(client, pcf);
84817 +       irq = client->irq;
84818 +       mutex_init(&pcf->lock);
84819 +       mutex_init(&pcf->working_lock);
84820 +       mutex_init(&pcf->working_lock_nobat);
84821 +       mutex_init(&pcf->working_lock_usb_curlimit);
84822 +       INIT_WORK(&pcf->work, pcf50633_work);
84823 +       INIT_WORK(&pcf->work_nobat, pcf50633_work_nobat);
84824 +       INIT_WORK(&pcf->work_usb_curlimit, pcf50633_work_usbcurlim);
84825 +
84826 +       pcf->client = client;
84827 +       pcf->irq = irq;
84828 +       pcf->working = 0;
84829 +       pcf->suppress_onkey_events = 0;
84830 +       pcf->onkey_seconds = -1;
84831 +       pcf->pdata = pdata;
84832 +
84833 +       /* FIXME: now we try to detect the chip */
84834 +
84835 +       populate_sysfs_group(pcf);
84836 +
84837 +       err = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
84838 +       if (err) {
84839 +               dev_err(&client->dev, "error creating sysfs group\n");
84840 +               goto exit_free;
84841 +       }
84842 +
84843 +       /* create virtual charger 'device' */
84844 +
84845 +       /* register power off handler with core power management */
84846 +       /* FIXME : pm_power_off = &pcf50633_go_standby; */
84847 +
84848 +       pcf->input_dev = input_allocate_device();
84849 +       if (!pcf->input_dev)
84850 +               goto exit_sysfs;
84851 +
84852 +       pcf->input_dev->name = "GTA02 PMU events";
84853 +       pcf->input_dev->phys = "FIXME";
84854 +       pcf->input_dev->id.bustype = BUS_I2C;
84855 +
84856 +       pcf->input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
84857 +       set_bit(KEY_POWER, pcf->input_dev->keybit);
84858 +       set_bit(KEY_POWER2, pcf->input_dev->keybit);
84859 +       set_bit(KEY_BATTERY, pcf->input_dev->keybit);
84860 +
84861 +       err = input_register_device(pcf->input_dev);
84862 +       if (err)
84863 +               goto exit_sysfs;
84864 +
84865 +       /* configure interrupt mask */
84866 +
84867 +       /* we want SECOND to kick for the coldplug initialisation */
84868 +       pcf50633_reg_write(pcf, PCF50633_REG_INT1M, 0x00);
84869 +
84870 +       pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
84871 +       pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
84872 +       pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
84873 +       pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
84874 +
84875 +       /* force the backlight up, Qi does not do this for us */
84876 +
84877 +       /* pcf50633 manual p60
84878 +        * "led_out should never be set to 000000, as this would result
84879 +        * in a deadlock making it impossible to program another value.
84880 +        * If led_out should be inadvertently set to 000000, the
84881 +        * LEDOUT register can be reset by disabling and enabling the
84882 +        * LED converter via control bit led_on in the LEDENA register"
84883 +        */
84884 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
84885 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
84886 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
84887 +       pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x3f);
84888 +
84889 +       err = request_irq(irq, pcf50633_irq, IRQF_TRIGGER_FALLING,
84890 +                         "pcf50633", pcf);
84891 +       if (err < 0)
84892 +               goto exit_input;
84893 +
84894 +       if (enable_irq_wake(irq) < 0)
84895 +               dev_err(&client->dev, "IRQ %u cannot be enabled as wake-up"
84896 +                       "source in this hardware revision!\n", irq);
84897 +
84898 +       if (pcf->pdata->used_features & PCF50633_FEAT_RTC) {
84899 +               pcf50633_rtc_pdev.dev.platform_data = pcf;
84900 +
84901 +               err = platform_device_register(&pcf50633_rtc_pdev);
84902 +               if (err)
84903 +                       goto exit_irq;
84904 +       }
84905 +
84906 +       if (pcf->pdata->flag_use_apm_emulation)
84907 +               apm_get_power_status = NULL;
84908 +
84909 +       pdata->pcf = pcf;
84910 +
84911 +       /* Create platform regulator devices from the platform data */
84912 +       for (i = 0; i < __NUM_PCF50633_REGULATORS; i++) {
84913 +               struct platform_device *pdev;
84914 +
84915 +               pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
84916 +               /* FIXME : Handle failure */
84917 +
84918 +               pdev->name = "pcf50633-regltr";
84919 +               pdev->id = i;
84920 +               pdev->dev.parent = &client->dev;
84921 +               pdev->dev.platform_data = &pdata->reg_init_data[i];
84922 +               pdev->dev.driver_data = pcf;
84923 +               pcf->regulator_pdev[i] = pdev;
84924 +
84925 +               platform_device_register(pdev);
84926 +       }
84927 +
84928 +       pcf->probe_completed = 1;
84929 +
84930 +       /* if platform was interested, give him a chance to register
84931 +        * platform devices that switch power with us as the parent
84932 +        * at registration time -- ensures suspend / resume ordering
84933 +        */
84934 +       if (pcf->pdata->attach_child_devices)
84935 +               (pcf->pdata->attach_child_devices)(&client->dev);
84936 +
84937 +       dev_info(&client->dev, "probe completed\n");
84938 +
84939 +       return 0;
84940 +exit_irq:
84941 +       free_irq(pcf->irq, pcf);
84942 +exit_input:
84943 +       input_unregister_device(pcf->input_dev);
84944 +exit_sysfs:
84945 +       pm_power_off = NULL;
84946 +       sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
84947 +exit_free:
84948 +       kfree(pcf);
84949 +       return err;
84950 +}
84951 +
84952 +static int pcf50633_remove(struct i2c_client *client)
84953 +{
84954 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
84955 +
84956 +       DEBUGP("entering\n");
84957 +
84958 +       apm_get_power_status = NULL;
84959 +
84960 +       free_irq(pcf->irq, pcf);
84961 +
84962 +       input_unregister_device(pcf->input_dev);
84963 +
84964 +       if (pcf->pdata->used_features & PCF50633_FEAT_RTC)
84965 +               rtc_device_unregister(pcf->rtc);
84966 +
84967 +       sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
84968 +
84969 +       pm_power_off = NULL;
84970 +
84971 +       kfree(pcf);
84972 +
84973 +       return 0;
84974 +}
84975 +
84976 +/* you're going to need >300 bytes in buf */
84977 +
84978 +int pcf50633_report_resumers(struct pcf50633_data *pcf, char *buf)
84979 +{
84980 +       static char *int_names[] = {
84981 +               "adpins",
84982 +               "adprem",
84983 +               "usbins",
84984 +               "usbrem",
84985 +               NULL,
84986 +               NULL,
84987 +               "rtcalarm",
84988 +               "second",
84989 +
84990 +               "onkeyr",
84991 +               "onkeyf",
84992 +               "exton1r",
84993 +               "exton1f",
84994 +               "exton2r",
84995 +               "exton2f",
84996 +               "exton3r",
84997 +               "exton3f",
84998 +
84999 +               "batfull",
85000 +               "chghalt",
85001 +               "thlimon",
85002 +               "thlimoff",
85003 +               "usblimon",
85004 +               "usblimoff",
85005 +               "adcrdy",
85006 +               "onkey1s",
85007 +
85008 +               "lowsys",
85009 +               "lowbat",
85010 +               "hightmp",
85011 +               "autopwrfail",
85012 +               "dwn1pwrfail",
85013 +               "dwn2pwrfail",
85014 +               "ledpwrfail",
85015 +               "ledovp",
85016 +
85017 +               "ldo1pwrfail",
85018 +               "ldo2pwrfail",
85019 +               "ldo3pwrfail",
85020 +               "ldo4pwrfail",
85021 +               "ldo5pwrfail",
85022 +               "ldo6pwrfail",
85023 +               "hcidopwrfail",
85024 +               "hcidoovl"
85025 +       };
85026 +       char *end = buf;
85027 +       int n;
85028 +
85029 +       for (n = 0; n < ARRAY_SIZE(int_names); n++)
85030 +               if (int_names[n]) {
85031 +                       if (pcf->pcfirq_resume[n >> 3] & (1 >> (n & 7)))
85032 +                               end += sprintf(end, "  * %s\n", int_names[n]);
85033 +                       else
85034 +                               end += sprintf(end, "    %s\n", int_names[n]);
85035 +               }
85036 +
85037 +       return end - buf;
85038 +}
85039 +
85040 +
85041 +#ifdef CONFIG_PM
85042 +
85043 +static int pcf50633_suspend(struct device *dev, pm_message_t state)
85044 +{
85045 +       struct i2c_client *client = to_i2c_client(dev);
85046 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
85047 +       int i;
85048 +       int ret;
85049 +       u_int8_t res[5];
85050 +
85051 +       dev_err(dev, "pcf50633_suspend\n");
85052 +
85053 +       /* we suspend once (!) as late as possible in the suspend sequencing */
85054 +
85055 +       if ((state.event != PM_EVENT_SUSPEND) ||
85056 +           (pcf->suspend_state != PCF50633_SS_RUNNING))
85057 +               return -EBUSY;
85058 +
85059 +       /* The general idea is to power down all unused power supplies,
85060 +        * and then mask all PCF50633 interrupt sources but EXTONR, ONKEYF
85061 +        * and ALARM */
85062 +
85063 +       mutex_lock(&pcf->lock);
85064 +
85065 +       pcf->suspend_state = PCF50633_SS_STARTING_SUSPEND;
85066 +
85067 +       /* we are not going to service any further interrupts until we
85068 +        * resume.  If the IRQ workqueue is still pending in the background,
85069 +        * it will bail when it sees we set suspend state above
85070 +        */
85071 +
85072 +       disable_irq(pcf->irq);
85073 +
85074 +       /* set interrupt masks so only those sources we want to wake
85075 +        * us are able to
85076 +        */
85077 +       for (i = 0; i < 5; i++)
85078 +               res[i] = ~pcf->pdata->resumers[i];
85079 +
85080 +       ret = pcf50633_write(pcf, PCF50633_REG_INT1M, 5, &res[0]);
85081 +       if (ret)
85082 +               dev_err(dev, "Failed to set wake masks :-( %d\n", ret);
85083 +
85084 +       pcf->suspend_state = PCF50633_SS_COMPLETED_SUSPEND;
85085 +
85086 +       mutex_unlock(&pcf->lock);
85087 +
85088 +       return 0;
85089 +}
85090 +
85091 +
85092 +int pcf50633_ready(struct pcf50633_data *pcf)
85093 +{
85094 +       if (!pcf)
85095 +               return -EACCES;
85096 +
85097 +       /* this was seen during boot with Qi, mmc_rescan racing us */
85098 +       if (!pcf->probe_completed)
85099 +               return -EACCES;
85100 +
85101 +       if ((pcf->suspend_state != PCF50633_SS_RUNNING) &&
85102 +           (pcf->suspend_state < PCF50633_SS_COMPLETED_RESUME))
85103 +               return -EBUSY;
85104 +
85105 +       return 0;
85106 +}
85107 +EXPORT_SYMBOL_GPL(pcf50633_ready);
85108 +
85109 +int pcf50633_wait_for_ready(struct pcf50633_data *pcf, int timeout_ms,
85110 +                                                               char *name)
85111 +{
85112 +       /* so we always go once */
85113 +       timeout_ms += 5;
85114 +
85115 +       while ((timeout_ms >= 5) && (pcf50633_ready(pcf))) {
85116 +               timeout_ms -= 5; /* well, it isn't very accurate, but OK */
85117 +               msleep(5);
85118 +       }
85119 +
85120 +       if (timeout_ms < 5) {
85121 +               printk(KERN_ERR"pcf50633_wait_for_ready: "
85122 +                                       "%s BAILING on timeout\n", name);
85123 +               return -EBUSY;
85124 +       }
85125 +
85126 +       return 0;
85127 +}
85128 +EXPORT_SYMBOL_GPL(pcf50633_wait_for_ready);
85129 +
85130 +static int pcf50633_resume(struct device *dev)
85131 +{
85132 +       struct i2c_client *client = to_i2c_client(dev);
85133 +       struct pcf50633_data *pcf = i2c_get_clientdata(client);
85134 +       int ret;
85135 +       u8 res[5];
85136 +
85137 +       dev_dbg(dev, "pcf50633_resume suspended on entry = %d\n",
85138 +                                                (int)pcf->suspend_state);
85139 +       mutex_lock(&pcf->lock);
85140 +
85141 +       pcf->suspend_state = PCF50633_SS_STARTING_RESUME;
85142 +
85143 +       memset(res, 0, sizeof(res));
85144 +       /* not interested in second on resume */
85145 +       res[0] = PCF50633_INT1_SECOND;
85146 +       ret = pcf50633_write(pcf, PCF50633_REG_INT1M, 5, &res[0]);
85147 +       if (ret)
85148 +               dev_err(dev, "Failed to set int masks :-( %d\n", ret);
85149 +
85150 +       pcf->suspend_state = PCF50633_SS_COMPLETED_RESUME;
85151 +
85152 +       enable_irq(pcf->irq);
85153 +
85154 +       mutex_unlock(&pcf->lock);
85155 +
85156 +       /* gratuitous call to PCF work function, in the case that the PCF
85157 +        * interrupt edge was missed during resume, this forces the pending
85158 +        * register clear and lifts the interrupt back high again.  In the
85159 +        * case nothing is waiting for service, no harm done.
85160 +        */
85161 +
85162 +       get_device(&pcf->client->dev);
85163 +       pcf50633_work(&pcf->work);
85164 +
85165 +       return 0;
85166 +}
85167 +#else
85168 +#define pcf50633_suspend NULL
85169 +#define pcf50633_resume NULL
85170 +#endif
85171 +
85172 +static struct i2c_device_id pcf50633_id_table[] = {
85173 +       {"pcf50633", 0x73},
85174 +};
85175 +
85176 +static struct i2c_driver pcf50633_driver = {
85177 +       .driver = {
85178 +               .name   = "pcf50633",
85179 +               .suspend= pcf50633_suspend,
85180 +               .resume = pcf50633_resume,
85181 +       },
85182 +       .id_table = pcf50633_id_table,
85183 +       .probe = pcf50633_probe,
85184 +       .remove = pcf50633_remove,
85185 +};
85186 +
85187 +static int __init pcf50633_init(void)
85188 +{
85189 +       return i2c_add_driver(&pcf50633_driver);
85190 +}
85191 +
85192 +static void pcf50633_exit(void)
85193 +{
85194 +       i2c_del_driver(&pcf50633_driver);
85195 +}
85196 +
85197 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 power management unit");
85198 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
85199 +MODULE_LICENSE("GPL");
85200 +
85201 +module_init(pcf50633_init);
85202 +module_exit(pcf50633_exit);
85203 Index: linux-2.6.28/drivers/i2c/i2c-core.c
85204 ===================================================================
85205 --- linux-2.6.28.orig/drivers/i2c/i2c-core.c    2008-12-25 00:26:37.000000000 +0100
85206 +++ linux-2.6.28/drivers/i2c/i2c-core.c 2009-01-02 00:01:56.000000000 +0100
85207 @@ -1,4 +1,3 @@
85208 -/* i2c-core.c - a device driver for the iic-bus interface                   */
85209  /* ------------------------------------------------------------------------- */
85210  /*   Copyright (C) 1995-99 Simon G. Vogl
85211
85212 @@ -158,10 +157,16 @@ static int i2c_device_suspend(struct dev
85213
85214         if (!dev->driver)
85215                 return 0;
85216 +#if 0
85217         driver = to_i2c_driver(dev->driver);
85218         if (!driver->suspend)
85219                 return 0;
85220         return driver->suspend(to_i2c_client(dev), mesg);
85221 +#else
85222 +       if (!dev->driver->suspend)
85223 +               return 0;
85224 +       return dev->driver->suspend(dev, mesg);
85225 +#endif
85226  }
85227
85228  static int i2c_device_resume(struct device * dev)
85229 @@ -170,10 +175,16 @@ static int i2c_device_resume(struct devi
85230
85231         if (!dev->driver)
85232                 return 0;
85233 +#if 0
85234         driver = to_i2c_driver(dev->driver);
85235         if (!driver->resume)
85236                 return 0;
85237         return driver->resume(to_i2c_client(dev));
85238 +#else
85239 +       if (!dev->driver->resume)
85240 +               return 0;
85241 +       return dev->driver->resume(dev);
85242 +#endif
85243  }
85244
85245  static void i2c_client_release(struct device *dev)
85246 @@ -1129,11 +1140,11 @@ static int i2c_probe_address(struct i2c_
85247         int err;
85248
85249         /* Make sure the address is valid */
85250 -       if (addr < 0x03 || addr > 0x77) {
85251 +       /*if (addr < 0x03 || addr > 0x77) {
85252                 dev_warn(&adapter->dev, "Invalid probe address 0x%02x\n",
85253                          addr);
85254                 return -EINVAL;
85255 -       }
85256 +       }*/
85257
85258         /* Skip if already in use */
85259         if (i2c_check_addr(adapter, addr))
85260 Index: linux-2.6.28/drivers/input/keyboard/gpio_keys.c
85261 ===================================================================
85262 --- linux-2.6.28.orig/drivers/input/keyboard/gpio_keys.c        2008-12-25 00:26:37.000000000 +0100
85263 +++ linux-2.6.28/drivers/input/keyboard/gpio_keys.c     2009-01-02 00:01:56.000000000 +0100
85264 @@ -23,7 +23,7 @@
85265  #include <linux/input.h>
85266  #include <linux/gpio_keys.h>
85267
85268 -#include <asm/gpio.h>
85269 +#include <mach/gpio.h>
85270
85271  struct gpio_button_data {
85272         struct gpio_keys_button *button;
85273 Index: linux-2.6.28/drivers/input/keyboard/Kconfig
85274 ===================================================================
85275 --- linux-2.6.28.orig/drivers/input/keyboard/Kconfig    2008-12-25 00:26:37.000000000 +0100
85276 +++ linux-2.6.28/drivers/input/keyboard/Kconfig 2009-01-02 00:01:56.000000000 +0100
85277 @@ -323,4 +323,21 @@ config KEYBOARD_SH_KEYSC
85278
85279           To compile this driver as a module, choose M here: the
85280           module will be called sh_keysc.
85281 +config KEYBOARD_NEO1973
85282 +       tristate "FIC Neo1973 buttons"
85283 +       depends on MACH_NEO1973
85284 +       default y
85285 +       help
85286 +         Say Y here to enable the buttons on the FIC Neo1973
85287 +         GSM phone.
85288 +
85289 +         To compile this driver as a module, choose M here: the
85290 +         module will be called neo1973kbd.
85291 +
85292 +config KEYBOARD_QT2410
85293 +       tristate "QT2410 buttons"
85294 +       depends on MACH_QT2410
85295 +       default y
85296 +
85297 +
85298  endif
85299 Index: linux-2.6.28/drivers/input/keyboard/Makefile
85300 ===================================================================
85301 --- linux-2.6.28.orig/drivers/input/keyboard/Makefile   2008-12-25 00:26:37.000000000 +0100
85302 +++ linux-2.6.28/drivers/input/keyboard/Makefile        2009-01-02 00:01:56.000000000 +0100
85303 @@ -14,6 +14,8 @@ obj-$(CONFIG_KEYBOARD_LOCOMO)         += locomo
85304  obj-$(CONFIG_KEYBOARD_NEWTON)          += newtonkbd.o
85305  obj-$(CONFIG_KEYBOARD_STOWAWAY)                += stowaway.o
85306  obj-$(CONFIG_KEYBOARD_CORGI)           += corgikbd.o
85307 +obj-$(CONFIG_KEYBOARD_NEO1973)         += neo1973kbd.o
85308 +obj-$(CONFIG_KEYBOARD_QT2410)          += qt2410kbd.o
85309  obj-$(CONFIG_KEYBOARD_SPITZ)           += spitzkbd.o
85310  obj-$(CONFIG_KEYBOARD_TOSA)            += tosakbd.o
85311  obj-$(CONFIG_KEYBOARD_HIL)             += hil_kbd.o
85312 Index: linux-2.6.28/drivers/input/keyboard/neo1973kbd.c
85313 ===================================================================
85314 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
85315 +++ linux-2.6.28/drivers/input/keyboard/neo1973kbd.c    2009-01-02 00:01:56.000000000 +0100
85316 @@ -0,0 +1,465 @@
85317 +/*
85318 + * Keyboard driver for FIC Neo1973 GSM phone
85319 + *
85320 + * (C) 2006-2007 by Openmoko, Inc.
85321 + * Author: Harald Welte <laforge@openmoko.org>
85322 + * All rights reserved.
85323 + *
85324 + * inspired by corkgbd.c by Richard Purdie
85325 + *
85326 + * This program is free software; you can redistribute it and/or modify
85327 + * it under the terms of the GNU General Public License version 2 as
85328 + * published by the Free Software Foundation.
85329 + *
85330 + */
85331 +
85332 +#include <linux/delay.h>
85333 +#include <linux/platform_device.h>
85334 +#include <linux/init.h>
85335 +#include <linux/input.h>
85336 +#include <linux/interrupt.h>
85337 +#include <linux/jiffies.h>
85338 +#include <linux/module.h>
85339 +#include <linux/slab.h>
85340 +#include <linux/workqueue.h>
85341 +
85342 +#include <mach/gpio.h>
85343 +#include <asm/mach-types.h>
85344 +
85345 +extern int global_inside_suspend;
85346 +
85347 +struct neo1973kbd {
85348 +       struct platform_device *pdev;
85349 +       struct input_dev *input;
85350 +       struct device *cdev;
85351 +       struct work_struct work;
85352 +       int aux_state;
85353 +       int work_in_progress;
85354 +       int hp_irq_count_in_work;
85355 +       int hp_irq_count;
85356 +       int jack_irq;
85357 +};
85358 +
85359 +static struct class *neo1973kbd_switch_class;
85360 +
85361 +enum keys {
85362 +       NEO1973_KEY_AUX,    /* GTA01 / 02 only */
85363 +       NEO1973_KEY_HOLD,
85364 +       NEO1973_KEY_JACK,
85365 +       NEO1973_KEY_PLUS,   /* GTA03 only */
85366 +       NEO1973_KEY_MINUS,  /* GTA03 only */
85367 +};
85368 +
85369 +struct neo1973kbd_key {
85370 +       const char * name;
85371 +       irqreturn_t (*isr)(int irq, void *dev_id);
85372 +       int irq;
85373 +       int input_key;
85374 +};
85375 +
85376 +static irqreturn_t neo1973kbd_aux_irq(int irq, void *dev_id);
85377 +static irqreturn_t neo1973kbd_headphone_irq(int irq, void *dev_id);
85378 +static irqreturn_t neo1973kbd_default_key_irq(int irq, void *dev_id);
85379 +
85380 +
85381 +static struct neo1973kbd_key keys[] = {
85382 +       [NEO1973_KEY_AUX] = {
85383 +               .name = "Neo1973 AUX button",
85384 +               .isr = neo1973kbd_aux_irq,
85385 +               .input_key = KEY_PHONE,
85386 +       },
85387 +       [NEO1973_KEY_HOLD] = {
85388 +               .name = "Neo1973 HOLD button",
85389 +               .isr = neo1973kbd_default_key_irq,
85390 +               .input_key = KEY_PAUSE,
85391 +       },
85392 +       [NEO1973_KEY_JACK] = {
85393 +               .name = "Neo1973 Headphone jack",
85394 +               .isr = neo1973kbd_headphone_irq,
85395 +       },
85396 +       [NEO1973_KEY_PLUS] = {
85397 +               .name = "GTA03 PLUS button",
85398 +               .isr = neo1973kbd_default_key_irq,
85399 +               .input_key = KEY_KPPLUS,
85400 +       },
85401 +       [NEO1973_KEY_MINUS] = {
85402 +               .name = "GTA03 MINUS button",
85403 +               .isr = neo1973kbd_default_key_irq,
85404 +               .input_key = KEY_KPMINUS,
85405 +       },
85406 +};
85407 +
85408 +/* This timer section filters AUX button IRQ bouncing */
85409 +
85410 +static void aux_key_timer_f(unsigned long data);
85411 +
85412 +static struct timer_list aux_key_timer =
85413 +               TIMER_INITIALIZER(aux_key_timer_f, 0, 0);
85414 +
85415 +#define AUX_TIMER_TIMEOUT (HZ >> 7)
85416 +#define AUX_TIMER_ALLOWED_NOOP 2
85417 +#define AUX_TIMER_CONSECUTIVE_EVENTS 5
85418 +
85419 +struct neo1973kbd *timer_kbd;
85420 +
85421 +static void aux_key_timer_f(unsigned long data)
85422 +{
85423 +       static int noop_counter;
85424 +       static int last_key = -1;
85425 +       static int last_count;
85426 +       int key_pressed;
85427 +
85428 +       key_pressed =
85429 +           !gpio_get_value(timer_kbd->pdev->resource[NEO1973_KEY_AUX].start);
85430 +       if (machine_is_neo1973_gta02())
85431 +               key_pressed = !key_pressed;
85432 +
85433 +       if (likely(key_pressed == last_key))
85434 +               last_count++;
85435 +       else {
85436 +               last_count = 1;
85437 +               last_key = key_pressed;
85438 +       }
85439 +
85440 +       if (unlikely(last_count >= AUX_TIMER_CONSECUTIVE_EVENTS)) {
85441 +               if (timer_kbd->aux_state != last_key) {
85442 +                       input_report_key(timer_kbd->input, KEY_PHONE, last_key);
85443 +                       input_sync(timer_kbd->input);
85444 +
85445 +                       timer_kbd->aux_state = last_key;
85446 +                       noop_counter = 0;
85447 +               }
85448 +               last_count = 0;
85449 +               if (unlikely(++noop_counter > AUX_TIMER_ALLOWED_NOOP)) {
85450 +                       noop_counter = 0;
85451 +                       return;
85452 +               }
85453 +       }
85454 +
85455 +       mod_timer(&aux_key_timer, jiffies + AUX_TIMER_TIMEOUT);
85456 +}
85457 +
85458 +static irqreturn_t neo1973kbd_aux_irq(int irq, void *dev)
85459 +{
85460 +       int *p = NULL;
85461 +
85462 +       /* if you stall inside resume then AUX will force a panic,
85463 +          which in turn forces a dump of the pending syslog */
85464 +
85465 +       if (global_inside_suspend)
85466 +               printk(KERN_ERR "death %d\n", *p);
85467 +
85468 +       mod_timer(&aux_key_timer, jiffies + AUX_TIMER_TIMEOUT);
85469 +
85470 +       return IRQ_HANDLED;
85471 +}
85472 +
85473 +static irqreturn_t neo1973kbd_default_key_irq(int irq, void *dev_id)
85474 +{
85475 +       struct neo1973kbd *kbd = dev_id;
85476 +       int n;
85477 +
85478 +       for (n = 0; n < ARRAY_SIZE(keys); n++) {
85479 +
85480 +               if (irq != keys[n].irq)
85481 +                       continue;
85482 +
85483 +               input_report_key(kbd->input, keys[n].input_key,
85484 +                                 gpio_get_value(kbd->pdev->resource[n].start));
85485 +               input_sync(kbd->input);
85486 +       }
85487 +
85488 +       return IRQ_HANDLED;
85489 +}
85490 +
85491 +
85492 +static const char *event_array_jack[2][4] = {
85493 +       [0] = {
85494 +               "SWITCH_NAME=headset",
85495 +               "SWITCH_STATE=0",
85496 +               "EVENT=remove",
85497 +               NULL
85498 +       },
85499 +       [1] = {
85500 +               "SWITCH_NAME=headset",
85501 +               "SWITCH_STATE=1",
85502 +               "EVENT=insert",
85503 +               NULL
85504 +       },
85505 +};
85506 +
85507 +static void neo1973kbd_jack_event(struct device *dev, int num)
85508 +{
85509 +       kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, (char **)event_array_jack[!!num]);
85510 +}
85511 +
85512 +
85513 +static void neo1973kbd_debounce_jack(struct work_struct *work)
85514 +{
85515 +       struct neo1973kbd *kbd = container_of(work, struct neo1973kbd, work);
85516 +       unsigned long flags;
85517 +       int loop = 0;
85518 +       int level;
85519 +
85520 +       do {
85521 +               /*
85522 +                * we wait out any multiple interrupt
85523 +                * stuttering in 100ms lumps
85524 +                */
85525 +               do {
85526 +                       kbd->hp_irq_count_in_work = kbd->hp_irq_count;
85527 +                       msleep(100);
85528 +               } while (kbd->hp_irq_count != kbd->hp_irq_count_in_work);
85529 +               /*
85530 +                * no new interrupts on jack for 100ms...
85531 +                * ok we will report it
85532 +                */
85533 +               level = gpio_get_value(kbd->pdev->resource[NEO1973_KEY_JACK].start);
85534 +               input_report_switch(kbd->input, SW_HEADPHONE_INSERT, level);
85535 +               input_sync(kbd->input);
85536 +               neo1973kbd_jack_event(kbd->cdev, level);
85537 +               /*
85538 +                * we go around the outer loop again if we detect that more
85539 +                * interrupts came while we are servicing here.  But we have
85540 +                * to sequence it carefully with interrupts off
85541 +                */
85542 +               local_save_flags(flags);
85543 +               /* no interrupts during this work means we can exit the work */
85544 +               loop = !!(kbd->hp_irq_count != kbd->hp_irq_count_in_work);
85545 +               if (!loop)
85546 +                       kbd->work_in_progress = 0;
85547 +               local_irq_restore(flags);
85548 +               /*
85549 +                * interrupt that comes here will either queue a new work action
85550 +                * since work_in_progress is cleared now, or be dealt with
85551 +                * when we loop.
85552 +                */
85553 +       } while (loop);
85554 +}
85555 +
85556 +
85557 +static irqreturn_t neo1973kbd_headphone_irq(int irq, void *dev_id)
85558 +{
85559 +       struct neo1973kbd *neo1973kbd_data = dev_id;
85560 +
85561 +       /*
85562 +        * this interrupt is prone to bouncing and userspace doesn't like
85563 +        * to have to deal with that kind of thing.  So we do not accept
85564 +        * that a jack interrupt is equal to a jack event.  Instead we fire
85565 +        * some work on the first interrupt, and it hangs about in 100ms units
85566 +        * until no more interrupts come.  Then it accepts the state it finds
85567 +        * for jack insert and reports it once
85568 +        */
85569 +
85570 +       neo1973kbd_data->hp_irq_count++;
85571 +       /*
85572 +        * the first interrupt we see for a while, we fire the work item
85573 +        * and record the interrupt count when we did that.  If more interrupts
85574 +        * come in the meanwhile, we can tell by the difference in that
85575 +        * stored count and hp_irq_count which increments every interrupt
85576 +        */
85577 +       if (!neo1973kbd_data->work_in_progress) {
85578 +               neo1973kbd_data->jack_irq = irq;
85579 +               neo1973kbd_data->hp_irq_count_in_work =
85580 +                                               neo1973kbd_data->hp_irq_count;
85581 +               if (!schedule_work(&neo1973kbd_data->work))
85582 +                       printk(KERN_ERR
85583 +                               "Unable to schedule headphone debounce\n");
85584 +               else
85585 +                       neo1973kbd_data->work_in_progress = 1;
85586 +       }
85587 +
85588 +       return IRQ_HANDLED;
85589 +}
85590 +
85591 +#ifdef CONFIG_PM
85592 +static int neo1973kbd_suspend(struct platform_device *dev, pm_message_t state)
85593 +{
85594 +       return 0;
85595 +}
85596 +
85597 +static int neo1973kbd_resume(struct platform_device *dev)
85598 +{
85599 +       return 0;
85600 +}
85601 +#else
85602 +#define neo1973kbd_suspend     NULL
85603 +#define neo1973kbd_resume      NULL
85604 +#endif
85605 +
85606 +static ssize_t neo1973kbd_switch_name_show(struct device *dev,
85607 +                       struct device_attribute *attr, char *buf)
85608 +{
85609 +       return sprintf(buf, "%s\n", "neo1973 Headset Jack");
85610 +}
85611 +
85612 +static ssize_t neo1973kbd_switch_state_show(struct device *dev,
85613 +                       struct device_attribute *attr, char *buf)
85614 +{
85615 +       struct neo1973kbd *kbd = dev_get_drvdata(dev);
85616 +       return sprintf(buf, "%d\n",
85617 +                  gpio_get_value(kbd->pdev->resource[NEO1973_KEY_JACK].start));
85618 +}
85619 +
85620 +static DEVICE_ATTR(name, S_IRUGO , neo1973kbd_switch_name_show, NULL);
85621 +static DEVICE_ATTR(state, S_IRUGO , neo1973kbd_switch_state_show, NULL);
85622 +
85623 +static int neo1973kbd_probe(struct platform_device *pdev)
85624 +{
85625 +       struct neo1973kbd *neo1973kbd;
85626 +       struct input_dev *input_dev;
85627 +       int rc;
85628 +       int irq;
85629 +       int n;
85630 +
85631 +       neo1973kbd = kzalloc(sizeof(struct neo1973kbd), GFP_KERNEL);
85632 +       input_dev = input_allocate_device();
85633 +       if (!neo1973kbd || !input_dev) {
85634 +               kfree(neo1973kbd);
85635 +               input_free_device(input_dev);
85636 +               return -ENOMEM;
85637 +       }
85638 +
85639 +       neo1973kbd->pdev = pdev;
85640 +       timer_kbd = neo1973kbd;
85641 +
85642 +       if (pdev->resource[0].flags != 0)
85643 +               return -EINVAL;
85644 +
85645 +       platform_set_drvdata(pdev, neo1973kbd);
85646 +
85647 +       neo1973kbd->input = input_dev;
85648 +
85649 +       INIT_WORK(&neo1973kbd->work, neo1973kbd_debounce_jack);
85650 +
85651 +       input_dev->name = "Neo1973 Buttons";
85652 +       input_dev->phys = "neo1973kbd/input0";
85653 +       input_dev->id.bustype = BUS_HOST;
85654 +       input_dev->id.vendor = 0x0001;
85655 +       input_dev->id.product = 0x0001;
85656 +       input_dev->id.version = 0x0100;
85657 +       input_dev->dev.parent = &pdev->dev;
85658 +
85659 +       input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_SW);
85660 +       set_bit(SW_HEADPHONE_INSERT, input_dev->swbit);
85661 +       set_bit(KEY_PHONE, input_dev->keybit);
85662 +       set_bit(KEY_PAUSE, input_dev->keybit);
85663 +
85664 +       rc = input_register_device(neo1973kbd->input);
85665 +       if (rc)
85666 +               goto out_register;
85667 +
85668 +       neo1973kbd->cdev = device_create(neo1973kbd_switch_class,
85669 +                                         &pdev->dev, 0, neo1973kbd, "headset");
85670 +       if (unlikely(IS_ERR(neo1973kbd->cdev))) {
85671 +               rc = PTR_ERR(neo1973kbd->cdev);
85672 +               goto out_device_create;
85673 +       }
85674 +
85675 +       rc = device_create_file(neo1973kbd->cdev, &dev_attr_name);
85676 +       if(rc)
85677 +               goto out_device_create_file;
85678 +
85679 +       rc = device_create_file(neo1973kbd->cdev, &dev_attr_state);
85680 +       if(rc)
85681 +               goto out_device_create_file;
85682 +
85683 +       /* register GPIO IRQs */
85684 +
85685 +       for(n = 0; n < ARRAY_SIZE(keys); n++) {
85686 +
85687 +               if (!pdev->resource[0].start)
85688 +                       continue;
85689 +
85690 +               irq = gpio_to_irq(pdev->resource[n].start);
85691 +               if (irq < 0)
85692 +                       continue;
85693 +
85694 +               if (request_irq(irq, keys[n].isr, IRQF_DISABLED |
85695 +                               IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
85696 +                               keys[n].name, neo1973kbd)) {
85697 +                       dev_err(&pdev->dev, "Can't get IRQ %u\n", irq);
85698 +
85699 +                       /* unwind any irq registrations and fail */
85700 +
85701 +                       while (n > 0) {
85702 +                               n--;
85703 +                               free_irq(gpio_to_irq(pdev->resource[n].start),
85704 +                                                                   neo1973kbd);
85705 +                       }
85706 +                       goto out_device_create_file;
85707 +               }
85708 +
85709 +               keys[n].irq = irq;
85710 +       }
85711 +
85712 +       /*
85713 +        * GTA01 revisions before Bv4 can't be resumed by the PMU, so we use
85714 +        * resume by AUX.
85715 +        */
85716 +       if (machine_is_neo1973_gta01())
85717 +               enable_irq_wake(keys[NEO1973_KEY_AUX].irq);
85718 +
85719 +       enable_irq_wake(keys[NEO1973_KEY_JACK].irq);
85720 +
85721 +       return 0;
85722 +
85723 +out_device_create_file:
85724 +       device_unregister(neo1973kbd->cdev);
85725 +out_device_create:
85726 +       input_unregister_device(neo1973kbd->input);
85727 +out_register:
85728 +       input_free_device(neo1973kbd->input);
85729 +       platform_set_drvdata(pdev, NULL);
85730 +       kfree(neo1973kbd);
85731 +
85732 +       return -ENODEV;
85733 +}
85734 +
85735 +static int neo1973kbd_remove(struct platform_device *pdev)
85736 +{
85737 +       struct neo1973kbd *neo1973kbd = platform_get_drvdata(pdev);
85738 +
85739 +       free_irq(gpio_to_irq(pdev->resource[2].start), neo1973kbd);
85740 +       free_irq(gpio_to_irq(pdev->resource[1].start), neo1973kbd);
85741 +       free_irq(gpio_to_irq(pdev->resource[0].start), neo1973kbd);
85742 +
85743 +       device_unregister(neo1973kbd->cdev);
85744 +       input_unregister_device(neo1973kbd->input);
85745 +       input_free_device(neo1973kbd->input);
85746 +       platform_set_drvdata(pdev, NULL);
85747 +       kfree(neo1973kbd);
85748 +
85749 +       return 0;
85750 +}
85751 +
85752 +static struct platform_driver neo1973kbd_driver = {
85753 +       .probe          = neo1973kbd_probe,
85754 +       .remove         = neo1973kbd_remove,
85755 +       .suspend        = neo1973kbd_suspend,
85756 +       .resume         = neo1973kbd_resume,
85757 +       .driver         = {
85758 +               .name   = "neo1973-button",
85759 +       },
85760 +};
85761 +
85762 +static int __devinit neo1973kbd_init(void)
85763 +{
85764 +       neo1973kbd_switch_class = class_create(THIS_MODULE, "switch");
85765 +       if (IS_ERR(neo1973kbd_switch_class))
85766 +               return PTR_ERR(neo1973kbd_switch_class);
85767 +       return platform_driver_register(&neo1973kbd_driver);
85768 +}
85769 +
85770 +static void __exit neo1973kbd_exit(void)
85771 +{
85772 +       platform_driver_unregister(&neo1973kbd_driver);
85773 +       class_destroy(neo1973kbd_switch_class);
85774 +}
85775 +
85776 +module_init(neo1973kbd_init);
85777 +module_exit(neo1973kbd_exit);
85778 +
85779 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
85780 +MODULE_DESCRIPTION("FIC Neo1973 buttons input driver");
85781 +MODULE_LICENSE("GPL");
85782 Index: linux-2.6.28/drivers/input/keyboard/qt2410kbd.c
85783 ===================================================================
85784 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
85785 +++ linux-2.6.28/drivers/input/keyboard/qt2410kbd.c     2009-01-02 00:01:56.000000000 +0100
85786 @@ -0,0 +1,231 @@
85787 +/*
85788 + * Keyboard driver for Armzone QT2410
85789 + *
85790 + * (C) 2006 by Openmoko, Inc.
85791 + * Author: Harald Welte <laforge@openmoko.org>
85792 + * All rights reserved.
85793 + *
85794 + * This program is free software; you can redistribute it and/or modify
85795 + * it under the terms of the GNU General Public License version 2 as
85796 + * published by the Free Software Foundation.
85797 + *
85798 + */
85799 +
85800 +#include <linux/delay.h>
85801 +#include <linux/platform_device.h>
85802 +#include <linux/init.h>
85803 +#include <linux/input.h>
85804 +#include <linux/interrupt.h>
85805 +#include <linux/jiffies.h>
85806 +#include <linux/module.h>
85807 +#include <linux/slab.h>
85808 +
85809 +#include <mach/hardware.h>
85810 +#include <mach/gta01.h>
85811 +
85812 +struct gta01kbd {
85813 +       struct input_dev *input;
85814 +       unsigned int suspended;
85815 +       unsigned long suspend_jiffies;
85816 +};
85817 +
85818 +static irqreturn_t gta01kbd_interrupt(int irq, void *dev_id)
85819 +{
85820 +       struct gta01kbd *gta01kbd_data = dev_id;
85821 +
85822 +       /* FIXME: use GPIO from platform_dev resources */
85823 +       if (s3c2410_gpio_getpin(S3C2410_GPF0))
85824 +               input_report_key(gta01kbd_data->input, KEY_PHONE, 1);
85825 +       else
85826 +               input_report_key(gta01kbd_data->input, KEY_PHONE, 0);
85827 +
85828 +       input_sync(gta01kbd_data->input);
85829 +
85830 +       return IRQ_HANDLED;
85831 +}
85832 +
85833 +
85834 +#ifdef CONFIG_PM
85835 +static int gta01kbd_suspend(struct platform_device *dev, pm_message_t state)
85836 +{
85837 +       struct gta01kbd *gta01kbd = platform_get_drvdata(dev);
85838 +
85839 +       gta01kbd->suspended = 1;
85840 +
85841 +       return 0;
85842 +}
85843 +
85844 +static int gta01kbd_resume(struct platform_device *dev)
85845 +{
85846 +       struct gta01kbd *gta01kbd = platform_get_drvdata(dev);
85847 +
85848 +       gta01kbd->suspended = 0;
85849 +
85850 +       return 0;
85851 +}
85852 +#else
85853 +#define gta01kbd_suspend       NULL
85854 +#define gta01kbd_resume                NULL
85855 +#endif
85856 +
85857 +static int gta01kbd_probe(struct platform_device *pdev)
85858 +{
85859 +       struct gta01kbd *gta01kbd;
85860 +       struct input_dev *input_dev;
85861 +       int irq_911;
85862 +       int rc = 0;
85863 +
85864 +       gta01kbd = kzalloc(sizeof(struct gta01kbd), GFP_KERNEL);
85865 +       if (!gta01kbd) {
85866 +               rc = -ENOMEM;
85867 +               goto bail;
85868 +       }
85869 +       input_dev = input_allocate_device();
85870 +       if (!gta01kbd || !input_dev) {
85871 +               rc = -ENOMEM;
85872 +               goto bail_free;
85873 +       }
85874 +
85875 +       if (pdev->resource[0].flags != 0) {\
85876 +               rc = -EINVAL;
85877 +               goto bail_free_dev;
85878 +       }
85879 +
85880 +       irq_911 = s3c2410_gpio_getirq(pdev->resource[0].start);
85881 +       if (irq_911 < 0) {
85882 +               rc = -EINVAL;
85883 +               goto bail_free_dev;
85884 +       }
85885 +
85886 +       platform_set_drvdata(pdev, gta01kbd);
85887 +
85888 +       gta01kbd->input = input_dev;
85889 +
85890 +#if 0
85891 +       spin_lock_init(&gta01kbd->lock);
85892 +       /* Init Keyboard rescan timer */
85893 +       init_timer(&corgikbd->timer);
85894 +       corgikbd->timer.function = corgikbd_timer_callback;
85895 +       corgikbd->timer.data = (unsigned long) corgikbd;
85896 +
85897 +       /* Init Hinge Timer */
85898 +       init_timer(&corgikbd->htimer);
85899 +       corgikbd->htimer.function = corgikbd_hinge_timer;
85900 +       corgikbd->htimer.data = (unsigned long) corgikbd;
85901 +
85902 +       corgikbd->suspend_jiffies=jiffies;
85903 +
85904 +       memcpy(corgikbd->keycode, corgikbd_keycode, sizeof(corgikbd->keycode));
85905 +#endif
85906 +
85907 +       input_dev->name = "QT2410 Buttons";
85908 +       input_dev->phys = "qt2410kbd/input0";
85909 +       input_dev->id.bustype = BUS_HOST;
85910 +       input_dev->id.vendor = 0x0001;
85911 +       input_dev->id.product = 0x0001;
85912 +       input_dev->id.version = 0x0100;
85913 +
85914 +       input_dev->evbit[0] = BIT(EV_KEY);
85915 +#if 0
85916 +       input_dev->keycode = gta01kbd->keycode;
85917 +       input_dev->keycodesize = sizeof(unsigned char);
85918 +       input_dev->keycodemax = ARRAY_SIZE(corgikbd_keycode);
85919 +
85920 +       for (i = 0; i < ARRAY_SIZE(corgikbd_keycode); i++)
85921 +               set_bit(corgikbd->keycode[i], input_dev->keybit);
85922 +       clear_bit(0, input_dev->keybit);
85923 +       set_bit(SW_LID, input_dev->swbit);
85924 +       set_bit(SW_TABLET_MODE, input_dev->swbit);
85925 +       set_bit(SW_HEADPHONE_INSERT, input_dev->swbit);
85926 +#endif
85927 +
85928 +       rc = input_register_device(gta01kbd->input);
85929 +       if (rc)
85930 +               goto bail_free_dev;
85931 +
85932 +       s3c2410_gpio_cfgpin(S3C2410_GPF0, S3C2410_GPF0_EINT0);
85933 +       if (request_irq(irq_911, gta01kbd_interrupt,
85934 +                       IRQF_DISABLED | IRQF_TRIGGER_RISING |
85935 +                       IRQF_TRIGGER_FALLING, "qt2410kbd_eint0", gta01kbd))
85936 +               printk(KERN_WARNING "gta01kbd: Can't get IRQ\n");
85937 +       enable_irq_wake(irq_911);
85938 +
85939 +       /* FIXME: headphone insert */
85940 +
85941 +#if 0
85942 +       mod_timer(&corgikbd->htimer, jiffies + msecs_to_jiffies(HINGE_SCAN_INTERVAL));
85943 +
85944 +       /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */
85945 +       for (i = 0; i < CORGI_KEY_SENSE_NUM; i++) {
85946 +               pxa_gpio_mode(CORGI_GPIO_KEY_SENSE(i) | GPIO_IN);
85947 +               if (request_irq(CORGI_IRQ_GPIO_KEY_SENSE(i), corgikbd_interrupt,
85948 +                               SA_INTERRUPT | SA_TRIGGER_RISING,
85949 +                               "corgikbd", corgikbd))
85950 +                       printk(KERN_WARNING "corgikbd: Can't get IRQ: %d!\n", i);
85951 +       }
85952 +
85953 +       /* Set Strobe lines as outputs - set high */
85954 +       for (i = 0; i < CORGI_KEY_STROBE_NUM; i++)
85955 +               pxa_gpio_mode(CORGI_GPIO_KEY_STROBE(i) | GPIO_OUT | GPIO_DFLT_HIGH);
85956 +
85957 +       /* Setup the headphone jack as an input */
85958 +       pxa_gpio_mode(CORGI_GPIO_AK_INT | GPIO_IN);
85959 +#endif
85960 +
85961 +       return 0;
85962 +
85963 +bail_free_dev:
85964 +       input_free_device(input_dev);
85965 +bail_free:
85966 +       kfree(gta01kbd);
85967 +bail:
85968 +       return rc;
85969 +}
85970 +
85971 +static int gta01kbd_remove(struct platform_device *pdev)
85972 +{
85973 +       struct gta01kbd *gta01kbd = platform_get_drvdata(pdev);
85974 +
85975 +       free_irq(s3c2410_gpio_getirq(pdev->resource[0].start), gta01kbd);
85976 +#if 0
85977 +       int i;
85978 +
85979 +       for (i = 0; i < CORGI_KEY_SENSE_NUM; i++)
85980 +               free_irq(CORGI_IRQ_GPIO_KEY_SENSE(i), corgikbd);
85981 +
85982 +       del_timer_sync(&corgikbd->htimer);
85983 +       del_timer_sync(&corgikbd->timer);
85984 +#endif
85985 +       input_unregister_device(gta01kbd->input);
85986 +
85987 +       kfree(gta01kbd);
85988 +
85989 +       return 0;
85990 +}
85991 +
85992 +static struct platform_driver gta01kbd_driver = {
85993 +       .probe          = gta01kbd_probe,
85994 +       .remove         = gta01kbd_remove,
85995 +       .suspend        = gta01kbd_suspend,
85996 +       .resume         = gta01kbd_resume,
85997 +       .driver         = {
85998 +               .name   = "qt2410-button",
85999 +       },
86000 +};
86001 +
86002 +static int __devinit gta01kbd_init(void)
86003 +{
86004 +       return platform_driver_register(&gta01kbd_driver);
86005 +}
86006 +
86007 +static void __exit gta01kbd_exit(void)
86008 +{
86009 +       platform_driver_unregister(&gta01kbd_driver);
86010 +}
86011 +
86012 +module_init(gta01kbd_init);
86013 +module_exit(gta01kbd_exit);
86014 +
86015 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
86016 +MODULE_DESCRIPTION("Armzone QT2410 Buttons Driver");
86017 +MODULE_LICENSE("GPL");
86018 Index: linux-2.6.28/drivers/input/misc/Kconfig
86019 ===================================================================
86020 --- linux-2.6.28.orig/drivers/input/misc/Kconfig        2009-01-02 00:00:02.000000000 +0100
86021 +++ linux-2.6.28/drivers/input/misc/Kconfig     2009-01-02 00:01:56.000000000 +0100
86022 @@ -236,4 +236,25 @@ config INPUT_GPIO_BUTTONS
86023           To compile this driver as a module, choose M here: the
86024           module will be called gpio-buttons.
86025
86026 +config INPUT_LIS302DL
86027 +       tristate "STmicro LIS302DL 3-axis accelerometer"
86028 +       depends on SPI_MASTER
86029 +       help
86030 +         SPI driver for the STmicro LIS302DL 3-axis accelerometer.
86031 +
86032 +         The userspece interface is a 3-axis (X/Y/Z) relative movement
86033 +         Linux input device, reporting REL_[XYZ] events.
86034 +
86035 +config INPUT_PCF50633_PMU
86036 +       tristate "PCF50633 PMU events"
86037 +       depends on MFD_PCF50633
86038 +       help
86039 +        Say Y to include support for input events on NXP PCF50633.
86040 +
86041 +config INPUT_PCF50606_PMU
86042 +       tristate "PCF50606 PMU events"
86043 +       depends on MFD_PCF50606
86044 +       help
86045 +        Say Y to include support for input events on NXP PCF50606.
86046 +
86047  endif
86048 Index: linux-2.6.28/drivers/input/misc/lis302dl.c
86049 ===================================================================
86050 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
86051 +++ linux-2.6.28/drivers/input/misc/lis302dl.c  2009-01-02 00:01:56.000000000 +0100
86052 @@ -0,0 +1,874 @@
86053 +/* Linux kernel driver for the ST LIS302D 3-axis accelerometer
86054 + *
86055 + * Copyright (C) 2007-2008 by Openmoko, Inc.
86056 + * Author: Harald Welte <laforge@openmoko.org>
86057 + *         converted to private bitbang by:
86058 + *         Andy Green <andy@openmoko.com>
86059 + *         ability to set acceleration threshold added by:
86060 + *         Simon Kagstrom <simon.kagstrom@gmail.com>
86061 + * All rights reserved.
86062 + *
86063 + * This program is free software; you can redistribute it and/or
86064 + * modify it under the terms of the GNU General Public License as
86065 + * published by the Free Software Foundation; either version 2 of
86066 + * the License, or (at your option) any later version.
86067 + *
86068 + * This program is distributed in the hope that it will be useful,
86069 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
86070 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
86071 + * GNU General Public License for more details.
86072 + *
86073 + * You should have received a copy of the GNU General Public License
86074 + * along with this program; if not, write to the Free Software
86075 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
86076 + * MA 02111-1307 USA
86077 + *
86078 + * TODO
86079 + *     * statistics for overflow events
86080 + *     * configuration interface (sysfs) for
86081 + *             * enable/disable x/y/z axis data ready
86082 + *             * enable/disable resume from freee fall / click
86083 + *             * free fall / click parameters
86084 + *             * high pass filter parameters
86085 + */
86086 +#include <linux/kernel.h>
86087 +#include <linux/types.h>
86088 +#include <linux/module.h>
86089 +#include <linux/device.h>
86090 +#include <linux/platform_device.h>
86091 +#include <linux/delay.h>
86092 +#include <linux/irq.h>
86093 +#include <linux/interrupt.h>
86094 +#include <linux/sysfs.h>
86095 +
86096 +#include <linux/lis302dl.h>
86097 +
86098 +/* Utility functions */
86099 +static u8 __reg_read(struct lis302dl_info *lis, u8 reg)
86100 +{
86101 +       return (lis->pdata->lis302dl_bitbang_reg_read)(lis, reg);
86102 +}
86103 +
86104 +static void __reg_write(struct lis302dl_info *lis, u8 reg, u8 val)
86105 +{
86106 +       (lis->pdata->lis302dl_bitbang_reg_write)(lis, reg, val);
86107 +}
86108 +
86109 +static void __reg_set_bit_mask(struct lis302dl_info *lis, u8 reg, u8 mask,
86110 +               u8 val)
86111 +{
86112 +       u_int8_t tmp;
86113 +
86114 +       val &= mask;
86115 +
86116 +       tmp = __reg_read(lis, reg);
86117 +       tmp &= ~mask;
86118 +       tmp |= val;
86119 +       __reg_write(lis, reg, tmp);
86120 +}
86121 +
86122 +static int __ms_to_duration(struct lis302dl_info *lis, int ms)
86123 +{
86124 +       /* If we have 400 ms sampling rate, the stepping is 2.5 ms,
86125 +        * on 100 ms the stepping is 10ms */
86126 +       if (lis->flags & LIS302DL_F_DR)
86127 +               return min((ms * 10) / 25, 637);
86128 +
86129 +       return min(ms / 10, 2550);
86130 +}
86131 +
86132 +static int __duration_to_ms(struct lis302dl_info *lis, int duration)
86133 +{
86134 +       if (lis->flags & LIS302DL_F_DR)
86135 +               return (duration * 25) / 10;
86136 +
86137 +       return duration * 10;
86138 +}
86139 +
86140 +static u8 __mg_to_threshold(struct lis302dl_info *lis, int mg)
86141 +{
86142 +       /* If FS is set each bit is 71mg, otherwise 18mg. The THS register
86143 +        * has 7 bits for the threshold value */
86144 +       if (lis->flags & LIS302DL_F_FS)
86145 +               return min(mg / 71, 127);
86146 +
86147 +       return min(mg / 18, 127);
86148 +}
86149 +
86150 +static int __threshold_to_mg(struct lis302dl_info *lis, u8 threshold)
86151 +{
86152 +       if (lis->flags & LIS302DL_F_FS)
86153 +               return threshold * 71;
86154 +
86155 +       return threshold * 18;
86156 +}
86157 +
86158 +/* interrupt handling related */
86159 +
86160 +enum lis302dl_intmode {
86161 +       LIS302DL_INTMODE_GND            = 0x00,
86162 +       LIS302DL_INTMODE_FF_WU_1        = 0x01,
86163 +       LIS302DL_INTMODE_FF_WU_2        = 0x02,
86164 +       LIS302DL_INTMODE_FF_WU_12       = 0x03,
86165 +       LIS302DL_INTMODE_DATA_READY     = 0x04,
86166 +       LIS302DL_INTMODE_CLICK          = 0x07,
86167 +};
86168 +
86169 +static void __lis302dl_int_mode(struct device *dev, int int_pin,
86170 +                             enum lis302dl_intmode mode)
86171 +{
86172 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86173 +
86174 +       switch (int_pin) {
86175 +       case 1:
86176 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL3, 0x07, mode);
86177 +               break;
86178 +       case 2:
86179 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL3, 0x38, mode << 3);
86180 +               break;
86181 +       default:
86182 +               BUG();
86183 +       }
86184 +}
86185 +
86186 +static void __enable_wakeup(struct lis302dl_info *lis)
86187 +{
86188 +       __reg_write(lis, LIS302DL_REG_CTRL1, 0);
86189 +
86190 +       /* First zero to get to a known state */
86191 +       __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1, LIS302DL_FFWUCFG_XHIE |
86192 +                       LIS302DL_FFWUCFG_YHIE | LIS302DL_FFWUCFG_ZHIE |
86193 +                       LIS302DL_FFWUCFG_LIR);
86194 +       __reg_write(lis, LIS302DL_REG_FF_WU_THS_1,
86195 +                       __mg_to_threshold(lis, lis->wakeup.threshold));
86196 +       __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
86197 +                       __ms_to_duration(lis, lis->wakeup.duration));
86198 +
86199 +       /* Route the interrupt for wakeup */
86200 +       __lis302dl_int_mode(lis->dev, 1,
86201 +                       LIS302DL_INTMODE_FF_WU_1);
86202 +
86203 +       __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
86204 +       __reg_read(lis, LIS302DL_REG_OUT_X);
86205 +       __reg_read(lis, LIS302DL_REG_OUT_Y);
86206 +       __reg_read(lis, LIS302DL_REG_OUT_Z);
86207 +       __reg_read(lis, LIS302DL_REG_STATUS);
86208 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
86209 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_2);
86210 +       __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD | 7);
86211 +}
86212 +
86213 +static void __enable_data_collection(struct lis302dl_info *lis)
86214 +{
86215 +       u_int8_t ctrl1 = LIS302DL_CTRL1_PD | LIS302DL_CTRL1_Xen |
86216 +                        LIS302DL_CTRL1_Yen | LIS302DL_CTRL1_Zen;
86217 +
86218 +       /* make sure we're powered up and generate data ready */
86219 +       __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, ctrl1, ctrl1);
86220 +
86221 +       /* If the threshold is zero, let the device generated an interrupt
86222 +        * on each datum */
86223 +       if (lis->threshold == 0) {
86224 +               __reg_write(lis, LIS302DL_REG_CTRL2, 0);
86225 +               __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_DATA_READY);
86226 +               __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_DATA_READY);
86227 +       } else {
86228 +               __reg_write(lis, LIS302DL_REG_CTRL2,
86229 +                               LIS302DL_CTRL2_HPFF1);
86230 +               __reg_write(lis, LIS302DL_REG_FF_WU_THS_1,
86231 +                               __mg_to_threshold(lis, lis->threshold));
86232 +               __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
86233 +                               __ms_to_duration(lis, lis->duration));
86234 +
86235 +               /* Clear the HP filter "starting point" */
86236 +               __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
86237 +               __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1,
86238 +                               LIS302DL_FFWUCFG_XHIE | LIS302DL_FFWUCFG_YHIE |
86239 +                               LIS302DL_FFWUCFG_ZHIE | LIS302DL_FFWUCFG_LIR);
86240 +               __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_FF_WU_12);
86241 +               __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_FF_WU_12);
86242 +       }
86243 +}
86244 +
86245 +#if 0
86246 +static void _report_btn_single(struct input_dev *inp, int btn)
86247 +{
86248 +       input_report_key(inp, btn, 1);
86249 +       input_sync(inp);
86250 +       input_report_key(inp, btn, 0);
86251 +}
86252 +
86253 +static void _report_btn_double(struct input_dev *inp, int btn)
86254 +{
86255 +       input_report_key(inp, btn, 1);
86256 +       input_sync(inp);
86257 +       input_report_key(inp, btn, 0);
86258 +       input_sync(inp);
86259 +       input_report_key(inp, btn, 1);
86260 +       input_sync(inp);
86261 +       input_report_key(inp, btn, 0);
86262 +}
86263 +#endif
86264 +
86265 +
86266 +static void lis302dl_bitbang_read_sample(struct lis302dl_info *lis)
86267 +{
86268 +       u8 data = 0xc0 | LIS302DL_REG_OUT_X; /* read, autoincrement */
86269 +       u8 read[5];
86270 +       unsigned long flags;
86271 +       int mg_per_sample;
86272 +
86273 +       local_irq_save(flags);
86274 +       mg_per_sample = __threshold_to_mg(lis, 1);
86275 +
86276 +       (lis->pdata->lis302dl_bitbang)(lis, &data, 1, &read[0], 5);
86277 +
86278 +       local_irq_restore(flags);
86279 +
86280 +       input_report_rel(lis->input_dev, REL_X, mg_per_sample * (s8)read[0]);
86281 +       input_report_rel(lis->input_dev, REL_Y, mg_per_sample * (s8)read[2]);
86282 +       input_report_rel(lis->input_dev, REL_Z, mg_per_sample * (s8)read[4]);
86283 +
86284 +       input_sync(lis->input_dev);
86285 +
86286 +       /* Reset the HP filter */
86287 +       __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
86288 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
86289 +}
86290 +
86291 +static irqreturn_t lis302dl_interrupt(int irq, void *_lis)
86292 +{
86293 +       struct lis302dl_info *lis = _lis;
86294 +
86295 +       lis302dl_bitbang_read_sample(lis);
86296 +       return IRQ_HANDLED;
86297 +}
86298 +
86299 +/* sysfs */
86300 +
86301 +static ssize_t show_rate(struct device *dev, struct device_attribute *attr,
86302 +                        char *buf)
86303 +{
86304 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86305 +       u8 ctrl1;
86306 +       unsigned long flags;
86307 +
86308 +       local_irq_save(flags);
86309 +       ctrl1 = __reg_read(lis, LIS302DL_REG_CTRL1);
86310 +       local_irq_restore(flags);
86311 +
86312 +       return sprintf(buf, "%d\n", ctrl1 & LIS302DL_CTRL1_DR ? 400 : 100);
86313 +}
86314 +
86315 +static ssize_t set_rate(struct device *dev, struct device_attribute *attr,
86316 +                       const char *buf, size_t count)
86317 +{
86318 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86319 +       unsigned long flags;
86320 +
86321 +       local_irq_save(flags);
86322 +
86323 +       if (!strcmp(buf, "400\n")) {
86324 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_DR,
86325 +                                LIS302DL_CTRL1_DR);
86326 +               lis->flags |= LIS302DL_F_DR;
86327 +       } else {
86328 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_DR,
86329 +                               0);
86330 +               lis->flags &= ~LIS302DL_F_DR;
86331 +       }
86332 +       local_irq_restore(flags);
86333 +
86334 +       return count;
86335 +}
86336 +
86337 +static DEVICE_ATTR(sample_rate, S_IRUGO | S_IWUSR, show_rate, set_rate);
86338 +
86339 +static ssize_t show_scale(struct device *dev, struct device_attribute *attr,
86340 +                         char *buf)
86341 +{
86342 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86343 +       u_int8_t ctrl1;
86344 +       unsigned long flags;
86345 +
86346 +       local_irq_save(flags);
86347 +       ctrl1 = __reg_read(lis, LIS302DL_REG_CTRL1);
86348 +       local_irq_restore(flags);
86349 +
86350 +       return sprintf(buf, "%s\n", ctrl1 & LIS302DL_CTRL1_FS ? "9.2" : "2.3");
86351 +}
86352 +
86353 +static ssize_t set_scale(struct device *dev, struct device_attribute *attr,
86354 +                        const char *buf, size_t count)
86355 +{
86356 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86357 +       unsigned long flags;
86358 +
86359 +       local_irq_save(flags);
86360 +
86361 +       if (!strcmp(buf, "9.2\n")) {
86362 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_FS,
86363 +                                LIS302DL_CTRL1_FS);
86364 +               lis->flags |= LIS302DL_F_FS;
86365 +       } else {
86366 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_FS,
86367 +                               0);
86368 +               lis->flags &= ~LIS302DL_F_FS;
86369 +       }
86370 +
86371 +       if (lis->flags & LIS302DL_F_INPUT_OPEN)
86372 +               __enable_data_collection(lis);
86373 +
86374 +       local_irq_restore(flags);
86375 +
86376 +       return count;
86377 +}
86378 +
86379 +static DEVICE_ATTR(full_scale, S_IRUGO | S_IWUSR, show_scale, set_scale);
86380 +
86381 +static ssize_t show_threshold(struct device *dev, struct device_attribute *attr,
86382 +                char *buf)
86383 +{
86384 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86385 +
86386 +       /* Display the device view of the threshold setting */
86387 +       return sprintf(buf, "%d\n", __threshold_to_mg(lis,
86388 +                       __mg_to_threshold(lis, lis->threshold)));
86389 +}
86390 +
86391 +static ssize_t set_threshold(struct device *dev, struct device_attribute *attr,
86392 +                const char *buf, size_t count)
86393 +{
86394 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86395 +       unsigned int val;
86396 +
86397 +       if (sscanf(buf, "%u\n", &val) != 1)
86398 +               return -EINVAL;
86399 +       /* 8g is the maximum if FS is 1 */
86400 +       if (val > 8000)
86401 +               return -ERANGE;
86402 +
86403 +       /* Set the threshold and write it out if the device is used */
86404 +       lis->threshold = val;
86405 +
86406 +       if (lis->flags & LIS302DL_F_INPUT_OPEN) {
86407 +               unsigned long flags;
86408 +
86409 +               local_irq_save(flags);
86410 +               __enable_data_collection(lis);
86411 +               local_irq_restore(flags);
86412 +       }
86413 +
86414 +       return count;
86415 +}
86416 +
86417 +static DEVICE_ATTR(threshold, S_IRUGO | S_IWUSR, show_threshold, set_threshold);
86418 +
86419 +static ssize_t show_duration(struct device *dev, struct device_attribute *attr,
86420 +                char *buf)
86421 +{
86422 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86423 +
86424 +       return sprintf(buf, "%d\n", __duration_to_ms(lis,
86425 +                       __ms_to_duration(lis, lis->duration)));
86426 +}
86427 +
86428 +static ssize_t set_duration(struct device *dev, struct device_attribute *attr,
86429 +                const char *buf, size_t count)
86430 +{
86431 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86432 +       unsigned int val;
86433 +
86434 +       if (sscanf(buf, "%u\n", &val) != 1)
86435 +               return -EINVAL;
86436 +       if (val > 2550)
86437 +               return -ERANGE;
86438 +
86439 +       lis->duration = val;
86440 +       if (lis->flags & LIS302DL_F_INPUT_OPEN)
86441 +               __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
86442 +                               __ms_to_duration(lis, lis->duration));
86443 +
86444 +       return count;
86445 +}
86446 +
86447 +static DEVICE_ATTR(duration, S_IRUGO | S_IWUSR, show_duration, set_duration);
86448 +
86449 +static ssize_t lis302dl_dump(struct device *dev, struct device_attribute *attr,
86450 +                                                                     char *buf)
86451 +{
86452 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86453 +       int n = 0;
86454 +       u8 reg[0x40];
86455 +       char *end = buf;
86456 +       unsigned long flags;
86457 +
86458 +       local_irq_save(flags);
86459 +
86460 +       for (n = 0; n < sizeof(reg); n++)
86461 +               reg[n] = __reg_read(lis, n);
86462 +
86463 +       local_irq_restore(flags);
86464 +
86465 +       for (n = 0; n < sizeof(reg); n += 16) {
86466 +               hex_dump_to_buffer(reg + n, 16, 16, 1, end, 128, 0);
86467 +               end += strlen(end);
86468 +               *end++ = '\n';
86469 +               *end++ = '\0';
86470 +       }
86471 +
86472 +       return end - buf;
86473 +}
86474 +static DEVICE_ATTR(dump, S_IRUGO, lis302dl_dump, NULL);
86475 +
86476 +/* Configure freefall/wakeup interrupts */
86477 +static ssize_t set_wakeup_threshold(struct device *dev,
86478 +               struct device_attribute *attr, const char *buf, size_t count)
86479 +{
86480 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86481 +       unsigned int threshold;
86482 +
86483 +       if (sscanf(buf, "%u\n", &threshold) != 1)
86484 +               return -EINVAL;
86485 +
86486 +       if (threshold > 8000)
86487 +               return -ERANGE;
86488 +
86489 +       /* Zero turns the feature off */
86490 +       if (threshold == 0) {
86491 +               if (lis->flags & LIS302DL_F_IRQ_WAKE) {
86492 +                       disable_irq_wake(lis->pdata->interrupt);
86493 +                       lis->flags &= ~LIS302DL_F_IRQ_WAKE;
86494 +               }
86495 +
86496 +               return count;
86497 +       }
86498 +
86499 +       lis->wakeup.threshold = threshold;
86500 +
86501 +       if (!(lis->flags & LIS302DL_F_IRQ_WAKE)) {
86502 +               enable_irq_wake(lis->pdata->interrupt);
86503 +               lis->flags |= LIS302DL_F_IRQ_WAKE;
86504 +       }
86505 +
86506 +       return count;
86507 +}
86508 +
86509 +static ssize_t show_wakeup_threshold(struct device *dev,
86510 +               struct device_attribute *attr, char *buf)
86511 +{
86512 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86513 +
86514 +       /* All events off? */
86515 +       if (lis->wakeup.threshold == 0)
86516 +               return sprintf(buf, "off\n");
86517 +
86518 +       return sprintf(buf, "%u\n", lis->wakeup.threshold);
86519 +}
86520 +
86521 +static DEVICE_ATTR(wakeup_threshold, S_IRUGO | S_IWUSR, show_wakeup_threshold,
86522 +               set_wakeup_threshold);
86523 +
86524 +static ssize_t set_wakeup_duration(struct device *dev,
86525 +               struct device_attribute *attr, const char *buf, size_t count)
86526 +{
86527 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86528 +       unsigned int duration;
86529 +
86530 +       if (sscanf(buf, "%u\n", &duration) != 1)
86531 +               return -EINVAL;
86532 +
86533 +       if (duration > 2550)
86534 +               return -ERANGE;
86535 +
86536 +       lis->wakeup.duration = duration;
86537 +
86538 +       return count;
86539 +}
86540 +
86541 +static ssize_t show_wakeup_duration(struct device *dev,
86542 +               struct device_attribute *attr, char *buf)
86543 +{
86544 +       struct lis302dl_info *lis = dev_get_drvdata(dev);
86545 +
86546 +       return sprintf(buf, "%u\n", lis->wakeup.duration);
86547 +}
86548 +
86549 +static DEVICE_ATTR(wakeup_duration, S_IRUGO | S_IWUSR, show_wakeup_duration,
86550 +               set_wakeup_duration);
86551 +
86552 +static struct attribute *lis302dl_sysfs_entries[] = {
86553 +       &dev_attr_sample_rate.attr,
86554 +       &dev_attr_full_scale.attr,
86555 +       &dev_attr_threshold.attr,
86556 +       &dev_attr_duration.attr,
86557 +       &dev_attr_dump.attr,
86558 +       &dev_attr_wakeup_threshold.attr,
86559 +       &dev_attr_wakeup_duration.attr,
86560 +       NULL
86561 +};
86562 +
86563 +static struct attribute_group lis302dl_attr_group = {
86564 +       .name   = NULL,
86565 +       .attrs  = lis302dl_sysfs_entries,
86566 +};
86567 +
86568 +/* input device handling and driver core interaction */
86569 +
86570 +static int lis302dl_input_open(struct input_dev *inp)
86571 +{
86572 +       struct lis302dl_info *lis = input_get_drvdata(inp);
86573 +       unsigned long flags;
86574 +
86575 +       local_irq_save(flags);
86576 +
86577 +       __enable_data_collection(lis);
86578 +       lis->flags |= LIS302DL_F_INPUT_OPEN;
86579 +
86580 +       local_irq_restore(flags);
86581 +
86582 +       return 0;
86583 +}
86584 +
86585 +static void lis302dl_input_close(struct input_dev *inp)
86586 +{
86587 +       struct lis302dl_info *lis = input_get_drvdata(inp);
86588 +       u_int8_t ctrl1 = LIS302DL_CTRL1_Xen | LIS302DL_CTRL1_Yen |
86589 +                        LIS302DL_CTRL1_Zen;
86590 +       unsigned long flags;
86591 +
86592 +       local_irq_save(flags);
86593 +
86594 +       /* since the input core already serializes access and makes sure we
86595 +        * only see close() for the close of the last user, we can safely
86596 +        * disable the data ready events */
86597 +       __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, ctrl1, 0x00);
86598 +       lis->flags &= ~LIS302DL_F_INPUT_OPEN;
86599 +
86600 +       /* however, don't power down the whole device if still needed */
86601 +       if (!(lis->flags & LIS302DL_F_WUP_FF ||
86602 +             lis->flags & LIS302DL_F_WUP_CLICK)) {
86603 +               __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD,
86604 +                                0x00);
86605 +       }
86606 +       local_irq_restore(flags);
86607 +}
86608 +
86609 +/* get the device to reload its coefficients from EEPROM and wait for it
86610 + * to complete
86611 + */
86612 +
86613 +static int __lis302dl_reset_device(struct lis302dl_info *lis)
86614 +{
86615 +       int timeout = 10;
86616 +
86617 +       __reg_write(lis, LIS302DL_REG_CTRL2,
86618 +                       LIS302DL_CTRL2_BOOT | LIS302DL_CTRL2_FDS);
86619 +
86620 +       while ((__reg_read(lis, LIS302DL_REG_CTRL2)
86621 +                       & LIS302DL_CTRL2_BOOT) && (timeout--))
86622 +               mdelay(1);
86623 +
86624 +       return !!(timeout < 0);
86625 +}
86626 +
86627 +static int __devinit lis302dl_probe(struct platform_device *pdev)
86628 +{
86629 +       int rc;
86630 +       struct lis302dl_info *lis;
86631 +       u_int8_t wai;
86632 +       unsigned long flags;
86633 +       struct lis302dl_platform_data *pdata = pdev->dev.platform_data;
86634 +
86635 +       lis = kzalloc(sizeof(*lis), GFP_KERNEL);
86636 +       if (!lis)
86637 +               return -ENOMEM;
86638 +
86639 +       lis->dev = &pdev->dev;
86640 +
86641 +       dev_set_drvdata(lis->dev, lis);
86642 +
86643 +       lis->pdata = pdata;
86644 +
86645 +       rc = sysfs_create_group(&lis->dev->kobj, &lis302dl_attr_group);
86646 +       if (rc) {
86647 +               dev_err(lis->dev, "error creating sysfs group\n");
86648 +               goto bail_free_lis;
86649 +       }
86650 +
86651 +       /* initialize input layer details */
86652 +       lis->input_dev = input_allocate_device();
86653 +       if (!lis->input_dev) {
86654 +               dev_err(lis->dev, "Unable to allocate input device\n");
86655 +               goto bail_sysfs;
86656 +       }
86657 +
86658 +       input_set_drvdata(lis->input_dev, lis);
86659 +       lis->input_dev->name = pdata->name;
86660 +        /* SPI Bus not defined as a valid bus for input subsystem*/
86661 +       lis->input_dev->id.bustype = BUS_I2C; /* lie about it */
86662 +       lis->input_dev->open = lis302dl_input_open;
86663 +       lis->input_dev->close = lis302dl_input_close;
86664 +
86665 +       rc = input_register_device(lis->input_dev);
86666 +       if (rc) {
86667 +               dev_err(lis->dev, "error %d registering input device\n", rc);
86668 +               goto bail_inp_dev;
86669 +       }
86670 +
86671 +       local_irq_save(flags);
86672 +       /* Configure our IO */
86673 +       (lis->pdata->lis302dl_suspend_io)(lis, 1);
86674 +
86675 +       wai = __reg_read(lis, LIS302DL_REG_WHO_AM_I);
86676 +       if (wai != LIS302DL_WHO_AM_I_MAGIC) {
86677 +               dev_err(lis->dev, "unknown who_am_i signature 0x%02x\n", wai);
86678 +               dev_set_drvdata(lis->dev, NULL);
86679 +               rc = -ENODEV;
86680 +               local_irq_restore(flags);
86681 +               goto bail_inp_reg;
86682 +       }
86683 +
86684 +       set_bit(EV_REL, lis->input_dev->evbit);
86685 +       set_bit(REL_X, lis->input_dev->relbit);
86686 +       set_bit(REL_Y, lis->input_dev->relbit);
86687 +       set_bit(REL_Z, lis->input_dev->relbit);
86688 +/*     set_bit(EV_KEY, lis->input_dev->evbit);
86689 +       set_bit(BTN_X, lis->input_dev->keybit);
86690 +       set_bit(BTN_Y, lis->input_dev->keybit);
86691 +       set_bit(BTN_Z, lis->input_dev->keybit);
86692 +*/
86693 +       lis->threshold = 0;
86694 +       lis->duration = 0;
86695 +       memset(&lis->wakeup, 0, sizeof(lis->wakeup));
86696 +
86697 +       if (__lis302dl_reset_device(lis))
86698 +               dev_err(lis->dev, "device BOOT reload failed\n");
86699 +
86700 +       /* force us powered */
86701 +       __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD |
86702 +                       LIS302DL_CTRL1_Xen |
86703 +                       LIS302DL_CTRL1_Yen |
86704 +                       LIS302DL_CTRL1_Zen);
86705 +       mdelay(1);
86706 +
86707 +       __reg_write(lis, LIS302DL_REG_CTRL2, 0);
86708 +       __reg_write(lis, LIS302DL_REG_CTRL3,
86709 +                       LIS302DL_CTRL3_PP_OD | LIS302DL_CTRL3_IHL);
86710 +       __reg_write(lis, LIS302DL_REG_FF_WU_THS_1, 0x0);
86711 +       __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1, 0x00);
86712 +       __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1, 0x0);
86713 +
86714 +       /* start off in powered down mode; we power up when someone opens us */
86715 +       __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_Xen |
86716 +                       LIS302DL_CTRL1_Yen | LIS302DL_CTRL1_Zen);
86717 +
86718 +       if (pdata->open_drain)
86719 +               /* switch interrupt to open collector, active-low */
86720 +               __reg_write(lis, LIS302DL_REG_CTRL3,
86721 +                               LIS302DL_CTRL3_PP_OD | LIS302DL_CTRL3_IHL);
86722 +       else
86723 +               /* push-pull, active-low */
86724 +               __reg_write(lis, LIS302DL_REG_CTRL3, LIS302DL_CTRL3_IHL);
86725 +
86726 +       __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_GND);
86727 +       __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_GND);
86728 +
86729 +       __reg_read(lis, LIS302DL_REG_STATUS);
86730 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
86731 +       __reg_read(lis, LIS302DL_REG_FF_WU_SRC_2);
86732 +       __reg_read(lis, LIS302DL_REG_CLICK_SRC);
86733 +       local_irq_restore(flags);
86734 +
86735 +       dev_info(lis->dev, "Found %s\n", pdata->name);
86736 +
86737 +       lis->pdata = pdata;
86738 +
86739 +       set_irq_handler(lis->pdata->interrupt, handle_level_irq);
86740 +
86741 +       rc = request_irq(lis->pdata->interrupt, lis302dl_interrupt,
86742 +                        IRQF_TRIGGER_LOW, "lis302dl", lis);
86743 +
86744 +       if (rc < 0) {
86745 +               dev_err(lis->dev, "error requesting IRQ %d\n",
86746 +                       lis->pdata->interrupt);
86747 +               goto bail_inp_reg;
86748 +       }
86749 +       return 0;
86750 +
86751 +bail_inp_reg:
86752 +       input_unregister_device(lis->input_dev);
86753 +bail_inp_dev:
86754 +       input_free_device(lis->input_dev);
86755 +bail_sysfs:
86756 +       sysfs_remove_group(&lis->dev->kobj, &lis302dl_attr_group);
86757 +bail_free_lis:
86758 +       kfree(lis);
86759 +       return rc;
86760 +}
86761 +
86762 +static int __devexit lis302dl_remove(struct platform_device *pdev)
86763 +{
86764 +       struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
86765 +       unsigned long flags;
86766 +
86767 +       /* Disable interrupts */
86768 +       if (lis->flags & LIS302DL_F_IRQ_WAKE)
86769 +               disable_irq_wake(lis->pdata->interrupt);
86770 +       free_irq(lis->pdata->interrupt, lis);
86771 +
86772 +       /* Reset and power down the device */
86773 +       local_irq_save(flags);
86774 +       __reg_write(lis, LIS302DL_REG_CTRL3, 0x00);
86775 +       __reg_write(lis, LIS302DL_REG_CTRL2, 0x00);
86776 +       __reg_write(lis, LIS302DL_REG_CTRL1, 0x00);
86777 +       local_irq_restore(flags);
86778 +
86779 +       /* Cleanup resources */
86780 +       sysfs_remove_group(&pdev->dev.kobj, &lis302dl_attr_group);
86781 +       input_unregister_device(lis->input_dev);
86782 +       if (lis->input_dev)
86783 +               input_free_device(lis->input_dev);
86784 +       dev_set_drvdata(lis->dev, NULL);
86785 +       kfree(lis);
86786 +
86787 +       return 0;
86788 +}
86789 +
86790 +#ifdef CONFIG_PM
86791 +
86792 +static u8 regs_to_save[] = {
86793 +       LIS302DL_REG_CTRL1,
86794 +       LIS302DL_REG_CTRL2,
86795 +       LIS302DL_REG_CTRL3,
86796 +       LIS302DL_REG_FF_WU_CFG_1,
86797 +       LIS302DL_REG_FF_WU_THS_1,
86798 +       LIS302DL_REG_FF_WU_DURATION_1,
86799 +       LIS302DL_REG_FF_WU_CFG_2,
86800 +       LIS302DL_REG_FF_WU_THS_2,
86801 +       LIS302DL_REG_FF_WU_DURATION_2,
86802 +       LIS302DL_REG_CLICK_CFG,
86803 +       LIS302DL_REG_CLICK_THSY_X,
86804 +       LIS302DL_REG_CLICK_THSZ,
86805 +       LIS302DL_REG_CLICK_TIME_LIMIT,
86806 +       LIS302DL_REG_CLICK_LATENCY,
86807 +       LIS302DL_REG_CLICK_WINDOW,
86808 +
86809 +};
86810 +
86811 +static int lis302dl_suspend(struct platform_device *pdev, pm_message_t state)
86812 +{
86813 +       struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
86814 +       unsigned long flags;
86815 +       u_int8_t tmp;
86816 +       int n;
86817 +
86818 +       /* determine if we want to wake up from the accel. */
86819 +       if (lis->flags & LIS302DL_F_WUP_CLICK)
86820 +               return 0;
86821 +
86822 +       disable_irq(lis->pdata->interrupt);
86823 +       local_irq_save(flags);
86824 +
86825 +       /*
86826 +        * When we share SPI over multiple sensors, there is a race here
86827 +        * that one or more sensors will lose.  In that case, the shared
86828 +        * SPI bus GPIO will be in sleep mode and partially pulled down.  So
86829 +        * we explicitly put our IO into "wake" mode here before the final
86830 +        * traffic to the sensor.
86831 +        */
86832 +       (lis->pdata->lis302dl_suspend_io)(lis, 1);
86833 +
86834 +       /* save registers */
86835 +       for (n = 0; n < ARRAY_SIZE(regs_to_save); n++)
86836 +               lis->regs[regs_to_save[n]] =
86837 +                       __reg_read(lis, regs_to_save[n]);
86838 +
86839 +       /* power down or enable wakeup */
86840 +
86841 +       if (lis->wakeup.threshold == 0) {
86842 +               tmp = __reg_read(lis, LIS302DL_REG_CTRL1);
86843 +               tmp &= ~LIS302DL_CTRL1_PD;
86844 +               __reg_write(lis, LIS302DL_REG_CTRL1, tmp);
86845 +       } else
86846 +               __enable_wakeup(lis);
86847 +
86848 +       /* place our IO to the device in sleep-compatible states */
86849 +       (lis->pdata->lis302dl_suspend_io)(lis, 0);
86850 +
86851 +       local_irq_restore(flags);
86852 +
86853 +       return 0;
86854 +}
86855 +
86856 +static int lis302dl_resume(struct platform_device *pdev)
86857 +{
86858 +       struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
86859 +       unsigned long flags;
86860 +       int n;
86861 +
86862 +       if (lis->flags & LIS302DL_F_WUP_CLICK)
86863 +               return 0;
86864 +
86865 +       local_irq_save(flags);
86866 +
86867 +       /* get our IO to the device back in operational states */
86868 +       (lis->pdata->lis302dl_suspend_io)(lis, 1);
86869 +
86870 +       /* resume from powerdown first! */
86871 +       __reg_write(lis, LIS302DL_REG_CTRL1,
86872 +                       LIS302DL_CTRL1_PD |
86873 +                       LIS302DL_CTRL1_Xen |
86874 +                       LIS302DL_CTRL1_Yen |
86875 +                       LIS302DL_CTRL1_Zen);
86876 +       mdelay(1);
86877 +
86878 +       if (__lis302dl_reset_device(lis))
86879 +               dev_err(&pdev->dev, "device BOOT reload failed\n");
86880 +
86881 +       lis->regs[LIS302DL_REG_CTRL1] |=        LIS302DL_CTRL1_PD |
86882 +                                               LIS302DL_CTRL1_Xen |
86883 +                                               LIS302DL_CTRL1_Yen |
86884 +                                               LIS302DL_CTRL1_Zen;
86885 +
86886 +       /* restore registers after resume */
86887 +       for (n = 0; n < ARRAY_SIZE(regs_to_save); n++)
86888 +               __reg_write(lis, regs_to_save[n], lis->regs[regs_to_save[n]]);
86889 +
86890 +       local_irq_restore(flags);
86891 +       enable_irq(lis->pdata->interrupt);
86892 +
86893 +       return 0;
86894 +}
86895 +#else
86896 +#define lis302dl_suspend       NULL
86897 +#define lis302dl_resume                NULL
86898 +#endif
86899 +
86900 +static struct platform_driver lis302dl_driver = {
86901 +       .driver = {
86902 +               .name   = "lis302dl",
86903 +               .owner  = THIS_MODULE,
86904 +       },
86905 +
86906 +       .probe   = lis302dl_probe,
86907 +       .remove  = __devexit_p(lis302dl_remove),
86908 +       .suspend = lis302dl_suspend,
86909 +       .resume  = lis302dl_resume,
86910 +};
86911 +
86912 +static int __devinit lis302dl_init(void)
86913 +{
86914 +       return platform_driver_register(&lis302dl_driver);
86915 +}
86916 +
86917 +static void __exit lis302dl_exit(void)
86918 +{
86919 +       platform_driver_unregister(&lis302dl_driver);
86920 +}
86921 +
86922 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
86923 +MODULE_LICENSE("GPL");
86924 +
86925 +module_init(lis302dl_init);
86926 +module_exit(lis302dl_exit);
86927 Index: linux-2.6.28/drivers/input/misc/Makefile
86928 ===================================================================
86929 --- linux-2.6.28.orig/drivers/input/misc/Makefile       2009-01-02 00:00:02.000000000 +0100
86930 +++ linux-2.6.28/drivers/input/misc/Makefile    2009-01-02 00:05:46.000000000 +0100
86931 @@ -22,3 +22,6 @@ obj-$(CONFIG_INPUT_UINPUT)            += uinput.o
86932  obj-$(CONFIG_INPUT_APANEL)             += apanel.o
86933  obj-$(CONFIG_INPUT_SGI_BTNS)           += sgi_btns.o
86934  obj-$(CONFIG_INPUT_GPIO_BUTTONS)       += gpio_buttons.o
86935 +obj-$(CONFIG_INPUT_LIS302DL)           += lis302dl.o
86936 +obj-$(CONFIG_INPUT_PCF50633_PMU)       += pcf50633-input.o
86937 +obj-$(CONFIG_INPUT_PCF50606_PMU)       += pcf50606-input.o
86938 Index: linux-2.6.28/drivers/input/misc/pcf50606-input.c
86939 ===================================================================
86940 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
86941 +++ linux-2.6.28/drivers/input/misc/pcf50606-input.c    2009-01-02 00:01:56.000000000 +0100
86942 @@ -0,0 +1,123 @@
86943 +/* Philips PCF50606 Input Driver
86944 + *
86945 + * (C) 2006-2008 by Openmoko, Inc.
86946 + * Author: Balaji Rao <balajirrao@openmoko.org>
86947 + * All rights reserved.
86948 + *
86949 + * Broken down from monstrous PCF50606 driver mainly by
86950 + * Harald Welte, Matt Hsu, Andy Green and Werner Almesberger
86951 + *
86952 + * This program is free software; you can redistribute it and/or
86953 + * modify it under the terms of the GNU General Public License as
86954 + * published by the Free Software Foundation; either version 2 of
86955 + * the License, or (at your option) any later version.
86956 + *
86957 + * This program is distributed in the hope that it will be useful,
86958 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
86959 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
86960 + * GNU General Public License for more details.
86961 + *
86962 + * You should have received a copy of the GNU General Public License
86963 + * along with this program; if not, write to the Free Software
86964 + * Foundation, Inc., 59 Temple Place, Suite 060, Boston,
86965 + * MA 02111-1307 USA
86966 + */
86967 +
86968 +#include <linux/input.h>
86969 +
86970 +#include <linux/mfd/pcf50606/core.h>
86971 +#include <linux/mfd/pcf50606/input.h>
86972 +
86973 +static void
86974 +pcf50606_input_irq(struct pcf50606 *pcf, int irq, void *data)
86975 +{
86976 +       struct input_dev *input_dev = pcf->input.input_dev;
86977 +       int onkey_released;
86978 +
86979 +       /* We report only one event depending on if the key status */
86980 +       onkey_released = pcf50606_reg_read(pcf, PCF50606_REG_OOCS) &
86981 +                                       PCF50606_OOCS_ONKEY;
86982 +
86983 +       if (irq == PCF50606_IRQ_ONKEYF && !onkey_released)
86984 +               input_report_key(input_dev, KEY_POWER, 1);
86985 +       else if (irq == PCF50606_IRQ_ONKEYR && onkey_released)
86986 +               input_report_key(input_dev, KEY_POWER, 0);
86987 +
86988 +       input_sync(input_dev);
86989 +}
86990 +
86991 +int __init pcf50606_input_probe(struct platform_device *pdev)
86992 +{
86993 +       struct pcf50606 *pcf;
86994 +       struct input_dev *input_dev;
86995 +       int ret;
86996 +
86997 +       pcf = platform_get_drvdata(pdev);
86998 +
86999 +       input_dev = input_allocate_device();
87000 +       if (!input_dev)
87001 +               return -ENODEV;
87002 +
87003 +       input_dev->name = "PCF50606 PMU events";
87004 +       input_dev->id.bustype = BUS_I2C;
87005 +
87006 +       input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
87007 +       set_bit(KEY_POWER, input_dev->keybit);
87008 +       set_bit(KEY_POWER2, input_dev->keybit);
87009 +
87010 +       ret = input_register_device(input_dev);
87011 +       if (ret)
87012 +               goto out;
87013 +
87014 +       pcf->input.input_dev = input_dev;
87015 +
87016 +       /* Currently we care only about ONKEY and USBINS/USBREM
87017 +        *
87018 +        * USBINS/USBREM are told to us by mbc driver as we can't setup
87019 +        * two handlers for an IRQ
87020 +        */
87021 +       pcf->irq_handler[PCF50606_IRQ_ONKEYR].handler = pcf50606_input_irq;
87022 +
87023 +       pcf->irq_handler[PCF50606_IRQ_ONKEYF].handler = pcf50606_input_irq;
87024 +
87025 +       return 0;
87026 +
87027 +out:
87028 +       input_free_device(input_dev);
87029 +       return ret;
87030 +}
87031 +
87032 +static int __devexit pcf50606_input_remove(struct platform_device *pdev)
87033 +{
87034 +       struct pcf50606 *pcf;
87035 +
87036 +       pcf = platform_get_drvdata(pdev);
87037 +       input_unregister_device(pcf->input.input_dev);
87038 +
87039 +       return 0;
87040 +}
87041 +
87042 +struct platform_driver pcf50606_input_driver = {
87043 +       .driver = {
87044 +               .name = "pcf50606-input",
87045 +       },
87046 +       .probe = pcf50606_input_probe,
87047 +       .remove = __devexit_p(pcf50606_input_remove),
87048 +};
87049 +
87050 +static int __init pcf50606_input_init(void)
87051 +{
87052 +               return platform_driver_register(&pcf50606_input_driver);
87053 +}
87054 +module_init(pcf50606_input_init);
87055 +
87056 +static void __exit pcf50606_input_exit(void)
87057 +{
87058 +               platform_driver_unregister(&pcf50606_input_driver);
87059 +}
87060 +module_exit(pcf50606_input_exit);
87061 +
87062 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
87063 +MODULE_DESCRIPTION("PCF50606 input driver");
87064 +MODULE_LICENSE("GPL");
87065 +MODULE_ALIAS("platform:pcf50606-input");
87066 Index: linux-2.6.28/drivers/input/misc/pcf50633-input.c
87067 ===================================================================
87068 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
87069 +++ linux-2.6.28/drivers/input/misc/pcf50633-input.c    2009-01-02 00:01:56.000000000 +0100
87070 @@ -0,0 +1,123 @@
87071 +/* Philips PCF50633 Input Driver
87072 + *
87073 + * (C) 2006-2008 by Openmoko, Inc.
87074 + * Author: Balaji Rao <balajirrao@openmoko.org>
87075 + * All rights reserved.
87076 + *
87077 + * Broken down from monstrous PCF50633 driver mainly by
87078 + * Harald Welte, Andy Green and Werner Almesberger
87079 + *
87080 + * This program is free software; you can redistribute it and/or
87081 + * modify it under the terms of the GNU General Public License as
87082 + * published by the Free Software Foundation; either version 2 of
87083 + * the License, or (at your option) any later version.
87084 + *
87085 + * This program is distributed in the hope that it will be useful,
87086 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87087 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87088 + * GNU General Public License for more details.
87089 + *
87090 + * You should have received a copy of the GNU General Public License
87091 + * along with this program; if not, write to the Free Software
87092 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
87093 + * MA 02111-1307 USA
87094 + */
87095 +
87096 +#include <linux/input.h>
87097 +
87098 +#include <linux/mfd/pcf50633/core.h>
87099 +#include <linux/mfd/pcf50633/input.h>
87100 +
87101 +static void
87102 +pcf50633_input_irq(struct pcf50633 *pcf, int irq, void *data)
87103 +{
87104 +       struct input_dev *input_dev = pcf->input.input_dev;
87105 +       int onkey_released;
87106 +
87107 +       /* We report only one event depending on if the key status */
87108 +       onkey_released = pcf50633_reg_read(pcf, PCF50633_REG_OOCSTAT) &
87109 +                                       PCF50633_OOCSTAT_ONKEY;
87110 +
87111 +       if (irq == PCF50633_IRQ_ONKEYF && !onkey_released)
87112 +               input_report_key(input_dev, KEY_POWER, 1);
87113 +       else if (irq == PCF50633_IRQ_ONKEYR && onkey_released)
87114 +               input_report_key(input_dev, KEY_POWER, 0);
87115 +
87116 +       input_sync(input_dev);
87117 +}
87118 +
87119 +int __init pcf50633_input_probe(struct platform_device *pdev)
87120 +{
87121 +       struct pcf50633 *pcf;
87122 +       struct input_dev *input_dev;
87123 +       int ret;
87124 +
87125 +       pcf = platform_get_drvdata(pdev);
87126 +
87127 +       input_dev = input_allocate_device();
87128 +       if (!input_dev)
87129 +               return -ENODEV;
87130 +
87131 +       input_dev->name = "GTA02 PMU events";
87132 +       input_dev->id.bustype = BUS_I2C;
87133 +
87134 +       input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
87135 +       set_bit(KEY_POWER, input_dev->keybit);
87136 +       set_bit(KEY_POWER2, input_dev->keybit);
87137 +
87138 +       ret = input_register_device(input_dev);
87139 +       if (ret)
87140 +               goto out;
87141 +
87142 +       pcf->input.input_dev = input_dev;
87143 +
87144 +       /* Currently we care only about ONKEY and USBINS/USBREM
87145 +        *
87146 +        * USBINS/USBREM are told to us by mbc driver as we can't setup
87147 +        * two handlers for an IRQ
87148 +        */
87149 +       pcf->irq_handler[PCF50633_IRQ_ONKEYR].handler = pcf50633_input_irq;
87150 +
87151 +       pcf->irq_handler[PCF50633_IRQ_ONKEYF].handler = pcf50633_input_irq;
87152 +
87153 +       return 0;
87154 +
87155 +out:
87156 +       input_free_device(input_dev);
87157 +       return ret;
87158 +}
87159 +
87160 +static int __devexit pcf50633_input_remove(struct platform_device *pdev)
87161 +{
87162 +       struct pcf50633 *pcf;
87163 +
87164 +       pcf = platform_get_drvdata(pdev);
87165 +       input_unregister_device(pcf->input.input_dev);
87166 +
87167 +       return 0;
87168 +}
87169 +
87170 +struct platform_driver pcf50633_input_driver = {
87171 +       .driver = {
87172 +               .name = "pcf50633-input",
87173 +       },
87174 +       .probe = pcf50633_input_probe,
87175 +       .remove = __devexit_p(pcf50633_input_remove),
87176 +};
87177 +
87178 +static int __init pcf50633_input_init(void)
87179 +{
87180 +               return platform_driver_register(&pcf50633_input_driver);
87181 +}
87182 +module_init(pcf50633_input_init);
87183 +
87184 +static void __exit pcf50633_input_exit(void)
87185 +{
87186 +               platform_driver_unregister(&pcf50633_input_driver);
87187 +}
87188 +module_exit(pcf50633_input_exit);
87189 +
87190 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
87191 +MODULE_DESCRIPTION("PCF50633 input driver");
87192 +MODULE_LICENSE("GPL");
87193 +MODULE_ALIAS("platform:pcf50633-input");
87194 Index: linux-2.6.28/drivers/input/mousedev.c
87195 ===================================================================
87196 --- linux-2.6.28.orig/drivers/input/mousedev.c  2008-12-25 00:26:37.000000000 +0100
87197 +++ linux-2.6.28/drivers/input/mousedev.c       2009-01-02 00:01:56.000000000 +0100
87198 @@ -1016,6 +1016,7 @@ static const struct input_device_id mous
87199                 .evbit = { BIT_MASK(EV_KEY) | BIT_MASK(EV_REL) },
87200                 .relbit = { BIT_MASK(REL_WHEEL) },
87201         },      /* A separate scrollwheel */
87202 +#if 0
87203         {
87204                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
87205                                 INPUT_DEVICE_ID_MATCH_KEYBIT |
87206 @@ -1025,6 +1026,7 @@ static const struct input_device_id mous
87207                 .absbit = { BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
87208         },      /* A tablet like device, at least touch detection,
87209                    two absolute axes */
87210 +#endif
87211         {
87212                 .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
87213                                 INPUT_DEVICE_ID_MATCH_KEYBIT |
87214 Index: linux-2.6.28/drivers/input/touchscreen/Kconfig
87215 ===================================================================
87216 --- linux-2.6.28.orig/drivers/input/touchscreen/Kconfig 2008-12-25 00:26:37.000000000 +0100
87217 +++ linux-2.6.28/drivers/input/touchscreen/Kconfig      2009-01-02 00:01:56.000000000 +0100
87218 @@ -11,6 +11,50 @@ menuconfig INPUT_TOUCHSCREEN
87219
87220  if INPUT_TOUCHSCREEN
87221
87222 +menuconfig TOUCHSCREEN_FILTER
87223 +       boolean "Touchscreen Filtering"
87224 +       depends on INPUT_TOUCHSCREEN
87225 +       help
87226 +         Select this to include kernel touchscreen filter support.  The filters
87227 +         can be combined in any order in your machine init and the parameters
87228 +         for them can also be set there.
87229 +
87230 +if TOUCHSCREEN_FILTER
87231 +
87232 +config TOUCHSCREEN_FILTER_GROUP
87233 +       bool "Group Touchscreen Filter"
87234 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
87235 +       default Y
87236 +       help
87237 +         Say Y here if you want to use the Group touchscreen filter, it
87238 +         avoids using atypical samples.
87239 +
87240 +config TOUCHSCREEN_FILTER_MEDIAN
87241 +       bool "Median Average Touchscreen Filter"
87242 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
87243 +       default Y
87244 +       help
87245 +         Say Y here if you want to use the Median touchscreen filter, it's
87246 +         highly effective if you data is noisy with occasional excursions.
87247 +
87248 +config TOUCHSCREEN_FILTER_MEAN
87249 +       bool "Mean Average Touchscreen Filter"
87250 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
87251 +       default Y
87252 +       help
87253 +         Say Y here if you want to use the Mean touchscreen filter, it
87254 +         can further improve decent quality data by removing jitter
87255 +
87256 +config TOUCHSCREEN_FILTER_LINEAR
87257 +       bool "Linear Touchscreen Filter"
87258 +       depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
87259 +       default Y
87260 +       help
87261 +         Say Y here if you want to use the Mean touchscreen filter, it
87262 +         enables the use of calibration data for the touchscreen.
87263 +
87264 +endif
87265 +
87266  config TOUCHSCREEN_ADS7846
87267         tristate "ADS7846/TSC2046 and ADS7843 based touchscreens"
87268         depends on SPI_MASTER
87269 @@ -71,6 +115,25 @@ config TOUCHSCREEN_FUJITSU
87270           To compile this driver as a module, choose M here: the
87271           module will be called fujitsu-ts.
87272
87273 +config TOUCHSCREEN_S3C2410
87274 +       tristate "Samsung S3C2410 touchscreen input driver"
87275 +       depends on ARCH_S3C2410 && INPUT && INPUT_TOUCHSCREEN
87276 +       select SERIO
87277 +       select TOUCHSCREEN_FILTER
87278 +       help
87279 +         Say Y here if you have the s3c2410 touchscreen.
87280 +
87281 +         If unsure, say N.
87282 +
87283 +         To compile this driver as a module, choose M here: the
87284 +         module will be called s3c2410_ts.
87285 +
87286 +config TOUCHSCREEN_S3C2410_DEBUG
87287 +       boolean "Samsung S3C2410 touchscreen debug messages"
87288 +       depends on TOUCHSCREEN_S3C2410
87289 +       help
87290 +         Select this if you want debug messages
87291 +
87292  config TOUCHSCREEN_GUNZE
87293         tristate "Gunze AHL-51S touchscreen"
87294         select SERIO
87295 @@ -376,4 +439,15 @@ config TOUCHSCREEN_TOUCHIT213
87296           To compile this driver as a module, choose M here: the
87297           module will be called touchit213.
87298
87299 +config TOUCHSCREEN_PCAP7200
87300 +       tristate "EETI Projected capacitive touchscreen controller"
87301 +       help
87302 +         Say Y here if you have the EETI PCAP7200 touchscreen
87303 +         controller chip in your system.
87304 +
87305 +         If unsure, say N.
87306 +
87307 +         To compile this driver as a module, choose M here: the
87308 +         module will be called pcap7200.
87309  endif
87310 +
87311 Index: linux-2.6.28/drivers/input/touchscreen/Makefile
87312 ===================================================================
87313 --- linux-2.6.28.orig/drivers/input/touchscreen/Makefile        2008-12-25 00:26:37.000000000 +0100
87314 +++ linux-2.6.28/drivers/input/touchscreen/Makefile     2009-01-02 00:01:56.000000000 +0100
87315 @@ -31,3 +31,10 @@ wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9705)       +
87316  wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o
87317  wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o
87318  obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE)     += mainstone-wm97xx.o
87319 +obj-$(CONFIG_TOUCHSCREEN_S3C2410)      += s3c2410_ts.o
87320 +obj-$(CONFIG_TOUCHSCREEN_FILTER)       += ts_filter.o
87321 +obj-$(CONFIG_TOUCHSCREEN_FILTER_GROUP) += ts_filter_group.o
87322 +obj-$(CONFIG_TOUCHSCREEN_FILTER_LINEAR)        += ts_filter_linear.o
87323 +obj-$(CONFIG_TOUCHSCREEN_FILTER_MEDIAN)        += ts_filter_median.o
87324 +obj-$(CONFIG_TOUCHSCREEN_FILTER_MEAN)  += ts_filter_mean.o
87325 +obj-$(CONFIG_TOUCHSCREEN_PCAP7200)     += pcap7200_ts.o
87326 Index: linux-2.6.28/drivers/input/touchscreen/s3c2410_ts.c
87327 ===================================================================
87328 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
87329 +++ linux-2.6.28/drivers/input/touchscreen/s3c2410_ts.c 2009-01-02 00:01:56.000000000 +0100
87330 @@ -0,0 +1,618 @@
87331 +/*
87332 + * This program is free software; you can redistribute it and/or modify
87333 + * it under the terms of the GNU General Public License as published by
87334 + * the Free Software Foundation; either version 2 of the License, or
87335 + * (at your option) any later version.
87336 + *
87337 + * This program is distributed in the hope that it will be useful,
87338 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87339 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87340 + * GNU General Public License for more details.
87341 + *
87342 + * You should have received a copy of the GNU General Public License
87343 + * along with this program; if not, write to the Free Software
87344 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
87345 + *
87346 + * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
87347 + * iPAQ H1940 touchscreen support
87348 + *
87349 + * ChangeLog
87350 + *
87351 + * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
87352 + *      - added clock (de-)allocation code
87353 + *
87354 + * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org>
87355 + *      - h1940_ -> s3c2410 (this driver is now also used on the n30
87356 + *        machines :P)
87357 + *      - Debug messages are now enabled with the config option
87358 + *        TOUCHSCREEN_S3C2410_DEBUG
87359 + *      - Changed the way the value are read
87360 + *      - Input subsystem should now work
87361 + *      - Use ioremap and readl/writel
87362 + *
87363 + * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org>
87364 + *      - Make use of some undocumented features of the touchscreen
87365 + *        controller
87366 + *
87367 + * 2007-05-23: Harald Welte <laforge@openmoko.org>
87368 + *      - Add proper support for S32440
87369 + *
87370 + * 2008-06-23: Andy Green <andy@openmoko.com>
87371 + *      - removed averaging system
87372 + *      - added generic Touchscreen filter stuff
87373 + *
87374 + * 2008-11-27: Nelson Castillo <arhuaco@freaks-unidos.net>
87375 + *      - improve interrupt handling
87376 + */
87377 +
87378 +#include <linux/errno.h>
87379 +#include <linux/kernel.h>
87380 +#include <linux/module.h>
87381 +#include <linux/slab.h>
87382 +#include <linux/input.h>
87383 +#include <linux/init.h>
87384 +#include <linux/serio.h>
87385 +#include <linux/timer.h>
87386 +#include <linux/kfifo.h>
87387 +#include <linux/delay.h>
87388 +#include <linux/platform_device.h>
87389 +#include <linux/clk.h>
87390 +#include <asm/io.h>
87391 +#include <asm/irq.h>
87392 +
87393 +#include <mach/regs-gpio.h>
87394 +#include <mach/ts.h>
87395 +
87396 +#include <plat/regs-adc.h>
87397 +
87398 +#include <linux/ts_filter.h>
87399 +
87400 +/* For ts.dev.id.version */
87401 +#define S3C2410TSVERSION       0x0101
87402 +
87403 +#define TSC_SLEEP  (S3C2410_ADCTSC_PULL_UP_DISABLE | S3C2410_ADCTSC_XY_PST(0))
87404 +
87405 +#define WAIT4INT(x)  (((x)<<8) | \
87406 +                    S3C2410_ADCTSC_YM_SEN | \
87407 +                    S3C2410_ADCTSC_YP_SEN | \
87408 +                    S3C2410_ADCTSC_XP_SEN | \
87409 +                    S3C2410_ADCTSC_XY_PST(3))
87410 +
87411 +#define AUTOPST             (S3C2410_ADCTSC_YM_SEN | \
87412 +                     S3C2410_ADCTSC_YP_SEN | \
87413 +                     S3C2410_ADCTSC_XP_SEN | \
87414 +                     S3C2410_ADCTSC_AUTO_PST | \
87415 +                     S3C2410_ADCTSC_XY_PST(0))
87416 +
87417 +#define DEBUG_LVL    KERN_DEBUG
87418 +
87419 +MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
87420 +MODULE_DESCRIPTION("s3c2410 touchscreen driver");
87421 +MODULE_LICENSE("GPL");
87422 +
87423 +/*
87424 + * Definitions & global arrays.
87425 + */
87426 +
87427 +static char *s3c2410ts_name = "s3c2410 TouchScreen";
87428 +
87429 +#define TS_RELEASE_TIMEOUT (HZ >> 4)           /* ~ 60 milliseconds */
87430 +#define TS_EVENT_FIFO_SIZE (2 << 6) /* must be a power of 2 */
87431 +
87432 +#define TS_STATE_STANDBY 0 /* initial state */
87433 +#define TS_STATE_PRESSED 1
87434 +#define TS_STATE_RELEASE_PENDING 2
87435 +#define TS_STATE_RELEASE 3
87436 +
87437 +/*
87438 + * Per-touchscreen data.
87439 + */
87440 +
87441 +struct s3c2410ts {
87442 +       struct input_dev *dev;
87443 +       struct ts_filter *tsf[MAX_TS_FILTER_CHAIN];
87444 +       int coords[2]; /* just X and Y for us */
87445 +       int is_down;
87446 +       int state;
87447 +       struct kfifo *event_fifo;
87448 +};
87449 +
87450 +static struct s3c2410ts ts;
87451 +
87452 +static void __iomem *base_addr;
87453 +
87454 +/*
87455 + * A few low level functions.
87456 + */
87457 +
87458 +static inline void s3c2410_ts_connect(void)
87459 +{
87460 +       s3c2410_gpio_cfgpin(S3C2410_GPG12, S3C2410_GPG12_XMON);
87461 +       s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPG13_nXPON);
87462 +       s3c2410_gpio_cfgpin(S3C2410_GPG14, S3C2410_GPG14_YMON);
87463 +       s3c2410_gpio_cfgpin(S3C2410_GPG15, S3C2410_GPG15_nYPON);
87464 +}
87465 +
87466 +static void s3c2410_ts_start_adc_conversion(void)
87467 +{
87468 +       writel(S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST,
87469 +              base_addr + S3C2410_ADCTSC);
87470 +       writel(readl(base_addr + S3C2410_ADCCON) | S3C2410_ADCCON_ENABLE_START,
87471 +              base_addr + S3C2410_ADCCON);
87472 +}
87473 +
87474 +/*
87475 + * Just send the input events.
87476 + */
87477 +
87478 +enum ts_input_event {IE_DOWN = 0, IE_UP};
87479 +
87480 +static void ts_input_report(int event, int coords[])
87481 +{
87482 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
87483 +       static char *s[] = {"down", "up"};
87484 +       struct timeval tv;
87485 +
87486 +       do_gettimeofday(&tv);
87487 +#endif
87488 +
87489 +       if (event == IE_DOWN) {
87490 +               input_report_abs(ts.dev, ABS_X, coords[0]);
87491 +               input_report_abs(ts.dev, ABS_Y, coords[1]);
87492 +               input_report_key(ts.dev, BTN_TOUCH, 1);
87493 +               input_report_abs(ts.dev, ABS_PRESSURE, 1);
87494 +
87495 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
87496 +               printk(DEBUG_LVL "T:%06d %6s (X:%03d, Y:%03d)\n",
87497 +                      (int)tv.tv_usec, s[event], coords[0], coords[1]);
87498 +#endif
87499 +       } else {
87500 +               input_report_key(ts.dev, BTN_TOUCH, 0);
87501 +               input_report_abs(ts.dev, ABS_PRESSURE, 0);
87502 +
87503 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
87504 +               printk(DEBUG_LVL "T:%06d %6s\n",
87505 +                      (int)tv.tv_usec, s[event]);
87506 +#endif
87507 +       }
87508 +
87509 +       input_sync(ts.dev);
87510 +}
87511 +
87512 +/*
87513 + * Manage the state of the touchscreen.
87514 + */
87515 +
87516 +static void event_send_timer_f(unsigned long data);
87517 +
87518 +static struct timer_list event_send_timer =
87519 +               TIMER_INITIALIZER(event_send_timer_f, 0, 0);
87520 +
87521 +static void event_send_timer_f(unsigned long data)
87522 +{
87523 +       static unsigned long running;
87524 +       static int noop_counter;
87525 +       int event_type;
87526 +
87527 +       if (unlikely(test_and_set_bit(0, &running))) {
87528 +               mod_timer(&event_send_timer,
87529 +                         jiffies + TS_RELEASE_TIMEOUT);
87530 +               return;
87531 +       }
87532 +
87533 +       while (__kfifo_get(ts.event_fifo, (unsigned char *)&event_type,
87534 +                          sizeof(int))) {
87535 +               int buf[2];
87536 +
87537 +               switch (event_type) {
87538 +               case 'D':
87539 +                       if (ts.state == TS_STATE_RELEASE_PENDING)
87540 +                               /* Ignore short UP event */
87541 +                               ts.state = TS_STATE_PRESSED;
87542 +                       break;
87543 +
87544 +               case 'U':
87545 +                       ts.state = TS_STATE_RELEASE_PENDING;
87546 +                       break;
87547 +
87548 +               case 'P':
87549 +                       if (ts.is_down) /* stylus_action needs a conversion */
87550 +                               s3c2410_ts_start_adc_conversion();
87551 +
87552 +                       if (unlikely(__kfifo_get(ts.event_fifo,
87553 +                                                (unsigned char *)buf,
87554 +                                                sizeof(int) * 2)
87555 +                                    != sizeof(int) * 2))
87556 +                               goto ts_exit_error;
87557 +
87558 +                       ts_input_report(IE_DOWN, buf);
87559 +                       ts.state = TS_STATE_PRESSED;
87560 +                       break;
87561 +
87562 +               default:
87563 +                       goto ts_exit_error;
87564 +               }
87565 +
87566 +               noop_counter = 0;
87567 +       }
87568 +
87569 +       if (noop_counter++ >= 1) {
87570 +               noop_counter = 0;
87571 +               if (ts.state == TS_STATE_RELEASE_PENDING) {
87572 +                       /* We delay the UP event for a
87573 +                        * while to avoid jitter. If we get a DOWN
87574 +                        * event we do not send it. */
87575 +
87576 +                       ts_input_report(IE_UP, NULL);
87577 +                       ts.state = TS_STATE_STANDBY;
87578 +
87579 +                       if (ts.tsf[0])
87580 +                               (ts.tsf[0]->api->clear)(ts.tsf[0]);
87581 +               }
87582 +       } else {
87583 +               mod_timer(&event_send_timer, jiffies + TS_RELEASE_TIMEOUT);
87584 +       }
87585 +
87586 +       clear_bit(0, &running);
87587 +
87588 +       return;
87589 +
87590 +ts_exit_error: /* should not happen unless we have a bug */
87591 +       printk(KERN_ERR __FILE__ ": event_send_timer_f failed\n");
87592 +}
87593 +
87594 +/*
87595 + * Manage interrupts.
87596 + */
87597 +
87598 +static irqreturn_t stylus_updown(int irq, void *dev_id)
87599 +{
87600 +       unsigned long data0;
87601 +       unsigned long data1;
87602 +       int event_type;
87603 +
87604 +       data0 = readl(base_addr+S3C2410_ADCDAT0);
87605 +       data1 = readl(base_addr+S3C2410_ADCDAT1);
87606 +
87607 +       ts.is_down = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) &&
87608 +                                           (!(data1 & S3C2410_ADCDAT0_UPDOWN));
87609 +
87610 +       event_type = ts.is_down ? 'D' : 'U';
87611 +
87612 +       if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)&event_type,
87613 +                    sizeof(int)) != sizeof(int))) /* should not happen */
87614 +               printk(KERN_ERR __FILE__": stylus_updown lost event!\n");
87615 +
87616 +       if (ts.is_down)
87617 +               s3c2410_ts_start_adc_conversion();
87618 +       else
87619 +               writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC);
87620 +
87621 +       mod_timer(&event_send_timer, jiffies + 1);
87622 +
87623 +       return IRQ_HANDLED;
87624 +}
87625 +
87626 +static irqreturn_t stylus_action(int irq, void *dev_id)
87627 +{
87628 +       int buf[3];
87629 +
87630 +       /* grab the ADC results */
87631 +       ts.coords[0] = readl(base_addr + S3C2410_ADCDAT0) &
87632 +                                                   S3C2410_ADCDAT0_XPDATA_MASK;
87633 +       ts.coords[1] = readl(base_addr + S3C2410_ADCDAT1) &
87634 +                                                   S3C2410_ADCDAT1_YPDATA_MASK;
87635 +
87636 +       if (ts.tsf[0]) { /* filtering is enabled, don't use raw directly */
87637 +               switch ((ts.tsf[0]->api->process)(ts.tsf[0], &ts.coords[0])) {
87638 +               case 0: /*
87639 +                        * no real sample came out of processing yet,
87640 +                        * get another raw result to feed it
87641 +                        */
87642 +                       s3c2410_ts_start_adc_conversion();
87643 +                       return IRQ_HANDLED;
87644 +               case 1: /* filters are ready to deliver a sample */
87645 +                       (ts.tsf[0]->api->scale)(ts.tsf[0], &ts.coords[0]);
87646 +                       break;
87647 +               case -1:
87648 +                       /* error in filters, ignore the event */
87649 +                       (ts.tsf[0]->api->clear)(ts.tsf[0]);
87650 +                       writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
87651 +                       return IRQ_HANDLED;
87652 +               default:
87653 +                       printk(KERN_ERR":stylus_action error\n");
87654 +               }
87655 +       }
87656 +
87657 +       /* We use a buffer because want an atomic operation */
87658 +       buf[0] = 'P';
87659 +       buf[1] = ts.coords[0];
87660 +       buf[2] = ts.coords[1];
87661 +
87662 +       if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)buf,
87663 +                    sizeof(int) * 3) != sizeof(int) * 3))
87664 +               /* should not happen */
87665 +                       printk(KERN_ERR":stylus_action error\n");
87666 +
87667 +       writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
87668 +       mod_timer(&event_send_timer, jiffies + 1);
87669 +
87670 +       return IRQ_HANDLED;
87671 +}
87672 +
87673 +static struct clk      *adc_clock;
87674 +
87675 +/*
87676 + * The functions for inserting/removing us as a module.
87677 + */
87678 +
87679 +static int __init s3c2410ts_probe(struct platform_device *pdev)
87680 +{
87681 +       int rc;
87682 +       struct s3c2410_ts_mach_info *info;
87683 +       struct input_dev *input_dev;
87684 +       int ret = 0;
87685 +
87686 +       dev_info(&pdev->dev, "Starting\n");
87687 +
87688 +       info = (struct s3c2410_ts_mach_info *)pdev->dev.platform_data;
87689 +
87690 +       if (!info)
87691 +       {
87692 +               dev_err(&pdev->dev, "Hm... too bad: no platform data for ts\n");
87693 +               return -EINVAL;
87694 +       }
87695 +
87696 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
87697 +       printk(DEBUG_LVL "Entering s3c2410ts_init\n");
87698 +#endif
87699 +
87700 +       adc_clock = clk_get(NULL, "adc");
87701 +       if (!adc_clock) {
87702 +               dev_err(&pdev->dev, "failed to get adc clock source\n");
87703 +               return -ENOENT;
87704 +       }
87705 +       clk_enable(adc_clock);
87706 +
87707 +#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
87708 +       printk(DEBUG_LVL "got and enabled clock\n");
87709 +#endif
87710 +
87711 +       base_addr = ioremap(S3C2410_PA_ADC,0x20);
87712 +       if (base_addr == NULL) {
87713 +               dev_err(&pdev->dev, "Failed to remap register block\n");
87714 +               ret = -ENOMEM;
87715 +               goto bail0;
87716 +       }
87717 +
87718 +
87719 +       /* If we acutally are a S3C2410: Configure GPIOs */
87720 +       if (!strcmp(pdev->name, "s3c2410-ts"))
87721 +               s3c2410_ts_connect();
87722 +
87723 +       if ((info->presc & 0xff) > 0)
87724 +               writel(S3C2410_ADCCON_PRSCEN |
87725 +                      S3C2410_ADCCON_PRSCVL(info->presc&0xFF),
87726 +                                                   base_addr + S3C2410_ADCCON);
87727 +       else
87728 +               writel(0, base_addr+S3C2410_ADCCON);
87729 +
87730 +       /* Initialise registers */
87731 +       if ((info->delay & 0xffff) > 0)
87732 +               writel(info->delay & 0xffff,  base_addr + S3C2410_ADCDLY);
87733 +
87734 +       writel(WAIT4INT(0), base_addr + S3C2410_ADCTSC);
87735 +
87736 +       /* Initialise input stuff */
87737 +       memset(&ts, 0, sizeof(struct s3c2410ts));
87738 +       input_dev = input_allocate_device();
87739 +
87740 +       if (!input_dev) {
87741 +               dev_err(&pdev->dev, "Unable to allocate the input device\n");
87742 +               ret = -ENOMEM;
87743 +               goto bail1;
87744 +       }
87745 +
87746 +       ts.dev = input_dev;
87747 +       ts.dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) |
87748 +                          BIT_MASK(EV_ABS);
87749 +       ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
87750 +       input_set_abs_params(ts.dev, ABS_X, 0, 0x3FF, 0, 0);
87751 +       input_set_abs_params(ts.dev, ABS_Y, 0, 0x3FF, 0, 0);
87752 +       input_set_abs_params(ts.dev, ABS_PRESSURE, 0, 1, 0, 0);
87753 +
87754 +       ts.dev->name = s3c2410ts_name;
87755 +       ts.dev->id.bustype = BUS_RS232;
87756 +       ts.dev->id.vendor = 0xDEAD;
87757 +       ts.dev->id.product = 0xBEEF;
87758 +       ts.dev->id.version = S3C2410TSVERSION;
87759 +       ts.state = TS_STATE_STANDBY;
87760 +       ts.event_fifo = kfifo_alloc(TS_EVENT_FIFO_SIZE, GFP_KERNEL, NULL);
87761 +       if (IS_ERR(ts.event_fifo)) {
87762 +               ret = -EIO;
87763 +               goto bail2;
87764 +       }
87765 +
87766 +       /* create the filter chain set up for the 2 coordinates we produce */
87767 +       ret = ts_filter_create_chain(
87768 +               pdev, (struct ts_filter_api **)&info->filter_sequence,
87769 +               (void *)&info->filter_config, ts.tsf, ARRAY_SIZE(ts.coords));
87770 +       if (ret)
87771 +               dev_info(&pdev->dev, "%d filter(s) initialized\n", ret);
87772 +       else /* this is OK, just means there won't be any filtering */
87773 +               dev_info(&pdev->dev, "Unfiltered output selected\n");
87774 +
87775 +       if (ts.tsf[0])
87776 +               (ts.tsf[0]->api->clear)(ts.tsf[0]);
87777 +       else
87778 +               dev_info(&pdev->dev, "No filtering\n");
87779 +
87780 +       /* Get irqs */
87781 +       if (request_irq(IRQ_ADC, stylus_action, IRQF_SAMPLE_RANDOM,
87782 +                                                   "s3c2410_action", ts.dev)) {
87783 +               dev_err(&pdev->dev, "Could not allocate ts IRQ_ADC !\n");
87784 +               iounmap(base_addr);
87785 +               ret = -EIO;
87786 +               goto bail3;
87787 +       }
87788 +       if (request_irq(IRQ_TC, stylus_updown, IRQF_SAMPLE_RANDOM,
87789 +                       "s3c2410_action", ts.dev)) {
87790 +               dev_err(&pdev->dev, "Could not allocate ts IRQ_TC !\n");
87791 +               free_irq(IRQ_ADC, ts.dev);
87792 +               iounmap(base_addr);
87793 +               ret = -EIO;
87794 +               goto bail4;
87795 +       }
87796 +
87797 +       dev_info(&pdev->dev, "successfully loaded\n");
87798 +
87799 +       /* All went ok, so register to the input system */
87800 +       rc = input_register_device(ts.dev);
87801 +       if (rc) {
87802 +               ret = -EIO;
87803 +               goto bail5;
87804 +       }
87805 +
87806 +       return 0;
87807 +
87808 +bail5:
87809 +       free_irq(IRQ_TC, ts.dev);
87810 +       free_irq(IRQ_ADC, ts.dev);
87811 +       clk_disable(adc_clock);
87812 +       iounmap(base_addr);
87813 +       disable_irq(IRQ_TC);
87814 +bail4:
87815 +       disable_irq(IRQ_ADC);
87816 +bail3:
87817 +       ts_filter_destroy_chain(pdev, ts.tsf);
87818 +       kfifo_free(ts.event_fifo);
87819 +bail2:
87820 +       input_unregister_device(ts.dev);
87821 +bail1:
87822 +       iounmap(base_addr);
87823 +bail0:
87824 +
87825 +       return ret;
87826 +}
87827 +
87828 +static int s3c2410ts_remove(struct platform_device *pdev)
87829 +{
87830 +       disable_irq(IRQ_ADC);
87831 +       disable_irq(IRQ_TC);
87832 +       free_irq(IRQ_TC,ts.dev);
87833 +       free_irq(IRQ_ADC,ts.dev);
87834 +
87835 +       if (adc_clock) {
87836 +               clk_disable(adc_clock);
87837 +               clk_put(adc_clock);
87838 +               adc_clock = NULL;
87839 +       }
87840 +
87841 +       input_unregister_device(ts.dev);
87842 +       iounmap(base_addr);
87843 +
87844 +       ts_filter_destroy_chain(pdev, ts.tsf);
87845 +
87846 +       kfifo_free(ts.event_fifo);
87847 +
87848 +       return 0;
87849 +}
87850 +
87851 +#ifdef CONFIG_PM
87852 +static int s3c2410ts_suspend(struct platform_device *pdev, pm_message_t state)
87853 +{
87854 +       writel(TSC_SLEEP, base_addr+S3C2410_ADCTSC);
87855 +       writel(readl(base_addr+S3C2410_ADCCON) | S3C2410_ADCCON_STDBM,
87856 +              base_addr+S3C2410_ADCCON);
87857 +
87858 +       disable_irq(IRQ_ADC);
87859 +       disable_irq(IRQ_TC);
87860 +
87861 +       clk_disable(adc_clock);
87862 +
87863 +       return 0;
87864 +}
87865 +
87866 +static int s3c2410ts_resume(struct platform_device *pdev)
87867 +{
87868 +       struct s3c2410_ts_mach_info *info =
87869 +               ( struct s3c2410_ts_mach_info *)pdev->dev.platform_data;
87870 +
87871 +       clk_enable(adc_clock);
87872 +       mdelay(1);
87873 +
87874 +       if (ts.tsf[0])
87875 +               (ts.tsf[0]->api->clear)(ts.tsf[0]);
87876 +
87877 +       enable_irq(IRQ_ADC);
87878 +       enable_irq(IRQ_TC);
87879 +
87880 +       if ((info->presc&0xff) > 0)
87881 +               writel(S3C2410_ADCCON_PRSCEN |
87882 +                      S3C2410_ADCCON_PRSCVL(info->presc&0xFF),
87883 +                                                     base_addr+S3C2410_ADCCON);
87884 +       else
87885 +               writel(0,base_addr+S3C2410_ADCCON);
87886 +
87887 +       /* Initialise registers */
87888 +       if ((info->delay & 0xffff) > 0)
87889 +               writel(info->delay & 0xffff,  base_addr+S3C2410_ADCDLY);
87890 +
87891 +       writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC);
87892 +
87893 +       return 0;
87894 +}
87895 +
87896 +#else
87897 +#define s3c2410ts_suspend NULL
87898 +#define s3c2410ts_resume  NULL
87899 +#endif
87900 +
87901 +static struct platform_driver s3c2410ts_driver = {
87902 +       .driver         = {
87903 +              .name   = "s3c2410-ts",
87904 +              .owner  = THIS_MODULE,
87905 +       },
87906 +       .probe          = s3c2410ts_probe,
87907 +       .remove         = s3c2410ts_remove,
87908 +       .suspend        = s3c2410ts_suspend,
87909 +       .resume         = s3c2410ts_resume,
87910 +
87911 +};
87912 +
87913 +static struct platform_driver s3c2440ts_driver = {
87914 +       .driver         = {
87915 +              .name   = "s3c2440-ts",
87916 +              .owner  = THIS_MODULE,
87917 +       },
87918 +       .probe          = s3c2410ts_probe,
87919 +       .remove         = s3c2410ts_remove,
87920 +       .suspend        = s3c2410ts_suspend,
87921 +       .resume         = s3c2410ts_resume,
87922 +
87923 +};
87924 +
87925 +static int __init s3c2410ts_init(void)
87926 +{
87927 +       int rc;
87928 +
87929 +       rc = platform_driver_register(&s3c2410ts_driver);
87930 +       if (rc < 0)
87931 +               return rc;
87932 +
87933 +       rc = platform_driver_register(&s3c2440ts_driver);
87934 +       if (rc < 0)
87935 +               platform_driver_unregister(&s3c2410ts_driver);
87936 +
87937 +       return rc;
87938 +}
87939 +
87940 +static void __exit s3c2410ts_exit(void)
87941 +{
87942 +       platform_driver_unregister(&s3c2440ts_driver);
87943 +       platform_driver_unregister(&s3c2410ts_driver);
87944 +}
87945 +
87946 +module_init(s3c2410ts_init);
87947 +module_exit(s3c2410ts_exit);
87948 +
87949 Index: linux-2.6.28/drivers/input/touchscreen/ts_filter.c
87950 ===================================================================
87951 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
87952 +++ linux-2.6.28/drivers/input/touchscreen/ts_filter.c  2009-01-02 00:01:56.000000000 +0100
87953 @@ -0,0 +1,64 @@
87954 +/*
87955 + * This program is free software; you can redistribute it and/or modify
87956 + * it under the terms of the GNU General Public License as published by
87957 + * the Free Software Foundation; either version 2 of the License, or
87958 + * (at your option) any later version.
87959 + *
87960 + * This program is distributed in the hope that it will be useful,
87961 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
87962 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
87963 + * GNU General Public License for more details.
87964 + *
87965 + * You should have received a copy of the GNU General Public License
87966 + * along with this program; if not, write to the Free Software
87967 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
87968 + *
87969 + * Copyright (c) 2008 Andy Green <andy@openmoko.com>
87970 + */
87971 +
87972 +#include <linux/kernel.h>
87973 +#include <linux/device.h>
87974 +#include <linux/ts_filter.h>
87975 +
87976 +int ts_filter_create_chain(struct platform_device *pdev,
87977 +                          struct ts_filter_api **api, void **config,
87978 +                          struct ts_filter **list, int count_coords)
87979 +{
87980 +       int count = 0;
87981 +       struct ts_filter *last = NULL;
87982 +
87983 +       if (!api)
87984 +               return 0;
87985 +
87986 +       while (*api && count < MAX_TS_FILTER_CHAIN) {
87987 +               *list = ((*api)->create)(pdev, *config++, count_coords);
87988 +               if (!*list) {
87989 +                       printk(KERN_ERR "Filter %d failed init\n", count);
87990 +                       return count;
87991 +               }
87992 +               (*list)->api = *api++;
87993 +               if (last)
87994 +                       last->next = *list;
87995 +               last = *list;
87996 +               list++;
87997 +               count++;
87998 +       }
87999 +
88000 +       return count;
88001 +}
88002 +EXPORT_SYMBOL_GPL(ts_filter_create_chain);
88003 +
88004 +void ts_filter_destroy_chain(struct platform_device *pdev,
88005 +                            struct ts_filter **list)
88006 +{
88007 +       struct ts_filter **first;
88008 +       int count = 0;
88009 +
88010 +       first = list;
88011 +       while (*list && count++ < MAX_TS_FILTER_CHAIN) {
88012 +               ((*list)->api->destroy)(pdev, *list);
88013 +               list++;
88014 +       }
88015 +       *first = NULL;
88016 +}
88017 +EXPORT_SYMBOL_GPL(ts_filter_destroy_chain);
88018 Index: linux-2.6.28/drivers/input/touchscreen/ts_filter_group.c
88019 ===================================================================
88020 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
88021 +++ linux-2.6.28/drivers/input/touchscreen/ts_filter_group.c    2009-01-02 00:01:56.000000000 +0100
88022 @@ -0,0 +1,219 @@
88023 +/*
88024 + * This program is free software; you can redistribute it and/or modify
88025 + * it under the terms of the GNU General Public License as published by
88026 + * the Free Software Foundation; either version 2 of the License, or
88027 + * (at your option) any later version.
88028 + *
88029 + * This program is distributed in the hope that it will be useful,
88030 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
88031 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
88032 + * GNU General Public License for more details.
88033 + *
88034 + * You should have received a copy of the GNU General Public License
88035 + * along with this program; if not, write to the Free Software
88036 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
88037 + *
88038 + * Copyright (C) 2008 by Openmoko, Inc.
88039 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
88040 + * All rights reserved.
88041 + *
88042 + * This filter is useful to reject samples that are not reliable. We consider
88043 + * that a sample is not reliable if it deviates form the Majority.
88044 + *
88045 + * 1) We collect S samples.
88046 + *
88047 + * 2) For each dimension:
88048 + *
88049 + *  - We sort the points.
88050 + *  - Points that are "close enough" are considered to be in the same set.
88051 + *  - We choose the set with more elements. If more than "threshold"
88052 + *    points are in this set we use the first and the last point of the set
88053 + *    to define the valid range for this dimension [min, max], otherwise we
88054 + *    discard all the points and go to step 1.
88055 + *
88056 + * 3) We consider the unsorted S samples and try to feed them to the next
88057 + *    filter in the chain. If one of the points of each sample
88058 + *    is not in the allowed range for its dimension, we discard the sample.
88059 + *
88060 + */
88061 +
88062 +#include <linux/kernel.h>
88063 +#include <linux/slab.h>
88064 +#include <linux/sort.h>
88065 +#include <linux/ts_filter_group.h>
88066 +
88067 +static void ts_filter_group_clear_internal(struct ts_filter_group *tsfg,
88068 +                                          int attempts)
88069 +{
88070 +       tsfg->N = 0;
88071 +       tsfg->tries_left = attempts;
88072 +}
88073 +
88074 +static void ts_filter_group_clear(struct ts_filter *tsf)
88075 +{
88076 +       struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
88077 +
88078 +       ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
88079 +
88080 +       if (tsf->next) /* chain */
88081 +               (tsf->next->api->clear)(tsf->next);
88082 +}
88083 +
88084 +static struct ts_filter *ts_filter_group_create(struct platform_device *pdev,
88085 +                                               void *conf, int count_coords)
88086 +{
88087 +       struct ts_filter_group *tsfg;
88088 +       int i;
88089 +
88090 +       BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
88091 +
88092 +       tsfg = kzalloc(sizeof(struct ts_filter_group), GFP_KERNEL);
88093 +       if (!tsfg)
88094 +               return NULL;
88095 +
88096 +       tsfg->config = (struct ts_filter_group_configuration *)conf;
88097 +       tsfg->tsf.count_coords = count_coords;
88098 +
88099 +       BUG_ON(tsfg->config->attempts <= 0);
88100 +
88101 +       tsfg->samples[0] = kmalloc((2 + count_coords) * sizeof(int) *
88102 +                                  tsfg->config->extent, GFP_KERNEL);
88103 +       if (!tsfg->samples[0]) {
88104 +               kfree(tsfg);
88105 +               return NULL;
88106 +       }
88107 +       for (i = 1; i < count_coords; ++i)
88108 +               tsfg->samples[i] = tsfg->samples[0] + i * tsfg->config->extent;
88109 +       tsfg->sorted_samples = tsfg->samples[0] + count_coords *
88110 +                              tsfg->config->extent;
88111 +       tsfg->group_size = tsfg->samples[0] + (1 + count_coords) *
88112 +                              tsfg->config->extent;
88113 +
88114 +       ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
88115 +
88116 +       printk(KERN_INFO"  Created group ts filter len %d depth %d close %d "
88117 +                       "thresh %d\n", tsfg->config->extent, count_coords,
88118 +                       tsfg->config->close_enough, tsfg->config->threshold);
88119 +
88120 +       return &tsfg->tsf;
88121 +}
88122 +
88123 +static void ts_filter_group_destroy(struct platform_device *pdev,
88124 +                                   struct ts_filter *tsf)
88125 +{
88126 +       struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
88127 +
88128 +       kfree(tsfg->samples[0]); /* first guy has pointer from kmalloc */
88129 +       kfree(tsf);
88130 +}
88131 +
88132 +static void ts_filter_group_scale(struct ts_filter *tsf, int *coords)
88133 +{
88134 +       if (tsf->next)
88135 +               (tsf->next->api->scale)(tsf->next, coords);
88136 +}
88137 +
88138 +static int int_cmp(const void *_a, const void *_b)
88139 +{
88140 +       const int *a = _a;
88141 +       const int *b = _b;
88142 +
88143 +       if (*a > *b)
88144 +               return 1;
88145 +       if (*a < *b)
88146 +               return -1;
88147 +       return 0;
88148 +}
88149 +
88150 +static int ts_filter_group_process(struct ts_filter *tsf, int *coords)
88151 +{
88152 +       struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
88153 +       int n;
88154 +       int i;
88155 +       int ret = 0; /* ask for more samples by default */
88156 +
88157 +       BUG_ON(tsfg->N >= tsfg->config->extent);
88158 +
88159 +       for (n = 0; n < tsf->count_coords; n++)
88160 +               tsfg->samples[n][tsfg->N] = coords[n];
88161 +
88162 +       if (++tsfg->N < tsfg->config->extent)
88163 +               return 0;       /* we meed more samples */
88164 +
88165 +       for (n = 0; n < tsfg->tsf.count_coords; n++) {
88166 +               int *v = tsfg->sorted_samples;
88167 +               int ngroups = 0;
88168 +               int best_size;
88169 +               int best_idx = 0;
88170 +               int idx = 0;
88171 +
88172 +               memcpy(v, tsfg->samples[n], tsfg->N * sizeof(int));
88173 +               sort(v, tsfg->N, sizeof(int), int_cmp, NULL);
88174 +
88175 +               tsfg->group_size[0] = 1;
88176 +               for (i = 1; i < tsfg->N; ++i) {
88177 +                       if (v[i] - v[i - 1] <= tsfg->config->close_enough)
88178 +                               tsfg->group_size[ngroups]++;
88179 +                       else
88180 +                               tsfg->group_size[++ngroups] = 1;
88181 +               }
88182 +               ngroups++;
88183 +
88184 +               best_size = tsfg->group_size[0];
88185 +               for (i = 1; i < ngroups; i++) {
88186 +                       idx += tsfg->group_size[i - 1];
88187 +                       if (best_size < tsfg->group_size[i]) {
88188 +                               best_size = tsfg->group_size[i];
88189 +                               best_idx = idx;
88190 +                       }
88191 +               }
88192 +
88193 +               if (best_size < tsfg->config->threshold) {
88194 +                       /* this set is not good enough for us */
88195 +                       if (--tsfg->tries_left) {
88196 +                               ts_filter_group_clear_internal
88197 +                                       (tsfg, tsfg->tries_left);
88198 +                               return 0; /* ask for more samples */
88199 +                       }
88200 +                       return -1; /* we give up */
88201 +               }
88202 +
88203 +               tsfg->range_min[n] = v[best_idx];
88204 +               tsfg->range_max[n] = v[best_idx + best_size - 1];
88205 +       }
88206 +
88207 +       BUG_ON(!tsf->next);
88208 +
88209 +       for (i = 0; i < tsfg->N; ++i) {
88210 +               int r;
88211 +
88212 +               for (n = 0; n < tsfg->tsf.count_coords; ++n) {
88213 +                       coords[n] = tsfg->samples[n][i];
88214 +                       if (coords[n] < tsfg->range_min[n] ||
88215 +                           coords[n] > tsfg->range_max[n])
88216 +                               break;
88217 +               }
88218 +
88219 +               if (n != tsfg->tsf.count_coords) /* sample not OK */
88220 +                       continue;
88221 +
88222 +               r = (tsf->next->api->process)(tsf->next, coords);
88223 +               if (r)  {
88224 +                       ret = r;
88225 +                       break;
88226 +               }
88227 +       }
88228 +
88229 +       ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
88230 +
88231 +       return ret;
88232 +}
88233 +
88234 +struct ts_filter_api ts_filter_group_api = {
88235 +       .create = ts_filter_group_create,
88236 +       .destroy = ts_filter_group_destroy,
88237 +       .clear = ts_filter_group_clear,
88238 +       .process = ts_filter_group_process,
88239 +       .scale = ts_filter_group_scale,
88240 +};
88241 +
88242 Index: linux-2.6.28/drivers/input/touchscreen/ts_filter_linear.c
88243 ===================================================================
88244 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
88245 +++ linux-2.6.28/drivers/input/touchscreen/ts_filter_linear.c   2009-01-02 00:01:56.000000000 +0100
88246 @@ -0,0 +1,178 @@
88247 +/*
88248 + * This program is free software; you can redistribute it and/or modify
88249 + * it under the terms of the GNU General Public License as published by
88250 + * the Free Software Foundation; version 2 of the License, or
88251 + * (at your option) any later version.
88252 + *
88253 + * This program is distributed in the hope that it will be useful,
88254 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
88255 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
88256 + * GNU General Public License for more details.
88257 + *
88258 + * You should have received a copy of the GNU General Public License
88259 + * along with this program; if not, write to the Free Software
88260 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
88261 + *
88262 + * Copyright (C) 2008 by Openmoko, Inc.
88263 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
88264 + * All rights reserved.
88265 + *
88266 + * Linearly scale touchscreen values.
88267 + *
88268 + * Expose the TS_FILTER_LINEAR_NCONSTANTS for the linear transformation
88269 + * using sysfs.
88270 + *
88271 + */
88272 +
88273 +#include <linux/ts_filter_linear.h>
88274 +#include <linux/kernel.h>
88275 +#include <linux/slab.h>
88276 +#include <linux/string.h>
88277 +
88278 +
88279 +/*
88280 + * sysfs functions
88281 + */
88282 +
88283 +
88284 +static ssize_t const_attr_show(struct kobject *kobj,
88285 +                              struct attribute *attr,
88286 +                              char *buf)
88287 +{
88288 +       struct const_attribute *a = to_const_attr(attr);
88289 +
88290 +       return a->show(to_const_obj(kobj), a, buf);
88291 +}
88292 +
88293 +static ssize_t const_attr_store(struct kobject *kobj,
88294 +                               struct attribute *attr,
88295 +                               const char *buf, size_t len)
88296 +{
88297 +       struct const_attribute *a = to_const_attr(attr);
88298 +
88299 +       return a->store(to_const_obj(kobj), a, buf, len);
88300 +}
88301 +
88302 +static struct sysfs_ops const_sysfs_ops = {
88303 +       .show =         const_attr_show,
88304 +       .store =        const_attr_store,
88305 +};
88306 +
88307 +static void const_release(struct kobject *kobj)
88308 +{
88309 +       kfree(to_const_obj(kobj)->tsfl);
88310 +}
88311 +
88312 +static ssize_t const_show(struct const_obj *obj, struct const_attribute *attr,
88313 +                         char *buf)
88314 +{
88315 +       int who;
88316 +
88317 +       sscanf(attr->attr.name, "%d", &who);
88318 +       return sprintf(buf, "%d\n", obj->tsfl->constants[who]);
88319 +}
88320 +
88321 +static ssize_t const_store(struct const_obj *obj, struct const_attribute *attr,
88322 +                          const char *buf, size_t count)
88323 +{
88324 +       int who;
88325 +
88326 +       sscanf(attr->attr.name, "%d", &who);
88327 +       sscanf(buf, "%d", &obj->tsfl->constants[who]);
88328 +       return count;
88329 +}
88330 +
88331 +/*
88332 + * filter functions
88333 + */
88334 +
88335 +static struct ts_filter *ts_filter_linear_create(struct platform_device *pdev,
88336 +                                                void *conf, int count_coords)
88337 +{
88338 +       struct ts_filter_linear *tsfl;
88339 +       int i;
88340 +       int ret;
88341 +
88342 +       tsfl = kzalloc(sizeof(struct ts_filter_linear), GFP_KERNEL);
88343 +       if (!tsfl)
88344 +               return NULL;
88345 +
88346 +       tsfl->config = (struct ts_filter_linear_configuration *)conf;
88347 +       tsfl->tsf.count_coords = count_coords;
88348 +
88349 +       for (i = 0; i < TS_FILTER_LINEAR_NCONSTANTS; ++i) {
88350 +               tsfl->constants[i] = tsfl->config->constants[i];
88351 +
88352 +               /* sysfs */
88353 +               sprintf(tsfl->attr_names[i], "%d", i);
88354 +               tsfl->kattrs[i].attr.name = tsfl->attr_names[i];
88355 +               tsfl->kattrs[i].attr.mode = 0666;
88356 +               tsfl->kattrs[i].show = const_show;
88357 +               tsfl->kattrs[i].store = const_store;
88358 +               tsfl->attrs[i] = &tsfl->kattrs[i].attr;
88359 +       }
88360 +       tsfl->attrs[i] = NULL;
88361 +
88362 +       tsfl->const_ktype.sysfs_ops = &const_sysfs_ops;
88363 +       tsfl->const_ktype.release = const_release;
88364 +       tsfl->const_ktype.default_attrs = tsfl->attrs;
88365 +       tsfl->c_obj.tsfl = tsfl; /* kernel frees tsfl in const_release */
88366 +
88367 +       /* TODO: /sys/ts-calibration is not OK */
88368 +       ret = kobject_init_and_add(&tsfl->c_obj.kobj, &tsfl->const_ktype,
88369 +                                  &pdev->dev.kobj, "calibration");
88370 +       if (ret) {
88371 +               kobject_put(&tsfl->c_obj.kobj);
88372 +               return NULL;
88373 +       }
88374 +
88375 +       printk(KERN_INFO"  Created Linear ts filter depth %d\n", count_coords);
88376 +
88377 +       return &tsfl->tsf;
88378 +}
88379 +
88380 +static void ts_filter_linear_destroy(struct platform_device *pdev,
88381 +                                    struct ts_filter *tsf)
88382 +{
88383 +       struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf;
88384 +
88385 +       /* kernel frees tsfl in const_release */
88386 +       kobject_put(&tsfl->c_obj.kobj);
88387 +}
88388 +
88389 +static void ts_filter_linear_clear(struct ts_filter *tsf)
88390 +{
88391 +       if (tsf->next) /* chain */
88392 +               (tsf->next->api->clear)(tsf->next);
88393 +}
88394 +
88395 +
88396 +static void ts_filter_linear_scale(struct ts_filter *tsf, int *coords)
88397 +{
88398 +       struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf;
88399 +       int *k = tsfl->constants;
88400 +       int c0 = coords[tsfl->config->coord0];
88401 +       int c1 = coords[tsfl->config->coord1];
88402 +
88403 +       coords[tsfl->config->coord0] = (k[2] + k[0] * c0 + k[1] * c1) / k[6];
88404 +       coords[tsfl->config->coord1] = (k[5] + k[3] * c0 + k[4] * c1) / k[6];
88405 +
88406 +       if (tsf->next)
88407 +               (tsf->next->api->scale)(tsf->next, coords);
88408 +}
88409 +
88410 +static int ts_filter_linear_process(struct ts_filter *tsf, int *coords)
88411 +{
88412 +       if (tsf->next)
88413 +               return (tsf->next->api->process)(tsf->next, coords);
88414 +
88415 +       return 1;
88416 +}
88417 +
88418 +struct ts_filter_api ts_filter_linear_api = {
88419 +       .create = ts_filter_linear_create,
88420 +       .destroy = ts_filter_linear_destroy,
88421 +       .clear = ts_filter_linear_clear,
88422 +       .process = ts_filter_linear_process,
88423 +       .scale = ts_filter_linear_scale,
88424 +};
88425 Index: linux-2.6.28/drivers/input/touchscreen/ts_filter_mean.c
88426 ===================================================================
88427 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
88428 +++ linux-2.6.28/drivers/input/touchscreen/ts_filter_mean.c     2009-01-02 00:01:56.000000000 +0100
88429 @@ -0,0 +1,172 @@
88430 +/*
88431 + * This program is free software; you can redistribute it and/or modify
88432 + * it under the terms of the GNU General Public License as published by
88433 + * the Free Software Foundation; either version 2 of the License, or
88434 + * (at your option) any later version.
88435 + *
88436 + * This program is distributed in the hope that it will be useful,
88437 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
88438 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
88439 + * GNU General Public License for more details.
88440 + *
88441 + * You should have received a copy of the GNU General Public License
88442 + * along with this program; if not, write to the Free Software
88443 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
88444 + *
88445 + * Copyright (c) 2008 Andy Green <andy@openmoko.com>
88446 + *
88447 + *
88448 + * Mean has no effect if the samples are changing by more that the
88449 + * threshold set by averaging_threshold in the configuration.
88450 + *
88451 + * However while samples come in that don't go outside this threshold from
88452 + * the last reported sample, Mean replaces the samples with a simple mean
88453 + * of a configurable number of samples (set by bits_filter_length in config,
88454 + * which is 2^n, so 5 there makes 32 sample averaging).
88455 + *
88456 + * Mean works well if the input data is already good quality, reducing + / - 1
88457 + * sample jitter when the stylus is still, or moving very slowly, without
88458 + * introducing abrupt transitions or reducing ability to follow larger
88459 + * movements.  If you set the threshold higher than the dynamic range of the
88460 + * coordinates, you can just use it as a simple mean average.
88461 + */
88462 +
88463 +#include <linux/errno.h>
88464 +#include <linux/kernel.h>
88465 +#include <linux/slab.h>
88466 +#include <linux/ts_filter_mean.h>
88467 +
88468 +static void ts_filter_mean_clear_internal(struct ts_filter *tsf)
88469 +{
88470 +       struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
88471 +       int n;
88472 +
88473 +       for (n = 0; n < tsfs->tsf.count_coords; n++) {
88474 +               tsfs->fhead[n] = 0;
88475 +               tsfs->ftail[n] = 0;
88476 +               tsfs->lowpass[n] = 0;
88477 +       }
88478 +}
88479 +
88480 +static void ts_filter_mean_clear(struct ts_filter *tsf)
88481 +{
88482 +       ts_filter_mean_clear_internal(tsf);
88483 +
88484 +       if (tsf->next) /* chain */
88485 +               (tsf->next->api->clear)(tsf->next);
88486 +}
88487 +
88488 +static struct ts_filter *ts_filter_mean_create(struct platform_device *pdev,
88489 +                                              void *config, int count_coords)
88490 +{
88491 +       int *p;
88492 +       int n;
88493 +       struct ts_filter_mean *tsfs = kzalloc(
88494 +                                 sizeof(struct ts_filter_mean), GFP_KERNEL);
88495 +
88496 +       if (!tsfs)
88497 +               return NULL;
88498 +
88499 +       BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
88500 +       tsfs->tsf.count_coords = count_coords;
88501 +
88502 +       tsfs->config = (struct ts_filter_mean_configuration *)config;
88503 +
88504 +       tsfs->config->extent = 1 << tsfs->config->bits_filter_length;
88505 +       BUG_ON((tsfs->config->extent > 256) || (!tsfs->config->extent));
88506 +
88507 +       p = kmalloc(tsfs->config->extent * sizeof(int) * count_coords,
88508 +                                                                   GFP_KERNEL);
88509 +       if (!p)
88510 +               return NULL;
88511 +
88512 +       for (n = 0; n < count_coords; n++) {
88513 +               tsfs->fifo[n] = p;
88514 +               p += tsfs->config->extent;
88515 +       }
88516 +
88517 +       if (!tsfs->config->averaging_threshold)
88518 +               tsfs->config->averaging_threshold = 0xffff; /* always active */
88519 +
88520 +       ts_filter_mean_clear_internal(&tsfs->tsf);
88521 +
88522 +       printk(KERN_INFO"  Created Mean ts filter len %d depth %d thresh %d\n",
88523 +              tsfs->config->extent, count_coords,
88524 +              tsfs->config->averaging_threshold);
88525 +
88526 +       return &tsfs->tsf;
88527 +}
88528 +
88529 +static void ts_filter_mean_destroy(struct platform_device *pdev,
88530 +                                  struct ts_filter *tsf)
88531 +{
88532 +       struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
88533 +
88534 +       kfree(tsfs->fifo[0]); /* first guy has pointer from kmalloc */
88535 +       kfree(tsf);
88536 +}
88537 +
88538 +static void ts_filter_mean_scale(struct ts_filter *tsf, int *coords)
88539 +{
88540 +       if (tsf->next) /* chain */
88541 +               (tsf->next->api->scale)(tsf->next, coords);
88542 +}
88543 +
88544 +/* give us the raw sample data in x and y, and if we return 1 then you can
88545 + * get a filtered coordinate from tsm->x and tsm->y: if we return 0 you didn't
88546 + * fill the filter with samples yet.
88547 + */
88548 +
88549 +static int ts_filter_mean_process(struct ts_filter *tsf, int *coords)
88550 +{
88551 +       struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
88552 +       int n;
88553 +       int len;
88554 +
88555 +       for (n = 0; n < tsf->count_coords; n++) {
88556 +
88557 +               /* has he moved far enough away that we should abandon current
88558 +                * low pass filtering state?
88559 +                */
88560 +               if ((coords[n] < (tsfs->reported[n] -
88561 +                                         tsfs->config->averaging_threshold)) ||
88562 +                   (coords[n] > (tsfs->reported[n] +
88563 +                                         tsfs->config->averaging_threshold))) {
88564 +                       tsfs->fhead[n] = 0;
88565 +                       tsfs->ftail[n] = 0;
88566 +                       tsfs->lowpass[n] = 0;
88567 +               }
88568 +
88569 +               /* capture this sample into fifo and sum */
88570 +               tsfs->fifo[n][tsfs->fhead[n]++] = coords[n];
88571 +               if (tsfs->fhead[n] == tsfs->config->extent)
88572 +                       tsfs->fhead[n] = 0;
88573 +               tsfs->lowpass[n] += coords[n];
88574 +
88575 +               /* adjust the sum into an average and use that*/
88576 +               len = (tsfs->fhead[n] - tsfs->ftail[n]) &
88577 +                                                    (tsfs->config->extent - 1);
88578 +               coords[n] = (tsfs->lowpass[n] + (len >> 1)) / len;
88579 +               tsfs->reported[n] = coords[n];
88580 +
88581 +               /* remove oldest sample if we are full */
88582 +               if (len == (tsfs->config->extent - 1)) {
88583 +                       tsfs->lowpass[n] -= tsfs->fifo[n][tsfs->ftail[n]++];
88584 +                       if (tsfs->ftail[n] == tsfs->config->extent)
88585 +                               tsfs->ftail[n] = 0;
88586 +               }
88587 +       }
88588 +
88589 +       if (tsf->next) /* chain */
88590 +               return (tsf->next->api->process)(tsf->next, coords);
88591 +
88592 +       return 1;
88593 +}
88594 +
88595 +struct ts_filter_api ts_filter_mean_api = {
88596 +       .create = ts_filter_mean_create,
88597 +       .destroy = ts_filter_mean_destroy,
88598 +       .clear = ts_filter_mean_clear,
88599 +       .process = ts_filter_mean_process,
88600 +       .scale = ts_filter_mean_scale,
88601 +};
88602 Index: linux-2.6.28/drivers/input/touchscreen/ts_filter_median.c
88603 ===================================================================
88604 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
88605 +++ linux-2.6.28/drivers/input/touchscreen/ts_filter_median.c   2009-01-02 00:01:56.000000000 +0100
88606 @@ -0,0 +1,215 @@
88607 +/*
88608 + * This program is free software; you can redistribute it and/or modify
88609 + * it under the terms of the GNU General Public License as published by
88610 + * the Free Software Foundation; either version 2 of the License, or
88611 + * (at your option) any later version.
88612 + *
88613 + * This program is distributed in the hope that it will be useful,
88614 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
88615 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
88616 + * GNU General Public License for more details.
88617 + *
88618 + * You should have received a copy of the GNU General Public License
88619 + * along with this program; if not, write to the Free Software
88620 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
88621 + *
88622 + * Copyright (c) 2008 Andy Green <andy@openmoko.com>
88623 + *
88624 + *
88625 + * Median averaging stuff.  We sort incoming raw samples into an array of
88626 + * MEDIAN_SIZE length, discarding the oldest sample each time once we are full.
88627 + * We then return the sum of the middle three samples for X and Y.  It means
88628 + * the final result must be divided by (3 * scaling factor) to correct for
88629 + * avoiding the repeated /3.
88630 + *
88631 + * This strongly rejects brief excursions away from a central point that is
88632 + * sticky in time compared to the excursion duration.
88633 + *
88634 + * Thanks to Dale Schumacher (who wrote some example code) and Carl-Daniel
88635 + * Halifinger who pointed out this would be a good method.
88636 + */
88637 +
88638 +#include <linux/errno.h>
88639 +#include <linux/kernel.h>
88640 +#include <linux/slab.h>
88641 +#include <linux/ts_filter_median.h>
88642 +
88643 +static void ts_filter_median_insert(int *p, int sample, int count)
88644 +{
88645 +       int n;
88646 +
88647 +       /* search through what we got so far to find where to put sample */
88648 +       for (n = 0; n < count; n++)
88649 +                /* we met somebody bigger than us? */
88650 +               if (sample < p[n]) {
88651 +                       /* starting from the end, push bigger guys down one */
88652 +                       for (count--; count >= n; count--)
88653 +                               p[count + 1] = p[count];
88654 +                       p[n] = sample; /* and put us in place of first bigger */
88655 +                       return;
88656 +               }
88657 +
88658 +       p[count] = sample; /* nobody was bigger than us, add us on the end */
88659 +}
88660 +
88661 +static void ts_filter_median_del(int *p, int value, int count)
88662 +{
88663 +       int index;
88664 +
88665 +       for (index = 0; index < count; index++)
88666 +               if (p[index] == value) {
88667 +                       for (; index < count; index++)
88668 +                               p[index] = p[index + 1];
88669 +                       return;
88670 +               }
88671 +}
88672 +
88673 +
88674 +static void ts_filter_median_clear_internal(struct ts_filter *tsf)
88675 +{
88676 +       struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
88677 +
88678 +       tsfm->pos = 0;
88679 +       tsfm->valid = 0;
88680 +
88681 +}
88682 +static void ts_filter_median_clear(struct ts_filter *tsf)
88683 +{
88684 +       ts_filter_median_clear_internal(tsf);
88685 +
88686 +       if (tsf->next) /* chain */
88687 +               (tsf->next->api->clear)(tsf->next);
88688 +}
88689 +
88690 +static struct ts_filter *ts_filter_median_create(struct platform_device *pdev,
88691 +                                                void *conf, int count_coords)
88692 +{
88693 +       int *p;
88694 +       int n;
88695 +       struct ts_filter_median *tsfm = kzalloc(sizeof(struct ts_filter_median),
88696 +                                                                   GFP_KERNEL);
88697 +
88698 +       if (!tsfm)
88699 +               return NULL;
88700 +
88701 +       tsfm->config = (struct ts_filter_median_configuration *)conf;
88702 +       BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
88703 +       tsfm->tsf.count_coords = count_coords;
88704 +
88705 +       tsfm->config->midpoint = (tsfm->config->extent >> 1) + 1;
88706 +
88707 +       p = kmalloc(2 * count_coords * sizeof(int) * (tsfm->config->extent + 1),
88708 +                                                                   GFP_KERNEL);
88709 +       if (!p) {
88710 +               kfree(tsfm);
88711 +               return NULL;
88712 +       }
88713 +
88714 +       for (n = 0; n < count_coords; n++) {
88715 +               tsfm->sort[n] = p;
88716 +               p += tsfm->config->extent + 1;
88717 +               tsfm->fifo[n] = p;
88718 +               p += tsfm->config->extent + 1;
88719 +       }
88720 +
88721 +       ts_filter_median_clear_internal(&tsfm->tsf);
88722 +
88723 +       printk(KERN_INFO"  Created Median ts filter len %d depth %d dec %d\n",
88724 +              tsfm->config->extent, count_coords,
88725 +              tsfm->config->decimation_threshold);
88726 +
88727 +       return &tsfm->tsf;
88728 +}
88729 +
88730 +static void ts_filter_median_destroy(struct platform_device *pdev,
88731 +                                    struct ts_filter *tsf)
88732 +{
88733 +       struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
88734 +
88735 +       kfree(tsfm->sort[0]); /* first guy has pointer from kmalloc */
88736 +       kfree(tsf);
88737 +}
88738 +
88739 +static void ts_filter_median_scale(struct ts_filter *tsf, int *coords)
88740 +{
88741 +       int n;
88742 +
88743 +       for (n = 0; n < tsf->count_coords; n++)
88744 +               coords[n] = (coords[n] + 2) / 3;
88745 +
88746 +       if (tsf->next) /* chain */
88747 +               (tsf->next->api->scale)(tsf->next, coords);
88748 +}
88749 +
88750 +/* give us the raw sample data coords, and if we return 1 then you can
88751 + * get a filtered coordinate from coords: if we return 0 you didn't
88752 + * fill all the filters with samples yet.
88753 + */
88754 +
88755 +static int ts_filter_median_process(struct ts_filter *tsf, int *coords)
88756 +{
88757 +       struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
88758 +       int n;
88759 +       int movement = 1;
88760 +
88761 +       for (n = 0; n < tsf->count_coords; n++) {
88762 +               /* grab copy in insertion order to remove when oldest */
88763 +               tsfm->fifo[n][tsfm->pos] = coords[n];
88764 +               /* insert these samples in sorted order in the median arrays */
88765 +               ts_filter_median_insert(tsfm->sort[n], coords[n], tsfm->valid);
88766 +       }
88767 +       /* move us on in the fifo */
88768 +       if (++tsfm->pos == (tsfm->config->extent + 1))
88769 +               tsfm->pos = 0;
88770 +
88771 +       /* we have finished a median sampling? */
88772 +       if (++tsfm->valid != tsfm->config->extent)
88773 +               return 0; /* no valid sample to use */
88774 +
88775 +       /* discard the oldest sample in median sorted array */
88776 +       tsfm->valid--;
88777 +
88778 +       /* sum the middle 3 in the median sorted arrays.  We don't divide back
88779 +        * down which increases the sum resolution by a factor of 3 until the
88780 +        * scale API is called
88781 +        */
88782 +       for (n = 0; n < tsfm->tsf.count_coords; n++)
88783 +               /* perform the deletion of the oldest sample */
88784 +               ts_filter_median_del(tsfm->sort[n], tsfm->fifo[n][tsfm->pos],
88785 +                                                                  tsfm->valid);
88786 +
88787 +       tsfm->decimation_count--;
88788 +       if (tsfm->decimation_count >= 0)
88789 +               return 0;
88790 +
88791 +       for (n = 0; n < tsfm->tsf.count_coords; n++) {
88792 +               /* give the coordinate result from summing median 3 */
88793 +               coords[n] = tsfm->sort[n][tsfm->config->midpoint - 1] +
88794 +                           tsfm->sort[n][tsfm->config->midpoint] +
88795 +                           tsfm->sort[n][tsfm->config->midpoint + 1]
88796 +                       ;
88797 +
88798 +               movement += abs(tsfm->last_issued[n] - coords[n]);
88799 +       }
88800 +
88801 +       if (movement > tsfm->config->decimation_threshold) /* fast */
88802 +               tsfm->decimation_count = tsfm->config->decimation_above;
88803 +       else
88804 +               tsfm->decimation_count = tsfm->config->decimation_below;
88805 +
88806 +       memcpy(&tsfm->last_issued[0], coords,
88807 +              tsfm->tsf.count_coords * sizeof(int));
88808 +
88809 +       if (tsf->next) /* chain */
88810 +               return (tsf->next->api->process)(tsf->next, coords);
88811 +
88812 +       return 1;
88813 +}
88814 +
88815 +struct ts_filter_api ts_filter_median_api = {
88816 +       .create = ts_filter_median_create,
88817 +       .destroy = ts_filter_median_destroy,
88818 +       .clear = ts_filter_median_clear,
88819 +       .process = ts_filter_median_process,
88820 +       .scale = ts_filter_median_scale,
88821 +};
88822 Index: linux-2.6.28/drivers/Kconfig
88823 ===================================================================
88824 --- linux-2.6.28.orig/drivers/Kconfig   2008-12-25 00:26:37.000000000 +0100
88825 +++ linux-2.6.28/drivers/Kconfig        2009-01-02 00:01:56.000000000 +0100
88826 @@ -107,4 +107,6 @@ source "drivers/uio/Kconfig"
88827  source "drivers/xen/Kconfig"
88828
88829  source "drivers/staging/Kconfig"
88830 +
88831 +source "drivers/android/Kconfig"
88832  endmenu
88833 Index: linux-2.6.28/drivers/leds/Kconfig
88834 ===================================================================
88835 --- linux-2.6.28.orig/drivers/leds/Kconfig      2009-01-02 00:00:02.000000000 +0100
88836 +++ linux-2.6.28/drivers/leds/Kconfig   2009-01-02 00:01:56.000000000 +0100
88837 @@ -33,7 +33,7 @@ config LEDS_LOCOMO
88838
88839  config LEDS_S3C24XX
88840         tristate "LED Support for Samsung S3C24XX GPIO LEDs"
88841 -       depends on LEDS_CLASS && ARCH_S3C2410
88842 +       depends on LEDS_CLASS && ARCH_S3C2410 && S3C2410_PWM
88843         help
88844           This option enables support for LEDs connected to GPIO lines
88845           on Samsung S3C24XX series CPUs, such as the S3C2410 and S3C2440.
88846 @@ -171,6 +171,18 @@ config LEDS_DA903X
88847           This option enables support for on-chip LED drivers found
88848           on Dialog Semiconductor DA9030/DA9034 PMICs.
88849
88850 +config LEDS_NEO1973_VIBRATOR
88851 +       tristate "Vibrator Support for the FIC Neo1973 GSM phone"
88852 +       depends on LEDS_CLASS && MACH_NEO1973
88853 +       help
88854 +         This option enables support for the vibrator on the FIC Neo1973.
88855 +
88856 +config LEDS_NEO1973_GTA02
88857 +       tristate "LED Support for the FIC Neo1973 (GTA02)"
88858 +       depends on LEDS_CLASS && MACH_NEO1973_GTA02
88859 +       help
88860 +         This option enables support for the LEDs on the FIC Neo1973.
88861 +
88862  comment "LED Triggers"
88863
88864  config LEDS_TRIGGERS
88865 Index: linux-2.6.28/drivers/leds/led-class.c
88866 ===================================================================
88867 --- linux-2.6.28.orig/drivers/leds/led-class.c  2008-12-25 00:26:37.000000000 +0100
88868 +++ linux-2.6.28/drivers/leds/led-class.c       2009-01-02 00:01:56.000000000 +0100
88869 @@ -56,8 +56,10 @@ static ssize_t led_brightness_store(stru
88870         if (count == size) {
88871                 ret = count;
88872
88873 +#if 0 /* This is really bad. Don't do it!!!! */
88874                 if (state == LED_OFF)
88875                         led_trigger_remove(led_cdev);
88876 +#endif
88877                 led_set_brightness(led_cdev, state);
88878         }
88879
88880 Index: linux-2.6.28/drivers/leds/leds-neo1973-gta02.c
88881 ===================================================================
88882 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
88883 +++ linux-2.6.28/drivers/leds/leds-neo1973-gta02.c      2009-01-02 00:01:56.000000000 +0100
88884 @@ -0,0 +1,179 @@
88885 +/*
88886 + * LED driver for the Openmoko GTA02 GSM phone
88887 + *
88888 + * (C) 2006-2008 by Openmoko, Inc.
88889 + * Author: Harald Welte <laforge@openmoko.org>
88890 + * All rights reserved.
88891 + *
88892 + * This program is free software; you can redistribute it and/or modify
88893 + * it under the terms of the GNU General Public License version 2 as
88894 + * published by the Free Software Foundation.
88895 + *
88896 + */
88897 +
88898 +#include <linux/kernel.h>
88899 +#include <linux/init.h>
88900 +#include <linux/platform_device.h>
88901 +#include <linux/leds.h>
88902 +#include <mach/hardware.h>
88903 +#include <asm/mach-types.h>
88904 +#include <mach/gta02.h>
88905 +#include <plat/regs-timer.h>
88906 +#include <asm/plat-s3c24xx/neo1973.h>
88907 +
88908 +#define MAX_LEDS 3
88909 +#define COUNTER 256
88910 +
88911 +struct gta02_led_priv
88912 +{
88913 +       spinlock_t lock;
88914 +       struct led_classdev cdev;
88915 +       unsigned int gpio;
88916 +};
88917 +
88918 +struct gta02_led_bundle
88919 +{
88920 +       int num_leds;
88921 +       struct gta02_led_priv led[MAX_LEDS];
88922 +};
88923 +
88924 +static inline struct gta02_led_priv *to_priv(struct led_classdev *led_cdev)
88925 +{
88926 +       return container_of(led_cdev, struct gta02_led_priv, cdev);
88927 +}
88928 +
88929 +static inline struct gta02_led_bundle *to_bundle(struct led_classdev *led_cdev)
88930 +{
88931 +       return dev_get_drvdata(led_cdev->dev->parent);
88932 +}
88933 +
88934 +static void gta02led_set(struct led_classdev *led_cdev,
88935 +                        enum led_brightness value)
88936 +{
88937 +       unsigned long flags;
88938 +       struct gta02_led_priv *lp = to_priv(led_cdev);
88939 +
88940 +       spin_lock_irqsave(&lp->lock, flags);
88941 +       neo1973_gpb_setpin(lp->gpio, value ? 1 : 0);
88942 +       spin_unlock_irqrestore(&lp->lock, flags);
88943 +}
88944 +
88945 +#ifdef CONFIG_PM
88946 +static int gta02led_suspend(struct platform_device *pdev, pm_message_t state)
88947 +{
88948 +       struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
88949 +       int i;
88950 +
88951 +       for (i = 0; i < bundle->num_leds; i++)
88952 +               led_classdev_suspend(&bundle->led[i].cdev);
88953 +
88954 +       return 0;
88955 +}
88956 +
88957 +static int gta02led_resume(struct platform_device *pdev)
88958 +{
88959 +       struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
88960 +       int i;
88961 +
88962 +       for (i = 0; i < bundle->num_leds; i++)
88963 +               led_classdev_resume(&bundle->led[i].cdev);
88964 +
88965 +       return 0;
88966 +}
88967 +#endif
88968 +
88969 +static int __init gta02led_probe(struct platform_device *pdev)
88970 +{
88971 +       int i, rc;
88972 +       struct gta02_led_bundle *bundle;
88973 +
88974 +       if (!machine_is_neo1973_gta02())
88975 +               return -EIO;
88976 +
88977 +       bundle = kzalloc(sizeof(struct gta02_led_bundle), GFP_KERNEL);
88978 +       if (!bundle)
88979 +               return -ENOMEM;
88980 +       platform_set_drvdata(pdev, bundle);
88981 +
88982 +       for (i = 0; i < pdev->num_resources; i++) {
88983 +               struct gta02_led_priv *lp;
88984 +               struct resource *r;
88985 +
88986 +               if (i >= MAX_LEDS)
88987 +                       break;
88988 +
88989 +               r = platform_get_resource(pdev, 0, i);
88990 +               if (!r || !r->start || !r->name)
88991 +                       continue;
88992 +
88993 +               lp = &bundle->led[i];
88994 +
88995 +               lp->gpio = r->start;
88996 +               lp->cdev.name = r->name;
88997 +               lp->cdev.brightness_set = gta02led_set;
88998 +
88999 +               switch (lp->gpio) {
89000 +               case S3C2410_GPB0:
89001 +               case S3C2410_GPB1:
89002 +               case S3C2410_GPB2:
89003 +                       s3c2410_gpio_cfgpin(lp->gpio, S3C2410_GPIO_OUTPUT);
89004 +                       neo1973_gpb_add_shadow_gpio(lp->gpio);
89005 +                       break;
89006 +               default:
89007 +                       break;
89008 +               }
89009 +
89010 +               spin_lock_init(&lp->lock);
89011 +               rc = led_classdev_register(&pdev->dev, &lp->cdev);
89012 +       }
89013 +
89014 +       bundle->num_leds = i;
89015 +
89016 +       return 0;
89017 +}
89018 +
89019 +static int gta02led_remove(struct platform_device *pdev)
89020 +{
89021 +       struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
89022 +       int i;
89023 +
89024 +       for (i = 0; i < bundle->num_leds; i++) {
89025 +               struct gta02_led_priv *lp = &bundle->led[i];
89026 +               gta02led_set(&lp->cdev, 0);
89027 +               led_classdev_unregister(&lp->cdev);
89028 +       }
89029 +
89030 +       platform_set_drvdata(pdev, NULL);
89031 +       kfree(bundle);
89032 +
89033 +       return 0;
89034 +}
89035 +
89036 +static struct platform_driver gta02led_driver = {
89037 +       .probe          = gta02led_probe,
89038 +       .remove         = gta02led_remove,
89039 +#ifdef CONFIG_PM
89040 +       .suspend        = gta02led_suspend,
89041 +       .resume         = gta02led_resume,
89042 +#endif
89043 +       .driver         = {
89044 +               .name           = "gta02-led",
89045 +       },
89046 +};
89047 +
89048 +static int __init gta02led_init(void)
89049 +{
89050 +       return platform_driver_register(&gta02led_driver);
89051 +}
89052 +
89053 +static void __exit gta02led_exit(void)
89054 +{
89055 +       platform_driver_unregister(&gta02led_driver);
89056 +}
89057 +
89058 +module_init(gta02led_init);
89059 +module_exit(gta02led_exit);
89060 +
89061 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
89062 +MODULE_DESCRIPTION("Openmoko GTA02 LED driver");
89063 +MODULE_LICENSE("GPL");
89064 Index: linux-2.6.28/drivers/leds/leds-neo1973-vibrator.c
89065 ===================================================================
89066 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
89067 +++ linux-2.6.28/drivers/leds/leds-neo1973-vibrator.c   2009-01-02 00:01:56.000000000 +0100
89068 @@ -0,0 +1,209 @@
89069 +/*
89070 + * LED driver for the vibrator of the Openmoko GTA01/GTA02 GSM Phones
89071 + *
89072 + * (C) 2006-2008 by Openmoko, Inc.
89073 + * Author: Harald Welte <laforge@openmoko.org>
89074 + * All rights reserved.
89075 + *
89076 + * This program is free software; you can redistribute it and/or modify
89077 + * it under the terms of the GNU General Public License version 2 as
89078 + * published by the Free Software Foundation.
89079 + *
89080 + * Javi Roman <javiroman@kernel-labs.org>:
89081 + *     Implement PWM support for GTA01Bv4 and later
89082 + */
89083 +
89084 +#include <linux/kernel.h>
89085 +#include <linux/init.h>
89086 +#include <linux/platform_device.h>
89087 +#include <linux/leds.h>
89088 +#include <mach/hardware.h>
89089 +#include <asm/mach-types.h>
89090 +#include <mach/pwm.h>
89091 +#include <mach/gta01.h>
89092 +#include <plat/regs-timer.h>
89093 +
89094 +#ifdef CONFIG_MACH_NEO1973_GTA02
89095 +#include <mach/fiq_ipc_gta02.h>
89096 +#endif
89097 +#include <asm/plat-s3c24xx/neo1973.h>
89098 +
89099 +#define COUNTER 64
89100 +
89101 +struct neo1973_vib_priv {
89102 +       struct led_classdev cdev;
89103 +       unsigned int gpio;
89104 +       spinlock_t lock;
89105 +       unsigned int has_pwm;
89106 +       struct s3c2410_pwm pwm;
89107 +};
89108 +
89109 +static void neo1973_vib_vib_set(struct led_classdev *led_cdev,
89110 +                               enum led_brightness value)
89111 +{
89112 +       unsigned long flags;
89113 +       struct neo1973_vib_priv *vp = container_of(led_cdev,
89114 +                                                  struct neo1973_vib_priv,
89115 +                                                  cdev);
89116 +
89117 +#ifdef CONFIG_MACH_NEO1973_GTA02
89118 +       if (machine_is_neo1973_gta02()) { /* use FIQ to control GPIO */
89119 +               fiq_ipc.vib_pwm = value; /* set it for FIQ */
89120 +               fiq_kick(); /* start up FIQs if not already going */
89121 +               return;
89122 +       }
89123 +#endif
89124 +       /*
89125 +        * value == 255 -> 99% duty cycle (full power)
89126 +        * value == 128 -> 50% duty cycle (medium power)
89127 +        * value == 0 -> 0% duty cycle (zero power)
89128 +        */
89129 +       spin_lock_irqsave(&vp->lock, flags);
89130 +       if (vp->has_pwm) {
89131 +               s3c2410_pwm_duty_cycle(value / 4, &vp->pwm);
89132 +       }
89133 +       else {
89134 +               neo1973_gpb_setpin(vp->gpio, value ? 1 : 0);
89135 +       }
89136 +       spin_unlock_irqrestore(&vp->lock, flags);
89137 +}
89138 +
89139 +static struct neo1973_vib_priv neo1973_vib_led = {
89140 +       .cdev = {
89141 +               .name = "neo1973:vibrator",
89142 +               .brightness_set = neo1973_vib_vib_set,
89143 +       },
89144 +};
89145 +
89146 +static int neo1973_vib_init_hw(struct neo1973_vib_priv *vp)
89147 +{
89148 +       int rc;
89149 +
89150 +       rc = s3c2410_pwm_init(&vp->pwm);
89151 +       if (rc)
89152 +               return rc;
89153 +
89154 +       vp->pwm.timerid = PWM3;
89155 +       /* use same prescaler as arch/arm/plat-s3c24xx/time.c */
89156 +       vp->pwm.prescaler = (6 - 1) / 2;
89157 +       vp->pwm.divider = S3C2410_TCFG1_MUX3_DIV2;
89158 +       vp->pwm.counter = COUNTER;
89159 +       vp->pwm.comparer = COUNTER;
89160 +
89161 +       rc = s3c2410_pwm_enable(&vp->pwm);
89162 +       if (rc)
89163 +               return rc;
89164 +
89165 +       s3c2410_pwm_start(&vp->pwm);
89166 +
89167 +       return 0;
89168 +}
89169 +
89170 +#ifdef CONFIG_PM
89171 +static int neo1973_vib_suspend(struct platform_device *dev, pm_message_t state)
89172 +{
89173 +       led_classdev_suspend(&neo1973_vib_led.cdev);
89174 +       return 0;
89175 +}
89176 +
89177 +static int neo1973_vib_resume(struct platform_device *dev)
89178 +{
89179 +       struct neo1973_vib_priv *vp = platform_get_drvdata(dev);
89180 +
89181 +       if (vp->has_pwm)
89182 +               neo1973_vib_init_hw(vp);
89183 +
89184 +       led_classdev_resume(&neo1973_vib_led.cdev);
89185 +
89186 +       return 0;
89187 +}
89188 +#endif /* CONFIG_PM */
89189 +
89190 +static int __init neo1973_vib_probe(struct platform_device *pdev)
89191 +{
89192 +       struct resource *r;
89193 +       int rc;
89194 +
89195 +       if (!machine_is_neo1973_gta01() && !machine_is_neo1973_gta02())
89196 +               return -EIO;
89197 +
89198 +       r = platform_get_resource(pdev, 0, 0);
89199 +       if (!r || !r->start)
89200 +               return -EIO;
89201 +
89202 +       neo1973_vib_led.gpio = r->start;
89203 +       platform_set_drvdata(pdev, &neo1973_vib_led);
89204 +
89205 +#ifdef CONFIG_MACH_NEO1973_GTA02
89206 +       if (machine_is_neo1973_gta02()) { /* use FIQ to control GPIO */
89207 +               neo1973_gpb_setpin(neo1973_vib_led.gpio, 0); /* off */
89208 +               s3c2410_gpio_cfgpin(neo1973_vib_led.gpio, S3C2410_GPIO_OUTPUT);
89209 +               /* safe, kmalloc'd copy needed for FIQ ISR */
89210 +               fiq_ipc.vib_gpio_pin = neo1973_vib_led.gpio;
89211 +               fiq_ipc.vib_pwm = 0; /* off */
89212 +               goto configured;
89213 +       }
89214 +#endif
89215 +
89216 +       /* TOUT3 */
89217 +       if (neo1973_vib_led.gpio == S3C2410_GPB3) {
89218 +               rc = neo1973_vib_init_hw(&neo1973_vib_led);
89219 +               if (rc)
89220 +                       return rc;
89221 +
89222 +               s3c2410_pwm_duty_cycle(0, &neo1973_vib_led.pwm);
89223 +               s3c2410_gpio_cfgpin(neo1973_vib_led.gpio, S3C2410_GPB3_TOUT3);
89224 +               neo1973_vib_led.has_pwm = 1;
89225 +       }
89226 +#ifdef CONFIG_MACH_NEO1973_GTA02
89227 +configured:
89228 +#endif
89229 +       spin_lock_init(&neo1973_vib_led.lock);
89230 +
89231 +       return led_classdev_register(&pdev->dev, &neo1973_vib_led.cdev);
89232 +}
89233 +
89234 +static int neo1973_vib_remove(struct platform_device *pdev)
89235 +{
89236 +#ifdef CONFIG_MACH_NEO1973_GTA02
89237 +       if (machine_is_neo1973_gta02()) /* use FIQ to control GPIO */
89238 +               fiq_ipc.vib_pwm = 0; /* off */
89239 +       /* would only need kick if already off so no kick needed */
89240 +#endif
89241 +
89242 +       if (neo1973_vib_led.has_pwm)
89243 +               s3c2410_pwm_disable(&neo1973_vib_led.pwm);
89244 +
89245 +       led_classdev_unregister(&neo1973_vib_led.cdev);
89246 +
89247 +       return 0;
89248 +}
89249 +
89250 +static struct platform_driver neo1973_vib_driver = {
89251 +       .probe          = neo1973_vib_probe,
89252 +       .remove         = neo1973_vib_remove,
89253 +#ifdef CONFIG_PM
89254 +       .suspend        = neo1973_vib_suspend,
89255 +       .resume         = neo1973_vib_resume,
89256 +#endif
89257 +       .driver         = {
89258 +               .name           = "neo1973-vibrator",
89259 +       },
89260 +};
89261 +
89262 +static int __init neo1973_vib_init(void)
89263 +{
89264 +       return platform_driver_register(&neo1973_vib_driver);
89265 +}
89266 +
89267 +static void __exit neo1973_vib_exit(void)
89268 +{
89269 +       platform_driver_unregister(&neo1973_vib_driver);
89270 +}
89271 +
89272 +module_init(neo1973_vib_init);
89273 +module_exit(neo1973_vib_exit);
89274 +
89275 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
89276 +MODULE_DESCRIPTION("Openmoko GTA01/GTA02 vibrator driver");
89277 +MODULE_LICENSE("GPL");
89278 Index: linux-2.6.28/drivers/leds/Makefile
89279 ===================================================================
89280 --- linux-2.6.28.orig/drivers/leds/Makefile     2009-01-02 00:00:02.000000000 +0100
89281 +++ linux-2.6.28/drivers/leds/Makefile  2009-01-02 00:01:56.000000000 +0100
89282 @@ -24,6 +24,8 @@ obj-$(CONFIG_LEDS_FSG)                        += leds-fsg.o
89283  obj-$(CONFIG_LEDS_PCA955X)             += leds-pca955x.o
89284  obj-$(CONFIG_LEDS_DA903X)              += leds-da903x.o
89285  obj-$(CONFIG_LEDS_HP_DISK)             += leds-hp-disk.o
89286 +obj-$(CONFIG_LEDS_NEO1973_VIBRATOR)    += leds-neo1973-vibrator.o
89287 +obj-$(CONFIG_LEDS_NEO1973_GTA02)       += leds-neo1973-gta02.o
89288
89289  # LED Triggers
89290  obj-$(CONFIG_LEDS_TRIGGER_TIMER)       += ledtrig-timer.o
89291 Index: linux-2.6.28/drivers/Makefile
89292 ===================================================================
89293 --- linux-2.6.28.orig/drivers/Makefile  2008-12-25 00:26:37.000000000 +0100
89294 +++ linux-2.6.28/drivers/Makefile       2009-01-02 00:01:56.000000000 +0100
89295 @@ -86,6 +86,7 @@ obj-$(CONFIG_CPU_IDLE)                += cpuidle/
89296  obj-y                          += idle/
89297  obj-$(CONFIG_MMC)              += mmc/
89298  obj-$(CONFIG_MEMSTICK)         += memstick/
89299 +obj-$(CONFIG_AR6000_WLAN)      += ar6000/
89300  obj-$(CONFIG_NEW_LEDS)         += leds/
89301  obj-$(CONFIG_INFINIBAND)       += infiniband/
89302  obj-$(CONFIG_SGI_SN)           += sn/
89303 @@ -98,6 +99,7 @@ obj-$(CONFIG_DCA)             += dca/
89304  obj-$(CONFIG_HID)              += hid/
89305  obj-$(CONFIG_PPC_PS3)          += ps3/
89306  obj-$(CONFIG_OF)               += of/
89307 +obj-y                          += android/
89308  obj-$(CONFIG_SSB)              += ssb/
89309  obj-$(CONFIG_VIRTIO)           += virtio/
89310  obj-$(CONFIG_REGULATOR)                += regulator/
89311 Index: linux-2.6.28/drivers/mfd/glamo/glamo-core.c
89312 ===================================================================
89313 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
89314 +++ linux-2.6.28/drivers/mfd/glamo/glamo-core.c 2009-01-02 00:01:56.000000000 +0100
89315 @@ -0,0 +1,1399 @@
89316 +/* Smedia Glamo 336x/337x driver
89317 + *
89318 + * (C) 2007 by Openmoko, Inc.
89319 + * Author: Harald Welte <laforge@openmoko.org>
89320 + * All rights reserved.
89321 + *
89322 + * This program is free software; you can redistribute it and/or
89323 + * modify it under the terms of the GNU General Public License as
89324 + * published by the Free Software Foundation; either version 2 of
89325 + * the License, or (at your option) any later version.
89326 + *
89327 + * This program is distributed in the hope that it will be useful,
89328 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
89329 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
89330 + * GNU General Public License for more details.
89331 + *
89332 + * You should have received a copy of the GNU General Public License
89333 + * along with this program; if not, write to the Free Software
89334 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
89335 + * MA 02111-1307 USA
89336 + */
89337 +
89338 +#include <linux/module.h>
89339 +#include <linux/kernel.h>
89340 +#include <linux/errno.h>
89341 +#include <linux/string.h>
89342 +#include <linux/mm.h>
89343 +#include <linux/tty.h>
89344 +#include <linux/slab.h>
89345 +#include <linux/delay.h>
89346 +#include <linux/fb.h>
89347 +#include <linux/init.h>
89348 +#include <linux/irq.h>
89349 +#include <linux/interrupt.h>
89350 +#include <linux/workqueue.h>
89351 +#include <linux/wait.h>
89352 +#include <linux/platform_device.h>
89353 +#include <linux/kernel_stat.h>
89354 +#include <linux/spinlock.h>
89355 +#include <linux/glamofb.h>
89356 +#include <linux/mmc/mmc.h>
89357 +#include <linux/mmc/host.h>
89358 +
89359 +#include <asm/io.h>
89360 +#include <asm/uaccess.h>
89361 +#include <asm/div64.h>
89362 +
89363 +//#include <mach/regs-irq.h>
89364 +
89365 +#ifdef CONFIG_PM
89366 +#include <linux/pm.h>
89367 +#endif
89368 +
89369 +#include "glamo-regs.h"
89370 +#include "glamo-core.h"
89371 +
89372 +#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
89373 +
89374 +#define GLAMO_MEM_REFRESH_COUNT 0x100
89375 +
89376 +struct reg_range {
89377 +       int start;
89378 +       int count;
89379 +       char *name;
89380 +       char dump;
89381 +};
89382 +struct reg_range reg_range[] = {
89383 +       { 0x0000, 0x76,         "General",      1 },
89384 +       { 0x0200, 0x16,         "Host Bus",     1 },
89385 +       { 0x0300, 0x38,         "Memory",       1 },
89386 +/*     { 0x0400, 0x100,        "Sensor",       0 }, */
89387 +/*             { 0x0500, 0x300,        "ISP",          0 }, */
89388 +/*             { 0x0800, 0x400,        "JPEG",         0 }, */
89389 +/*             { 0x0c00, 0xcc,         "MPEG",         0 }, */
89390 +       { 0x1100, 0xb2,         "LCD 1",        1 },
89391 +       { 0x1200, 0x64,         "LCD 2",        1 },
89392 +       { 0x1400, 0x40,         "MMC",          1 },
89393 +/*             { 0x1500, 0x080,        "MPU 0",        0 },
89394 +       { 0x1580, 0x080,        "MPU 1",        0 },
89395 +       { 0x1600, 0x080,        "Cmd Queue",    0 },
89396 +       { 0x1680, 0x080,        "RISC CPU",     0 },
89397 +       { 0x1700, 0x400,        "2D Unit",      0 },
89398 +       { 0x1b00, 0x900,        "3D Unit",      0 }, */
89399 +};
89400 +
89401 +static struct glamo_core *glamo_handle;
89402 +
89403 +static inline void __reg_write(struct glamo_core *glamo,
89404 +                               u_int16_t reg, u_int16_t val)
89405 +{
89406 +       writew(val, glamo->base + reg);
89407 +}
89408 +
89409 +static inline u_int16_t __reg_read(struct glamo_core *glamo,
89410 +                                  u_int16_t reg)
89411 +{
89412 +       return readw(glamo->base + reg);
89413 +}
89414 +
89415 +static void __reg_set_bit_mask(struct glamo_core *glamo,
89416 +                               u_int16_t reg, u_int16_t mask,
89417 +                               u_int16_t val)
89418 +{
89419 +       u_int16_t tmp;
89420 +
89421 +       val &= mask;
89422 +
89423 +       tmp = __reg_read(glamo, reg);
89424 +       tmp &= ~mask;
89425 +       tmp |= val;
89426 +       __reg_write(glamo, reg, tmp);
89427 +}
89428 +
89429 +static void reg_set_bit_mask(struct glamo_core *glamo,
89430 +                               u_int16_t reg, u_int16_t mask,
89431 +                               u_int16_t val)
89432 +{
89433 +       spin_lock(&glamo->lock);
89434 +       __reg_set_bit_mask(glamo, reg, mask, val);
89435 +       spin_unlock(&glamo->lock);
89436 +}
89437 +
89438 +static inline void __reg_set_bit(struct glamo_core *glamo,
89439 +                                u_int16_t reg, u_int16_t bit)
89440 +{
89441 +       __reg_set_bit_mask(glamo, reg, bit, 0xffff);
89442 +}
89443 +
89444 +static inline void __reg_clear_bit(struct glamo_core *glamo,
89445 +                                  u_int16_t reg, u_int16_t bit)
89446 +{
89447 +       __reg_set_bit_mask(glamo, reg, bit, 0);
89448 +}
89449 +
89450 +static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
89451 +                                   u_int16_t *src, int len)
89452 +{
89453 +       if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
89454 +               dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
89455 +                       "0x%x)!!\n", addr, src, len);
89456 +       }
89457 +
89458 +}
89459 +
89460 +static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
89461 +                                  u_int32_t addr, int len)
89462 +{
89463 +       if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
89464 +               dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
89465 +                       "0x%x)!!\n", buf, addr, len);
89466 +       }
89467 +
89468 +
89469 +}
89470 +
89471 +/***********************************************************************
89472 + * resources of sibling devices
89473 + ***********************************************************************/
89474 +
89475 +#if 0
89476 +static struct resource glamo_core_resources[] = {
89477 +       {
89478 +               .start  = GLAMO_REGOFS_GENERIC,
89479 +               .end    = GLAMO_REGOFS_GENERIC + 0x400,
89480 +               .flags  = IORESOURCE_MEM,
89481 +       }, {
89482 +               .start  = 0,
89483 +               .end    = 0,
89484 +               .flags  = IORESOURCE_IRQ,
89485 +       },
89486 +};
89487 +
89488 +static struct platform_device glamo_core_dev = {
89489 +       .name           = "glamo-core",
89490 +       .resource       = &glamo_core_resources,
89491 +       .num_resources  = ARRAY_SIZE(glamo_core_resources),
89492 +};
89493 +#endif
89494 +
89495 +static struct resource glamo_jpeg_resources[] = {
89496 +       {
89497 +               .start  = GLAMO_REGOFS_JPEG,
89498 +               .end    = GLAMO_REGOFS_MPEG - 1,
89499 +               .flags  = IORESOURCE_MEM,
89500 +       }, {
89501 +               .start  = IRQ_GLAMO_JPEG,
89502 +               .end    = IRQ_GLAMO_JPEG,
89503 +               .flags  = IORESOURCE_IRQ,
89504 +       },
89505 +};
89506 +
89507 +static struct platform_device glamo_jpeg_dev = {
89508 +       .name           = "glamo-jpeg",
89509 +       .resource       = glamo_jpeg_resources,
89510 +       .num_resources  = ARRAY_SIZE(glamo_jpeg_resources),
89511 +};
89512 +
89513 +static struct resource glamo_mpeg_resources[] = {
89514 +       {
89515 +               .start  = GLAMO_REGOFS_MPEG,
89516 +               .end    = GLAMO_REGOFS_LCD - 1,
89517 +               .flags  = IORESOURCE_MEM,
89518 +       }, {
89519 +               .start  = IRQ_GLAMO_MPEG,
89520 +               .end    = IRQ_GLAMO_MPEG,
89521 +               .flags  = IORESOURCE_IRQ,
89522 +       },
89523 +};
89524 +
89525 +static struct platform_device glamo_mpeg_dev = {
89526 +       .name           = "glamo-mpeg",
89527 +       .resource       = glamo_mpeg_resources,
89528 +       .num_resources  = ARRAY_SIZE(glamo_mpeg_resources),
89529 +};
89530 +
89531 +static struct resource glamo_2d_resources[] = {
89532 +       {
89533 +               .start  = GLAMO_REGOFS_2D,
89534 +               .end    = GLAMO_REGOFS_3D - 1,
89535 +               .flags  = IORESOURCE_MEM,
89536 +       }, {
89537 +               .start  = IRQ_GLAMO_2D,
89538 +               .end    = IRQ_GLAMO_2D,
89539 +               .flags  = IORESOURCE_IRQ,
89540 +       },
89541 +};
89542 +
89543 +static struct platform_device glamo_2d_dev = {
89544 +       .name           = "glamo-2d",
89545 +       .resource       = glamo_2d_resources,
89546 +       .num_resources  = ARRAY_SIZE(glamo_2d_resources),
89547 +};
89548 +
89549 +static struct resource glamo_3d_resources[] = {
89550 +       {
89551 +               .start  = GLAMO_REGOFS_3D,
89552 +               .end    = GLAMO_REGOFS_END - 1,
89553 +               .flags  = IORESOURCE_MEM,
89554 +       },
89555 +};
89556 +
89557 +static struct platform_device glamo_3d_dev = {
89558 +       .name           = "glamo-3d",
89559 +       .resource       = glamo_3d_resources,
89560 +       .num_resources  = ARRAY_SIZE(glamo_3d_resources),
89561 +};
89562 +
89563 +static struct platform_device glamo_spigpio_dev = {
89564 +       .name           = "glamo-spi-gpio",
89565 +};
89566 +
89567 +static struct resource glamo_fb_resources[] = {
89568 +       /* FIXME: those need to be incremented by parent base */
89569 +       {
89570 +               .name   = "glamo-fb-regs",
89571 +               .start  = GLAMO_REGOFS_LCD,
89572 +               .end    = GLAMO_REGOFS_MMC - 1,
89573 +               .flags  = IORESOURCE_MEM,
89574 +       }, {
89575 +               .name   = "glamo-fb-mem",
89576 +               .start  = GLAMO_OFFSET_FB,
89577 +               .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
89578 +               .flags  = IORESOURCE_MEM,
89579 +       },
89580 +};
89581 +
89582 +static struct platform_device glamo_fb_dev = {
89583 +       .name           = "glamo-fb",
89584 +       .resource       = glamo_fb_resources,
89585 +       .num_resources  = ARRAY_SIZE(glamo_fb_resources),
89586 +};
89587 +
89588 +static struct resource glamo_mmc_resources[] = {
89589 +       {
89590 +               /* FIXME: those need to be incremented by parent base */
89591 +               .start  = GLAMO_REGOFS_MMC,
89592 +               .end    = GLAMO_REGOFS_MPROC0 - 1,
89593 +               .flags  = IORESOURCE_MEM
89594 +       }, {
89595 +               .start  = IRQ_GLAMO_MMC,
89596 +               .end    = IRQ_GLAMO_MMC,
89597 +               .flags  = IORESOURCE_IRQ,
89598 +       }, { /* our data buffer for MMC transfers */
89599 +               .start  = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
89600 +               .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
89601 +                                 GLAMO_MMC_BUFFER_SIZE - 1,
89602 +               .flags  = IORESOURCE_MEM
89603 +       },
89604 +};
89605 +
89606 +struct glamo_mci_pdata glamo_mci_def_pdata = {
89607 +       .gpio_detect            = 0,
89608 +       .glamo_can_set_mci_power        = NULL, /* filled in from MFD platform data */
89609 +       .ocr_avail      = MMC_VDD_20_21 |
89610 +                         MMC_VDD_21_22 |
89611 +                         MMC_VDD_22_23 |
89612 +                         MMC_VDD_23_24 |
89613 +                         MMC_VDD_24_25 |
89614 +                         MMC_VDD_25_26 |
89615 +                         MMC_VDD_26_27 |
89616 +                         MMC_VDD_27_28 |
89617 +                         MMC_VDD_28_29 |
89618 +                         MMC_VDD_29_30 |
89619 +                         MMC_VDD_30_31 |
89620 +                         MMC_VDD_32_33,
89621 +       .glamo_irq_is_wired     = NULL, /* filled in from MFD platform data */
89622 +       .mci_suspending = NULL, /* filled in from MFD platform data */
89623 +       .mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
89624 +};
89625 +EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
89626 +
89627 +
89628 +
89629 +static void mangle_mem_resources(struct resource *res, int num_res,
89630 +                                struct resource *parent)
89631 +{
89632 +       int i;
89633 +
89634 +       for (i = 0; i < num_res; i++) {
89635 +               if (res[i].flags != IORESOURCE_MEM)
89636 +                       continue;
89637 +               res[i].start += parent->start;
89638 +               res[i].end += parent->start;
89639 +               res[i].parent = parent;
89640 +       }
89641 +}
89642 +
89643 +/***********************************************************************
89644 + * IRQ demultiplexer
89645 + ***********************************************************************/
89646 +#define irq2glamo(x)   (x - IRQ_GLAMO(0))
89647 +
89648 +static void glamo_ack_irq(unsigned int irq)
89649 +{
89650 +       /* clear interrupt source */
89651 +       __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
89652 +                   1 << irq2glamo(irq));
89653 +}
89654 +
89655 +static void glamo_mask_irq(unsigned int irq)
89656 +{
89657 +       u_int16_t tmp;
89658 +
89659 +       /* clear bit in enable register */
89660 +       tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
89661 +       tmp &= ~(1 << irq2glamo(irq));
89662 +       __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
89663 +}
89664 +
89665 +static void glamo_unmask_irq(unsigned int irq)
89666 +{
89667 +       u_int16_t tmp;
89668 +
89669 +       /* set bit in enable register */
89670 +       tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
89671 +       tmp |= (1 << irq2glamo(irq));
89672 +       __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
89673 +}
89674 +
89675 +static struct irq_chip glamo_irq_chip = {
89676 +       .ack    = glamo_ack_irq,
89677 +       .mask   = glamo_mask_irq,
89678 +       .unmask = glamo_unmask_irq,
89679 +};
89680 +
89681 +static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
89682 +{
89683 +       const unsigned int cpu = smp_processor_id();
89684 +
89685 +       desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
89686 +
89687 +       if (unlikely(desc->status & IRQ_INPROGRESS)) {
89688 +               desc->status |= (IRQ_PENDING | IRQ_MASKED);
89689 +               desc->chip->mask(irq);
89690 +               desc->chip->ack(irq);
89691 +               return;
89692 +       }
89693 +
89694 +       kstat_cpu(cpu).irqs[irq]++;
89695 +       desc->chip->ack(irq);
89696 +       desc->status |= IRQ_INPROGRESS;
89697 +
89698 +       do {
89699 +               u_int16_t irqstatus;
89700 +               int i;
89701 +
89702 +               if (unlikely((desc->status &
89703 +                               (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
89704 +                               (IRQ_PENDING | IRQ_MASKED))) {
89705 +                       /* dealing with pending IRQ, unmasking */
89706 +                       desc->chip->unmask(irq);
89707 +                       desc->status &= ~IRQ_MASKED;
89708 +               }
89709 +
89710 +               desc->status &= ~IRQ_PENDING;
89711 +
89712 +               /* read IRQ status register */
89713 +               irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
89714 +               for (i = 0; i < 9; i++)
89715 +                       if (irqstatus & (1 << i))
89716 +                               desc_handle_irq(IRQ_GLAMO(i),
89717 +                                   irq_desc+IRQ_GLAMO(i));
89718 +
89719 +       } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
89720 +
89721 +       desc->status &= ~IRQ_INPROGRESS;
89722 +}
89723 +
89724 +
89725 +static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
89726 +                          const char *buf, size_t count)
89727 +{
89728 +       unsigned long reg = simple_strtoul(buf, NULL, 10);
89729 +       struct glamo_core *glamo = dev_get_drvdata(dev);
89730 +
89731 +       while (*buf && (*buf != ' '))
89732 +               buf++;
89733 +       if (*buf != ' ')
89734 +               return -EINVAL;
89735 +       while (*buf && (*buf == ' '))
89736 +               buf++;
89737 +       if (!*buf)
89738 +               return -EINVAL;
89739 +
89740 +       printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
89741 +              reg, simple_strtoul(buf, NULL, 10));
89742 +
89743 +       __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
89744 +
89745 +       return count;
89746 +}
89747 +
89748 +static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
89749 +                       char *buf)
89750 +{
89751 +       struct glamo_core *glamo = dev_get_drvdata(dev);
89752 +       int n, n1 = 0, r;
89753 +       char * end = buf;
89754 +
89755 +       spin_lock(&glamo->lock);
89756 +
89757 +       for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
89758 +               if (!reg_range[r].dump)
89759 +                       continue;
89760 +               n1 = 0;
89761 +               end += sprintf(end, "\n%s\n", reg_range[r].name);
89762 +               for (n = reg_range[r].start;
89763 +                    n < reg_range[r].start + reg_range[r].count; n += 2) {
89764 +                       if (((n1++) & 7) == 0)
89765 +                               end += sprintf(end, "\n%04X:  ", n);
89766 +                       end += sprintf(end, "%04x ", __reg_read(glamo, n));
89767 +               }
89768 +               end += sprintf(end, "\n");
89769 +               if (!attr) {
89770 +                       printk("%s", buf);
89771 +                       end = buf;
89772 +               }
89773 +       }
89774 +       spin_unlock(&glamo->lock);
89775 +
89776 +       return end - buf;
89777 +}
89778 +
89779 +static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
89780 +static struct attribute *glamo_sysfs_entries[] = {
89781 +       &dev_attr_regs.attr,
89782 +       NULL
89783 +};
89784 +static struct attribute_group glamo_attr_group = {
89785 +       .name   = NULL,
89786 +       .attrs  = glamo_sysfs_entries,
89787 +};
89788 +
89789 +
89790 +
89791 +/***********************************************************************
89792 + * 'engine' support
89793 + ***********************************************************************/
89794 +
89795 +int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
89796 +{
89797 +       switch (engine) {
89798 +       case GLAMO_ENGINE_LCD:
89799 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
89800 +                                  GLAMO_HOSTBUS2_MMIO_EN_LCD,
89801 +                                  GLAMO_HOSTBUS2_MMIO_EN_LCD);
89802 +               __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
89803 +                           GLAMO_CLOCK_LCD_EN_M5CLK |
89804 +                           GLAMO_CLOCK_LCD_EN_DHCLK |
89805 +                           GLAMO_CLOCK_LCD_EN_DMCLK |
89806 +                           GLAMO_CLOCK_LCD_EN_DCLK |
89807 +                           GLAMO_CLOCK_LCD_DG_M5CLK |
89808 +                           GLAMO_CLOCK_LCD_DG_DMCLK);
89809 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89810 +                           GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
89811 +                           GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
89812 +                           GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
89813 +               break;
89814 +       case GLAMO_ENGINE_MMC:
89815 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
89816 +                                  GLAMO_HOSTBUS2_MMIO_EN_MMC,
89817 +                                  GLAMO_HOSTBUS2_MMIO_EN_MMC);
89818 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
89819 +                                  GLAMO_CLOCK_MMC_EN_M9CLK |
89820 +                                  GLAMO_CLOCK_MMC_EN_TCLK |
89821 +                                  GLAMO_CLOCK_MMC_DG_M9CLK |
89822 +                                  GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
89823 +               /* enable the TCLK divider clk input */
89824 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89825 +                                                GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
89826 +                                                GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
89827 +               break;
89828 +       case GLAMO_ENGINE_2D:
89829 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
89830 +                                  GLAMO_CLOCK_2D_EN_M7CLK |
89831 +                                  GLAMO_CLOCK_2D_EN_GCLK |
89832 +                                  GLAMO_CLOCK_2D_DG_M7CLK |
89833 +                                  GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
89834 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
89835 +                                  GLAMO_HOSTBUS2_MMIO_EN_2D,
89836 +                                  GLAMO_HOSTBUS2_MMIO_EN_2D);
89837 +               break;
89838 +       case GLAMO_ENGINE_CMDQ:
89839 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
89840 +                                  GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
89841 +               __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
89842 +                                  GLAMO_HOSTBUS2_MMIO_EN_CQ,
89843 +                                  GLAMO_HOSTBUS2_MMIO_EN_CQ);
89844 +               break;
89845 +       /* FIXME: Implementation */
89846 +       default:
89847 +               break;
89848 +       }
89849 +
89850 +       glamo->engine_enabled_bitfield |= 1 << engine;
89851 +
89852 +       return 0;
89853 +}
89854 +
89855 +int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
89856 +{
89857 +       int ret;
89858 +
89859 +       spin_lock(&glamo->lock);
89860 +
89861 +       ret = __glamo_engine_enable(glamo, engine);
89862 +
89863 +       spin_unlock(&glamo->lock);
89864 +
89865 +       return ret;
89866 +}
89867 +EXPORT_SYMBOL_GPL(glamo_engine_enable);
89868 +
89869 +int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
89870 +{
89871 +       switch (engine) {
89872 +       case GLAMO_ENGINE_LCD:
89873 +               /* remove pixel clock to LCM */
89874 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
89875 +                           GLAMO_CLOCK_LCD_EN_DCLK, 0);
89876 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
89877 +                           GLAMO_CLOCK_LCD_EN_DHCLK |
89878 +                           GLAMO_CLOCK_LCD_EN_DMCLK, 0);
89879 +               /* kill memory clock */
89880 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
89881 +                           GLAMO_CLOCK_LCD_EN_M5CLK, 0);
89882 +               /* stop dividing the clocks */
89883 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89884 +                           GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
89885 +                           GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
89886 +                           GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
89887 +               break;
89888 +
89889 +       case GLAMO_ENGINE_MMC:
89890 +//             __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
89891 +//                                                GLAMO_CLOCK_MMC_EN_M9CLK |
89892 +//                                                GLAMO_CLOCK_MMC_EN_TCLK |
89893 +//                                                GLAMO_CLOCK_MMC_DG_M9CLK |
89894 +//                                                GLAMO_CLOCK_MMC_DG_TCLK, 0);
89895 +               /* disable the TCLK divider clk input */
89896 +//             __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
89897 +//                                     GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
89898 +
89899 +       default:
89900 +               break;
89901 +       }
89902 +
89903 +       glamo->engine_enabled_bitfield &= ~(1 << engine);
89904 +
89905 +       return 0;
89906 +}
89907 +int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
89908 +{
89909 +       int ret;
89910 +
89911 +       spin_lock(&glamo->lock);
89912 +
89913 +       ret = __glamo_engine_disable(glamo, engine);
89914 +
89915 +       spin_unlock(&glamo->lock);
89916 +
89917 +       return ret;
89918 +}
89919 +EXPORT_SYMBOL_GPL(glamo_engine_disable);
89920 +
89921 +static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
89922 +       [GLAMO_ENGINE_LCD]      = GLAMO_REG_CLOCK_LCD,
89923 +       [GLAMO_ENGINE_MMC]      = GLAMO_REG_CLOCK_MMC,
89924 +       [GLAMO_ENGINE_ISP]      = GLAMO_REG_CLOCK_ISP,
89925 +       [GLAMO_ENGINE_JPEG]     = GLAMO_REG_CLOCK_JPEG,
89926 +       [GLAMO_ENGINE_3D]       = GLAMO_REG_CLOCK_3D,
89927 +       [GLAMO_ENGINE_2D]       = GLAMO_REG_CLOCK_2D,
89928 +       [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
89929 +       [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
89930 +};
89931 +
89932 +void glamo_engine_clkreg_set(struct glamo_core *glamo,
89933 +                            enum glamo_engine engine,
89934 +                            u_int16_t mask, u_int16_t val)
89935 +{
89936 +       reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
89937 +}
89938 +EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
89939 +
89940 +u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
89941 +                                 enum glamo_engine engine)
89942 +{
89943 +       u_int16_t val;
89944 +
89945 +       spin_lock(&glamo->lock);
89946 +       val = __reg_read(glamo, engine_clock_regs[engine]);
89947 +       spin_unlock(&glamo->lock);
89948 +
89949 +       return val;
89950 +}
89951 +EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
89952 +
89953 +struct glamo_script reset_regs[] = {
89954 +       [GLAMO_ENGINE_LCD] = {
89955 +               GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
89956 +       },
89957 +#if 0
89958 +       [GLAMO_ENGINE_HOST] = {
89959 +               GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
89960 +       },
89961 +       [GLAMO_ENGINE_MEM] = {
89962 +               GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
89963 +       },
89964 +#endif
89965 +       [GLAMO_ENGINE_MMC] = {
89966 +               GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
89967 +       },
89968 +       [GLAMO_ENGINE_2D] = {
89969 +               GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
89970 +       },
89971 +       [GLAMO_ENGINE_JPEG] = {
89972 +               GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
89973 +       },
89974 +};
89975 +
89976 +void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
89977 +{
89978 +       struct glamo_script *rst;
89979 +
89980 +       if (engine >= ARRAY_SIZE(reset_regs)) {
89981 +               dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
89982 +               return;
89983 +       }
89984 +
89985 +       rst = &reset_regs[engine];
89986 +
89987 +       spin_lock(&glamo->lock);
89988 +       __reg_set_bit(glamo, rst->reg, rst->val);
89989 +       __reg_clear_bit(glamo, rst->reg, rst->val);
89990 +       spin_unlock(&glamo->lock);
89991 +}
89992 +EXPORT_SYMBOL_GPL(glamo_engine_reset);
89993 +
89994 +void glamo_lcm_reset(int level)
89995 +{
89996 +       if (!glamo_handle)
89997 +               return;
89998 +
89999 +       glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
90000 +       glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
90001 +
90002 +}
90003 +EXPORT_SYMBOL_GPL(glamo_lcm_reset);
90004 +
90005 +enum glamo_pll {
90006 +       GLAMO_PLL1,
90007 +       GLAMO_PLL2,
90008 +};
90009 +
90010 +static int glamo_pll_rate(struct glamo_core *glamo,
90011 +                         enum glamo_pll pll)
90012 +{
90013 +       u_int16_t reg;
90014 +       unsigned int div = 512;
90015 +       /* FIXME: move osci into platform_data */
90016 +       unsigned int osci = 32768;
90017 +
90018 +       if (osci == 32768)
90019 +               div = 1;
90020 +
90021 +       switch (pll) {
90022 +       case GLAMO_PLL1:
90023 +               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
90024 +               break;
90025 +       case GLAMO_PLL2:
90026 +               reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
90027 +               break;
90028 +       default:
90029 +               return -EINVAL;
90030 +       }
90031 +       return (osci/div)*reg;
90032 +}
90033 +
90034 +int glamo_engine_reclock(struct glamo_core *glamo,
90035 +                        enum glamo_engine engine,
90036 +                        int ps)
90037 +{
90038 +       int pll, khz;
90039 +       u_int16_t reg, mask, val = 0;
90040 +
90041 +       if (!ps)
90042 +               return 0;
90043 +
90044 +       switch (engine) {
90045 +       case GLAMO_ENGINE_LCD:
90046 +               pll = GLAMO_PLL1;
90047 +               reg = GLAMO_REG_CLOCK_GEN7;
90048 +               mask = 0xff;
90049 +               break;
90050 +       default:
90051 +               dev_warn(&glamo->pdev->dev,
90052 +                        "reclock of engine 0x%x not supported\n", engine);
90053 +               return -EINVAL;
90054 +               break;
90055 +       }
90056 +
90057 +       pll = glamo_pll_rate(glamo, pll);
90058 +       khz = 1000000000UL / ps;
90059 +
90060 +       if (khz)
90061 +               val = (pll / khz) / 1000;
90062 +
90063 +       dev_dbg(&glamo->pdev->dev,
90064 +                       "PLL %d, kHZ %d, div %d\n", pll, khz, val);
90065 +
90066 +       if (val) {
90067 +               val--;
90068 +               reg_set_bit_mask(glamo, reg, mask, val);
90069 +               mdelay(5); /* wait some time to stabilize */
90070 +
90071 +               return 0;
90072 +       } else {
90073 +               return -EINVAL;
90074 +       }
90075 +}
90076 +EXPORT_SYMBOL_GPL(glamo_engine_reclock);
90077 +
90078 +/***********************************************************************
90079 + * script support
90080 + ***********************************************************************/
90081 +
90082 +int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
90083 +                    int len, int may_sleep)
90084 +{
90085 +       int i;
90086 +
90087 +       for (i = 0; i < len; i++) {
90088 +               struct glamo_script *line = &script[i];
90089 +
90090 +               switch (line->reg) {
90091 +               case 0xffff:
90092 +                       return 0;
90093 +               case 0xfffe:
90094 +                       if (may_sleep)
90095 +                               msleep(line->val);
90096 +                       else
90097 +                               mdelay(line->val * 4);
90098 +                       break;
90099 +               case 0xfffd:
90100 +                       /* spin until PLLs lock */
90101 +                       while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
90102 +                               ;
90103 +                       break;
90104 +               default:
90105 +                       __reg_write(glamo, script[i].reg, script[i].val);
90106 +                       break;
90107 +               }
90108 +       }
90109 +
90110 +       return 0;
90111 +}
90112 +EXPORT_SYMBOL(glamo_run_script);
90113 +
90114 +static struct glamo_script glamo_init_script[] = {
90115 +       { GLAMO_REG_CLOCK_HOST,         0x1000 },
90116 +               { 0xfffe, 2 },
90117 +       { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
90118 +       { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
90119 +       { GLAMO_REG_CLOCK_LCD,          0x1000 },
90120 +       { GLAMO_REG_CLOCK_MMC,          0x1000 },
90121 +       { GLAMO_REG_CLOCK_ISP,          0x1000 },
90122 +       { GLAMO_REG_CLOCK_ISP,          0x3000 },
90123 +       { GLAMO_REG_CLOCK_JPEG,         0x1000 },
90124 +       { GLAMO_REG_CLOCK_3D,           0x1000 },
90125 +       { GLAMO_REG_CLOCK_3D,           0x3000 },
90126 +       { GLAMO_REG_CLOCK_2D,           0x1000 },
90127 +       { GLAMO_REG_CLOCK_2D,           0x3000 },
90128 +       { GLAMO_REG_CLOCK_RISC1,        0x1000 },
90129 +       { GLAMO_REG_CLOCK_MPEG,         0x3000 },
90130 +       { GLAMO_REG_CLOCK_MPEG,         0x3000 },
90131 +       { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
90132 +               { 0xfffe, 2 },
90133 +       { GLAMO_REG_CLOCK_HOST,         0x0000 },
90134 +       { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
90135 +       { GLAMO_REG_CLOCK_LCD,          0x0000 },
90136 +       { GLAMO_REG_CLOCK_MMC,          0x0000 },
90137 +#if 0
90138 +/* unused engines must be left in reset to stop MMC block read "blackouts" */
90139 +       { GLAMO_REG_CLOCK_ISP,          0x0000 },
90140 +       { GLAMO_REG_CLOCK_ISP,          0x0000 },
90141 +       { GLAMO_REG_CLOCK_JPEG,         0x0000 },
90142 +       { GLAMO_REG_CLOCK_3D,           0x0000 },
90143 +       { GLAMO_REG_CLOCK_3D,           0x0000 },
90144 +       { GLAMO_REG_CLOCK_2D,           0x0000 },
90145 +       { GLAMO_REG_CLOCK_2D,           0x0000 },
90146 +       { GLAMO_REG_CLOCK_RISC1,        0x0000 },
90147 +       { GLAMO_REG_CLOCK_MPEG,         0x0000 },
90148 +       { GLAMO_REG_CLOCK_MPEG,         0x0000 },
90149 +#endif
90150 +       { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
90151 +       { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
90152 +       { 0xfffd, 0 },
90153 +       /*
90154 +        * b9 of this register MUST be zero to get any interrupts on INT#
90155 +        * the other set bits enable all the engine interrupt sources
90156 +        */
90157 +       { GLAMO_REG_IRQ_ENABLE,         0x01ff },
90158 +       { GLAMO_REG_CLOCK_GEN6,         0x2000 },
90159 +       { GLAMO_REG_CLOCK_GEN7,         0x0101 },
90160 +       { GLAMO_REG_CLOCK_GEN8,         0x0100 },
90161 +       { GLAMO_REG_CLOCK_HOST,         0x000d },
90162 +       /*
90163 +        * b7..b4 = 0 = no wait states on read or write
90164 +        * b0 = 1 select PLL2 for Host interface, b1 = enable it
90165 +        */
90166 +       { 0x200,        0x0e03 },
90167 +       { 0x202,        0x07ff },
90168 +       { 0x212,        0x0000 },
90169 +       { 0x214,        0x4000 },
90170 +       { 0x216,        0xf00e },
90171 +
90172 +       /* S-Media recommended "set tiling mode to 512 mode for memory access
90173 +        * more efficiency when 640x480" */
90174 +       { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
90175 +       { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
90176 +
90177 +       { GLAMO_REGOFS_HOSTBUS + 2,     0xffff }, /* enable  on MMIO*/
90178 +
90179 +       { GLAMO_REG_MEM_TIMING1,        0x0108 },
90180 +       { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
90181 +       { GLAMO_REG_MEM_TIMING3,        0x0000 },
90182 +       { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
90183 +       { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
90184 +       { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
90185 +       { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
90186 +       { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
90187 +       { GLAMO_REG_MEM_TIMING9,        0x6006 },
90188 +       { GLAMO_REG_MEM_TIMING10,       0x00ff },
90189 +       { GLAMO_REG_MEM_TIMING11,       0x0001 },
90190 +       { GLAMO_REG_MEM_POWER1,         0x0020 },
90191 +       { GLAMO_REG_MEM_POWER2,         0x0000 },
90192 +       { GLAMO_REG_MEM_DRAM1,          0x0000 },
90193 +               { 0xfffe, 1 },
90194 +       { GLAMO_REG_MEM_DRAM1,          0xc100 },
90195 +               { 0xfffe, 1 },
90196 +       { GLAMO_REG_MEM_DRAM1,          0xe100 },
90197 +       { GLAMO_REG_MEM_DRAM2,          0x01d6 },
90198 +       { GLAMO_REG_CLOCK_MEMORY,       0x000b },
90199 +       { GLAMO_REG_GPIO_GEN1,          0x000f },
90200 +       { GLAMO_REG_GPIO_GEN2,          0x111e },
90201 +       { GLAMO_REG_GPIO_GEN3,          0xccc3 },
90202 +       { GLAMO_REG_GPIO_GEN4,          0x111e },
90203 +       { GLAMO_REG_GPIO_GEN5,          0x000f },
90204 +};
90205 +#if 0
90206 +static struct glamo_script glamo_resume_script[] = {
90207 +
90208 +       { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
90209 +       { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
90210 +       { GLAMO_REG_DFT_GEN6, 1 },
90211 +               { 0xfffe, 100 },
90212 +               { 0xfffd, 0 },
90213 +       { 0x200,        0x0e03 },
90214 +
90215 +       /*
90216 +        * b9 of this register MUST be zero to get any interrupts on INT#
90217 +        * the other set bits enable all the engine interrupt sources
90218 +        */
90219 +       { GLAMO_REG_IRQ_ENABLE,         0x01ff },
90220 +       { GLAMO_REG_CLOCK_HOST,         0x0018 },
90221 +       { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
90222 +
90223 +       { GLAMO_REG_MEM_DRAM1,          0x0000 },
90224 +               { 0xfffe, 1 },
90225 +       { GLAMO_REG_MEM_DRAM1,          0xc100 },
90226 +               { 0xfffe, 1 },
90227 +       { GLAMO_REG_MEM_DRAM1,          0xe100 },
90228 +       { GLAMO_REG_MEM_DRAM2,          0x01d6 },
90229 +       { GLAMO_REG_CLOCK_MEMORY,       0x000b },
90230 +};
90231 +#endif
90232 +
90233 +enum glamo_power {
90234 +       GLAMO_POWER_ON,
90235 +       GLAMO_POWER_SUSPEND,
90236 +};
90237 +
90238 +static void glamo_power(struct glamo_core *glamo,
90239 +                       enum glamo_power new_state)
90240 +{
90241 +       int n;
90242 +       unsigned long flags;
90243 +
90244 +       spin_lock_irqsave(&glamo->lock, flags);
90245 +
90246 +       dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
90247 +
90248 +       /*
90249 +Power management
90250 +static const REG_VALUE_MASK_TYPE reg_powerOn[] =
90251 +{
90252 +    { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
90253 +    { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
90254 +    { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
90255 +    { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
90256 +    { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
90257 +};
90258 +
90259 +static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
90260 +{
90261 +    { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
90262 +    { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
90263 +    { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
90264 +    { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
90265 +};
90266 +
90267 +static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
90268 +{
90269 +    { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
90270 +    { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
90271 +    { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
90272 +    { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
90273 +};
90274 +*/
90275 +
90276 +       switch (new_state) {
90277 +       case GLAMO_POWER_ON:
90278 +
90279 +               /*
90280 +                * glamo state on resume is nondeterministic in some
90281 +                * fundamental way, it has also been observed that the
90282 +                * Glamo reset pin can get asserted by, eg, touching it with
90283 +                * a scope probe.  So the only answer is to roll with it and
90284 +                * force an external reset on the Glamo during resume.
90285 +                */
90286 +
90287 +               (glamo->pdata->glamo_external_reset)(0);
90288 +               udelay(10);
90289 +               (glamo->pdata->glamo_external_reset)(1);
90290 +               mdelay(5);
90291 +
90292 +               glamo_run_script(glamo, glamo_init_script,
90293 +                        ARRAY_SIZE(glamo_init_script), 0);
90294 +
90295 +               break;
90296 +
90297 +       case GLAMO_POWER_SUSPEND:
90298 +
90299 +               /* nuke interrupts */
90300 +               __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
90301 +
90302 +               /* stash a copy of which engines were running */
90303 +               glamo->engine_enabled_bitfield_suspend =
90304 +                                                glamo->engine_enabled_bitfield;
90305 +
90306 +               /* take down each engine before we kill mem and pll */
90307 +               for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
90308 +                       if (glamo->engine_enabled_bitfield & (1 << n))
90309 +                               __glamo_engine_disable(glamo, n);
90310 +
90311 +               /* enable self-refresh */
90312 +
90313 +               __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
90314 +                                       GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
90315 +                                       GLAMO_MEM_DRAM1_EN_GATE_CKE |
90316 +                                       GLAMO_MEM_DRAM1_SELF_REFRESH |
90317 +                                       GLAMO_MEM_REFRESH_COUNT);
90318 +               __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
90319 +                                       GLAMO_MEM_DRAM1_EN_MODEREG_SET |
90320 +                                       GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
90321 +                                       GLAMO_MEM_DRAM1_EN_GATE_CKE |
90322 +                                       GLAMO_MEM_DRAM1_SELF_REFRESH |
90323 +                                       GLAMO_MEM_REFRESH_COUNT);
90324 +
90325 +               /* force RAM into deep powerdown */
90326 +
90327 +               __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
90328 +                                       GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
90329 +                                       (7 << 6) | /* tRC */
90330 +                                       (1 << 4) | /* tRP */
90331 +                                       (1 << 2) | /* tRCD */
90332 +                                       2); /* CAS latency */
90333 +
90334 +               /* disable clocks to memory */
90335 +               __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
90336 +
90337 +               /* all dividers from OSCI */
90338 +               __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
90339 +
90340 +               /* PLL2 into bypass */
90341 +               __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
90342 +
90343 +               __reg_write(glamo, 0x200, 0x0e00);
90344 +
90345 +
90346 +               /* kill PLLS 1 then 2 */
90347 +               __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
90348 +               __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
90349 +
90350 +               break;
90351 +       }
90352 +
90353 +       spin_unlock_irqrestore(&glamo->lock, flags);
90354 +}
90355 +
90356 +#if 0
90357 +#define MEMDETECT_RETRY        6
90358 +static unsigned int detect_memsize(struct glamo_core *glamo)
90359 +{
90360 +       int i;
90361 +
90362 +       /*static const u_int16_t pattern[] = {
90363 +               0x1111, 0x8a8a, 0x2222, 0x7a7a,
90364 +               0x3333, 0x6a6a, 0x4444, 0x5a5a,
90365 +               0x5555, 0x4a4a, 0x6666, 0x3a3a,
90366 +               0x7777, 0x2a2a, 0x8888, 0x1a1a
90367 +       }; */
90368 +
90369 +       for (i = 0; i < MEMDETECT_RETRY; i++) {
90370 +               switch (glamo->type) {
90371 +               case 3600:
90372 +                       __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
90373 +                       __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
90374 +                       break;
90375 +               case 3650:
90376 +                       switch (glamo->revision) {
90377 +                       case GLAMO_CORE_REV_A0:
90378 +                               if (i & 1)
90379 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
90380 +                                                   0x097a);
90381 +                               else
90382 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
90383 +                                                   0x0173);
90384 +
90385 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
90386 +                               msleep(1);
90387 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
90388 +                               break;
90389 +                       default:
90390 +                               if (i & 1)
90391 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
90392 +                                                   0x0972);
90393 +                               else
90394 +                                       __reg_write(glamo, GLAMO_REG_MEM_TYPE,
90395 +                                                   0x0872);
90396 +
90397 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
90398 +                               msleep(1);
90399 +                               __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
90400 +                               break;
90401 +                       }
90402 +                       break;
90403 +               case 3700:
90404 +                       /* FIXME */
90405 +               default:
90406 +                       break;
90407 +               }
90408 +
90409 +#if 0
90410 +               /* FIXME: finish implementation */
90411 +               for (j = 0; j < 8; j++) {
90412 +                       __
90413 +#endif
90414 +       }
90415 +
90416 +       return 0;
90417 +}
90418 +#endif
90419 +
90420 +/* Find out if we can support this version of the Glamo chip */
90421 +static int glamo_supported(struct glamo_core *glamo)
90422 +{
90423 +       u_int16_t dev_id, rev_id; /*, memsize; */
90424 +
90425 +       dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
90426 +       rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
90427 +
90428 +       switch (dev_id) {
90429 +       case 0x3650:
90430 +               switch (rev_id) {
90431 +               case GLAMO_CORE_REV_A2:
90432 +                       break;
90433 +               case GLAMO_CORE_REV_A0:
90434 +               case GLAMO_CORE_REV_A1:
90435 +               case GLAMO_CORE_REV_A3:
90436 +                       dev_warn(&glamo->pdev->dev, "untested core revision "
90437 +                                "%04x, your mileage may vary\n", rev_id);
90438 +                       break;
90439 +               default:
90440 +                       dev_warn(&glamo->pdev->dev, "unknown glamo revision "
90441 +                                "%04x, your mileage may vary\n", rev_id);
90442 +                       /* maybe should abort ? */
90443 +               }
90444 +               break;
90445 +       case 0x3600:
90446 +       case 0x3700:
90447 +       default:
90448 +               dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
90449 +                       dev_id);
90450 +               return 0;
90451 +       }
90452 +
90453 +       dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
90454 +                "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
90455 +                glamo_pll_rate(glamo, GLAMO_PLL1),
90456 +                glamo_pll_rate(glamo, GLAMO_PLL2));
90457 +
90458 +       return 1;
90459 +}
90460 +
90461 +static int __init glamo_probe(struct platform_device *pdev)
90462 +{
90463 +       int rc = 0, irq;
90464 +       struct glamo_core *glamo;
90465 +       struct platform_device *glamo_mmc_dev;
90466 +
90467 +       if (glamo_handle) {
90468 +               dev_err(&pdev->dev,
90469 +                       "This driver supports only one instance\n");
90470 +               return -EBUSY;
90471 +       }
90472 +
90473 +       glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
90474 +       if (!glamo)
90475 +               return -ENOMEM;
90476 +
90477 +       spin_lock_init(&glamo->lock);
90478 +       glamo_handle = glamo;
90479 +       glamo->pdev = pdev;
90480 +       glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
90481 +       glamo->irq = platform_get_irq(pdev, 0);
90482 +       glamo->pdata = pdev->dev.platform_data;
90483 +       if (!glamo->mem || !glamo->pdata) {
90484 +               dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
90485 +               rc = -ENOENT;
90486 +               goto bail_free;
90487 +       }
90488 +
90489 +       /* register a number of sibling devices whoise IOMEM resources
90490 +        * are siblings of pdev's IOMEM resource */
90491 +#if 0
90492 +       glamo_core_dev.dev.parent = &pdev.dev;
90493 +       mangle_mem_resources(glamo_core_dev.resources,
90494 +                            glamo_core_dev.num_resources, glamo->mem);
90495 +       glamo_core_dev.resources[1].start = glamo->irq;
90496 +       glamo_core_dev.resources[1].end = glamo->irq;
90497 +       platform_device_register(&glamo_core_dev);
90498 +#endif
90499 +       /* only remap the generic, hostbus and memory controller registers */
90500 +       glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
90501 +       if (!glamo->base) {
90502 +               dev_err(&pdev->dev, "failed to ioremap() memory region\n");
90503 +               goto bail_free;
90504 +       }
90505 +
90506 +       platform_set_drvdata(pdev, glamo);
90507 +
90508 +       (glamo->pdata->glamo_external_reset)(0);
90509 +       udelay(10);
90510 +       (glamo->pdata->glamo_external_reset)(1);
90511 +       mdelay(10);
90512 +
90513 +       /*
90514 +        * finally set the mfd interrupts up
90515 +        * can't do them earlier or sibling probes blow up
90516 +        */
90517 +
90518 +       for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
90519 +               set_irq_chip(irq, &glamo_irq_chip);
90520 +               set_irq_handler(irq, handle_level_irq);
90521 +               set_irq_flags(irq, IRQF_VALID);
90522 +       }
90523 +
90524 +       if (glamo->pdata->glamo_irq_is_wired &&
90525 +           !glamo->pdata->glamo_irq_is_wired()) {
90526 +               set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
90527 +               set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
90528 +               dev_info(&pdev->dev, "Glamo interrupt registered\n");
90529 +               glamo->irq_works = 1;
90530 +       } else {
90531 +               dev_err(&pdev->dev, "Glamo interrupt not used\n");
90532 +               glamo->irq_works = 0;
90533 +       }
90534 +
90535 +
90536 +       /* confirm it isn't insane version */
90537 +       if (!glamo_supported(glamo)) {
90538 +               dev_err(&pdev->dev, "This Glamo is not supported\n");
90539 +               goto bail_irq;
90540 +       }
90541 +
90542 +       /* sysfs */
90543 +       rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
90544 +       if (rc < 0) {
90545 +               dev_err(&pdev->dev, "cannot create sysfs group\n");
90546 +               goto bail_irq;
90547 +       }
90548 +
90549 +       /* init the chip with canned register set */
90550 +
90551 +       dev_dbg(&glamo->pdev->dev, "running init script\n");
90552 +       glamo_run_script(glamo, glamo_init_script,
90553 +                        ARRAY_SIZE(glamo_init_script), 1);
90554 +
90555 +       dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
90556 +                glamo_pll_rate(glamo, GLAMO_PLL1),
90557 +                glamo_pll_rate(glamo, GLAMO_PLL2));
90558 +
90559 +       /* bring MCI specific stuff over from our MFD platform data */
90560 +       glamo_mci_def_pdata.glamo_can_set_mci_power =
90561 +                                       glamo->pdata->glamo_can_set_mci_power;
90562 +       glamo_mci_def_pdata.glamo_mci_use_slow =
90563 +                                       glamo->pdata->glamo_mci_use_slow;
90564 +       glamo_mci_def_pdata.glamo_irq_is_wired =
90565 +                                       glamo->pdata->glamo_irq_is_wired;
90566 +
90567 +       /* start creating the siblings */
90568 +
90569 +       glamo_2d_dev.dev.parent = &pdev->dev;
90570 +       mangle_mem_resources(glamo_2d_dev.resource,
90571 +                            glamo_2d_dev.num_resources, glamo->mem);
90572 +       platform_device_register(&glamo_2d_dev);
90573 +
90574 +       glamo_3d_dev.dev.parent = &pdev->dev;
90575 +       mangle_mem_resources(glamo_3d_dev.resource,
90576 +                            glamo_3d_dev.num_resources, glamo->mem);
90577 +       platform_device_register(&glamo_3d_dev);
90578 +
90579 +       glamo_jpeg_dev.dev.parent = &pdev->dev;
90580 +       mangle_mem_resources(glamo_jpeg_dev.resource,
90581 +                            glamo_jpeg_dev.num_resources, glamo->mem);
90582 +       platform_device_register(&glamo_jpeg_dev);
90583 +
90584 +       glamo_mpeg_dev.dev.parent = &pdev->dev;
90585 +       mangle_mem_resources(glamo_mpeg_dev.resource,
90586 +                            glamo_mpeg_dev.num_resources, glamo->mem);
90587 +       platform_device_register(&glamo_mpeg_dev);
90588 +
90589 +       glamo->pdata->glamo = glamo;
90590 +       glamo_fb_dev.dev.parent = &pdev->dev;
90591 +       glamo_fb_dev.dev.platform_data = glamo->pdata;
90592 +       mangle_mem_resources(glamo_fb_dev.resource,
90593 +                            glamo_fb_dev.num_resources, glamo->mem);
90594 +       platform_device_register(&glamo_fb_dev);
90595 +
90596 +       glamo->pdata->spigpio_info->glamo = glamo;
90597 +       glamo_spigpio_dev.dev.parent = &pdev->dev;
90598 +       glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
90599 +       platform_device_register(&glamo_spigpio_dev);
90600 +
90601 +       glamo_mmc_dev = glamo->pdata->mmc_dev;
90602 +       glamo_mmc_dev->name = "glamo-mci";
90603 +       glamo_mmc_dev->dev.parent = &pdev->dev;
90604 +       glamo_mmc_dev->resource = glamo_mmc_resources;
90605 +       glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
90606 +
90607 +       /* we need it later to give to the engine enable and disable */
90608 +       glamo_mci_def_pdata.pglamo = glamo;
90609 +       mangle_mem_resources(glamo_mmc_dev->resource,
90610 +                            glamo_mmc_dev->num_resources, glamo->mem);
90611 +       platform_device_register(glamo_mmc_dev);
90612 +
90613 +       /* only request the generic, hostbus and memory controller MMIO */
90614 +       glamo->mem = request_mem_region(glamo->mem->start,
90615 +                                       GLAMO_REGOFS_VIDCAP, "glamo-core");
90616 +       if (!glamo->mem) {
90617 +               dev_err(&pdev->dev, "failed to request memory region\n");
90618 +               goto bail_irq;
90619 +       }
90620 +
90621 +       return 0;
90622 +
90623 +bail_irq:
90624 +       disable_irq(glamo->irq);
90625 +       set_irq_chained_handler(glamo->irq, NULL);
90626 +
90627 +       for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
90628 +               set_irq_flags(irq, 0);
90629 +               set_irq_chip(irq, NULL);
90630 +       }
90631 +
90632 +       iounmap(glamo->base);
90633 +bail_free:
90634 +       platform_set_drvdata(pdev, NULL);
90635 +       glamo_handle = NULL;
90636 +       kfree(glamo);
90637 +
90638 +       return rc;
90639 +}
90640 +
90641 +static int glamo_remove(struct platform_device *pdev)
90642 +{
90643 +       struct glamo_core *glamo = platform_get_drvdata(pdev);
90644 +       int irq;
90645 +
90646 +       disable_irq(glamo->irq);
90647 +       set_irq_chained_handler(glamo->irq, NULL);
90648 +
90649 +       for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
90650 +               set_irq_flags(irq, 0);
90651 +               set_irq_chip(irq, NULL);
90652 +       }
90653 +
90654 +       platform_set_drvdata(pdev, NULL);
90655 +       platform_device_unregister(&glamo_fb_dev);
90656 +       platform_device_unregister(glamo->pdata->mmc_dev);
90657 +       iounmap(glamo->base);
90658 +       release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
90659 +       glamo_handle = NULL;
90660 +       kfree(glamo);
90661 +
90662 +       return 0;
90663 +}
90664 +
90665 +#ifdef CONFIG_PM
90666 +
90667 +static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
90668 +{
90669 +       glamo_handle->suspending = 1;
90670 +       glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
90671 +
90672 +       return 0;
90673 +}
90674 +
90675 +static int glamo_resume(struct platform_device *pdev)
90676 +{
90677 +       glamo_power(glamo_handle, GLAMO_POWER_ON);
90678 +       glamo_handle->suspending = 0;
90679 +
90680 +       return 0;
90681 +}
90682 +
90683 +#else
90684 +#define glamo_suspend NULL
90685 +#define glamo_resume  NULL
90686 +#endif
90687 +
90688 +static struct platform_driver glamo_driver = {
90689 +       .probe          = glamo_probe,
90690 +       .remove         = glamo_remove,
90691 +       .suspend        = glamo_suspend,
90692 +       .resume = glamo_resume,
90693 +       .driver         = {
90694 +               .name   = "glamo3362",
90695 +               .owner  = THIS_MODULE,
90696 +       },
90697 +};
90698 +
90699 +static int __devinit glamo_init(void)
90700 +{
90701 +       return platform_driver_register(&glamo_driver);
90702 +}
90703 +
90704 +static void __exit glamo_cleanup(void)
90705 +{
90706 +       platform_driver_unregister(&glamo_driver);
90707 +}
90708 +
90709 +module_init(glamo_init);
90710 +module_exit(glamo_cleanup);
90711 +
90712 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
90713 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
90714 +MODULE_LICENSE("GPL");
90715 Index: linux-2.6.28/drivers/mfd/glamo/glamo-core.h
90716 ===================================================================
90717 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
90718 +++ linux-2.6.28/drivers/mfd/glamo/glamo-core.h 2009-01-02 00:01:56.000000000 +0100
90719 @@ -0,0 +1,92 @@
90720 +#ifndef __GLAMO_CORE_H
90721 +#define __GLAMO_CORE_H
90722 +
90723 +#include <asm/system.h>
90724 +
90725 +/* for the time being, we put the on-screen framebuffer into the lowest
90726 + * VRAM space.  This should make the code easily compatible with the various
90727 + * 2MB/4MB/8MB variants of the Smedia chips */
90728 +#define GLAMO_OFFSET_VRAM      0x800000
90729 +#define GLAMO_OFFSET_FB        (GLAMO_OFFSET_VRAM)
90730 +
90731 +/* we only allocate the minimum possible size for the framebuffer to make
90732 + * sure we have sufficient memory for other functions of the chip */
90733 +//#define GLAMO_FB_SIZE        (640*480*4)     /* == 0x12c000 */
90734 +#define GLAMO_INTERNAL_RAM_SIZE 0x800000
90735 +#define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
90736 +#define GLAMO_FB_SIZE  (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
90737 +
90738 +struct glamo_core {
90739 +       int irq;
90740 +       int irq_works; /* 0 means PCB does not support Glamo IRQ */
90741 +       struct resource *mem;
90742 +       struct resource *mem_core;
90743 +       void __iomem *base;
90744 +       struct platform_device *pdev;
90745 +       struct glamofb_platform_data *pdata;
90746 +       u_int16_t type;
90747 +       u_int16_t revision;
90748 +       spinlock_t lock;
90749 +       u32 engine_enabled_bitfield;
90750 +       u32 engine_enabled_bitfield_suspend;
90751 +       int suspending;
90752 +};
90753 +
90754 +struct glamo_script {
90755 +       u_int16_t reg;
90756 +       u_int16_t val;
90757 +};
90758 +
90759 +int glamo_run_script(struct glamo_core *glamo,
90760 +                    struct glamo_script *script, int len, int may_sleep);
90761 +
90762 +enum glamo_engine {
90763 +       GLAMO_ENGINE_CAPTURE,
90764 +       GLAMO_ENGINE_ISP,
90765 +       GLAMO_ENGINE_JPEG,
90766 +       GLAMO_ENGINE_MPEG_ENC,
90767 +       GLAMO_ENGINE_MPEG_DEC,
90768 +       GLAMO_ENGINE_LCD,
90769 +       GLAMO_ENGINE_CMDQ,
90770 +       GLAMO_ENGINE_2D,
90771 +       GLAMO_ENGINE_3D,
90772 +       GLAMO_ENGINE_MMC,
90773 +       GLAMO_ENGINE_MICROP0,
90774 +       GLAMO_ENGINE_RISC,
90775 +       GLAMO_ENGINE_MICROP1_MPEG_ENC,
90776 +       GLAMO_ENGINE_MICROP1_MPEG_DEC,
90777 +#if 0
90778 +       GLAMO_ENGINE_H264_DEC,
90779 +       GLAMO_ENGINE_RISC1,
90780 +       GLAMO_ENGINE_SPI,
90781 +#endif
90782 +       __NUM_GLAMO_ENGINES
90783 +};
90784 +
90785 +struct glamo_mci_pdata {
90786 +       struct glamo_core * pglamo;
90787 +       unsigned int    gpio_detect;
90788 +       unsigned int    gpio_wprotect;
90789 +       unsigned long   ocr_avail;
90790 +       int             (*glamo_can_set_mci_power)(void);
90791 +       /* glamo-mci asking if it should use the slow clock to card */
90792 +       int             (*glamo_mci_use_slow)(void);
90793 +       int             (*glamo_irq_is_wired)(void);
90794 +       void            (*mci_suspending)(struct platform_device *dev);
90795 +       int             (*mci_all_dependencies_resumed)(struct platform_device *dev);
90796 +
90797 +};
90798 +
90799 +int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
90800 +int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
90801 +void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
90802 +int glamo_engine_reclock(struct glamo_core *glamo,
90803 +                        enum glamo_engine engine, int ps);
90804 +
90805 +void glamo_engine_clkreg_set(struct glamo_core *glamo,
90806 +                            enum glamo_engine engine,
90807 +                            u_int16_t mask, u_int16_t val);
90808 +
90809 +u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
90810 +                                 enum glamo_engine engine);
90811 +#endif /* __GLAMO_CORE_H */
90812 Index: linux-2.6.28/drivers/mfd/glamo/glamo-fb.c
90813 ===================================================================
90814 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
90815 +++ linux-2.6.28/drivers/mfd/glamo/glamo-fb.c   2009-01-02 00:01:56.000000000 +0100
90816 @@ -0,0 +1,1048 @@
90817 +/* Smedia Glamo 336x/337x driver
90818 + *
90819 + * (C) 2007-2008 by Openmoko, Inc.
90820 + * Author: Harald Welte <laforge@openmoko.org>
90821 + * All rights reserved.
90822 + *
90823 + * This program is free software; you can redistribute it and/or
90824 + * modify it under the terms of the GNU General Public License as
90825 + * published by the Free Software Foundation; either version 2 of
90826 + * the License, or (at your option) any later version.
90827 + *
90828 + * This program is distributed in the hope that it will be useful,
90829 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
90830 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
90831 + * GNU General Public License for more details.
90832 + *
90833 + * You should have received a copy of the GNU General Public License
90834 + * along with this program; if not, write to the Free Software
90835 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
90836 + * MA 02111-1307 USA
90837 + */
90838 +
90839 +#include <linux/module.h>
90840 +#include <linux/kernel.h>
90841 +#include <linux/errno.h>
90842 +#include <linux/string.h>
90843 +#include <linux/mm.h>
90844 +#include <linux/slab.h>
90845 +#include <linux/delay.h>
90846 +#include <linux/fb.h>
90847 +#include <linux/init.h>
90848 +#include <linux/vmalloc.h>
90849 +#include <linux/dma-mapping.h>
90850 +#include <linux/interrupt.h>
90851 +#include <linux/workqueue.h>
90852 +#include <linux/wait.h>
90853 +#include <linux/platform_device.h>
90854 +#include <linux/clk.h>
90855 +#include <linux/spinlock.h>
90856 +
90857 +#include <asm/io.h>
90858 +#include <asm/uaccess.h>
90859 +#include <asm/div64.h>
90860 +
90861 +#ifdef CONFIG_PM
90862 +#include <linux/pm.h>
90863 +#endif
90864 +
90865 +#include <linux/glamofb.h>
90866 +
90867 +#include "glamo-regs.h"
90868 +#include "glamo-core.h"
90869 +
90870 +#ifndef DEBUG
90871 +#define GLAMO_LOG(...)
90872 +#else
90873 +#define GLAMO_LOG(...) \
90874 +do { \
90875 +       printk(KERN_DEBUG "in %s:%s:%d", __FILE__, __func__, __LINE__); \
90876 +       printk(KERN_DEBUG __VA_ARGS__); \
90877 +} while (0);
90878 +#endif
90879 +
90880 +
90881 +#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
90882 +
90883 +struct glamofb_handle {
90884 +       struct fb_info *fb;
90885 +       struct device *dev;
90886 +       struct resource *reg;
90887 +       struct resource *fb_res;
90888 +       char __iomem *base;
90889 +       struct glamofb_platform_data *mach_info;
90890 +       char __iomem *cursor_addr;
90891 +       int cursor_on;
90892 +       u_int32_t pseudo_pal[16];
90893 +       spinlock_t lock_cmd;
90894 +};
90895 +
90896 +/* 'sibling' spi device for lcm init */
90897 +static struct platform_device glamo_spi_dev = {
90898 +       .name           = "glamo-lcm-spi",
90899 +};
90900 +
90901 +
90902 +static int reg_read(struct glamofb_handle *glamo,
90903 +                          u_int16_t reg)
90904 +{
90905 +       return readw(glamo->base + reg);
90906 +}
90907 +
90908 +static void reg_write(struct glamofb_handle *glamo,
90909 +                            u_int16_t reg, u_int16_t val)
90910 +{
90911 +       writew(val, glamo->base + reg);
90912 +}
90913 +
90914 +static struct glamo_script glamo_regs[] = {
90915 +       { GLAMO_REG_LCD_MODE1, 0x0020 },
90916 +       /* no display rotation, no hardware cursor, no dither, no gamma,
90917 +        * no retrace flip, vsync low-active, hsync low active,
90918 +        * no TVCLK, no partial display, hw dest color from fb,
90919 +        * no partial display mode, LCD1, software flip,  */
90920 +       { GLAMO_REG_LCD_MODE2, 0x9020 },
90921 +         /* video flip, no ptr, no ptr, dhclk off,
90922 +          * normal mode,  no cpuif,
90923 +          * res, serial msb first, single fb, no fr ctrl,
90924 +          * cpu if bits all zero, no crc
90925 +          * 0000 0000 0010  0000 */
90926 +       { GLAMO_REG_LCD_MODE3, 0x0b40 },
90927 +         /* src data rgb565, res, 18bit rgb666
90928 +          * 000 01 011 0100 0000 */
90929 +       { GLAMO_REG_LCD_POLARITY, 0x440c },
90930 +         /* DE high active, no cpu/lcd if, cs0 force low, a0 low active,
90931 +          * np cpu if, 9bit serial data, sclk rising edge latch data
90932 +          * 01 00 0 100 0 000 01 0 0 */
90933 +       /* The following values assume 640*480@16bpp */
90934 +       { GLAMO_REG_LCD_A_BASE1, 0x0000 }, /* display A base address 15:0 */
90935 +       { GLAMO_REG_LCD_A_BASE2, 0x0000 }, /* display A base address 22:16 */
90936 +       { GLAMO_REG_LCD_B_BASE1, 0x6000 }, /* display B base address 15:0 */
90937 +       { GLAMO_REG_LCD_B_BASE2, 0x0009 }, /* display B base address 22:16 */
90938 +       { GLAMO_REG_LCD_CURSOR_BASE1, 0xC000 }, /* cursor base address 15:0 */
90939 +       { GLAMO_REG_LCD_CURSOR_BASE2, 0x0012 }, /* cursor base address 22:16 */
90940 +       { GLAMO_REG_LCD_COMMAND2, 0x0000 }, /* display page A */
90941 +};
90942 +
90943 +static int glamofb_run_script(struct glamofb_handle *glamo,
90944 +                               struct glamo_script *script, int len)
90945 +{
90946 +       int i;
90947 +
90948 +       if (glamo->mach_info->glamo->suspending) {
90949 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_run_script while "
90950 +                                                                "suspended\n");
90951 +               return -EBUSY;
90952 +       }
90953 +
90954 +       for (i = 0; i < len; i++) {
90955 +               struct glamo_script *line = &script[i];
90956 +
90957 +               if (line->reg == 0xffff)
90958 +                       return 0;
90959 +               else if (line->reg == 0xfffe)
90960 +                       msleep(line->val);
90961 +               else
90962 +                       reg_write(glamo, script[i].reg, script[i].val);
90963 +       }
90964 +
90965 +       return 0;
90966 +}
90967 +
90968 +static int glamofb_check_var(struct fb_var_screeninfo *var,
90969 +                            struct fb_info *info)
90970 +{
90971 +       struct glamofb_handle *glamo = info->par;
90972 +
90973 +       if (glamo->mach_info->glamo->suspending) {
90974 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_check_var while "
90975 +                                                                "suspended\n");
90976 +               return -EBUSY;
90977 +       }
90978 +
90979 +       if (var->yres > glamo->mach_info->yres.max)
90980 +               var->yres = glamo->mach_info->yres.max;
90981 +       else if (var->yres < glamo->mach_info->yres.min)
90982 +               var->yres = glamo->mach_info->yres.min;
90983 +
90984 +       if (var->xres > glamo->mach_info->xres.max)
90985 +               var->xres = glamo->mach_info->xres.max;
90986 +       else if (var->xres < glamo->mach_info->xres.min)
90987 +               var->xres = glamo->mach_info->xres.min;
90988 +
90989 +       if (var->bits_per_pixel > glamo->mach_info->bpp.max)
90990 +               var->bits_per_pixel = glamo->mach_info->bpp.max;
90991 +       else if (var->bits_per_pixel < glamo->mach_info->bpp.min)
90992 +               var->bits_per_pixel = glamo->mach_info->bpp.min;
90993 +
90994 +       /* FIXME: set rgb positions */
90995 +       switch (var->bits_per_pixel) {
90996 +       case 16:
90997 +               switch (reg_read(glamo, GLAMO_REG_LCD_MODE3) & 0xc000) {
90998 +               case GLAMO_LCD_SRC_RGB565:
90999 +                       var->red.offset         = 11;
91000 +                       var->green.offset       = 5;
91001 +                       var->blue.offset        = 0;
91002 +                       var->red.length         = 5;
91003 +                       var->green.length       = 6;
91004 +                       var->blue.length        = 5;
91005 +                       var->transp.length      = 0;
91006 +                       break;
91007 +               case GLAMO_LCD_SRC_ARGB1555:
91008 +                       var->transp.offset      = 15;
91009 +                       var->red.offset         = 10;
91010 +                       var->green.offset       = 5;
91011 +                       var->blue.offset        = 0;
91012 +                       var->transp.length      = 1;
91013 +                       var->red.length         = 5;
91014 +                       var->green.length       = 5;
91015 +                       var->blue.length        = 5;
91016 +                       break;
91017 +               case GLAMO_LCD_SRC_ARGB4444:
91018 +                       var->transp.offset      = 12;
91019 +                       var->red.offset         = 8;
91020 +                       var->green.offset       = 4;
91021 +                       var->blue.offset        = 0;
91022 +                       var->transp.length      = 4;
91023 +                       var->red.length         = 4;
91024 +                       var->green.length       = 4;
91025 +                       var->blue.length        = 4;
91026 +                       break;
91027 +               }
91028 +               break;
91029 +       case 24:
91030 +       case 32:
91031 +       default:
91032 +               /* The Smedia Glamo doesn't support anything but 16bit color */
91033 +               printk(KERN_ERR
91034 +                      "Smedia driver does not [yet?] support 24/32bpp\n");
91035 +               return -EINVAL;
91036 +       }
91037 +
91038 +       return 0;
91039 +}
91040 +
91041 +static void reg_set_bit_mask(struct glamofb_handle *glamo,
91042 +                            u_int16_t reg, u_int16_t mask,
91043 +                            u_int16_t val)
91044 +{
91045 +       u_int16_t tmp;
91046 +
91047 +       val &= mask;
91048 +
91049 +       tmp = reg_read(glamo, reg);
91050 +       tmp &= ~mask;
91051 +       tmp |= val;
91052 +       reg_write(glamo, reg, tmp);
91053 +}
91054 +
91055 +#define GLAMO_LCD_WIDTH_MASK 0x03FF
91056 +#define GLAMO_LCD_HEIGHT_MASK 0x03FF
91057 +#define GLAMO_LCD_PITCH_MASK 0x07FE
91058 +#define GLAMO_LCD_HV_TOTAL_MASK 0x03FF
91059 +#define GLAMO_LCD_HV_RETR_START_MASK 0x03FF
91060 +#define GLAMO_LCD_HV_RETR_END_MASK 0x03FF
91061 +#define GLAMO_LCD_HV_RETR_DISP_START_MASK 0x03FF
91062 +#define GLAMO_LCD_HV_RETR_DISP_END_MASK 0x03FF
91063 +
91064 +enum orientation {
91065 +    ORIENTATION_PORTRAIT,
91066 +    ORIENTATION_LANDSCAPE
91067 +};
91068 +
91069 +
91070 +/* the caller has to enxure lock_cmd is held and we are in cmd mode */
91071 +static void __rotate_lcd(struct glamofb_handle *glamo, __u32 rotation)
91072 +{
91073 +       int glamo_rot;
91074 +
91075 +       if (glamo->mach_info->glamo->suspending) {
91076 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING rotate_lcd while "
91077 +                                                                "suspended\n");
91078 +               return;
91079 +       }
91080 +
91081 +       switch (rotation) {
91082 +               case FB_ROTATE_UR:
91083 +                       glamo_rot = GLAMO_LCD_ROT_MODE_0;
91084 +                       break;
91085 +               case FB_ROTATE_CW:
91086 +                       glamo_rot = GLAMO_LCD_ROT_MODE_90;
91087 +                       break;
91088 +               case FB_ROTATE_UD:
91089 +                       glamo_rot = GLAMO_LCD_ROT_MODE_180;
91090 +                       break;
91091 +               case FB_ROTATE_CCW:
91092 +                       glamo_rot = GLAMO_LCD_ROT_MODE_270;
91093 +                       break;
91094 +               default:
91095 +                       glamo_rot = GLAMO_LCD_ROT_MODE_0;
91096 +                       break;
91097 +       }
91098 +
91099 +       reg_set_bit_mask(glamo,
91100 +                        GLAMO_REG_LCD_WIDTH,
91101 +                        GLAMO_LCD_ROT_MODE_MASK,
91102 +                        glamo_rot);
91103 +       reg_set_bit_mask(glamo,
91104 +                        GLAMO_REG_LCD_MODE1,
91105 +                        GLAMO_LCD_MODE1_ROTATE_EN,
91106 +                        (glamo_rot != GLAMO_LCD_ROT_MODE_0)?
91107 +                                GLAMO_LCD_MODE1_ROTATE_EN : 0);
91108 +}
91109 +
91110 +static enum orientation get_orientation(struct fb_var_screeninfo *var)
91111 +{
91112 +       if (var->xres <= var->yres)
91113 +               return ORIENTATION_PORTRAIT;
91114 +
91115 +       return ORIENTATION_LANDSCAPE;
91116 +}
91117 +
91118 +static int will_orientation_change(struct fb_var_screeninfo *var)
91119 +{
91120 +       enum orientation orient = get_orientation(var);
91121 +
91122 +       switch (orient) {
91123 +               case ORIENTATION_LANDSCAPE:
91124 +                       if (var->rotate == FB_ROTATE_UR ||
91125 +                           var->rotate == FB_ROTATE_UD)
91126 +                               return 1;
91127 +                       break;
91128 +               case ORIENTATION_PORTRAIT:
91129 +                       if (var->rotate == FB_ROTATE_CW ||
91130 +                           var->rotate == FB_ROTATE_CCW)
91131 +                               return 1;
91132 +                       break;
91133 +       }
91134 +       return 0;
91135 +}
91136 +
91137 +static void glamofb_update_lcd_controller(struct glamofb_handle *glamo,
91138 +                                         struct fb_var_screeninfo *var)
91139 +{
91140 +       int sync, bp, disp, fp, total, xres, yres, pitch, orientation_changing;
91141 +       unsigned long flags;
91142 +
91143 +       if (!glamo || !var)
91144 +               return;
91145 +
91146 +       if (glamo->mach_info->glamo->suspending) {
91147 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_update_lcd_controller while "
91148 +                                                                "suspended\n");
91149 +               return;
91150 +       }
91151 +
91152 +       dev_dbg(&glamo->mach_info->glamo->pdev->dev,
91153 +                         "glamofb_update_lcd_controller spin_lock_irqsave\n");
91154 +       spin_lock_irqsave(&glamo->lock_cmd, flags);
91155 +
91156 +       if (glamofb_cmd_mode(glamo, 1))
91157 +               goto out_unlock;
91158 +
91159 +       if (var->pixclock)
91160 +               glamo_engine_reclock(glamo->mach_info->glamo,
91161 +                                    GLAMO_ENGINE_LCD,
91162 +                                    var->pixclock);
91163 +
91164 +       xres = var->xres;
91165 +       yres = var->yres;
91166 +
91167 +       /* figure out if orientation is going to change */
91168 +       orientation_changing = will_orientation_change(var);
91169 +
91170 +       /* adjust the pitch according to new orientation to come */
91171 +
91172 +       if (orientation_changing) {
91173 +               pitch = var->yres * var->bits_per_pixel / 8;
91174 +        } else {
91175 +               pitch = var->xres * var->bits_per_pixel / 8;
91176 +        }
91177 +
91178 +       /*
91179 +        * set the desired LCD geometry
91180 +        */
91181 +       reg_set_bit_mask(glamo,
91182 +                        GLAMO_REG_LCD_WIDTH,
91183 +                        GLAMO_LCD_WIDTH_MASK,
91184 +                        xres);
91185 +       reg_set_bit_mask(glamo,
91186 +                        GLAMO_REG_LCD_HEIGHT,
91187 +                        GLAMO_LCD_HEIGHT_MASK,
91188 +                        yres);
91189 +       reg_set_bit_mask(glamo,
91190 +                        GLAMO_REG_LCD_PITCH,
91191 +                        GLAMO_LCD_PITCH_MASK,
91192 +                        pitch);
91193 +
91194 +       /* honour the rotation request */
91195 +       __rotate_lcd(glamo, var->rotate);
91196 +
91197 +       /* update the reported geometry of the framebuffer. */
91198 +       if (orientation_changing) {
91199 +               var->xres_virtual = var->xres = yres;
91200 +               var->xres_virtual *= 2;
91201 +               var->yres_virtual = var->yres = xres;
91202 +       } else {
91203 +               var->xres_virtual = var->xres = xres;
91204 +               var->yres_virtual = var->yres = yres;
91205 +               var->yres_virtual *= 2;
91206 +       }
91207 +
91208 +       /* update scannout timings */
91209 +       sync = 0;
91210 +       bp = sync + var->hsync_len;
91211 +       disp = bp + var->left_margin;
91212 +       fp = disp + xres;
91213 +       total = fp + var->right_margin;
91214 +
91215 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_TOTAL,
91216 +                        GLAMO_LCD_HV_TOTAL_MASK, total);
91217 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_RETR_START,
91218 +                        GLAMO_LCD_HV_RETR_START_MASK, sync);
91219 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_RETR_END,
91220 +                        GLAMO_LCD_HV_RETR_END_MASK, bp);
91221 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_DISP_START,
91222 +                         GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
91223 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_DISP_END,
91224 +                        GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
91225 +
91226 +       sync = 0;
91227 +       bp = sync + var->vsync_len;
91228 +       disp = bp + var->upper_margin;
91229 +       fp = disp + yres;
91230 +       total = fp + var->lower_margin;
91231 +
91232 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_TOTAL,
91233 +                        GLAMO_LCD_HV_TOTAL_MASK, total);
91234 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_RETR_START,
91235 +                         GLAMO_LCD_HV_RETR_START_MASK, sync);
91236 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_RETR_END,
91237 +                        GLAMO_LCD_HV_RETR_END_MASK, bp);
91238 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_DISP_START,
91239 +                        GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
91240 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_DISP_END,
91241 +                        GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
91242 +
91243 +       glamofb_cmd_mode(glamo, 0);
91244 +
91245 +out_unlock:
91246 +       dev_dbg(&glamo->mach_info->glamo->pdev->dev,
91247 +                     "glamofb_update_lcd_controller spin_unlock_irqrestore\n");
91248 +       spin_unlock_irqrestore(&glamo->lock_cmd, flags);
91249 +}
91250 +
91251 +static int glamofb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
91252 +{
91253 +       struct glamofb_handle *glamo = info->par;
91254 +       u_int16_t page = var->yoffset / glamo->mach_info->yres.defval;
91255 +       reg_write(glamo, GLAMO_REG_LCD_COMMAND2, page);
91256 +
91257 +       return 0;
91258 +}
91259 +
91260 +static int glamofb_set_par(struct fb_info *info)
91261 +{
91262 +       struct glamofb_handle *glamo = info->par;
91263 +       struct fb_var_screeninfo *var = &info->var;
91264 +
91265 +       if (glamo->mach_info->glamo->suspending) {
91266 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_set_par while "
91267 +                                                                "suspended\n");
91268 +               return -EBUSY;
91269 +       }
91270 +
91271 +       switch (var->bits_per_pixel) {
91272 +       case 16:
91273 +               info->fix.visual = FB_VISUAL_TRUECOLOR;
91274 +               break;
91275 +       default:
91276 +               printk("Smedia driver doesn't support != 16bpp\n");
91277 +               return -EINVAL;
91278 +       }
91279 +
91280 +       info->fix.line_length = (var->xres * var->bits_per_pixel) / 8;
91281 +
91282 +       glamofb_update_lcd_controller(glamo, var);
91283 +
91284 +       return 0;
91285 +}
91286 +
91287 +
91288 +static void notify_blank(struct fb_info *info, int blank_mode)
91289 +{
91290 +       struct fb_event event;
91291 +
91292 +       event.info = info;
91293 +       event.data = &blank_mode;
91294 +       fb_notifier_call_chain(FB_EVENT_CONBLANK, &event);
91295 +}
91296 +
91297 +
91298 +static int glamofb_blank(int blank_mode, struct fb_info *info)
91299 +{
91300 +       struct glamofb_handle *gfb = info->par;
91301 +       struct glamo_core *gcore = gfb->mach_info->glamo;
91302 +
91303 +       dev_dbg(gfb->dev, "glamofb_blank(%u)\n", blank_mode);
91304 +
91305 +       switch (blank_mode) {
91306 +       case FB_BLANK_VSYNC_SUSPEND:
91307 +       case FB_BLANK_HSYNC_SUSPEND:
91308 +               /* FIXME: add pdata hook/flag to indicate whether
91309 +                * we should already switch off pixel clock here */
91310 +               break;
91311 +       case FB_BLANK_POWERDOWN:
91312 +               /* disable the pixel clock */
91313 +               glamo_engine_clkreg_set(gcore, GLAMO_ENGINE_LCD,
91314 +                                       GLAMO_CLOCK_LCD_EN_DCLK, 0);
91315 +               break;
91316 +       case FB_BLANK_UNBLANK:
91317 +       case FB_BLANK_NORMAL:
91318 +               /* enable the pixel clock */
91319 +               glamo_engine_clkreg_set(gcore, GLAMO_ENGINE_LCD,
91320 +                                       GLAMO_CLOCK_LCD_EN_DCLK,
91321 +                                       GLAMO_CLOCK_LCD_EN_DCLK);
91322 +               notify_blank(info, blank_mode);
91323 +               break;
91324 +       }
91325 +
91326 +       /* FIXME: once we have proper clock management in glamo-core,
91327 +        * we can determine if other units need MCLK1 or the PLL, and
91328 +        * disable it if not used. */
91329 +       return 0;
91330 +}
91331 +
91332 +static inline unsigned int chan_to_field(unsigned int chan,
91333 +                                        struct fb_bitfield *bf)
91334 +{
91335 +       chan &= 0xffff;
91336 +       chan >>= 16 - bf->length;
91337 +       return chan << bf->offset;
91338 +}
91339 +
91340 +static int glamofb_setcolreg(unsigned regno,
91341 +                            unsigned red, unsigned green, unsigned blue,
91342 +                            unsigned transp, struct fb_info *info)
91343 +{
91344 +       struct glamofb_handle *glamo = info->par;
91345 +       unsigned int val;
91346 +
91347 +       if (glamo->mach_info->glamo->suspending) {
91348 +               dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_set_par while "
91349 +                                                                "suspended\n");
91350 +               return -EBUSY;
91351 +       }
91352 +
91353 +       switch (glamo->fb->fix.visual) {
91354 +       case FB_VISUAL_TRUECOLOR:
91355 +       case FB_VISUAL_DIRECTCOLOR:
91356 +               /* true-colour, use pseuo-palette */
91357 +
91358 +               if (regno < 16) {
91359 +                       u32 *pal = glamo->fb->pseudo_palette;
91360 +
91361 +                       val  = chan_to_field(red, &glamo->fb->var.red);
91362 +                       val |= chan_to_field(green, &glamo->fb->var.green);
91363 +                       val |= chan_to_field(blue, &glamo->fb->var.blue);
91364 +
91365 +                       pal[regno] = val;
91366 +               };
91367 +               break;
91368 +       default:
91369 +               return 1; /* unknown type */
91370 +       }
91371 +
91372 +       return 0;
91373 +}
91374 +
91375 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
91376 +static inline void glamofb_vsync_wait(struct glamofb_handle *glamo,
91377 +               int line, int size, int range)
91378 +{
91379 +       int count[2];
91380 +
91381 +       do {
91382 +               count[0] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
91383 +               count[1] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
91384 +       } while (count[0] != count[1] ||
91385 +                       (line < count[0] + range &&
91386 +                        size > count[0] - range) ||
91387 +                       count[0] < range * 2);
91388 +}
91389 +
91390 +/*
91391 + * Enable/disable the hardware cursor mode altogether
91392 + * (for blinking and such, use glamofb_cursor()).
91393 + */
91394 +static void glamofb_cursor_onoff(struct glamofb_handle *glamo, int on)
91395 +{
91396 +       int y, size;
91397 +
91398 +       if (glamo->cursor_on) {
91399 +               y = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_POS);
91400 +               size = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE);
91401 +
91402 +               glamofb_vsync_wait(glamo, y, size, 30);
91403 +       }
91404 +
91405 +       reg_set_bit_mask(glamo, GLAMO_REG_LCD_MODE1,
91406 +                       GLAMO_LCD_MODE1_CURSOR_EN,
91407 +                       on ? GLAMO_LCD_MODE1_CURSOR_EN : 0);
91408 +       glamo->cursor_on = on;
91409 +
91410 +       /* Hide the cursor by default */
91411 +       reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE, 0);
91412 +}
91413 +
91414 +static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
91415 +{
91416 +       struct glamofb_handle *glamo = info->par;
91417 +       unsigned long flags;
91418 +
91419 +       spin_lock_irqsave(&glamo->lock_cmd, flags);
91420 +
91421 +       reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
91422 +                       cursor->enable ? cursor->image.width : 0);
91423 +
91424 +       if (cursor->set & FB_CUR_SETPOS) {
91425 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_POS,
91426 +                         cursor->image.dx);
91427 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_POS,
91428 +                         cursor->image.dy);
91429 +       }
91430 +
91431 +       if (cursor->set & FB_CUR_SETCMAP) {
91432 +               uint16_t fg = glamo->pseudo_pal[cursor->image.fg_color];
91433 +               uint16_t bg = glamo->pseudo_pal[cursor->image.bg_color];
91434 +
91435 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_FG_COLOR, fg);
91436 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_BG_COLOR, bg);
91437 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_DST_COLOR, fg);
91438 +       }
91439 +
91440 +       if (cursor->set & FB_CUR_SETHOT)
91441 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_PRESET,
91442 +                               (cursor->hot.x << 8) | cursor->hot.y);
91443 +
91444 +       if ((cursor->set & FB_CUR_SETSIZE) ||
91445 +           (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE))) {
91446 +               int x, y, pitch, op;
91447 +               const uint8_t *pcol = cursor->image.data;
91448 +               const uint8_t *pmsk = cursor->mask;
91449 +               uint8_t __iomem *dst = glamo->cursor_addr;
91450 +               uint8_t dcol = 0;
91451 +               uint8_t dmsk = 0;
91452 +               uint8_t byte = 0;
91453 +
91454 +               if (cursor->image.depth > 1) {
91455 +                       spin_unlock_irqrestore(&glamo->lock_cmd, flags);
91456 +                       return -EINVAL;
91457 +               }
91458 +
91459 +               pitch = ((cursor->image.width + 7) >> 2) & ~1;
91460 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_PITCH,
91461 +                       pitch);
91462 +               reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE,
91463 +                       cursor->image.height);
91464 +
91465 +               for (y = 0; y < cursor->image.height; y++) {
91466 +                       byte = 0;
91467 +                       for (x = 0; x < cursor->image.width; x++) {
91468 +                               if ((x % 8) == 0) {
91469 +                                       dcol = *pcol++;
91470 +                                       dmsk = *pmsk++;
91471 +                               } else {
91472 +                                       dcol >>= 1;
91473 +                                       dmsk >>= 1;
91474 +                               }
91475 +
91476 +                               if (cursor->rop == ROP_COPY)
91477 +                                       op = (dmsk & 1) ?
91478 +                                               (dcol & 1) ? 1 : 3 : 0;
91479 +                               else
91480 +                                       op = ((dmsk & 1) << 1) |
91481 +                                               ((dcol & 1) << 0);
91482 +                               byte |= op << ((x & 3) << 1);
91483 +
91484 +                               if (x % 4 == 3) {
91485 +                                       writeb(byte, dst + x / 4);
91486 +                                       byte = 0;
91487 +                               }
91488 +                       }
91489 +                       if (x % 4) {
91490 +                               writeb(byte, dst + x / 4);
91491 +                               byte = 0;
91492 +                       }
91493 +
91494 +                       dst += pitch;
91495 +               }
91496 +       }
91497 +
91498 +       spin_unlock_irqrestore(&glamo->lock_cmd, flags);
91499 +
91500 +       return 0;
91501 +}
91502 +#endif
91503 +
91504 +static inline int glamofb_cmdq_empty(struct glamofb_handle *gfb)
91505 +{
91506 +       /* DGCMdQempty -- 1 == command queue is empty */
91507 +       return reg_read(gfb, GLAMO_REG_LCD_STATUS1) & (1 << 15);
91508 +}
91509 +
91510 +/* call holding gfb->lock_cmd  when locking, until you unlock */
91511 +int glamofb_cmd_mode(struct glamofb_handle *gfb, int on)
91512 +{
91513 +       int timeout = 2000000;
91514 +
91515 +       if (gfb->mach_info->glamo->suspending) {
91516 +               dev_err(&gfb->mach_info->glamo->pdev->dev, "IGNORING glamofb_cmd_mode while "
91517 +                                                                "suspended\n");
91518 +               return -EBUSY;
91519 +       }
91520 +
91521 +       dev_dbg(gfb->dev, "glamofb_cmd_mode(gfb=%p, on=%d)\n", gfb, on);
91522 +       if (on) {
91523 +               dev_dbg(gfb->dev, "%s: waiting for cmdq empty: ",
91524 +                       __FUNCTION__);
91525 +               while ((!glamofb_cmdq_empty(gfb)) && (timeout--))
91526 +                       /* yield() */;
91527 +               if (timeout < 0) {
91528 +                       printk(KERN_ERR"*************"
91529 +                                      "glamofb cmd_queue never got empty"
91530 +                                      "*************\n");
91531 +                       return -EIO;
91532 +               }
91533 +               dev_dbg(gfb->dev, "empty!\n");
91534 +
91535 +               /* display the entire frame then switch to command */
91536 +               reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
91537 +                         GLAMO_LCD_CMD_TYPE_DISP |
91538 +                         GLAMO_LCD_CMD_DATA_FIRE_VSYNC);
91539 +
91540 +               /* wait until lcd idle */
91541 +               dev_dbg(gfb->dev, "waiting for lcd idle: ");
91542 +               timeout = 2000000;
91543 +               while ((!reg_read(gfb, GLAMO_REG_LCD_STATUS2) & (1 << 12)) &&
91544 +                     (timeout--))
91545 +                       /* yield() */;
91546 +               if (timeout < 0) {
91547 +                       printk(KERN_ERR"*************"
91548 +                                      "glamofb lcd never idle"
91549 +                                      "*************\n");
91550 +                       return -EIO;
91551 +               }
91552 +
91553 +               mdelay(100);
91554 +
91555 +               dev_dbg(gfb->dev, "cmd mode entered\n");
91556 +
91557 +       } else {
91558 +               /* RGB interface needs vsync/hsync */
91559 +               if (reg_read(gfb, GLAMO_REG_LCD_MODE3) & GLAMO_LCD_MODE3_RGB)
91560 +                       reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
91561 +                                 GLAMO_LCD_CMD_TYPE_DISP |
91562 +                                 GLAMO_LCD_CMD_DATA_DISP_SYNC);
91563 +
91564 +               reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
91565 +                         GLAMO_LCD_CMD_TYPE_DISP |
91566 +                         GLAMO_LCD_CMD_DATA_DISP_FIRE);
91567 +       }
91568 +
91569 +       return 0;
91570 +}
91571 +EXPORT_SYMBOL_GPL(glamofb_cmd_mode);
91572 +
91573 +
91574 +int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val)
91575 +{
91576 +       int timeout = 200000;
91577 +
91578 +       if (gfb->mach_info->glamo->suspending) {
91579 +               dev_err(&gfb->mach_info->glamo->pdev->dev, "IGNORING glamofb_cmd_write while "
91580 +                                                                "suspended\n");
91581 +               return -EBUSY;
91582 +       }
91583 +
91584 +       dev_dbg(gfb->dev, "%s: waiting for cmdq empty\n", __FUNCTION__);
91585 +       while ((!glamofb_cmdq_empty(gfb)) && (timeout--))
91586 +               yield();
91587 +       if (timeout < 0) {
91588 +               printk(KERN_ERR"*************"
91589 +                               "glamofb cmd_queue never got empty"
91590 +                               "*************\n");
91591 +               return 1;
91592 +       }
91593 +       dev_dbg(gfb->dev, "idle, writing 0x%04x\n", val);
91594 +
91595 +       reg_write(gfb, GLAMO_REG_LCD_COMMAND1, val);
91596 +
91597 +       return 0;
91598 +}
91599 +EXPORT_SYMBOL_GPL(glamofb_cmd_write);
91600 +
91601 +static struct fb_ops glamofb_ops = {
91602 +       .owner          = THIS_MODULE,
91603 +       .fb_check_var   = glamofb_check_var,
91604 +       .fb_pan_display = glamofb_pan_display,
91605 +       .fb_set_par     = glamofb_set_par,
91606 +       .fb_blank       = glamofb_blank,
91607 +       .fb_setcolreg   = glamofb_setcolreg,
91608 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
91609 +       .fb_cursor      = glamofb_cursor,
91610 +#endif
91611 +       .fb_fillrect    = cfb_fillrect,
91612 +       .fb_copyarea    = cfb_copyarea,
91613 +       .fb_imageblit   = cfb_imageblit,
91614 +};
91615 +
91616 +static int glamofb_init_regs(struct glamofb_handle *glamo)
91617 +{
91618 +       struct fb_info *info = glamo->fb;
91619 +
91620 +       glamofb_check_var(&info->var, info);
91621 +       glamofb_run_script(glamo, glamo_regs, ARRAY_SIZE(glamo_regs));
91622 +       glamofb_set_par(info);
91623 +
91624 +       return 0;
91625 +}
91626 +
91627 +static int __init glamofb_probe(struct platform_device *pdev)
91628 +{
91629 +       int rc = -EIO;
91630 +       struct fb_info *fbinfo;
91631 +       struct glamofb_handle *glamofb;
91632 +       struct glamofb_platform_data *mach_info = pdev->dev.platform_data;
91633 +
91634 +       printk(KERN_INFO "SMEDIA Glamo frame buffer driver (C) 2007 "
91635 +               "Openmoko, Inc.\n");
91636 +
91637 +       fbinfo = framebuffer_alloc(sizeof(struct glamofb_handle), &pdev->dev);
91638 +       if (!fbinfo)
91639 +               return -ENOMEM;
91640 +
91641 +       glamofb = fbinfo->par;
91642 +       glamofb->fb = fbinfo;
91643 +       glamofb->dev = &pdev->dev;
91644 +
91645 +       strcpy(fbinfo->fix.id, "SMedia Glamo");
91646 +
91647 +       glamofb->reg = platform_get_resource_byname(pdev, IORESOURCE_MEM,
91648 +                                                   "glamo-fb-regs");
91649 +       if (!glamofb->reg) {
91650 +               dev_err(&pdev->dev, "platform device with no registers?\n");
91651 +               rc = -ENOENT;
91652 +               goto out_free;
91653 +       }
91654 +
91655 +       glamofb->fb_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
91656 +                                                       "glamo-fb-mem");
91657 +       if (!glamofb->fb_res) {
91658 +               dev_err(&pdev->dev, "platform device with no memory ?\n");
91659 +               rc = -ENOENT;
91660 +               goto out_free;
91661 +       }
91662 +
91663 +       glamofb->reg = request_mem_region(glamofb->reg->start,
91664 +                                         RESSIZE(glamofb->reg), pdev->name);
91665 +       if (!glamofb->reg) {
91666 +               dev_err(&pdev->dev, "failed to request mmio region\n");
91667 +               goto out_free;
91668 +       }
91669 +
91670 +       glamofb->fb_res = request_mem_region(glamofb->fb_res->start,
91671 +                                            mach_info->fb_mem_size,
91672 +                                            pdev->name);
91673 +       if (!glamofb->fb_res) {
91674 +               dev_err(&pdev->dev, "failed to request vram region\n");
91675 +               goto out_release_reg;
91676 +       }
91677 +
91678 +       /* we want to remap only the registers required for this core
91679 +        * driver. */
91680 +       glamofb->base = ioremap(glamofb->reg->start, RESSIZE(glamofb->reg));
91681 +       if (!glamofb->base) {
91682 +               dev_err(&pdev->dev, "failed to ioremap() mmio memory\n");
91683 +               goto out_release_fb;
91684 +       }
91685 +       fbinfo->fix.smem_start = (unsigned long) glamofb->fb_res->start;
91686 +       fbinfo->fix.smem_len = mach_info->fb_mem_size;
91687 +
91688 +       fbinfo->screen_base = ioremap(glamofb->fb_res->start,
91689 +                                      RESSIZE(glamofb->fb_res));
91690 +       if (!fbinfo->screen_base) {
91691 +               dev_err(&pdev->dev, "failed to ioremap() vram memory\n");
91692 +               goto out_release_fb;
91693 +       }
91694 +       glamofb->cursor_addr = fbinfo->screen_base + 0x12C000;
91695 +
91696 +       platform_set_drvdata(pdev, glamofb);
91697 +
91698 +       glamofb->mach_info = pdev->dev.platform_data;
91699 +
91700 +       fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
91701 +       fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
91702 +       fbinfo->fix.type_aux = 0;
91703 +       fbinfo->fix.xpanstep = 0;
91704 +       fbinfo->fix.ypanstep = mach_info->yres.defval;
91705 +       fbinfo->fix.ywrapstep = 0;
91706 +       fbinfo->fix.accel = FB_ACCEL_GLAMO;
91707 +
91708 +       fbinfo->var.nonstd = 0;
91709 +       fbinfo->var.activate = FB_ACTIVATE_NOW;
91710 +       fbinfo->var.height = mach_info->height;
91711 +       fbinfo->var.width = mach_info->width;
91712 +       fbinfo->var.accel_flags = 0;    /* FIXME */
91713 +       fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
91714 +
91715 +       fbinfo->fbops = &glamofb_ops;
91716 +       fbinfo->flags = FBINFO_FLAG_DEFAULT;
91717 +       fbinfo->pseudo_palette = &glamofb->pseudo_pal;
91718 +
91719 +       fbinfo->var.xres = mach_info->xres.defval;
91720 +       fbinfo->var.xres_virtual = mach_info->xres.defval;
91721 +       fbinfo->var.yres = mach_info->yres.defval;
91722 +       fbinfo->var.yres_virtual = mach_info->yres.defval * 2;
91723 +       fbinfo->var.bits_per_pixel = mach_info->bpp.defval;
91724 +
91725 +       fbinfo->var.pixclock = mach_info->pixclock;
91726 +       fbinfo->var.left_margin = mach_info->left_margin;
91727 +       fbinfo->var.right_margin = mach_info->right_margin;
91728 +       fbinfo->var.upper_margin = mach_info->upper_margin;
91729 +       fbinfo->var.lower_margin = mach_info->lower_margin;
91730 +       fbinfo->var.hsync_len = mach_info->hsync_len;
91731 +       fbinfo->var.vsync_len = mach_info->vsync_len;
91732 +
91733 +       memset(fbinfo->screen_base, 0,
91734 +                       mach_info->xres.max *
91735 +                       mach_info->yres.max *
91736 +                       mach_info->bpp.max / 8);
91737 +
91738 +       glamo_engine_enable(mach_info->glamo, GLAMO_ENGINE_LCD);
91739 +       glamo_engine_reset(mach_info->glamo, GLAMO_ENGINE_LCD);
91740 +
91741 +       dev_info(&pdev->dev, "spin_lock_init\n");
91742 +       spin_lock_init(&glamofb->lock_cmd);
91743 +       glamofb_init_regs(glamofb);
91744 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
91745 +       glamofb_cursor_onoff(glamofb, 1);
91746 +#endif
91747 +
91748 +       rc = register_framebuffer(fbinfo);
91749 +       if (rc < 0) {
91750 +               dev_err(&pdev->dev, "failed to register framebuffer\n");
91751 +               goto out_unmap_fb;
91752 +       }
91753 +
91754 +       if (mach_info->spi_info) {
91755 +               /* register the sibling spi device */
91756 +               mach_info->spi_info->glamofb_handle = glamofb;
91757 +               glamo_spi_dev.dev.parent = &pdev->dev;
91758 +               glamo_spi_dev.dev.platform_data = mach_info->spi_info;
91759 +               platform_device_register(&glamo_spi_dev);
91760 +       }
91761 +
91762 +       printk(KERN_INFO "fb%d: %s frame buffer device\n",
91763 +               fbinfo->node, fbinfo->fix.id);
91764 +
91765 +       return 0;
91766 +
91767 +out_unmap_fb:
91768 +       iounmap(fbinfo->screen_base);
91769 +       iounmap(glamofb->base);
91770 +out_release_fb:
91771 +       release_mem_region(glamofb->fb_res->start, RESSIZE(glamofb->fb_res));
91772 +out_release_reg:
91773 +       release_mem_region(glamofb->reg->start, RESSIZE(glamofb->reg));
91774 +out_free:
91775 +       framebuffer_release(fbinfo);
91776 +       return rc;
91777 +}
91778 +
91779 +static int glamofb_remove(struct platform_device *pdev)
91780 +{
91781 +       struct glamofb_handle *glamofb = platform_get_drvdata(pdev);
91782 +
91783 +       platform_set_drvdata(pdev, NULL);
91784 +       iounmap(glamofb->base);
91785 +       release_mem_region(glamofb->reg->start, RESSIZE(glamofb->reg));
91786 +       kfree(glamofb);
91787 +
91788 +       return 0;
91789 +}
91790 +
91791 +#ifdef CONFIG_PM
91792 +
91793 +static int glamofb_suspend(struct platform_device *pdev, pm_message_t state)
91794 +{
91795 +       struct glamofb_handle *gfb = platform_get_drvdata(pdev);
91796 +
91797 +       /* we need to stop anything touching our framebuffer */
91798 +//     fb_blank(gfb->fb, FB_BLANK_NORMAL);
91799 +       fb_set_suspend(gfb->fb, 1);
91800 +
91801 +       /* seriously -- nobody is allowed to touch glamo memory when we
91802 +        * are suspended or we lock on nWAIT
91803 +        */
91804 +//     iounmap(gfb->fb->screen_base);
91805 +
91806 +       return 0;
91807 +}
91808 +
91809 +static int glamofb_resume(struct platform_device *pdev)
91810 +{
91811 +       struct glamofb_handle *glamofb = platform_get_drvdata(pdev);
91812 +       struct glamofb_platform_data *mach_info = pdev->dev.platform_data;
91813 +
91814 +       /* OK let's allow framebuffer ops again */
91815 +//     gfb->fb->screen_base = ioremap(gfb->fb_res->start,
91816 +//                                    RESSIZE(gfb->fb_res));
91817 +       glamo_engine_enable(mach_info->glamo, GLAMO_ENGINE_LCD);
91818 +       glamo_engine_reset(mach_info->glamo, GLAMO_ENGINE_LCD);
91819 +
91820 +       printk(KERN_ERR"spin_lock_init\n");
91821 +       spin_lock_init(&glamofb->lock_cmd);
91822 +       glamofb_init_regs(glamofb);
91823 +#ifdef CONFIG_MFD_GLAMO_HWACCEL
91824 +       glamofb_cursor_onoff(glamofb, 1);
91825 +#endif
91826 +
91827 +
91828 +       fb_set_suspend(glamofb->fb, 0);
91829 +//     fb_blank(gfb->fb, FB_BLANK_UNBLANK);
91830 +
91831 +       return 0;
91832 +}
91833 +#else
91834 +#define glamo_suspend NULL
91835 +#define glamo_resume  NULL
91836 +#endif
91837 +
91838 +static struct platform_driver glamofb_driver = {
91839 +       .probe          = glamofb_probe,
91840 +       .remove         = glamofb_remove,
91841 +       .suspend        = glamofb_suspend,
91842 +       .resume = glamofb_resume,
91843 +       .driver         = {
91844 +               .name   = "glamo-fb",
91845 +               .owner  = THIS_MODULE,
91846 +       },
91847 +};
91848 +
91849 +static int __devinit glamofb_init(void)
91850 +{
91851 +       return platform_driver_register(&glamofb_driver);
91852 +}
91853 +
91854 +static void __exit glamofb_cleanup(void)
91855 +{
91856 +       platform_driver_unregister(&glamofb_driver);
91857 +}
91858 +
91859 +module_init(glamofb_init);
91860 +module_exit(glamofb_cleanup);
91861 +
91862 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
91863 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x framebuffer driver");
91864 +MODULE_LICENSE("GPL");
91865 Index: linux-2.6.28/drivers/mfd/glamo/glamo-gpio.c
91866 ===================================================================
91867 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
91868 +++ linux-2.6.28/drivers/mfd/glamo/glamo-gpio.c 2009-01-02 00:01:56.000000000 +0100
91869 @@ -0,0 +1,62 @@
91870 +
91871 +#include <linux/kernel.h>
91872 +#include <linux/module.h>
91873 +#include <linux/spinlock.h>
91874 +#include <linux/io.h>
91875 +
91876 +#include <linux/glamo-gpio.h>
91877 +
91878 +#include "glamo-core.h"
91879 +#include "glamo-regs.h"
91880 +
91881 +void glamo_gpio_setpin(struct glamo_core *glamo, unsigned int pin,
91882 +                      unsigned int value)
91883 +{
91884 +       unsigned int reg = REG_OF_GPIO(pin);
91885 +       u_int16_t tmp;
91886 +
91887 +       spin_lock(&glamo->lock);
91888 +       tmp = readw(glamo->base + reg);
91889 +       if (value)
91890 +               tmp |= OUTPUT_BIT(pin);
91891 +       else
91892 +               tmp &= ~OUTPUT_BIT(pin);
91893 +       writew(tmp, glamo->base + reg);
91894 +       spin_unlock(&glamo->lock);
91895 +}
91896 +EXPORT_SYMBOL(glamo_gpio_setpin);
91897 +
91898 +int glamo_gpio_getpin(struct glamo_core *glamo, unsigned int pin)
91899 +{
91900 +       return readw(REG_OF_GPIO(pin)) & INPUT_BIT(pin) ? 1 : 0;
91901 +}
91902 +EXPORT_SYMBOL(glamo_gpio_getpin);
91903 +
91904 +void glamo_gpio_cfgpin(struct glamo_core *glamo, unsigned int pinfunc)
91905 +{
91906 +       unsigned int reg = REG_OF_GPIO(pinfunc);
91907 +       u_int16_t tmp;
91908 +
91909 +       spin_lock(&glamo->lock);
91910 +       tmp = readw(glamo->base + reg);
91911 +
91912 +       if ((pinfunc & 0x00f0) == GLAMO_GPIO_F_FUNC) {
91913 +               /* pin is a function pin: clear gpio bit */
91914 +               tmp &= ~FUNC_BIT(pinfunc);
91915 +       } else {
91916 +               /* pin is gpio: set gpio bit */
91917 +               tmp |= FUNC_BIT(pinfunc);
91918 +
91919 +               if (pinfunc & GLAMO_GPIO_F_IN) {
91920 +                       /* gpio input: set bit to disable output mode */
91921 +                       tmp |= GPIO_OUT_BIT(pinfunc);
91922 +               } else if (pinfunc & GLAMO_GPIO_F_OUT) {
91923 +                       /* gpio output: clear bit to enable output mode */
91924 +                       tmp &= ~GPIO_OUT_BIT(pinfunc);
91925 +               }
91926 +       }
91927 +       writew(tmp, glamo->base + reg);
91928 +       spin_unlock(&glamo->lock);
91929 +}
91930 +EXPORT_SYMBOL(glamo_gpio_cfgpin);
91931 +
91932 Index: linux-2.6.28/drivers/mfd/glamo/glamo-lcm-spi.c
91933 ===================================================================
91934 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
91935 +++ linux-2.6.28/drivers/mfd/glamo/glamo-lcm-spi.c      2009-01-02 00:01:56.000000000 +0100
91936 @@ -0,0 +1,240 @@
91937 +/*
91938 + * Copyright (C) 2007 Openmoko, Inc.
91939 + * Author: Harald Welte <laforge@openmoko.org>
91940 + *
91941 + * Smedia Glamo GPIO based SPI driver
91942 + *
91943 + * This program is free software; you can redistribute it and/or modify
91944 + * it under the terms of the GNU General Public License version 2 as
91945 + * published by the Free Software Foundation.
91946 + *
91947 + * This driver currently only implements a minimum subset of the hardware
91948 + * features, esp. those features that are required to drive the jbt6k74
91949 + * LCM controller asic in the TD028TTEC1 LCM.
91950 + *
91951 +*/
91952 +
91953 +#define DEBUG
91954 +
91955 +#include <linux/kernel.h>
91956 +#include <linux/init.h>
91957 +#include <linux/delay.h>
91958 +#include <linux/device.h>
91959 +#include <linux/spinlock.h>
91960 +#include <linux/workqueue.h>
91961 +#include <linux/platform_device.h>
91962 +
91963 +#include <linux/spi/spi.h>
91964 +#include <linux/spi/spi_bitbang.h>
91965 +#include <linux/spi/glamo.h>
91966 +
91967 +#include <linux/glamofb.h>
91968 +
91969 +#include <mach/hardware.h>
91970 +
91971 +#include "glamo-core.h"
91972 +#include "glamo-regs.h"
91973 +
91974 +struct glamo_spi {
91975 +       struct spi_bitbang      bitbang;
91976 +       struct spi_master       *master;
91977 +       struct glamo_spi_info   *info;
91978 +       struct device           *dev;
91979 +};
91980 +
91981 +static inline struct glamo_spi *to_gs(struct spi_device *spi)
91982 +{
91983 +       return spi->controller_data;
91984 +}
91985 +
91986 +static int glamo_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
91987 +{
91988 +       unsigned int bpw;
91989 +
91990 +       bpw = t ? t->bits_per_word : spi->bits_per_word;
91991 +
91992 +       if (bpw != 9 && bpw != 8) {
91993 +               dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
91994 +               return -EINVAL;
91995 +       }
91996 +
91997 +       return 0;
91998 +}
91999 +
92000 +static void glamo_spi_chipsel(struct spi_device *spi, int value)
92001 +{
92002 +#if 0
92003 +       struct glamo_spi *gs = to_gs(spi);
92004 +
92005 +       dev_dbg(&spi->dev, "chipsel %d: spi=%p, gs=%p, info=%p, handle=%p\n",
92006 +               value, spi, gs, gs->info, gs->info->glamofb_handle);
92007 +
92008 +       glamofb_cmd_mode(gs->info->glamofb_handle, value);
92009 +#endif
92010 +}
92011 +
92012 +static int glamo_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
92013 +{
92014 +       struct glamo_spi *gs = to_gs(spi);
92015 +       const u_int16_t *ui16 = (const u_int16_t *) t->tx_buf;
92016 +       u_int16_t nine_bits;
92017 +       int i;
92018 +
92019 +       dev_dbg(&spi->dev, "txrx: tx %p, rx %p, bpw %d, len %d\n",
92020 +               t->tx_buf, t->rx_buf, t->bits_per_word, t->len);
92021 +
92022 +       if (spi->bits_per_word == 9)
92023 +               nine_bits = (1 << 9);
92024 +       else
92025 +               nine_bits = 0;
92026 +
92027 +       if (t->len > 3 * sizeof(u_int16_t)) {
92028 +               dev_err(&spi->dev, "this driver doesn't support "
92029 +                       "%u sized xfers\n", t->len);
92030 +               return -EINVAL;
92031 +       }
92032 +
92033 +       for (i = 0; i < t->len/sizeof(u_int16_t); i++) {
92034 +               /* actually transfer the data */
92035 +#if 1
92036 +               glamofb_cmd_write(gs->info->glamofb_handle,
92037 +                                 GLAMO_LCD_CMD_TYPE_SERIAL | nine_bits |
92038 +                                 (1 << 10) | (1 << 11) | (ui16[i] & 0x1ff));
92039 +#endif
92040 +               /* FIXME: fire ?!? */
92041 +               if (i == 0 && (ui16[i] & 0x1ff) == 0x29) {
92042 +                       dev_dbg(&spi->dev, "leaving command mode\n");
92043 +                       glamofb_cmd_mode(gs->info->glamofb_handle, 0);
92044 +               }
92045 +       }
92046 +
92047 +       return t->len;
92048 +}
92049 +
92050 +static int glamo_spi_setup(struct spi_device *spi)
92051 +{
92052 +       int ret;
92053 +
92054 +       if (!spi->bits_per_word)
92055 +               spi->bits_per_word = 9;
92056 +
92057 +       /* FIXME: hardware can do this */
92058 +       if (spi->mode & SPI_LSB_FIRST)
92059 +               return -EINVAL;
92060 +
92061 +       ret = glamo_spi_setupxfer(spi, NULL);
92062 +       if (ret < 0) {
92063 +               dev_err(&spi->dev, "setupxfer returned %d\n", ret);
92064 +               return ret;
92065 +       }
92066 +
92067 +       dev_dbg(&spi->dev, "%s: mode %d, %u bpw\n",
92068 +               __FUNCTION__, spi->mode, spi->bits_per_word);
92069 +
92070 +       return 0;
92071 +}
92072 +
92073 +static int glamo_spi_probe(struct platform_device *pdev)
92074 +{
92075 +       struct spi_master *master;
92076 +       struct glamo_spi *sp;
92077 +       int ret;
92078 +       int i;
92079 +
92080 +       master = spi_alloc_master(&pdev->dev, sizeof(struct glamo_spi));
92081 +       if (master == NULL) {
92082 +               dev_err(&pdev->dev, "failed to allocate spi master\n");
92083 +               ret = -ENOMEM;
92084 +               goto err;
92085 +       }
92086 +
92087 +       sp = spi_master_get_devdata(master);
92088 +       memset(sp, 0, sizeof(struct glamo_spi));
92089 +
92090 +       sp->master = spi_master_get(master);
92091 +       sp->info = pdev->dev.platform_data;
92092 +       if (!sp->info) {
92093 +               dev_err(&pdev->dev, "can't operate without platform data\n");
92094 +               ret = -EIO;
92095 +               goto err_no_pdev;
92096 +       }
92097 +       dev_dbg(&pdev->dev, "sp->info(pdata) = %p\n", sp->info);
92098 +
92099 +       sp->dev = &pdev->dev;
92100 +
92101 +       platform_set_drvdata(pdev, sp);
92102 +
92103 +       sp->bitbang.master = sp->master;
92104 +       sp->bitbang.setup_transfer = glamo_spi_setupxfer;
92105 +       sp->bitbang.chipselect = glamo_spi_chipsel;
92106 +       sp->bitbang.txrx_bufs = glamo_spi_txrx;
92107 +       sp->bitbang.master->setup = glamo_spi_setup;
92108 +
92109 +       ret = spi_bitbang_start(&sp->bitbang);
92110 +       if (ret)
92111 +               goto err_no_bitbang;
92112 +
92113 +       /* register the chips to go with the board */
92114 +
92115 +       glamofb_cmd_mode(sp->info->glamofb_handle, 1);
92116 +
92117 +       for (i = 0; i < sp->info->board_size; i++) {
92118 +               dev_info(&pdev->dev, "registering %p: %s\n",
92119 +                        &sp->info->board_info[i],
92120 +                        sp->info->board_info[i].modalias);
92121 +
92122 +               sp->info->board_info[i].controller_data = sp;
92123 +               spi_new_device(master, sp->info->board_info + i);
92124 +       }
92125 +
92126 +       return 0;
92127 +
92128 +err_no_bitbang:
92129 +       platform_set_drvdata(pdev, NULL);
92130 +err_no_pdev:
92131 +       spi_master_put(sp->bitbang.master);
92132 +err:
92133 +       return ret;
92134 +
92135 +}
92136 +
92137 +static int glamo_spi_remove(struct platform_device *pdev)
92138 +{
92139 +       struct glamo_spi *sp = platform_get_drvdata(pdev);
92140 +
92141 +       spi_bitbang_stop(&sp->bitbang);
92142 +       spi_master_put(sp->bitbang.master);
92143 +
92144 +       return 0;
92145 +}
92146 +
92147 +#define glamo_spi_suspend NULL
92148 +#define glamo_spi_resume NULL
92149 +
92150 +static struct platform_driver glamo_spi_drv = {
92151 +       .probe          = glamo_spi_probe,
92152 +       .remove         = glamo_spi_remove,
92153 +       .suspend        = glamo_spi_suspend,
92154 +       .resume         = glamo_spi_resume,
92155 +       .driver         = {
92156 +               .name   = "glamo-lcm-spi",
92157 +               .owner  = THIS_MODULE,
92158 +       },
92159 +};
92160 +
92161 +static int __init glamo_spi_init(void)
92162 +{
92163 +       return platform_driver_register(&glamo_spi_drv);
92164 +}
92165 +
92166 +static void __exit glamo_spi_exit(void)
92167 +{
92168 +       platform_driver_unregister(&glamo_spi_drv);
92169 +}
92170 +
92171 +module_init(glamo_spi_init);
92172 +module_exit(glamo_spi_exit);
92173 +
92174 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x LCM serial command SPI Driver");
92175 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>")
92176 +MODULE_LICENSE("GPL");
92177 Index: linux-2.6.28/drivers/mfd/glamo/glamo-mci.c
92178 ===================================================================
92179 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
92180 +++ linux-2.6.28/drivers/mfd/glamo/glamo-mci.c  2009-01-02 00:01:56.000000000 +0100
92181 @@ -0,0 +1,1133 @@
92182 +/*
92183 + *  linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
92184 + *
92185 + *  Copyright (C) 2007 Openmoko, Inc,  Andy Green <andy@openmoko.com>
92186 + *  Based on S3C MMC driver that was:
92187 + *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
92188 + *
92189 + * This program is free software; you can redistribute it and/or modify
92190 + * it under the terms of the GNU General Public License version 2 as
92191 + * published by the Free Software Foundation.
92192 + */
92193 +
92194 +#include <linux/module.h>
92195 +#include <linux/dma-mapping.h>
92196 +#include <linux/clk.h>
92197 +#include <linux/mmc/mmc.h>
92198 +#include <linux/mmc/host.h>
92199 +#include <linux/platform_device.h>
92200 +#include <linux/irq.h>
92201 +#include <linux/pcf50633.h>
92202 +#include <linux/delay.h>
92203 +#include <linux/interrupt.h>
92204 +#include <linux/spinlock.h>
92205 +
92206 +#include <asm/dma.h>
92207 +#include <asm/dma-mapping.h>
92208 +#include <asm/io.h>
92209 +
92210 +#include "glamo-mci.h"
92211 +#include "glamo-core.h"
92212 +#include "glamo-regs.h"
92213 +
92214 +/* from glamo-core.c */
92215 +extern struct glamo_mci_pdata glamo_mci_def_pdata;
92216 +
92217 +static spinlock_t clock_lock;
92218 +
92219 +#define DRIVER_NAME "glamo-mci"
92220 +#define RESSIZE(ressource) (((ressource)->end - (ressource)->start) + 1)
92221 +
92222 +static void glamo_mci_send_request(struct mmc_host *mmc);
92223 +
92224 +/*
92225 + * Max SD clock rate
92226 + *
92227 + * held at /(3 + 1) due to concerns of 100R recommended series resistor
92228 + * allows 16MHz @ 4-bit --> 8MBytes/sec raw
92229 + *
92230 + * you can override this on kernel commandline using
92231 + *
92232 + *   glamo_mci.sd_max_clk=10000000
92233 + *
92234 + * for example
92235 + */
92236 +
92237 +static int sd_max_clk = 50000000 / 3;
92238 +module_param(sd_max_clk, int, 0644);
92239 +
92240 +/*
92241 + * Slow SD clock rate
92242 + *
92243 + * you can override this on kernel commandline using
92244 + *
92245 + *   glamo_mci.sd_slow_ratio=8
92246 + *
92247 + * for example
92248 + *
92249 + * platform callback is used to decide effective clock rate, if not
92250 + * defined then max is used, if defined and returns nonzero, rate is
92251 + * divided by this factor
92252 + */
92253 +
92254 +static int sd_slow_ratio = 8;
92255 +module_param(sd_slow_ratio, int, 0644);
92256 +
92257 +/*
92258 + * Post-power SD clock rate
92259 + *
92260 + * you can override this on kernel commandline using
92261 + *
92262 + *   glamo_mci.sd_post_power_clock=1000000
92263 + *
92264 + * for example
92265 + *
92266 + * After changing power to card, clock is held at this rate until first bulk
92267 + * transfer completes
92268 + */
92269 +
92270 +static int sd_post_power_clock = 1000000;
92271 +module_param(sd_post_power_clock, int, 0644);
92272 +
92273 +
92274 +/*
92275 + * SD Signal drive strength
92276 + *
92277 + * you can override this on kernel commandline using
92278 + *
92279 + *   glamo_mci.sd_drive=0
92280 + *
92281 + * for example
92282 + */
92283 +
92284 +static int sd_drive;
92285 +module_param(sd_drive, int, 0644);
92286 +
92287 +/*
92288 + * SD allow SD clock to run while idle
92289 + *
92290 + * you can override this on kernel commandline using
92291 + *
92292 + *   glamo_mci.sd_idleclk=0
92293 + *
92294 + * for example
92295 + */
92296 +
92297 +static int sd_idleclk = 0; /* disallow idle clock by default */
92298 +module_param(sd_idleclk, int, 0644);
92299 +
92300 +/* used to stash real idleclk state in suspend: we force it to run in there */
92301 +static int suspend_sd_idleclk;
92302 +
92303 +
92304 +unsigned char CRC7(u8 * pu8, int cnt)
92305 +{
92306 +       u8 crc = 0;
92307 +
92308 +       while (cnt--) {
92309 +               int n;
92310 +               u8 d = *pu8++;
92311 +               for (n = 0; n < 8; n++) {
92312 +                       crc <<= 1;
92313 +                       if ((d & 0x80) ^ (crc & 0x80))
92314 +                               crc ^= 0x09;
92315 +                       d <<= 1;
92316 +               }
92317 +       }
92318 +       return (crc << 1) | 1;
92319 +}
92320 +
92321 +static int get_data_buffer(struct glamo_mci_host *host,
92322 +                          volatile u32 *words, volatile u16 **pointer)
92323 +{
92324 +       struct scatterlist *sg;
92325 +
92326 +       *words = 0;
92327 +       *pointer = NULL;
92328 +
92329 +       if (host->pio_active == XFER_NONE)
92330 +               return -EINVAL;
92331 +
92332 +       if ((!host->mrq) || (!host->mrq->data))
92333 +               return -EINVAL;
92334 +
92335 +       if (host->pio_sgptr >= host->mrq->data->sg_len) {
92336 +               dev_dbg(&host->pdev->dev, "no more buffers (%i/%i)\n",
92337 +                     host->pio_sgptr, host->mrq->data->sg_len);
92338 +               return -EBUSY;
92339 +       }
92340 +       sg = &host->mrq->data->sg[host->pio_sgptr];
92341 +
92342 +       *words = sg->length >> 1; /* we are working with a 16-bit data bus */
92343 +       *pointer = page_address(sg_page(sg)) + sg->offset;
92344 +
92345 +       BUG_ON(((long)(*pointer)) & 1);
92346 +
92347 +       host->pio_sgptr++;
92348 +
92349 +       /* dev_info(&host->pdev->dev, "new buffer (%i/%i)\n",
92350 +             host->pio_sgptr, host->mrq->data->sg_len); */
92351 +       return 0;
92352 +}
92353 +
92354 +static void do_pio_read(struct glamo_mci_host *host)
92355 +{
92356 +       int res;
92357 +       u16 __iomem *from_ptr = host->base_data + (RESSIZE(host->mem_data) /
92358 +                                                             sizeof(u16) / 2);
92359 +#ifdef DEBUG
92360 +       u16 * block;
92361 +#endif
92362 +
92363 +       while (1) {
92364 +               res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
92365 +               if (res) {
92366 +                       host->pio_active = XFER_NONE;
92367 +                       host->complete_what = COMPLETION_FINALIZE;
92368 +
92369 +                       dev_dbg(&host->pdev->dev, "pio_read(): "
92370 +                               "complete (no more data).\n");
92371 +                       return;
92372 +               }
92373 +
92374 +               dev_dbg(&host->pdev->dev, "pio_read(): host->pio_words: %d\n",
92375 +                               host->pio_words);
92376 +
92377 +               host->pio_count += host->pio_words << 1;
92378 +
92379 +#ifdef DEBUG
92380 +               block = (u16 *)host->pio_ptr;
92381 +               res = host->pio_words << 1;
92382 +#endif
92383 +#if 0
92384 +               /* u16-centric memcpy */
92385 +               while (host->pio_words--)
92386 +                       *host->pio_ptr++ = *from_ptr++;
92387 +#else
92388 +               /* memcpy can be faster? */
92389 +               memcpy((void *)host->pio_ptr, from_ptr, host->pio_words << 1);
92390 +               host->pio_ptr += host->pio_words;
92391 +#endif
92392 +
92393 +#ifdef DEBUG
92394 +               print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
92395 +                              (void *)block, res, 1);
92396 +#endif
92397 +       }
92398 +}
92399 +
92400 +static int do_pio_write(struct glamo_mci_host *host)
92401 +{
92402 +       int res = 0;
92403 +       volatile u16 __iomem *to_ptr = host->base_data;
92404 +       int err = 0;
92405 +
92406 +       dev_dbg(&host->pdev->dev, "pio_write():\n");
92407 +       while (!res) {
92408 +               res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
92409 +               if (res)
92410 +                       continue;
92411 +
92412 +               dev_dbg(&host->pdev->dev, "pio_write():new source: [%i]@[%p]\n",
92413 +                       host->pio_words, host->pio_ptr);
92414 +
92415 +               host->pio_count += host->pio_words << 1;
92416 +               while (host->pio_words--)
92417 +                       writew(*host->pio_ptr++, to_ptr++);
92418 +       }
92419 +
92420 +       dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
92421 +       host->pio_active = XFER_NONE;
92422 +       return err;
92423 +}
92424 +
92425 +static void __glamo_mci_fix_card_div(struct glamo_mci_host *host, int div)
92426 +{
92427 +       unsigned long flags;
92428 +
92429 +       spin_lock_irqsave(&clock_lock, flags);
92430 +
92431 +       if (div < 0) {
92432 +               /* stop clock - remove clock from divider input */
92433 +               writew(readw(glamo_mci_def_pdata.pglamo->base +
92434 +                    GLAMO_REG_CLOCK_GEN5_1) & (~GLAMO_CLOCK_GEN51_EN_DIV_TCLK),
92435 +                    glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
92436 +
92437 +               goto done;
92438 +       } else {
92439 +               /* set the nearest prescaler factor
92440 +               *
92441 +               * register shared with SCLK divisor -- no chance of race because
92442 +               * we don't use sensor interface
92443 +               */
92444 +               writew((readw(glamo_mci_def_pdata.pglamo->base +
92445 +                               GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
92446 +                      glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN8);
92447 +               /* enable clock to divider input */
92448 +               writew(readw(glamo_mci_def_pdata.pglamo->base +
92449 +                       GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
92450 +                    glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
92451 +       }
92452 +
92453 +       if (host->force_slow_during_powerup)
92454 +               div = host->clk_rate / sd_post_power_clock;
92455 +       else
92456 +               if (host->pdata->glamo_mci_use_slow)
92457 +                       if ((host->pdata->glamo_mci_use_slow)())
92458 +                               div = div * sd_slow_ratio;
92459 +
92460 +       if (div > 255)
92461 +               div = 255;
92462 +
92463 +       /*
92464 +        * set the nearest prescaler factor
92465 +        *
92466 +        * register shared with SCLK divisor -- no chance of race because
92467 +        * we don't use sensor interface
92468 +        */
92469 +       writew((readw(glamo_mci_def_pdata.pglamo->base +
92470 +                       GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
92471 +               glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN8);
92472 +       /* enable clock to divider input */
92473 +       writew(readw(glamo_mci_def_pdata.pglamo->base +
92474 +               GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
92475 +               glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
92476 +
92477 +done:
92478 +       spin_unlock_irqrestore(&clock_lock, flags);
92479 +}
92480 +
92481 +static int __glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq,
92482 +                                                                 int *division)
92483 +{
92484 +       int div = 0;
92485 +       int real_rate = 0;
92486 +
92487 +       if (freq) {
92488 +               /* Set clock */
92489 +               for (div = 0; div < 256; div++) {
92490 +                       real_rate = host->clk_rate / (div + 1);
92491 +                       if (real_rate <= freq)
92492 +                               break;
92493 +               }
92494 +               if (div > 255)
92495 +                       div = 255;
92496 +
92497 +               if (division)
92498 +                       *division = div;
92499 +
92500 +               __glamo_mci_fix_card_div(host, div);
92501 +
92502 +       } else {
92503 +               /* stop clock */
92504 +               if (division)
92505 +                       *division = 0xff;
92506 +
92507 +               if (!sd_idleclk && !host->force_slow_during_powerup)
92508 +                       /* clock off */
92509 +                       __glamo_mci_fix_card_div(host, -1);
92510 +       }
92511 +
92512 +       return real_rate;
92513 +}
92514 +
92515 +static void glamo_mci_irq(unsigned int irq, struct irq_desc *desc)
92516 +{
92517 +       struct glamo_mci_host *host = (struct glamo_mci_host *)
92518 +                                     desc->handler_data;
92519 +       u16 status;
92520 +       struct mmc_command *cmd;
92521 +       unsigned long iflags;
92522 +
92523 +       if (!host)
92524 +               return;
92525 +
92526 +       if (host->suspending) { /* bad news, dangerous time */
92527 +               dev_err(&host->pdev->dev, "****glamo_mci_irq before resumed\n");
92528 +               return;
92529 +       }
92530 +
92531 +       if (!host->mrq)
92532 +               return;
92533 +       cmd = host->mrq->cmd;
92534 +       if (!cmd)
92535 +               return;
92536 +
92537 +       spin_lock_irqsave(&host->complete_lock, iflags);
92538 +
92539 +       status = readw(host->base + GLAMO_REG_MMC_RB_STAT1);
92540 +
92541 +       /* ack this interrupt source */
92542 +       writew(GLAMO_IRQ_MMC,
92543 +              glamo_mci_def_pdata.pglamo->base + GLAMO_REG_IRQ_CLEAR);
92544 +
92545 +       if (status & (GLAMO_STAT1_MMC_RTOUT |
92546 +                     GLAMO_STAT1_MMC_DTOUT))
92547 +               cmd->error = -ETIMEDOUT;
92548 +       if (status & (GLAMO_STAT1_MMC_BWERR |
92549 +                     GLAMO_STAT1_MMC_BRERR))
92550 +               cmd->error = -EILSEQ;
92551 +       if (cmd->error) {
92552 +               dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
92553 +               goto done;
92554 +       }
92555 +
92556 +       /* disable the initial slow start after first bulk transfer */
92557 +       if (host->force_slow_during_powerup)
92558 +               host->force_slow_during_powerup--;
92559 +
92560 +       if (host->pio_active == XFER_READ)
92561 +               do_pio_read(host);
92562 +
92563 +       host->mrq->data->bytes_xfered = host->pio_count;
92564 +       dev_dbg(&host->pdev->dev, "status = 0x%04x count=%d\n",
92565 +                status, host->pio_count);
92566 +
92567 +       /* issue STOP if we have been given one to use */
92568 +       if (host->mrq->stop) {
92569 +               host->cmd_is_stop = 1;
92570 +               glamo_mci_send_request(host->mmc);
92571 +               host->cmd_is_stop = 0;
92572 +       }
92573 +
92574 +       if (!sd_idleclk && !host->force_slow_during_powerup)
92575 +               /* clock off */
92576 +               __glamo_mci_fix_card_div(host, -1);
92577 +
92578 +done:
92579 +       host->complete_what = COMPLETION_NONE;
92580 +       host->mrq = NULL;
92581 +       mmc_request_done(host->mmc, cmd->mrq);
92582 +       spin_unlock_irqrestore(&host->complete_lock, iflags);
92583 +}
92584 +
92585 +static int glamo_mci_send_command(struct glamo_mci_host *host,
92586 +                                 struct mmc_command *cmd)
92587 +{
92588 +       u8 u8a[6];
92589 +       u16 fire = 0;
92590 +
92591 +       /* if we can't do it, reject as busy */
92592 +       if (!readw(host->base + GLAMO_REG_MMC_RB_STAT1) &
92593 +            GLAMO_STAT1_MMC_IDLE) {
92594 +               host->mrq = NULL;
92595 +               cmd->error = -EBUSY;
92596 +               mmc_request_done(host->mmc, host->mrq);
92597 +               return -EBUSY;
92598 +       }
92599 +
92600 +       /* create an array in wire order for CRC computation */
92601 +       u8a[0] = 0x40 | (cmd->opcode & 0x3f);
92602 +       u8a[1] = (u8)(cmd->arg >> 24);
92603 +       u8a[2] = (u8)(cmd->arg >> 16);
92604 +       u8a[3] = (u8)(cmd->arg >> 8);
92605 +       u8a[4] = (u8)cmd->arg;
92606 +       u8a[5] = CRC7(&u8a[0], 5); /* CRC7 on first 5 bytes of packet */
92607 +
92608 +       /* issue the wire-order array including CRC in register order */
92609 +       writew((u8a[4] << 8) | u8a[5], host->base + GLAMO_REG_MMC_CMD_REG1);
92610 +       writew((u8a[2] << 8) | u8a[3], host->base + GLAMO_REG_MMC_CMD_REG2);
92611 +       writew((u8a[0] << 8) | u8a[1], host->base + GLAMO_REG_MMC_CMD_REG3);
92612 +
92613 +       /* command index toggle */
92614 +       fire |= (host->ccnt & 1) << 12;
92615 +
92616 +       /* set type of command */
92617 +       switch (mmc_cmd_type(cmd)) {
92618 +       case MMC_CMD_BC:
92619 +               fire |= GLAMO_FIRE_MMC_CMDT_BNR;
92620 +               break;
92621 +       case MMC_CMD_BCR:
92622 +               fire |= GLAMO_FIRE_MMC_CMDT_BR;
92623 +               break;
92624 +       case MMC_CMD_AC:
92625 +               fire |= GLAMO_FIRE_MMC_CMDT_AND;
92626 +               break;
92627 +       case MMC_CMD_ADTC:
92628 +               fire |= GLAMO_FIRE_MMC_CMDT_AD;
92629 +               break;
92630 +       }
92631 +       /*
92632 +        * if it expects a response, set the type expected
92633 +        *
92634 +        * R1, Length  : 48bit, Normal response
92635 +        * R1b, Length : 48bit, same R1, but added card busy status
92636 +        * R2, Length  : 136bit (really 128 bits with CRC snipped)
92637 +        * R3, Length  : 48bit (OCR register value)
92638 +        * R4, Length  : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
92639 +        * R5, Length  : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
92640 +        * R6, Length  : 48bit (RCA register)
92641 +        * R7, Length  : 48bit (interface condition, VHS(voltage supplied),
92642 +        *                     check pattern, CRC7)
92643 +        */
92644 +       switch (mmc_resp_type(cmd)) {
92645 +       case MMC_RSP_R6: /* same index as R7 and R1 */
92646 +               fire |= GLAMO_FIRE_MMC_RSPT_R1;
92647 +               break;
92648 +       case MMC_RSP_R1B:
92649 +               fire |= GLAMO_FIRE_MMC_RSPT_R1b;
92650 +               break;
92651 +       case MMC_RSP_R2:
92652 +               fire |= GLAMO_FIRE_MMC_RSPT_R2;
92653 +               break;
92654 +       case MMC_RSP_R3:
92655 +               fire |= GLAMO_FIRE_MMC_RSPT_R3;
92656 +               break;
92657 +       /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
92658 +       }
92659 +       /*
92660 +        * From the command index, set up the command class in the host ctrllr
92661 +        *
92662 +        * missing guys present on chip but couldn't figure out how to use yet:
92663 +        *     0x0 "stream read"
92664 +        *     0x9 "cancel running command"
92665 +        */
92666 +       switch (cmd->opcode) {
92667 +       case MMC_READ_SINGLE_BLOCK:
92668 +               fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
92669 +               break;
92670 +       case MMC_SWITCH: /* 64 byte payload */
92671 +       case 0x33: /* observed issued by MCI */
92672 +       case MMC_READ_MULTIPLE_BLOCK:
92673 +               /* we will get an interrupt off this */
92674 +               if (!cmd->mrq->stop)
92675 +                       /* multiblock no stop */
92676 +                       fire |= GLAMO_FIRE_MMC_CC_MBRNS;
92677 +               else
92678 +                        /* multiblock with stop */
92679 +                       fire |= GLAMO_FIRE_MMC_CC_MBRS;
92680 +               break;
92681 +       case MMC_WRITE_BLOCK:
92682 +               fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
92683 +               break;
92684 +       case MMC_WRITE_MULTIPLE_BLOCK:
92685 +               if (cmd->mrq->stop)
92686 +                        /* multiblock with stop */
92687 +                       fire |= GLAMO_FIRE_MMC_CC_MBWS;
92688 +               else
92689 +//                      /* multiblock NO stop-- 'RESERVED'? */
92690 +                       fire |= GLAMO_FIRE_MMC_CC_MBWNS;
92691 +               break;
92692 +       case MMC_STOP_TRANSMISSION:
92693 +               fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
92694 +               break;
92695 +       default:
92696 +               fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
92697 +               break;
92698 +       }
92699 +
92700 +       /* always largest timeout */
92701 +       writew(0xfff, host->base + GLAMO_REG_MMC_TIMEOUT);
92702 +
92703 +       /* Generate interrupt on txfer */
92704 +       writew((readw(host->base + GLAMO_REG_MMC_BASIC) & 0x3e) |
92705 +                  0x0800 | GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
92706 +                  GLAMO_BASIC_MMC_EN_COMPL_INT | (sd_drive << 6),
92707 +                  host->base + GLAMO_REG_MMC_BASIC);
92708 +
92709 +       /* send the command out on the wire */
92710 +       /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
92711 +       writew(fire, host->base + GLAMO_REG_MMC_CMD_FIRE);
92712 +       cmd->error = 0;
92713 +       return 0;
92714 +}
92715 +
92716 +static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
92717 +                                struct mmc_data *data)
92718 +{
92719 +       /*
92720 +        * the S-Media-internal RAM offset for our MMC buffer
92721 +        * Read is halfway up the buffer and write is at the start
92722 +        */
92723 +       if (data->flags & MMC_DATA_READ) {
92724 +               writew((u16)(GLAMO_FB_SIZE + (RESSIZE(host->mem_data) / 2)),
92725 +                          host->base + GLAMO_REG_MMC_WDATADS1);
92726 +               writew((u16)((GLAMO_FB_SIZE +
92727 +                                       (RESSIZE(host->mem_data) / 2)) >> 16),
92728 +                          host->base + GLAMO_REG_MMC_WDATADS2);
92729 +       } else {
92730 +               writew((u16)GLAMO_FB_SIZE, host->base +
92731 +                                              GLAMO_REG_MMC_RDATADS1);
92732 +               writew((u16)(GLAMO_FB_SIZE >> 16), host->base +
92733 +                                                      GLAMO_REG_MMC_RDATADS2);
92734 +       }
92735 +
92736 +       /* set up the block info */
92737 +       writew(data->blksz, host->base + GLAMO_REG_MMC_DATBLKLEN);
92738 +       writew(data->blocks, host->base + GLAMO_REG_MMC_DATBLKCNT);
92739 +       dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
92740 +                                  data->blksz, data->blocks);
92741 +       host->pio_sgptr = 0;
92742 +       host->pio_words = 0;
92743 +       host->pio_count = 0;
92744 +       host->pio_active = 0;
92745 +       /* if write, prep the write into the shared RAM before the command */
92746 +       if (data->flags & MMC_DATA_WRITE) {
92747 +               host->pio_active = XFER_WRITE;
92748 +               return do_pio_write(host);
92749 +       }
92750 +       host->pio_active = XFER_READ;
92751 +       return 0;
92752 +}
92753 +
92754 +static void glamo_mci_send_request(struct mmc_host *mmc)
92755 +{
92756 +       struct glamo_mci_host *host = mmc_priv(mmc);
92757 +       struct mmc_request *mrq = host->mrq;
92758 +       struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
92759 +       u16 * pu16 = (u16 *)&cmd->resp[0];
92760 +       u16 * reg_resp = (u16 *)(host->base + GLAMO_REG_MMC_CMD_RSP1);
92761 +       u16 status;
92762 +       int n;
92763 +       int timeout = 1000000;
92764 +       int insanity_timeout = 1000000;
92765 +
92766 +       if (host->suspending) {
92767 +               dev_err(&host->pdev->dev, "IGNORING glamo_mci_send_request while "
92768 +                                                                "suspended\n");
92769 +               cmd->error = -EIO;
92770 +               if (cmd->data)
92771 +                       cmd->data->error = -EIO;
92772 +               mmc_request_done(mmc, mrq);
92773 +               return;
92774 +       }
92775 +
92776 +       host->ccnt++;
92777 +       /*
92778 +        * somehow 2.6.24 MCI manages to issue MMC_WRITE_BLOCK *without* the
92779 +        * MMC_DATA_WRITE flag, WTF?  Work around the madness.
92780 +        */
92781 +       if (cmd->opcode == MMC_WRITE_BLOCK)
92782 +               if (mrq->data)
92783 +                       mrq->data->flags |= MMC_DATA_WRITE;
92784 +
92785 +        /* this guy has data to read/write? */
92786 +       if ((!host->cmd_is_stop) && cmd->data) {
92787 +               int res;
92788 +               host->dcnt++;
92789 +               res = glamo_mci_prepare_pio(host, cmd->data);
92790 +               if (res) {
92791 +                       cmd->error = -EIO;
92792 +                       cmd->data->error = -EIO;
92793 +                       mmc_request_done(mmc, mrq);
92794 +                       return;
92795 +               }
92796 +       }
92797 +
92798 +       dev_dbg(&host->pdev->dev,"cmd 0x%x, "
92799 +                "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
92800 +                cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
92801 +                cmd->flags);
92802 +
92803 +       /* resume requested clock rate
92804 +        * scale it down by sd_slow_ratio if platform requests it
92805 +        */
92806 +       __glamo_mci_fix_card_div(host, host->clk_div);
92807 +
92808 +       if (glamo_mci_send_command(host, cmd))
92809 +               goto bail;
92810 +
92811 +       /* we are deselecting card?  because it isn't going to ack then... */
92812 +       if ((cmd->opcode == 7) && (cmd->arg == 0))
92813 +               goto done;
92814 +
92815 +       /*
92816 +        * we must spin until response is ready or timed out
92817 +        * -- we don't get interrupts unless there is a bulk rx
92818 +        */
92819 +       do
92820 +               status = readw(host->base + GLAMO_REG_MMC_RB_STAT1);
92821 +       while (((((status >> 15) & 1) != (host->ccnt & 1)) ||
92822 +               (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
92823 +                            GLAMO_STAT1_MMC_RTOUT |
92824 +                            GLAMO_STAT1_MMC_DTOUT |
92825 +                            GLAMO_STAT1_MMC_BWERR |
92826 +                            GLAMO_STAT1_MMC_BRERR)))) && (insanity_timeout--));
92827 +
92828 +       if (insanity_timeout < 0)
92829 +               dev_info(&host->pdev->dev, "command timeout, continuing\n");
92830 +
92831 +       if (status & (GLAMO_STAT1_MMC_RTOUT |
92832 +                     GLAMO_STAT1_MMC_DTOUT))
92833 +               cmd->error = -ETIMEDOUT;
92834 +       if (status & (GLAMO_STAT1_MMC_BWERR |
92835 +                     GLAMO_STAT1_MMC_BRERR))
92836 +               cmd->error = -EILSEQ;
92837 +
92838 +       if (host->cmd_is_stop)
92839 +               goto bail;
92840 +
92841 +       if (cmd->error) {
92842 +               dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
92843 +               goto done;
92844 +       }
92845 +       /*
92846 +        * mangle the response registers in two different exciting
92847 +        * undocumented ways discovered by trial and error
92848 +        */
92849 +       if (mmc_resp_type(cmd) == MMC_RSP_R2)
92850 +               /* grab the response */
92851 +               for (n = 0; n < 8; n++) /* super mangle power 1 */
92852 +                       pu16[n ^ 6] = readw(&reg_resp[n]);
92853 +       else
92854 +               for (n = 0; n < 3; n++) /* super mangle power 2 */
92855 +                       pu16[n] = (readw(&reg_resp[n]) >> 8) |
92856 +                                 (readw(&reg_resp[n + 1]) << 8);
92857 +       /*
92858 +        * if we don't have bulk data to take care of, we're done
92859 +        */
92860 +       if (!cmd->data)
92861 +               goto done;
92862 +       if (!(cmd->data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)))
92863 +               goto done;
92864 +
92865 +       /*
92866 +        * Otherwise can can use the interrupt as async completion --
92867 +        * if there is read data coming, or we wait for write data to complete,
92868 +        * exit without mmc_request_done() as the payload interrupt
92869 +        * will service it
92870 +        */
92871 +       dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
92872 +       /*
92873 +        * if the glamo INT# line isn't wired (*cough* it can happen)
92874 +        * I'm afraid we have to spin on the IRQ status bit and "be
92875 +        * our own INT# line"
92876 +        */
92877 +       if (!glamo_mci_def_pdata.pglamo->irq_works) {
92878 +               /*
92879 +                * we have faith we will get an "interrupt"...
92880 +                * but something insane like suspend problems can mean
92881 +                * we spin here forever, so we timeout after a LONG time
92882 +                */
92883 +               while ((!(readw(glamo_mci_def_pdata.pglamo->base +
92884 +                        GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
92885 +                      (timeout--))
92886 +                       ;
92887 +
92888 +               if (timeout < 0) {
92889 +                       if (cmd->data->error)
92890 +                               cmd->data->error = -ETIMEDOUT;
92891 +                       dev_err(&host->pdev->dev, "Payload timeout\n");
92892 +                       goto bail;
92893 +               }
92894 +
92895 +               /* yay we are an interrupt controller! -- call the ISR
92896 +                * it will stop clock to card
92897 +                */
92898 +               glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC),
92899 +                             irq_desc + IRQ_GLAMO(GLAMO_IRQIDX_MMC));
92900 +       }
92901 +       return;
92902 +
92903 +done:
92904 +       host->complete_what = COMPLETION_NONE;
92905 +       host->mrq = NULL;
92906 +       mmc_request_done(host->mmc, cmd->mrq);
92907 +bail:
92908 +       if (!sd_idleclk && !host->force_slow_during_powerup)
92909 +               /* stop the clock to card */
92910 +               __glamo_mci_fix_card_div(host, -1);
92911 +}
92912 +
92913 +static void glamo_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
92914 +{
92915 +       struct glamo_mci_host *host = mmc_priv(mmc);
92916 +
92917 +       host->cmd_is_stop = 0;
92918 +       host->mrq = mrq;
92919 +       glamo_mci_send_request(mmc);
92920 +}
92921 +
92922 +#if 1
92923 +static void glamo_mci_reset(struct glamo_mci_host *host)
92924 +{
92925 +       if (host->suspending) {
92926 +               dev_err(&host->pdev->dev, "IGNORING glamo_mci_reset while "
92927 +                                                                "suspended\n");
92928 +               return;
92929 +       }
92930 +       dev_dbg(&host->pdev->dev, "******* glamo_mci_reset\n");
92931 +       /* reset MMC controller */
92932 +       writew(GLAMO_CLOCK_MMC_RESET | GLAMO_CLOCK_MMC_DG_TCLK |
92933 +                  GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
92934 +                  GLAMO_CLOCK_MMC_EN_M9CLK,
92935 +                  glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
92936 +       udelay(10);
92937 +       /* and disable reset */
92938 +       writew(GLAMO_CLOCK_MMC_DG_TCLK |
92939 +                  GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
92940 +                  GLAMO_CLOCK_MMC_EN_M9CLK,
92941 +                  glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
92942 +}
92943 +#endif
92944 +static inline int glamo_mci_get_mv(int vdd)
92945 +{
92946 +       int mv = 1650;
92947 +
92948 +       if (vdd > 7)
92949 +               mv += 350 + 100 * (vdd - 8);
92950 +
92951 +       return mv;
92952 +}
92953 +
92954 +static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
92955 +{
92956 +       struct glamo_mci_host *host = mmc_priv(mmc);
92957 +       struct regulator *regulator;
92958 +       int n = 0;
92959 +       int div;
92960 +       int powering = 0;
92961 +       int mv;
92962 +
92963 +       if (host->suspending) {
92964 +               dev_err(&host->pdev->dev, "IGNORING glamo_mci_set_ios while "
92965 +                                                                "suspended\n");
92966 +               return;
92967 +       }
92968 +
92969 +       regulator = host->regulator;
92970 +
92971 +       /* Set power */
92972 +       switch(ios->power_mode) {
92973 +       case MMC_POWER_UP:
92974 +               if (host->pdata->glamo_can_set_mci_power()) {
92975 +                       mv = glamo_mci_get_mv(ios->vdd);
92976 +                       regulator_set_voltage(regulator, mv * 1000, mv * 1000);
92977 +                       regulator_enable(regulator);
92978 +               }
92979 +               break;
92980 +       case MMC_POWER_ON:
92981 +               /*
92982 +                * we should use very slow clock until first bulk
92983 +                * transfer completes OK
92984 +                */
92985 +               host->force_slow_during_powerup = 1;
92986 +
92987 +               if (host->vdd_current != ios->vdd) {
92988 +                       if (host->pdata->glamo_can_set_mci_power()) {
92989 +                               mv = glamo_mci_get_mv(ios->vdd);
92990 +                               regulator_set_voltage(regulator, mv * 1000, mv * 1000);
92991 +                               printk(KERN_INFO "SD power -> %dmV\n", mv);
92992 +                       }
92993 +                       host->vdd_current = ios->vdd;
92994 +               }
92995 +               if (host->power_mode_current == MMC_POWER_OFF) {
92996 +                       glamo_engine_enable(glamo_mci_def_pdata.pglamo,
92997 +                                                             GLAMO_ENGINE_MMC);
92998 +                       powering = 1;
92999 +               }
93000 +               break;
93001 +
93002 +       case MMC_POWER_OFF:
93003 +       default:
93004 +               if (host->power_mode_current == MMC_POWER_OFF)
93005 +                       break;
93006 +               /* never want clocking with dead card */
93007 +               __glamo_mci_fix_card_div(host, -1);
93008 +
93009 +               glamo_engine_disable(glamo_mci_def_pdata.pglamo,
93010 +                                    GLAMO_ENGINE_MMC);
93011 +               regulator_disable(regulator);
93012 +               host->vdd_current = -1;
93013 +               break;
93014 +       }
93015 +       host->power_mode_current = ios->power_mode;
93016 +
93017 +       host->real_rate = __glamo_mci_set_card_clock(host, ios->clock, &div);
93018 +       host->clk_div = div;
93019 +
93020 +       /* after power-up, we are meant to give it >= 74 clocks so it can
93021 +        * initialize itself.  Doubt any modern cards need it but anyway...
93022 +        */
93023 +       if (powering)
93024 +               mdelay(1);
93025 +
93026 +       if (!sd_idleclk && !host->force_slow_during_powerup)
93027 +               /* stop the clock to card, because we are idle until transfer */
93028 +               __glamo_mci_fix_card_div(host, -1);
93029 +
93030 +       if ((ios->power_mode == MMC_POWER_ON) ||
93031 +           (ios->power_mode == MMC_POWER_UP)) {
93032 +               dev_info(&host->pdev->dev,
93033 +                       "powered (vdd = %d) clk: %lukHz div=%d (req: %ukHz). "
93034 +                       "Bus width=%d\n",(int)ios->vdd,
93035 +                       host->real_rate / 1000, (int)host->clk_div,
93036 +                       ios->clock / 1000, (int)ios->bus_width);
93037 +       } else
93038 +               dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
93039 +
93040 +       /* set bus width */
93041 +       host->bus_width = ios->bus_width;
93042 +       if (host->bus_width == MMC_BUS_WIDTH_4)
93043 +               n = GLAMO_BASIC_MMC_EN_4BIT_DATA;
93044 +       writew((readw(host->base + GLAMO_REG_MMC_BASIC) &
93045 +                                         (~(GLAMO_BASIC_MMC_EN_4BIT_DATA |
93046 +                                            GLAMO_BASIC_MMC_EN_DR_STR0 |
93047 +                                            GLAMO_BASIC_MMC_EN_DR_STR1))) | n |
93048 +                              sd_drive << 6, host->base + GLAMO_REG_MMC_BASIC);
93049 +}
93050 +
93051 +
93052 +/*
93053 + * no physical write protect supported by us
93054 + */
93055 +static int glamo_mci_get_ro(struct mmc_host *mmc)
93056 +{
93057 +       return 0;
93058 +}
93059 +
93060 +static struct mmc_host_ops glamo_mci_ops = {
93061 +       .request        = glamo_mci_request,
93062 +       .set_ios        = glamo_mci_set_ios,
93063 +       .get_ro         = glamo_mci_get_ro,
93064 +};
93065 +
93066 +static int glamo_mci_probe(struct platform_device *pdev)
93067 +{
93068 +       struct mmc_host         *mmc;
93069 +       struct glamo_mci_host   *host;
93070 +       int ret;
93071 +
93072 +       dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
93073 +
93074 +       mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
93075 +       if (!mmc) {
93076 +               ret = -ENOMEM;
93077 +               goto probe_out;
93078 +       }
93079 +
93080 +       host = mmc_priv(mmc);
93081 +       host->mmc = mmc;
93082 +       host->pdev = pdev;
93083 +       host->pdata = &glamo_mci_def_pdata;
93084 +       host->power_mode_current = MMC_POWER_OFF;
93085 +
93086 +       host->complete_what = COMPLETION_NONE;
93087 +       host->pio_active = XFER_NONE;
93088 +
93089 +       spin_lock_init(&host->complete_lock);
93090 +
93091 +       host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
93092 +       if (!host->mem) {
93093 +               dev_err(&pdev->dev,
93094 +                       "failed to get io memory region resouce.\n");
93095 +
93096 +               ret = -ENOENT;
93097 +               goto probe_free_host;
93098 +       }
93099 +
93100 +       host->mem = request_mem_region(host->mem->start,
93101 +               RESSIZE(host->mem), pdev->name);
93102 +
93103 +       if (!host->mem) {
93104 +               dev_err(&pdev->dev, "failed to request io memory region.\n");
93105 +               ret = -ENOENT;
93106 +               goto probe_free_host;
93107 +       }
93108 +
93109 +       host->base = ioremap(host->mem->start, RESSIZE(host->mem));
93110 +       if (!host->base) {
93111 +               dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
93112 +               ret = -EINVAL;
93113 +               goto probe_free_mem_region;
93114 +       }
93115 +
93116 +       host->regulator = regulator_get(&pdev->dev, "SD_3V3");
93117 +       if (!host->regulator) {
93118 +               dev_err(&pdev->dev, "Cannot proceed without regulator.\n");
93119 +               return -ENODEV;
93120 +       }
93121 +
93122 +       /* set the handler for our bit of the shared chip irq register */
93123 +       set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq);
93124 +       /* stash host as our handler's private data */
93125 +       set_irq_data(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
93126 +
93127 +       /* Get ahold of our data buffer we use for data in and out on MMC */
93128 +       host->mem_data = platform_get_resource(pdev, IORESOURCE_MEM, 1);
93129 +       if (!host->mem_data) {
93130 +               dev_err(&pdev->dev,
93131 +                       "failed to get io memory region resource.\n");
93132 +               ret = -ENOENT;
93133 +               goto probe_iounmap;
93134 +       }
93135 +
93136 +       host->mem_data = request_mem_region(host->mem_data->start,
93137 +               RESSIZE(host->mem_data), pdev->name);
93138 +
93139 +       if (!host->mem_data) {
93140 +               dev_err(&pdev->dev, "failed to request io memory region.\n");
93141 +               ret = -ENOENT;
93142 +               goto probe_iounmap;
93143 +       }
93144 +       host->base_data = ioremap(host->mem_data->start,
93145 +                                         RESSIZE(host->mem_data));
93146 +       host->data_max_size = RESSIZE(host->mem_data);
93147 +
93148 +       if (host->base_data == 0) {
93149 +               dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
93150 +               ret = -EINVAL;
93151 +               goto probe_free_mem_region_data;
93152 +       }
93153 +
93154 +       host->vdd_current = 0;
93155 +       host->clk_rate = 50000000; /* really it's 49152000 */
93156 +       host->clk_div = 16;
93157 +
93158 +       /* explain our host controller capabilities */
93159 +       mmc->ops        = &glamo_mci_ops;
93160 +       mmc->ocr_avail  = host->pdata->ocr_avail;
93161 +       mmc->caps       = MMC_CAP_4_BIT_DATA |
93162 +                         MMC_CAP_MMC_HIGHSPEED |
93163 +                         MMC_CAP_SD_HIGHSPEED;
93164 +       mmc->f_min      = host->clk_rate / 256;
93165 +       mmc->f_max      = sd_max_clk;
93166 +
93167 +       mmc->max_blk_count      = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
93168 +       mmc->max_blk_size       = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
93169 +       mmc->max_req_size       = RESSIZE(host->mem_data) / 2;
93170 +       mmc->max_seg_size       = mmc->max_req_size;
93171 +       mmc->max_phys_segs      = 1; /* hw doesn't talk about segs??? */
93172 +       mmc->max_hw_segs        = 1;
93173 +
93174 +       dev_info(&host->pdev->dev, "probe: mapped mci_base:%p irq:%u.\n",
93175 +               host->base, host->irq);
93176 +
93177 +       platform_set_drvdata(pdev, mmc);
93178 +
93179 +       glamo_engine_enable(glamo_mci_def_pdata.pglamo, GLAMO_ENGINE_MMC);
93180 +       glamo_mci_reset(host);
93181 +
93182 +       if ((ret = mmc_add_host(mmc))) {
93183 +               dev_err(&pdev->dev, "failed to add mmc host.\n");
93184 +               goto probe_free_mem_region_data;
93185 +       }
93186 +
93187 +       dev_info(&pdev->dev,"initialisation done.\n");
93188 +       return 0;
93189 +
93190 + probe_free_mem_region_data:
93191 +       release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
93192 +
93193 + probe_iounmap:
93194 +       iounmap(host->base);
93195 +
93196 + probe_free_mem_region:
93197 +       release_mem_region(host->mem->start, RESSIZE(host->mem));
93198 +
93199 + probe_free_host:
93200 +       mmc_free_host(mmc);
93201 + probe_out:
93202 +       return ret;
93203 +}
93204 +
93205 +static int glamo_mci_remove(struct platform_device *pdev)
93206 +{
93207 +       struct mmc_host         *mmc  = platform_get_drvdata(pdev);
93208 +       struct glamo_mci_host   *host = mmc_priv(mmc);
93209 +       struct regulator *regulator;
93210 +
93211 +       mmc_remove_host(mmc);
93212 +       /* stop using our handler, revert it to default */
93213 +       set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), handle_level_irq);
93214 +       iounmap(host->base);
93215 +       iounmap(host->base_data);
93216 +       release_mem_region(host->mem->start, RESSIZE(host->mem));
93217 +       release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
93218 +
93219 +       regulator = host->regulator;
93220 +       regulator_put(regulator);
93221 +
93222 +       mmc_free_host(mmc);
93223 +
93224 +       glamo_engine_disable(glamo_mci_def_pdata.pglamo, GLAMO_ENGINE_MMC);
93225 +       return 0;
93226 +}
93227 +
93228 +
93229 +#ifdef CONFIG_PM
93230 +
93231 +static int glamo_mci_suspend(struct platform_device *dev, pm_message_t state)
93232 +{
93233 +       struct mmc_host *mmc = platform_get_drvdata(dev);
93234 +       struct glamo_mci_host   *host = mmc_priv(mmc);
93235 +       int ret;
93236 +
93237 +       /*
93238 +        * possible workaround for SD corruption during suspend - resume
93239 +        * make sure the clock was running during suspend and consequently
93240 +        * resume
93241 +        */
93242 +       __glamo_mci_fix_card_div(host, host->clk_div);
93243 +
93244 +       /* we are going to do more commands to override this in
93245 +        * mmc_suspend_host(), so we need to change sd_idleclk for the
93246 +        * duration as well
93247 +        */
93248 +       suspend_sd_idleclk = sd_idleclk;
93249 +       sd_idleclk = 1;
93250 +
93251 +       ret = mmc_suspend_host(mmc, state);
93252 +
93253 +       host->suspending++;
93254 +       /* so that when we resume, we use any modified max rate */
93255 +       mmc->f_max = sd_max_clk;
93256 +
93257 +       return ret;
93258 +}
93259 +
93260 +int glamo_mci_resume(struct platform_device *dev)
93261 +{
93262 +       struct mmc_host *mmc = platform_get_drvdata(dev);
93263 +       struct glamo_mci_host   *host = mmc_priv(mmc);
93264 +       int ret;
93265 +
93266 +       sd_idleclk = 1;
93267 +
93268 +       glamo_engine_enable(host->pdata->pglamo, GLAMO_ENGINE_MMC);
93269 +       glamo_mci_reset(host);
93270 +
93271 +       host->suspending--;
93272 +
93273 +       ret = mmc_resume_host(mmc);
93274 +
93275 +       /* put sd_idleclk back to pre-suspend state */
93276 +       sd_idleclk = suspend_sd_idleclk;
93277 +
93278 +       return ret;
93279 +}
93280 +EXPORT_SYMBOL_GPL(glamo_mci_resume);
93281 +
93282 +#else /* CONFIG_PM */
93283 +#define glamo_mci_suspend NULL
93284 +#define glamo_mci_resume NULL
93285 +#endif /* CONFIG_PM */
93286 +
93287 +
93288 +static struct platform_driver glamo_mci_driver =
93289 +{
93290 +       .driver.name    = "glamo-mci",
93291 +       .probe          = glamo_mci_probe,
93292 +       .remove         = glamo_mci_remove,
93293 +       .suspend        = glamo_mci_suspend,
93294 +       .resume         = glamo_mci_resume,
93295 +};
93296 +
93297 +static int __init glamo_mci_init(void)
93298 +{
93299 +       spin_lock_init(&clock_lock);
93300 +       platform_driver_register(&glamo_mci_driver);
93301 +       return 0;
93302 +}
93303 +
93304 +static void __exit glamo_mci_exit(void)
93305 +{
93306 +       platform_driver_unregister(&glamo_mci_driver);
93307 +}
93308 +
93309 +module_init(glamo_mci_init);
93310 +module_exit(glamo_mci_exit);
93311 +
93312 +MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
93313 +MODULE_LICENSE("GPL");
93314 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
93315 Index: linux-2.6.28/drivers/mfd/glamo/glamo-mci.h
93316 ===================================================================
93317 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
93318 +++ linux-2.6.28/drivers/mfd/glamo/glamo-mci.h  2009-01-02 00:01:56.000000000 +0100
93319 @@ -0,0 +1,83 @@
93320 +/*
93321 + *  linux/drivers/mmc/host/glamo-mmc.h - GLAMO MCI driver
93322 + *
93323 + *  Copyright (C) 2007-2008 Openmoko, Inc, Andy Green <andy@openmoko.com>
93324 + *   based on S3C MMC driver -->
93325 + *  Copyright (C) 2004-2006 Thomas Kleffel, All Rights Reserved.
93326 + *
93327 + * This program is free software; you can redistribute it and/or modify
93328 + * it under the terms of the GNU General Public License version 2 as
93329 + * published by the Free Software Foundation.
93330 + */
93331 +
93332 +#include <linux/regulator/consumer.h>
93333 +
93334 +enum glamo_mci_waitfor {
93335 +       COMPLETION_NONE,
93336 +       COMPLETION_FINALIZE,
93337 +       COMPLETION_CMDSENT,
93338 +       COMPLETION_RSPFIN,
93339 +       COMPLETION_XFERFINISH,
93340 +       COMPLETION_XFERFINISH_RSPFIN,
93341 +};
93342 +
93343 +struct glamo_mci_host {
93344 +       struct platform_device  *pdev;
93345 +       struct glamo_mci_pdata  *pdata;
93346 +       struct mmc_host         *mmc;
93347 +       struct resource         *mem;
93348 +       struct resource         *mem_data;
93349 +       struct clk              *clk;
93350 +       void __iomem            *base;
93351 +       u16 __iomem             *base_data;
93352 +       int                     irq;
93353 +       int                     irq_cd;
93354 +       int                     dma;
93355 +       int                     data_max_size;
93356 +
93357 +       int                     suspending;
93358 +
93359 +       int                     power_mode_current;
93360 +       unsigned int            vdd_current;
93361 +
93362 +       unsigned long           clk_rate;
93363 +       unsigned long           clk_div;
93364 +       unsigned long           real_rate;
93365 +       u8                      prescaler;
93366 +
93367 +       int                     force_slow_during_powerup;
93368 +
93369 +       unsigned                sdiimsk;
93370 +       int                     dodma;
93371 +
93372 +       volatile int            dmatogo;
93373 +
93374 +       struct mmc_request      *mrq;
93375 +       int                     cmd_is_stop;
93376 +
93377 +       spinlock_t              complete_lock;
93378 +       volatile enum glamo_mci_waitfor
93379 +                               complete_what;
93380 +
93381 +       volatile int            dma_complete;
93382 +
93383 +       volatile u32            pio_sgptr;
93384 +       volatile u32            pio_words;
93385 +       volatile u32            pio_count;
93386 +       volatile u16            *pio_ptr;
93387 +#define XFER_NONE 0
93388 +#define XFER_READ 1
93389 +#define XFER_WRITE 2
93390 +       volatile u32            pio_active;
93391 +
93392 +       int                     bus_width;
93393 +
93394 +       char                    dbgmsg_cmd[301];
93395 +       char                    dbgmsg_dat[301];
93396 +       volatile char           *status;
93397 +
93398 +       unsigned int            ccnt, dcnt;
93399 +       struct tasklet_struct   pio_tasklet;
93400 +
93401 +       struct regulator        *regulator;
93402 +};
93403 Index: linux-2.6.28/drivers/mfd/glamo/glamo-regs.h
93404 ===================================================================
93405 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
93406 +++ linux-2.6.28/drivers/mfd/glamo/glamo-regs.h 2009-01-02 00:01:56.000000000 +0100
93407 @@ -0,0 +1,632 @@
93408 +#ifndef _GLAMO_REGS_H
93409 +#define _GLAMO_REGS_H
93410 +
93411 +/* Smedia Glamo 336x/337x driver
93412 + *
93413 + * (C) 2007 by Openmoko, Inc.
93414 + * Author: Harald Welte <laforge@openmoko.org>
93415 + * All rights reserved.
93416 + *
93417 + * This program is free software; you can redistribute it and/or
93418 + * modify it under the terms of the GNU General Public License as
93419 + * published by the Free Software Foundation; either version 2 of
93420 + * the License, or (at your option) any later version.
93421 + *
93422 + * This program is distributed in the hope that it will be useful,
93423 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
93424 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
93425 + * GNU General Public License for more details.
93426 + *
93427 + * You should have received a copy of the GNU General Public License
93428 + * along with this program; if not, write to the Free Software
93429 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
93430 + * MA 02111-1307 USA
93431 + */
93432 +
93433 +enum glamo_regster_offsets {
93434 +       GLAMO_REGOFS_GENERIC    = 0x0000,
93435 +       GLAMO_REGOFS_HOSTBUS    = 0x0200,
93436 +       GLAMO_REGOFS_MEMORY     = 0x0300,
93437 +       GLAMO_REGOFS_VIDCAP     = 0x0400,
93438 +       GLAMO_REGOFS_ISP        = 0x0500,
93439 +       GLAMO_REGOFS_JPEG       = 0x0800,
93440 +       GLAMO_REGOFS_MPEG       = 0x0c00,
93441 +       GLAMO_REGOFS_LCD        = 0x1100,
93442 +       GLAMO_REGOFS_MMC        = 0x1400,
93443 +       GLAMO_REGOFS_MPROC0     = 0x1500,
93444 +       GLAMO_REGOFS_MPROC1     = 0x1580,
93445 +       GLAMO_REGOFS_CMDQUEUE   = 0x1600,
93446 +       GLAMO_REGOFS_RISC       = 0x1680,
93447 +       GLAMO_REGOFS_2D         = 0x1700,
93448 +       GLAMO_REGOFS_3D         = 0x1b00,
93449 +       GLAMO_REGOFS_END        = 0x2400,
93450 +};
93451 +
93452 +
93453 +enum glamo_register_generic {
93454 +       GLAMO_REG_GCONF1        = 0x0000,
93455 +       GLAMO_REG_GCONF2        = 0x0002,
93456 +#define        GLAMO_REG_DEVICE_ID     GLAMO_REG_GCONF2
93457 +       GLAMO_REG_GCONF3        = 0x0004,
93458 +#define        GLAMO_REG_REVISION_ID   GLAMO_REG_GCONF3
93459 +       GLAMO_REG_IRQ_GEN1      = 0x0006,
93460 +#define GLAMO_REG_IRQ_ENABLE   GLAMO_REG_IRQ_GEN1
93461 +       GLAMO_REG_IRQ_GEN2      = 0x0008,
93462 +#define GLAMO_REG_IRQ_SET      GLAMO_REG_IRQ_GEN2
93463 +       GLAMO_REG_IRQ_GEN3      = 0x000a,
93464 +#define GLAMO_REG_IRQ_CLEAR    GLAMO_REG_IRQ_GEN3
93465 +       GLAMO_REG_IRQ_GEN4      = 0x000c,
93466 +#define GLAMO_REG_IRQ_STATUS   GLAMO_REG_IRQ_GEN4
93467 +       GLAMO_REG_CLOCK_HOST    = 0x0010,
93468 +       GLAMO_REG_CLOCK_MEMORY  = 0x0012,
93469 +       GLAMO_REG_CLOCK_LCD     = 0x0014,
93470 +       GLAMO_REG_CLOCK_MMC     = 0x0016,
93471 +       GLAMO_REG_CLOCK_ISP     = 0x0018,
93472 +       GLAMO_REG_CLOCK_JPEG    = 0x001a,
93473 +       GLAMO_REG_CLOCK_3D      = 0x001c,
93474 +       GLAMO_REG_CLOCK_2D      = 0x001e,
93475 +       GLAMO_REG_CLOCK_RISC1   = 0x0020,       /* 3365 only? */
93476 +       GLAMO_REG_CLOCK_RISC2   = 0x0022,       /* 3365 only? */
93477 +       GLAMO_REG_CLOCK_MPEG    = 0x0024,
93478 +       GLAMO_REG_CLOCK_MPROC   = 0x0026,
93479 +
93480 +       GLAMO_REG_CLOCK_GEN5_1  = 0x0030,
93481 +       GLAMO_REG_CLOCK_GEN5_2  = 0x0032,
93482 +       GLAMO_REG_CLOCK_GEN6    = 0x0034,
93483 +       GLAMO_REG_CLOCK_GEN7    = 0x0036,
93484 +       GLAMO_REG_CLOCK_GEN8    = 0x0038,
93485 +       GLAMO_REG_CLOCK_GEN9    = 0x003a,
93486 +       GLAMO_REG_CLOCK_GEN10   = 0x003c,
93487 +       GLAMO_REG_CLOCK_GEN11   = 0x003e,
93488 +       GLAMO_REG_PLL_GEN1      = 0x0040,
93489 +       GLAMO_REG_PLL_GEN2      = 0x0042,
93490 +       GLAMO_REG_PLL_GEN3      = 0x0044,
93491 +       GLAMO_REG_PLL_GEN4      = 0x0046,
93492 +       GLAMO_REG_PLL_GEN5      = 0x0048,
93493 +       GLAMO_REG_GPIO_GEN1     = 0x0050,
93494 +       GLAMO_REG_GPIO_GEN2     = 0x0052,
93495 +       GLAMO_REG_GPIO_GEN3     = 0x0054,
93496 +       GLAMO_REG_GPIO_GEN4     = 0x0056,
93497 +       GLAMO_REG_GPIO_GEN5     = 0x0058,
93498 +       GLAMO_REG_GPIO_GEN6     = 0x005a,
93499 +       GLAMO_REG_GPIO_GEN7     = 0x005c,
93500 +       GLAMO_REG_GPIO_GEN8     = 0x005e,
93501 +       GLAMO_REG_GPIO_GEN9     = 0x0060,
93502 +       GLAMO_REG_GPIO_GEN10    = 0x0062,
93503 +       GLAMO_REG_DFT_GEN1      = 0x0070,
93504 +       GLAMO_REG_DFT_GEN2      = 0x0072,
93505 +       GLAMO_REG_DFT_GEN3      = 0x0074,
93506 +       GLAMO_REG_DFT_GEN4      = 0x0076,
93507 +
93508 +       GLAMO_REG_DFT_GEN5      = 0x01e0,
93509 +       GLAMO_REG_DFT_GEN6      = 0x01f0,
93510 +};
93511 +
93512 +#define GLAMO_REG_HOSTBUS(x)   (GLAMO_REGOFS_HOSTBUS-2+(x*2))
93513 +
93514 +#define REG_MEM(x)             (GLAMO_REGOFS_MEMORY+(x))
93515 +#define GLAMO_REG_MEM_TIMING(x)        (GLAMO_REG_MEM_TIMING1-2+(x*2))
93516 +
93517 +enum glamo_register_mem {
93518 +       GLAMO_REG_MEM_TYPE      = REG_MEM(0x00),
93519 +       GLAMO_REG_MEM_GEN       = REG_MEM(0x02),
93520 +       GLAMO_REG_MEM_TIMING1   = REG_MEM(0x04),
93521 +       GLAMO_REG_MEM_TIMING2   = REG_MEM(0x06),
93522 +       GLAMO_REG_MEM_TIMING3   = REG_MEM(0x08),
93523 +       GLAMO_REG_MEM_TIMING4   = REG_MEM(0x0a),
93524 +       GLAMO_REG_MEM_TIMING5   = REG_MEM(0x0c),
93525 +       GLAMO_REG_MEM_TIMING6   = REG_MEM(0x0e),
93526 +       GLAMO_REG_MEM_TIMING7   = REG_MEM(0x10),
93527 +       GLAMO_REG_MEM_TIMING8   = REG_MEM(0x12),
93528 +       GLAMO_REG_MEM_TIMING9   = REG_MEM(0x14),
93529 +       GLAMO_REG_MEM_TIMING10  = REG_MEM(0x16),
93530 +       GLAMO_REG_MEM_TIMING11  = REG_MEM(0x18),
93531 +       GLAMO_REG_MEM_POWER1    = REG_MEM(0x1a),
93532 +       GLAMO_REG_MEM_POWER2    = REG_MEM(0x1c),
93533 +       GLAMO_REG_MEM_LCD_BUF1  = REG_MEM(0x1e),
93534 +       GLAMO_REG_MEM_LCD_BUF2  = REG_MEM(0x20),
93535 +       GLAMO_REG_MEM_LCD_BUF3  = REG_MEM(0x22),
93536 +       GLAMO_REG_MEM_LCD_BUF4  = REG_MEM(0x24),
93537 +       GLAMO_REG_MEM_BIST1     = REG_MEM(0x26),
93538 +       GLAMO_REG_MEM_BIST2     = REG_MEM(0x28),
93539 +       GLAMO_REG_MEM_BIST3     = REG_MEM(0x2a),
93540 +       GLAMO_REG_MEM_BIST4     = REG_MEM(0x2c),
93541 +       GLAMO_REG_MEM_BIST5     = REG_MEM(0x2e),
93542 +       GLAMO_REG_MEM_MAH1      = REG_MEM(0x30),
93543 +       GLAMO_REG_MEM_MAH2      = REG_MEM(0x32),
93544 +       GLAMO_REG_MEM_DRAM1     = REG_MEM(0x34),
93545 +       GLAMO_REG_MEM_DRAM2     = REG_MEM(0x36),
93546 +       GLAMO_REG_MEM_CRC       = REG_MEM(0x38),
93547 +};
93548 +
93549 +#define GLAMO_MEM_TYPE_MASK    0x03
93550 +
93551 +enum glamo_reg_mem_dram1 {
93552 +       /* b0 - b10 == refresh period, 1 -> 2048 clocks */
93553 +       GLAMO_MEM_DRAM1_EN_GATE_CLK     = (1 << 11),
93554 +       GLAMO_MEM_DRAM1_SELF_REFRESH    = (1 << 12),
93555 +       GLAMO_MEM_DRAM1_EN_GATE_CKE     = (1 << 13),
93556 +       GLAMO_MEM_DRAM1_EN_DRAM_REFRESH = (1 << 14),
93557 +       GLAMO_MEM_DRAM1_EN_MODEREG_SET  = (1 << 15),
93558 +};
93559 +
93560 +enum glamo_reg_mem_dram2 {
93561 +       GLAMO_MEM_DRAM2_DEEP_PWRDOWN    = (1 << 12),
93562 +};
93563 +
93564 +enum glamo_irq_index {
93565 +       GLAMO_IRQIDX_HOSTBUS    = 0,
93566 +       GLAMO_IRQIDX_JPEG       = 1,
93567 +       GLAMO_IRQIDX_MPEG       = 2,
93568 +       GLAMO_IRQIDX_MPROC1     = 3,
93569 +       GLAMO_IRQIDX_MPROC0     = 4,
93570 +       GLAMO_IRQIDX_CMDQUEUE   = 5,
93571 +       GLAMO_IRQIDX_2D         = 6,
93572 +       GLAMO_IRQIDX_MMC        = 7,
93573 +       GLAMO_IRQIDX_RISC       = 8,
93574 +};
93575 +
93576 +enum glamo_irq {
93577 +       GLAMO_IRQ_HOSTBUS       = (1 << GLAMO_IRQIDX_HOSTBUS),
93578 +       GLAMO_IRQ_JPEG          = (1 << GLAMO_IRQIDX_JPEG),
93579 +       GLAMO_IRQ_MPEG          = (1 << GLAMO_IRQIDX_MPEG),
93580 +       GLAMO_IRQ_MPROC1        = (1 << GLAMO_IRQIDX_MPROC1),
93581 +       GLAMO_IRQ_MPROC0        = (1 << GLAMO_IRQIDX_MPROC0),
93582 +       GLAMO_IRQ_CMDQUEUE      = (1 << GLAMO_IRQIDX_CMDQUEUE),
93583 +       GLAMO_IRQ_2D            = (1 << GLAMO_IRQIDX_2D),
93584 +       GLAMO_IRQ_MMC           = (1 << GLAMO_IRQIDX_MMC),
93585 +       GLAMO_IRQ_RISC          = (1 << GLAMO_IRQIDX_RISC),
93586 +};
93587 +
93588 +enum glamo_reg_clock_host {
93589 +       GLAMO_CLOCK_HOST_DG_BCLK        = 0x0001,
93590 +       GLAMO_CLOCK_HOST_DG_M0CLK       = 0x0004,
93591 +       GLAMO_CLOCK_HOST_RESET          = 0x1000,
93592 +};
93593 +
93594 +enum glamo_reg_clock_mem {
93595 +       GLAMO_CLOCK_MEM_DG_M1CLK        = 0x0001,
93596 +       GLAMO_CLOCK_MEM_EN_M1CLK        = 0x0002,
93597 +       GLAMO_CLOCK_MEM_DG_MOCACLK      = 0x0004,
93598 +       GLAMO_CLOCK_MEM_EN_MOCACLK      = 0x0008,
93599 +       GLAMO_CLOCK_MEM_RESET           = 0x1000,
93600 +       GLAMO_CLOCK_MOCA_RESET          = 0x2000,
93601 +};
93602 +
93603 +enum glamo_reg_clock_lcd {
93604 +       GLAMO_CLOCK_LCD_DG_DCLK         = 0x0001,
93605 +       GLAMO_CLOCK_LCD_EN_DCLK         = 0x0002,
93606 +       GLAMO_CLOCK_LCD_DG_DMCLK        = 0x0004,
93607 +       GLAMO_CLOCK_LCD_EN_DMCLK        = 0x0008,
93608 +       //
93609 +       GLAMO_CLOCK_LCD_EN_DHCLK        = 0x0020,
93610 +       GLAMO_CLOCK_LCD_DG_M5CLK        = 0x0040,
93611 +       GLAMO_CLOCK_LCD_EN_M5CLK        = 0x0080,
93612 +       GLAMO_CLOCK_LCD_RESET           = 0x1000,
93613 +};
93614 +
93615 +enum glamo_reg_clock_mmc {
93616 +       GLAMO_CLOCK_MMC_DG_TCLK         = 0x0001,
93617 +       GLAMO_CLOCK_MMC_EN_TCLK         = 0x0002,
93618 +       GLAMO_CLOCK_MMC_DG_M9CLK        = 0x0004,
93619 +       GLAMO_CLOCK_MMC_EN_M9CLK        = 0x0008,
93620 +       GLAMO_CLOCK_MMC_RESET           = 0x1000,
93621 +};
93622 +
93623 +enum glamo_reg_basic_mmc {
93624 +       /* set to disable CRC error rejection */
93625 +       GLAMO_BASIC_MMC_DISABLE_CRC     = 0x0001,
93626 +       /* enable completion interrupt */
93627 +       GLAMO_BASIC_MMC_EN_COMPL_INT    = 0x0002,
93628 +       /* stop MMC clock while enforced idle waiting for data from card */
93629 +       GLAMO_BASIC_MMC_NO_CLK_RD_WAIT  = 0x0004,
93630 +       /* 0 = 1-bit bus to card, 1 = use 4-bit bus (has to be negotiated) */
93631 +       GLAMO_BASIC_MMC_EN_4BIT_DATA    = 0x0008,
93632 +       /* enable 75K pullups on D3..D0 */
93633 +       GLAMO_BASIC_MMC_EN_DATA_PUPS    = 0x0010,
93634 +       /* enable 75K pullup on CMD */
93635 +       GLAMO_BASIC_MMC_EN_CMD_PUP      = 0x0020,
93636 +       /* IO drive strength 00=weak -> 11=strongest */
93637 +       GLAMO_BASIC_MMC_EN_DR_STR0      = 0x0040,
93638 +       GLAMO_BASIC_MMC_EN_DR_STR1      = 0x0080,
93639 +       /* TCLK delay stage A, 0000 = 500ps --> 1111 = 8ns */
93640 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA0   = 0x0100,
93641 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA1   = 0x0200,
93642 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA2   = 0x0400,
93643 +       GLAMO_BASIC_MMC_EN_TCLK_DLYA3   = 0x0800,
93644 +       /* TCLK delay stage B (cumulative), 0000 = 500ps --> 1111 = 8ns */
93645 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB0   = 0x1000,
93646 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB1   = 0x2000,
93647 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB2   = 0x4000,
93648 +       GLAMO_BASIC_MMC_EN_TCLK_DLYB3   = 0x8000,
93649 +};
93650 +
93651 +enum glamo_reg_stat1_mmc {
93652 +       /* command "counter" (really: toggle) */
93653 +       GLAMO_STAT1_MMC_CMD_CTR = 0x8000,
93654 +       /* engine is idle */
93655 +       GLAMO_STAT1_MMC_IDLE    = 0x4000,
93656 +       /* readback response is ready */
93657 +       GLAMO_STAT1_MMC_RB_RRDY = 0x0200,
93658 +       /* readback data is ready */
93659 +       GLAMO_STAT1_MMC_RB_DRDY = 0x0100,
93660 +       /* no response timeout */
93661 +       GLAMO_STAT1_MMC_RTOUT   = 0x0020,
93662 +       /* no data timeout */
93663 +       GLAMO_STAT1_MMC_DTOUT   = 0x0010,
93664 +       /* CRC error on block write */
93665 +       GLAMO_STAT1_MMC_BWERR   = 0x0004,
93666 +       /* CRC error on block read */
93667 +       GLAMO_STAT1_MMC_BRERR   = 0x0002
93668 +};
93669 +
93670 +enum glamo_reg_fire_mmc {
93671 +       /* command "counter" (really: toggle)
93672 +        * the STAT1 register reflects this so you can ensure you don't look
93673 +        * at status for previous command
93674 +        */
93675 +       GLAMO_FIRE_MMC_CMD_CTR  = 0x8000,
93676 +       /* sets kind of response expected */
93677 +       GLAMO_FIRE_MMC_RES_MASK = 0x0700,
93678 +       /* sets command type */
93679 +       GLAMO_FIRE_MMC_TYP_MASK = 0x00C0,
93680 +       /* sets command class */
93681 +       GLAMO_FIRE_MMC_CLS_MASK = 0x000F,
93682 +};
93683 +
93684 +enum glamo_fire_mmc_response_types {
93685 +       GLAMO_FIRE_MMC_RSPT_R1  = 0x0000,
93686 +       GLAMO_FIRE_MMC_RSPT_R1b = 0x0100,
93687 +       GLAMO_FIRE_MMC_RSPT_R2  = 0x0200,
93688 +       GLAMO_FIRE_MMC_RSPT_R3  = 0x0300,
93689 +       GLAMO_FIRE_MMC_RSPT_R4  = 0x0400,
93690 +       GLAMO_FIRE_MMC_RSPT_R5  = 0x0500,
93691 +};
93692 +
93693 +enum glamo_fire_mmc_command_types {
93694 +       /* broadcast, no response */
93695 +       GLAMO_FIRE_MMC_CMDT_BNR = 0x0000,
93696 +       /* broadcast, with response */
93697 +       GLAMO_FIRE_MMC_CMDT_BR  = 0x0040,
93698 +       /* addressed, no data */
93699 +       GLAMO_FIRE_MMC_CMDT_AND = 0x0080,
93700 +       /* addressed, with data */
93701 +       GLAMO_FIRE_MMC_CMDT_AD  = 0x00C0,
93702 +};
93703 +
93704 +enum glamo_fire_mmc_command_class {
93705 +       /* "Stream Read" */
93706 +       GLAMO_FIRE_MMC_CC_STRR  = 0x0000,
93707 +       /* Single Block Read */
93708 +       GLAMO_FIRE_MMC_CC_SBR   = 0x0001,
93709 +       /* Multiple Block Read With Stop */
93710 +       GLAMO_FIRE_MMC_CC_MBRS  = 0x0002,
93711 +       /* Multiple Block Read No Stop */
93712 +       GLAMO_FIRE_MMC_CC_MBRNS = 0x0003,
93713 +       /* RESERVED for "Stream Write" */
93714 +       GLAMO_FIRE_MMC_CC_STRW  = 0x0004,
93715 +       /* "Stream Write" */
93716 +       GLAMO_FIRE_MMC_CC_SBW   = 0x0005,
93717 +       /* RESERVED for Multiple Block Write With Stop */
93718 +       GLAMO_FIRE_MMC_CC_MBWS  = 0x0006,
93719 +       /* Multiple Block Write No Stop */
93720 +       GLAMO_FIRE_MMC_CC_MBWNS = 0x0007,
93721 +       /* STOP command */
93722 +       GLAMO_FIRE_MMC_CC_STOP  = 0x0008,
93723 +       /* Cancel on Running Command */
93724 +       GLAMO_FIRE_MMC_CC_CANCL = 0x0009,
93725 +       /* "Basic Command" */
93726 +       GLAMO_FIRE_MMC_CC_BASIC = 0x000a,
93727 +};
93728 +
93729 +/* these are offsets from the start of the MMC register region */
93730 +enum glamo_register_mmc {
93731 +       /* MMC command, b15..8 = cmd arg b7..0; b7..1 = CRC; b0 = end bit */
93732 +       GLAMO_REG_MMC_CMD_REG1  = 0x00,
93733 +       /* MMC command, b15..0 = cmd arg b23 .. 8 */
93734 +       GLAMO_REG_MMC_CMD_REG2  = 0x02,
93735 +       /* MMC command, b15=start, b14=transmission,
93736 +        * b13..8=cmd idx, b7..0=cmd arg b31..24
93737 +        */
93738 +       GLAMO_REG_MMC_CMD_REG3  = 0x04,
93739 +       GLAMO_REG_MMC_CMD_FIRE  = 0x06,
93740 +       GLAMO_REG_MMC_CMD_RSP1  = 0x10,
93741 +       GLAMO_REG_MMC_CMD_RSP2  = 0x12,
93742 +       GLAMO_REG_MMC_CMD_RSP3  = 0x14,
93743 +       GLAMO_REG_MMC_CMD_RSP4  = 0x16,
93744 +       GLAMO_REG_MMC_CMD_RSP5  = 0x18,
93745 +       GLAMO_REG_MMC_CMD_RSP6  = 0x1a,
93746 +       GLAMO_REG_MMC_CMD_RSP7  = 0x1c,
93747 +       GLAMO_REG_MMC_CMD_RSP8  = 0x1e,
93748 +       GLAMO_REG_MMC_RB_STAT1  = 0x20,
93749 +       GLAMO_REG_MMC_RB_BLKCNT = 0x22,
93750 +       GLAMO_REG_MMC_RB_BLKLEN = 0x24,
93751 +       GLAMO_REG_MMC_BASIC     = 0x30,
93752 +       GLAMO_REG_MMC_RDATADS1  = 0x34,
93753 +       GLAMO_REG_MMC_RDATADS2  = 0x36,
93754 +       GLAMO_REG_MMC_WDATADS1  = 0x38,
93755 +       GLAMO_REG_MMC_WDATADS2  = 0x3a,
93756 +       GLAMO_REG_MMC_DATBLKCNT = 0x3c,
93757 +       GLAMO_REG_MMC_DATBLKLEN = 0x3e,
93758 +       GLAMO_REG_MMC_TIMEOUT   = 0x40,
93759 +
93760 +};
93761 +
93762 +enum glamo_reg_clock_isp {
93763 +       GLAMO_CLOCK_ISP_DG_I1CLK        = 0x0001,
93764 +       GLAMO_CLOCK_ISP_EN_I1CLK        = 0x0002,
93765 +       GLAMO_CLOCK_ISP_DG_CCLK         = 0x0004,
93766 +       GLAMO_CLOCK_ISP_EN_CCLK         = 0x0008,
93767 +       //
93768 +       GLAMO_CLOCK_ISP_EN_SCLK         = 0x0020,
93769 +       GLAMO_CLOCK_ISP_DG_M2CLK        = 0x0040,
93770 +       GLAMO_CLOCK_ISP_EN_M2CLK        = 0x0080,
93771 +       GLAMO_CLOCK_ISP_DG_M15CLK       = 0x0100,
93772 +       GLAMO_CLOCK_ISP_EN_M15CLK       = 0x0200,
93773 +       GLAMO_CLOCK_ISP1_RESET          = 0x1000,
93774 +       GLAMO_CLOCK_ISP2_RESET          = 0x2000,
93775 +};
93776 +
93777 +enum glamo_reg_clock_jpeg {
93778 +       GLAMO_CLOCK_JPEG_DG_JCLK        = 0x0001,
93779 +       GLAMO_CLOCK_JPEG_EN_JCLK        = 0x0002,
93780 +       GLAMO_CLOCK_JPEG_DG_M3CLK       = 0x0004,
93781 +       GLAMO_CLOCK_JPEG_EN_M3CLK       = 0x0008,
93782 +       GLAMO_CLOCK_JPEG_RESET          = 0x1000,
93783 +};
93784 +
93785 +enum glamo_reg_clock_2d {
93786 +       GLAMO_CLOCK_2D_DG_GCLK          = 0x0001,
93787 +       GLAMO_CLOCK_2D_EN_GCLK          = 0x0002,
93788 +       GLAMO_CLOCK_2D_DG_M7CLK         = 0x0004,
93789 +       GLAMO_CLOCK_2D_EN_M7CLK         = 0x0008,
93790 +       GLAMO_CLOCK_2D_DG_M6CLK         = 0x0010,
93791 +       GLAMO_CLOCK_2D_EN_M6CLK         = 0x0020,
93792 +       GLAMO_CLOCK_2D_RESET            = 0x1000,
93793 +       GLAMO_CLOCK_2D_CQ_RESET         = 0x2000,
93794 +};
93795 +
93796 +enum glamo_reg_clock_3d {
93797 +       GLAMO_CLOCK_3D_DG_ECLK          = 0x0001,
93798 +       GLAMO_CLOCK_3D_EN_ECLK          = 0x0002,
93799 +       GLAMO_CLOCK_3D_DG_RCLK          = 0x0004,
93800 +       GLAMO_CLOCK_3D_EN_RCLK          = 0x0008,
93801 +       GLAMO_CLOCK_3D_DG_M8CLK         = 0x0010,
93802 +       GLAMO_CLOCK_3D_EN_M8CLK         = 0x0020,
93803 +       GLAMO_CLOCK_3D_BACK_RESET       = 0x1000,
93804 +       GLAMO_CLOCK_3D_FRONT_RESET      = 0x2000,
93805 +};
93806 +
93807 +enum glamo_reg_clock_mpeg {
93808 +       GLAMO_CLOCK_MPEG_DG_X0CLK       = 0x0001,
93809 +       GLAMO_CLOCK_MPEG_EN_X0CLK       = 0x0002,
93810 +       GLAMO_CLOCK_MPEG_DG_X1CLK       = 0x0004,
93811 +       GLAMO_CLOCK_MPEG_EN_X1CLK       = 0x0008,
93812 +       GLAMO_CLOCK_MPEG_DG_X2CLK       = 0x0010,
93813 +       GLAMO_CLOCK_MPEG_EN_X2CLK       = 0x0020,
93814 +       GLAMO_CLOCK_MPEG_DG_X3CLK       = 0x0040,
93815 +       GLAMO_CLOCK_MPEG_EN_X3CLK       = 0x0080,
93816 +       GLAMO_CLOCK_MPEG_DG_X4CLK       = 0x0100,
93817 +       GLAMO_CLOCK_MPEG_EN_X4CLK       = 0x0200,
93818 +       GLAMO_CLOCK_MPEG_DG_X6CLK       = 0x0400,
93819 +       GLAMO_CLOCK_MPEG_EN_X6CLK       = 0x0800,
93820 +       GLAMO_CLOCK_MPEG_ENC_RESET      = 0x1000,
93821 +       GLAMO_CLOCK_MPEG_DEC_RESET      = 0x2000,
93822 +};
93823 +
93824 +enum glamo_reg_clock51 {
93825 +       GLAMO_CLOCK_GEN51_EN_DIV_MCLK   = 0x0001,
93826 +       GLAMO_CLOCK_GEN51_EN_DIV_SCLK   = 0x0002,
93827 +       GLAMO_CLOCK_GEN51_EN_DIV_JCLK   = 0x0004,
93828 +       GLAMO_CLOCK_GEN51_EN_DIV_DCLK   = 0x0008,
93829 +       GLAMO_CLOCK_GEN51_EN_DIV_DMCLK  = 0x0010,
93830 +       GLAMO_CLOCK_GEN51_EN_DIV_DHCLK  = 0x0020,
93831 +       GLAMO_CLOCK_GEN51_EN_DIV_GCLK   = 0x0040,
93832 +       GLAMO_CLOCK_GEN51_EN_DIV_TCLK   = 0x0080,
93833 +       /* FIXME: higher bits */
93834 +};
93835 +
93836 +enum glamo_reg_hostbus2 {
93837 +       GLAMO_HOSTBUS2_MMIO_EN_ISP      = 0x0001,
93838 +       GLAMO_HOSTBUS2_MMIO_EN_JPEG     = 0x0002,
93839 +       GLAMO_HOSTBUS2_MMIO_EN_MPEG     = 0x0004,
93840 +       GLAMO_HOSTBUS2_MMIO_EN_LCD      = 0x0008,
93841 +       GLAMO_HOSTBUS2_MMIO_EN_MMC      = 0x0010,
93842 +       GLAMO_HOSTBUS2_MMIO_EN_MICROP0  = 0x0020,
93843 +       GLAMO_HOSTBUS2_MMIO_EN_MICROP1  = 0x0040,
93844 +       GLAMO_HOSTBUS2_MMIO_EN_CQ       = 0x0080,
93845 +       GLAMO_HOSTBUS2_MMIO_EN_RISC     = 0x0100,
93846 +       GLAMO_HOSTBUS2_MMIO_EN_2D       = 0x0200,
93847 +       GLAMO_HOSTBUS2_MMIO_EN_3D       = 0x0400,
93848 +};
93849 +
93850 +/* LCD Controller */
93851 +
93852 +#define REG_LCD(x)     (x)
93853 +enum glamo_reg_lcd {
93854 +       GLAMO_REG_LCD_MODE1             = REG_LCD(0x00),
93855 +       GLAMO_REG_LCD_MODE2             = REG_LCD(0x02),
93856 +       GLAMO_REG_LCD_MODE3             = REG_LCD(0x04),
93857 +       GLAMO_REG_LCD_WIDTH             = REG_LCD(0x06),
93858 +       GLAMO_REG_LCD_HEIGHT            = REG_LCD(0x08),
93859 +       GLAMO_REG_LCD_POLARITY          = REG_LCD(0x0a),
93860 +       GLAMO_REG_LCD_A_BASE1           = REG_LCD(0x0c),
93861 +       GLAMO_REG_LCD_A_BASE2           = REG_LCD(0x0e),
93862 +       GLAMO_REG_LCD_B_BASE1           = REG_LCD(0x10),
93863 +       GLAMO_REG_LCD_B_BASE2           = REG_LCD(0x12),
93864 +       GLAMO_REG_LCD_C_BASE1           = REG_LCD(0x14),
93865 +       GLAMO_REG_LCD_C_BASE2           = REG_LCD(0x16),
93866 +       GLAMO_REG_LCD_PITCH             = REG_LCD(0x18),
93867 +       /* RES */
93868 +       GLAMO_REG_LCD_HORIZ_TOTAL       = REG_LCD(0x1c),
93869 +       /* RES */
93870 +       GLAMO_REG_LCD_HORIZ_RETR_START  = REG_LCD(0x20),
93871 +       /* RES */
93872 +       GLAMO_REG_LCD_HORIZ_RETR_END    = REG_LCD(0x24),
93873 +       /* RES */
93874 +       GLAMO_REG_LCD_HORIZ_DISP_START  = REG_LCD(0x28),
93875 +       /* RES */
93876 +       GLAMO_REG_LCD_HORIZ_DISP_END    = REG_LCD(0x2c),
93877 +       /* RES */
93878 +       GLAMO_REG_LCD_VERT_TOTAL        = REG_LCD(0x30),
93879 +       /* RES */
93880 +       GLAMO_REG_LCD_VERT_RETR_START   = REG_LCD(0x34),
93881 +       /* RES */
93882 +       GLAMO_REG_LCD_VERT_RETR_END     = REG_LCD(0x38),
93883 +       /* RES */
93884 +       GLAMO_REG_LCD_VERT_DISP_START   = REG_LCD(0x3c),
93885 +       /* RES */
93886 +       GLAMO_REG_LCD_VERT_DISP_END     = REG_LCD(0x40),
93887 +       /* RES */
93888 +       GLAMO_REG_LCD_POL               = REG_LCD(0x44),
93889 +       GLAMO_REG_LCD_DATA_START        = REG_LCD(0x46),
93890 +       GLAMO_REG_LCD_FRATE_CONTRO      = REG_LCD(0x48),
93891 +       GLAMO_REG_LCD_DATA_CMD_HDR      = REG_LCD(0x4a),
93892 +       GLAMO_REG_LCD_SP_START          = REG_LCD(0x4c),
93893 +       GLAMO_REG_LCD_SP_END            = REG_LCD(0x4e),
93894 +       GLAMO_REG_LCD_CURSOR_BASE1      = REG_LCD(0x50),
93895 +       GLAMO_REG_LCD_CURSOR_BASE2      = REG_LCD(0x52),
93896 +       GLAMO_REG_LCD_CURSOR_PITCH      = REG_LCD(0x54),
93897 +       GLAMO_REG_LCD_CURSOR_X_SIZE     = REG_LCD(0x56),
93898 +       GLAMO_REG_LCD_CURSOR_Y_SIZE     = REG_LCD(0x58),
93899 +       GLAMO_REG_LCD_CURSOR_X_POS      = REG_LCD(0x5a),
93900 +       GLAMO_REG_LCD_CURSOR_Y_POS      = REG_LCD(0x5c),
93901 +       GLAMO_REG_LCD_CURSOR_PRESET     = REG_LCD(0x5e),
93902 +       GLAMO_REG_LCD_CURSOR_FG_COLOR   = REG_LCD(0x60),
93903 +       /* RES */
93904 +       GLAMO_REG_LCD_CURSOR_BG_COLOR   = REG_LCD(0x64),
93905 +       /* RES */
93906 +       GLAMO_REG_LCD_CURSOR_DST_COLOR  = REG_LCD(0x68),
93907 +       /* RES */
93908 +       GLAMO_REG_LCD_STATUS1           = REG_LCD(0x80),
93909 +       GLAMO_REG_LCD_STATUS2           = REG_LCD(0x82),
93910 +       GLAMO_REG_LCD_STATUS3           = REG_LCD(0x84),
93911 +       GLAMO_REG_LCD_STATUS4           = REG_LCD(0x86),
93912 +       /* RES */
93913 +       GLAMO_REG_LCD_COMMAND1          = REG_LCD(0xa0),
93914 +       GLAMO_REG_LCD_COMMAND2          = REG_LCD(0xa2),
93915 +       /* RES */
93916 +       GLAMO_REG_LCD_WFORM_DELAY1      = REG_LCD(0xb0),
93917 +       GLAMO_REG_LCD_WFORM_DELAY2      = REG_LCD(0xb2),
93918 +       /* RES */
93919 +       GLAMO_REG_LCD_GAMMA_CORR        = REG_LCD(0x100),
93920 +       /* RES */
93921 +       GLAMO_REG_LCD_GAMMA_R_ENTRY01   = REG_LCD(0x110),
93922 +       GLAMO_REG_LCD_GAMMA_R_ENTRY23   = REG_LCD(0x112),
93923 +       GLAMO_REG_LCD_GAMMA_R_ENTRY45   = REG_LCD(0x114),
93924 +       GLAMO_REG_LCD_GAMMA_R_ENTRY67   = REG_LCD(0x116),
93925 +       GLAMO_REG_LCD_GAMMA_R_ENTRY8    = REG_LCD(0x118),
93926 +       /* RES */
93927 +       GLAMO_REG_LCD_GAMMA_G_ENTRY01   = REG_LCD(0x130),
93928 +       GLAMO_REG_LCD_GAMMA_G_ENTRY23   = REG_LCD(0x132),
93929 +       GLAMO_REG_LCD_GAMMA_G_ENTRY45   = REG_LCD(0x134),
93930 +       GLAMO_REG_LCD_GAMMA_G_ENTRY67   = REG_LCD(0x136),
93931 +       GLAMO_REG_LCD_GAMMA_G_ENTRY8    = REG_LCD(0x138),
93932 +       /* RES */
93933 +       GLAMO_REG_LCD_GAMMA_B_ENTRY01   = REG_LCD(0x150),
93934 +       GLAMO_REG_LCD_GAMMA_B_ENTRY23   = REG_LCD(0x152),
93935 +       GLAMO_REG_LCD_GAMMA_B_ENTRY45   = REG_LCD(0x154),
93936 +       GLAMO_REG_LCD_GAMMA_B_ENTRY67   = REG_LCD(0x156),
93937 +       GLAMO_REG_LCD_GAMMA_B_ENTRY8    = REG_LCD(0x158),
93938 +       /* RES */
93939 +       GLAMO_REG_LCD_SRAM_DRIVING1     = REG_LCD(0x160),
93940 +       GLAMO_REG_LCD_SRAM_DRIVING2     = REG_LCD(0x162),
93941 +       GLAMO_REG_LCD_SRAM_DRIVING3     = REG_LCD(0x164),
93942 +};
93943 +
93944 +enum glamo_reg_lcd_mode1 {
93945 +       GLAMO_LCD_MODE1_PWRSAVE         = 0x0001,
93946 +       GLAMO_LCD_MODE1_PARTIAL_PRT     = 0x0002,
93947 +       GLAMO_LCD_MODE1_HWFLIP          = 0x0004,
93948 +       GLAMO_LCD_MODE1_LCD2            = 0x0008,
93949 +       /* RES */
93950 +       GLAMO_LCD_MODE1_PARTIAL_MODE    = 0x0020,
93951 +       GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040,
93952 +       GLAMO_LCD_MODE1_PARTIAL_ENABLE  = 0x0080,
93953 +       GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100,
93954 +       GLAMO_LCD_MODE1_HSYNC_HIGH_ACT  = 0x0200,
93955 +       GLAMO_LCD_MODE1_VSYNC_HIGH_ACT  = 0x0400,
93956 +       GLAMO_LCD_MODE1_HSYNC_FLIP      = 0x0800,
93957 +       GLAMO_LCD_MODE1_GAMMA_COR_EN    = 0x1000,
93958 +       GLAMO_LCD_MODE1_DITHER_EN       = 0x2000,
93959 +       GLAMO_LCD_MODE1_CURSOR_EN       = 0x4000,
93960 +       GLAMO_LCD_MODE1_ROTATE_EN       = 0x8000,
93961 +};
93962 +
93963 +enum glamo_reg_lcd_mode2 {
93964 +       GLAMO_LCD_MODE2_CRC_CHECK_EN    = 0x0001,
93965 +       GLAMO_LCD_MODE2_DCMD_PER_LINE   = 0x0002,
93966 +       GLAMO_LCD_MODE2_NOUSE_BDEF      = 0x0004,
93967 +       GLAMO_LCD_MODE2_OUT_POS_MODE    = 0x0008,
93968 +       GLAMO_LCD_MODE2_FRATE_CTRL_EN   = 0x0010,
93969 +       GLAMO_LCD_MODE2_SINGLE_BUFFER   = 0x0020,
93970 +       GLAMO_LCD_MODE2_SER_LSB_TO_MSB  = 0x0040,
93971 +       /* FIXME */
93972 +};
93973 +
93974 +enum glamo_reg_lcd_mode3 {
93975 +       /* LCD color source data format */
93976 +       GLAMO_LCD_SRC_RGB565            = 0x0000,
93977 +       GLAMO_LCD_SRC_ARGB1555          = 0x4000,
93978 +       GLAMO_LCD_SRC_ARGB4444          = 0x8000,
93979 +       /* interface type */
93980 +       GLAMO_LCD_MODE3_LCD             = 0x1000,
93981 +       GLAMO_LCD_MODE3_RGB             = 0x0800,
93982 +       GLAMO_LCD_MODE3_CPU             = 0x0000,
93983 +       /* mode */
93984 +       GLAMO_LCD_MODE3_RGB332          = 0x0000,
93985 +       GLAMO_LCD_MODE3_RGB444          = 0x0100,
93986 +       GLAMO_LCD_MODE3_RGB565          = 0x0200,
93987 +       GLAMO_LCD_MODE3_RGB666          = 0x0300,
93988 +       /* depth */
93989 +       GLAMO_LCD_MODE3_6BITS           = 0x0000,
93990 +       GLAMO_LCD_MODE3_8BITS           = 0x0010,
93991 +       GLAMO_LCD_MODE3_9BITS           = 0x0020,
93992 +       GLAMO_LCD_MODE3_16BITS          = 0x0030,
93993 +       GLAMO_LCD_MODE3_18BITS          = 0x0040,
93994 +};
93995 +
93996 +enum glamo_lcd_rot_mode {
93997 +        GLAMO_LCD_ROT_MODE_0            = 0x0000,
93998 +        GLAMO_LCD_ROT_MODE_180          = 0x2000,
93999 +        GLAMO_LCD_ROT_MODE_MIRROR       = 0x4000,
94000 +        GLAMO_LCD_ROT_MODE_FLIP         = 0x6000,
94001 +        GLAMO_LCD_ROT_MODE_90           = 0x8000,
94002 +        GLAMO_LCD_ROT_MODE_270          = 0xa000,
94003 +};
94004 +#define GLAMO_LCD_ROT_MODE_MASK         0xe000
94005 +
94006 +enum glamo_lcd_cmd_type {
94007 +       GLAMO_LCD_CMD_TYPE_DISP         = 0x0000,
94008 +       GLAMO_LCD_CMD_TYPE_PARALLEL     = 0x4000,
94009 +       GLAMO_LCD_CMD_TYPE_SERIAL       = 0x8000,
94010 +       GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
94011 +};
94012 +#define GLAMO_LCD_CMD_TYPE_MASK                0xc000
94013 +
94014 +enum glamo_lcd_cmds {
94015 +       GLAMO_LCD_CMD_DATA_DISP_FIRE    = 0x00,
94016 +       GLAMO_LCD_CMD_DATA_DISP_SYNC    = 0x01,         /* RGB only */
94017 +       /* switch to command mode, no display */
94018 +       GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,
94019 +       /* display until VSYNC, switch to command */
94020 +       GLAMO_LCD_CMD_DATA_FIRE_VSYNC   = 0x11,
94021 +       /* display until HSYNC, switch to command */
94022 +       GLAMO_LCD_CMD_DATA_FIRE_HSYNC   = 0x12,
94023 +       /* display until VSYNC, 1 black frame, VSYNC, switch to command */
94024 +       GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,
94025 +       /* don't care about display and switch to command */
94026 +       GLAMO_LCD_CMD_DATA_FIRE_FREE    = 0x14,         /* RGB only */
94027 +       /* don't care about display, keep data display but disable data,
94028 +        * and switch to command */
94029 +       GLAMO_LCD_CMD_DATA_FIRE_FREE_D  = 0x15,         /* RGB only */
94030 +};
94031 +
94032 +enum glamo_core_revisions {
94033 +       GLAMO_CORE_REV_A0               = 0x0000,
94034 +       GLAMO_CORE_REV_A1               = 0x0001,
94035 +       GLAMO_CORE_REV_A2               = 0x0002,
94036 +       GLAMO_CORE_REV_A3               = 0x0003,
94037 +};
94038 +
94039 +#endif /* _GLAMO_REGS_H */
94040 Index: linux-2.6.28/drivers/mfd/glamo/glamo-spi-gpio.c
94041 ===================================================================
94042 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
94043 +++ linux-2.6.28/drivers/mfd/glamo/glamo-spi-gpio.c     2009-01-02 00:01:56.000000000 +0100
94044 @@ -0,0 +1,288 @@
94045 +/*
94046 + * Copyright (C) 2007 Openmoko, Inc.
94047 + * Author: Harald Welte <laforge@openmoko.org>
94048 + *
94049 + * Smedia Glamo GPIO based SPI driver
94050 + *
94051 + * This program is free software; you can redistribute it and/or modify
94052 + * it under the terms of the GNU General Public License version 2 as
94053 + * published by the Free Software Foundation.
94054 + *
94055 + * This driver currently only implements a minimum subset of the hardware
94056 + * features, esp. those features that are required to drive the jbt6k74
94057 + * LCM controller asic in the TD028TTEC1 LCM.
94058 + *
94059 +*/
94060 +
94061 +#define DEBUG
94062 +
94063 +#include <linux/kernel.h>
94064 +#include <linux/init.h>
94065 +#include <linux/delay.h>
94066 +#include <linux/device.h>
94067 +#include <linux/spinlock.h>
94068 +#include <linux/workqueue.h>
94069 +#include <linux/platform_device.h>
94070 +
94071 +#include <linux/spi/spi.h>
94072 +#include <linux/spi/spi_bitbang.h>
94073 +#include <linux/spi/glamo.h>
94074 +
94075 +#include <linux/glamofb.h>
94076 +
94077 +#include <mach/hardware.h>
94078 +
94079 +#include "glamo-core.h"
94080 +#include "glamo-regs.h"
94081 +
94082 +struct glamo_spigpio {
94083 +       struct spi_bitbang              bitbang;
94084 +       struct spi_master               *master;
94085 +       struct glamo_spigpio_info       *info;
94086 +       struct glamo_core               *glamo;
94087 +};
94088 +
94089 +static inline struct glamo_spigpio *to_sg(struct spi_device *spi)
94090 +{
94091 +       return spi->controller_data;
94092 +}
94093 +
94094 +static inline void setsck(struct spi_device *dev, int on)
94095 +{
94096 +       struct glamo_spigpio *sg = to_sg(dev);
94097 +       glamo_gpio_setpin(sg->glamo, sg->info->pin_clk, on ? 1 : 0);
94098 +}
94099 +
94100 +static inline void setmosi(struct spi_device *dev, int on)
94101 +{
94102 +       struct glamo_spigpio *sg = to_sg(dev);
94103 +       glamo_gpio_setpin(sg->glamo, sg->info->pin_mosi, on ? 1 : 0);
94104 +}
94105 +
94106 +static inline u32 getmiso(struct spi_device *dev)
94107 +{
94108 +       struct glamo_spigpio *sg = to_sg(dev);
94109 +       if (sg->info->pin_miso)
94110 +               return glamo_gpio_getpin(sg->glamo, sg->info->pin_miso) ? 1 : 0;
94111 +       else
94112 +               return 0;
94113 +}
94114 +
94115 +#define spidelay(x) ndelay(x)
94116 +
94117 +#define EXPAND_BITBANG_TXRX
94118 +#include <linux/spi/spi_bitbang.h>
94119 +
94120 +static u32 glamo_spigpio_txrx_mode0(struct spi_device *spi,
94121 +                                   unsigned nsecs, u32 word, u8 bits)
94122 +{
94123 +       return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits);
94124 +}
94125 +
94126 +static u32 glamo_spigpio_txrx_mode1(struct spi_device *spi,
94127 +                                   unsigned nsecs, u32 word, u8 bits)
94128 +{
94129 +       return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits);
94130 +}
94131 +
94132 +static u32 glamo_spigpio_txrx_mode2(struct spi_device *spi,
94133 +                                   unsigned nsecs, u32 word, u8 bits)
94134 +{
94135 +       return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits);
94136 +}
94137 +
94138 +static u32 glamo_spigpio_txrx_mode3(struct spi_device *spi,
94139 +                                   unsigned nsecs, u32 word, u8 bits)
94140 +{
94141 +       return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits);
94142 +}
94143 +
94144 +
94145 +#if 0
94146 +static int glamo_spigpio_setupxfer(struct spi_device *spi,
94147 +                                  struct spi_transfer *t)
94148 +{
94149 +       struct glamo_spi *gs = to_sg(spi);
94150 +       unsigned int bpw;
94151 +
94152 +       bpw = t ? t->bits_per_word : spi->bits_per_word;
94153 +
94154 +       if (bpw != 9 && bpw != 8) {
94155 +               dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
94156 +               return -EINVAL;
94157 +       }
94158 +
94159 +       return 0;
94160 +}
94161 +#endif
94162 +
94163 +static void glamo_spigpio_chipsel(struct spi_device *spi, int value)
94164 +{
94165 +       struct glamo_spigpio *gs = to_sg(spi);
94166 +#if 0
94167 +       dev_dbg(&spi->dev, "chipsel %d: spi=%p, gs=%p, info=%p, handle=%p\n",
94168 +               value, spi, gs, gs->info, gs->info->glamo);
94169 +#endif
94170 +       glamo_gpio_setpin(gs->glamo, gs->info->pin_cs, value ? 0 : 1);
94171 +}
94172 +
94173 +
94174 +static int glamo_spigpio_probe(struct platform_device *pdev)
94175 +{
94176 +       struct spi_master *master;
94177 +       struct glamo_spigpio *sp;
94178 +       int ret;
94179 +       int i;
94180 +
94181 +       master = spi_alloc_master(&pdev->dev, sizeof(struct glamo_spigpio));
94182 +       if (master == NULL) {
94183 +               dev_err(&pdev->dev, "failed to allocate spi master\n");
94184 +               ret = -ENOMEM;
94185 +               goto err;
94186 +       }
94187 +
94188 +       sp = spi_master_get_devdata(master);
94189 +       platform_set_drvdata(pdev, sp);
94190 +       sp->info = pdev->dev.platform_data;
94191 +       if (!sp->info) {
94192 +               dev_err(&pdev->dev, "can't operate without platform data\n");
94193 +               ret = -EIO;
94194 +               goto err_no_pdev;
94195 +       }
94196 +
94197 +       master->num_chipselect = 1;
94198 +       master->bus_num = 2; /* FIXME: use dynamic number */
94199 +
94200 +       sp->master = spi_master_get(master);
94201 +       sp->glamo = sp->info->glamo;
94202 +
94203 +       sp->bitbang.master = sp->master;
94204 +       sp->bitbang.chipselect = glamo_spigpio_chipsel;
94205 +       sp->bitbang.txrx_word[SPI_MODE_0] = glamo_spigpio_txrx_mode0;
94206 +       sp->bitbang.txrx_word[SPI_MODE_1] = glamo_spigpio_txrx_mode1;
94207 +       sp->bitbang.txrx_word[SPI_MODE_2] = glamo_spigpio_txrx_mode2;
94208 +       sp->bitbang.txrx_word[SPI_MODE_3] = glamo_spigpio_txrx_mode3;
94209 +
94210 +       /* set state of spi pins */
94211 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_clk, 0);
94212 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_mosi, 0);
94213 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_cs, 1);
94214 +
94215 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_clk);
94216 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_mosi);
94217 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_cs);
94218 +       if (sp->info->pin_miso)
94219 +               glamo_gpio_cfgpin(sp->glamo, sp->info->pin_miso);
94220 +
94221 +       /* bring the LCM panel out of reset if it isn't already */
94222 +
94223 +       glamo_gpio_setpin(sp->glamo, GLAMO_GPIO4, 1);
94224 +       glamo_gpio_cfgpin(sp->glamo, GLAMO_GPIO4_OUTPUT);
94225 +       msleep(90);
94226 +
94227 +#if 0
94228 +       sp->dev = &pdev->dev;
94229 +
94230 +       sp->bitbang.setup_transfer = glamo_spi_setupxfer;
94231 +       sp->bitbang.txrx_bufs = glamo_spi_txrx;
94232 +       sp->bitbang.master->setup = glamo_spi_setup;
94233 +#endif
94234 +
94235 +       ret = spi_bitbang_start(&sp->bitbang);
94236 +       if (ret)
94237 +               goto err_no_bitbang;
94238 +
94239 +       /* register the chips to go with the board */
94240 +
94241 +       for (i = 0; i < sp->info->board_size; i++) {
94242 +               dev_info(&pdev->dev, "registering %p: %s\n",
94243 +                        &sp->info->board_info[i],
94244 +                        sp->info->board_info[i].modalias);
94245 +
94246 +               sp->info->board_info[i].controller_data = sp;
94247 +               spi_new_device(master, sp->info->board_info + i);
94248 +       }
94249 +
94250 +       return 0;
94251 +
94252 +err_no_bitbang:
94253 +       platform_set_drvdata(pdev, NULL);
94254 +err_no_pdev:
94255 +       spi_master_put(sp->bitbang.master);
94256 +err:
94257 +       return ret;
94258 +
94259 +}
94260 +
94261 +static int glamo_spigpio_remove(struct platform_device *pdev)
94262 +{
94263 +       struct glamo_spigpio *sp = platform_get_drvdata(pdev);
94264 +
94265 +       spi_bitbang_stop(&sp->bitbang);
94266 +       spi_master_put(sp->bitbang.master);
94267 +
94268 +       return 0;
94269 +}
94270 +
94271 +/*#define glamo_spigpio_suspend NULL
94272 +#define glamo_spigpio_resume NULL
94273 +*/
94274 +
94275 +
94276 +#ifdef CONFIG_PM
94277 +static int glamo_spigpio_suspend(struct platform_device *pdev, pm_message_t state)
94278 +{
94279 +       return 0;
94280 +}
94281 +
94282 +static int glamo_spigpio_resume(struct platform_device *pdev)
94283 +{
94284 +       struct glamo_spigpio *sp = platform_get_drvdata(pdev);
94285 +
94286 +       if (!sp)
94287 +               return 0;
94288 +
94289 +       /* set state of spi pins */
94290 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_clk, 0);
94291 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_mosi, 0);
94292 +       glamo_gpio_setpin(sp->glamo, sp->info->pin_cs, 1);
94293 +
94294 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_clk);
94295 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_mosi);
94296 +       glamo_gpio_cfgpin(sp->glamo, sp->info->pin_cs);
94297 +       if (sp->info->pin_miso)
94298 +               glamo_gpio_cfgpin(sp->glamo, sp->info->pin_miso);
94299 +
94300 +       return 0;
94301 +}
94302 +#endif
94303 +
94304 +static struct platform_driver glamo_spi_drv = {
94305 +       .probe          = glamo_spigpio_probe,
94306 +       .remove         = glamo_spigpio_remove,
94307 +#ifdef CONFIG_PM
94308 +       .suspend_late   = glamo_spigpio_suspend,
94309 +       .resume_early   = glamo_spigpio_resume,
94310 +#endif
94311 +       .driver         = {
94312 +               .name   = "glamo-spi-gpio",
94313 +               .owner  = THIS_MODULE,
94314 +       },
94315 +};
94316 +
94317 +static int __init glamo_spi_init(void)
94318 +{
94319 +       return platform_driver_register(&glamo_spi_drv);
94320 +}
94321 +
94322 +static void __exit glamo_spi_exit(void)
94323 +{
94324 +       platform_driver_unregister(&glamo_spi_drv);
94325 +}
94326 +
94327 +module_init(glamo_spi_init);
94328 +module_exit(glamo_spi_exit);
94329 +
94330 +MODULE_DESCRIPTION("Smedia Glamo 336x/337x LCM serial command SPI Driver");
94331 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>")
94332 +MODULE_LICENSE("GPL");
94333 Index: linux-2.6.28/drivers/mfd/glamo/Kconfig
94334 ===================================================================
94335 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
94336 +++ linux-2.6.28/drivers/mfd/glamo/Kconfig      2009-01-02 00:01:56.000000000 +0100
94337 @@ -0,0 +1,44 @@
94338 +config MFD_GLAMO
94339 +       bool "Smedia Glamo 336x/337x support"
94340 +       help
94341 +         This enables the core driver for the Smedia Glamo 336x/337x
94342 +         multi-function device.  It includes irq_chip demultiplex as
94343 +         well as clock / power management and GPIO support.
94344 +
94345 +config MFD_GLAMO_FB
94346 +       tristate "Smedia Glamo 336x/337x framebuffer support"
94347 +       depends on FB && MFD_GLAMO
94348 +       help
94349 +         Frame buffer driver for the LCD controller in the Smedia Glamo
94350 +         336x/337x.
94351 +
94352 +         This driver is also available as a module ( = code which can be
94353 +         inserted and removed from the running kernel whenever you want). The
94354 +         module will be called glamofb. If you want to compile it as a module,
94355 +         say M here and read <file:Documentation/modules.txt>.
94356 +
94357 +         If unsure, say N.
94358 +
94359 +config MFD_GLAMO_SPI_GPIO
94360 +       tristate "Glamo GPIO SPI bitbang support"
94361 +       depends on MFD_GLAMO
94362 +       help
94363 +         Enable a bitbanging SPI adapter driver for the Smedia Glamo.
94364 +
94365 +config MFD_GLAMO_SPI_FB
94366 +       tristate "Glamo LCM control channel SPI support"
94367 +       depends on MFD_GLAMO_FB
94368 +       help
94369 +         Enable a bitbanging SPI adapter driver for the Smedia Glamo LCM
94370 +        control channel.  This SPI interface is frequently used to
94371 +        interconnect the LCM control interface.
94372 +
94373 +config MFD_GLAMO_MCI
94374 +       tristate "Glamo S3C SD/MMC Card Interface support"
94375 +       depends on MFD_GLAMO && MMC
94376 +       help
94377 +         This selects a driver for the MCI interface found in
94378 +         the S-Media GLAMO chip, as used in Openmoko
94379 +         neo1973 GTA-02.
94380 +
94381 +         If unsure, say N.
94382 \ No newline at end of file
94383 Index: linux-2.6.28/drivers/mfd/glamo/Makefile
94384 ===================================================================
94385 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
94386 +++ linux-2.6.28/drivers/mfd/glamo/Makefile     2009-01-02 00:01:56.000000000 +0100
94387 @@ -0,0 +1,12 @@
94388 +#
94389 +# Makefile for the Smedia Glamo framebuffer driver
94390 +#
94391 +
94392 +obj-$(CONFIG_MFD_GLAMO)                        += glamo-core.o glamo-gpio.o
94393 +obj-$(CONFIG_MFD_GLAMO_SPI)            += glamo-spi.o
94394 +obj-$(CONFIG_MFD_GLAMO_SPI_GPIO)       += glamo-spi-gpio.o
94395 +
94396 +obj-$(CONFIG_MFD_GLAMO_FB)             += glamo-fb.o
94397 +obj-$(CONFIG_MFD_GLAMO_SPI_FB)         += glamo-lcm-spi.o
94398 +obj-$(CONFIG_MFD_GLAMO_MCI)            += glamo-mci.o
94399 +
94400 Index: linux-2.6.28/drivers/mfd/Kconfig
94401 ===================================================================
94402 --- linux-2.6.28.orig/drivers/mfd/Kconfig       2008-12-25 00:26:37.000000000 +0100
94403 +++ linux-2.6.28/drivers/mfd/Kconfig    2009-01-02 00:01:56.000000000 +0100
94404 @@ -153,6 +153,55 @@ config MFD_WM8350_I2C
94405           I2C as the control interface.  Additional options must be
94406           selected to enable support for the functionality of the chip.
94407
94408 +config MFD_PCF50633
94409 +       tristate "Support for NXP PCF50633"
94410 +       depends on I2C
94411 +       help
94412 +         Say yes here if you have NXP PCF50633 chip on your board.
94413 +         This core driver provides register access and IRQ handling
94414 +         facilities, and registers devices for the various functions
94415 +         so that function-specific drivers can bind to them.
94416 +
94417 +
94418 +config PCF50633_ADC
94419 +       tristate "Support for NXP PCF50633 ADC"
94420 +       depends on MFD_PCF50633
94421 +       help
94422 +        Say yes here if you want to include support for ADC in the
94423 +        NXP PCF50633 chip.
94424 +
94425 +config PCF50633_GPIO
94426 +       tristate "Support for NXP PCF50633 GPIO"
94427 +       depends on MFD_PCF50633
94428 +       help
94429 +        Say yes here if you want to include support GPIO for pins on
94430 +        the PCF50633 chip.
94431 +
94432 +config MFD_PCF50606
94433 +       tristate "Support for NXP PCF50606"
94434 +       depends on I2C
94435 +       help
94436 +         Say yes here if you have NXP PCF50606 chip on your board.
94437 +         This core driver provides register access and IRQ handling
94438 +         facilities, and registers devices for the various functions
94439 +         so that function-specific drivers can bind to them.
94440 +
94441 +config PCF50606_ADC
94442 +       tristate "Support for NXP PCF50606 ADC"
94443 +       depends on MFD_PCF50606
94444 +       help
94445 +        Say yes here if you want to include support for ADC in the
94446 +        NXP PCF50606 chip.
94447 +
94448 +config PCF50606_GPO
94449 +       tristate "Support for NXP PCF50606 GPO"
94450 +       depends on MFD_PCF50606
94451 +       help
94452 +        Say yes here if you want to include support GPO for pins on
94453 +        the PCF50606 chip.
94454 +
94455 +source "drivers/mfd/glamo/Kconfig"
94456 +
94457  endmenu
94458
94459  menu "Multimedia Capabilities Port drivers"
94460 Index: linux-2.6.28/drivers/mfd/Makefile
94461 ===================================================================
94462 --- linux-2.6.28.orig/drivers/mfd/Makefile      2008-12-25 00:26:37.000000000 +0100
94463 +++ linux-2.6.28/drivers/mfd/Makefile   2009-01-02 00:01:56.000000000 +0100
94464 @@ -4,6 +4,7 @@
94465
94466  obj-$(CONFIG_MFD_SM501)                += sm501.o
94467  obj-$(CONFIG_MFD_ASIC3)                += asic3.o
94468 +obj-$(CONFIG_MFD_GLAMO)                += glamo/
94469
94470  obj-$(CONFIG_HTC_EGPIO)                += htc-egpio.o
94471  obj-$(CONFIG_HTC_PASIC3)       += htc-pasic3.o
94472 @@ -31,4 +32,13 @@ obj-$(CONFIG_MCP_UCB1200)    += ucb1x00-ass
94473  endif
94474  obj-$(CONFIG_UCB1400_CORE)     += ucb1400_core.o
94475
94476 -obj-$(CONFIG_PMIC_DA903X)      += da903x.o
94477 \ No newline at end of file
94478 +obj-$(CONFIG_PMIC_DA903X)      += da903x.o
94479 +
94480 +obj-$(CONFIG_MFD_PCF50633)     += pcf50633-core.o
94481 +obj-$(CONFIG_PCF50633_ADC)     += pcf50633-adc.o
94482 +obj-$(CONFIG_PCF50633_GPIO)    += pcf50633-gpio.o
94483 +
94484 +obj-$(CONFIG_MFD_PCF50606)     += pcf50606-core.o
94485 +obj-$(CONFIG_PCF50606_ADC)     += pcf50606-adc.o
94486 +obj-$(CONFIG_PCF50606_GPO)     += pcf50606-gpo.o
94487 +
94488 Index: linux-2.6.28/drivers/mfd/pcf50606-adc.c
94489 ===================================================================
94490 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
94491 +++ linux-2.6.28/drivers/mfd/pcf50606-adc.c     2009-01-02 00:01:56.000000000 +0100
94492 @@ -0,0 +1,239 @@
94493 +/* Philips PCF50606 ADC Driver
94494 + *
94495 + * (C) 2006-2008 by Openmoko, Inc.
94496 + * Author: Balaji Rao <balajirrao@openmoko.org>
94497 + * All rights reserved.
94498 + *
94499 + * Broken down from monstrous PCF50606 driver mainly by
94500 + * Harald Welte, Andy Green and Werner Almesberger
94501 + *
94502 + * This program is free software; you can redistribute it and/or
94503 + * modify it under the terms of the GNU General Public License as
94504 + * published by the Free Software Foundation; either version 2 of
94505 + * the License, or (at your option) any later version.
94506 + *
94507 + * This program is distributed in the hope that it will be useful,
94508 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
94509 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
94510 + * GNU General Public License for more details.
94511 + *
94512 + * You should have received a copy of the GNU General Public License
94513 + * along with this program; if not, write to the Free Software
94514 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
94515 + * MA 02111-1307 USA
94516 + */
94517 +
94518 +#include <linux/mfd/pcf50606/core.h>
94519 +#include <linux/mfd/pcf50606/adc.h>
94520 +
94521 +struct pcf50606_adc_request {
94522 +       int mux;
94523 +       int avg;
94524 +       int result;
94525 +       void (*callback)(struct pcf50606 *, void *, int);
94526 +       void *callback_param;
94527 +
94528 +       /* Used in case of sync requests */
94529 +       struct completion completion;
94530 +
94531 +};
94532 +
94533 +static void adc_read_setup(struct pcf50606 *pcf,
94534 +                                int channel, int avg)
94535 +{
94536 +       channel &= PCF50606_ADCC2_ADCMUX_MASK;
94537 +
94538 +       /* start ADC conversion of selected channel */
94539 +       pcf50606_reg_write(pcf, PCF50606_REG_ADCC2, channel |
94540 +                   PCF50606_ADCC2_ADCSTART | PCF50606_ADCC2_RES_10BIT);
94541 +
94542 +}
94543 +
94544 +static void trigger_next_adc_job_if_any(struct pcf50606 *pcf)
94545 +{
94546 +       int head, tail;
94547 +
94548 +       mutex_lock(&pcf->adc.queue_mutex);
94549 +
94550 +       head = pcf->adc.queue_head;
94551 +       tail = pcf->adc.queue_tail;
94552 +
94553 +       if (!pcf->adc.queue[head])
94554 +               goto out;
94555 +
94556 +       adc_read_setup(pcf, pcf->adc.queue[head]->mux,
94557 +                               pcf->adc.queue[head]->avg);
94558 +out:
94559 +       mutex_unlock(&pcf->adc.queue_mutex);
94560 +}
94561 +
94562 +static int
94563 +adc_enqueue_request(struct pcf50606 *pcf, struct pcf50606_adc_request *req)
94564 +{
94565 +       int head, tail;
94566 +
94567 +       mutex_lock(&pcf->adc.queue_mutex);
94568 +       head = pcf->adc.queue_head;
94569 +       tail = pcf->adc.queue_tail;
94570 +
94571 +       if (pcf->adc.queue[tail]) {
94572 +               mutex_unlock(&pcf->adc.queue_mutex);
94573 +               return -EBUSY;
94574 +       }
94575 +
94576 +       pcf->adc.queue[tail] = req;
94577 +
94578 +       pcf->adc.queue_tail =
94579 +               (tail + 1) & (PCF50606_MAX_ADC_FIFO_DEPTH - 1);
94580 +
94581 +       mutex_unlock(&pcf->adc.queue_mutex);
94582 +
94583 +       trigger_next_adc_job_if_any(pcf);
94584 +
94585 +       return 0;
94586 +}
94587 +
94588 +static void
94589 +pcf50606_adc_sync_read_callback(struct pcf50606 *pcf, void *param, int result)
94590 +{
94591 +       struct pcf50606_adc_request *req;
94592 +
94593 +       /*We know here that the passed param is an adc_request object */
94594 +       req = (struct pcf50606_adc_request *)param;
94595 +
94596 +       req->result = result;
94597 +       complete(&req->completion);
94598 +}
94599 +
94600 +int pcf50606_adc_sync_read(struct pcf50606 *pcf, int mux, int avg)
94601 +{
94602 +
94603 +       struct pcf50606_adc_request *req;
94604 +       int result;
94605 +
94606 +       /* req is freed when the result is ready, in pcf50606_work*/
94607 +       req = kzalloc(sizeof(*req), GFP_KERNEL);
94608 +       if (!req)
94609 +               return -ENOMEM;
94610 +
94611 +       req->mux = mux;
94612 +       req->avg = avg;
94613 +       req->callback =  pcf50606_adc_sync_read_callback;
94614 +       req->callback_param = req;
94615 +       init_completion(&req->completion);
94616 +
94617 +       adc_enqueue_request(pcf, req);
94618 +
94619 +       wait_for_completion(&req->completion);
94620 +       result = req->result;
94621 +
94622 +       return result;
94623 +}
94624 +EXPORT_SYMBOL_GPL(pcf50606_adc_sync_read);
94625 +
94626 +int pcf50606_adc_async_read(struct pcf50606 *pcf, int mux, int avg,
94627 +                            void (*callback)(struct pcf50606 *, void *, int),
94628 +                            void *callback_param)
94629 +{
94630 +       struct pcf50606_adc_request *req;
94631 +
94632 +       /* req is freed when the result is ready, in pcf50606_work*/
94633 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
94634 +       if (!req)
94635 +               return -ENOMEM;
94636 +
94637 +       req->mux = mux;
94638 +       req->avg = avg;
94639 +       req->callback = callback;
94640 +       req->callback_param = callback_param;
94641 +
94642 +       adc_enqueue_request(pcf, req);
94643 +
94644 +       return 0;
94645 +}
94646 +EXPORT_SYMBOL_GPL(pcf50606_adc_async_read);
94647 +
94648 +static int adc_result(struct pcf50606 *pcf)
94649 +{
94650 +       u16 ret = (pcf50606_reg_read(pcf, PCF50606_REG_ADCS1) << 2) |
94651 +                       (pcf50606_reg_read(pcf, PCF50606_REG_ADCS2) & 0x03);
94652 +
94653 +       dev_info(pcf->dev, "adc result = %d\n", ret);
94654 +
94655 +       return ret;
94656 +}
94657 +
94658 +static void pcf50606_adc_irq(struct pcf50606 *pcf, int irq, void *unused)
94659 +{
94660 +       struct pcf50606_adc_request *req;
94661 +       int head;
94662 +
94663 +       mutex_lock(&pcf->adc.queue_mutex);
94664 +       head = pcf->adc.queue_head;
94665 +
94666 +       req = pcf->adc.queue[head];
94667 +       if (!req) {
94668 +               dev_err(pcf->dev, "ADC queue empty\n");
94669 +               mutex_unlock(&pcf->adc.queue_mutex);
94670 +               return;
94671 +       }
94672 +       pcf->adc.queue[head] = NULL;
94673 +       pcf->adc.queue_head = (head + 1) &
94674 +                                     (PCF50606_MAX_ADC_FIFO_DEPTH - 1);
94675 +
94676 +       mutex_unlock(&pcf->adc.queue_mutex);
94677 +       req->callback(pcf, req->callback_param, adc_result(pcf));
94678 +
94679 +       kfree(req);
94680 +
94681 +       trigger_next_adc_job_if_any(pcf);
94682 +}
94683 +
94684 +int __init pcf50606_adc_probe(struct platform_device *pdev)
94685 +{
94686 +       struct pcf50606 *pcf;
94687 +
94688 +       pcf = platform_get_drvdata(pdev);
94689 +
94690 +       /* Set up IRQ handlers */
94691 +       pcf->irq_handler[PCF50606_IRQ_ADCRDY].handler = pcf50606_adc_irq;
94692 +
94693 +       mutex_init(&pcf->adc.queue_mutex);
94694 +       return 0;
94695 +}
94696 +
94697 +static int __devexit pcf50606_adc_remove(struct platform_device *pdev)
94698 +{
94699 +       struct pcf50606 *pcf;
94700 +
94701 +       pcf = platform_get_drvdata(pdev);
94702 +       pcf->irq_handler[PCF50606_IRQ_ADCRDY].handler = NULL;
94703 +
94704 +       return 0;
94705 +}
94706 +
94707 +struct platform_driver pcf50606_adc_driver = {
94708 +       .driver = {
94709 +               .name = "pcf50606-adc",
94710 +       },
94711 +       .probe = pcf50606_adc_probe,
94712 +       .remove = __devexit_p(pcf50606_adc_remove),
94713 +};
94714 +
94715 +static int __init pcf50606_adc_init(void)
94716 +{
94717 +               return platform_driver_register(&pcf50606_adc_driver);
94718 +}
94719 +module_init(pcf50606_adc_init);
94720 +
94721 +static void __exit pcf50606_adc_exit(void)
94722 +{
94723 +               platform_driver_unregister(&pcf50606_adc_driver);
94724 +}
94725 +module_exit(pcf50606_adc_exit);
94726 +
94727 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
94728 +MODULE_DESCRIPTION("PCF50606 adc driver");
94729 +MODULE_LICENSE("GPL");
94730 +MODULE_ALIAS("platform:pcf50606-adc");
94731 +
94732 Index: linux-2.6.28/drivers/mfd/pcf50606-core.c
94733 ===================================================================
94734 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
94735 +++ linux-2.6.28/drivers/mfd/pcf50606-core.c    2009-01-02 00:01:56.000000000 +0100
94736 @@ -0,0 +1,580 @@
94737 +/* Philips PCF50606 Power Management Unit (PMU) driver
94738 + *
94739 + * (C) 2006-2008 by Openmoko, Inc.
94740 + * Author: Harald Welte <laforge@openmoko.org>
94741 + *         Matt Hsu <matt@openmoko.org>
94742 + * All rights reserved.
94743 + *
94744 + * This program is free software; you can redistribute it and/or
94745 + * modify it under the terms of the GNU General Public License as
94746 + * published by the Free Software Foundation; either version 2 of
94747 + * the License, or (at your option) any later version.
94748 + *
94749 + * This program is distributed in the hope that it will be useful,
94750 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
94751 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
94752 + * GNU General Public License for more details.
94753 + *
94754 + * You should have received a copy of the GNU General Public License
94755 + * along with this program; if not, write to the Free Software
94756 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
94757 + * MA 02111-1307 USA
94758 + *
94759 + */
94760 +#include <linux/i2c.h>
94761 +#include <linux/irq.h>
94762 +#include <linux/device.h>
94763 +#include <linux/module.h>
94764 +#include <linux/reboot.h>
94765 +#include <linux/interrupt.h>
94766 +#include <linux/workqueue.h>
94767 +#include <linux/platform_device.h>
94768 +
94769 +#include <linux/mfd/pcf50606/core.h>
94770 +
94771 +/* Read a block of upto 32 regs  */
94772 +int pcf50606_read_block(struct pcf50606 *pcf , u8 reg,
94773 +                                       int nr_regs, u8 *data)
94774 +{
94775 +       int ret;
94776 +
94777 +       mutex_lock(&pcf->lock);
94778 +       ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
94779 +                                                       nr_regs, data);
94780 +       mutex_unlock(&pcf->lock);
94781 +
94782 +       return ret;
94783 +}
94784 +EXPORT_SYMBOL_GPL(pcf50606_read_block);
94785 +
94786 +/* Write a block of upto 32 regs  */
94787 +int pcf50606_write_block(struct pcf50606 *pcf , u8 reg,
94788 +                                       int nr_regs, u8 *data)
94789 +{
94790 +       int ret;
94791 +
94792 +       mutex_lock(&pcf->lock);
94793 +       ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
94794 +                                                       nr_regs, data);
94795 +       mutex_unlock(&pcf->lock);
94796 +
94797 +       return ret;
94798 +}
94799 +EXPORT_SYMBOL_GPL(pcf50606_write_block);
94800 +
94801 +u8 pcf50606_reg_read(struct pcf50606 *pcf, u8 reg)
94802 +{
94803 +       int ret;
94804 +
94805 +       mutex_lock(&pcf->lock);
94806 +       ret = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94807 +       mutex_unlock(&pcf->lock);
94808 +
94809 +       return ret;
94810 +}
94811 +EXPORT_SYMBOL_GPL(pcf50606_reg_read);
94812 +
94813 +int pcf50606_reg_write(struct pcf50606 *pcf, u8 reg, u8 val)
94814 +{
94815 +       int ret;
94816 +       mutex_lock(&pcf->lock);
94817 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, val);
94818 +       mutex_unlock(&pcf->lock);
94819 +
94820 +       return ret;
94821 +}
94822 +EXPORT_SYMBOL_GPL(pcf50606_reg_write);
94823 +
94824 +int pcf50606_reg_set_bit_mask(struct pcf50606 *pcf, u8 reg, u8 mask, u8 val)
94825 +{
94826 +       int ret;
94827 +       u8 tmp;
94828 +
94829 +       val &= mask;
94830 +
94831 +       mutex_lock(&pcf->lock);
94832 +
94833 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94834 +       tmp &= ~mask;
94835 +       tmp |= val;
94836 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94837 +
94838 +       mutex_unlock(&pcf->lock);
94839 +
94840 +       return ret;
94841 +}
94842 +EXPORT_SYMBOL_GPL(pcf50606_reg_set_bit_mask);
94843 +
94844 +int pcf50606_reg_clear_bits(struct pcf50606 *pcf, u8 reg, u8 val)
94845 +{
94846 +       int ret;
94847 +       u8 tmp;
94848 +
94849 +       mutex_lock(&pcf->lock);
94850 +
94851 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94852 +       tmp &= ~val;
94853 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94854 +
94855 +       mutex_unlock(&pcf->lock);
94856 +
94857 +       return ret;
94858 +}
94859 +EXPORT_SYMBOL_GPL(pcf50606_reg_clear_bits);
94860 +
94861 +static ssize_t show_resume_reason(struct device *dev,
94862 +                               struct device_attribute *attr, char *buf)
94863 +{
94864 +       struct pcf50606 *pcf = dev_get_drvdata(dev);
94865 +       int n;
94866 +
94867 +       n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
94868 +                               pcf->resume_reason[0],
94869 +                               pcf->resume_reason[1],
94870 +                               pcf->resume_reason[2],
94871 +                               pcf->resume_reason[3],
94872 +                               pcf->resume_reason[4]);
94873 +
94874 +       return n;
94875 +}
94876 +static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
94877 +
94878 +static struct attribute *pcf_sysfs_entries[] = {
94879 +       &dev_attr_resume_reason.attr,
94880 +       NULL,
94881 +};
94882 +
94883 +static struct attribute_group pcf_attr_group = {
94884 +       .name   = NULL,                 /* put in device directory */
94885 +       .attrs  = pcf_sysfs_entries,
94886 +};
94887 +
94888 +
94889 +static int pcf50606_irq_mask_set(struct pcf50606 *pcf, int irq, int mask)
94890 +{
94891 +       u8 reg, bits, tmp;
94892 +       int ret = 0, idx;
94893 +
94894 +       idx = irq / 8;
94895 +       reg =  PCF50606_REG_INT1M + idx;
94896 +       bits = 1 << (irq % 8);
94897 +
94898 +       mutex_lock(&pcf->lock);
94899 +
94900 +       if (mask) {
94901 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94902 +               tmp |= bits;
94903 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94904 +
94905 +               pcf->mask_regs[idx] &= ~bits;
94906 +               pcf->mask_regs[idx] |= bits;
94907 +       } else {
94908 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
94909 +               tmp &= ~bits;
94910 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
94911 +
94912 +               pcf->mask_regs[idx] &= ~bits;
94913 +       }
94914 +
94915 +       mutex_unlock(&pcf->lock);
94916 +
94917 +       return 0;
94918 +}
94919 +
94920 +int pcf50606_irq_mask(struct pcf50606 *pcf, int irq)
94921 +{
94922 +       dev_info(pcf->dev, "Masking IRQ %d\n", irq);
94923 +
94924 +       return pcf50606_irq_mask_set(pcf, irq, 1);
94925 +}
94926 +EXPORT_SYMBOL_GPL(pcf50606_irq_mask);
94927 +
94928 +int pcf50606_irq_unmask(struct pcf50606 *pcf, int irq)
94929 +{
94930 +       dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
94931 +
94932 +       return pcf50606_irq_mask_set(pcf, irq, 0);
94933 +}
94934 +EXPORT_SYMBOL_GPL(pcf50606_irq_unmask);
94935 +
94936 +int pcf50606_irq_mask_get(struct pcf50606 *pcf, int irq)
94937 +{
94938 +       u8 reg, bits;
94939 +
94940 +       reg =  (irq / 8);
94941 +       bits = (1 << (irq % 8));
94942 +
94943 +       return pcf->mask_regs[reg] & bits;
94944 +}
94945 +EXPORT_SYMBOL_GPL(pcf50606_irq_mask_get);
94946 +
94947 +static void pcf50606_irq_call_handler(struct pcf50606 *pcf,
94948 +                                       int irq)
94949 +{
94950 +       if (pcf->irq_handler[irq].handler)
94951 +               pcf->irq_handler[irq].handler(pcf, irq,
94952 +                                       pcf->irq_handler[irq].data);
94953 +}
94954 +
94955 +#define PCF50606_ONKEY1S_TIMEOUT 8
94956 +
94957 +static void pcf50606_irq_worker(struct work_struct *work)
94958 +{
94959 +       struct pcf50606 *pcf;
94960 +       int ret, i, j;
94961 +       u8 pcf_int[3], chgstat;
94962 +
94963 +       pcf = container_of(work, struct pcf50606, irq_work);
94964 +
94965 +       /* Read the 3 INT regs in one transaction */
94966 +       ret = pcf50606_read_block(pcf, PCF50606_REG_INT1,
94967 +                                               sizeof(pcf_int), pcf_int);
94968 +       if (ret != sizeof(pcf_int)) {
94969 +               dev_info(pcf->dev, "Error reading INT registers\n");
94970 +
94971 +               /* We don't have an option but to retry. Because if
94972 +                * we don't, there won't be another interrupt edge.
94973 +                */
94974 +               goto reschedule;
94975 +       }
94976 +
94977 +       /* We immediately read the usb and adapter status. We thus make sure
94978 +        * only of CHGINS/CHGRM handlers are called */
94979 +       if (pcf_int[1] & (PCF50606_INT2_CHGINS | PCF50606_INT2_CHGRM)) {
94980 +               chgstat = pcf50606_reg_read(pcf, PCF50606_REG_MBCS1);
94981 +               if (chgstat & (0x1 << 4))
94982 +                       pcf_int[1] &= ~(1 << PCF50606_INT2_CHGRM);
94983 +               else
94984 +                       pcf_int[1] &= ~(1 << PCF50606_INT2_CHGINS);
94985 +       }
94986 +
94987 +       dev_info(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x",
94988 +                               pcf_int[0], pcf_int[1], pcf_int[2]);
94989 +
94990 +       /* Some revisions of the chip don't have a 8s standby mode on
94991 +        * ONKEY1S press. We try to manually do it in such cases. */
94992 +
94993 +       if (pcf_int[0] & PCF50606_INT1_SECOND && pcf->onkey1s_held) {
94994 +               dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
94995 +                                                       pcf->onkey1s_held);
94996 +               if (pcf->onkey1s_held++ == PCF50606_ONKEY1S_TIMEOUT)
94997 +                       if (pcf->pdata->force_shutdown)
94998 +                               pcf->pdata->force_shutdown(pcf);
94999 +       }
95000 +
95001 +       if (pcf_int[0] & PCF50606_INT1_ONKEY1S) {
95002 +               dev_info(pcf->dev, "ONKEY1S held\n");
95003 +               pcf->onkey1s_held = 1 ;
95004 +
95005 +               /* Unmask IRQ_SECOND */
95006 +               pcf50606_reg_clear_bits(pcf, PCF50606_REG_INT1M,
95007 +                                               PCF50606_INT1_SECOND);
95008 +
95009 +               /* Unmask IRQ_ONKEYF */
95010 +               pcf50606_reg_clear_bits(pcf, PCF50606_REG_INT1M,
95011 +                                               PCF50606_INT1_ONKEYF);
95012 +       }
95013 +
95014 +       if ((pcf_int[0] & PCF50606_INT1_ONKEYR) && pcf->onkey1s_held) {
95015 +               pcf->onkey1s_held = 0;
95016 +
95017 +               /* Mask SECOND and ONKEYF interrupts */
95018 +               if (pcf->mask_regs[0] & PCF50606_INT1_SECOND)
95019 +                       pcf50606_reg_set_bit_mask(pcf,
95020 +                                       PCF50606_REG_INT1M,
95021 +                                       PCF50606_INT1_SECOND,
95022 +                                       PCF50606_INT1_SECOND);
95023 +
95024 +               if (pcf->mask_regs[0] & PCF50606_INT1_ONKEYF)
95025 +                       pcf50606_reg_set_bit_mask(pcf,
95026 +                                       PCF50606_REG_INT1M,
95027 +                                       PCF50606_INT1_ONKEYF,
95028 +                                       PCF50606_INT1_ONKEYF);
95029 +       }
95030 +
95031 +       /* Have we just resumed ? */
95032 +       if (pcf->is_suspended) {
95033 +
95034 +               pcf->is_suspended = 0;
95035 +
95036 +               /* Set the resume reason filtering out non resumers */
95037 +               for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
95038 +                       pcf->resume_reason[i] = pcf_int[i] &
95039 +                                               pcf->pdata->resumers[i];
95040 +
95041 +               /* Make sure we don't pass on any input events to
95042 +                * userspace now */
95043 +               pcf_int[0] &= ~(PCF50606_INT1_SECOND | PCF50606_INT1_ALARM);
95044 +       }
95045 +
95046 +       /* Unset masked interrupts */
95047 +       for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
95048 +               pcf_int[i] &= ~pcf->mask_regs[i];
95049 +
95050 +       for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
95051 +               for (j = 0; j < 8 ; j++)
95052 +                       if (pcf_int[i] & (1 << j))
95053 +                               pcf50606_irq_call_handler(pcf, (i * 8) + j);
95054 +
95055 +       put_device(pcf->dev);
95056 +
95057 +       return;
95058 +reschedule:
95059 +       schedule_work(&pcf->irq_work);
95060 +
95061 +       /* Don't put_device here. Will be used when we are rescheduled */
95062 +
95063 +       return;
95064 +}
95065 +
95066 +static irqreturn_t pcf50606_irq(int irq, void *data)
95067 +{
95068 +       struct pcf50606 *pcf = data;
95069 +
95070 +       get_device(pcf->dev);
95071 +       schedule_work(&pcf->irq_work);
95072 +
95073 +       return IRQ_HANDLED;
95074 +}
95075 +
95076 +static void
95077 +pcf50606_client_dev_register(struct pcf50606 *pcf, const char *name,
95078 +                                               struct platform_device **pdev)
95079 +{
95080 +       int ret;
95081 +
95082 +       *pdev = platform_device_alloc(name, -1);
95083 +
95084 +       if (!pdev) {
95085 +               dev_err(pcf->dev, "Falied to allocate %s\n", name);
95086 +               return;
95087 +       }
95088 +
95089 +       (*pdev)->dev.parent = pcf->dev;
95090 +       platform_set_drvdata(*pdev, pcf);
95091 +
95092 +       ret = platform_device_add(*pdev);
95093 +       if (ret != 0) {
95094 +               dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
95095 +               platform_device_put(*pdev);
95096 +               *pdev = NULL;
95097 +       }
95098 +}
95099 +
95100 +#ifdef CONFIG_PM
95101 +static int pcf50606_suspend(struct device *dev, pm_message_t state)
95102 +{
95103 +       struct pcf50606 *pcf;
95104 +       int ret, i;
95105 +       u8 res[3];
95106 +
95107 +       pcf = dev_get_drvdata(dev);
95108 +
95109 +       /* Make sure our interrupt handlers are not called
95110 +        * henceforth */
95111 +       disable_irq(pcf->irq);
95112 +
95113 +       /* Make sure that an IRQ worker has quit */
95114 +       cancel_work_sync(&pcf->irq_work);
95115 +
95116 +       /* Save the masks */
95117 +       ret = pcf50606_read_block(pcf, PCF50606_REG_INT1M,
95118 +                               ARRAY_SIZE(pcf->suspend_irq_masks),
95119 +                                               pcf->suspend_irq_masks);
95120 +       if (ret < 0)
95121 +               dev_err(pcf->dev, "error saving irq masks\n");
95122 +
95123 +       /* Set interrupt masks. So that only those sources we want to wake
95124 +        * us up can
95125 +        */
95126 +       for (i = 0; i < ARRAY_SIZE(res); i++)
95127 +               res[i] = ~pcf->pdata->resumers[i];
95128 +
95129 +       pcf50606_write_block(pcf, PCF50606_REG_INT1M,
95130 +                                       ARRAY_SIZE(res), &res[0]);
95131 +
95132 +       pcf->is_suspended = 1;
95133 +
95134 +       return 0;
95135 +}
95136 +
95137 +static int pcf50606_resume(struct device *dev)
95138 +{
95139 +       struct pcf50606 *pcf;
95140 +
95141 +       pcf = dev_get_drvdata(dev);
95142 +
95143 +       /* Write the saved mask registers */
95144 +       pcf50606_write_block(pcf, PCF50606_REG_INT1M,
95145 +                       ARRAY_SIZE(pcf->suspend_irq_masks),
95146 +                                       pcf->suspend_irq_masks);
95147 +
95148 +       /* Clear any pending interrupts and set resume reason if any */
95149 +       pcf50606_irq_worker(&pcf->irq_work);
95150 +
95151 +       enable_irq(pcf->irq);
95152 +
95153 +       return 0;
95154 +}
95155 +#else
95156 +#define pcf50606_suspend NULL
95157 +#define pcf50606_resume NULL
95158 +#endif
95159 +
95160 +static int pcf50606_probe(struct i2c_client *client,
95161 +                               const struct i2c_device_id *ids)
95162 +{
95163 +       struct pcf50606 *pcf;
95164 +       struct pcf50606_platform_data *pdata;
95165 +       int i, ret = 0;
95166 +       int version, variant;
95167 +       u8 mbcs1;
95168 +
95169 +       pdata = client->dev.platform_data;
95170 +
95171 +       pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
95172 +       if (!pcf)
95173 +               return -ENOMEM;
95174 +
95175 +       pcf->pdata = pdata;
95176 +       pdata->pcf = pcf;
95177 +
95178 +       mutex_init(&pcf->lock);
95179 +
95180 +       i2c_set_clientdata(client, pcf);
95181 +       pcf->dev = &client->dev;
95182 +       pcf->i2c_client = client;
95183 +
95184 +       INIT_WORK(&pcf->irq_work, pcf50606_irq_worker);
95185 +
95186 +       version = pcf50606_reg_read(pcf, 0);
95187 +       if (version < 0) {
95188 +               dev_err(pcf->dev, "Unable to probe pcf50606\n");
95189 +               kfree(pcf);
95190 +               return -ENODEV;
95191 +       }
95192 +
95193 +       variant = pcf50606_reg_read(pcf, 1);
95194 +       if (version < 0) {
95195 +               dev_err(pcf->dev, "Unable to probe pcf50606\n");
95196 +               kfree(pcf);
95197 +               return -ENODEV;
95198 +       }
95199 +
95200 +       dev_info(pcf->dev, "Probed device version %d variant %d\n",
95201 +                                                       version, variant);
95202 +
95203 +       /* Enable all inteerupts except RTC SECOND */
95204 +       pcf->mask_regs[0] = 0x80;
95205 +       pcf50606_reg_write(pcf, PCF50606_REG_INT1M, 0x80);
95206 +
95207 +       pcf50606_reg_write(pcf, PCF50606_REG_INT2M, 0x00);
95208 +       pcf50606_reg_write(pcf, PCF50606_REG_INT3M, 0x00);
95209 +
95210 +       pcf50606_client_dev_register(pcf, "pcf50606-input",
95211 +                                               &pcf->input.pdev);
95212 +       pcf50606_client_dev_register(pcf, "pcf50606-rtc",
95213 +                                               &pcf->rtc.pdev);
95214 +       pcf50606_client_dev_register(pcf, "pcf50606-mbc",
95215 +                                               &pcf->mbc.pdev);
95216 +       pcf50606_client_dev_register(pcf, "pcf50606-adc",
95217 +                                               &pcf->adc.pdev);
95218 +       pcf50606_client_dev_register(pcf, "pcf50606-wdt",
95219 +                                               &pcf->wdt.pdev);
95220 +       for (i = 0; i < PCF50606_NUM_REGULATORS; i++) {
95221 +               struct platform_device *pdev;
95222 +
95223 +               pdev = platform_device_alloc("pcf50606-regltr", i);
95224 +               if (!pdev) {
95225 +                       dev_err(pcf->dev, "Cannot create regulator\n");
95226 +                       continue;
95227 +               }
95228 +
95229 +               pdev->dev.parent = pcf->dev;
95230 +               pdev->dev.platform_data = &pdata->reg_init_data[i];
95231 +               pdev->dev.driver_data = pcf;
95232 +               pcf->pmic.pdev[i] = pdev;
95233 +
95234 +               platform_device_add(pdev);
95235 +       }
95236 +
95237 +       pcf->irq = client->irq;
95238 +
95239 +       if (client->irq) {
95240 +               ret = request_irq(client->irq, pcf50606_irq,
95241 +                               IRQF_TRIGGER_FALLING, "pcf50606", pcf);
95242 +
95243 +               if (ret) {
95244 +                       dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
95245 +                       goto err;
95246 +               }
95247 +       } else {
95248 +               dev_err(pcf->dev, "No IRQ configured\n");
95249 +               goto err;
95250 +       }
95251 +
95252 +       if (enable_irq_wake(client->irq) < 0)
95253 +               dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
95254 +                       "in this hardware revision", client->irq);
95255 +
95256 +       /* Cold Intialization */
95257 +       mbcs1 = pcf50606_reg_read(pcf, PCF50606_REG_MBCS1);
95258 +
95259 +       if (mbcs1 & (0x01 << 4)) /* Charger present ? */
95260 +               pcf50606_irq_call_handler(pcf, PCF50606_IRQ_CHGINS);
95261 +
95262 +       ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
95263 +       if (ret)
95264 +               dev_err(pcf->dev, "error creating sysfs entries\n");
95265 +
95266 +       if (pdata->probe_done)
95267 +               pdata->probe_done(pcf);
95268 +
95269 +       return 0;
95270 +
95271 +err:
95272 +       kfree(pcf);
95273 +       return ret;
95274 +}
95275 +
95276 +static int pcf50606_remove(struct i2c_client *client)
95277 +{
95278 +       struct pcf50606 *pcf = i2c_get_clientdata(client);
95279 +
95280 +       free_irq(pcf->irq, pcf);
95281 +       kfree(pcf);
95282 +
95283 +       return 0;
95284 +}
95285 +
95286 +static struct i2c_device_id pcf50606_id_table[] = {
95287 +       {"pcf50606", 0x73},
95288 +};
95289 +
95290 +static struct i2c_driver pcf50606_driver = {
95291 +       .driver = {
95292 +               .name   = "pcf50606",
95293 +               .suspend = pcf50606_suspend,
95294 +               .resume = pcf50606_resume,
95295 +       },
95296 +       .id_table = pcf50606_id_table,
95297 +       .probe = pcf50606_probe,
95298 +       .remove = pcf50606_remove,
95299 +};
95300 +
95301 +static int __init pcf50606_init(void)
95302 +{
95303 +       return i2c_add_driver(&pcf50606_driver);
95304 +}
95305 +
95306 +static void pcf50606_exit(void)
95307 +{
95308 +       i2c_del_driver(&pcf50606_driver);
95309 +}
95310 +
95311 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50606 PMU");
95312 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
95313 +MODULE_LICENSE("GPL");
95314 +
95315 +module_init(pcf50606_init);
95316 +module_exit(pcf50606_exit);
95317 Index: linux-2.6.28/drivers/mfd/pcf50606-gpo.c
95318 ===================================================================
95319 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
95320 +++ linux-2.6.28/drivers/mfd/pcf50606-gpo.c     2009-01-02 00:01:56.000000000 +0100
95321 @@ -0,0 +1,128 @@
95322 +/* Philips PCF50606 GPO Driver
95323 + *
95324 + * (C) 2006-2008 by Openmoko, Inc.
95325 + * Author: Balaji Rao <balajirrao@openmoko.org>
95326 + * All rights reserved.
95327 + *
95328 + * Broken down from monstrous PCF50606 driver mainly by
95329 + * Harald Welte, Andy Green and Werner Almesberger
95330 + *
95331 + * This program is free software; you can redistribute it and/or
95332 + * modify it under the terms of the GNU General Public License as
95333 + * published by the Free Software Foundation; either version 2 of
95334 + * the License, or (at your option) any later version.
95335 + *
95336 + * This program is distributed in the hope that it will be useful,
95337 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
95338 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
95339 + * GNU General Public License for more details.
95340 + *
95341 + * You should have received a copy of the GNU General Public License
95342 + * along with this program; if not, write to the Free Software
95343 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
95344 + * MA 02111-1307 USA
95345 + */
95346 +
95347 +#include <linux/mfd/pcf50606/core.h>
95348 +#include <linux/mfd/pcf50606/gpo.h>
95349 +#include <linux/mfd/pcf50606/pmic.h>
95350 +
95351 +void pcf50606_gpo_set_active(struct pcf50606 *pcf, int gpo, int val)
95352 +{
95353 +       u8 reg, value, mask;
95354 +
95355 +       reg = gpo;
95356 +       value = val;
95357 +       mask = 0x07;
95358 +
95359 +       if (gpo == PCF50606_GPO2) {
95360 +               value = val << 4;
95361 +               mask = 0x07 << 4;
95362 +       }
95363 +       pcf50606_reg_set_bit_mask(pcf, reg, mask, value);
95364 +}
95365 +EXPORT_SYMBOL_GPL(pcf50606_gpo_set_active);
95366 +
95367 +int pcf50606_gpo_get_active(struct pcf50606 *pcf, int gpo)
95368 +{
95369 +       u8 reg, value, shift = 0;
95370 +
95371 +       reg = gpo;
95372 +       if (gpo == PCF50606_GPO2)
95373 +               shift = 4;
95374 +
95375 +       value = pcf50606_reg_read(pcf, reg);
95376 +
95377 +       return (value >> shift) & 0x07;
95378 +}
95379 +EXPORT_SYMBOL_GPL(pcf50606_gpo_get_active);
95380 +
95381 +void pcf50606_gpo_set_standby(struct pcf50606 *pcf, int gpo, int val)
95382 +{
95383 +       u8 reg;
95384 +
95385 +       if (gpo == PCF50606_GPO1 || gpo == PCF50606_GPO2) {
95386 +               dev_err(pcf->dev, "Can't set standby settings for GPO[12]n");
95387 +               return;
95388 +       }
95389 +
95390 +       reg = gpo;
95391 +
95392 +       pcf50606_reg_set_bit_mask(pcf, gpo, 0x07 << 3, val);
95393 +}
95394 +EXPORT_SYMBOL_GPL(pcf50606_gpo_set_standby);
95395 +
95396 +int pcf50606_gpo_get_standby(struct pcf50606 *pcf, int gpo)
95397 +{
95398 +       u8 reg, value;
95399 +
95400 +       if (gpo == PCF50606_GPO1 || gpo == PCF50606_GPO2) {
95401 +               dev_err(pcf->dev, "Can't get standby settings for GPO[12]n");
95402 +               return -EINVAL;
95403 +       }
95404 +
95405 +       reg = gpo;
95406 +       value = pcf50606_reg_read(pcf, reg);
95407 +
95408 +       return (value >> 3) & 0x07;
95409 +}
95410 +EXPORT_SYMBOL_GPL(pcf50606_gpo_get_standby);
95411 +
95412 +void pcf50606_gpo_invert_set(struct pcf50606 *pcf, int gpo, int invert)
95413 +{
95414 +       u8 reg, value, mask;
95415 +
95416 +       reg = gpo;
95417 +       value = !!invert << 6;
95418 +       mask = 0x01 << 6;
95419 +
95420 +       if (gpo == PCF50606_GPO1) {
95421 +               mask = 0x01 << 4;
95422 +               value = !!invert << 4;
95423 +       }
95424 +       else if (gpo == PCF50606_GPO2) {
95425 +               mask = 0x01 << 7;
95426 +               value = !!invert << 7;
95427 +       }
95428 +
95429 +       pcf50606_reg_set_bit_mask(pcf, reg, mask, value);
95430 +}
95431 +EXPORT_SYMBOL_GPL(pcf50606_gpo_invert_set);
95432 +
95433 +int pcf50606_gpo_invert_get(struct pcf50606 *pcf, int gpo)
95434 +{
95435 +       u8 reg, value, shift;
95436 +
95437 +       reg = gpo;
95438 +       shift = 6;
95439 +
95440 +       if (gpo == PCF50606_GPO1)
95441 +               shift = 4;
95442 +       else if (gpo == PCF50606_GPO2)
95443 +               shift = 7;
95444 +
95445 +       value =  pcf50606_reg_read(pcf, reg);
95446 +
95447 +       return (value >> shift) & 0x01;
95448 +}
95449 +EXPORT_SYMBOL_GPL(pcf50606_gpo_invert_get);
95450 Index: linux-2.6.28/drivers/mfd/pcf50633-adc.c
95451 ===================================================================
95452 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
95453 +++ linux-2.6.28/drivers/mfd/pcf50633-adc.c     2009-01-02 00:01:56.000000000 +0100
95454 @@ -0,0 +1,252 @@
95455 +/* Philips PCF50633 ADC Driver
95456 + *
95457 + * (C) 2006-2008 by Openmoko, Inc.
95458 + * Author: Balaji Rao <balajirrao@openmoko.org>
95459 + * All rights reserved.
95460 + *
95461 + * Broken down from monstrous PCF50633 driver mainly by
95462 + * Harald Welte, Andy Green and Werner Almesberger
95463 + *
95464 + * This program is free software; you can redistribute it and/or
95465 + * modify it under the terms of the GNU General Public License as
95466 + * published by the Free Software Foundation; either version 2 of
95467 + * the License, or (at your option) any later version.
95468 + *
95469 + * This program is distributed in the hope that it will be useful,
95470 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
95471 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
95472 + * GNU General Public License for more details.
95473 + *
95474 + * You should have received a copy of the GNU General Public License
95475 + * along with this program; if not, write to the Free Software
95476 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
95477 + * MA 02111-1307 USA
95478 + */
95479 +
95480 +/*
95481 + * NOTE: This driver does not yet support subtractive ADC mode, which means
95482 + * you can do only one measurement per read request.
95483 + */
95484 +
95485 +#include <linux/mfd/pcf50633/core.h>
95486 +#include <linux/mfd/pcf50633/adc.h>
95487 +
95488 +struct pcf50633_adc_request {
95489 +       int mux;
95490 +       int avg;
95491 +       int result;
95492 +       void (*callback)(struct pcf50633 *, void *, int);
95493 +       void *callback_param;
95494 +
95495 +       /* Used in case of sync requests */
95496 +       struct completion completion;
95497 +
95498 +};
95499 +
95500 +static void adc_read_setup(struct pcf50633 *pcf,
95501 +                                int channel, int avg)
95502 +{
95503 +       channel &= PCF50633_ADCC1_ADCMUX_MASK;
95504 +
95505 +       /* kill ratiometric, but enable ACCSW biasing */
95506 +       pcf50633_reg_write(pcf, PCF50633_REG_ADCC2, 0x00);
95507 +       pcf50633_reg_write(pcf, PCF50633_REG_ADCC3, 0x01);
95508 +
95509 +       /* start ADC conversion on selected channel */
95510 +       pcf50633_reg_write(pcf, PCF50633_REG_ADCC1, channel | avg |
95511 +                   PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT);
95512 +
95513 +}
95514 +
95515 +static void trigger_next_adc_job_if_any(struct pcf50633 *pcf)
95516 +{
95517 +       int head, tail;
95518 +
95519 +       mutex_lock(&pcf->adc.queue_mutex);
95520 +
95521 +       head = pcf->adc.queue_head;
95522 +       tail = pcf->adc.queue_tail;
95523 +
95524 +       if (!pcf->adc.queue[head])
95525 +               goto out;
95526 +
95527 +       adc_read_setup(pcf, pcf->adc.queue[head]->mux,
95528 +                               pcf->adc.queue[head]->avg);
95529 +out:
95530 +       mutex_unlock(&pcf->adc.queue_mutex);
95531 +}
95532 +
95533 +static int
95534 +adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req)
95535 +{
95536 +       int head, tail;
95537 +
95538 +       mutex_lock(&pcf->adc.queue_mutex);
95539 +       head = pcf->adc.queue_head;
95540 +       tail = pcf->adc.queue_tail;
95541 +
95542 +       if (pcf->adc.queue[tail]) {
95543 +               mutex_unlock(&pcf->adc.queue_mutex);
95544 +               return -EBUSY;
95545 +       }
95546 +
95547 +       pcf->adc.queue[tail] = req;
95548 +
95549 +       pcf->adc.queue_tail =
95550 +               (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
95551 +
95552 +       mutex_unlock(&pcf->adc.queue_mutex);
95553 +
95554 +       trigger_next_adc_job_if_any(pcf);
95555 +
95556 +       return 0;
95557 +}
95558 +
95559 +static void
95560 +pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result)
95561 +{
95562 +       struct pcf50633_adc_request *req;
95563 +
95564 +       /*We know here that the passed param is an adc_request object */
95565 +       req = (struct pcf50633_adc_request *)param;
95566 +
95567 +       req->result = result;
95568 +       complete(&req->completion);
95569 +}
95570 +
95571 +int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
95572 +{
95573 +
95574 +       struct pcf50633_adc_request *req;
95575 +       int result;
95576 +
95577 +       /* req is freed when the result is ready, in interrupt handler */
95578 +       req = kzalloc(sizeof(*req), GFP_KERNEL);
95579 +       if (!req)
95580 +               return -ENOMEM;
95581 +
95582 +       req->mux = mux;
95583 +       req->avg = avg;
95584 +       req->callback =  pcf50633_adc_sync_read_callback;
95585 +       req->callback_param = req;
95586 +       init_completion(&req->completion);
95587 +
95588 +       adc_enqueue_request(pcf, req);
95589 +
95590 +       wait_for_completion(&req->completion);
95591 +       result = req->result;
95592 +
95593 +       return result;
95594 +}
95595 +EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read);
95596 +
95597 +int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
95598 +                            void (*callback)(struct pcf50633 *, void *, int),
95599 +                            void *callback_param)
95600 +{
95601 +       struct pcf50633_adc_request *req;
95602 +
95603 +       /* req is freed when the result is ready, in interrupt handler */
95604 +       req = kmalloc(sizeof(*req), GFP_KERNEL);
95605 +       if (!req)
95606 +               return -ENOMEM;
95607 +
95608 +       req->mux = mux;
95609 +       req->avg = avg;
95610 +       req->callback = callback;
95611 +       req->callback_param = callback_param;
95612 +
95613 +       adc_enqueue_request(pcf, req);
95614 +
95615 +       return 0;
95616 +}
95617 +EXPORT_SYMBOL_GPL(pcf50633_adc_async_read);
95618 +
95619 +static int adc_result(struct pcf50633 *pcf)
95620 +{
95621 +       u8 adcs1, adcs3;
95622 +       u16 result;
95623 +
95624 +       adcs1 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS1);
95625 +       adcs3 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS3);
95626 +       result = (adcs1 << 2) | (adcs3 & PCF50633_ADCS3_ADCDAT1L_MASK);
95627 +
95628 +       dev_info(pcf->dev, "adc result = %d\n", result);
95629 +
95630 +       return result;
95631 +}
95632 +
95633 +static void pcf50633_adc_irq(struct pcf50633 *pcf, int irq, void *unused)
95634 +{
95635 +       struct pcf50633_adc_request *req;
95636 +       int head;
95637 +
95638 +       mutex_lock(&pcf->adc.queue_mutex);
95639 +       head = pcf->adc.queue_head;
95640 +
95641 +       req = pcf->adc.queue[head];
95642 +       if (!req) {
95643 +               dev_err(pcf->dev, "ADC queue empty\n");
95644 +               mutex_unlock(&pcf->adc.queue_mutex);
95645 +               return;
95646 +       }
95647 +       pcf->adc.queue[head] = NULL;
95648 +       pcf->adc.queue_head = (head + 1) &
95649 +                                     (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
95650 +
95651 +       mutex_unlock(&pcf->adc.queue_mutex);
95652 +       req->callback(pcf, req->callback_param, adc_result(pcf));
95653 +
95654 +       kfree(req);
95655 +
95656 +       trigger_next_adc_job_if_any(pcf);
95657 +}
95658 +
95659 +int __init pcf50633_adc_probe(struct platform_device *pdev)
95660 +{
95661 +       struct pcf50633 *pcf;
95662 +
95663 +       pcf = platform_get_drvdata(pdev);
95664 +
95665 +       /* Set up IRQ handlers */
95666 +       pcf->irq_handler[PCF50633_IRQ_ADCRDY].handler = pcf50633_adc_irq;
95667 +
95668 +       mutex_init(&pcf->adc.queue_mutex);
95669 +       return 0;
95670 +}
95671 +
95672 +static int __devexit pcf50633_adc_remove(struct platform_device *pdev)
95673 +{
95674 +       struct pcf50633 *pcf;
95675 +
95676 +       pcf = platform_get_drvdata(pdev);
95677 +       pcf->irq_handler[PCF50633_IRQ_ADCRDY].handler = NULL;
95678 +
95679 +       return 0;
95680 +}
95681 +
95682 +struct platform_driver pcf50633_adc_driver = {
95683 +       .driver = {
95684 +               .name = "pcf50633-adc",
95685 +       },
95686 +       .probe = pcf50633_adc_probe,
95687 +       .remove = __devexit_p(pcf50633_adc_remove),
95688 +};
95689 +
95690 +static int __init pcf50633_adc_init(void)
95691 +{
95692 +               return platform_driver_register(&pcf50633_adc_driver);
95693 +}
95694 +module_init(pcf50633_adc_init);
95695 +
95696 +static void __exit pcf50633_adc_exit(void)
95697 +{
95698 +               platform_driver_unregister(&pcf50633_adc_driver);
95699 +}
95700 +module_exit(pcf50633_adc_exit);
95701 +
95702 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
95703 +MODULE_DESCRIPTION("PCF50633 adc driver");
95704 +MODULE_LICENSE("GPL");
95705 +MODULE_ALIAS("platform:pcf50633-adc");
95706 +
95707 Index: linux-2.6.28/drivers/mfd/pcf50633-core.c
95708 ===================================================================
95709 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
95710 +++ linux-2.6.28/drivers/mfd/pcf50633-core.c    2009-01-02 00:01:56.000000000 +0100
95711 @@ -0,0 +1,627 @@
95712 +/* Philips PCF50633 Power Management Unit (PMU) driver
95713 + *
95714 + * (C) 2006-2008 by Openmoko, Inc.
95715 + * Author: Harald Welte <laforge@openmoko.org>
95716 + * All rights reserved.
95717 + *
95718 + * This program is free software; you can redistribute it and/or
95719 + * modify it under the terms of the GNU General Public License as
95720 + * published by the Free Software Foundation; either version 2 of
95721 + * the License, or (at your option) any later version.
95722 + *
95723 + * This program is distributed in the hope that it will be useful,
95724 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
95725 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
95726 + * GNU General Public License for more details.
95727 + *
95728 + * You should have received a copy of the GNU General Public License
95729 + * along with this program; if not, write to the Free Software
95730 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
95731 + * MA 02111-1307 USA
95732 + *
95733 + */
95734 +#include <linux/i2c.h>
95735 +#include <linux/irq.h>
95736 +#include <linux/device.h>
95737 +#include <linux/module.h>
95738 +#include <linux/reboot.h>
95739 +#include <linux/interrupt.h>
95740 +#include <linux/workqueue.h>
95741 +#include <linux/platform_device.h>
95742 +
95743 +#include <linux/mfd/pcf50633/core.h>
95744 +
95745 +/* Read a block of upto 32 regs  */
95746 +int pcf50633_read_block(struct pcf50633 *pcf , u8 reg,
95747 +                                       int nr_regs, u8 *data)
95748 +{
95749 +       int ret;
95750 +
95751 +       mutex_lock(&pcf->lock);
95752 +       ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
95753 +                                                       nr_regs, data);
95754 +       mutex_unlock(&pcf->lock);
95755 +
95756 +       return ret;
95757 +}
95758 +EXPORT_SYMBOL_GPL(pcf50633_read_block);
95759 +
95760 +/* Write a block of upto 32 regs  */
95761 +int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
95762 +                                       int nr_regs, u8 *data)
95763 +{
95764 +       int ret;
95765 +
95766 +       mutex_lock(&pcf->lock);
95767 +       ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
95768 +                                                       nr_regs, data);
95769 +       mutex_unlock(&pcf->lock);
95770 +
95771 +       return ret;
95772 +}
95773 +EXPORT_SYMBOL_GPL(pcf50633_write_block);
95774 +
95775 +u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg)
95776 +{
95777 +       int ret;
95778 +
95779 +       mutex_lock(&pcf->lock);
95780 +       ret = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
95781 +       mutex_unlock(&pcf->lock);
95782 +
95783 +       return ret;
95784 +}
95785 +EXPORT_SYMBOL_GPL(pcf50633_reg_read);
95786 +
95787 +int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val)
95788 +{
95789 +       int ret;
95790 +       mutex_lock(&pcf->lock);
95791 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, val);
95792 +       mutex_unlock(&pcf->lock);
95793 +
95794 +       return ret;
95795 +}
95796 +EXPORT_SYMBOL_GPL(pcf50633_reg_write);
95797 +
95798 +int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val)
95799 +{
95800 +       int ret;
95801 +       u8 tmp;
95802 +
95803 +       val &= mask;
95804 +
95805 +       mutex_lock(&pcf->lock);
95806 +
95807 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
95808 +       tmp &= ~mask;
95809 +       tmp |= val;
95810 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
95811 +
95812 +       mutex_unlock(&pcf->lock);
95813 +
95814 +       return ret;
95815 +}
95816 +EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask);
95817 +
95818 +int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val)
95819 +{
95820 +       int ret;
95821 +       u8 tmp;
95822 +
95823 +       mutex_lock(&pcf->lock);
95824 +
95825 +       tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
95826 +       tmp &= ~val;
95827 +       ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
95828 +
95829 +       mutex_unlock(&pcf->lock);
95830 +
95831 +       return ret;
95832 +}
95833 +EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits);
95834 +
95835 +/* sysfs attributes */
95836 +static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
95837 +                           char *buf)
95838 +{
95839 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
95840 +       u8 dump[16];
95841 +       int n, n1, idx = 0;
95842 +       char *buf1 = buf;
95843 +       static u8 address_no_read[] = { /* must be ascending */
95844 +               PCF50633_REG_INT1,
95845 +               PCF50633_REG_INT2,
95846 +               PCF50633_REG_INT3,
95847 +               PCF50633_REG_INT4,
95848 +               PCF50633_REG_INT5,
95849 +               0 /* terminator */
95850 +       };
95851 +
95852 +       for (n = 0; n < 256; n += sizeof(dump)) {
95853 +               for (n1 = 0; n1 < sizeof(dump); n1++)
95854 +                       if (n == address_no_read[idx]) {
95855 +                               idx++;
95856 +                               dump[n1] = 0x00;
95857 +                       } else
95858 +                               dump[n1] = pcf50633_reg_read(pcf, n + n1);
95859 +
95860 +               hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
95861 +               buf1 += strlen(buf1);
95862 +               *buf1++ = '\n';
95863 +               *buf1 = '\0';
95864 +       }
95865 +
95866 +       return buf1 - buf;
95867 +}
95868 +static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
95869 +
95870 +static ssize_t show_resume_reason(struct device *dev,
95871 +                               struct device_attribute *attr, char *buf)
95872 +{
95873 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
95874 +       int n;
95875 +
95876 +       n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
95877 +                               pcf->resume_reason[0],
95878 +                               pcf->resume_reason[1],
95879 +                               pcf->resume_reason[2],
95880 +                               pcf->resume_reason[3],
95881 +                               pcf->resume_reason[4]);
95882 +
95883 +       return n;
95884 +}
95885 +static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
95886 +
95887 +static struct attribute *pcf_sysfs_entries[] = {
95888 +       &dev_attr_dump_regs.attr,
95889 +       &dev_attr_resume_reason.attr,
95890 +       NULL,
95891 +};
95892 +
95893 +static struct attribute_group pcf_attr_group = {
95894 +       .name   = NULL,                 /* put in device directory */
95895 +       .attrs  = pcf_sysfs_entries,
95896 +};
95897 +
95898 +
95899 +static int pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, int mask)
95900 +{
95901 +       u8 reg, bits, tmp;
95902 +       int ret = 0, idx;
95903 +
95904 +       idx = irq / 8;
95905 +       reg =  PCF50633_REG_INT1M + idx;
95906 +       bits = 1 << (irq % 8);
95907 +
95908 +       mutex_lock(&pcf->lock);
95909 +
95910 +       if (mask) {
95911 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
95912 +               tmp |= bits;
95913 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
95914 +
95915 +               pcf->mask_regs[idx] &= ~bits;
95916 +               pcf->mask_regs[idx] |= bits;
95917 +       } else {
95918 +               tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
95919 +               tmp &= ~bits;
95920 +               ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
95921 +
95922 +               pcf->mask_regs[idx] &= ~bits;
95923 +       }
95924 +
95925 +       mutex_unlock(&pcf->lock);
95926 +
95927 +       return 0;
95928 +}
95929 +
95930 +int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
95931 +{
95932 +       dev_info(pcf->dev, "Masking IRQ %d\n", irq);
95933 +
95934 +       return pcf50633_irq_mask_set(pcf, irq, 1);
95935 +}
95936 +EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
95937 +
95938 +int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
95939 +{
95940 +       dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
95941 +
95942 +       return pcf50633_irq_mask_set(pcf, irq, 0);
95943 +}
95944 +EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
95945 +
95946 +int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
95947 +{
95948 +       u8 reg, bits;
95949 +
95950 +       reg =  (irq / 8);
95951 +       bits = (1 << (irq % 8));
95952 +
95953 +       return pcf->mask_regs[reg] & bits;
95954 +}
95955 +EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
95956 +
95957 +static void pcf50633_irq_call_handler(struct pcf50633 *pcf,
95958 +                                       int irq)
95959 +{
95960 +       if (pcf->irq_handler[irq].handler) {
95961 +               pcf->irq_handler[irq].handler(pcf, irq,
95962 +                                       pcf->irq_handler[irq].data);
95963 +       }
95964 +}
95965 +
95966 +#define PCF50633_ONKEY1S_TIMEOUT 8
95967 +
95968 +static void pcf50633_irq_worker(struct work_struct *work)
95969 +{
95970 +       struct pcf50633 *pcf;
95971 +       int ret, i, j;
95972 +       u8 pcf_int[5], chgstat;
95973 +
95974 +       pcf = container_of(work, struct pcf50633, irq_work);
95975 +
95976 +       /* Read the 5 INT regs in one transaction */
95977 +       ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
95978 +                                               sizeof(pcf_int), pcf_int);
95979 +       if (ret != sizeof(pcf_int)) {
95980 +               dev_info(pcf->dev, "Error reading INT registers\n");
95981 +
95982 +               /* We don't have an option but to retry. Because if
95983 +                * we don't, there won't be another interrupt edge.
95984 +                */
95985 +               goto reschedule;
95986 +       }
95987 +
95988 +       pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN,  0x04 );  /* defeat 8s death from lowsys on A5 */
95989 +
95990 +       /* We immediately read the usb and adapter status. We thus make sure
95991 +        * only of USBINS/USBREM and ADAPINS/ADPREM IRQ handlers are called */
95992 +       if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
95993 +               chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
95994 +               if (chgstat & (0x3 << 4))
95995 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM);
95996 +               else
95997 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS);
95998 +       }
95999 +
96000 +       if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
96001 +               chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
96002 +               if (chgstat & (0x3 << 4))
96003 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM);
96004 +               else
96005 +                       pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS);
96006 +       }
96007 +
96008 +       dev_info(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
96009 +                       "INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
96010 +                       pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
96011 +
96012 +       /* Some revisions of the chip don't have a 8s standby mode on
96013 +        * ONKEY1S press. We try to manually do it in such cases. */
96014 +
96015 +       if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
96016 +               dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
96017 +                                                       pcf->onkey1s_held);
96018 +               if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
96019 +                       if (pcf->pdata->force_shutdown)
96020 +                               pcf->pdata->force_shutdown(pcf);
96021 +       }
96022 +
96023 +       if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
96024 +               dev_info(pcf->dev, "ONKEY1S held\n");
96025 +               pcf->onkey1s_held = 1 ;
96026 +
96027 +               /* Unmask IRQ_SECOND */
96028 +               pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
96029 +                                               PCF50633_INT1_SECOND);
96030 +
96031 +               /* Unmask IRQ_ONKEYR */
96032 +               pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
96033 +                                               PCF50633_INT2_ONKEYR);
96034 +       }
96035 +
96036 +       if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
96037 +               pcf->onkey1s_held = 0;
96038 +
96039 +               /* Mask SECOND and ONKEYR interrupts */
96040 +               if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
96041 +                       pcf50633_reg_set_bit_mask(pcf,
96042 +                                       PCF50633_REG_INT1M,
96043 +                                       PCF50633_INT1_SECOND,
96044 +                                       PCF50633_INT1_SECOND);
96045 +
96046 +               if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
96047 +                       pcf50633_reg_set_bit_mask(pcf,
96048 +                                       PCF50633_REG_INT2M,
96049 +                                       PCF50633_INT2_ONKEYR,
96050 +                                       PCF50633_INT2_ONKEYR);
96051 +       }
96052 +
96053 +       /* Have we just resumed ? */
96054 +       if (pcf->is_suspended) {
96055 +
96056 +               pcf->is_suspended = 0;
96057 +
96058 +               /* Set the resume reason filtering out non resumers */
96059 +               for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
96060 +                       pcf->resume_reason[i] = pcf_int[i] &
96061 +                                               pcf->pdata->resumers[i];
96062 +
96063 +               /* Make sure we don't pass on any ONKEY events to
96064 +                * userspace now */
96065 +               pcf_int[1] &= ~ (PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
96066 +       }
96067 +
96068 +       /* Unset masked interrupts */
96069 +       for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
96070 +               pcf_int[i] &= ~pcf->mask_regs[i];
96071 +               for (j = 0; j < 8 ; j++)
96072 +                       if (pcf_int[i] & (1 << j))
96073 +                               pcf50633_irq_call_handler(pcf, (i * 8) + j);
96074 +       }
96075 +
96076 +       put_device(pcf->dev);
96077 +
96078 +       enable_irq(pcf->irq);
96079 +
96080 +       return;
96081 +reschedule:
96082 +       schedule_work(&pcf->irq_work);
96083 +
96084 +       /* Don't put_device here. Will be used when we are rescheduled */
96085 +
96086 +       return;
96087 +}
96088 +
96089 +static irqreturn_t pcf50633_irq(int irq, void *data)
96090 +{
96091 +       struct pcf50633 *pcf = data;
96092 +
96093 +       get_device(pcf->dev);
96094 +
96095 +       disable_irq(pcf->irq);
96096 +
96097 +       schedule_work(&pcf->irq_work);
96098 +
96099 +       return IRQ_HANDLED;
96100 +}
96101 +
96102 +static void
96103 +pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
96104 +                                               struct platform_device **pdev)
96105 +{
96106 +       int ret;
96107 +
96108 +       *pdev = platform_device_alloc(name, -1);
96109 +
96110 +       if (!pdev) {
96111 +               dev_err(pcf->dev, "Falied to allocate %s\n", name);
96112 +               return;
96113 +       }
96114 +
96115 +       (*pdev)->dev.parent = pcf->dev;
96116 +       platform_set_drvdata(*pdev, pcf);
96117 +
96118 +       ret = platform_device_add(*pdev);
96119 +       if (ret != 0) {
96120 +               dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
96121 +               platform_device_put(*pdev);
96122 +               *pdev = NULL;
96123 +       }
96124 +}
96125 +
96126 +#ifdef CONFIG_PM
96127 +static int pcf50633_suspend(struct device *dev, pm_message_t state)
96128 +{
96129 +       struct pcf50633 *pcf;
96130 +       int ret, i;
96131 +       u8 res[5];
96132 +
96133 +       pcf = dev_get_drvdata(dev);
96134 +
96135 +       /* Make sure our interrupt handlers are not called
96136 +        * henceforth */
96137 +       disable_irq(pcf->irq);
96138 +
96139 +       /* Make sure that an IRQ worker has quit */
96140 +       cancel_work_sync(&pcf->irq_work);
96141 +
96142 +       /* Save the masks */
96143 +       ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
96144 +                               ARRAY_SIZE(pcf->suspend_irq_masks),
96145 +                                       pcf->suspend_irq_masks);
96146 +       if (ret < 0)
96147 +               dev_err(pcf->dev, "error saving irq masks\n");
96148 +
96149 +       /* Set interrupt masks. So that only those sources we want to wake
96150 +        * us up can
96151 +        */
96152 +       for (i = 0; i < ARRAY_SIZE(res); i++)
96153 +               res[i] = ~pcf->pdata->resumers[i];
96154 +
96155 +       pcf50633_write_block(pcf, PCF50633_REG_INT1M, ARRAY_SIZE(res), &res[0]);
96156 +
96157 +       pcf->is_suspended = 1;
96158 +
96159 +       return 0;
96160 +}
96161 +
96162 +static int pcf50633_resume(struct device *dev)
96163 +{
96164 +       struct pcf50633 *pcf;
96165 +
96166 +       pcf = dev_get_drvdata(dev);
96167 +
96168 +       /* Write the saved mask registers */
96169 +       pcf50633_write_block(pcf, PCF50633_REG_INT1M,
96170 +                               ARRAY_SIZE(pcf->suspend_irq_masks),
96171 +                                       pcf->suspend_irq_masks);
96172 +
96173 +       get_device(pcf->dev);
96174 +
96175 +       /*
96176 +        * Clear any pending interrupts and set resume reason if any.
96177 +        * This will leave with enable_irq()
96178 +        */
96179 +       pcf50633_irq_worker(&pcf->irq_work);
96180 +
96181 +       return 0;
96182 +}
96183 +#else
96184 +#define pcf50633_suspend NULL
96185 +#define pcf50633_resume NULL
96186 +#endif
96187 +
96188 +static int pcf50633_probe(struct i2c_client *client,
96189 +                               const struct i2c_device_id *ids)
96190 +{
96191 +       struct pcf50633 *pcf;
96192 +       struct pcf50633_platform_data *pdata;
96193 +       int i, ret = 0;
96194 +       int version;
96195 +       int variant;
96196 +
96197 +       pdata = client->dev.platform_data;
96198 +
96199 +       pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
96200 +       if (!pcf)
96201 +               return -ENOMEM;
96202 +
96203 +       pcf->pdata = pdata;
96204 +       pdata->pcf = pcf;
96205 +
96206 +       mutex_init(&pcf->lock);
96207 +
96208 +       i2c_set_clientdata(client, pcf);
96209 +       pcf->dev = &client->dev;
96210 +       pcf->i2c_client = client;
96211 +
96212 +       INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
96213 +
96214 +       version = pcf50633_reg_read(pcf, 0);
96215 +       if (version < 0) {
96216 +               dev_err(pcf->dev, "Unable to probe pcf50633\n");
96217 +               kfree(pcf);
96218 +               return -ENODEV;
96219 +       }
96220 +
96221 +       variant = pcf50633_reg_read(pcf, 1);
96222 +       if (variant < 0) {
96223 +               dev_err(pcf->dev, "Unable to probe pcf50633\n");
96224 +               kfree(pcf);
96225 +               return -ENODEV;
96226 +       }
96227 +
96228 +       dev_info(pcf->dev, "Probed device version %d variant %d\n",
96229 +                                                       version, variant);
96230 +
96231 +       /* Enable all inteerupts except RTC SECOND */
96232 +       pcf->mask_regs[0] = 0x80;
96233 +       pcf50633_reg_write(pcf, PCF50633_REG_INT1M, 0x80);
96234 +
96235 +       pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
96236 +       pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
96237 +       pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
96238 +       pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
96239 +
96240 +       pcf50633_client_dev_register(pcf, "pcf50633-input",
96241 +                                               &pcf->input.pdev);
96242 +       pcf50633_client_dev_register(pcf, "pcf50633-rtc",
96243 +                                               &pcf->rtc.pdev);
96244 +       pcf50633_client_dev_register(pcf, "pcf50633-mbc",
96245 +                                               &pcf->mbc.pdev);
96246 +       pcf50633_client_dev_register(pcf, "pcf50633-adc",
96247 +                                               &pcf->adc.pdev);
96248 +       for (i = 0; i < PCF50633_NUM_REGULATORS; i++) {
96249 +               struct platform_device *pdev;
96250 +
96251 +               pdev = platform_device_alloc("pcf50633-regltr", i);
96252 +               if (!pdev) {
96253 +                       dev_err(pcf->dev, "Cannot create regulator\n");
96254 +                       continue;
96255 +               }
96256 +
96257 +               pdev->dev.parent = pcf->dev;
96258 +               pdev->dev.platform_data = &pdata->reg_init_data[i];
96259 +               pdev->dev.driver_data = pcf;
96260 +               pcf->pmic.pdev[i] = pdev;
96261 +
96262 +               platform_device_add(pdev);
96263 +       }
96264 +
96265 +       pcf->irq = client->irq;
96266 +
96267 +       if (client->irq) {
96268 +               ret = request_irq(client->irq, pcf50633_irq,
96269 +                               IRQF_TRIGGER_LOW, "pcf50633", pcf);
96270 +
96271 +               if (ret) {
96272 +                       dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
96273 +                       goto err;
96274 +               }
96275 +       } else {
96276 +               dev_err(pcf->dev, "No IRQ configured\n");
96277 +               goto err;
96278 +       }
96279 +
96280 +       if (enable_irq_wake(client->irq) < 0)
96281 +               dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up "
96282 +                       "source in this hardware revision\n", client->irq);
96283 +
96284 +       ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
96285 +       if (ret)
96286 +               dev_err(pcf->dev, "error creating sysfs entries\n");
96287 +
96288 +       if (pdata->probe_done)
96289 +               pdata->probe_done(pcf);
96290 +
96291 +       return 0;
96292 +
96293 +err:
96294 +       kfree(pcf);
96295 +       return ret;
96296 +}
96297 +
96298 +static int pcf50633_remove(struct i2c_client *client)
96299 +{
96300 +       struct pcf50633 *pcf = i2c_get_clientdata(client);
96301 +
96302 +       free_irq(pcf->irq, pcf);
96303 +       kfree(pcf);
96304 +
96305 +       return 0;
96306 +}
96307 +
96308 +static struct i2c_device_id pcf50633_id_table[] = {
96309 +       {"pcf50633", 0x73},
96310 +};
96311 +
96312 +static struct i2c_driver pcf50633_driver = {
96313 +       .driver = {
96314 +               .name   = "pcf50633",
96315 +               .suspend = pcf50633_suspend,
96316 +               .resume = pcf50633_resume,
96317 +       },
96318 +       .id_table = pcf50633_id_table,
96319 +       .probe = pcf50633_probe,
96320 +       .remove = pcf50633_remove,
96321 +};
96322 +
96323 +static int __init pcf50633_init(void)
96324 +{
96325 +       return i2c_add_driver(&pcf50633_driver);
96326 +}
96327 +
96328 +static void pcf50633_exit(void)
96329 +{
96330 +       i2c_del_driver(&pcf50633_driver);
96331 +}
96332 +
96333 +MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
96334 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
96335 +MODULE_LICENSE("GPL");
96336 +
96337 +module_init(pcf50633_init);
96338 +module_exit(pcf50633_exit);
96339 Index: linux-2.6.28/drivers/mfd/pcf50633-gpio.c
96340 ===================================================================
96341 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
96342 +++ linux-2.6.28/drivers/mfd/pcf50633-gpio.c    2009-01-02 00:01:56.000000000 +0100
96343 @@ -0,0 +1,100 @@
96344 +/* Philips PCF50633 GPIO Driver
96345 + *
96346 + * (C) 2006-2008 by Openmoko, Inc.
96347 + * Author: Balaji Rao <balajirrao@openmoko.org>
96348 + * All rights reserved.
96349 + *
96350 + * Broken down from monstrous PCF50633 driver mainly by
96351 + * Harald Welte, Andy Green and Werner Almesberger
96352 + *
96353 + * This program is free software; you can redistribute it and/or
96354 + * modify it under the terms of the GNU General Public License as
96355 + * published by the Free Software Foundation; either version 2 of
96356 + * the License, or (at your option) any later version.
96357 + *
96358 + * This program is distributed in the hope that it will be useful,
96359 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
96360 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
96361 + * GNU General Public License for more details.
96362 + *
96363 + * You should have received a copy of the GNU General Public License
96364 + * along with this program; if not, write to the Free Software
96365 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
96366 + * MA 02111-1307 USA
96367 + */
96368 +
96369 +#include <linux/mfd/pcf50633/core.h>
96370 +#include <linux/mfd/pcf50633/gpio.h>
96371 +#include <linux/mfd/pcf50633/pmic.h>
96372 +
96373 +void pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, int val)
96374 +{
96375 +       u8 reg;
96376 +
96377 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
96378 +
96379 +       pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
96380 +}
96381 +EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
96382 +
96383 +int pcf50633_gpio_get(struct pcf50633 *pcf, int gpio)
96384 +{
96385 +       u8 reg, val;
96386 +
96387 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
96388 +       val = pcf50633_reg_read(pcf, reg) & 0x07;
96389 +
96390 +       return val;
96391 +}
96392 +EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
96393 +
96394 +void pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert)
96395 +{
96396 +       u8 val, reg;
96397 +
96398 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
96399 +       val = !!invert << 3;
96400 +
96401 +       pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
96402 +}
96403 +EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set);
96404 +
96405 +int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio)
96406 +{
96407 +       u8 reg, val;
96408 +
96409 +       reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
96410 +       val = pcf50633_reg_read(pcf, reg);
96411 +
96412 +       return val & (1 << 3);
96413 +}
96414 +EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get);
96415 +
96416 +static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
96417 +       [PCF50633_REGULATOR_AUTO]       = PCF50633_REG_AUTOOUT,
96418 +       [PCF50633_REGULATOR_DOWN1]      = PCF50633_REG_DOWN1OUT,
96419 +       [PCF50633_REGULATOR_DOWN2]      = PCF50633_REG_DOWN2OUT,
96420 +       [PCF50633_REGULATOR_MEMLDO]     = PCF50633_REG_MEMLDOOUT,
96421 +       [PCF50633_REGULATOR_LDO1]       = PCF50633_REG_LDO1OUT,
96422 +       [PCF50633_REGULATOR_LDO2]       = PCF50633_REG_LDO2OUT,
96423 +       [PCF50633_REGULATOR_LDO3]       = PCF50633_REG_LDO3OUT,
96424 +       [PCF50633_REGULATOR_LDO4]       = PCF50633_REG_LDO4OUT,
96425 +       [PCF50633_REGULATOR_LDO5]       = PCF50633_REG_LDO5OUT,
96426 +       [PCF50633_REGULATOR_LDO6]       = PCF50633_REG_LDO6OUT,
96427 +       [PCF50633_REGULATOR_HCLDO]      = PCF50633_REG_HCLDOOUT,
96428 +};
96429 +
96430 +void pcf50633_gpio_power_supply_set(struct pcf50633 *pcf,
96431 +                                       int gpio, int regulator, int on)
96432 +{
96433 +       u8 reg, val, mask;
96434 +
96435 +       /* the *ENA register is always one after the *OUT register */
96436 +       reg = pcf50633_regulator_registers[regulator] + 1;
96437 +
96438 +       val = (!!on << (gpio - PCF50633_GPIO1));
96439 +       mask = (1 << (gpio - PCF50633_GPIO1));
96440 +
96441 +       pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
96442 +}
96443 +EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set);
96444 Index: linux-2.6.28/drivers/mfd/pcf50633-i2c.c
96445 ===================================================================
96446 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
96447 +++ linux-2.6.28/drivers/mfd/pcf50633-i2c.c     2009-01-02 00:01:56.000000000 +0100
96448 @@ -0,0 +1,3 @@
96449 +
96450 +};
96451 +
96452 Index: linux-2.6.28/drivers/misc/Kconfig
96453 ===================================================================
96454 --- linux-2.6.28.orig/drivers/misc/Kconfig      2008-12-25 00:26:37.000000000 +0100
96455 +++ linux-2.6.28/drivers/misc/Kconfig   2009-01-02 00:01:56.000000000 +0100
96456 @@ -401,6 +401,11 @@ config THINKPAD_ACPI_HOTKEY_POLL
96457           If you are not sure, say Y here.  The driver enables polling only if
96458           it is strictly necessary to do so.
96459
96460 +config LOW_MEMORY_KILLER
96461 +    tristate "Low Memory Killer"
96462 +         ---help---
96463 +         Register processes to be killed when memory is low.
96464 +
96465  config ATMEL_SSC
96466         tristate "Device driver for Atmel SSC peripheral"
96467         depends on AVR32 || ARCH_AT91
96468 @@ -500,4 +505,9 @@ config SGI_GRU_DEBUG
96469
96470  source "drivers/misc/c2port/Kconfig"
96471
96472 +config MACH_NEO1973
96473 +       bool
96474 +       help
96475 +         Common machine code for Openmoko GTAxx hardware
96476 +
96477  endif # MISC_DEVICES
96478 Index: linux-2.6.28/drivers/misc/lowmemorykiller.c
96479 ===================================================================
96480 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
96481 +++ linux-2.6.28/drivers/misc/lowmemorykiller.c 2009-01-02 00:01:56.000000000 +0100
96482 @@ -0,0 +1,119 @@
96483 +/* drivers/misc/lowmemorykiller.c
96484 + *
96485 + * Copyright (C) 2007-2008 Google, Inc.
96486 + *
96487 + * This software is licensed under the terms of the GNU General Public
96488 + * License version 2, as published by the Free Software Foundation, and
96489 + * may be copied, distributed, and modified under those terms.
96490 + *
96491 + * This program is distributed in the hope that it will be useful,
96492 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
96493 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
96494 + * GNU General Public License for more details.
96495 + *
96496 + */
96497 +
96498 +#include <linux/module.h>
96499 +#include <linux/kernel.h>
96500 +#include <linux/mm.h>
96501 +#include <linux/oom.h>
96502 +#include <linux/sched.h>
96503 +
96504 +static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask);
96505 +
96506 +static struct shrinker lowmem_shrinker = {
96507 +       .shrink = lowmem_shrink,
96508 +       .seeks = DEFAULT_SEEKS * 16
96509 +};
96510 +static uint32_t lowmem_debug_level = 2;
96511 +static int lowmem_adj[6] = {
96512 +       0,
96513 +       1,
96514 +       6,
96515 +       12,
96516 +};
96517 +static int lowmem_adj_size = 4;
96518 +static size_t lowmem_minfree[6] = {
96519 +       3*512, // 6MB
96520 +       2*1024, // 8MB
96521 +       4*1024, // 16MB
96522 +       16*1024, // 64MB
96523 +};
96524 +static int lowmem_minfree_size = 4;
96525 +
96526 +#define lowmem_print(level, x...) do { if(lowmem_debug_level >= (level)) printk(x); } while(0)
96527 +
96528 +module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR);
96529 +module_param_array_named(adj, lowmem_adj, int, &lowmem_adj_size, S_IRUGO | S_IWUSR);
96530 +module_param_array_named(minfree, lowmem_minfree, uint, &lowmem_minfree_size, S_IRUGO | S_IWUSR);
96531 +module_param_named(debug_level, lowmem_debug_level, uint, S_IRUGO | S_IWUSR);
96532 +
96533 +static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
96534 +{
96535 +       struct task_struct *p;
96536 +       struct task_struct *selected = NULL;
96537 +       int rem = 0;
96538 +       int tasksize;
96539 +       int i;
96540 +       int min_adj = OOM_ADJUST_MAX + 1;
96541 +       int selected_tasksize = 0;
96542 +       int array_size = ARRAY_SIZE(lowmem_adj);
96543 +       int other_free = global_page_state(NR_FREE_PAGES) + global_page_state(NR_FILE_PAGES);
96544 +       if(lowmem_adj_size < array_size)
96545 +               array_size = lowmem_adj_size;
96546 +       if(lowmem_minfree_size < array_size)
96547 +               array_size = lowmem_minfree_size;
96548 +       for(i = 0; i < array_size; i++) {
96549 +               if(other_free < lowmem_minfree[i]) {
96550 +                       min_adj = lowmem_adj[i];
96551 +                       break;
96552 +               }
96553 +       }
96554 +       if(nr_to_scan > 0)
96555 +               lowmem_print(3, "lowmem_shrink %d, %x, ofree %d, ma %d\n", nr_to_scan, gfp_mask, other_free, min_adj);
96556 +       read_lock(&tasklist_lock);
96557 +       for_each_process(p) {
96558 +               if(p->oomkilladj >= 0 && p->mm) {
96559 +                       tasksize = get_mm_rss(p->mm);
96560 +                       if(nr_to_scan > 0 && tasksize > 0 && p->oomkilladj >= min_adj) {
96561 +                               if(selected == NULL ||
96562 +                                  p->oomkilladj > selected->oomkilladj ||
96563 +                                  (p->oomkilladj == selected->oomkilladj &&
96564 +                                   tasksize > selected_tasksize)) {
96565 +                                       selected = p;
96566 +                                       selected_tasksize = tasksize;
96567 +                                       lowmem_print(2, "select %d (%s), adj %d, size %d, to kill\n",
96568 +                                                    p->pid, p->comm, p->oomkilladj, tasksize);
96569 +                               }
96570 +                       }
96571 +                       rem += tasksize;
96572 +               }
96573 +       }
96574 +       if(selected != NULL) {
96575 +               lowmem_print(1, "send sigkill to %d (%s), adj %d, size %d\n",
96576 +                            selected->pid, selected->comm,
96577 +                            selected->oomkilladj, selected_tasksize);
96578 +               force_sig(SIGKILL, selected);
96579 +               rem -= selected_tasksize;
96580 +       }
96581 +       lowmem_print(4, "lowmem_shrink %d, %x, return %d\n", nr_to_scan, gfp_mask, rem);
96582 +       read_unlock(&tasklist_lock);
96583 +       return rem;
96584 +}
96585 +
96586 +static int __init lowmem_init(void)
96587 +{
96588 +       register_shrinker(&lowmem_shrinker);
96589 +       return 0;
96590 +}
96591 +
96592 +static void __exit lowmem_exit(void)
96593 +{
96594 +       unregister_shrinker(&lowmem_shrinker);
96595 +}
96596 +
96597 +module_init(lowmem_init);
96598 +module_exit(lowmem_exit);
96599 +
96600 +MODULE_LICENSE("GPL");
96601 +
96602 Index: linux-2.6.28/drivers/misc/Makefile
96603 ===================================================================
96604 --- linux-2.6.28.orig/drivers/misc/Makefile     2008-12-25 00:26:37.000000000 +0100
96605 +++ linux-2.6.28/drivers/misc/Makefile  2009-01-02 00:06:11.000000000 +0100
96606 @@ -33,3 +33,8 @@ obj-$(CONFIG_SGI_XP)          += sgi-xp/
96607  obj-$(CONFIG_SGI_GRU)          += sgi-gru/
96608  obj-$(CONFIG_HP_ILO)           += hpilo.o
96609  obj-$(CONFIG_C2PORT)           += c2port/
96610 +obj-$(CONFIG_MACH_SMDK6410)    += smdk6410-sleeptest.o
96611 +obj-$(CONFIG_LOW_MEMORY_KILLER)        += lowmemorykiller.o
96612 +obj-$(CONFIG_MACH_NEO1973)      += neo1973_version.o \
96613 +                                   neo1973_pm_host.o \
96614 +                                   neo1973_pm_resume_reason.o
96615 Index: linux-2.6.28/drivers/misc/neo1973_pm_charging_led.c
96616 ===================================================================
96617 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
96618 +++ linux-2.6.28/drivers/misc/neo1973_pm_charging_led.c 2009-01-02 00:01:56.000000000 +0100
96619 @@ -0,0 +1,106 @@
96620 +/*
96621 + * Charging LED sysfs for the FIC Neo1973 GSM Phone
96622 + * (currently only implemented in GTA02 but ready for GTA01 implementation)
96623 + *
96624 + * (C) 2008 by Openmoko Inc.
96625 + * Author: Andy Green <andy@openmoko.com>
96626 + * All rights reserved.
96627 + *
96628 + * This program is free software; you can redistribute it and/or modify
96629 + * it under the terms of the GNU General Public License charging_led 2 as
96630 + * published by the Free Software Foundation
96631 + *
96632 + */
96633 +
96634 +#include <linux/module.h>
96635 +#include <linux/init.h>
96636 +#include <linux/kernel.h>
96637 +#include <linux/platform_device.h>
96638 +
96639 +#include <asm/hardware.h>
96640 +#include <asm/mach-types.h>
96641 +
96642 +#ifdef CONFIG_MACH_NEO1973_GTA02
96643 +#include <asm/arch/gta02.h>
96644 +
96645 +static enum neo1973_charging_led_modes charging_mode;
96646 +
96647 +static char *charging_led_mode_names[] = {
96648 +       "Disabled",
96649 +       "Aux LED",
96650 +       "Power LED"
96651 +};
96652 +
96653 +static ssize_t charging_led_read(struct device *dev,
96654 +                                struct device_attribute *attr, char *buf)
96655 +{
96656 +       return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
96657 +}
96658 +
96659 +static ssize_t charging_led_read(struct device *dev,
96660 +                                struct device_attribute *attr, char *buf)
96661 +{
96662 +       return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
96663 +}
96664 +
96665 +
96666 +static DEVICE_ATTR(pcb, 0644, charging_led_read, charging_led_write);
96667 +
96668 +static struct attribute *neo1973_charging_led_sysfs_entries[] = {
96669 +       &dev_attr_pcb.attr,
96670 +       NULL
96671 +};
96672 +
96673 +static struct attribute_group neo1973_charging_led_attr_group = {
96674 +       .name   = NULL,
96675 +       .attrs  = neo1973_charging_led_sysfs_entries,
96676 +};
96677 +
96678 +static int __init neo1973_charging_led_probe(struct platform_device *pdev)
96679 +{
96680 +       dev_info(&pdev->dev, "starting\n");
96681 +
96682 +       switch (machine_arch_type) {
96683 +#ifdef CONFIG_MACH_NEO1973_GTA01
96684 +       case MACH_TYPE_NEO1973_GTA01:
96685 +               return -EINVAL;
96686 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
96687 +       default:
96688 +               break;
96689 +       }
96690 +
96691 +       return sysfs_create_group(&pdev->dev.kobj,
96692 +                                            &neo1973_charging_led_attr_group);
96693 +}
96694 +
96695 +static int neo1973_charging_led_remove(struct platform_device *pdev)
96696 +{
96697 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_charging_led_attr_group);
96698 +       return 0;
96699 +}
96700 +
96701 +static struct platform_driver neo1973_charging_led_driver = {
96702 +       .probe          = neo1973_charging_led_probe,
96703 +       .remove         = neo1973_charging_led_remove,
96704 +       .driver         = {
96705 +               .name           = "neo1973-charging-led",
96706 +       },
96707 +};
96708 +
96709 +static int __devinit neo1973_charging_led_init(void)
96710 +{
96711 +       return platform_driver_register(&neo1973_charging_led_driver);
96712 +}
96713 +
96714 +static void neo1973_charging_led_exit(void)
96715 +{
96716 +       platform_driver_unregister(&neo1973_charging_led_driver);
96717 +}
96718 +
96719 +module_init(neo1973_charging_led_init);
96720 +module_exit(neo1973_charging_led_exit);
96721 +
96722 +MODULE_LICENSE("GPL");
96723 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
96724 +MODULE_DESCRIPTION("Neo1973 PCB charging_led");
96725 +#endif
96726 Index: linux-2.6.28/drivers/misc/neo1973_pm_host.c
96727 ===================================================================
96728 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
96729 +++ linux-2.6.28/drivers/misc/neo1973_pm_host.c 2009-01-02 00:01:56.000000000 +0100
96730 @@ -0,0 +1,109 @@
96731 +/*
96732 + * Bluetooth PM code for the FIC Neo1973 GSM Phone
96733 + *
96734 + * (C) 2007 by Openmoko Inc.
96735 + * Author: Harald Welte <laforge@openmoko.org>
96736 + * All rights reserved.
96737 + *
96738 + * This program is free software; you can redistribute it and/or modify
96739 + * it under the terms of the GNU General Public License version 2 as
96740 + * published by the Free Software Foundation
96741 + *
96742 + */
96743 +
96744 +#include <linux/module.h>
96745 +#include <linux/init.h>
96746 +#include <linux/kernel.h>
96747 +#include <linux/platform_device.h>
96748 +
96749 +#include <mach/hardware.h>
96750 +#include <asm/mach-types.h>
96751 +
96752 +#ifdef CONFIG_MACH_NEO1973_GTA02
96753 +#include <mach/gta02.h>
96754 +#include <linux/mfd/pcf50633/gpio.h>
96755 +
96756 +static ssize_t pm_host_read(struct device *dev, struct device_attribute *attr,
96757 +                           char *buf)
96758 +{
96759 +       return sprintf(buf, "%d\n",
96760 +                      pcf50633_gpio_get(gta02_pcf_pdata.pcf, PCF50633_GPO)
96761 +                                               == PCF50633_GPOCFG_GPOSEL_1);
96762 +}
96763 +
96764 +static ssize_t pm_host_write(struct device *dev, struct device_attribute *attr,
96765 +                            const char *buf, size_t count)
96766 +{
96767 +       unsigned long on = simple_strtoul(buf, NULL, 10);
96768 +       u8 val;
96769 +
96770 +       if (on)
96771 +               val = PCF50633_GPOCFG_GPOSEL_1;
96772 +       else
96773 +               val = PCF50633_GPOCFG_GPOSEL_0;
96774 +
96775 +
96776 +       pcf50633_gpio_set(gta02_pcf_pdata.pcf, PCF50633_GPO, val);
96777 +
96778 +       return count;
96779 +}
96780 +
96781 +static DEVICE_ATTR(hostmode, 0644, pm_host_read, pm_host_write);
96782 +
96783 +static struct attribute *neo1973_pm_host_sysfs_entries[] = {
96784 +       &dev_attr_hostmode.attr,
96785 +       NULL
96786 +};
96787 +
96788 +static struct attribute_group neo1973_pm_host_attr_group = {
96789 +       .name   = NULL,
96790 +       .attrs  = neo1973_pm_host_sysfs_entries,
96791 +};
96792 +
96793 +static int __init neo1973_pm_host_probe(struct platform_device *pdev)
96794 +{
96795 +       dev_info(&pdev->dev, "starting\n");
96796 +
96797 +       switch (machine_arch_type) {
96798 +#ifdef CONFIG_MACH_NEO1973_GTA01
96799 +       case MACH_TYPE_NEO1973_GTA01:
96800 +               return -EINVAL;
96801 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
96802 +       default:
96803 +               break;
96804 +       }
96805 +
96806 +       return sysfs_create_group(&pdev->dev.kobj, &neo1973_pm_host_attr_group);
96807 +}
96808 +
96809 +static int neo1973_pm_host_remove(struct platform_device *pdev)
96810 +{
96811 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_pm_host_attr_group);
96812 +       return 0;
96813 +}
96814 +
96815 +static struct platform_driver neo1973_pm_host_driver = {
96816 +       .probe          = neo1973_pm_host_probe,
96817 +       .remove         = neo1973_pm_host_remove,
96818 +       .driver         = {
96819 +               .name           = "neo1973-pm-host",
96820 +       },
96821 +};
96822 +
96823 +static int __devinit neo1973_pm_host_init(void)
96824 +{
96825 +       return platform_driver_register(&neo1973_pm_host_driver);
96826 +}
96827 +
96828 +static void neo1973_pm_host_exit(void)
96829 +{
96830 +       platform_driver_unregister(&neo1973_pm_host_driver);
96831 +}
96832 +
96833 +module_init(neo1973_pm_host_init);
96834 +module_exit(neo1973_pm_host_exit);
96835 +
96836 +MODULE_LICENSE("GPL");
96837 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
96838 +MODULE_DESCRIPTION("Neo1973 USB Host Power Management");
96839 +#endif
96840 Index: linux-2.6.28/drivers/misc/neo1973_pm_resume_reason.c
96841 ===================================================================
96842 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
96843 +++ linux-2.6.28/drivers/misc/neo1973_pm_resume_reason.c        2009-01-02 00:01:56.000000000 +0100
96844 @@ -0,0 +1,147 @@
96845 +/*
96846 + * Resume reason sysfs for the FIC Neo1973 GSM Phone
96847 + *
96848 + * (C) 2008 by Openmoko Inc.
96849 + * Author: Andy Green <andy@openmoko.com>
96850 + * All rights reserved.
96851 + *
96852 + * This program is free software; you can redistribute it and/or modify
96853 + * it under the terms of the GNU General Public License resume_reason 2 as
96854 + * published by the Free Software Foundation
96855 + *
96856 + */
96857 +
96858 +#include <linux/module.h>
96859 +#include <linux/init.h>
96860 +#include <linux/kernel.h>
96861 +#include <linux/platform_device.h>
96862 +#include <linux/io.h>
96863 +
96864 +#include <mach/hardware.h>
96865 +#include <asm/mach-types.h>
96866 +
96867 +#ifdef CONFIG_MACH_NEO1973_GTA02
96868 +#include <mach/gta02.h>
96869 +#include <linux/mfd/pcf50633/core.h>
96870 +#endif
96871 +
96872 +static unsigned int *gstatus4_mapped;
96873 +static char *resume_reasons[][17] = { { /* GTA01 */
96874 +       "EINT00_NULL",
96875 +       "EINT01_GSM",
96876 +       "EINT02_NULL",
96877 +       "EINT03_NULL",
96878 +       "EINT04_JACK",
96879 +       "EINT05_SDCARD",
96880 +       "EINT06_AUXKEY",
96881 +       "EINT07_HOLDKEY",
96882 +       "EINT08_NULL",
96883 +       "EINT09_NULL",
96884 +       "EINT10_NULL",
96885 +       "EINT11_NULL",
96886 +       "EINT12_NULL",
96887 +       "EINT13_NULL",
96888 +       "EINT14_NULL",
96889 +       "EINT15_NULL",
96890 +       NULL
96891 +}, { /* GTA02 */
96892 +       "EINT00_ACCEL1",
96893 +       "EINT01_GSM",
96894 +       "EINT02_BLUETOOTH",
96895 +       "EINT03_DEBUGBRD",
96896 +       "EINT04_JACK",
96897 +       "EINT05_WLAN",
96898 +       "EINT06_AUXKEY",
96899 +       "EINT07_HOLDKEY",
96900 +       "EINT08_ACCEL2",
96901 +       "EINT09_PMU",
96902 +       "EINT10_NULL",
96903 +       "EINT11_NULL",
96904 +       "EINT12_GLAMO",
96905 +       "EINT13_NULL",
96906 +       "EINT14_NULL",
96907 +       "EINT15_NULL",
96908 +       NULL
96909 +} };
96910 +
96911 +static ssize_t resume_reason_read(struct device *dev,
96912 +                                 struct device_attribute *attr,
96913 +                                 char *buf)
96914 +{
96915 +       int bit = 0;
96916 +       char *end = buf;
96917 +       int gta = !!machine_is_neo1973_gta02();
96918 +
96919 +       for (bit = 0; resume_reasons[gta][bit]; bit++) {
96920 +               if ((*gstatus4_mapped) & (1 << bit))
96921 +                       end += sprintf(end, "* %s\n", resume_reasons[gta][bit]);
96922 +               else
96923 +                       end += sprintf(end, "  %s\n", resume_reasons[gta][bit]);
96924 +
96925 +#ifdef CONFIG_MACH_NEO1973_GTA02
96926 +               if ((gta) && (bit == 9)); /* PMU */
96927 +//                     end += pcf50633_report_resumers(gta02_pcf_pdata.pcf, end);
96928 +#endif
96929 +       }
96930 +
96931 +       return end - buf;
96932 +}
96933 +
96934 +
96935 +static DEVICE_ATTR(resume_reason, 0644, resume_reason_read, NULL);
96936 +
96937 +static struct attribute *neo1973_resume_reason_sysfs_entries[] = {
96938 +       &dev_attr_resume_reason.attr,
96939 +       NULL
96940 +};
96941 +
96942 +static struct attribute_group neo1973_resume_reason_attr_group = {
96943 +       .name   = NULL,
96944 +       .attrs  = neo1973_resume_reason_sysfs_entries,
96945 +};
96946 +
96947 +static int __init neo1973_resume_reason_probe(struct platform_device *pdev)
96948 +{
96949 +       dev_info(&pdev->dev, "starting\n");
96950 +
96951 +       gstatus4_mapped = ioremap(0x560000BC /* GSTATUS4 */, 0x4);
96952 +       if (!gstatus4_mapped) {
96953 +               dev_err(&pdev->dev, "failed to ioremap() memory region\n");
96954 +               return -EINVAL;
96955 +       }
96956 +
96957 +       return sysfs_create_group(&pdev->dev.kobj,
96958 +                                           &neo1973_resume_reason_attr_group);
96959 +}
96960 +
96961 +static int neo1973_resume_reason_remove(struct platform_device *pdev)
96962 +{
96963 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_resume_reason_attr_group);
96964 +       iounmap(gstatus4_mapped);
96965 +       return 0;
96966 +}
96967 +
96968 +static struct platform_driver neo1973_resume_reason_driver = {
96969 +       .probe          = neo1973_resume_reason_probe,
96970 +       .remove         = neo1973_resume_reason_remove,
96971 +       .driver         = {
96972 +               .name           = "neo1973-resume",
96973 +       },
96974 +};
96975 +
96976 +static int __devinit neo1973_resume_reason_init(void)
96977 +{
96978 +       return platform_driver_register(&neo1973_resume_reason_driver);
96979 +}
96980 +
96981 +static void neo1973_resume_reason_exit(void)
96982 +{
96983 +       platform_driver_unregister(&neo1973_resume_reason_driver);
96984 +}
96985 +
96986 +module_init(neo1973_resume_reason_init);
96987 +module_exit(neo1973_resume_reason_exit);
96988 +
96989 +MODULE_LICENSE("GPL");
96990 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
96991 +MODULE_DESCRIPTION("Neo1973 resume_reason");
96992 Index: linux-2.6.28/drivers/misc/neo1973_pm_usbhost.c
96993 ===================================================================
96994 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
96995 +++ linux-2.6.28/drivers/misc/neo1973_pm_usbhost.c      2009-01-02 00:01:56.000000000 +0100
96996 @@ -0,0 +1,132 @@
96997 +/*
96998 + * Bluetooth PM code for the FIC Neo1973 GSM Phone
96999 + *
97000 + * (C) 2007 by OpenMoko Inc.
97001 + * Author: Harald Welte <laforge@openmoko.org>
97002 + * All rights reserved.
97003 + *
97004 + * This program is free software; you can redistribute it and/or modify
97005 + * it under the terms of the GNU General Public License version 2 as
97006 + * published by the Free Software Foundation
97007 + *
97008 + */
97009 +
97010 +#include <linux/module.h>
97011 +#include <linux/init.h>
97012 +#include <linux/kernel.h>
97013 +#include <linux/platform_device.h>
97014 +
97015 +#include <asm/hardware.h>
97016 +#include <asm/mach-types.h>
97017 +
97018 +#ifdef CONFIG_MACH_NEO1973_GTA02
97019 +#include <asm/arch/gta02.h>
97020 +#include <linux/pcf50633.h>
97021 +#endif
97022 +
97023 +static ssize_t pm_usbhost_read(struct device *dev, struct device_attribute *attr,
97024 +                      char *buf)
97025 +{
97026 +       return sprintf(buf, "%d\n",
97027 +                      pcf50633_gpio_get(pcf50633_global, PCF50633_GPO));
97028 +}
97029 +
97030 +static ssize_t pm_usbhost_write(struct device *dev, struct device_attribute *attr,
97031 +                       const char *buf, size_t count)
97032 +{
97033 +       unsigned long on = simple_strtoul(buf, NULL, 10);
97034 +
97035 +       pcf50633_gpio_set(pcf50633_global, PCF50633_GPO, on);
97036 +
97037 +       return count;
97038 +}
97039 +
97040 +static DEVICE_ATTR(hostmode, 0644, pm_usbhost_read, pm_usbhost_write);
97041 +
97042 +#ifdef CONFIG_PM
97043 +static int neo1973_usbhost_suspend(struct platform_device *pdev, pm_message_t state)
97044 +{
97045 +       dev_dbg(&pdev->dev, "suspending\n");
97046 +       /* FIXME: The PMU should save the PMU status, and the GPIO code should
97047 +        * preserve the GPIO level, so there shouldn't be anything left to do
97048 +        * for us, should there? */
97049 +
97050 +       return 0;
97051 +}
97052 +
97053 +static int neo1973_usbhost_resume(struct platform_device *pdev)
97054 +{
97055 +       dev_dbg(&pdev->dev, "resuming\n");
97056 +
97057 +       return 0;
97058 +}
97059 +#else
97060 +#define neo1973_usbhost_suspend        NULL
97061 +#define neo1973_usbhost_resume NULL
97062 +#endif
97063 +
97064 +static struct attribute *neo1973_usbhost_sysfs_entries[] = {
97065 +       &dev_attr_hostmode.attr,
97066 +       NULL
97067 +};
97068 +
97069 +static struct attribute_group neo1973_usbhost_attr_group = {
97070 +       .name   = NULL,
97071 +       .attrs  = neo1973_usbhost_sysfs_entries,
97072 +};
97073 +
97074 +static int __init neo1973_usbhost_probe(struct platform_device *pdev)
97075 +{
97076 +       dev_info(&pdev->dev, "starting\n");
97077 +
97078 +       switch (machine_arch_type) {
97079 +
97080 +#ifdef CONFIG_MACH_NEO1973_GTA01
97081 +       case MACH_TYPE_NEO1973_GTA01:
97082 +               return -EINVAL;
97083 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
97084 +
97085 +#ifdef CONFIG_MACH_NEO1973_GTA02
97086 +       case MACH_TYPE_NEO1973_GTA02:
97087 +/* race */
97088 +/*             pcf50633_gpio_set(pcf50633_global, PCF50633_GPO, 0); */
97089 +               break;
97090 +#endif /* CONFIG_MACH_NEO1973_GTA02 */
97091 +       }
97092 +
97093 +       return sysfs_create_group(&pdev->dev.kobj, &neo1973_usbhost_attr_group);
97094 +}
97095 +
97096 +static int neo1973_usbhost_remove(struct platform_device *pdev)
97097 +{
97098 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_usbhost_attr_group);
97099 +
97100 +       return 0;
97101 +}
97102 +
97103 +static struct platform_driver neo1973_usbhost_driver = {
97104 +       .probe          = neo1973_usbhost_probe,
97105 +       .remove         = neo1973_usbhost_remove,
97106 +       .suspend        = neo1973_usbhost_suspend,
97107 +       .resume         = neo1973_usbhost_resume,
97108 +       .driver         = {
97109 +               .name           = "neo1973-pm-host",
97110 +       },
97111 +};
97112 +
97113 +static int __devinit neo1973_usbhost_init(void)
97114 +{
97115 +       return platform_driver_register(&neo1973_usbhost_driver);
97116 +}
97117 +
97118 +static void neo1973_usbhost_exit(void)
97119 +{
97120 +       platform_driver_unregister(&neo1973_usbhost_driver);
97121 +}
97122 +
97123 +module_init(neo1973_usbhost_init);
97124 +module_exit(neo1973_usbhost_exit);
97125 +
97126 +MODULE_LICENSE("GPL");
97127 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
97128 +MODULE_DESCRIPTION("Neo1973 USB Host Power Management");
97129 Index: linux-2.6.28/drivers/misc/neo1973_version.c
97130 ===================================================================
97131 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
97132 +++ linux-2.6.28/drivers/misc/neo1973_version.c 2009-01-02 00:01:56.000000000 +0100
97133 @@ -0,0 +1,90 @@
97134 +/*
97135 + * PCB version sysfs for the FIC Neo1973 GSM Phone
97136 + *
97137 + * (C) 2007 by Openmoko Inc.
97138 + * Author: Andy Green <andy@openmoko.com>
97139 + * All rights reserved.
97140 + *
97141 + * This program is free software; you can redistribute it and/or modify
97142 + * it under the terms of the GNU General Public License version 2 as
97143 + * published by the Free Software Foundation
97144 + *
97145 + */
97146 +
97147 +#include <linux/module.h>
97148 +#include <linux/init.h>
97149 +#include <linux/kernel.h>
97150 +#include <linux/platform_device.h>
97151 +
97152 +#include <mach/hardware.h>
97153 +#include <asm/mach-types.h>
97154 +
97155 +#ifdef CONFIG_MACH_NEO1973_GTA02
97156 +#include <mach/gta02.h>
97157 +
97158 +static ssize_t version_read(struct device *dev, struct device_attribute *attr,
97159 +                           char *buf)
97160 +{
97161 +       return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
97162 +}
97163 +
97164 +
97165 +static DEVICE_ATTR(pcb, 0644, version_read, NULL);
97166 +
97167 +static struct attribute *neo1973_version_sysfs_entries[] = {
97168 +       &dev_attr_pcb.attr,
97169 +       NULL
97170 +};
97171 +
97172 +static struct attribute_group neo1973_version_attr_group = {
97173 +       .name   = NULL,
97174 +       .attrs  = neo1973_version_sysfs_entries,
97175 +};
97176 +
97177 +static int __init neo1973_version_probe(struct platform_device *pdev)
97178 +{
97179 +       dev_info(&pdev->dev, "starting\n");
97180 +
97181 +       switch (machine_arch_type) {
97182 +#ifdef CONFIG_MACH_NEO1973_GTA01
97183 +       case MACH_TYPE_NEO1973_GTA01:
97184 +               return -EINVAL;
97185 +#endif /* CONFIG_MACH_NEO1973_GTA01 */
97186 +       default:
97187 +               break;
97188 +       }
97189 +
97190 +       return sysfs_create_group(&pdev->dev.kobj, &neo1973_version_attr_group);
97191 +}
97192 +
97193 +static int neo1973_version_remove(struct platform_device *pdev)
97194 +{
97195 +       sysfs_remove_group(&pdev->dev.kobj, &neo1973_version_attr_group);
97196 +       return 0;
97197 +}
97198 +
97199 +static struct platform_driver neo1973_version_driver = {
97200 +       .probe          = neo1973_version_probe,
97201 +       .remove         = neo1973_version_remove,
97202 +       .driver         = {
97203 +               .name           = "neo1973-version",
97204 +       },
97205 +};
97206 +
97207 +static int __devinit neo1973_version_init(void)
97208 +{
97209 +       return platform_driver_register(&neo1973_version_driver);
97210 +}
97211 +
97212 +static void neo1973_version_exit(void)
97213 +{
97214 +       platform_driver_unregister(&neo1973_version_driver);
97215 +}
97216 +
97217 +module_init(neo1973_version_init);
97218 +module_exit(neo1973_version_exit);
97219 +
97220 +MODULE_LICENSE("GPL");
97221 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
97222 +MODULE_DESCRIPTION("Neo1973 PCB version");
97223 +#endif
97224 Index: linux-2.6.28/drivers/misc/smdk6410-sleeptest.c
97225 ===================================================================
97226 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
97227 +++ linux-2.6.28/drivers/misc/smdk6410-sleeptest.c      2009-01-02 00:01:56.000000000 +0100
97228 @@ -0,0 +1,65 @@
97229 +/* linux/drivers/misc/smdk6410-sleeptest.c
97230 + *
97231 + * Copyright 2008 Simtec Electronics
97232 + *     Ben Dooks <ben@simtec.co.uk>
97233 + *     http://armlinux.simtec.co.uk/
97234 + *
97235 + * This program is free software; you can redistribute it and/or modify
97236 + * it under the terms of the GNU General Public License version 2 as
97237 + * published by the Free Software Foundation.
97238 +*/
97239 +
97240 +#include <linux/init.h>
97241 +#include <linux/kernel.h>
97242 +#include <linux/module.h>
97243 +#include <linux/init.h>
97244 +#include <linux/gpio.h>
97245 +#include <linux/err.h>
97246 +#include <linux/interrupt.h>
97247 +
97248 +#include <plat/gpio-cfg.h>
97249 +
97250 +static irqreturn_t sleep_action(int irq, void *pw)
97251 +{
97252 +       printk(KERN_INFO "%s: irq %d\n", __func__, irq);
97253 +       return IRQ_HANDLED;
97254 +}
97255 +
97256 +static void sleep_setup(unsigned int irq, unsigned int gpio)
97257 +{
97258 +       int ret;
97259 +
97260 +       WARN_ON(s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)) < 0);
97261 +       WARN_ON(s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP) < 0);
97262 +
97263 +       ret = request_irq(irq, sleep_action, IRQF_TRIGGER_FALLING,
97264 +                         "sleep", NULL);
97265 +       if (ret < 0)
97266 +               printk(KERN_ERR "%s: request_irq() failed\n", __func__);
97267 +
97268 +       ret = set_irq_wake(irq, 1);
97269 +       if (ret < 0)
97270 +               printk(KERN_ERR "%s: set_irq_wake() failed\n", __func__);
97271 +}
97272 +
97273 +static void sleep_led(unsigned int gpio)
97274 +{
97275 +       gpio_request(gpio, "sleep led");
97276 +       gpio_direction_output(gpio, 0);
97277 +}
97278 +
97279 +static __init int smdk6410_sleeptest_init(void)
97280 +{
97281 +       sleep_setup(IRQ_EINT(10), S3C64XX_GPN(10));
97282 +       sleep_led(S3C64XX_GPN(15));
97283 +       sleep_led(S3C64XX_GPN(14));
97284 +       sleep_led(S3C64XX_GPN(13));
97285 +       sleep_led(S3C64XX_GPN(12));
97286 +
97287 +       return 0;
97288 +}
97289 +
97290 +module_init(smdk6410_sleeptest_init);
97291 +
97292 +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
97293 +MODULE_LICENSE("GPL");
97294 Index: linux-2.6.28/drivers/mmc/core/core.c
97295 ===================================================================
97296 --- linux-2.6.28.orig/drivers/mmc/core/core.c   2008-12-25 00:26:37.000000000 +0100
97297 +++ linux-2.6.28/drivers/mmc/core/core.c        2009-01-02 00:01:56.000000000 +0100
97298 @@ -57,10 +57,11 @@ static int mmc_schedule_delayed_work(str
97299  /*
97300   * Internal function. Flush all scheduled work from the MMC work queue.
97301   */
97302 -static void mmc_flush_scheduled_work(void)
97303 +void mmc_flush_scheduled_work(void)
97304  {
97305         flush_workqueue(workqueue);
97306  }
97307 +EXPORT_SYMBOL_GPL(mmc_flush_scheduled_work);
97308
97309  /**
97310   *     mmc_request_done - finish processing an MMC request
97311 @@ -495,7 +496,13 @@ void mmc_set_timing(struct mmc_host *hos
97312   */
97313  static void mmc_power_up(struct mmc_host *host)
97314  {
97315 -       int bit = fls(host->ocr_avail) - 1;
97316 +       int bit;
97317 +
97318 +       /* If ocr is set, we use it */
97319 +       if (host->ocr)
97320 +               bit = ffs(host->ocr) - 1;
97321 +       else
97322 +               bit = fls(host->ocr_avail) - 1;
97323
97324         host->ios.vdd = bit;
97325         if (mmc_host_is_spi(host)) {
97326 Index: linux-2.6.28/drivers/mmc/host/Kconfig
97327 ===================================================================
97328 --- linux-2.6.28.orig/drivers/mmc/host/Kconfig  2009-01-02 00:00:02.000000000 +0100
97329 +++ linux-2.6.28/drivers/mmc/host/Kconfig       2009-01-02 00:01:56.000000000 +0100
97330 @@ -48,6 +48,18 @@ config MMC_SDHCI_PCI
97331
97332           If unsure, say N.
97333
97334 +config MMC_SDHCI_S3C
97335 +       tristate "SDHCI support on Samsung S3C SoC"
97336 +       depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
97337 +       help
97338 +         This selects the Secure Digital Host Controller Interface (SDHCI)
97339 +         often referrered to as the HSMMC block in some of the Samsung S3C
97340 +         range of SoC.
97341 +
97342 +         If you have a controller with this interface, say Y or M here.
97343 +
97344 +         If unsure, say N.
97345 +
97346  config MMC_RICOH_MMC
97347         tristate "Ricoh MMC Controller Disabler  (EXPERIMENTAL)"
97348         depends on MMC_SDHCI_PCI
97349 Index: linux-2.6.28/drivers/mmc/host/Makefile
97350 ===================================================================
97351 --- linux-2.6.28.orig/drivers/mmc/host/Makefile 2009-01-02 00:00:02.000000000 +0100
97352 +++ linux-2.6.28/drivers/mmc/host/Makefile      2009-01-02 00:01:56.000000000 +0100
97353 @@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_PXA)         += pxamci.o
97354  obj-$(CONFIG_MMC_IMX)          += imxmmc.o
97355  obj-$(CONFIG_MMC_SDHCI)                += sdhci.o
97356  obj-$(CONFIG_MMC_SDHCI_PCI)    += sdhci-pci.o
97357 +obj-$(CONFIG_MMC_SDHCI_S3C)    += sdhci-s3c.o
97358  obj-$(CONFIG_MMC_RICOH_MMC)    += ricoh_mmc.o
97359  obj-$(CONFIG_MMC_WBSD)         += wbsd.o
97360  obj-$(CONFIG_MMC_AU1X)         += au1xmmc.o
97361 Index: linux-2.6.28/drivers/mmc/host/s3cmci.c
97362 ===================================================================
97363 --- linux-2.6.28.orig/drivers/mmc/host/s3cmci.c 2008-12-25 00:26:37.000000000 +0100
97364 +++ linux-2.6.28/drivers/mmc/host/s3cmci.c      2009-01-02 00:01:56.000000000 +0100
97365 @@ -2,6 +2,7 @@
97366   *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
97367   *
97368   *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
97369 + *  Copyright (C) 2007 Harald Welte <laforge@gnumonks.org>
97370   *
97371   * Current driver maintained by Ben Dooks and Simtec Electronics
97372   *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
97373 @@ -25,7 +26,15 @@
97374  #include <mach/regs-sdi.h>
97375  #include <mach/regs-gpio.h>
97376
97377 -#include <asm/plat-s3c24xx/mci.h>
97378 +#include <plat/mci.h>
97379 +
97380 +#include <asm/dma.h>
97381 +#include <asm/dma-mapping.h>
97382 +
97383 +#include <asm/io.h>
97384 +#include <mach/regs-gpio.h>
97385 +#include <mach/mci.h>
97386 +#include <mach/dma.h>
97387
97388  #include "s3cmci.h"
97389
97390 @@ -47,6 +56,9 @@ static const int dbgmap_err   = dbg_fail
97391  static const int dbgmap_info  = dbg_info | dbg_conf;
97392  static const int dbgmap_debug = dbg_err | dbg_debug;
97393
97394 +static int f_max = -1; /* override maximum frequency limit */
97395 +static int persist; /* keep interface alive across suspend/resume */
97396 +
97397  #define dbg(host, channels, args...)             \
97398         do {                                      \
97399         if (dbgmap_err & channels)                \
97400 @@ -280,8 +292,11 @@ static void do_pio_read(struct s3cmci_ho
97401                  * an even multiple of 4. */
97402                 if (fifo >= host->pio_bytes)
97403                         fifo = host->pio_bytes;
97404 -               else
97405 +               else {
97406                         fifo -= fifo & 3;
97407 +                       if (!fifo)
97408 +                               break;
97409 +               }
97410
97411                 host->pio_bytes -= fifo;
97412                 host->pio_count += fifo;
97413 @@ -353,8 +368,11 @@ static void do_pio_write(struct s3cmci_h
97414                  * words, so round down to an even multiple of 4. */
97415                 if (fifo >= host->pio_bytes)
97416                         fifo = host->pio_bytes;
97417 -               else
97418 +               else {
97419                         fifo -= fifo & 3;
97420 +                       if (!fifo)
97421 +                               break;
97422 +               }
97423
97424                 host->pio_bytes -= fifo;
97425                 host->pio_count += fifo;
97426 @@ -373,7 +391,6 @@ static void pio_tasklet(unsigned long da
97427  {
97428         struct s3cmci_host *host = (struct s3cmci_host *) data;
97429
97430 -
97431         disable_irq(host->irq);
97432
97433         if (host->pio_active == XFER_WRITE)
97434 @@ -614,7 +631,6 @@ irq_out:
97435
97436         spin_unlock_irqrestore(&host->complete_lock, iflags);
97437         return IRQ_HANDLED;
97438 -
97439  }
97440
97441  /*
97442 @@ -1027,6 +1043,7 @@ static void s3cmci_send_request(struct m
97443                         dbg(host, dbg_err, "data prepare error %d\n", res);
97444                         cmd->error = res;
97445                         cmd->data->error = res;
97446 +                       cmd->data->error = -EIO;
97447
97448                         mmc_request_done(mmc, mrq);
97449                         return;
97450 @@ -1264,10 +1281,8 @@ static int __devinit s3cmci_probe(struct
97451         host->is2440    = is2440;
97452
97453         host->pdata = pdev->dev.platform_data;
97454 -       if (!host->pdata) {
97455 -               pdev->dev.platform_data = &s3cmci_def_pdata;
97456 +       if (!host->pdata)
97457                 host->pdata = &s3cmci_def_pdata;
97458 -       }
97459
97460         spin_lock_init(&host->complete_lock);
97461         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
97462 @@ -1380,6 +1395,18 @@ static int __devinit s3cmci_probe(struct
97463         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
97464         mmc->f_max      = host->clk_rate / host->clk_div;
97465
97466 +       if (f_max >= 0) {
97467 +               unsigned f = f_max;
97468 +
97469 +               if (f < mmc->f_min)
97470 +                       f = mmc->f_min;
97471 +               if (mmc->f_max > f) {
97472 +                       dev_info(&pdev->dev, "f_max lowered from %u to %u Hz\n",
97473 +                           mmc->f_max, f);
97474 +                       mmc->f_max = f;
97475 +               }
97476 +       }
97477 +
97478         if (host->pdata->ocr_avail)
97479                 mmc->ocr_avail = host->pdata->ocr_avail;
97480
97481 @@ -1492,18 +1519,60 @@ static int __devinit s3cmci_2440_probe(s
97482
97483  #ifdef CONFIG_PM
97484
97485 +static int save_regs(struct mmc_host *mmc)
97486 +{
97487 +       struct s3cmci_host *host = mmc_priv(mmc);
97488 +       unsigned long flags;
97489 +       unsigned from;
97490 +       u32 *to = host->saved;
97491 +
97492 +       mmc_flush_scheduled_work();
97493 +
97494 +       local_irq_save(flags);
97495 +       for (from = S3C2410_SDICON; from != S3C2410_SDIIMSK+4; from += 4)
97496 +               if (from != host->sdidata)
97497 +                       *to++ = readl(host->base + from);
97498 +       BUG_ON(to-host->saved != ARRAY_SIZE(host->saved));
97499 +       local_irq_restore(flags);
97500 +
97501 +       return 0;
97502 +}
97503 +
97504 +static int restore_regs(struct mmc_host *mmc)
97505 +{
97506 +       struct s3cmci_host *host = mmc_priv(mmc);
97507 +       unsigned long flags;
97508 +       unsigned to;
97509 +       u32 *from = host->saved;
97510 +
97511 +       /*
97512 +        * Before we begin with the necromancy, make sure we don't
97513 +        * inadvertently start something we'll regret microseconds later.
97514 +        */
97515 +       from[S3C2410_SDICMDCON - S3C2410_SDICON] = 0;
97516 +
97517 +       local_irq_save(flags);
97518 +       for (to = S3C2410_SDICON; to != S3C2410_SDIIMSK+4; to += 4)
97519 +               if (to != host->sdidata)
97520 +                       writel(*from++, host->base + to);
97521 +       BUG_ON(from-host->saved != ARRAY_SIZE(host->saved));
97522 +       local_irq_restore(flags);
97523 +
97524 +       return 0;
97525 +}
97526 +
97527  static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
97528  {
97529         struct mmc_host *mmc = platform_get_drvdata(dev);
97530
97531 -       return  mmc_suspend_host(mmc, state);
97532 +       return persist ? save_regs(mmc) : mmc_suspend_host(mmc, state);
97533  }
97534
97535  static int s3cmci_resume(struct platform_device *dev)
97536  {
97537         struct mmc_host *mmc = platform_get_drvdata(dev);
97538
97539 -       return mmc_resume_host(mmc);
97540 +       return persist ? restore_regs(mmc) : mmc_resume_host(mmc);
97541  }
97542
97543  #else /* CONFIG_PM */
97544 @@ -1561,9 +1630,13 @@ static void __exit s3cmci_exit(void)
97545  module_init(s3cmci_init);
97546  module_exit(s3cmci_exit);
97547
97548 +module_param(f_max, int, 0644);
97549 +module_param(persist, int, 0644);
97550 +
97551  MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
97552  MODULE_LICENSE("GPL v2");
97553  MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
97554  MODULE_ALIAS("platform:s3c2410-sdi");
97555  MODULE_ALIAS("platform:s3c2412-sdi");
97556  MODULE_ALIAS("platform:s3c2440-sdi");
97557 +
97558 Index: linux-2.6.28/drivers/mmc/host/s3cmci.h
97559 ===================================================================
97560 --- linux-2.6.28.orig/drivers/mmc/host/s3cmci.h 2008-12-25 00:26:37.000000000 +0100
97561 +++ linux-2.6.28/drivers/mmc/host/s3cmci.h      2009-01-02 00:01:56.000000000 +0100
97562 @@ -8,6 +8,9 @@
97563   * published by the Free Software Foundation.
97564   */
97565
97566 +
97567 +#include <mach/regs-sdi.h>
97568 +
97569  /* FIXME: DMA Resource management ?! */
97570  #define S3CMCI_DMA 0
97571
97572 @@ -68,6 +71,13 @@ struct s3cmci_host {
97573         unsigned int            ccnt, dcnt;
97574         struct tasklet_struct   pio_tasklet;
97575
97576 +       /*
97577 +        * Here's where we save the registers during suspend. Note that we skip
97578 +        * SDIDATA, which is at different positions on 2410 and 2440, so
97579 +        * there's no "+1" in the array size.
97580 +        */
97581 +       u32                     saved[(S3C2410_SDIIMSK-S3C2410_SDICON)/4];
97582 +
97583  #ifdef CONFIG_CPU_FREQ
97584         struct notifier_block   freq_transition;
97585  #endif
97586 Index: linux-2.6.28/drivers/mmc/host/sdhci.c
97587 ===================================================================
97588 --- linux-2.6.28.orig/drivers/mmc/host/sdhci.c  2008-12-25 00:26:37.000000000 +0100
97589 +++ linux-2.6.28/drivers/mmc/host/sdhci.c       2009-01-02 00:01:56.000000000 +0100
97590 @@ -73,6 +73,11 @@ static void sdhci_dumpregs(struct sdhci_
97591                 readl(host->ioaddr + SDHCI_CAPABILITIES),
97592                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
97593
97594 +       if (host->flags & SDHCI_USE_ADMA)
97595 +               printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
97596 +                      readl(host->ioaddr + SDHCI_ADMA_ERROR),
97597 +                      readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97598 +
97599         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
97600  }
97601
97602 @@ -731,6 +736,23 @@ static void sdhci_set_transfer_mode(stru
97603         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
97604  }
97605
97606 +static void shdci_check_dma_overrun(struct sdhci_host *host, struct mmc_data *data)
97607 +{
97608 +       u32 dma_pos = readl(host->ioaddr + SDHCI_DMA_ADDRESS);
97609 +       u32 dma_start = sg_dma_address(data->sg);
97610 +       u32 dma_end = dma_start + data->sg->length;
97611 +
97612 +       /* Test whether we ended up moving more data than
97613 +        * was originally requested. */
97614 +
97615 +       if (dma_pos <= dma_end)
97616 +               return;
97617 +
97618 +       printk(KERN_ERR "%s: dma overrun, dma %08x, req %08x..%08x\n",
97619 +              mmc_hostname(host->mmc), dma_pos,
97620 +              dma_start, dma_end);
97621 +}
97622 +
97623  static void sdhci_finish_data(struct sdhci_host *host)
97624  {
97625         struct mmc_data *data;
97626 @@ -744,6 +766,8 @@ static void sdhci_finish_data(struct sdh
97627                 if (host->flags & SDHCI_USE_ADMA)
97628                         sdhci_adma_table_post(host, data);
97629                 else {
97630 +                       shdci_check_dma_overrun(host, data);
97631 +
97632                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
97633                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
97634                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
97635 @@ -883,13 +907,18 @@ static void sdhci_finish_command(struct
97636
97637  static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
97638  {
97639 +       if (clock == host->clock)
97640 +               return;
97641 +
97642 +       host->ops->change_clock(host, clock);
97643 +}
97644 +
97645 +void sdhci_change_clock(struct sdhci_host *host, unsigned int clock)
97646 +{
97647         int div;
97648         u16 clk;
97649         unsigned long timeout;
97650
97651 -       if (clock == host->clock)
97652 -               return;
97653 -
97654         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
97655
97656         if (clock == 0)
97657 @@ -926,6 +955,8 @@ out:
97658         host->clock = clock;
97659  }
97660
97661 +EXPORT_SYMBOL_GPL(sdhci_set_clock);
97662 +
97663  static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
97664  {
97665         u8 pwr;
97666 @@ -999,12 +1030,13 @@ static void sdhci_request(struct mmc_hos
97667  #endif
97668
97669         host->mrq = mrq;
97670 -
97671 +/*
97672         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
97673                 || (host->flags & SDHCI_DEVICE_DEAD)) {
97674                 host->mrq->cmd->error = -ENOMEDIUM;
97675                 tasklet_schedule(&host->finish_tasklet);
97676         } else
97677 +*/
97678                 sdhci_send_command(host, mrq->cmd);
97679
97680         mmiowb();
97681 @@ -1033,6 +1065,9 @@ static void sdhci_set_ios(struct mmc_hos
97682                 sdhci_init(host);
97683         }
97684
97685 +       if (host->ops->set_ios)
97686 +               host->ops->set_ios(host, ios);
97687 +
97688         sdhci_set_clock(host, ios->clock);
97689
97690         if (ios->power_mode == MMC_POWER_OFF)
97691 @@ -1136,7 +1171,7 @@ static void sdhci_tasklet_card(unsigned
97692         host = (struct sdhci_host*)param;
97693
97694         spin_lock_irqsave(&host->lock, flags);
97695 -
97696 +/*
97697         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
97698                 if (host->mrq) {
97699                         printk(KERN_ERR "%s: Card removed during transfer!\n",
97700 @@ -1151,7 +1186,7 @@ static void sdhci_tasklet_card(unsigned
97701                         tasklet_schedule(&host->finish_tasklet);
97702                 }
97703         }
97704 -
97705 +*/
97706         spin_unlock_irqrestore(&host->lock, flags);
97707
97708         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
97709 @@ -1283,11 +1318,24 @@ static void sdhci_cmd_irq(struct sdhci_h
97710          *       controllers.
97711          */
97712         if (host->cmd->flags & MMC_RSP_BUSY) {
97713 +               u32 present;
97714 +
97715                 if (host->cmd->data)
97716                         DBG("Cannot wait for busy signal when also "
97717                                 "doing a data transfer");
97718 -               else
97719 +               else if (!(host->quirks & SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY))
97720                         return;
97721 +
97722 +               /* The Samsung SDHCI does not seem to provide an INT_DATA_END
97723 +                * when the system goes non-busy, so check the state of the
97724 +                * transfer by reading SDHCI_PRESENT_STATE to see if the
97725 +                * controller is ready
97726 +                */
97727 +
97728 +               present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
97729 +               DBG("busy? present %08x, intstat %08x\n", present, intmask);
97730 +
97731 +               /* fall through and take the SDHCI_INT_RESPONSE */
97732         }
97733
97734         if (intmask & SDHCI_INT_RESPONSE)
97735 @@ -1604,17 +1652,23 @@ int sdhci_add_host(struct sdhci_host *ho
97736                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
97737         }
97738
97739 -       host->max_clk =
97740 -               (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
97741 +       if (host->ops->get_max_clock)
97742 +               host->max_clk = host->ops->get_max_clock(host);
97743 +       else {
97744 +               host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
97745 +               host->max_clk *= 1000000;
97746 +       }
97747         if (host->max_clk == 0) {
97748                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
97749                         "frequency.\n", mmc_hostname(mmc));
97750                 return -ENODEV;
97751         }
97752 -       host->max_clk *= 1000000;
97753
97754 -       host->timeout_clk =
97755 -               (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
97756 +       if (host->ops->get_timeout_clock)
97757 +               host->timeout_clk = host->ops->get_timeout_clock(host);
97758 +       else
97759 +               host->timeout_clk =
97760 +                       (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
97761         if (host->timeout_clk == 0) {
97762                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
97763                         "frequency.\n", mmc_hostname(mmc));
97764 Index: linux-2.6.28/drivers/mmc/host/sdhci.h
97765 ===================================================================
97766 --- linux-2.6.28.orig/drivers/mmc/host/sdhci.h  2008-12-25 00:26:37.000000000 +0100
97767 +++ linux-2.6.28/drivers/mmc/host/sdhci.h       2009-01-02 00:01:56.000000000 +0100
97768 @@ -57,6 +57,7 @@
97769  #define  SDHCI_DATA_AVAILABLE  0x00000800
97770  #define  SDHCI_CARD_PRESENT    0x00010000
97771  #define  SDHCI_WRITE_PROTECT   0x00080000
97772 +#define  SDHCI_DATA_BIT(x)     (1 << ((x) + 20))
97773
97774  #define SDHCI_HOST_CONTROL     0x28
97775  #define  SDHCI_CTRL_LED                0x01
97776 @@ -210,6 +211,8 @@ struct sdhci_host {
97777  #define SDHCI_QUIRK_BROKEN_SMALL_PIO                   (1<<13)
97778  /* Controller supports high speed but doesn't have the caps bit set */
97779  #define SDHCI_QUIRK_FORCE_HIGHSPEED                    (1<<14)
97780 +/* Controller does not provide transfer-complete interrupt when not busy */
97781 +#define SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY               (1<<15)
97782
97783         int                     irq;            /* Device IRQ */
97784         void __iomem *          ioaddr;         /* Mapped address */
97785 @@ -267,6 +270,14 @@ struct sdhci_host {
97786
97787  struct sdhci_ops {
97788         int             (*enable_dma)(struct sdhci_host *host);
97789 +       unsigned int    (*get_max_clock)(struct sdhci_host *host);
97790 +       unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
97791 +
97792 +       void            (*change_clock)(struct sdhci_host *host,
97793 +                                       unsigned int clock);
97794 +
97795 +       void            (*set_ios)(struct sdhci_host *host,
97796 +                                  struct mmc_ios *ios);
97797  };
97798
97799
97800 @@ -274,6 +285,8 @@ extern struct sdhci_host *sdhci_alloc_ho
97801         size_t priv_size);
97802  extern void sdhci_free_host(struct sdhci_host *host);
97803
97804 +extern void sdhci_change_clock(struct sdhci_host *host, unsigned int clock);
97805 +
97806  static inline void *sdhci_priv(struct sdhci_host *host)
97807  {
97808         return (void *)host->private;
97809 Index: linux-2.6.28/drivers/mmc/host/sdhci-pci.c
97810 ===================================================================
97811 --- linux-2.6.28.orig/drivers/mmc/host/sdhci-pci.c      2008-12-25 00:26:37.000000000 +0100
97812 +++ linux-2.6.28/drivers/mmc/host/sdhci-pci.c   2009-01-02 00:01:56.000000000 +0100
97813 @@ -391,6 +391,7 @@ static int sdhci_pci_enable_dma(struct s
97814
97815  static struct sdhci_ops sdhci_pci_ops = {
97816         .enable_dma     = sdhci_pci_enable_dma,
97817 +       .change_clock   = sdhci_change_clock,
97818  };
97819
97820  /*****************************************************************************\
97821 Index: linux-2.6.28/drivers/mmc/host/sdhci-s3c.c
97822 ===================================================================
97823 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
97824 +++ linux-2.6.28/drivers/mmc/host/sdhci-s3c.c   2009-01-02 00:01:56.000000000 +0100
97825 @@ -0,0 +1,419 @@
97826 +/* linux/drivers/mmc/host/sdhci-s3c.c
97827 + *
97828 + * Copyright 2008 Openmoko Inc.
97829 + * Copyright 2008 Simtec Electronics
97830 + *      Ben Dooks <ben@simtec.co.uk>
97831 + *      http://armlinux.simtec.co.uk/
97832 + *
97833 + * SDHCI (HSMMC) support for Samsung SoC
97834 + *
97835 + * This program is free software; you can redistribute it and/or modify
97836 + * it under the terms of the GNU General Public License version 2 as
97837 + * published by the Free Software Foundation.
97838 + */
97839 +
97840 +#include <linux/delay.h>
97841 +#include <linux/dma-mapping.h>
97842 +#include <linux/platform_device.h>
97843 +#include <linux/clk.h>
97844 +#include <linux/io.h>
97845 +
97846 +#include <linux/mmc/host.h>
97847 +
97848 +#include <plat/regs-sdhci.h>
97849 +#include <plat/sdhci.h>
97850 +
97851 +#include "sdhci.h"
97852 +
97853 +#define MAX_BUS_CLK    (4)
97854 +
97855 +struct sdhci_s3c {
97856 +       struct sdhci_host       *host;
97857 +       struct platform_device  *pdev;
97858 +       struct resource         *ioarea;
97859 +       struct s3c_sdhci_platdata *pdata;
97860 +       unsigned int            cur_clk;
97861 +
97862 +       struct clk              *clk_io;        /* clock for io bus */
97863 +       struct clk              *clk_bus[MAX_BUS_CLK];
97864 +};
97865 +
97866 +static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
97867 +{
97868 +       return sdhci_priv(host);
97869 +}
97870 +
97871 +static u32 get_curclk(u32 ctrl2)
97872 +{
97873 +       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
97874 +       ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
97875 +
97876 +       return ctrl2;
97877 +}
97878 +
97879 +static void sdhci_s3c_check_sclk(struct sdhci_host *host)
97880 +{
97881 +       struct sdhci_s3c *ourhost = to_s3c(host);
97882 +       u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
97883 +
97884 +       if (get_curclk(tmp) != ourhost->cur_clk) {
97885 +               dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
97886 +
97887 +               tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
97888 +               tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
97889 +               writel(tmp, host->ioaddr + 0x80);
97890 +       }
97891 +}
97892 +
97893 +static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
97894 +{
97895 +       struct sdhci_s3c *ourhost = to_s3c(host);
97896 +       struct clk *busclk;
97897 +       unsigned int rate, max;
97898 +       int clk;
97899 +
97900 +       /* note, a reset will reset the clock source */
97901 +
97902 +       sdhci_s3c_check_sclk(host);
97903 +
97904 +       for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
97905 +               busclk = ourhost->clk_bus[clk];
97906 +               if (!busclk)
97907 +                       continue;
97908 +
97909 +               rate = clk_get_rate(busclk);
97910 +               if (rate > max)
97911 +                       max = rate;
97912 +       }
97913 +
97914 +       return max;
97915 +}
97916 +
97917 +static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
97918 +{
97919 +       return sdhci_s3c_get_max_clk(host) / 1000000;
97920 +}
97921 +
97922 +static void sdhci_s3c_set_ios(struct sdhci_host *host,
97923 +                             struct mmc_ios *ios)
97924 +{
97925 +       struct sdhci_s3c *ourhost = to_s3c(host);
97926 +       struct s3c_sdhci_platdata *pdata = ourhost->pdata;
97927 +       int width;
97928 +
97929 +       sdhci_s3c_check_sclk(host);
97930 +
97931 +       if (ios->power_mode != MMC_POWER_OFF) {
97932 +               switch (ios->bus_width) {
97933 +               case MMC_BUS_WIDTH_4:
97934 +                       width = 4;
97935 +                       break;
97936 +               case MMC_BUS_WIDTH_1:
97937 +                       width = 1;
97938 +                       break;
97939 +               default:
97940 +                       BUG();
97941 +               }
97942 +
97943 +               if (pdata->cfg_gpio)
97944 +                       pdata->cfg_gpio(ourhost->pdev, width);
97945 +       }
97946 +
97947 +       if (pdata->cfg_card)
97948 +               pdata->cfg_card(ourhost->pdev, host->ioaddr,
97949 +                               ios, host->mmc->card);
97950 +}
97951 +
97952 +static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
97953 +                                            unsigned int src,
97954 +                                            unsigned int wanted)
97955 +{
97956 +       unsigned long rate;
97957 +       struct clk *clksrc = ourhost->clk_bus[src];
97958 +       int div;
97959 +
97960 +       if (!clksrc)
97961 +               return UINT_MAX;
97962 +
97963 +       rate = clk_get_rate(clksrc);
97964 +
97965 +       for (div = 1; div < 256; div *= 2) {
97966 +               if ((rate / div) <= wanted)
97967 +                       break;
97968 +       }
97969 +
97970 +       dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
97971 +               src, rate, wanted, rate / div);
97972 +
97973 +       return (wanted - (rate / div));
97974 +}
97975 +
97976 +static void sdhci_s3c_change_clock(struct sdhci_host *host, unsigned int clock)
97977 +{
97978 +       struct sdhci_s3c *ourhost = to_s3c(host);
97979 +       unsigned int best = UINT_MAX;
97980 +       unsigned int delta;
97981 +       int best_src = 0;
97982 +       int src;
97983 +       u32 ctrl;
97984 +
97985 +       for (src = 0; src < MAX_BUS_CLK; src++) {
97986 +               delta = sdhci_s3c_consider_clock(ourhost, src, clock);
97987 +               if (delta < best) {
97988 +                       best = delta;
97989 +                       best_src = src;
97990 +               }
97991 +       }
97992 +
97993 +       dev_dbg(&ourhost->pdev->dev,
97994 +               "selected source %d, clock %d, delta %d\n",
97995 +                best_src, clock, best);
97996 +
97997 +       /* turn clock off to card before changing clock source */
97998 +       writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
97999 +
98000 +       /* select the new clock source */
98001 +
98002 +       if (ourhost->cur_clk != best_src) {
98003 +               struct clk *clk = ourhost->clk_bus[best_src];
98004 +
98005 +               ourhost->cur_clk = best_src;
98006 +               host->max_clk = clk_get_rate(clk);
98007 +               host->timeout_clk = host->max_clk / 1000000;
98008 +
98009 +               ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
98010 +               ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
98011 +               ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
98012 +               writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
98013 +       }
98014 +
98015 +       sdhci_change_clock(host, clock);
98016 +}
98017 +
98018 +static struct sdhci_ops sdhci_s3c_ops = {
98019 +       .get_max_clock          = sdhci_s3c_get_max_clk,
98020 +       .get_timeout_clock      = sdhci_s3c_get_timeout_clk,
98021 +       .change_clock           = sdhci_s3c_change_clock,
98022 +       .set_ios                = sdhci_s3c_set_ios,
98023 +};
98024 +
98025 +/*
98026 + * call this when you need sd stack to recognize insertion or removal of card
98027 + * that can't be told by SDHCI regs
98028 + */
98029 +
98030 +void sdhci_s3c_force_presence_change(struct platform_device *pdev)
98031 +{
98032 +       struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
98033 +
98034 +       dev_info(&pdev->dev, "sdhci_s3c_force_presence_change called\n");
98035 +       mmc_detect_change(pdata->sdhci_host->mmc, msecs_to_jiffies(200));
98036 +}
98037 +EXPORT_SYMBOL_GPL(sdhci_s3c_force_presence_change);
98038 +
98039 +
98040 +static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
98041 +{
98042 +       struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
98043 +       struct device *dev = &pdev->dev;
98044 +       struct sdhci_host *host;
98045 +       struct sdhci_s3c *sc;
98046 +       struct resource *res;
98047 +       int ret, irq, ptr, clks;
98048 +
98049 +       if (!pdata) {
98050 +               dev_err(dev, "no device data specified\n");
98051 +               return -ENOENT;
98052 +       }
98053 +
98054 +       irq = platform_get_irq(pdev, 0);
98055 +       if (irq < 0) {
98056 +               dev_err(dev, "no irq specified\n");
98057 +               return irq;
98058 +       }
98059 +
98060 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
98061 +       if (!res) {
98062 +               dev_err(dev, "no memory specified\n");
98063 +               return -ENOENT;
98064 +       }
98065 +
98066 +       host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
98067 +       if (IS_ERR(host)) {
98068 +               dev_err(dev, "sdhci_alloc_host() failed\n");
98069 +               return PTR_ERR(host);
98070 +       }
98071 +
98072 +       pdata->sdhci_host = host;
98073 +
98074 +       sc = sdhci_priv(host);
98075 +
98076 +       sc->host = host;
98077 +       sc->pdev = pdev;
98078 +       sc->pdata = pdata;
98079 +
98080 +       platform_set_drvdata(pdev, host);
98081 +
98082 +       sc->clk_io = clk_get(dev, "hsmmc");
98083 +       if (IS_ERR(sc->clk_io)) {
98084 +               dev_err(dev, "failed to get io clock\n");
98085 +               ret = PTR_ERR(sc->clk_io);
98086 +               goto err_io_clk;
98087 +       }
98088 +
98089 +       /* enable the local io clock and keep it running for the moment. */
98090 +       clk_enable(sc->clk_io);
98091 +
98092 +       for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
98093 +               struct clk *clk;
98094 +               char *name = pdata->clocks[ptr];
98095 +
98096 +               if (name == NULL)
98097 +                       continue;
98098 +
98099 +               clk = clk_get(dev, name);
98100 +               if (IS_ERR(clk)) {
98101 +                       dev_err(dev, "failed to get clock %s\n", name);
98102 +                       continue;
98103 +               }
98104 +
98105 +               clks++;
98106 +               sc->clk_bus[ptr] = clk;
98107 +               clk_enable(clk);
98108 +
98109 +               dev_info(dev, "clock source %d: %s (%ld Hz)\n",
98110 +                        ptr, name, clk_get_rate(clk));
98111 +       }
98112 +
98113 +       if (clks == 0) {
98114 +               dev_err(dev, "failed to find any bus clocks\n");
98115 +               ret = -ENOENT;
98116 +               goto err_no_busclks;
98117 +       }
98118 +
98119 +       sc->ioarea = request_mem_region(res->start, resource_size(res),
98120 +                                       mmc_hostname(host->mmc));
98121 +       if (!sc->ioarea) {
98122 +               dev_err(dev, "failed to reserve register area\n");
98123 +               ret = -ENXIO;
98124 +               goto err_req_regs;
98125 +       }
98126 +
98127 +       host->ioaddr = ioremap_nocache(res->start, resource_size(res));
98128 +       if (!host->ioaddr) {
98129 +               dev_err(dev, "failed to map registers\n");
98130 +               ret = -ENXIO;
98131 +               goto err_req_regs;
98132 +       }
98133 +
98134 +       /* Ensure we have minimal gpio selected CMD/CLK/Detect */
98135 +       if (pdata->cfg_gpio)
98136 +               pdata->cfg_gpio(pdev, 0);
98137 +
98138 +       sdhci_s3c_check_sclk(host);
98139 +
98140 +       host->hw_name = "samsung-hsmmc";
98141 +       host->ops = &sdhci_s3c_ops;
98142 +       host->quirks = 0;
98143 +       host->irq = irq;
98144 +
98145 +       /* Setup quirks for the controller */
98146 +
98147 +       /* Currently with ADMA enabled we are getting some length
98148 +        * interrupts that are not being dealt with, do disable
98149 +        * ADMA until this is sorted out. */
98150 +       host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
98151 +       host->quirks |= SDHCI_QUIRK_32BIT_ADMA_SIZE;
98152 +
98153 +       /* It seems we do not get an DATA transfer complete on non-busy
98154 +        * transfers, not sure if this is a problem with this specific
98155 +        * SDHCI block, or a missing configuration that needs to be set. */
98156 +       host->quirks |= SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY;
98157 +
98158 +       host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
98159 +                        SDHCI_QUIRK_32BIT_DMA_SIZE);
98160 +
98161 +       ret = sdhci_add_host(host);
98162 +       if (ret) {
98163 +               dev_err(dev, "sdhci_add_host() failed\n");
98164 +               goto err_add_host;
98165 +       }
98166 +
98167 +       return 0;
98168 +
98169 + err_add_host:
98170 +       release_resource(sc->ioarea);
98171 +       kfree(sc->ioarea);
98172 +
98173 + err_req_regs:
98174 +       for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
98175 +               clk_disable(sc->clk_bus[ptr]);
98176 +               clk_put(sc->clk_bus[ptr]);
98177 +       }
98178 +
98179 + err_no_busclks:
98180 +       clk_disable(sc->clk_io);
98181 +       clk_put(sc->clk_io);
98182 +
98183 + err_io_clk:
98184 +       sdhci_free_host(host);
98185 +
98186 +       return ret;
98187 +}
98188 +
98189 +static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
98190 +{
98191 +       return 0;
98192 +}
98193 +
98194 +#ifdef CONFIG_PM
98195 +
98196 +static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm)
98197 +{
98198 +       struct sdhci_host *host = platform_get_drvdata(dev);
98199 +
98200 +       sdhci_suspend_host(host, pm);
98201 +       return 0;
98202 +}
98203 +
98204 +static int sdhci_s3c_resume(struct platform_device *dev)
98205 +{
98206 +       struct sdhci_host *host = platform_get_drvdata(dev);
98207 +
98208 +       sdhci_resume_host(host);
98209 +       return 0;
98210 +}
98211 +
98212 +#else
98213 +#define sdhci_s3c_suspend NULL
98214 +#define sdhci_s3c_resume NULL
98215 +#endif
98216 +
98217 +static struct platform_driver sdhci_s3c_driver = {
98218 +       .probe          = sdhci_s3c_probe,
98219 +       .remove         = __devexit_p(sdhci_s3c_remove),
98220 +       .suspend        = sdhci_s3c_suspend,
98221 +       .resume         = sdhci_s3c_resume,
98222 +       .driver         = {
98223 +               .owner  = THIS_MODULE,
98224 +               .name   = "s3c-sdhci",
98225 +       },
98226 +};
98227 +
98228 +static int __init sdhci_s3c_init(void)
98229 +{
98230 +       return platform_driver_register(&sdhci_s3c_driver);
98231 +}
98232 +
98233 +static void __exit sdhci_s3c_exit(void)
98234 +{
98235 +       platform_driver_unregister(&sdhci_s3c_driver);
98236 +}
98237 +
98238 +module_init(sdhci_s3c_init);
98239 +module_exit(sdhci_s3c_exit);
98240 +
98241 +MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
98242 +MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
98243 +MODULE_LICENSE("GPL v2");
98244 +MODULE_ALIAS("platform:s3c-sdhci");
98245 Index: linux-2.6.28/drivers/mtd/nand/s3c2410.c
98246 ===================================================================
98247 --- linux-2.6.28.orig/drivers/mtd/nand/s3c2410.c        2008-12-25 00:26:37.000000000 +0100
98248 +++ linux-2.6.28/drivers/mtd/nand/s3c2410.c     2009-01-02 00:01:56.000000000 +0100
98249 @@ -45,8 +45,8 @@
98250
98251  #include <asm/io.h>
98252
98253 -#include <asm/plat-s3c/regs-nand.h>
98254 -#include <asm/plat-s3c/nand.h>
98255 +#include <plat/regs-nand.h>
98256 +#include <plat/nand.h>
98257
98258  #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
98259  static int hardware_ecc = 1;
98260 @@ -231,8 +231,6 @@ static int s3c2410_nand_setrate(struct s
98261                 BUG();
98262         }
98263
98264 -       dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
98265 -
98266         local_irq_save(flags);
98267
98268         cfg = readl(info->regs + S3C2410_NFCONF);
98269 @@ -240,6 +238,8 @@ static int s3c2410_nand_setrate(struct s
98270         cfg |= set;
98271         writel(cfg, info->regs + S3C2410_NFCONF);
98272
98273 +       dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
98274 +
98275         local_irq_restore(flags);
98276
98277         return 0;
98278 @@ -438,7 +438,7 @@ static int s3c2410_nand_correct_data(str
98279         if ((diff0 & ~(1<<fls(diff0))) == 0)
98280                 return 1;
98281
98282 -       return -1;
98283 +       return -EBADMSG;
98284  }
98285
98286  /* ECC functions
98287 @@ -530,7 +530,12 @@ static void s3c2410_nand_read_buf(struct
98288  static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
98289  {
98290         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
98291 +       u8 *ptr = buf + (len & ~3);
98292 +       int i;
98293 +
98294         readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
98295 +       for (i = 0; i != (len & 3); i++)
98296 +               ptr[i] = readb(info->regs + S3C2440_NFDATA);
98297  }
98298
98299  static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
98300 @@ -645,17 +650,31 @@ static int s3c2410_nand_remove(struct pl
98301  }
98302
98303  #ifdef CONFIG_MTD_PARTITIONS
98304 +const char *part_probes[] = { "cmdlinepart", NULL };
98305  static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
98306                                       struct s3c2410_nand_mtd *mtd,
98307                                       struct s3c2410_nand_set *set)
98308  {
98309 +       struct mtd_partition *part_info;
98310 +       int nr_part = 0;
98311 +
98312         if (set == NULL)
98313                 return add_mtd_device(&mtd->mtd);
98314
98315 -       if (set->nr_partitions > 0 && set->partitions != NULL) {
98316 -               return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
98317 +       if (set->nr_partitions == 0) {
98318 +               mtd->mtd.name = set->name;
98319 +               nr_part = parse_mtd_partitions(&mtd->mtd, part_probes,
98320 +                                               &part_info, 0);
98321 +       } else {
98322 +               if (set->nr_partitions > 0 && set->partitions != NULL) {
98323 +                       nr_part = set->nr_partitions;
98324 +                       part_info = set->partitions;
98325 +               }
98326         }
98327
98328 +       if (nr_part > 0 && part_info)
98329 +               return add_mtd_partitions(&mtd->mtd, part_info, nr_part);
98330 +
98331         return add_mtd_device(&mtd->mtd);
98332  }
98333  #else
98334 @@ -684,9 +703,13 @@ static void s3c2410_nand_init_chip(struc
98335         chip->select_chip  = s3c2410_nand_select_chip;
98336         chip->chip_delay   = 50;
98337         chip->priv         = nmtd;
98338 -       chip->options      = 0;
98339         chip->controller   = &info->controller;
98340
98341 +       if (set->flags & S3C2410_NAND_BBT)
98342 +               chip->options      = NAND_USE_FLASH_BBT;
98343 +       else
98344 +               chip->options      = 0;
98345 +
98346         switch (info->cpu_type) {
98347         case TYPE_S3C2410:
98348                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
98349 @@ -726,7 +749,7 @@ static void s3c2410_nand_init_chip(struc
98350         nmtd->mtd.owner    = THIS_MODULE;
98351         nmtd->set          = set;
98352
98353 -       if (hardware_ecc) {
98354 +       if (!info->platform->software_ecc && hardware_ecc) {
98355                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
98356                 chip->ecc.correct   = s3c2410_nand_correct_data;
98357                 chip->ecc.mode      = NAND_ECC_HW;
98358 Index: linux-2.6.28/drivers/net/wireless/libertas/if_sdio.c
98359 ===================================================================
98360 --- linux-2.6.28.orig/drivers/net/wireless/libertas/if_sdio.c   2008-12-25 00:26:37.000000000 +0100
98361 +++ linux-2.6.28/drivers/net/wireless/libertas/if_sdio.c        2009-01-02 00:01:56.000000000 +0100
98362 @@ -48,6 +48,7 @@ module_param_named(fw_name, lbs_fw_name,
98363
98364  static const struct sdio_device_id if_sdio_ids[] = {
98365         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_LIBERTAS) },
98366 +       { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_88W8688) },
98367         { /* end: all zeroes */                                         },
98368  };
98369
98370 @@ -72,7 +73,12 @@ static struct if_sdio_model if_sdio_mode
98371                 .helper = "sd8686_helper.bin",
98372                 .firmware = "sd8686.bin",
98373         },
98374 -};
98375 +       {
98376 +               /* 8688 */
98377 +               .model = 0x10,
98378 +               .helper = "sd8688_helper.bin",
98379 +               .firmware = "sd8688.bin",
98380 +       },};
98381
98382  struct if_sdio_packet {
98383         struct if_sdio_packet   *next;
98384 Index: linux-2.6.28/drivers/pnp/Kconfig
98385 ===================================================================
98386 --- linux-2.6.28.orig/drivers/pnp/Kconfig       2008-12-25 00:26:37.000000000 +0100
98387 +++ linux-2.6.28/drivers/pnp/Kconfig    2009-01-02 00:01:56.000000000 +0100
98388 @@ -5,7 +5,7 @@
98389  menuconfig PNP
98390         bool "Plug and Play support"
98391         depends on HAS_IOMEM
98392 -       depends on ISA || ACPI
98393 +       depends on ISA || ACPI || SDIO
98394         ---help---
98395           Plug and Play (PnP) is a standard for peripherals which allows those
98396           peripherals to be configured by software, e.g. assign IRQ's or other
98397 Index: linux-2.6.28/drivers/pnp/resource.c
98398 ===================================================================
98399 --- linux-2.6.28.orig/drivers/pnp/resource.c    2008-12-25 00:26:37.000000000 +0100
98400 +++ linux-2.6.28/drivers/pnp/resource.c 2009-01-02 00:01:56.000000000 +0100
98401 @@ -436,6 +436,7 @@ int pnp_check_dma(struct pnp_dev *dev, s
98402                 }
98403         }
98404
98405 +#if 0
98406         /* check if the resource is already in use, skip if the
98407          * device is active because it itself may be in use */
98408         if (!dev->active) {
98409 @@ -443,6 +444,7 @@ int pnp_check_dma(struct pnp_dev *dev, s
98410                         return 0;
98411                 free_dma(*dma);
98412         }
98413 +#endif
98414
98415         /* check for conflicts with other pnp devices */
98416         pnp_for_each_dev(tdev) {
98417 Index: linux-2.6.28/drivers/power/bq27000_battery.c
98418 ===================================================================
98419 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
98420 +++ linux-2.6.28/drivers/power/bq27000_battery.c        2009-01-02 00:01:56.000000000 +0100
98421 @@ -0,0 +1,463 @@
98422 +/*
98423 + * Driver for batteries with bq27000 chips inside via HDQ
98424 + *
98425 + * Copyright 2008 Openmoko, Inc
98426 + * Andy Green <andy@openmoko.com>
98427 + *
98428 + * based on ds2760 driver, original copyright notice for that --->
98429 + *
98430 + * Copyright © 2007 Anton Vorontsov
98431 + *            2004-2007 Matt Reimer
98432 + *            2004 Szabolcs Gyurko
98433 + *
98434 + * Use consistent with the GNU GPL is permitted,
98435 + * provided that this copyright notice is
98436 + * preserved in its entirety in all copies and derived works.
98437 + *
98438 + * Author:  Anton Vorontsov <cbou@mail.ru>
98439 + *         February 2007
98440 + *
98441 + *         Matt Reimer <mreimer@vpop.net>
98442 + *         April 2004, 2005, 2007
98443 + *
98444 + *         Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
98445 + *         September 2004
98446 + */
98447 +
98448 +#include <linux/module.h>
98449 +#include <linux/param.h>
98450 +#include <linux/jiffies.h>
98451 +#include <linux/delay.h>
98452 +#include <linux/pm.h>
98453 +#include <linux/workqueue.h>
98454 +#include <linux/platform_device.h>
98455 +#include <linux/power_supply.h>
98456 +#include <linux/bq27000_battery.h>
98457 +
98458 +enum bq27000_regs {
98459 +       /* RAM regs */
98460 +               /* read-write after this */
98461 +       BQ27000_CTRL = 0, /* Device Control Register */
98462 +       BQ27000_MODE, /* Device Mode Register */
98463 +       BQ27000_AR_L, /* At-Rate H L */
98464 +       BQ27000_AR_H,
98465 +               /* read-only after this */
98466 +       BQ27000_ARTTE_L, /* At-Rate Time To Empty H L */
98467 +       BQ27000_ARTTE_H,
98468 +       BQ27000_TEMP_L, /* Reported Temperature H L */
98469 +       BQ27000_TEMP_H,
98470 +       BQ27000_VOLT_L, /* Reported Voltage H L */
98471 +       BQ27000_VOLT_H,
98472 +       BQ27000_FLAGS, /* Status Flags */
98473 +       BQ27000_RSOC, /* Relative State of Charge */
98474 +       BQ27000_NAC_L, /* Nominal Available Capacity H L */
98475 +       BQ27000_NAC_H,
98476 +       BQ27000_CACD_L, /* Discharge Compensated H L */
98477 +       BQ27000_CACD_H,
98478 +       BQ27000_CACT_L, /* Temperature Compensated H L */
98479 +       BQ27000_CACT_H,
98480 +       BQ27000_LMD_L, /* Last measured discharge H L */
98481 +       BQ27000_LMD_H,
98482 +       BQ27000_AI_L, /* Average Current H L */
98483 +       BQ27000_AI_H,
98484 +       BQ27000_TTE_L, /* Time to Empty H L */
98485 +       BQ27000_TTE_H,
98486 +       BQ27000_TTF_L, /* Time to Full H L */
98487 +       BQ27000_TTF_H,
98488 +       BQ27000_SI_L, /* Standby Current H L */
98489 +       BQ27000_SI_H,
98490 +       BQ27000_STTE_L, /* Standby Time To Empty H L */
98491 +       BQ27000_STTE_H,
98492 +       BQ27000_MLI_L, /* Max Load Current H L */
98493 +       BQ27000_MLI_H,
98494 +       BQ27000_MLTTE_L, /* Max Load Time To Empty H L */
98495 +       BQ27000_MLTTE_H,
98496 +       BQ27000_SAE_L, /* Available Energy H L */
98497 +       BQ27000_SAE_H,
98498 +       BQ27000_AP_L, /* Available Power H L */
98499 +       BQ27000_AP_H,
98500 +       BQ27000_TTECP_L, /* Time to Empty at Constant Power H L */
98501 +       BQ27000_TTECP_H,
98502 +       BQ27000_CYCL_L, /* Cycle count since learning cycle H L */
98503 +       BQ27000_CYCL_H,
98504 +       BQ27000_CYCT_L, /* Cycle Count Total H L */
98505 +       BQ27000_CYCT_H,
98506 +       BQ27000_CSOC, /* Compensated State Of Charge */
98507 +       /* EEPROM regs */
98508 +               /* read-write after this */
98509 +       BQ27000_EE_EE_EN = 0x6e, /* EEPROM Program Enable */
98510 +       BQ27000_EE_ILMD = 0x76, /* Initial Last Measured Discharge High Byte */
98511 +       BQ27000_EE_SEDVF, /* Scaled EDVF Threshold */
98512 +       BQ27000_EE_SEDV1, /* Scaled EDV1 Threshold */
98513 +       BQ27000_EE_ISLC, /* Initial Standby Load Current */
98514 +       BQ27000_EE_DMFSD, /* Digital Magnitude Filter and Self Discharge */
98515 +       BQ27000_EE_TAPER, /* Aging Estimate Enable, Charge Termination Taper */
98516 +       BQ27000_EE_PKCFG, /* Pack Configuration Values */
98517 +       BQ27000_EE_IMLC, /* Initial Max Load Current or ID #3 */
98518 +       BQ27000_EE_DCOMP, /* Discharge rate compensation constants or ID #2 */
98519 +       BQ27000_EE_TCOMP, /* Temperature Compensation constants or ID #1 */
98520 +};
98521 +
98522 +enum bq27000_status_flags {
98523 +       BQ27000_STATUS_CHGS = 0x80, /* 1 = being charged */
98524 +       BQ27000_STATUS_NOACT = 0x40, /* 1 = no activity */
98525 +       BQ27000_STATUS_IMIN = 0x20, /* 1 = Lion taper current mode */
98526 +       BQ27000_STATUS_CI = 0x10, /* 1 = capacity likely  innacurate */
98527 +       BQ27000_STATUS_CALIP = 0x08, /* 1 = calibration in progress */
98528 +       BQ27000_STATUS_VDQ = 0x04, /* 1 = capacity should be accurate */
98529 +       BQ27000_STATUS_EDV1 = 0x02, /* 1 = end of discharge.. <6% left */
98530 +       BQ27000_STATUS_EDVF = 0x01, /* 1 = no, it's really empty now */
98531 +};
98532 +
98533 +#define NANOVOLTS_UNIT 3750
98534 +
98535 +struct bq27000_bat_regs {
98536 +       int             ai;
98537 +       int             flags;
98538 +       int             lmd;
98539 +       int             rsoc;
98540 +       int             temp;
98541 +       int             tte;
98542 +       int             ttf;
98543 +       int             volt;
98544 +};
98545 +
98546 +struct bq27000_device_info {
98547 +       struct device *dev;
98548 +       struct power_supply bat;
98549 +       struct delayed_work work;
98550 +       struct bq27000_platform_data *pdata;
98551 +
98552 +       struct bq27000_bat_regs regs;
98553 +};
98554 +
98555 +static unsigned int cache_time = 10000;
98556 +module_param(cache_time, uint, 0644);
98557 +MODULE_PARM_DESC(cache_time, "cache time in milliseconds");
98558 +
98559 +/*
98560 + * reading 16 bit values over HDQ has a special hazard where the
98561 + * hdq device firmware can update the 16-bit register during the time we
98562 + * read the two halves.  TI document SLUS556D recommends the algorithm here
98563 + * to avoid trouble
98564 + */
98565 +
98566 +static int hdq_read16(struct bq27000_device_info *di, int address)
98567 +{
98568 +       int acc;
98569 +       int high;
98570 +       int retries = 3;
98571 +
98572 +       while (retries--) {
98573 +
98574 +               high = (di->pdata->hdq_read)(address + 1); /* high part */
98575 +
98576 +               if (high < 0)
98577 +                       return high;
98578 +               acc = (di->pdata->hdq_read)(address);
98579 +               if (acc < 0)
98580 +                       return acc;
98581 +
98582 +               /* confirm high didn't change between reading it and low */
98583 +               if (high == (di->pdata->hdq_read)(address + 1))
98584 +                       return (high << 8) | acc;
98585 +       }
98586 +
98587 +       return -ETIME;
98588 +}
98589 +
98590 +static void bq27000_battery_external_power_changed(struct power_supply *psy)
98591 +{
98592 +       struct bq27000_device_info *di = container_of(psy, struct bq27000_device_info, bat);
98593 +
98594 +       power_supply_changed(&di->bat);
98595 +       dev_dbg(di->dev, "%s\n", __FUNCTION__);
98596 +}
98597 +
98598 +static int bq27000_battery_get_property(struct power_supply *psy,
98599 +                                      enum power_supply_property psp,
98600 +                                      union power_supply_propval *val)
98601 +{
98602 +       int n;
98603 +       struct bq27000_device_info *di = container_of(psy, struct bq27000_device_info, bat);
98604 +
98605 +       switch (psp) {
98606 +       case POWER_SUPPLY_PROP_STATUS:
98607 +               val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
98608 +
98609 +               if (!di->pdata->get_charger_online_status)
98610 +                       goto use_bat;
98611 +               if ((di->pdata->get_charger_online_status)()) {
98612 +                       /*
98613 +                        * charger is definitively present
98614 +                        * we report our state in terms of what it says it
98615 +                        * is doing
98616 +                        */
98617 +                       if (!di->pdata->get_charger_active_status)
98618 +                               goto use_bat;
98619 +
98620 +                       if ((di->pdata->get_charger_active_status)()) {
98621 +                               val->intval = POWER_SUPPLY_STATUS_CHARGING;
98622 +                               break;
98623 +                       }
98624 +                       val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
98625 +                       break;
98626 +               }
98627 +
98628 +               /*
98629 +                * platform provided definite indication of charger presence,
98630 +                * and it is telling us it isn't there... but we are on so we
98631 +                * must be running from battery --->
98632 +                */
98633 +
98634 +               val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
98635 +               break;
98636 +
98637 +use_bat:
98638 +               /*
98639 +                * either the charger is not connected, or the
98640 +                * platform doesn't give info about charger, use battery state
98641 +                * but... battery state can be out of date by 4 seconds or
98642 +                * so... use the platform callbacks if possible.
98643 +                */
98644 +
98645 +               /* no real activity on the battery */
98646 +               if (di->regs.ai < 2) {
98647 +                       if (!di->regs.ttf)
98648 +                               val->intval = POWER_SUPPLY_STATUS_FULL;
98649 +                       else
98650 +                               val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
98651 +                       break;
98652 +               }
98653 +               /* power is actually going in or out... */
98654 +               if (di->regs.flags < 0)
98655 +                       return di->regs.flags;
98656 +               if (di->regs.flags & BQ27000_STATUS_CHGS)
98657 +                       val->intval = POWER_SUPPLY_STATUS_CHARGING;
98658 +               else
98659 +                       val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
98660 +               break;
98661 +       case POWER_SUPPLY_PROP_HEALTH:
98662 +               val->intval = POWER_SUPPLY_HEALTH_UNKNOWN;
98663 +               /* Do we have accurate readings... */
98664 +               if (di->regs.flags < 0)
98665 +                       return di->regs.flags;
98666 +               if (di->regs.flags & BQ27000_STATUS_VDQ)
98667 +                       val->intval = POWER_SUPPLY_HEALTH_GOOD;
98668 +               break;
98669 +       case POWER_SUPPLY_PROP_VOLTAGE_NOW:
98670 +               if (di->regs.volt < 0)
98671 +                       return di->regs.volt;
98672 +               /* mV -> uV */
98673 +               val->intval = di->regs.volt * 1000;
98674 +               break;
98675 +       case POWER_SUPPLY_PROP_CURRENT_NOW:
98676 +               if (di->regs.flags < 0)
98677 +                       return di->regs.flags;
98678 +               if (di->regs.flags & BQ27000_STATUS_CHGS)
98679 +                       n = -NANOVOLTS_UNIT;
98680 +               else
98681 +                       n = NANOVOLTS_UNIT;
98682 +               if (di->regs.ai < 0)
98683 +                       return di->regs.ai;
98684 +               val->intval = (di->regs.ai * n) / di->pdata->rsense_mohms;
98685 +               break;
98686 +       case POWER_SUPPLY_PROP_CHARGE_FULL:
98687 +               if (di->regs.lmd < 0)
98688 +                       return di->regs.lmd;
98689 +               val->intval = (di->regs.lmd * 3570) / di->pdata->rsense_mohms;
98690 +               break;
98691 +       case POWER_SUPPLY_PROP_TEMP:
98692 +               if (di->regs.temp < 0)
98693 +                       return di->regs.temp;
98694 +               /* K (in 0.25K units) is 273.15 up from C (in 0.1C)*/
98695 +               /* 10926 = 27315 * 4 / 10 */
98696 +               val->intval = (((long)di->regs.temp * 10l) - 10926) / 4;
98697 +               break;
98698 +       case POWER_SUPPLY_PROP_TECHNOLOGY:
98699 +               val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
98700 +               break;
98701 +       case POWER_SUPPLY_PROP_CAPACITY:
98702 +               val->intval = di->regs.rsoc;
98703 +               if (val->intval < 0)
98704 +                       return val->intval;
98705 +               break;
98706 +       case POWER_SUPPLY_PROP_PRESENT:
98707 +               val->intval = !(di->regs.rsoc < 0);
98708 +               break;
98709 +       case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
98710 +               if (di->regs.tte < 0)
98711 +                       return di->regs.tte;
98712 +               val->intval = 60 * di->regs.tte;
98713 +               break;
98714 +       case POWER_SUPPLY_PROP_TIME_TO_FULL_NOW:
98715 +               if (di->regs.ttf < 0)
98716 +                       return di->regs.ttf;
98717 +               val->intval = 60 * di->regs.ttf;
98718 +               break;
98719 +       case POWER_SUPPLY_PROP_ONLINE:
98720 +               if (di->pdata->get_charger_online_status)
98721 +                       val->intval = (di->pdata->get_charger_online_status)();
98722 +               else
98723 +                       return -EINVAL;
98724 +               break;
98725 +       default:
98726 +               return -EINVAL;
98727 +       }
98728 +
98729 +       return 0;
98730 +}
98731 +
98732 +static void bq27000_battery_work(struct work_struct *work)
98733 +{
98734 +       struct bq27000_device_info *di =
98735 +               container_of(work, struct bq27000_device_info, work.work);
98736 +
98737 +       if ((di->pdata->hdq_initialized)()) {
98738 +               struct bq27000_bat_regs regs;
98739 +
98740 +               regs.ai    = hdq_read16(di, BQ27000_AI_L);
98741 +               regs.flags = (di->pdata->hdq_read)(BQ27000_FLAGS);
98742 +               regs.lmd   = hdq_read16(di, BQ27000_LMD_L);
98743 +               regs.rsoc  = (di->pdata->hdq_read)(BQ27000_RSOC);
98744 +               regs.temp  = hdq_read16(di, BQ27000_TEMP_L);
98745 +               regs.tte   = hdq_read16(di, BQ27000_TTE_L);
98746 +               regs.ttf   = hdq_read16(di, BQ27000_TTF_L);
98747 +               regs.volt  = hdq_read16(di, BQ27000_VOLT_L);
98748 +
98749 +               if (memcmp (&regs, &di->regs, sizeof(regs)) != 0) {
98750 +                       di->regs = regs;
98751 +                       power_supply_changed(&di->bat);
98752 +               }
98753 +       }
98754 +
98755 +       if (!schedule_delayed_work(&di->work, cache_time))
98756 +               dev_err(di->dev, "battery service reschedule failed\n");
98757 +}
98758 +
98759 +static enum power_supply_property bq27000_battery_props[] = {
98760 +       POWER_SUPPLY_PROP_STATUS,
98761 +       POWER_SUPPLY_PROP_HEALTH,
98762 +       POWER_SUPPLY_PROP_VOLTAGE_NOW,
98763 +       POWER_SUPPLY_PROP_CURRENT_NOW,
98764 +       POWER_SUPPLY_PROP_CHARGE_FULL,
98765 +       POWER_SUPPLY_PROP_TEMP,
98766 +       POWER_SUPPLY_PROP_TECHNOLOGY,
98767 +       POWER_SUPPLY_PROP_PRESENT,
98768 +       POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
98769 +       POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
98770 +       POWER_SUPPLY_PROP_CAPACITY,
98771 +       POWER_SUPPLY_PROP_ONLINE
98772 +};
98773 +
98774 +static int bq27000_battery_probe(struct platform_device *pdev)
98775 +{
98776 +       int retval = 0;
98777 +       struct bq27000_device_info *di;
98778 +       struct bq27000_platform_data *pdata;
98779 +
98780 +       dev_info(&pdev->dev, "BQ27000 Battery Driver (C) 2008 Openmoko, Inc\n");
98781 +
98782 +       di = kzalloc(sizeof(*di), GFP_KERNEL);
98783 +       if (!di) {
98784 +               retval = -ENOMEM;
98785 +               goto di_alloc_failed;
98786 +       }
98787 +
98788 +       platform_set_drvdata(pdev, di);
98789 +
98790 +       pdata = pdev->dev.platform_data;
98791 +       di->dev         = &pdev->dev;
98792 +       /* di->w1_dev        = pdev->dev.parent; */
98793 +       di->bat.name       = pdata->name;
98794 +       di->bat.type       = POWER_SUPPLY_TYPE_BATTERY;
98795 +       di->bat.properties     = bq27000_battery_props;
98796 +       di->bat.num_properties = ARRAY_SIZE(bq27000_battery_props);
98797 +       di->bat.get_property   = bq27000_battery_get_property;
98798 +       di->bat.external_power_changed =
98799 +                                 bq27000_battery_external_power_changed;
98800 +       di->bat.use_for_apm = 1;
98801 +       di->pdata = pdata;
98802 +
98803 +       retval = power_supply_register(&pdev->dev, &di->bat);
98804 +       if (retval) {
98805 +               dev_err(di->dev, "failed to register battery\n");
98806 +               goto batt_failed;
98807 +       }
98808 +
98809 +       INIT_DELAYED_WORK(&di->work, bq27000_battery_work);
98810 +
98811 +       if (!schedule_delayed_work(&di->work, 0))
98812 +               dev_err(di->dev, "failed to schedule bq27000_battery_work\n");
98813 +
98814 +       return 0;
98815 +
98816 +batt_failed:
98817 +       kfree(di);
98818 +di_alloc_failed:
98819 +       return retval;
98820 +}
98821 +
98822 +static int bq27000_battery_remove(struct platform_device *pdev)
98823 +{
98824 +       struct bq27000_device_info *di = platform_get_drvdata(pdev);
98825 +
98826 +       cancel_delayed_work(&di->work);
98827 +
98828 +       power_supply_unregister(&di->bat);
98829 +
98830 +       return 0;
98831 +}
98832 +
98833 +#ifdef CONFIG_PM
98834 +
98835 +static int bq27000_battery_suspend(struct platform_device *pdev,
98836 +                                 pm_message_t state)
98837 +{
98838 +       struct bq27000_device_info *di = platform_get_drvdata(pdev);
98839 +
98840 +       cancel_delayed_work(&di->work);
98841 +       return 0;
98842 +}
98843 +
98844 +static int bq27000_battery_resume(struct platform_device *pdev)
98845 +{
98846 +       struct bq27000_device_info *di = platform_get_drvdata(pdev);
98847 +
98848 +       schedule_delayed_work(&di->work, 0);
98849 +       return 0;
98850 +}
98851 +
98852 +#else
98853 +
98854 +#define bq27000_battery_suspend NULL
98855 +#define bq27000_battery_resume NULL
98856 +
98857 +#endif /* CONFIG_PM */
98858 +
98859 +static struct platform_driver bq27000_battery_driver = {
98860 +       .driver = {
98861 +               .name = "bq27000-battery",
98862 +       },
98863 +       .probe    = bq27000_battery_probe,
98864 +       .remove   = bq27000_battery_remove,
98865 +       .suspend  = bq27000_battery_suspend,
98866 +       .resume   = bq27000_battery_resume,
98867 +};
98868 +
98869 +static int __init bq27000_battery_init(void)
98870 +{
98871 +       return platform_driver_register(&bq27000_battery_driver);
98872 +}
98873 +
98874 +static void __exit bq27000_battery_exit(void)
98875 +{
98876 +       platform_driver_unregister(&bq27000_battery_driver);
98877 +}
98878 +
98879 +module_init(bq27000_battery_init);
98880 +module_exit(bq27000_battery_exit);
98881 +
98882 +MODULE_LICENSE("GPL");
98883 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
98884 +MODULE_DESCRIPTION("bq27000 battery driver");
98885 Index: linux-2.6.28/drivers/power/gta02_hdq.c
98886 ===================================================================
98887 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
98888 +++ linux-2.6.28/drivers/power/gta02_hdq.c      2009-01-02 00:01:56.000000000 +0100
98889 @@ -0,0 +1,292 @@
98890 +/*
98891 + * HDQ driver for the FIC Neo1973 GTA02 GSM phone
98892 + *
98893 + * (C) 2006-2007 by Openmoko, Inc.
98894 + * Author: Andy Green <andy@openmoko.com>
98895 + * All rights reserved.
98896 + *
98897 + * This program is free software; you can redistribute it and/or modify
98898 + * it under the terms of the GNU General Public License version 2 as
98899 + * published by the Free Software Foundation.
98900 + *
98901 + */
98902 +
98903 +#include <linux/kernel.h>
98904 +#include <linux/init.h>
98905 +#include <linux/delay.h>
98906 +#include <linux/platform_device.h>
98907 +#include <mach/hardware.h>
98908 +#include <linux/gta02_hdq.h>
98909 +#include <asm/mach-types.h>
98910 +#include <mach/gta02.h>
98911 +#include <mach/fiq_ipc_gta02.h>
98912 +
98913 +
98914 +
98915 +#define HDQ_READ 0
98916 +#define HDQ_WRITE 0x80
98917 +
98918 +static int fiq_busy(void)
98919 +{
98920 +       int request = (volatile u8)fiq_ipc.hdq_request_ctr;
98921 +       int transact = (volatile u8)fiq_ipc.hdq_transaction_ctr;
98922 +
98923 +       return (request != transact);
98924 +}
98925 +
98926 +int gta02hdq_initialized(void)
98927 +{
98928 +       return fiq_ipc.hdq_probed;
98929 +}
98930 +EXPORT_SYMBOL_GPL(gta02hdq_initialized);
98931 +
98932 +int gta02hdq_read(int address)
98933 +{
98934 +       int count_sleeps = 5;
98935 +       int ret = -ETIME;
98936 +
98937 +       if (!fiq_ipc.hdq_probed)
98938 +               return -EINVAL;
98939 +
98940 +       mutex_lock(&fiq_ipc.hdq_lock);
98941 +
98942 +       fiq_ipc.hdq_error = 0;
98943 +       fiq_ipc.hdq_ads = address | HDQ_READ;
98944 +       fiq_ipc.hdq_request_ctr++;
98945 +       fiq_kick();
98946 +       /*
98947 +        * FIQ takes care of it while we block our calling process
98948 +        * But we're not spinning -- other processes run normally while
98949 +        * we wait for the result
98950 +        */
98951 +       while (count_sleeps--) {
98952 +               msleep(10); /* valid transaction always completes in < 10ms */
98953 +
98954 +               if (fiq_busy())
98955 +                       continue;
98956 +
98957 +               if (fiq_ipc.hdq_error)
98958 +                       goto done; /* didn't see a response in good time */
98959 +
98960 +               ret = fiq_ipc.hdq_rx_data;
98961 +               goto done;
98962 +       }
98963 +
98964 +done:
98965 +       mutex_unlock(&fiq_ipc.hdq_lock);
98966 +       return ret;
98967 +}
98968 +EXPORT_SYMBOL_GPL(gta02hdq_read);
98969 +
98970 +int gta02hdq_write(int address, u8 data)
98971 +{
98972 +       int count_sleeps = 5;
98973 +       int ret = -ETIME;
98974 +
98975 +       if (!fiq_ipc.hdq_probed)
98976 +               return -EINVAL;
98977 +
98978 +       mutex_lock(&fiq_ipc.hdq_lock);
98979 +
98980 +       fiq_ipc.hdq_error = 0;
98981 +       fiq_ipc.hdq_ads = address | HDQ_WRITE;
98982 +       fiq_ipc.hdq_tx_data = data;
98983 +       fiq_ipc.hdq_request_ctr++;
98984 +       fiq_kick();
98985 +       /*
98986 +        * FIQ takes care of it while we block our calling process
98987 +        * But we're not spinning -- other processes run normally while
98988 +        * we wait for the result
98989 +        */
98990 +       while (count_sleeps--) {
98991 +               msleep(10); /* valid transaction always completes in < 10ms */
98992 +
98993 +               if (fiq_busy())
98994 +                       continue; /* something bad with FIQ */
98995 +
98996 +               if (fiq_ipc.hdq_error)
98997 +                       goto done; /* didn't see a response in good time */
98998 +
98999 +               ret = 0;
99000 +               goto done;
99001 +       }
99002 +
99003 +done:
99004 +       mutex_unlock(&fiq_ipc.hdq_lock);
99005 +       return ret;
99006 +}
99007 +EXPORT_SYMBOL_GPL(gta02hdq_write);
99008 +
99009 +/* sysfs */
99010 +
99011 +static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr,
99012 +                        char *buf)
99013 +{
99014 +       int n;
99015 +       int v;
99016 +       u8 u8a[128]; /* whole address space for HDQ */
99017 +       char *end = buf;
99018 +
99019 +       if (!fiq_ipc.hdq_probed)
99020 +               return -EINVAL;
99021 +
99022 +       /* the dump does not take care about 16 bit regs, because at this
99023 +        * bus level we don't know about the chip details
99024 +        */
99025 +       for (n = 0; n < sizeof(u8a); n++) {
99026 +               v = gta02hdq_read(n);
99027 +               if (v < 0)
99028 +                       goto bail;
99029 +               u8a[n] = v;
99030 +       }
99031 +
99032 +       for (n = 0; n < sizeof(u8a); n += 16) {
99033 +               hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0);
99034 +               end += strlen(end);
99035 +               *end++ = '\n';
99036 +               *end = '\0';
99037 +       }
99038 +       return (end - buf);
99039 +
99040 +bail:
99041 +       return sprintf(buf, "ERROR %d\n", v);
99042 +}
99043 +
99044 +/* you write by <address> <data>, eg, "34 128" */
99045 +
99046 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
99047 +
99048 +static ssize_t hdq_sysfs_write(struct device *dev,
99049 +                              struct device_attribute *attr,
99050 +                              const char *buf, size_t count)
99051 +{
99052 +       const char *end = buf + count;
99053 +       int address = atoi(buf);
99054 +
99055 +       if (!fiq_ipc.hdq_probed)
99056 +               return -EINVAL;
99057 +
99058 +       while ((buf != end) && (*buf != ' '))
99059 +               buf++;
99060 +       if (buf >= end)
99061 +               return 0;
99062 +       while ((buf < end) && (*buf == ' '))
99063 +               buf++;
99064 +       if (buf >= end)
99065 +               return 0;
99066 +
99067 +       gta02hdq_write(address, atoi(buf));
99068 +
99069 +       return count;
99070 +}
99071 +
99072 +static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL);
99073 +static DEVICE_ATTR(write, 0600, NULL, hdq_sysfs_write);
99074 +
99075 +static struct attribute *gta02hdq_sysfs_entries[] = {
99076 +       &dev_attr_dump.attr,
99077 +       &dev_attr_write.attr,
99078 +       NULL
99079 +};
99080 +
99081 +static struct attribute_group gta02hdq_attr_group = {
99082 +       .name   = "hdq",
99083 +       .attrs  = gta02hdq_sysfs_entries,
99084 +};
99085 +
99086 +
99087 +#ifdef CONFIG_PM
99088 +static int gta02hdq_suspend(struct platform_device *pdev, pm_message_t state)
99089 +{
99090 +       /* after 18s of this, the battery monitor will also go to sleep */
99091 +       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
99092 +       s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
99093 +       return 0;
99094 +}
99095 +
99096 +static int gta02hdq_resume(struct platform_device *pdev)
99097 +{
99098 +       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
99099 +       s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
99100 +       return 0;
99101 +}
99102 +#endif
99103 +
99104 +static int __init gta02hdq_probe(struct platform_device *pdev)
99105 +{
99106 +       struct resource *r = platform_get_resource(pdev, 0, 0);
99107 +       int ret;
99108 +       struct gta02_hdq_platform_data *pdata = pdev->dev.platform_data;
99109 +
99110 +       if (!machine_is_neo1973_gta02())
99111 +               return -EIO;
99112 +
99113 +       if (!r)
99114 +               return -EINVAL;
99115 +
99116 +       if (!fiq_ready) {
99117 +               printk(KERN_ERR "hdq probe fails on fiq not ready\n");
99118 +               return -EINVAL;
99119 +       }
99120 +
99121 +       platform_set_drvdata(pdev, NULL);
99122 +
99123 +       mutex_init(&fiq_ipc.hdq_lock);
99124 +
99125 +       /* set our HDQ comms pin from the platform data */
99126 +       fiq_ipc.hdq_gpio_pin = r->start;
99127 +
99128 +       s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
99129 +       s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
99130 +
99131 +       ret = sysfs_create_group(&pdev->dev.kobj, &gta02hdq_attr_group);
99132 +       if (ret)
99133 +               return ret;
99134 +
99135 +       fiq_ipc.hdq_probed = 1; /* we are ready to do stuff now */
99136 +
99137 +       /*
99138 +        * if wanted, users can defer registration of devices
99139 +        * that depend on HDQ until after we register, and can use our
99140 +        * device as parent so suspend-resume ordering is correct
99141 +        */
99142 +       if (pdata->attach_child_devices)
99143 +               (pdata->attach_child_devices)(&pdev->dev);
99144 +
99145 +       return 0;
99146 +}
99147 +
99148 +static int gta02hdq_remove(struct platform_device *pdev)
99149 +{
99150 +       sysfs_remove_group(&pdev->dev.kobj, &gta02hdq_attr_group);
99151 +       return 0;
99152 +}
99153 +
99154 +static struct platform_driver gta02hdq_driver = {
99155 +       .probe          = gta02hdq_probe,
99156 +       .remove         = gta02hdq_remove,
99157 +#ifdef CONFIG_PM
99158 +       .suspend        = gta02hdq_suspend,
99159 +       .resume         = gta02hdq_resume,
99160 +#endif
99161 +       .driver         = {
99162 +               .name           = "gta02-hdq",
99163 +       },
99164 +};
99165 +
99166 +static int __init gta02hdq_init(void)
99167 +{
99168 +       return platform_driver_register(&gta02hdq_driver);
99169 +}
99170 +
99171 +static void __exit gta02hdq_exit(void)
99172 +{
99173 +       platform_driver_unregister(&gta02hdq_driver);
99174 +}
99175 +
99176 +module_init(gta02hdq_init);
99177 +module_exit(gta02hdq_exit);
99178 +
99179 +MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
99180 +MODULE_DESCRIPTION("GTA02 HDQ driver");
99181 +MODULE_LICENSE("GPL");
99182 Index: linux-2.6.28/drivers/power/Kconfig
99183 ===================================================================
99184 --- linux-2.6.28.orig/drivers/power/Kconfig     2008-12-25 00:26:37.000000000 +0100
99185 +++ linux-2.6.28/drivers/power/Kconfig  2009-01-02 00:01:56.000000000 +0100
99186 @@ -68,4 +68,24 @@ config BATTERY_BQ27x00
99187         help
99188           Say Y here to enable support for batteries with BQ27200(I2C) chip.
99189
99190 +config BATTERY_BQ27000_HDQ
99191 +       tristate "BQ27000 HDQ battery monitor driver"
99192 +       help
99193 +         Say Y to enable support for the battery on the Neo Freerunner
99194 +
99195 +config GTA02_HDQ
99196 +       tristate "Neo Freerunner HDQ"
99197 +       depends on MACH_NEO1973_GTA02 && FIQ && S3C2440_C_FIQ
99198 +       help
99199 +         Say Y to enable support for communicating with an HDQ battery
99200 +         on the Neo Freerunner.  You probably want to select
99201 +         at least BATTERY_BQ27000_HDQ as well
99202 +
99203 +config CHARGER_PCF50633
99204 +       tristate "Support for NXP PCF50633 MBC"
99205 +       depends on MFD_PCF50633
99206 +       help
99207 +        Say Y to include support for NXP PCF50633 Main Battery Charger.
99208 +
99209  endif # POWER_SUPPLY
99210 +
99211 Index: linux-2.6.28/drivers/power/Makefile
99212 ===================================================================
99213 --- linux-2.6.28.orig/drivers/power/Makefile    2008-12-25 00:26:37.000000000 +0100
99214 +++ linux-2.6.28/drivers/power/Makefile 2009-01-02 00:01:56.000000000 +0100
99215 @@ -23,3 +23,9 @@ obj-$(CONFIG_BATTERY_OLPC)    += olpc_batte
99216  obj-$(CONFIG_BATTERY_TOSA)     += tosa_battery.o
99217  obj-$(CONFIG_BATTERY_WM97XX)   += wm97xx_battery.o
99218  obj-$(CONFIG_BATTERY_BQ27x00)  += bq27x00_battery.o
99219 +obj-$(CONFIG_BATTERY_PALMTX)   += palmtx_battery.o
99220 +obj-$(CONFIG_BATTERY_BQ27000_HDQ)      += bq27000_battery.o
99221 +
99222 +obj-$(CONFIG_GTA02_HDQ)                += gta02_hdq.o
99223 +
99224 +obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o
99225 Index: linux-2.6.28/drivers/power/pcf50633-charger.c
99226 ===================================================================
99227 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
99228 +++ linux-2.6.28/drivers/power/pcf50633-charger.c       2009-01-02 00:01:56.000000000 +0100
99229 @@ -0,0 +1,415 @@
99230 +/* Philips PCF50633 Main Battery Charger Driver
99231 + *
99232 + * (C) 2006-2008 by Openmoko, Inc.
99233 + * Author: Balaji Rao <balajirrao@openmoko.org>
99234 + * All rights reserved.
99235 + *
99236 + * Broken down from monstrous PCF50633 driver mainly by
99237 + * Harald Welte, Andy Green and Werner Almesberger
99238 + *
99239 + * This program is free software; you can redistribute it and/or
99240 + * modify it under the terms of the GNU General Public License as
99241 + * published by the Free Software Foundation; either version 2 of
99242 + * the License, or (at your option) any later version.
99243 + *
99244 + * This program is distributed in the hope that it will be useful,
99245 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
99246 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
99247 + * GNU General Public License for more details.
99248 + *
99249 + * You should have received a copy of the GNU General Public License
99250 + * along with this program; if not, write to the Free Software
99251 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
99252 + * MA 02111-1307 USA
99253 + */
99254 +
99255 +#include <linux/mfd/pcf50633/core.h>
99256 +#include <linux/mfd/pcf50633/mbc.h>
99257 +
99258 +void pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma)
99259 +{
99260 +       int ret;
99261 +       u8 bits;
99262 +       int charging_start = 1;
99263 +       u8 mbcs2, chgmod;
99264 +
99265 +       if (ma >= 1000)
99266 +               bits = PCF50633_MBCC7_USB_1000mA;
99267 +       else if (ma >= 500)
99268 +               bits = PCF50633_MBCC7_USB_500mA;
99269 +       else if (ma >= 100)
99270 +               bits = PCF50633_MBCC7_USB_100mA;
99271 +       else {
99272 +               bits = PCF50633_MBCC7_USB_SUSPEND;
99273 +               charging_start = 0;
99274 +       }
99275 +
99276 +       ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
99277 +                                       PCF50633_MBCC7_USB_MASK, bits);
99278 +       if (ret)
99279 +               dev_err(pcf->dev, "error setting usb curlim to %d mA\n", ma);
99280 +       else
99281 +               dev_info(pcf->dev, "usb curlim to %d mA\n", ma);
99282 +
99283 +       mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
99284 +       chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
99285 +
99286 +       /* If chgmod == BATFULL, setting chgena has no effect.
99287 +        * We need to set resume instead.
99288 +        */
99289 +       if (chgmod != PCF50633_MBCS2_MBC_BAT_FULL)
99290 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
99291 +                               PCF50633_MBCC1_CHGENA, PCF50633_MBCC1_CHGENA);
99292 +       else
99293 +               pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
99294 +                               PCF50633_MBCC1_RESUME, PCF50633_MBCC1_RESUME);
99295 +
99296 +       pcf->mbc.usb_active = charging_start;
99297 +       power_supply_changed(&pcf->mbc.usb);
99298 +}
99299 +EXPORT_SYMBOL_GPL(pcf50633_mbc_usb_curlim_set);
99300 +
99301 +static const char *chgmode_names[] = {
99302 +       [PCF50633_MBCS2_MBC_PLAY]               = "play-only",
99303 +       [PCF50633_MBCS2_MBC_USB_PRE]            = "pre",
99304 +       [PCF50633_MBCS2_MBC_ADP_PRE]            = "pre",
99305 +       [PCF50633_MBCS2_MBC_USB_PRE_WAIT]       = "pre-wait",
99306 +       [PCF50633_MBCS2_MBC_ADP_PRE_WAIT]       = "pre-wait",
99307 +       [PCF50633_MBCS2_MBC_USB_FAST]           = "fast",
99308 +       [PCF50633_MBCS2_MBC_ADP_FAST]           = "fast",
99309 +       [PCF50633_MBCS2_MBC_USB_FAST_WAIT]      = "fast-wait",
99310 +       [PCF50633_MBCS2_MBC_ADP_FAST_WAIT]      = "fast-wait",
99311 +       [PCF50633_MBCS2_MBC_BAT_FULL]   = "bat-full",
99312 +};
99313 +
99314 +static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
99315 +                           char *buf)
99316 +{
99317 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
99318 +
99319 +       u8 mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
99320 +       u8 chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
99321 +
99322 +       return sprintf(buf, "%s %d\n", chgmode_names[chgmod], chgmod);
99323 +}
99324 +static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, NULL);
99325 +
99326 +static ssize_t show_usblim(struct device *dev, struct device_attribute *attr,
99327 +                          char *buf)
99328 +{
99329 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
99330 +       u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
99331 +                                               PCF50633_MBCC7_USB_MASK;
99332 +       unsigned int ma;
99333 +
99334 +       if (usblim == PCF50633_MBCC7_USB_1000mA)
99335 +               ma = 1000;
99336 +       else if (usblim == PCF50633_MBCC7_USB_500mA)
99337 +               ma = 500;
99338 +       else if (usblim == PCF50633_MBCC7_USB_100mA)
99339 +               ma = 100;
99340 +       else
99341 +               ma = 0;
99342 +
99343 +       return sprintf(buf, "%u\n", ma);
99344 +}
99345 +static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, NULL);
99346 +
99347 +static ssize_t force_usb_limit_dangerous(struct device *dev,
99348 +                  struct device_attribute *attr, const char *buf, size_t count)
99349 +{
99350 +       struct pcf50633 *pcf = dev_get_drvdata(dev);
99351 +       unsigned long ma;
99352 +
99353 +       strict_strtoul(buf, 10, &ma);
99354 +
99355 +       pcf50633_mbc_usb_curlim_set(pcf, ma);
99356 +
99357 +       return count;
99358 +}
99359 +
99360 +static DEVICE_ATTR(force_usb_limit_dangerous, 0600,
99361 +                                              NULL, force_usb_limit_dangerous);
99362 +
99363 +static struct attribute *mbc_sysfs_entries[] = {
99364 +       &dev_attr_chgmode.attr,
99365 +       &dev_attr_usb_curlim.attr,
99366 +       &dev_attr_force_usb_limit_dangerous.attr,
99367 +       NULL,
99368 +};
99369 +
99370 +static struct attribute_group mbc_attr_group = {
99371 +       .name   = NULL,                 /* put in device directory */
99372 +       .attrs  = mbc_sysfs_entries,
99373 +};
99374 +
99375 +/* MBC state machine switches into charging mode when the battery voltage
99376 + * falls below 96% of a battery float voltage. But the voltage drop in Li-ion
99377 + * batteries is marginal(1~2 %) till about 80% of its capacity - which means,
99378 + * after a BATFULL, charging won't be restarted until 80%.
99379 + *
99380 + * This work_struct function restarts charging every
99381 + * CHARGING_RESTART_TIMEOUT seconds and makes sure we don't discharge too much
99382 + */
99383 +
99384 +#define CHARGING_RESTART_TIMEOUT       (900 * HZ)  /* 15 minutes */
99385 +
99386 +static void pcf50633_mbc_charging_restart(struct work_struct *work)
99387 +{
99388 +       struct pcf50633_mbc *mbc;
99389 +       struct pcf50633 *pcf;
99390 +       u8 mbcs2, chgmod;
99391 +
99392 +       mbc = container_of(work, struct pcf50633_mbc,
99393 +                               charging_restart_work.work);
99394 +       pcf = container_of(mbc, struct pcf50633, mbc);
99395 +
99396 +       mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
99397 +       chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
99398 +
99399 +       if (chgmod != PCF50633_MBCS2_MBC_BAT_FULL)
99400 +               return;
99401 +
99402 +       /* Restart charging */
99403 +       pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1, PCF50633_MBCC1_RESUME,
99404 +                                               PCF50633_MBCC1_RESUME);
99405 +       mbc->usb_active = 1;
99406 +       power_supply_changed(&mbc->usb);
99407 +
99408 +       dev_info(pcf->dev, "Charging restarted..\n");
99409 +}
99410 +
99411 +static void pcf50633_mbc_irq_handler(struct pcf50633 *pcf, int irq, void *data)
99412 +{
99413 +       struct pcf50633_mbc *mbc;
99414 +
99415 +       mbc = &pcf->mbc;
99416 +
99417 +       /* USB */
99418 +       if (irq == PCF50633_IRQ_USBINS)
99419 +               mbc->usb_online = 1;
99420 +       else if (irq == PCF50633_IRQ_USBREM) {
99421 +               mbc->usb_online = 0;
99422 +               mbc->usb_active = 0;
99423 +               pcf50633_mbc_usb_curlim_set(pcf, 0);
99424 +               cancel_delayed_work_sync(&mbc->charging_restart_work);
99425 +       }
99426 +
99427 +       /* Adapter */
99428 +       if (irq == PCF50633_IRQ_ADPINS) {
99429 +               pcf->mbc.adapter_online = 1;
99430 +               pcf->mbc.adapter_active = 1;
99431 +       } else if (irq == PCF50633_IRQ_ADPREM) {
99432 +               mbc->adapter_online = 0;
99433 +               mbc->adapter_active = 0;
99434 +       }
99435 +
99436 +       if (irq == PCF50633_IRQ_BATFULL) {
99437 +               mbc->usb_active = 0;
99438 +               mbc->adapter_active = 0;
99439 +               schedule_delayed_work(&mbc->charging_restart_work,
99440 +                                               CHARGING_RESTART_TIMEOUT);
99441 +       } else if (irq == PCF50633_IRQ_USBLIMON)
99442 +               mbc->usb_active = 0;
99443 +       else if (irq == PCF50633_IRQ_USBLIMOFF)
99444 +               mbc->usb_active = 1;
99445 +
99446 +       power_supply_changed(&mbc->ac);
99447 +       power_supply_changed(&mbc->usb);
99448 +       power_supply_changed(&mbc->adapter);
99449 +
99450 +       if (pcf->pdata->mbc_event_callback)
99451 +               pcf->pdata->mbc_event_callback(pcf, irq);
99452 +}
99453 +
99454 +static int adapter_get_property(struct power_supply *psy,
99455 +                       enum power_supply_property psp,
99456 +                       union power_supply_propval *val)
99457 +{
99458 +       int ret = 0;
99459 +       struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb);
99460 +
99461 +       switch (psp) {
99462 +       case POWER_SUPPLY_PROP_ONLINE:
99463 +               val->intval =  mbc->adapter_online;
99464 +               break;
99465 +       default:
99466 +               ret = -EINVAL;
99467 +               break;
99468 +       }
99469 +       return ret;
99470 +}
99471 +
99472 +static int usb_get_property(struct power_supply *psy,
99473 +                       enum power_supply_property psp,
99474 +                       union power_supply_propval *val)
99475 +{
99476 +       int ret = 0;
99477 +       struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb);
99478 +       struct pcf50633 *pcf = container_of(mbc, struct pcf50633, mbc);
99479 +
99480 +       u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
99481 +                                               PCF50633_MBCC7_USB_MASK;
99482 +
99483 +       switch (psp) {
99484 +       case POWER_SUPPLY_PROP_ONLINE:
99485 +               val->intval = mbc->usb_online && (usblim == PCF50633_MBCC7_USB_500mA);
99486 +               break;
99487 +       default:
99488 +               ret = -EINVAL;
99489 +               break;
99490 +       }
99491 +       return ret;
99492 +}
99493 +
99494 +static int ac_get_property(struct power_supply *psy,
99495 +                       enum power_supply_property psp,
99496 +                       union power_supply_propval *val)
99497 +{
99498 +       int ret = 0;
99499 +       struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, ac);
99500 +       struct pcf50633 *pcf = container_of(mbc, struct pcf50633, mbc);
99501 +
99502 +       u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
99503 +                                               PCF50633_MBCC7_USB_MASK;
99504 +
99505 +       switch (psp) {
99506 +       case POWER_SUPPLY_PROP_ONLINE:
99507 +               val->intval = mbc->usb_online && (usblim == PCF50633_MBCC7_USB_1000mA);
99508 +               break;
99509 +       default:
99510 +               ret = -EINVAL;
99511 +               break;
99512 +       }
99513 +       return ret;
99514 +}
99515 +
99516 +static enum power_supply_property power_props[] = {
99517 +       POWER_SUPPLY_PROP_ONLINE,
99518 +};
99519 +
99520 +int __init pcf50633_mbc_probe(struct platform_device *pdev)
99521 +{
99522 +       struct pcf50633 *pcf;
99523 +       struct pcf50633_mbc *mbc;
99524 +       int ret;
99525 +       u8 mbcs1;
99526 +
99527 +       pcf = platform_get_drvdata(pdev);
99528 +       mbc = &pcf->mbc;
99529 +
99530 +       /* Set up IRQ handlers */
99531 +       pcf->irq_handler[PCF50633_IRQ_ADPINS].handler =
99532 +                                       pcf50633_mbc_irq_handler;
99533 +       pcf->irq_handler[PCF50633_IRQ_ADPREM].handler =
99534 +                                       pcf50633_mbc_irq_handler;
99535 +       pcf->irq_handler[PCF50633_IRQ_USBINS].handler =
99536 +                                       pcf50633_mbc_irq_handler;
99537 +       pcf->irq_handler[PCF50633_IRQ_USBREM].handler =
99538 +                                       pcf50633_mbc_irq_handler;
99539 +       pcf->irq_handler[PCF50633_IRQ_BATFULL].handler =
99540 +                                       pcf50633_mbc_irq_handler;
99541 +       pcf->irq_handler[PCF50633_IRQ_CHGHALT].handler =
99542 +                                       pcf50633_mbc_irq_handler;
99543 +       pcf->irq_handler[PCF50633_IRQ_THLIMON].handler =
99544 +                                       pcf50633_mbc_irq_handler;
99545 +       pcf->irq_handler[PCF50633_IRQ_THLIMOFF].handler =
99546 +                                       pcf50633_mbc_irq_handler;
99547 +       pcf->irq_handler[PCF50633_IRQ_USBLIMON].handler =
99548 +                                       pcf50633_mbc_irq_handler;
99549 +       pcf->irq_handler[PCF50633_IRQ_USBLIMOFF].handler =
99550 +                                       pcf50633_mbc_irq_handler;
99551 +       pcf->irq_handler[PCF50633_IRQ_LOWSYS].handler =
99552 +                                       pcf50633_mbc_irq_handler;
99553 +       pcf->irq_handler[PCF50633_IRQ_LOWBAT].handler =
99554 +                                       pcf50633_mbc_irq_handler;
99555 +
99556 +       /* Create power supplies */
99557 +
99558 +       mbc->adapter.name               = "adapter";
99559 +       mbc->adapter.type               = POWER_SUPPLY_TYPE_MAINS;
99560 +       mbc->adapter.properties         = power_props;
99561 +       mbc->adapter.num_properties     = ARRAY_SIZE(power_props);
99562 +       mbc->adapter.get_property       = &adapter_get_property;
99563 +       mbc->adapter.supplied_to        = pcf->pdata->batteries;
99564 +       mbc->adapter.num_supplicants    = pcf->pdata->num_batteries;
99565 +
99566 +       mbc->usb.name                   = "usb";
99567 +       mbc->usb.type                   = POWER_SUPPLY_TYPE_USB;
99568 +       mbc->usb.properties             = power_props;
99569 +       mbc->usb.num_properties         = ARRAY_SIZE(power_props);
99570 +       mbc->usb.get_property           = usb_get_property;
99571 +       mbc->usb.supplied_to            = pcf->pdata->batteries;
99572 +       mbc->usb.num_supplicants        = pcf->pdata->num_batteries;
99573 +
99574 +       mbc->ac.name                    = "ac";
99575 +       mbc->ac.type                    = POWER_SUPPLY_TYPE_MAINS;
99576 +       mbc->ac.properties              = power_props;
99577 +       mbc->ac.num_properties          = ARRAY_SIZE(power_props);
99578 +       mbc->ac.get_property            = ac_get_property;
99579 +       mbc->ac.supplied_to             = pcf->pdata->batteries;
99580 +       mbc->ac.num_supplicants         = pcf->pdata->num_batteries;
99581 +
99582 +       INIT_DELAYED_WORK(&mbc->charging_restart_work,
99583 +                               pcf50633_mbc_charging_restart);
99584 +
99585 +       ret = power_supply_register(&pdev->dev, &mbc->adapter);
99586 +       if (ret)
99587 +               dev_err(pcf->dev, "failed to register adapter\n");
99588 +
99589 +       ret = power_supply_register(&pdev->dev, &mbc->usb);
99590 +       if (ret)
99591 +               dev_err(pcf->dev, "failed to register usb\n");
99592 +
99593 +       ret = power_supply_register(&pdev->dev, &mbc->ac);
99594 +       if (ret)
99595 +               dev_err(pcf->dev, "failed to register ac\n");
99596 +
99597 +       mbcs1 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS1);
99598 +       if (mbcs1 & 0x01)
99599 +               pcf50633_mbc_irq_handler(pcf, PCF50633_IRQ_USBINS, NULL);
99600 +       if (mbcs1 & 0x04)
99601 +               pcf50633_mbc_irq_handler(pcf, PCF50633_IRQ_ADPINS, NULL);
99602 +
99603 +       /* Disable automatic charging restart. Manually setting RESUME
99604 +        * won't have effect otherwise
99605 +        */
99606 +       pcf50633_reg_clear_bits(pcf, PCF50633_REG_MBCC1,
99607 +                                       PCF50633_MBCC1_AUTORES);
99608 +
99609 +       return sysfs_create_group(&pdev->dev.kobj, &mbc_attr_group);
99610 +}
99611 +
99612 +static int __devexit pcf50633_mbc_remove(struct platform_device *pdev)
99613 +{
99614 +       struct pcf50633 *pcf;
99615 +
99616 +       pcf = platform_get_drvdata(pdev);
99617 +
99618 +       return 0;
99619 +}
99620 +
99621 +struct platform_driver pcf50633_mbc_driver = {
99622 +       .driver = {
99623 +               .name = "pcf50633-mbc",
99624 +       },
99625 +       .probe = pcf50633_mbc_probe,
99626 +       .remove = __devexit_p(pcf50633_mbc_remove),
99627 +};
99628 +
99629 +static int __init pcf50633_mbc_init(void)
99630 +{
99631 +               return platform_driver_register(&pcf50633_mbc_driver);
99632 +}
99633 +module_init(pcf50633_mbc_init);
99634 +
99635 +static void __exit pcf50633_mbc_exit(void)
99636 +{
99637 +               platform_driver_unregister(&pcf50633_mbc_driver);
99638 +}
99639 +module_exit(pcf50633_mbc_exit);
99640 +
99641 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
99642 +MODULE_DESCRIPTION("PCF50633 mbc driver");
99643 +MODULE_LICENSE("GPL");
99644 +MODULE_ALIAS("platform:pcf50633-mbc");
99645 Index: linux-2.6.28/drivers/regulator/core.c
99646 ===================================================================
99647 --- linux-2.6.28.orig/drivers/regulator/core.c  2008-12-25 00:26:37.000000000 +0100
99648 +++ linux-2.6.28/drivers/regulator/core.c       2009-01-02 00:01:56.000000000 +0100
99649 @@ -1113,6 +1113,7 @@ int regulator_disable(struct regulator *
99650         if (!regulator->enabled) {
99651                 printk(KERN_ERR "%s: not in use by this consumer\n",
99652                         __func__);
99653 +               WARN_ON(1);
99654                 return 0;
99655         }
99656
99657 Index: linux-2.6.28/drivers/regulator/Kconfig
99658 ===================================================================
99659 --- linux-2.6.28.orig/drivers/regulator/Kconfig 2008-12-25 00:26:37.000000000 +0100
99660 +++ linux-2.6.28/drivers/regulator/Kconfig      2009-01-02 00:01:56.000000000 +0100
99661 @@ -73,4 +73,10 @@ config REGULATOR_DA903X
99662           Say y here to support the BUCKs and LDOs regulators found on
99663           Dialog Semiconductor DA9030/DA9034 PMIC.
99664
99665 +config REGULATOR_PCF50633
99666 +       bool "PCF50633 regulator driver"
99667 +        depends on MFD_PCF50633
99668 +       help
99669 +        Say Y here to support the voltage regulators and convertors
99670 +        on PCF50633
99671  endif
99672 Index: linux-2.6.28/drivers/regulator/Makefile
99673 ===================================================================
99674 --- linux-2.6.28.orig/drivers/regulator/Makefile        2008-12-25 00:26:37.000000000 +0100
99675 +++ linux-2.6.28/drivers/regulator/Makefile     2009-01-02 00:01:56.000000000 +0100
99676 @@ -11,5 +11,6 @@ obj-$(CONFIG_REGULATOR_BQ24022) += bq240
99677  obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
99678  obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
99679  obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
99680 +obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
99681
99682  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
99683 Index: linux-2.6.28/drivers/regulator/pcf50633-regulator.c
99684 ===================================================================
99685 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
99686 +++ linux-2.6.28/drivers/regulator/pcf50633-regulator.c 2009-01-02 00:01:56.000000000 +0100
99687 @@ -0,0 +1,330 @@
99688 +/* Philips PCF50633 PMIC Driver
99689 + *
99690 + * (C) 2006-2008 by Openmoko, Inc.
99691 + * Author: Balaji Rao <balajirrao@openmoko.org>
99692 + * All rights reserved.
99693 + *
99694 + * Broken down from monstrous PCF50633 driver mainly by
99695 + * Harald Welte and Andy Green
99696 + *
99697 + * This program is free software; you can redistribute it and/or
99698 + * modify it under the terms of the GNU General Public License as
99699 + * published by the Free Software Foundation; either version 2 of
99700 + * the License, or (at your option) any later version.
99701 + *
99702 + * This program is distributed in the hope that it will be useful,
99703 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
99704 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
99705 + * GNU General Public License for more details.
99706 + *
99707 + * You should have received a copy of the GNU General Public License
99708 + * along with this program; if not, write to the Free Software
99709 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
99710 + * MA 02111-1307 USA
99711 + */
99712 +
99713 +#include <linux/regulator/driver.h>
99714 +#include <linux/platform_device.h>
99715 +#include <linux/err.h>
99716 +
99717 +#include <linux/mfd/pcf50633/core.h>
99718 +#include <linux/mfd/pcf50633/pmic.h>
99719 +
99720 +#define PCF50633_REGULATOR(_name, _id)                 \
99721 +       {                                       \
99722 +               .name = _name,                  \
99723 +               .id = _id,                      \
99724 +               .ops = &pcf50633_regulator_ops, \
99725 +               .type = REGULATOR_VOLTAGE,      \
99726 +               .owner = THIS_MODULE,           \
99727 +       }
99728 +static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
99729 +       [PCF50633_REGULATOR_AUTO]       = PCF50633_REG_AUTOOUT,
99730 +       [PCF50633_REGULATOR_DOWN1]      = PCF50633_REG_DOWN1OUT,
99731 +       [PCF50633_REGULATOR_DOWN2]      = PCF50633_REG_DOWN2OUT,
99732 +       [PCF50633_REGULATOR_MEMLDO]     = PCF50633_REG_MEMLDOOUT,
99733 +       [PCF50633_REGULATOR_LDO1]       = PCF50633_REG_LDO1OUT,
99734 +       [PCF50633_REGULATOR_LDO2]       = PCF50633_REG_LDO2OUT,
99735 +       [PCF50633_REGULATOR_LDO3]       = PCF50633_REG_LDO3OUT,
99736 +       [PCF50633_REGULATOR_LDO4]       = PCF50633_REG_LDO4OUT,
99737 +       [PCF50633_REGULATOR_LDO5]       = PCF50633_REG_LDO5OUT,
99738 +       [PCF50633_REGULATOR_LDO6]       = PCF50633_REG_LDO6OUT,
99739 +       [PCF50633_REGULATOR_HCLDO]      = PCF50633_REG_HCLDOOUT,
99740 +};
99741 +
99742 +/* Bits from voltage value */
99743 +static u_int8_t auto_voltage_bits(unsigned int millivolts)
99744 +{
99745 +       if (millivolts < 1800)
99746 +               return 0;
99747 +       if (millivolts > 3800)
99748 +               return 0xff;
99749 +
99750 +       millivolts -= 625;
99751 +       return millivolts/25;
99752 +}
99753 +
99754 +static u_int8_t down_voltage_bits(unsigned int millivolts)
99755 +{
99756 +       if (millivolts < 625)
99757 +               return 0;
99758 +       else if (millivolts > 3000)
99759 +               return 0xff;
99760 +
99761 +       millivolts -= 625;
99762 +       return millivolts/25;
99763 +}
99764 +
99765 +static u_int8_t ldo_voltage_bits(unsigned int millivolts)
99766 +{
99767 +       if (millivolts < 900)
99768 +               return 0;
99769 +       else if (millivolts > 3600)
99770 +               return 0x1f;
99771 +
99772 +       millivolts -= 900;
99773 +       return millivolts/100;
99774 +}
99775 +
99776 +/* Obtain voltage value from bits */
99777 +
99778 +static unsigned int auto_voltage_value(uint8_t bits)
99779 +{
99780 +       if (bits < 0x2f)
99781 +               return 0;
99782 +       return 625 + (bits * 25);
99783 +}
99784 +
99785 +
99786 +static unsigned int down_voltage_value(uint8_t bits)
99787 +{
99788 +       return 625 + (bits*25);
99789 +}
99790 +
99791 +
99792 +static unsigned int ldo_voltage_value(uint8_t bits)
99793 +{
99794 +       bits &= 0x1f;
99795 +       return 900 + (bits * 100);
99796 +}
99797 +
99798 +static int pcf50633_regulator_set_voltage(struct regulator_dev *rdev,
99799 +                       int min_uV, int max_uV)
99800 +{
99801 +       uint8_t volt_bits;
99802 +       uint8_t regnr;
99803 +       int regulator_id;
99804 +       int millivolts;
99805 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);;
99806 +
99807 +       regulator_id = rdev_get_id(rdev);
99808 +
99809 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
99810 +               return -EINVAL;
99811 +
99812 +       millivolts = min_uV / 1000;
99813 +
99814 +       regnr = pcf50633_regulator_registers[regulator_id];
99815 +
99816 +       switch (regulator_id) {
99817 +       case PCF50633_REGULATOR_AUTO:
99818 +               volt_bits = auto_voltage_bits(millivolts);
99819 +               break;
99820 +       case PCF50633_REGULATOR_DOWN1:
99821 +               volt_bits = down_voltage_bits(millivolts);
99822 +               break;
99823 +       case PCF50633_REGULATOR_DOWN2:
99824 +               volt_bits = down_voltage_bits(millivolts);
99825 +               break;
99826 +       case PCF50633_REGULATOR_LDO1:
99827 +       case PCF50633_REGULATOR_LDO2:
99828 +       case PCF50633_REGULATOR_LDO3:
99829 +       case PCF50633_REGULATOR_LDO4:
99830 +       case PCF50633_REGULATOR_LDO5:
99831 +       case PCF50633_REGULATOR_LDO6:
99832 +       case PCF50633_REGULATOR_HCLDO:
99833 +               volt_bits = ldo_voltage_bits(millivolts);
99834 +               break;
99835 +       default:
99836 +               return -EINVAL;
99837 +       }
99838 +
99839 +       return pcf50633_reg_write(pcf, regnr, volt_bits);
99840 +}
99841 +
99842 +static int pcf50633_regulator_get_voltage(struct regulator_dev *rdev)
99843 +{
99844 +       uint8_t volt_bits;
99845 +       uint8_t regnr;
99846 +       unsigned int rc = 0;
99847 +       int regulator_id = rdev_get_id(rdev);
99848 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
99849 +
99850 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
99851 +               return -EINVAL;
99852 +
99853 +       regnr = pcf50633_regulator_registers[regulator_id];
99854 +       volt_bits = pcf50633_reg_read(pcf, regnr);
99855 +
99856 +       switch (regulator_id) {
99857 +       case PCF50633_REGULATOR_AUTO:
99858 +               rc = auto_voltage_value(volt_bits);
99859 +               break;
99860 +       case PCF50633_REGULATOR_DOWN1:
99861 +               rc = down_voltage_value(volt_bits);
99862 +               break;
99863 +       case PCF50633_REGULATOR_DOWN2:
99864 +               rc = down_voltage_value(volt_bits);
99865 +               break;
99866 +       case PCF50633_REGULATOR_LDO1:
99867 +       case PCF50633_REGULATOR_LDO2:
99868 +       case PCF50633_REGULATOR_LDO3:
99869 +       case PCF50633_REGULATOR_LDO4:
99870 +       case PCF50633_REGULATOR_LDO5:
99871 +       case PCF50633_REGULATOR_LDO6:
99872 +       case PCF50633_REGULATOR_HCLDO:
99873 +               rc = ldo_voltage_value(volt_bits);
99874 +               break;
99875 +       default:
99876 +               return -EINVAL;
99877 +       }
99878 +
99879 +       return rc * 1000;
99880 +}
99881 +
99882 +static int pcf50633_regulator_enable(struct regulator_dev *rdev)
99883 +{
99884 +       uint8_t regnr;
99885 +       int regulator_id = rdev_get_id(rdev);
99886 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
99887 +
99888 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
99889 +               return -EINVAL;
99890 +
99891 +       /* the *ENA register is always one after the *OUT register */
99892 +       regnr = pcf50633_regulator_registers[regulator_id] + 1;
99893 +
99894 +       pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON,
99895 +                      PCF50633_REGULATOR_ON);
99896 +
99897 +       return 0;
99898 +}
99899 +
99900 +static int pcf50633_regulator_disable(struct regulator_dev *rdev)
99901 +{
99902 +       uint8_t regnr;
99903 +       int regulator_id = rdev_get_id(rdev);
99904 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
99905 +
99906 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
99907 +               return -EINVAL;
99908 +
99909 +       /* the *ENA register is always one after the *OUT register */
99910 +       regnr = pcf50633_regulator_registers[regulator_id] + 1;
99911 +
99912 +       pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON, 0);
99913 +
99914 +       return 0;
99915 +}
99916 +
99917 +static int pcf50633_regulator_is_enabled(struct regulator_dev *rdev)
99918 +{
99919 +       uint8_t val, regnr;
99920 +       int regulator_id = rdev_get_id(rdev);
99921 +       struct pcf50633 *pcf = rdev_get_drvdata(rdev);
99922 +
99923 +       if (regulator_id >= PCF50633_NUM_REGULATORS)
99924 +               return -EINVAL;
99925 +
99926 +       /* the *ENA register is always one after the *OUT register */
99927 +       regnr = pcf50633_regulator_registers[regulator_id] + 1;
99928 +       val = pcf50633_reg_read(pcf, regnr) & PCF50633_REGULATOR_ON;
99929 +
99930 +       return val;
99931 +}
99932 +
99933 +struct regulator_ops pcf50633_regulator_ops = {
99934 +       .set_voltage = pcf50633_regulator_set_voltage,
99935 +       .get_voltage = pcf50633_regulator_get_voltage,
99936 +       .enable = pcf50633_regulator_enable,
99937 +       .disable = pcf50633_regulator_disable,
99938 +       .is_enabled = pcf50633_regulator_is_enabled,
99939 +       .set_suspend_enable = pcf50633_regulator_enable,
99940 +       .set_suspend_disable = pcf50633_regulator_disable,
99941 +};
99942 +
99943 +static struct regulator_desc regulators[] = {
99944 +       [PCF50633_REGULATOR_AUTO] =
99945 +               PCF50633_REGULATOR("auto", PCF50633_REGULATOR_AUTO),
99946 +       [PCF50633_REGULATOR_DOWN1] =
99947 +               PCF50633_REGULATOR("down1", PCF50633_REGULATOR_DOWN1),
99948 +       [PCF50633_REGULATOR_DOWN2] =
99949 +               PCF50633_REGULATOR("down2", PCF50633_REGULATOR_DOWN2),
99950 +       [PCF50633_REGULATOR_LDO1] =
99951 +               PCF50633_REGULATOR("ldo1", PCF50633_REGULATOR_LDO1),
99952 +       [PCF50633_REGULATOR_LDO2] =
99953 +               PCF50633_REGULATOR("ldo2", PCF50633_REGULATOR_LDO2),
99954 +       [PCF50633_REGULATOR_LDO3] =
99955 +               PCF50633_REGULATOR("ldo3", PCF50633_REGULATOR_LDO3),
99956 +       [PCF50633_REGULATOR_LDO4] =
99957 +               PCF50633_REGULATOR("ldo4", PCF50633_REGULATOR_LDO4),
99958 +       [PCF50633_REGULATOR_LDO5] =
99959 +               PCF50633_REGULATOR("ldo5", PCF50633_REGULATOR_LDO5),
99960 +       [PCF50633_REGULATOR_LDO6] =
99961 +               PCF50633_REGULATOR("ldo6", PCF50633_REGULATOR_LDO6),
99962 +       [PCF50633_REGULATOR_HCLDO] =
99963 +               PCF50633_REGULATOR("hcldo", PCF50633_REGULATOR_HCLDO),
99964 +       [PCF50633_REGULATOR_MEMLDO] =
99965 +               PCF50633_REGULATOR("memldo", PCF50633_REGULATOR_MEMLDO),
99966 +};
99967 +
99968 +int __init pcf50633_regulator_probe(struct platform_device *pdev)
99969 +{
99970 +       struct regulator_dev *rdev;
99971 +       struct pcf50633 *pcf;
99972 +
99973 +       pcf = pdev->dev.driver_data;
99974 +
99975 +       rdev = regulator_register(&regulators[pdev->id], &pdev->dev, pcf);
99976 +       if (IS_ERR(rdev))
99977 +               return PTR_ERR(rdev);
99978 +
99979 +       if (pcf->pdata->regulator_registered)
99980 +               pcf->pdata->regulator_registered(pcf, pdev->id);
99981 +
99982 +       return 0;
99983 +}
99984 +
99985 +static int __devexit pcf50633_regulator_remove(struct platform_device *pdev)
99986 +{
99987 +       struct regulator_dev *rdev = platform_get_drvdata(pdev);
99988 +
99989 +       regulator_unregister(rdev);
99990 +
99991 +       return 0;
99992 +}
99993 +
99994 +struct platform_driver pcf50633_regulator_driver = {
99995 +       .driver = {
99996 +               .name = "pcf50633-regltr",
99997 +       },
99998 +       .probe = pcf50633_regulator_probe,
99999 +       .remove = __devexit_p(pcf50633_regulator_remove),
100000 +};
100001 +
100002 +static int __init pcf50633_regulator_init(void)
100003 +{
100004 +       return platform_driver_register(&pcf50633_regulator_driver);
100005 +}
100006 +module_init(pcf50633_regulator_init);
100007 +
100008 +static void __exit pcf50633_regulator_exit(void)
100009 +{
100010 +       platform_driver_unregister(&pcf50633_regulator_driver);
100011 +}
100012 +module_exit(pcf50633_regulator_exit);
100013 +
100014 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
100015 +MODULE_DESCRIPTION("PCF50633 regulator driver");
100016 +MODULE_LICENSE("GPL");
100017 +MODULE_ALIAS("platform:pcf50633-regulator");
100018 Index: linux-2.6.28/drivers/rtc/Kconfig
100019 ===================================================================
100020 --- linux-2.6.28.orig/drivers/rtc/Kconfig       2008-12-25 00:26:37.000000000 +0100
100021 +++ linux-2.6.28/drivers/rtc/Kconfig    2009-01-02 00:01:56.000000000 +0100
100022 @@ -219,6 +219,18 @@ config RTC_DRV_PCF8583
100023           This driver can also be built as a module. If so, the module
100024           will be called rtc-pcf8583.
100025
100026 +config RTC_DRV_PCF50633
100027 +       tristate "Philips PCF50633"
100028 +       help
100029 +         If you say yes here you get support for the Philips PCF50633
100030 +         PMU's RTC.
100031 +
100032 +config RTC_DRV_PCF50606
100033 +       tristate "Philips PCF50606"
100034 +       help
100035 +         If you say yes here you get support for the Philips PCF50606
100036 +         PMU's RTC.
100037 +
100038  config RTC_DRV_M41T80
100039         tristate "ST M41T65/M41T80/81/82/83/84/85/87"
100040         help
100041 Index: linux-2.6.28/drivers/rtc/Makefile
100042 ===================================================================
100043 --- linux-2.6.28.orig/drivers/rtc/Makefile      2008-12-25 00:26:37.000000000 +0100
100044 +++ linux-2.6.28/drivers/rtc/Makefile   2009-01-02 00:01:56.000000000 +0100
100045 @@ -50,6 +50,8 @@ obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max
100046  obj-$(CONFIG_RTC_DRV_OMAP)     += rtc-omap.o
100047  obj-$(CONFIG_RTC_DRV_PCF8563)  += rtc-pcf8563.o
100048  obj-$(CONFIG_RTC_DRV_PCF8583)  += rtc-pcf8583.o
100049 +obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o
100050 +obj-$(CONFIG_RTC_DRV_PCF50606) += rtc-pcf50606.o
100051  obj-$(CONFIG_RTC_DRV_PL030)    += rtc-pl030.o
100052  obj-$(CONFIG_RTC_DRV_PL031)    += rtc-pl031.o
100053  obj-$(CONFIG_RTC_DRV_PARISC)   += rtc-parisc.o
100054 Index: linux-2.6.28/drivers/rtc/rtc-pcf50606.c
100055 ===================================================================
100056 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
100057 +++ linux-2.6.28/drivers/rtc/rtc-pcf50606.c     2009-01-02 00:01:56.000000000 +0100
100058 @@ -0,0 +1,300 @@
100059 +/* Philips PCF50606 RTC Driver
100060 + *
100061 + * (C) 2006-2008 by Openmoko, Inc.
100062 + * Author: Balaji Rao <balajirrao@openmoko.org>
100063 + * All rights reserved.
100064 + *
100065 + * Broken down from monstrous PCF50606 driver mainly by
100066 + * Harald Welte, Andy Green and Werner Almesberger
100067 + *
100068 + * This program is free software; you can redistribute it and/or
100069 + * modify it under the terms of the GNU General Public License as
100070 + * published by the Free Software Foundation; either version 2 of
100071 + * the License, or (at your option) any later version.
100072 + *
100073 + * This program is distributed in the hope that it will be useful,
100074 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
100075 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
100076 + * GNU General Public License for more details.
100077 + *
100078 + * You should have received a copy of the GNU General Public License
100079 + * along with this program; if not, write to the Free Software
100080 + * Foundation, Inc., 59 Temple Place, Suite 060, Boston,
100081 + * MA 02111-1307 USA
100082 + */
100083 +
100084 +#include <linux/rtc.h>
100085 +#include <linux/platform_device.h>
100086 +#include <linux/bcd.h>
100087 +
100088 +#include <linux/mfd/pcf50606/core.h>
100089 +#include <linux/mfd/pcf50606/rtc.h>
100090 +
100091 +enum pcf50606_time_indexes {
100092 +       PCF50606_TI_SEC = 0,
100093 +       PCF50606_TI_MIN,
100094 +       PCF50606_TI_HOUR,
100095 +       PCF50606_TI_WKDAY,
100096 +       PCF50606_TI_DAY,
100097 +       PCF50606_TI_MONTH,
100098 +       PCF50606_TI_YEAR,
100099 +       PCF50606_TI_EXTENT /* always last */
100100 +};
100101 +
100102 +
100103 +struct pcf50606_time {
100104 +       u_int8_t time[PCF50606_TI_EXTENT];
100105 +};
100106 +
100107 +static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50606_time *pcf)
100108 +{
100109 +       rtc->tm_sec = bcd2bin(pcf->time[PCF50606_TI_SEC]);
100110 +       rtc->tm_min = bcd2bin(pcf->time[PCF50606_TI_MIN]);
100111 +       rtc->tm_hour = bcd2bin(pcf->time[PCF50606_TI_HOUR]);
100112 +       rtc->tm_wday = bcd2bin(pcf->time[PCF50606_TI_WKDAY]);
100113 +       rtc->tm_mday = bcd2bin(pcf->time[PCF50606_TI_DAY]);
100114 +       rtc->tm_mon = bcd2bin(pcf->time[PCF50606_TI_MONTH]);
100115 +       rtc->tm_year = bcd2bin(pcf->time[PCF50606_TI_YEAR]) + 100;
100116 +}
100117 +
100118 +static void rtc2pcf_time(struct pcf50606_time *pcf, struct rtc_time *rtc)
100119 +{
100120 +       pcf->time[PCF50606_TI_SEC] = bin2bcd(rtc->tm_sec);
100121 +       pcf->time[PCF50606_TI_MIN] = bin2bcd(rtc->tm_min);
100122 +       pcf->time[PCF50606_TI_HOUR] = bin2bcd(rtc->tm_hour);
100123 +       pcf->time[PCF50606_TI_WKDAY] = bin2bcd(rtc->tm_wday);
100124 +       pcf->time[PCF50606_TI_DAY] = bin2bcd(rtc->tm_mday);
100125 +       pcf->time[PCF50606_TI_MONTH] = bin2bcd(rtc->tm_mon);
100126 +       pcf->time[PCF50606_TI_YEAR] = bin2bcd(rtc->tm_year - 100);
100127 +}
100128 +
100129 +static int pcf50606_rtc_ioctl(struct device *dev, unsigned int cmd,
100130 +                             unsigned long arg)
100131 +{
100132 +       struct pcf50606 *pcf;
100133 +
100134 +       pcf = dev_get_drvdata(dev);
100135 +
100136 +       switch (cmd) {
100137 +       case RTC_AIE_OFF:
100138 +               /* disable the alarm interrupt */
100139 +               pcf->rtc.alarm_enabled = 0;
100140 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
100141 +               return 0;
100142 +       case RTC_AIE_ON:
100143 +               /* enable the alarm interrupt */
100144 +               pcf->rtc.alarm_enabled = 1;
100145 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
100146 +               return 0;
100147 +       case RTC_PIE_OFF:
100148 +               /* disable periodic interrupt (hz tick) */
100149 +               pcf->rtc.second_enabled = 0;
100150 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_SECOND);
100151 +               return 0;
100152 +       case RTC_PIE_ON:
100153 +               /* ensable periodic interrupt (hz tick) */
100154 +               pcf->rtc.second_enabled = 1;
100155 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_SECOND);
100156 +               return 0;
100157 +       }
100158 +       return -ENOIOCTLCMD;
100159 +}
100160 +
100161 +static int pcf50606_rtc_read_time(struct device *dev, struct rtc_time *tm)
100162 +{
100163 +       struct pcf50606 *pcf;
100164 +       struct pcf50606_time pcf_tm;
100165 +       int ret;
100166 +
100167 +       pcf = dev_get_drvdata(dev);
100168 +
100169 +       ret = pcf50606_read_block(pcf, PCF50606_REG_RTCSC,
100170 +                                           PCF50606_TI_EXTENT,
100171 +                                           &pcf_tm.time[0]);
100172 +       if (ret != PCF50606_TI_EXTENT)
100173 +               dev_err(dev, "Failed to read time\n");
100174 +
100175 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
100176 +               pcf_tm.time[PCF50606_TI_DAY],
100177 +               pcf_tm.time[PCF50606_TI_MONTH],
100178 +               pcf_tm.time[PCF50606_TI_YEAR],
100179 +               pcf_tm.time[PCF50606_TI_HOUR],
100180 +               pcf_tm.time[PCF50606_TI_MIN],
100181 +               pcf_tm.time[PCF50606_TI_SEC]);
100182 +
100183 +       pcf2rtc_time(tm, &pcf_tm);
100184 +
100185 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
100186 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
100187 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
100188 +
100189 +       return 0;
100190 +}
100191 +
100192 +static int pcf50606_rtc_set_time(struct device *dev, struct rtc_time *tm)
100193 +{
100194 +       struct pcf50606 *pcf;
100195 +       struct pcf50606_time pcf_tm;
100196 +       int ret;
100197 +       int second_masked, alarm_masked;
100198 +
100199 +       pcf = dev_get_drvdata(dev);
100200 +
100201 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
100202 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
100203 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
100204 +       rtc2pcf_time(&pcf_tm, tm);
100205 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
100206 +               pcf_tm.time[PCF50606_TI_DAY],
100207 +               pcf_tm.time[PCF50606_TI_MONTH],
100208 +               pcf_tm.time[PCF50606_TI_YEAR],
100209 +               pcf_tm.time[PCF50606_TI_HOUR],
100210 +               pcf_tm.time[PCF50606_TI_MIN],
100211 +               pcf_tm.time[PCF50606_TI_SEC]);
100212 +
100213 +
100214 +       second_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_SECOND);
100215 +       alarm_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_ALARM);
100216 +
100217 +       if (!second_masked)
100218 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_SECOND);
100219 +       if (!alarm_masked)
100220 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
100221 +
100222 +       ret = pcf50606_write_block(pcf, PCF50606_REG_RTCSC,
100223 +                                            PCF50606_TI_EXTENT,
100224 +                                            &pcf_tm.time[0]);
100225 +       if (ret)
100226 +               dev_err(dev, "Failed to set time %d\n", ret);
100227 +
100228 +       if (!second_masked)
100229 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_SECOND);
100230 +       if (!alarm_masked)
100231 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
100232 +
100233 +
100234 +       return 0;
100235 +}
100236 +
100237 +static int pcf50606_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
100238 +{
100239 +       struct pcf50606 *pcf;
100240 +       struct pcf50606_time pcf_tm;
100241 +       int ret;
100242 +
100243 +       pcf = dev_get_drvdata(dev);
100244 +
100245 +       alrm->enabled = pcf->rtc.alarm_enabled;
100246 +
100247 +       ret = pcf50606_read_block(pcf, PCF50606_REG_RTCSCA,
100248 +                               PCF50606_TI_EXTENT, &pcf_tm.time[0]);
100249 +
100250 +       if (ret != PCF50606_TI_EXTENT)
100251 +               dev_err(dev, "Failed to read Alarm time :-(\n");
100252 +
100253 +       pcf2rtc_time(&alrm->time, &pcf_tm);
100254 +
100255 +       return 0;
100256 +}
100257 +
100258 +static int pcf50606_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
100259 +{
100260 +       struct pcf50606 *pcf;
100261 +       struct pcf50606_time pcf_tm;
100262 +       int ret, alarm_masked;
100263 +
100264 +       pcf = dev_get_drvdata(dev);
100265 +
100266 +       rtc2pcf_time(&pcf_tm, &alrm->time);
100267 +
100268 +       /* do like mktime does and ignore tm_wday */
100269 +       pcf_tm.time[PCF50606_TI_WKDAY] = 7;
100270 +
100271 +       alarm_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_ALARM);
100272 +
100273 +       /* disable alarm interrupt */
100274 +       if (!alarm_masked)
100275 +               pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
100276 +
100277 +       ret = pcf50606_write_block(pcf, PCF50606_REG_RTCSCA,
100278 +                                       PCF50606_TI_EXTENT, &pcf_tm.time[0]);
100279 +       if (ret)
100280 +               dev_err(dev, "Failed to write alarm time  %d\n", ret);
100281 +
100282 +       if (!alarm_masked)
100283 +               pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
100284 +
100285 +       return 0;
100286 +}
100287 +static struct rtc_class_ops pcf50606_rtc_ops = {
100288 +       .ioctl          = pcf50606_rtc_ioctl,
100289 +       .read_time      = pcf50606_rtc_read_time,
100290 +       .set_time       = pcf50606_rtc_set_time,
100291 +       .read_alarm     = pcf50606_rtc_read_alarm,
100292 +       .set_alarm      = pcf50606_rtc_set_alarm,
100293 +};
100294 +
100295 +static void pcf50606_rtc_irq(struct pcf50606 *pcf, int irq, void *unused)
100296 +{
100297 +       switch (irq) {
100298 +       case PCF50606_IRQ_ALARM:
100299 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_AF | RTC_IRQF);
100300 +               break;
100301 +       case PCF50606_IRQ_SECOND:
100302 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_PF | RTC_IRQF);
100303 +               break;
100304 +       }
100305 +}
100306 +
100307 +static int pcf50606_rtc_probe(struct platform_device *pdev)
100308 +{
100309 +       struct rtc_device *rtc;
100310 +       struct pcf50606 *pcf;
100311 +
100312 +       rtc = rtc_device_register("pcf50606", &pdev->dev,
100313 +                                       &pcf50606_rtc_ops, THIS_MODULE);
100314 +       if (IS_ERR(rtc))
100315 +               return -ENODEV;
100316 +
100317 +       pcf = platform_get_drvdata(pdev);
100318 +
100319 +       /* Set up IRQ handlers */
100320 +       pcf->irq_handler[PCF50606_IRQ_ALARM].handler = pcf50606_rtc_irq;
100321 +       pcf->irq_handler[PCF50606_IRQ_SECOND].handler = pcf50606_rtc_irq;
100322 +
100323 +       pcf->rtc.rtc_dev = rtc;
100324 +
100325 +       return 0;
100326 +}
100327 +
100328 +static int pcf50606_rtc_remove(struct platform_device *pdev)
100329 +{
100330 +       return 0;
100331 +}
100332 +
100333 +
100334 +static struct platform_driver pcf50606_rtc_driver = {
100335 +       .driver = {
100336 +               .name = "pcf50606-rtc",
100337 +       },
100338 +       .probe = pcf50606_rtc_probe,
100339 +       .remove = __devexit_p(pcf50606_rtc_remove),
100340 +};
100341 +
100342 +static int __init pcf50606_rtc_init(void)
100343 +{
100344 +       return platform_driver_register(&pcf50606_rtc_driver);
100345 +}
100346 +module_init(pcf50606_rtc_init);
100347 +
100348 +static void __exit pcf50606_rtc_exit(void)
100349 +{
100350 +       platform_driver_unregister(&pcf50606_rtc_driver);
100351 +}
100352 +module_exit(pcf50606_rtc_exit);
100353 +
100354 +
100355 +MODULE_DESCRIPTION("RTC driver for NXP PCF50606 power management unit");
100356 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
100357 +MODULE_LICENSE("GPL");
100358 +
100359 Index: linux-2.6.28/drivers/rtc/rtc-pcf50633.c
100360 ===================================================================
100361 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
100362 +++ linux-2.6.28/drivers/rtc/rtc-pcf50633.c     2009-01-02 00:01:56.000000000 +0100
100363 @@ -0,0 +1,300 @@
100364 +/* Philips PCF50633 RTC Driver
100365 + *
100366 + * (C) 2006-2008 by Openmoko, Inc.
100367 + * Author: Balaji Rao <balajirrao@openmoko.org>
100368 + * All rights reserved.
100369 + *
100370 + * Broken down from monstrous PCF50633 driver mainly by
100371 + * Harald Welte, Andy Green and Werner Almesberger
100372 + *
100373 + * This program is free software; you can redistribute it and/or
100374 + * modify it under the terms of the GNU General Public License as
100375 + * published by the Free Software Foundation; either version 2 of
100376 + * the License, or (at your option) any later version.
100377 + *
100378 + * This program is distributed in the hope that it will be useful,
100379 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
100380 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
100381 + * GNU General Public License for more details.
100382 + *
100383 + * You should have received a copy of the GNU General Public License
100384 + * along with this program; if not, write to the Free Software
100385 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
100386 + * MA 02111-1307 USA
100387 + */
100388 +
100389 +#include <linux/rtc.h>
100390 +#include <linux/platform_device.h>
100391 +#include <linux/bcd.h>
100392 +
100393 +#include <linux/mfd/pcf50633/core.h>
100394 +#include <linux/mfd/pcf50633/rtc.h>
100395 +
100396 +enum pcf50633_time_indexes {
100397 +       PCF50633_TI_SEC = 0,
100398 +       PCF50633_TI_MIN,
100399 +       PCF50633_TI_HOUR,
100400 +       PCF50633_TI_WKDAY,
100401 +       PCF50633_TI_DAY,
100402 +       PCF50633_TI_MONTH,
100403 +       PCF50633_TI_YEAR,
100404 +       PCF50633_TI_EXTENT /* always last */
100405 +};
100406 +
100407 +
100408 +struct pcf50633_time {
100409 +       u_int8_t time[PCF50633_TI_EXTENT];
100410 +};
100411 +
100412 +static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50633_time *pcf)
100413 +{
100414 +       rtc->tm_sec = bcd2bin(pcf->time[PCF50633_TI_SEC]);
100415 +       rtc->tm_min = bcd2bin(pcf->time[PCF50633_TI_MIN]);
100416 +       rtc->tm_hour = bcd2bin(pcf->time[PCF50633_TI_HOUR]);
100417 +       rtc->tm_wday = bcd2bin(pcf->time[PCF50633_TI_WKDAY]);
100418 +       rtc->tm_mday = bcd2bin(pcf->time[PCF50633_TI_DAY]);
100419 +       rtc->tm_mon = bcd2bin(pcf->time[PCF50633_TI_MONTH]);
100420 +       rtc->tm_year = bcd2bin(pcf->time[PCF50633_TI_YEAR]) + 100;
100421 +}
100422 +
100423 +static void rtc2pcf_time(struct pcf50633_time *pcf, struct rtc_time *rtc)
100424 +{
100425 +       pcf->time[PCF50633_TI_SEC] = bin2bcd(rtc->tm_sec);
100426 +       pcf->time[PCF50633_TI_MIN] = bin2bcd(rtc->tm_min);
100427 +       pcf->time[PCF50633_TI_HOUR] = bin2bcd(rtc->tm_hour);
100428 +       pcf->time[PCF50633_TI_WKDAY] = bin2bcd(rtc->tm_wday);
100429 +       pcf->time[PCF50633_TI_DAY] = bin2bcd(rtc->tm_mday);
100430 +       pcf->time[PCF50633_TI_MONTH] = bin2bcd(rtc->tm_mon);
100431 +       pcf->time[PCF50633_TI_YEAR] = bin2bcd(rtc->tm_year - 100);
100432 +}
100433 +
100434 +static int pcf50633_rtc_ioctl(struct device *dev, unsigned int cmd,
100435 +                             unsigned long arg)
100436 +{
100437 +       struct pcf50633 *pcf;
100438 +
100439 +       pcf = dev_get_drvdata(dev);
100440 +
100441 +       switch (cmd) {
100442 +       case RTC_AIE_OFF:
100443 +               /* disable the alarm interrupt */
100444 +               pcf->rtc.alarm_enabled = 0;
100445 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
100446 +               return 0;
100447 +       case RTC_AIE_ON:
100448 +               /* enable the alarm interrupt */
100449 +               pcf->rtc.alarm_enabled = 1;
100450 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
100451 +               return 0;
100452 +       case RTC_PIE_OFF:
100453 +               /* disable periodic interrupt (hz tick) */
100454 +               pcf->rtc.second_enabled = 0;
100455 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_SECOND);
100456 +               return 0;
100457 +       case RTC_PIE_ON:
100458 +               /* ensable periodic interrupt (hz tick) */
100459 +               pcf->rtc.second_enabled = 1;
100460 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_SECOND);
100461 +               return 0;
100462 +       }
100463 +       return -ENOIOCTLCMD;
100464 +}
100465 +
100466 +static int pcf50633_rtc_read_time(struct device *dev, struct rtc_time *tm)
100467 +{
100468 +       struct pcf50633 *pcf;
100469 +       struct pcf50633_time pcf_tm;
100470 +       int ret;
100471 +
100472 +       pcf = dev_get_drvdata(dev);
100473 +
100474 +       ret = pcf50633_read_block(pcf, PCF50633_REG_RTCSC,
100475 +                                           PCF50633_TI_EXTENT,
100476 +                                           &pcf_tm.time[0]);
100477 +       if (ret != PCF50633_TI_EXTENT)
100478 +               dev_err(dev, "Failed to read time\n");
100479 +
100480 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
100481 +               pcf_tm.time[PCF50633_TI_DAY],
100482 +               pcf_tm.time[PCF50633_TI_MONTH],
100483 +               pcf_tm.time[PCF50633_TI_YEAR],
100484 +               pcf_tm.time[PCF50633_TI_HOUR],
100485 +               pcf_tm.time[PCF50633_TI_MIN],
100486 +               pcf_tm.time[PCF50633_TI_SEC]);
100487 +
100488 +       pcf2rtc_time(tm, &pcf_tm);
100489 +
100490 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
100491 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
100492 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
100493 +
100494 +       return 0;
100495 +}
100496 +
100497 +static int pcf50633_rtc_set_time(struct device *dev, struct rtc_time *tm)
100498 +{
100499 +       struct pcf50633 *pcf;
100500 +       struct pcf50633_time pcf_tm;
100501 +       int ret;
100502 +       int second_masked, alarm_masked;
100503 +
100504 +       pcf = dev_get_drvdata(dev);
100505 +
100506 +       dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
100507 +               tm->tm_mday, tm->tm_mon, tm->tm_year,
100508 +               tm->tm_hour, tm->tm_min, tm->tm_sec);
100509 +       rtc2pcf_time(&pcf_tm, tm);
100510 +       dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
100511 +               pcf_tm.time[PCF50633_TI_DAY],
100512 +               pcf_tm.time[PCF50633_TI_MONTH],
100513 +               pcf_tm.time[PCF50633_TI_YEAR],
100514 +               pcf_tm.time[PCF50633_TI_HOUR],
100515 +               pcf_tm.time[PCF50633_TI_MIN],
100516 +               pcf_tm.time[PCF50633_TI_SEC]);
100517 +
100518 +
100519 +       second_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_SECOND);
100520 +       alarm_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_ALARM);
100521 +
100522 +       if (!second_masked)
100523 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_SECOND);
100524 +       if (!alarm_masked)
100525 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
100526 +
100527 +       ret = pcf50633_write_block(pcf, PCF50633_REG_RTCSC,
100528 +                                            PCF50633_TI_EXTENT,
100529 +                                            &pcf_tm.time[0]);
100530 +       if (ret)
100531 +               dev_err(dev, "Failed to set time %d\n", ret);
100532 +
100533 +       if (!second_masked)
100534 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_SECOND);
100535 +       if (!alarm_masked)
100536 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
100537 +
100538 +
100539 +       return 0;
100540 +}
100541 +
100542 +static int pcf50633_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
100543 +{
100544 +       struct pcf50633 *pcf;
100545 +       struct pcf50633_time pcf_tm;
100546 +       int ret;
100547 +
100548 +       pcf = dev_get_drvdata(dev);
100549 +
100550 +       alrm->enabled = pcf->rtc.alarm_enabled;
100551 +
100552 +       ret = pcf50633_read_block(pcf, PCF50633_REG_RTCSCA,
100553 +                               PCF50633_TI_EXTENT, &pcf_tm.time[0]);
100554 +
100555 +       if (ret != PCF50633_TI_EXTENT)
100556 +               dev_err(dev, "Failed to read Alarm time :-(\n");
100557 +
100558 +       pcf2rtc_time(&alrm->time, &pcf_tm);
100559 +
100560 +       return 0;
100561 +}
100562 +
100563 +static int pcf50633_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
100564 +{
100565 +       struct pcf50633 *pcf;
100566 +       struct pcf50633_time pcf_tm;
100567 +       int ret, alarm_masked;
100568 +
100569 +       pcf = dev_get_drvdata(dev);
100570 +
100571 +       rtc2pcf_time(&pcf_tm, &alrm->time);
100572 +
100573 +       /* do like mktime does and ignore tm_wday */
100574 +       pcf_tm.time[PCF50633_TI_WKDAY] = 7;
100575 +
100576 +       alarm_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_ALARM);
100577 +
100578 +       /* disable alarm interrupt */
100579 +       if (!alarm_masked)
100580 +               pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
100581 +
100582 +       ret = pcf50633_write_block(pcf, PCF50633_REG_RTCSCA,
100583 +                                       PCF50633_TI_EXTENT, &pcf_tm.time[0]);
100584 +       if (ret)
100585 +               dev_err(dev, "Failed to write alarm time  %d\n", ret);
100586 +
100587 +       if (!alarm_masked)
100588 +               pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
100589 +
100590 +       return 0;
100591 +}
100592 +static struct rtc_class_ops pcf50633_rtc_ops = {
100593 +       .ioctl          = pcf50633_rtc_ioctl,
100594 +       .read_time      = pcf50633_rtc_read_time,
100595 +       .set_time       = pcf50633_rtc_set_time,
100596 +       .read_alarm     = pcf50633_rtc_read_alarm,
100597 +       .set_alarm      = pcf50633_rtc_set_alarm,
100598 +};
100599 +
100600 +static void pcf50633_rtc_irq(struct pcf50633 *pcf, int irq, void *unused)
100601 +{
100602 +       switch (irq) {
100603 +       case PCF50633_IRQ_ALARM:
100604 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_AF | RTC_IRQF);
100605 +               break;
100606 +       case PCF50633_IRQ_SECOND:
100607 +               rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_PF | RTC_IRQF);
100608 +               break;
100609 +       }
100610 +}
100611 +
100612 +static int pcf50633_rtc_probe(struct platform_device *pdev)
100613 +{
100614 +       struct rtc_device *rtc;
100615 +       struct pcf50633 *pcf;
100616 +
100617 +       rtc = rtc_device_register("pcf50633", &pdev->dev,
100618 +                                       &pcf50633_rtc_ops, THIS_MODULE);
100619 +       if (IS_ERR(rtc))
100620 +               return -ENODEV;
100621 +
100622 +       pcf = platform_get_drvdata(pdev);
100623 +
100624 +       /* Set up IRQ handlers */
100625 +       pcf->irq_handler[PCF50633_IRQ_ALARM].handler = pcf50633_rtc_irq;
100626 +       pcf->irq_handler[PCF50633_IRQ_SECOND].handler = pcf50633_rtc_irq;
100627 +
100628 +       pcf->rtc.rtc_dev = rtc;
100629 +
100630 +       return 0;
100631 +}
100632 +
100633 +static int pcf50633_rtc_remove(struct platform_device *pdev)
100634 +{
100635 +       return 0;
100636 +}
100637 +
100638 +
100639 +static struct platform_driver pcf50633_rtc_driver = {
100640 +       .driver = {
100641 +               .name = "pcf50633-rtc",
100642 +       },
100643 +       .probe = pcf50633_rtc_probe,
100644 +       .remove = __devexit_p(pcf50633_rtc_remove),
100645 +};
100646 +
100647 +static int __init pcf50633_rtc_init(void)
100648 +{
100649 +       return platform_driver_register(&pcf50633_rtc_driver);
100650 +}
100651 +module_init(pcf50633_rtc_init);
100652 +
100653 +static void __exit pcf50633_rtc_exit(void)
100654 +{
100655 +       platform_driver_unregister(&pcf50633_rtc_driver);
100656 +}
100657 +module_exit(pcf50633_rtc_exit);
100658 +
100659 +
100660 +MODULE_DESCRIPTION("RTC driver for NXP PCF50633 power management unit");
100661 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
100662 +MODULE_LICENSE("GPL");
100663 +
100664 Index: linux-2.6.28/drivers/rtc/rtc-s3c.c
100665 ===================================================================
100666 --- linux-2.6.28.orig/drivers/rtc/rtc-s3c.c     2008-12-25 00:26:37.000000000 +0100
100667 +++ linux-2.6.28/drivers/rtc/rtc-s3c.c  2009-01-02 00:01:56.000000000 +0100
100668 @@ -26,7 +26,7 @@
100669  #include <asm/uaccess.h>
100670  #include <asm/io.h>
100671  #include <asm/irq.h>
100672 -#include <asm/plat-s3c/regs-rtc.h>
100673 +#include <plat/regs-rtc.h>
100674
100675  /* I have yet to find an S3C implementation with more than one
100676   * of these rtc blocks in */
100677 Index: linux-2.6.28/drivers/serial/Kconfig
100678 ===================================================================
100679 --- linux-2.6.28.orig/drivers/serial/Kconfig    2008-12-25 00:26:37.000000000 +0100
100680 +++ linux-2.6.28/drivers/serial/Kconfig 2009-01-02 00:01:56.000000000 +0100
100681 @@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE
100682
100683  config SERIAL_SAMSUNG
100684         tristate "Samsung SoC serial support"
100685 -       depends on ARM && PLAT_S3C24XX
100686 +       depends on ARM && PLAT_S3C
100687         select SERIAL_CORE
100688         help
100689           Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
100690 @@ -455,6 +455,16 @@ config SERIAL_SAMSUNG
100691           provide all of these ports, depending on how the serial port
100692           pins are configured.
100693
100694 +config SERIAL_SAMSUNG_UARTS
100695 +       int
100696 +       depends on SERIAL_SAMSUNG
100697 +       default 2 if ARCH_S3C2400
100698 +       default 4 if ARCH_S3C64XX || CPU_S3C2443
100699 +       default 3
100700 +       help
100701 +         Select the number of available UART ports for the Samsung S3C
100702 +         serial driver
100703 +
100704  config SERIAL_SAMSUNG_DEBUG
100705         bool "Samsung SoC serial debug"
100706         depends on SERIAL_SAMSUNG && DEBUG_LL
100707 @@ -508,7 +518,20 @@ config SERIAL_S3C2440
100708         help
100709           Serial port support for the Samsung S3C2440 and S3C2442 SoC
100710
100711 -
100712 +config SERIAL_S3C24A0
100713 +       tristate "Samsung S3C24A0 Serial port support"
100714 +       depends on SERIAL_SAMSUNG && CPU_S3C24A0
100715 +       default y if CPU_S3C24A0
100716 +       help
100717 +         Serial port support for the Samsung S3C24A0 SoC
100718 +
100719 +config SERIAL_S3C6400
100720 +       tristate "Samsung S3C6400/S3C6410 Serial port support"
100721 +       depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410)
100722 +       default y
100723 +       help
100724 +         Serial port support for the Samsung S3C6400 and S3C6410
100725 +         SoCs
100726
100727  config SERIAL_DZ
100728         bool "DECstation DZ serial driver"
100729 Index: linux-2.6.28/drivers/serial/Makefile
100730 ===================================================================
100731 --- linux-2.6.28.orig/drivers/serial/Makefile   2008-12-25 00:26:37.000000000 +0100
100732 +++ linux-2.6.28/drivers/serial/Makefile        2009-01-02 00:01:56.000000000 +0100
100733 @@ -41,6 +41,8 @@ obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.
100734  obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
100735  obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
100736  obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
100737 +obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
100738 +obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
100739  obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
100740  obj-$(CONFIG_SERIAL_MUX) += mux.o
100741  obj-$(CONFIG_SERIAL_68328) += 68328serial.o
100742 Index: linux-2.6.28/drivers/serial/s3c2410.c
100743 ===================================================================
100744 --- linux-2.6.28.orig/drivers/serial/s3c2410.c  2008-12-25 00:26:37.000000000 +0100
100745 +++ linux-2.6.28/drivers/serial/s3c2410.c       2009-01-02 00:01:56.000000000 +0100
100746 @@ -19,6 +19,7 @@
100747  #include <linux/serial.h>
100748
100749  #include <asm/irq.h>
100750 +
100751  #include <mach/hardware.h>
100752
100753  #include <plat/regs-serial.h>
100754 Index: linux-2.6.28/drivers/serial/s3c24a0.c
100755 ===================================================================
100756 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
100757 +++ linux-2.6.28/drivers/serial/s3c24a0.c       2009-01-02 00:01:56.000000000 +0100
100758 @@ -0,0 +1,118 @@
100759 +/* linux/drivers/serial/s3c24a0.c
100760 + *
100761 + * Driver for Samsung S3C24A0 SoC onboard UARTs.
100762 + *
100763 + * Based on drivers/serial/s3c2410.c
100764 + *
100765 + * Author: Sandeep Patil <sandeep.patil@azingo.com>
100766 + *
100767 + * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
100768 + *     http://armlinux.simtec.co.uk/
100769 + *
100770 + * This program is free software; you can redistribute it and/or modify
100771 + * it under the terms of the GNU General Public License version 2 as
100772 + * published by the Free Software Foundation.
100773 +*/
100774 +
100775 +#include <linux/module.h>
100776 +#include <linux/ioport.h>
100777 +#include <linux/platform_device.h>
100778 +#include <linux/init.h>
100779 +#include <linux/serial_core.h>
100780 +#include <linux/serial.h>
100781 +#include <linux/io.h>
100782 +#include <linux/irq.h>
100783 +
100784 +#include <mach/hardware.h>
100785 +
100786 +#include <plat/regs-serial.h>
100787 +#include <mach/regs-gpio.h>
100788 +
100789 +#include "samsung.h"
100790 +
100791 +static int s3c24a0_serial_setsource(struct uart_port *port,
100792 +                                   struct s3c24xx_uart_clksrc *clk)
100793 +{
100794 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
100795 +
100796 +       if (strcmp(clk->name, "uclk") == 0)
100797 +               ucon |= S3C2410_UCON_UCLK;
100798 +       else
100799 +               ucon &= ~S3C2410_UCON_UCLK;
100800 +
100801 +       wr_regl(port, S3C2410_UCON, ucon);
100802 +       return 0;
100803 +}
100804 +
100805 +static int s3c24a0_serial_getsource(struct uart_port *port,
100806 +                                   struct s3c24xx_uart_clksrc *clk)
100807 +{
100808 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
100809 +
100810 +       clk->divisor = 1;
100811 +       clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
100812 +
100813 +       return 0;
100814 +}
100815 +
100816 +static int s3c24a0_serial_resetport(struct uart_port *port,
100817 +                                   struct s3c2410_uartcfg *cfg)
100818 +{
100819 +       dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n",
100820 +           port, port->mapbase, cfg);
100821 +
100822 +       wr_regl(port, S3C2410_UCON,  cfg->ucon);
100823 +       wr_regl(port, S3C2410_ULCON, cfg->ulcon);
100824 +
100825 +       /* reset both fifos */
100826 +
100827 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
100828 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon);
100829 +
100830 +       return 0;
100831 +}
100832 +
100833 +static struct s3c24xx_uart_info s3c24a0_uart_inf = {
100834 +       .name           = "Samsung S3C24A0 UART",
100835 +       .type           = PORT_S3C2410,
100836 +       .fifosize       = 16,
100837 +       .rx_fifomask    = S3C24A0_UFSTAT_RXMASK,
100838 +       .rx_fifoshift   = S3C24A0_UFSTAT_RXSHIFT,
100839 +       .rx_fifofull    = S3C24A0_UFSTAT_RXFULL,
100840 +       .tx_fifofull    = S3C24A0_UFSTAT_TXFULL,
100841 +       .tx_fifomask    = S3C24A0_UFSTAT_TXMASK,
100842 +       .tx_fifoshift   = S3C24A0_UFSTAT_TXSHIFT,
100843 +       .get_clksrc     = s3c24a0_serial_getsource,
100844 +       .set_clksrc     = s3c24a0_serial_setsource,
100845 +       .reset_port     = s3c24a0_serial_resetport,
100846 +};
100847 +
100848 +static int s3c24a0_serial_probe(struct platform_device *dev)
100849 +{
100850 +       return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
100851 +}
100852 +
100853 +static struct platform_driver s3c24a0_serial_drv = {
100854 +       .probe          = s3c24a0_serial_probe,
100855 +       .remove         = s3c24xx_serial_remove,
100856 +       .driver         = {
100857 +               .name   = "s3c24a0-uart",
100858 +               .owner  = THIS_MODULE,
100859 +       },
100860 +};
100861 +
100862 +s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
100863 +
100864 +static int __init s3c24a0_serial_init(void)
100865 +{
100866 +       return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
100867 +}
100868 +
100869 +static void __exit s3c24a0_serial_exit(void)
100870 +{
100871 +       platform_driver_unregister(&s3c24a0_serial_drv);
100872 +}
100873 +
100874 +module_init(s3c24a0_serial_init);
100875 +module_exit(s3c24a0_serial_exit);
100876 +
100877 Index: linux-2.6.28/drivers/serial/s3c6400.c
100878 ===================================================================
100879 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
100880 +++ linux-2.6.28/drivers/serial/s3c6400.c       2009-01-02 00:01:56.000000000 +0100
100881 @@ -0,0 +1,152 @@
100882 +/* linux/drivers/serial/s3c6400.c
100883 + *
100884 + * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
100885 + *
100886 + * Copyright 2008 Openmoko,  Inc.
100887 + * Copyright 2008 Simtec Electronics
100888 + *     Ben Dooks <ben@simtec.co.uk>
100889 + *     http://armlinux.simtec.co.uk/
100890 + *
100891 + * This program is free software; you can redistribute it and/or modify
100892 + * it under the terms of the GNU General Public License version 2 as
100893 + * published by the Free Software Foundation.
100894 +*/
100895 +
100896 +#include <linux/module.h>
100897 +#include <linux/ioport.h>
100898 +#include <linux/io.h>
100899 +#include <linux/platform_device.h>
100900 +#include <linux/init.h>
100901 +#include <linux/serial_core.h>
100902 +#include <linux/serial.h>
100903 +
100904 +#include <asm/irq.h>
100905 +#include <mach/hardware.h>
100906 +
100907 +#include <plat/regs-serial.h>
100908 +
100909 +#include "samsung.h"
100910 +
100911 +static int s3c6400_serial_setsource(struct uart_port *port,
100912 +                                   struct s3c24xx_uart_clksrc *clk)
100913 +{
100914 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
100915 +
100916 +       if (strcmp(clk->name, "uclk0") == 0) {
100917 +               ucon &= ~S3C6400_UCON_CLKMASK;
100918 +               ucon |= S3C6400_UCON_UCLK0;
100919 +       } else if (strcmp(clk->name, "uclk1") == 0)
100920 +               ucon |= S3C6400_UCON_UCLK1;
100921 +       else if (strcmp(clk->name, "pclk") == 0) {
100922 +               /* See notes about transitioning from UCLK to PCLK */
100923 +               ucon &= ~S3C6400_UCON_UCLK0;
100924 +       } else {
100925 +               printk(KERN_ERR "unknown clock source %s\n", clk->name);
100926 +               return -EINVAL;
100927 +       }
100928 +
100929 +       wr_regl(port, S3C2410_UCON, ucon);
100930 +       return 0;
100931 +}
100932 +
100933 +
100934 +static int s3c6400_serial_getsource(struct uart_port *port,
100935 +                                   struct s3c24xx_uart_clksrc *clk)
100936 +{
100937 +       u32 ucon = rd_regl(port, S3C2410_UCON);
100938 +
100939 +       clk->divisor = 1;
100940 +
100941 +       switch (ucon & S3C6400_UCON_CLKMASK) {
100942 +       case S3C6400_UCON_UCLK0:
100943 +               clk->name = "uclk0";
100944 +               break;
100945 +
100946 +       case S3C6400_UCON_UCLK1:
100947 +               clk->name = "uclk1";
100948 +               break;
100949 +
100950 +       case S3C6400_UCON_PCLK:
100951 +       case S3C6400_UCON_PCLK2:
100952 +               clk->name = "pclk";
100953 +               break;
100954 +       }
100955 +
100956 +       return 0;
100957 +}
100958 +
100959 +static int s3c6400_serial_resetport(struct uart_port *port,
100960 +                                   struct s3c2410_uartcfg *cfg)
100961 +{
100962 +       unsigned long ucon = rd_regl(port, S3C2410_UCON);
100963 +
100964 +       dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
100965 +           port, port->mapbase, cfg);
100966 +
100967 +       /* ensure we don't change the clock settings... */
100968 +
100969 +       ucon &= S3C6400_UCON_CLKMASK;
100970 +
100971 +       wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
100972 +       wr_regl(port, S3C2410_ULCON, cfg->ulcon);
100973 +
100974 +       /* reset both fifos */
100975 +
100976 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
100977 +       wr_regl(port, S3C2410_UFCON, cfg->ufcon);
100978 +
100979 +       return 0;
100980 +}
100981 +
100982 +static struct s3c24xx_uart_info s3c6400_uart_inf = {
100983 +       .name           = "Samsung S3C6400 UART",
100984 +       .type           = PORT_S3C6400,
100985 +       .fifosize       = 64,
100986 +       .has_divslot    = 1,
100987 +       .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
100988 +       .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
100989 +       .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
100990 +       .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
100991 +       .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
100992 +       .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
100993 +       .get_clksrc     = s3c6400_serial_getsource,
100994 +       .set_clksrc     = s3c6400_serial_setsource,
100995 +       .reset_port     = s3c6400_serial_resetport,
100996 +};
100997 +
100998 +/* device management */
100999 +
101000 +static int s3c6400_serial_probe(struct platform_device *dev)
101001 +{
101002 +       dbg("s3c6400_serial_probe: dev=%p\n", dev);
101003 +       return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
101004 +}
101005 +
101006 +static struct platform_driver s3c6400_serial_drv = {
101007 +       .probe          = s3c6400_serial_probe,
101008 +       .remove         = s3c24xx_serial_remove,
101009 +       .driver         = {
101010 +               .name   = "s3c6400-uart",
101011 +               .owner  = THIS_MODULE,
101012 +       },
101013 +};
101014 +
101015 +s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
101016 +
101017 +static int __init s3c6400_serial_init(void)
101018 +{
101019 +       return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
101020 +}
101021 +
101022 +static void __exit s3c6400_serial_exit(void)
101023 +{
101024 +       platform_driver_unregister(&s3c6400_serial_drv);
101025 +}
101026 +
101027 +module_init(s3c6400_serial_init);
101028 +module_exit(s3c6400_serial_exit);
101029 +
101030 +MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
101031 +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
101032 +MODULE_LICENSE("GPL v2");
101033 +MODULE_ALIAS("platform:s3c6400-uart");
101034 Index: linux-2.6.28/drivers/serial/samsung.c
101035 ===================================================================
101036 --- linux-2.6.28.orig/drivers/serial/samsung.c  2008-12-25 00:26:37.000000000 +0100
101037 +++ linux-2.6.28/drivers/serial/samsung.c       2009-01-02 00:01:56.000000000 +0100
101038 @@ -42,13 +42,18 @@
101039  #include <linux/serial.h>
101040  #include <linux/delay.h>
101041  #include <linux/clk.h>
101042 +#include <linux/cpufreq.h>
101043
101044  #include <asm/irq.h>
101045
101046  #include <mach/hardware.h>
101047 +#include <mach/map.h>
101048
101049  #include <plat/regs-serial.h>
101050 +#if defined(CONFIG_MACH_NEO1973) && !defined(CONFIG_CPU_S3C6410)
101051  #include <mach/regs-gpio.h>
101052 +#include <mach/regs-clock.h>
101053 +#endif
101054
101055  #include "samsung.h"
101056
101057 @@ -58,19 +63,6 @@
101058  #define S3C24XX_SERIAL_MAJOR   204
101059  #define S3C24XX_SERIAL_MINOR   64
101060
101061 -/* we can support 3 uarts, but not always use them */
101062 -
101063 -#ifdef CONFIG_CPU_S3C2400
101064 -#define NR_PORTS (2)
101065 -#else
101066 -#define NR_PORTS (3)
101067 -#endif
101068 -
101069 -/* port irq numbers */
101070 -
101071 -#define TX_IRQ(port) ((port)->irq + 1)
101072 -#define RX_IRQ(port) ((port)->irq)
101073 -
101074  /* macros to change one thing to another */
101075
101076  #define tx_enabled(port) ((port)->unused[0])
101077 @@ -136,8 +128,10 @@ static void s3c24xx_serial_rx_disable(st
101078
101079  static void s3c24xx_serial_stop_tx(struct uart_port *port)
101080  {
101081 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
101082 +
101083         if (tx_enabled(port)) {
101084 -               disable_irq(TX_IRQ(port));
101085 +               disable_irq(ourport->tx_irq);
101086                 tx_enabled(port) = 0;
101087                 if (port->flags & UPF_CONS_FLOW)
101088                         s3c24xx_serial_rx_enable(port);
101089 @@ -146,11 +140,13 @@ static void s3c24xx_serial_stop_tx(struc
101090
101091  static void s3c24xx_serial_start_tx(struct uart_port *port)
101092  {
101093 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
101094 +
101095         if (!tx_enabled(port)) {
101096                 if (port->flags & UPF_CONS_FLOW)
101097                         s3c24xx_serial_rx_disable(port);
101098
101099 -               enable_irq(TX_IRQ(port));
101100 +               enable_irq(ourport->tx_irq);
101101                 tx_enabled(port) = 1;
101102         }
101103  }
101104 @@ -158,9 +154,11 @@ static void s3c24xx_serial_start_tx(stru
101105
101106  static void s3c24xx_serial_stop_rx(struct uart_port *port)
101107  {
101108 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
101109 +
101110         if (rx_enabled(port)) {
101111                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
101112 -               disable_irq(RX_IRQ(port));
101113 +               disable_irq(ourport->rx_irq);
101114                 rx_enabled(port) = 0;
101115         }
101116  }
101117 @@ -241,7 +239,7 @@ s3c24xx_serial_rx_chars(int irq, void *d
101118                 port->icount.rx++;
101119
101120                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
101121 -                       dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
101122 +                       printk(KERN_DEBUG "rxerr: port ch=0x%02x, rxs=0x%08x\n",
101123                             ch, uerstat);
101124
101125                         /* check for break */
101126 @@ -384,13 +382,13 @@ static void s3c24xx_serial_shutdown(stru
101127         struct s3c24xx_uart_port *ourport = to_ourport(port);
101128
101129         if (ourport->tx_claimed) {
101130 -               free_irq(TX_IRQ(port), ourport);
101131 +               free_irq(ourport->tx_irq, ourport);
101132                 tx_enabled(port) = 0;
101133                 ourport->tx_claimed = 0;
101134         }
101135
101136         if (ourport->rx_claimed) {
101137 -               free_irq(RX_IRQ(port), ourport);
101138 +               free_irq(ourport->rx_irq, ourport);
101139                 ourport->rx_claimed = 0;
101140                 rx_enabled(port) = 0;
101141         }
101142 @@ -407,12 +405,11 @@ static int s3c24xx_serial_startup(struct
101143
101144         rx_enabled(port) = 1;
101145
101146 -       ret = request_irq(RX_IRQ(port),
101147 -                         s3c24xx_serial_rx_chars, 0,
101148 +       ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
101149                           s3c24xx_serial_portname(port), ourport);
101150
101151         if (ret != 0) {
101152 -               printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
101153 +               printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
101154                 return ret;
101155         }
101156
101157 @@ -422,12 +419,11 @@ static int s3c24xx_serial_startup(struct
101158
101159         tx_enabled(port) = 1;
101160
101161 -       ret = request_irq(TX_IRQ(port),
101162 -                         s3c24xx_serial_tx_chars, 0,
101163 +       ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
101164                           s3c24xx_serial_portname(port), ourport);
101165
101166         if (ret) {
101167 -               printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
101168 +               printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
101169                 goto err;
101170         }
101171
101172 @@ -452,6 +448,8 @@ static void s3c24xx_serial_pm(struct uar
101173  {
101174         struct s3c24xx_uart_port *ourport = to_ourport(port);
101175
101176 +       ourport->pm_level = level;
101177 +
101178         switch (level) {
101179         case 3:
101180                 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
101181 @@ -514,6 +512,7 @@ s3c24xx_serial_setsource(struct uart_por
101182  struct baud_calc {
101183         struct s3c24xx_uart_clksrc      *clksrc;
101184         unsigned int                     calc;
101185 +       unsigned int                     divslot;
101186         unsigned int                     quot;
101187         struct clk                      *src;
101188  };
101189 @@ -523,6 +522,7 @@ static int s3c24xx_serial_calcbaud(struc
101190                                    struct s3c24xx_uart_clksrc *clksrc,
101191                                    unsigned int baud)
101192  {
101193 +       struct s3c24xx_uart_port *ourport = to_ourport(port);
101194         unsigned long rate;
101195
101196         calc->src = clk_get(port->dev, clksrc->name);
101197 @@ -533,8 +533,24 @@ static int s3c24xx_serial_calcbaud(struc
101198         rate /= clksrc->divisor;
101199
101200         calc->clksrc = clksrc;
101201 -       calc->quot = (rate + (8 * baud)) / (16 * baud);
101202 -       calc->calc = (rate / (calc->quot * 16));
101203 +
101204 +       if (ourport->info->has_divslot) {
101205 +               unsigned long div = rate / baud;
101206 +
101207 +               /* The UDIVSLOT register on the newer UARTs allows us to
101208 +                * get a divisor adjustment of 1/16th on the baud clock.
101209 +                *
101210 +                * We don't keep the UDIVSLOT value (the 16ths we calculated
101211 +                * by not multiplying the baud by 16) as it is easy enough
101212 +                * to recalculate.
101213 +                */
101214 +
101215 +               calc->quot = div / 16;
101216 +               calc->calc = rate / div;
101217 +       } else {
101218 +               calc->quot = (rate + (8 * baud)) / (16 * baud);
101219 +               calc->calc = (rate / (calc->quot * 16));
101220 +       }
101221
101222         calc->quot--;
101223         return 1;
101224 @@ -617,6 +633,30 @@ static unsigned int s3c24xx_serial_getcl
101225         return best->quot;
101226  }
101227
101228 +/* udivslot_table[]
101229 + *
101230 + * This table takes the fractional value of the baud divisor and gives
101231 + * the recommended setting for the UDIVSLOT register.
101232 + */
101233 +static u16 udivslot_table[16] = {
101234 +       [0] = 0x0000,
101235 +       [1] = 0x0080,
101236 +       [2] = 0x0808,
101237 +       [3] = 0x0888,
101238 +       [4] = 0x2222,
101239 +       [5] = 0x4924,
101240 +       [6] = 0x4A52,
101241 +       [7] = 0x54AA,
101242 +       [8] = 0x5555,
101243 +       [9] = 0xD555,
101244 +       [10] = 0xD5D5,
101245 +       [11] = 0xDDD5,
101246 +       [12] = 0xDDDD,
101247 +       [13] = 0xDFDD,
101248 +       [14] = 0xDFDF,
101249 +       [15] = 0xFFDF,
101250 +};
101251 +
101252  static void s3c24xx_serial_set_termios(struct uart_port *port,
101253                                        struct ktermios *termios,
101254                                        struct ktermios *old)
101255 @@ -629,6 +669,7 @@ static void s3c24xx_serial_set_termios(s
101256         unsigned int baud, quot;
101257         unsigned int ulcon;
101258         unsigned int umcon;
101259 +       unsigned int udivslot = 0;
101260
101261         /*
101262          * We don't support modem control lines.
101263 @@ -650,6 +691,7 @@ static void s3c24xx_serial_set_termios(s
101264         /* check to see if we need  to change clock source */
101265
101266         if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
101267 +               dbg("selecting clock %p\n", clk);
101268                 s3c24xx_serial_setsource(port, clksrc);
101269
101270                 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
101271 @@ -661,6 +703,14 @@ static void s3c24xx_serial_set_termios(s
101272
101273                 ourport->clksrc = clksrc;
101274                 ourport->baudclk = clk;
101275 +               ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
101276 +       }
101277 +
101278 +       if (ourport->info->has_divslot) {
101279 +               unsigned int div = ourport->baudclk_rate / baud;
101280 +
101281 +               udivslot = udivslot_table[div & 15];
101282 +               dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
101283         }
101284
101285         switch (termios->c_cflag & CSIZE) {
101286 @@ -702,12 +752,16 @@ static void s3c24xx_serial_set_termios(s
101287
101288         spin_lock_irqsave(&port->lock, flags);
101289
101290 -       dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
101291 +       dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
101292 +           ulcon, quot, udivslot);
101293
101294         wr_regl(port, S3C2410_ULCON, ulcon);
101295         wr_regl(port, S3C2410_UBRDIV, quot);
101296         wr_regl(port, S3C2410_UMCON, umcon);
101297
101298 +       if (ourport->info->has_divslot)
101299 +               wr_regl(port, S3C2443_DIVSLOT, udivslot);
101300 +
101301         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
101302             rd_regl(port, S3C2410_ULCON),
101303             rd_regl(port, S3C2410_UCON),
101304 @@ -752,6 +806,8 @@ static const char *s3c24xx_serial_type(s
101305                 return "S3C2440";
101306         case PORT_S3C2412:
101307                 return "S3C2412";
101308 +       case PORT_S3C6400:
101309 +               return "S3C6400/10";
101310         default:
101311                 return NULL;
101312         }
101313 @@ -827,14 +883,14 @@ static struct uart_ops s3c24xx_serial_op
101314  static struct uart_driver s3c24xx_uart_drv = {
101315         .owner          = THIS_MODULE,
101316         .dev_name       = "s3c2410_serial",
101317 -       .nr             = 3,
101318 +       .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
101319         .cons           = S3C24XX_SERIAL_CONSOLE,
101320         .driver_name    = S3C24XX_SERIAL_NAME,
101321         .major          = S3C24XX_SERIAL_MAJOR,
101322         .minor          = S3C24XX_SERIAL_MINOR,
101323  };
101324
101325 -static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
101326 +static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
101327         [0] = {
101328                 .port = {
101329                         .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
101330 @@ -859,7 +915,7 @@ static struct s3c24xx_uart_port s3c24xx_
101331                         .line           = 1,
101332                 }
101333         },
101334 -#if NR_PORTS > 2
101335 +#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
101336
101337         [2] = {
101338                 .port = {
101339 @@ -872,10 +928,88 @@ static struct s3c24xx_uart_port s3c24xx_
101340                         .flags          = UPF_BOOT_AUTOCONF,
101341                         .line           = 2,
101342                 }
101343 +       },
101344 +#endif
101345 +#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
101346 +       [3] = {
101347 +               .port = {
101348 +                       .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
101349 +                       .iotype         = UPIO_MEM,
101350 +                       .irq            = IRQ_S3CUART_RX3,
101351 +                       .uartclk        = 0,
101352 +                       .fifosize       = 16,
101353 +                       .ops            = &s3c24xx_serial_ops,
101354 +                       .flags          = UPF_BOOT_AUTOCONF,
101355 +                       .line           = 3,
101356 +               }
101357         }
101358  #endif
101359  };
101360
101361 +#ifdef CONFIG_MACH_NEO1973_GTA02
101362 +static void s3c24xx_serial_force_debug_port_up(void)
101363 +{
101364 +       struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[
101365 +                                                        CONFIG_DEBUG_S3C_UART];
101366 +       struct s3c24xx_uart_clksrc *clksrc = NULL;
101367 +       struct clk *clk = NULL;
101368 +       unsigned long tmp;
101369 +
101370 +       s3c24xx_serial_getclk(&ourport->port, &clksrc, &clk, 115200);
101371 +
101372 +       tmp = __raw_readl(S3C2410_CLKCON);
101373 +
101374 +       /* re-start uart clocks */
101375 +       tmp |= S3C2410_CLKCON_UART0;
101376 +       tmp |= S3C2410_CLKCON_UART1;
101377 +       tmp |= S3C2410_CLKCON_UART2;
101378 +
101379 +       __raw_writel(tmp, S3C2410_CLKCON);
101380 +       udelay(10);
101381 +
101382 +       s3c24xx_serial_setsource(&ourport->port, clksrc);
101383 +
101384 +       if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
101385 +               clk_disable(ourport->baudclk);
101386 +               ourport->baudclk  = NULL;
101387 +       }
101388 +
101389 +       clk_enable(clk);
101390 +
101391 +       ourport->clksrc = clksrc;
101392 +       ourport->baudclk = clk;
101393 +}
101394 +
101395 +static void s3c2410_printascii(const char *sz)
101396 +{
101397 +       struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[
101398 +                                                        CONFIG_DEBUG_S3C_UART];
101399 +       struct uart_port *port = &ourport->port;
101400 +
101401 +       /* 8 N 1 */
101402 +       wr_regl(port, S3C2410_ULCON, (rd_regl(port, S3C2410_ULCON)) | 3);
101403 +       /* polling mode */
101404 +       wr_regl(port, S3C2410_UCON, (rd_regl(port, S3C2410_UCON) & ~0xc0f) | 5);
101405 +       /* disable FIFO */
101406 +       wr_regl(port, S3C2410_UFCON, (rd_regl(port, S3C2410_UFCON) & ~0x01));
101407 +       /* fix baud rate */
101408 +       wr_regl(port, S3C2410_UBRDIV, 26);
101409 +
101410 +       while (*sz) {
101411 +               int timeout = 10000000;
101412 +
101413 +               /* spin on it being busy */
101414 +               while ((!(rd_regl(port, S3C2410_UTRSTAT) & 2)) && timeout--)
101415 +                       ;
101416 +
101417 +               /* transmit register */
101418 +               wr_regl(port, S3C2410_UTXH, *sz);
101419 +
101420 +               sz++;
101421 +       }
101422 +}
101423 +#endif
101424 +
101425  /* s3c24xx_serial_resetport
101426   *
101427   * wrapper to call the specific reset for this port (reset the fifos
101428 @@ -890,6 +1024,93 @@ static inline int s3c24xx_serial_resetpo
101429         return (info->reset_port)(port, cfg);
101430  }
101431
101432 +
101433 +#ifdef CONFIG_CPU_FREQ
101434 +
101435 +static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
101436 +                                            unsigned long val, void *data)
101437 +{
101438 +       struct s3c24xx_uart_port *port;
101439 +       struct uart_port *uport;
101440 +
101441 +       port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
101442 +       uport = &port->port;
101443 +
101444 +       /* check to see if port is enabled */
101445 +
101446 +       if (port->pm_level != 0)
101447 +               return 0;
101448 +
101449 +       /* try and work out if the baudrate is changing, we can detect
101450 +        * a change in rate, but we do not have support for detecting
101451 +        * a disturbance in the clock-rate over the change.
101452 +        */
101453 +
101454 +       if (IS_ERR(port->clk))
101455 +               goto exit;
101456 +
101457 +       if (port->baudclk_rate == clk_get_rate(port->clk))
101458 +               goto exit;
101459 +
101460 +       if (val == CPUFREQ_PRECHANGE) {
101461 +               /* we should really shut the port down whilst the
101462 +                * frequency change is in progress. */
101463 +
101464 +       } else if (val == CPUFREQ_POSTCHANGE) {
101465 +               struct ktermios *termios;
101466 +               struct tty_struct *tty;
101467 +
101468 +               if (uport->info == NULL) {
101469 +                       printk(KERN_WARNING "%s: info NULL\n", __func__);
101470 +                       goto exit;
101471 +               }
101472 +
101473 +               tty = uport->info->port.tty;
101474 +
101475 +               if (tty == NULL) {
101476 +                       printk(KERN_WARNING "%s: tty is NULL\n", __func__);
101477 +                       goto exit;
101478 +               }
101479 +
101480 +               termios = tty->termios;
101481 +
101482 +               if (termios == NULL) {
101483 +                       printk(KERN_WARNING "%s: no termios?\n", __func__);
101484 +                       goto exit;
101485 +               }
101486 +
101487 +               s3c24xx_serial_set_termios(uport, termios, NULL);
101488 +       }
101489 +
101490 + exit:
101491 +       return 0;
101492 +}
101493 +
101494 +static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
101495 +{
101496 +       port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
101497 +
101498 +       return cpufreq_register_notifier(&port->freq_transition,
101499 +                                        CPUFREQ_TRANSITION_NOTIFIER);
101500 +}
101501 +
101502 +static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
101503 +{
101504 +       cpufreq_unregister_notifier(&port->freq_transition,
101505 +                                   CPUFREQ_TRANSITION_NOTIFIER);
101506 +}
101507 +
101508 +#else
101509 +static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
101510 +{
101511 +       return 0;
101512 +}
101513 +
101514 +static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
101515 +{
101516 +}
101517 +#endif
101518 +
101519  /* s3c24xx_serial_init_port
101520   *
101521   * initialise a single serial port from the platform device given
101522 @@ -914,8 +1135,11 @@ static int s3c24xx_serial_init_port(stru
101523         if (port->mapbase != 0)
101524                 return 0;
101525
101526 -       if (cfg->hwport > 3)
101527 -               return -EINVAL;
101528 +       if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
101529 +               printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
101530 +                      cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
101531 +               return -ERANGE;
101532 +       }
101533
101534         /* setup info for port */
101535         port->dev       = &platdev->dev;
101536 @@ -943,18 +1167,26 @@ static int s3c24xx_serial_init_port(stru
101537
101538         dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
101539
101540 -       port->mapbase   = res->start;
101541 -       port->membase   = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
101542 +       port->mapbase = res->start;
101543 +       port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
101544         ret = platform_get_irq(platdev, 0);
101545         if (ret < 0)
101546                 port->irq = 0;
101547 -       else
101548 +       else {
101549                 port->irq = ret;
101550 +               ourport->rx_irq = ret;
101551 +               ourport->tx_irq = ret + 1;
101552 +       }
101553 +
101554 +       ret = platform_get_irq(platdev, 1);
101555 +       if (ret > 0)
101556 +               ourport->tx_irq = ret;
101557
101558         ourport->clk    = clk_get(&platdev->dev, "uart");
101559
101560 -       dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
101561 -           port->mapbase, port->membase, port->irq, port->uartclk);
101562 +       dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
101563 +           port->mapbase, port->membase, port->irq,
101564 +           ourport->rx_irq, ourport->tx_irq, port->uartclk);
101565
101566         /* reset the fifos (and setup the uart) */
101567         s3c24xx_serial_resetport(port, cfg);
101568 @@ -987,6 +1219,7 @@ int s3c24xx_serial_probe(struct platform
101569
101570         ourport = &s3c24xx_serial_ports[probe_index];
101571         probe_index++;
101572 +       init_resume_dependency_list(&ourport->resume_dependency);
101573
101574         dbg("%s: initialising port %p...\n", __func__, ourport);
101575
101576 @@ -1002,6 +1235,10 @@ int s3c24xx_serial_probe(struct platform
101577         if (ret < 0)
101578                 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
101579
101580 +       ret = s3c24xx_serial_cpufreq_register(ourport);
101581 +       if (ret < 0)
101582 +               dev_err(&dev->dev, "failed to add cpufreq notifier\n");
101583 +
101584         return 0;
101585
101586   probe_err:
101587 @@ -1015,6 +1252,7 @@ int s3c24xx_serial_remove(struct platfor
101588         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
101589
101590         if (port) {
101591 +               s3c24xx_serial_cpufreq_deregister(to_ourport(port));
101592                 device_remove_file(&dev->dev, &dev_attr_clock_source);
101593                 uart_remove_one_port(&s3c24xx_uart_drv, port);
101594         }
101595 @@ -1038,6 +1276,16 @@ static int s3c24xx_serial_suspend(struct
101596         return 0;
101597  }
101598
101599 +void s3c24xx_serial_register_resume_dependency(struct resume_dependency *
101600 +                                             resume_dependency, int uart_index)
101601 +{
101602 +       struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[uart_index];
101603 +
101604 +       register_resume_dependency(&ourport->resume_dependency,
101605 +                                                            resume_dependency);
101606 +}
101607 +EXPORT_SYMBOL(s3c24xx_serial_register_resume_dependency);
101608 +
101609  static int s3c24xx_serial_resume(struct platform_device *dev)
101610  {
101611         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
101612 @@ -1049,6 +1297,9 @@ static int s3c24xx_serial_resume(struct
101613                 clk_disable(ourport->clk);
101614
101615                 uart_resume_port(&s3c24xx_uart_drv, port);
101616 +
101617 +               callback_all_resume_dependencies(&ourport->resume_dependency);
101618 +
101619         }
101620
101621         return 0;
101622 @@ -1059,6 +1310,12 @@ int s3c24xx_serial_init(struct platform_
101623                         struct s3c24xx_uart_info *info)
101624  {
101625         dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
101626 +#ifdef CONFIG_MACH_NEO1973_GTA02
101627 +       /* set up the emergency debug UART functions */
101628 +
101629 +       printk_emergency_debug_spew_init = s3c24xx_serial_force_debug_port_up;
101630 +       printk_emergency_debug_spew_send_string = s3c2410_printascii;
101631 +#endif
101632
101633  #ifdef CONFIG_PM
101634         drv->suspend = s3c24xx_serial_suspend;
101635 @@ -1098,6 +1355,13 @@ module_exit(s3c24xx_serial_modexit);
101636  #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
101637
101638  static struct uart_port *cons_uart;
101639 +static int cons_silenced;
101640 +
101641 +void s3c24xx_serial_console_set_silence(int silenced)
101642 +{
101643 +       cons_silenced = silenced;
101644 +}
101645 +EXPORT_SYMBOL(s3c24xx_serial_console_set_silence);
101646
101647  static int
101648  s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
101649 @@ -1122,9 +1386,21 @@ static void
101650  s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
101651  {
101652         unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
101653 +       unsigned int umcon = rd_regl(cons_uart, S3C2410_UMCON);
101654 +
101655 +       if (cons_silenced)
101656 +               return;
101657 +
101658 +       /* If auto HW flow control enabled, temporarily turn it off */
101659 +       if (umcon & S3C2410_UMCOM_AFC)
101660 +               wr_regl(port, S3C2410_UMCON, (umcon & !S3C2410_UMCOM_AFC));
101661 +
101662         while (!s3c24xx_serial_console_txrdy(port, ufcon))
101663                 barrier();
101664         wr_regb(cons_uart, S3C2410_UTXH, ch);
101665 +
101666 +       if (umcon & S3C2410_UMCOM_AFC)
101667 +               wr_regl(port, S3C2410_UMCON, umcon);
101668  }
101669
101670  static void
101671 @@ -1219,7 +1495,7 @@ static int s3c24xx_serial_init_ports(str
101672
101673         platdev_ptr = s3c24xx_uart_devs;
101674
101675 -       for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
101676 +       for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
101677                 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
101678         }
101679
101680 @@ -1240,7 +1516,7 @@ s3c24xx_serial_console_setup(struct cons
101681
101682         /* is this a valid port */
101683
101684 -       if (co->index == -1 || co->index >= NR_PORTS)
101685 +       if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
101686                 co->index = 0;
101687
101688         port = &s3c24xx_serial_ports[co->index].port;
101689 Index: linux-2.6.28/drivers/serial/samsung.h
101690 ===================================================================
101691 --- linux-2.6.28.orig/drivers/serial/samsung.h  2008-12-25 00:26:37.000000000 +0100
101692 +++ linux-2.6.28/drivers/serial/samsung.h       2009-01-02 00:01:56.000000000 +0100
101693 @@ -10,6 +10,8 @@
101694   * published by the Free Software Foundation.
101695  */
101696
101697 +#include <linux/resume-dependency.h>
101698 +
101699  struct s3c24xx_uart_info {
101700         char                    *name;
101701         unsigned int            type;
101702 @@ -21,6 +23,10 @@ struct s3c24xx_uart_info {
101703         unsigned long           tx_fifoshift;
101704         unsigned long           tx_fifofull;
101705
101706 +       /* uart port features */
101707 +
101708 +       unsigned int            has_divslot:1;
101709 +
101710         /* clock source control */
101711
101712         int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
101713 @@ -33,12 +39,23 @@ struct s3c24xx_uart_info {
101714  struct s3c24xx_uart_port {
101715         unsigned char                   rx_claimed;
101716         unsigned char                   tx_claimed;
101717 +       unsigned int                    pm_level;
101718 +       unsigned long                   baudclk_rate;
101719 +
101720 +       unsigned int                    rx_irq;
101721 +       unsigned int                    tx_irq;
101722
101723         struct s3c24xx_uart_info        *info;
101724         struct s3c24xx_uart_clksrc      *clksrc;
101725         struct clk                      *clk;
101726         struct clk                      *baudclk;
101727         struct uart_port                port;
101728 +
101729 +#ifdef CONFIG_CPU_FREQ
101730 +       struct notifier_block           freq_transition;
101731 +#endif
101732 +
101733 +       struct resume_dependency        resume_dependency;
101734  };
101735
101736  /* conversion functions */
101737 Index: linux-2.6.28/drivers/spi/spi_s3c24xx.c
101738 ===================================================================
101739 --- linux-2.6.28.orig/drivers/spi/spi_s3c24xx.c 2008-12-25 00:26:37.000000000 +0100
101740 +++ linux-2.6.28/drivers/spi/spi_s3c24xx.c      2009-01-02 00:01:56.000000000 +0100
101741 @@ -28,7 +28,7 @@
101742  #include <mach/hardware.h>
101743
101744  #include <mach/regs-gpio.h>
101745 -#include <asm/plat-s3c24xx/regs-spi.h>
101746 +#include <plat/regs-spi.h>
101747  #include <mach/spi.h>
101748
101749  struct s3c24xx_spi {
101750 Index: linux-2.6.28/drivers/spi/spi_s3c24xx_gpio.c
101751 ===================================================================
101752 --- linux-2.6.28.orig/drivers/spi/spi_s3c24xx_gpio.c    2008-12-25 00:26:37.000000000 +0100
101753 +++ linux-2.6.28/drivers/spi/spi_s3c24xx_gpio.c 2009-01-02 00:01:56.000000000 +0100
101754 @@ -91,7 +91,7 @@ static void s3c2410_spigpio_chipselect(s
101755         struct s3c2410_spigpio *sg = spidev_to_sg(dev);
101756
101757         if (sg->info && sg->info->chip_select)
101758 -               (sg->info->chip_select)(sg->info, value);
101759 +               (sg->info->chip_select)(sg->info, dev->chip_select, value);
101760  }
101761
101762  static int s3c2410_spigpio_probe(struct platform_device *dev)
101763 @@ -100,6 +100,7 @@ static int s3c2410_spigpio_probe(struct
101764         struct spi_master       *master;
101765         struct s3c2410_spigpio  *sp;
101766         int ret;
101767 +       int i;
101768
101769         master = spi_alloc_master(&dev->dev, sizeof(struct s3c2410_spigpio));
101770         if (master == NULL) {
101771 @@ -112,9 +113,11 @@ static int s3c2410_spigpio_probe(struct
101772
101773         platform_set_drvdata(dev, sp);
101774
101775 -       /* copy in the plkatform data */
101776 +       /* copy in the platform data */
101777         info = sp->info = dev->dev.platform_data;
101778
101779 +       master->num_chipselect = info->num_chipselect;
101780 +
101781         /* setup spi bitbang adaptor */
101782         sp->bitbang.master = spi_master_get(master);
101783         sp->bitbang.master->bus_num = info->bus_num;
101784 @@ -143,6 +146,22 @@ static int s3c2410_spigpio_probe(struct
101785         if (ret)
101786                 goto err_no_bitbang;
101787
101788 +       /* register the chips to go with the board */
101789 +
101790 +       for (i = 0; i < sp->info->board_size; i++) {
101791 +               struct spi_device *spidev;
101792 +
101793 +               dev_info(&dev->dev, "registering %p: %s\n",
101794 +                        &sp->info->board_info[i],
101795 +                        sp->info->board_info[i].modalias);
101796 +
101797 +               sp->info->board_info[i].controller_data = sp;
101798 +               spidev = spi_new_device(master, sp->info->board_info + i);
101799 +               if (spidev)
101800 +                       spidev->max_speed_hz =
101801 +                                         sp->info->board_info[i].max_speed_hz;
101802 +       }
101803 +
101804         return 0;
101805
101806   err_no_bitbang:
101807 Index: linux-2.6.28/drivers/usb/gadget/composite.c
101808 ===================================================================
101809 --- linux-2.6.28.orig/drivers/usb/gadget/composite.c    2008-12-25 00:26:37.000000000 +0100
101810 +++ linux-2.6.28/drivers/usb/gadget/composite.c 2009-01-02 00:01:56.000000000 +0100
101811 @@ -1045,7 +1045,11 @@ composite_resume(struct usb_gadget *gadg
101812  /*-------------------------------------------------------------------------*/
101813
101814  static struct usb_gadget_driver composite_driver = {
101815 +#ifdef CONFIG_USB_GADGET_DUALSPEED
101816         .speed          = USB_SPEED_HIGH,
101817 +#else
101818 +       .speed          = USB_SPEED_FULL,
101819 +#endif
101820
101821         .bind           = composite_bind,
101822         .unbind         = __exit_p(composite_unbind),
101823 Index: linux-2.6.28/drivers/usb/gadget/ether.c
101824 ===================================================================
101825 --- linux-2.6.28.orig/drivers/usb/gadget/ether.c        2008-12-25 00:26:37.000000000 +0100
101826 +++ linux-2.6.28/drivers/usb/gadget/ether.c     2009-01-02 00:01:56.000000000 +0100
101827 @@ -122,11 +122,16 @@ static inline bool has_rndis(void)
101828   * Instead:  allocate your own, using normal USB-IF procedures.
101829   */
101830
101831 +#if 0
101832  /* Thanks to NetChip Technologies for donating this product ID.
101833   * It's for devices with only CDC Ethernet configurations.
101834   */
101835  #define CDC_VENDOR_NUM         0x0525  /* NetChip */
101836  #define CDC_PRODUCT_NUM                0xa4a1  /* Linux-USB Ethernet Gadget */
101837 +#else
101838 +#define CDC_VENDOR_NUM 0x1457          /* First International Computer */
101839 +#define CDC_PRODUCT_NUM        0x5117          /* Linux-USB Ethernet Gadget */
101840 +#endif
101841
101842  /* For hardware that can't talk CDC, we use the same vendor ID that
101843   * ARM Linux has used for ethernet-over-usb, both with sa1100 and
101844 @@ -147,8 +152,8 @@ static inline bool has_rndis(void)
101845   * used with CDC Ethernet, Linux 2.4 hosts will need updates to choose
101846   * the non-RNDIS configuration.
101847   */
101848 -#define RNDIS_VENDOR_NUM       0x0525  /* NetChip */
101849 -#define RNDIS_PRODUCT_NUM      0xa4a2  /* Ethernet/RNDIS Gadget */
101850 +#define RNDIS_VENDOR_NUM       0x1457  /* NetChip */
101851 +#define RNDIS_PRODUCT_NUM      0x5122  /* Ethernet/RNDIS Gadget */
101852
101853  /*-------------------------------------------------------------------------*/
101854
101855 Index: linux-2.6.28/drivers/usb/gadget/s3c2410_udc.c
101856 ===================================================================
101857 --- linux-2.6.28.orig/drivers/usb/gadget/s3c2410_udc.c  2008-12-25 00:26:37.000000000 +0100
101858 +++ linux-2.6.28/drivers/usb/gadget/s3c2410_udc.c       2009-01-02 00:01:56.000000000 +0100
101859 @@ -53,8 +53,8 @@
101860  #include <mach/hardware.h>
101861  #include <mach/regs-gpio.h>
101862
101863 -#include <asm/plat-s3c24xx/regs-udc.h>
101864 -#include <asm/plat-s3c24xx/udc.h>
101865 +#include <plat/regs-udc.h>
101866 +#include <plat/udc.h>
101867
101868
101869  #include "s3c2410_udc.h"
101870 @@ -134,6 +134,8 @@ static int dprintk(int level, const char
101871         return 0;
101872  }
101873  #endif
101874 +
101875 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
101876  static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
101877  {
101878         u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
101879 @@ -197,6 +199,7 @@ static const struct file_operations s3c2
101880         .release        = single_release,
101881         .owner          = THIS_MODULE,
101882  };
101883 +#endif
101884
101885  /* io macros */
101886
101887 @@ -843,6 +846,7 @@ static void s3c2410_udc_handle_ep(struct
101888         u32                     ep_csr1;
101889         u32                     idx;
101890
101891 +handle_ep_again:
101892         if (likely (!list_empty(&ep->queue)))
101893                 req = list_entry(ep->queue.next,
101894                                 struct s3c2410_request, queue);
101895 @@ -882,6 +886,8 @@ static void s3c2410_udc_handle_ep(struct
101896
101897                 if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
101898                         s3c2410_udc_read_fifo(ep,req);
101899 +                       if (s3c2410_udc_fifo_count_out())
101900 +                               goto handle_ep_again;
101901                 }
101902         }
101903  }
101904 @@ -1890,6 +1896,7 @@ static int s3c2410_udc_probe(struct plat
101905                 udc->vbus = 1;
101906         }
101907
101908 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
101909         if (s3c2410_udc_debugfs_root) {
101910                 udc->regs_info = debugfs_create_file("registers", S_IRUGO,
101911                                 s3c2410_udc_debugfs_root,
101912 @@ -1897,6 +1904,7 @@ static int s3c2410_udc_probe(struct plat
101913                 if (!udc->regs_info)
101914                         dev_warn(dev, "debugfs file creation failed\n");
101915         }
101916 +#endif
101917
101918         dev_dbg(dev, "probe ok\n");
101919
101920 @@ -2003,12 +2011,14 @@ static int __init udc_init(void)
101921
101922         dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
101923
101924 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
101925         s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
101926         if (IS_ERR(s3c2410_udc_debugfs_root)) {
101927                 printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
101928                         gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
101929                 s3c2410_udc_debugfs_root = NULL;
101930         }
101931 +#endif
101932
101933         retval = platform_driver_register(&udc_driver_2410);
101934         if (retval)
101935 Index: linux-2.6.28/drivers/usb/host/ohci-s3c2410.c
101936 ===================================================================
101937 --- linux-2.6.28.orig/drivers/usb/host/ohci-s3c2410.c   2008-12-25 00:26:37.000000000 +0100
101938 +++ linux-2.6.28/drivers/usb/host/ohci-s3c2410.c        2009-01-02 00:01:56.000000000 +0100
101939 @@ -24,6 +24,7 @@
101940
101941  #include <mach/hardware.h>
101942  #include <mach/usb-control.h>
101943 +#include <mach/regs-gpio.h>
101944
101945  #define valid_port(idx) ((idx) == 1 || (idx) == 2)
101946
101947 @@ -308,6 +309,42 @@ static void s3c2410_hcd_oc(struct s3c241
101948         local_irq_restore(flags);
101949  }
101950
101951 +/* switching of USB pads */
101952 +static ssize_t show_usb_mode(struct device *dev, struct device_attribute *attr,
101953 +                            char *buf)
101954 +{
101955 +       if (__raw_readl(S3C24XX_MISCCR) & S3C2410_MISCCR_USBHOST)
101956 +               return sprintf(buf, "host\n");
101957 +
101958 +       return sprintf(buf, "device\n");
101959 +}
101960 +
101961 +static ssize_t set_usb_mode(struct device *dev, struct device_attribute *attr,
101962 +                           const char *buf, size_t count)
101963 +{
101964 +       if (!strncmp(buf, "host", 4)) {
101965 +               printk("s3c2410: changing usb to host\n");
101966 +               s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST,
101967 +                                     S3C2410_MISCCR_USBHOST);
101968 +               /* FIXME:
101969 +                * - call machine-specific disable-pullup function i
101970 +                * - enable +Vbus (if hardware supports it)
101971 +                */
101972 +               s3c2410_gpio_setpin(S3C2410_GPB9, 0);
101973 +       } else if (!strncmp(buf, "device", 6)) {
101974 +               printk("s3c2410: changing usb to device\n");
101975 +               s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST, 0);
101976 +               s3c2410_gpio_setpin(S3C2410_GPB9, 1);
101977 +       } else {
101978 +               printk("s3c2410: unknown mode\n");
101979 +               return -EINVAL;
101980 +       }
101981 +
101982 +       return count;
101983 +}
101984 +
101985 +static DEVICE_ATTR(usb_mode, S_IRUGO | S_IWUSR, show_usb_mode, set_usb_mode);
101986 +
101987  /* may be called without controller electrically present */
101988  /* may be called with controller, bus, and devices active */
101989
101990 @@ -325,6 +362,7 @@ static void s3c2410_hcd_oc(struct s3c241
101991  static void
101992  usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev)
101993  {
101994 +       device_remove_file(&dev->dev, &dev_attr_usb_mode);
101995         usb_remove_hcd(hcd);
101996         s3c2410_stop_hc(dev);
101997         iounmap(hcd->regs);
101998 @@ -392,8 +430,15 @@ static int usb_hcd_s3c2410_probe (const
101999         if (retval != 0)
102000                 goto err_ioremap;
102001
102002 +       retval = device_create_file(&dev->dev, &dev_attr_usb_mode);
102003 +       if (retval != 0)
102004 +               goto err_hcd;
102005 +
102006         return 0;
102007
102008 + err_hcd:
102009 +       usb_remove_hcd(hcd);
102010 +
102011   err_ioremap:
102012         s3c2410_stop_hc(dev);
102013         iounmap(hcd->regs);
102014 Index: linux-2.6.28/drivers/video/backlight/gta01_bl.c
102015 ===================================================================
102016 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
102017 +++ linux-2.6.28/drivers/video/backlight/gta01_bl.c     2009-01-02 00:01:56.000000000 +0100
102018 @@ -0,0 +1,269 @@
102019 +/*
102020 + *  Backlight Driver for FIC GTA01 (Neo1973) GSM Phone
102021 + *
102022 + * Copyright (C) 2006-2007 by Openmoko, Inc.
102023 + * Author: Harald Welte <laforge@openmoko.org>
102024 + * All rights reserved.
102025 + *
102026 + *  based on corgi_cl.c, Copyright (c) 2004-2006 Richard Purdie
102027 + *
102028 + * This program is free software; you can redistribute it and/or
102029 + * modify it under the terms of the GNU General Public License as
102030 + * published by the Free Software Foundation, version 2.
102031 + *
102032 + * This program is distributed in the hope that it will be useful,
102033 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
102034 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
102035 + * GNU General Public License for more details.
102036 + *
102037 + * You should have received a copy of the GNU General Public License
102038 + * along with this program; if not, write to the Free Software
102039 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
102040 + * MA 02111-1307 USA
102041 + *
102042 + * Javi Roman <javiroman@kernel-labs.org>:
102043 + *     implement PWM, instead of simple on/off switching
102044 + *
102045 + */
102046 +
102047 +#include <linux/module.h>
102048 +#include <linux/kernel.h>
102049 +#include <linux/init.h>
102050 +#include <linux/platform_device.h>
102051 +#include <linux/mutex.h>
102052 +#include <linux/fb.h>
102053 +#include <linux/backlight.h>
102054 +#include <linux/clk.h>
102055 +
102056 +#include <mach/hardware.h>
102057 +#include <mach/gta01.h>
102058 +#include <mach/pwm.h>
102059 +
102060 +#include <plat/regs-timer.h>
102061 +#include <asm/plat-s3c24xx/neo1973.h>
102062 +
102063 +static struct backlight_properties gta01bl_prop;
102064 +static struct backlight_device *gta01_backlight_device;
102065 +static struct gta01bl_machinfo *bl_machinfo;
102066 +
102067 +static unsigned long gta01bl_flags;
102068 +
102069 +struct gta01bl_data {
102070 +       int intensity;
102071 +       struct mutex mutex;
102072 +       struct clk *clk;
102073 +       struct s3c2410_pwm pwm;
102074 +};
102075 +
102076 +static struct gta01bl_data gta01bl;
102077 +
102078 +static int gta01bl_defer_resume_backlight;
102079 +
102080 +#define GTA01BL_SUSPENDED     0x01
102081 +#define GTA01BL_BATTLOW       0x02
102082 +
102083 +/* On the GTA01 / Neo1973, we use a 50 or 66MHz PCLK, which gives
102084 + * us a 6.25..8.25MHz DIV8 clock, which is further divided by a
102085 + * prescaler of 4, resulting in a 1.56..2.06MHz tick.  This results in a
102086 + * minimum frequency of 24..31Hz.  At 400Hz, we need to set the count
102087 + * to something like 3906..5156, providing us a way sufficient resolution
102088 + * for display brightness adjustment. */
102089 +#define GTA01BL_COUNTER 5156
102090 +
102091 +static int gta01bl_send_intensity(struct backlight_device *bd)
102092 +{
102093 +       int intensity = bd->props.brightness;
102094 +
102095 +       if (bd->props.power != FB_BLANK_UNBLANK)
102096 +               intensity = 0;
102097 +       if (bd->props.fb_blank != FB_BLANK_UNBLANK)
102098 +               intensity = 0;
102099 +       if (gta01bl_flags & GTA01BL_SUSPENDED)
102100 +               intensity = 0;
102101 +       if (gta01bl_flags & GTA01BL_BATTLOW)
102102 +               intensity &= bl_machinfo->limit_mask;
102103 +
102104 +       mutex_lock(&gta01bl.mutex);
102105 +#ifdef GTA01_BACKLIGHT_ONOFF_ONLY
102106 +       if (intensity)
102107 +               neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
102108 +       else
102109 +               neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 0);
102110 +#else
102111 +       if (intensity == bd->props.max_brightness) {
102112 +               neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
102113 +               s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
102114 +       } else  {
102115 +               s3c2410_pwm_duty_cycle(intensity & 0xffff, &gta01bl.pwm);
102116 +               s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPB0_TOUT0);
102117 +       }
102118 +#endif
102119 +       mutex_unlock(&gta01bl.mutex);
102120 +
102121 +       gta01bl.intensity = intensity;
102122 +       return 0;
102123 +}
102124 +
102125 +static int gta01bl_init_hw(void)
102126 +{
102127 +       int rc;
102128 +
102129 +       rc = s3c2410_pwm_init(&gta01bl.pwm);
102130 +       if (rc)
102131 +               return rc;
102132 +
102133 +       gta01bl.pwm.timerid = PWM0;
102134 +       gta01bl.pwm.prescaler = (4 - 1);
102135 +       gta01bl.pwm.divider = S3C2410_TCFG1_MUX0_DIV8;
102136 +       gta01bl.pwm.counter = GTA01BL_COUNTER;
102137 +       gta01bl.pwm.comparer = gta01bl.pwm.counter;
102138 +
102139 +       rc = s3c2410_pwm_enable(&gta01bl.pwm);
102140 +       if (rc)
102141 +               return rc;
102142 +
102143 +       s3c2410_pwm_start(&gta01bl.pwm);
102144 +
102145 +       gta01bl_prop.max_brightness = gta01bl.pwm.counter;
102146 +
102147 +       return 0;
102148 +}
102149 +
102150 +#ifdef CONFIG_PM
102151 +static int gta01bl_suspend(struct platform_device *dev, pm_message_t state)
102152 +{
102153 +       gta01bl_flags |= GTA01BL_SUSPENDED;
102154 +       gta01bl_send_intensity(gta01_backlight_device);
102155 +       neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 0);
102156 +       s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
102157 +       return 0;
102158 +}
102159 +
102160 +void gta01bl_deferred_resume(void)
102161 +{
102162 +       mutex_lock(&gta01bl.mutex);
102163 +       gta01bl_init_hw();
102164 +       mutex_unlock(&gta01bl.mutex);
102165 +
102166 +       gta01bl_flags &= ~GTA01BL_SUSPENDED;
102167 +       gta01bl_send_intensity(gta01_backlight_device);
102168 +}
102169 +EXPORT_SYMBOL_GPL(gta01bl_deferred_resume);
102170 +
102171 +static int gta01bl_resume(struct platform_device *dev)
102172 +{
102173 +       if (!gta01bl_defer_resume_backlight)
102174 +               gta01bl_deferred_resume();
102175 +       return 0;
102176 +}
102177 +#else
102178 +#define gta01bl_suspend        NULL
102179 +#define gta01bl_resume NULL
102180 +#endif
102181 +
102182 +static int gta01bl_get_intensity(struct backlight_device *bd)
102183 +{
102184 +       return gta01bl.intensity;
102185 +}
102186 +
102187 +static int gta01bl_set_intensity(struct backlight_device *bd)
102188 +{
102189 +       gta01bl_send_intensity(gta01_backlight_device);
102190 +       return 0;
102191 +}
102192 +
102193 +/*
102194 + * Called when the battery is low to limit the backlight intensity.
102195 + * If limit==0 clear any limit, otherwise limit the intensity
102196 + */
102197 +void gta01bl_limit_intensity(int limit)
102198 +{
102199 +       if (limit)
102200 +               gta01bl_flags |= GTA01BL_BATTLOW;
102201 +       else
102202 +               gta01bl_flags &= ~GTA01BL_BATTLOW;
102203 +       gta01bl_send_intensity(gta01_backlight_device);
102204 +}
102205 +EXPORT_SYMBOL_GPL(gta01bl_limit_intensity);
102206 +
102207 +
102208 +static struct backlight_ops gta01bl_ops = {
102209 +       .get_brightness = gta01bl_get_intensity,
102210 +       .update_status  = gta01bl_set_intensity,
102211 +};
102212 +
102213 +static int __init gta01bl_probe(struct platform_device *pdev)
102214 +{
102215 +       struct gta01bl_machinfo *machinfo = pdev->dev.platform_data;
102216 +       int rc;
102217 +
102218 +#ifdef GTA01_BACKLIGHT_ONOFF_ONLY
102219 +       s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
102220 +       gta01bl_prop.max_brightness = 1;
102221 +#else
102222 +       rc = gta01bl_init_hw();
102223 +       if (rc < 0)
102224 +               return rc;
102225 +#endif
102226 +       mutex_init(&gta01bl.mutex);
102227 +
102228 +       if (!machinfo->limit_mask)
102229 +               machinfo->limit_mask = -1;
102230 +
102231 +       gta01bl_defer_resume_backlight = machinfo->defer_resume_backlight;
102232 +
102233 +       gta01_backlight_device = backlight_device_register("gta01-bl",
102234 +                                                          &pdev->dev, NULL,
102235 +                                                          &gta01bl_ops);
102236 +       if (IS_ERR(gta01_backlight_device))
102237 +               return PTR_ERR(gta01_backlight_device);
102238 +
102239 +       gta01bl_prop.power = FB_BLANK_UNBLANK;
102240 +       gta01bl_prop.brightness = gta01bl_prop.max_brightness;
102241 +       memcpy(&gta01_backlight_device->props,
102242 +              &gta01bl_prop, sizeof(gta01bl_prop));
102243 +       gta01bl_send_intensity(gta01_backlight_device);
102244 +
102245 +       return 0;
102246 +}
102247 +
102248 +static int gta01bl_remove(struct platform_device *dev)
102249 +{
102250 +#ifndef GTA01_BACKLIGHT_ONOFF_ONLY
102251 +       s3c2410_pwm_disable(&gta01bl.pwm);
102252 +#endif
102253 +       backlight_device_unregister(gta01_backlight_device);
102254 +       mutex_destroy(&gta01bl.mutex);
102255 +
102256 +       s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
102257 +       neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
102258 +
102259 +       return 0;
102260 +}
102261 +
102262 +static struct platform_driver gta01bl_driver = {
102263 +       .probe          = gta01bl_probe,
102264 +       .remove         = gta01bl_remove,
102265 +       .suspend        = gta01bl_suspend,
102266 +       .resume         = gta01bl_resume,
102267 +       .driver         = {
102268 +               .name   = "gta01-bl",
102269 +       },
102270 +};
102271 +
102272 +static int __init gta01bl_init(void)
102273 +{
102274 +       return platform_driver_register(&gta01bl_driver);
102275 +}
102276 +
102277 +static void __exit gta01bl_exit(void)
102278 +{
102279 +       platform_driver_unregister(&gta01bl_driver);
102280 +}
102281 +
102282 +module_init(gta01bl_init);
102283 +module_exit(gta01bl_exit);
102284 +
102285 +MODULE_DESCRIPTION("FIC GTA01 (Neo1973) Backlight Driver");
102286 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
102287 +MODULE_LICENSE("GPL");
102288 Index: linux-2.6.28/drivers/video/backlight/Kconfig
102289 ===================================================================
102290 --- linux-2.6.28.orig/drivers/video/backlight/Kconfig   2008-12-25 00:26:37.000000000 +0100
102291 +++ linux-2.6.28/drivers/video/backlight/Kconfig        2009-01-02 00:01:56.000000000 +0100
102292 @@ -152,6 +152,13 @@ config BACKLIGHT_OMAP1
102293           the PWL module of OMAP1 processors.  Say Y if your board
102294           uses this hardware.
102295
102296 +config BACKLIGHT_GTA01
102297 +       tristate "FIC Neo1973 GTA01 Backlight Driver"
102298 +       depends on BACKLIGHT_CLASS_DEVICE && MACH_NEO1973_GTA01
102299 +       default y
102300 +       help
102301 +         If you have a FIC Neo1973 GTA01, say y to enable the backlight driver.
102302 +
102303  config BACKLIGHT_HP680
102304         tristate "HP Jornada 680 Backlight Driver"
102305         depends on BACKLIGHT_CLASS_DEVICE && SH_HP6XX
102306 Index: linux-2.6.28/drivers/video/backlight/Makefile
102307 ===================================================================
102308 --- linux-2.6.28.orig/drivers/video/backlight/Makefile  2008-12-25 00:26:37.000000000 +0100
102309 +++ linux-2.6.28/drivers/video/backlight/Makefile       2009-01-02 00:01:56.000000000 +0100
102310 @@ -12,6 +12,7 @@ obj-$(CONFIG_LCD_TOSA)                   += tosa_lcd.o
102311  obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
102312  obj-$(CONFIG_BACKLIGHT_ATMEL_PWM)    += atmel-pwm-bl.o
102313  obj-$(CONFIG_BACKLIGHT_CORGI)  += corgi_bl.o
102314 +obj-$(CONFIG_BACKLIGHT_GTA01)  += gta01_bl.o
102315  obj-$(CONFIG_BACKLIGHT_HP680)  += hp680_bl.o
102316  obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
102317  obj-$(CONFIG_BACKLIGHT_OMAP1)  += omap1_bl.o
102318 Index: linux-2.6.28/drivers/video/console/fbcon.c
102319 ===================================================================
102320 --- linux-2.6.28.orig/drivers/video/console/fbcon.c     2008-12-25 00:26:37.000000000 +0100
102321 +++ linux-2.6.28/drivers/video/console/fbcon.c  2009-01-02 00:01:56.000000000 +0100
102322 @@ -401,6 +401,9 @@ static void fb_flashcursor(struct work_s
102323         int c;
102324         int mode;
102325
102326 +       if (info->state != FBINFO_STATE_RUNNING)
102327 +               return;
102328 +
102329         acquire_console_sem();
102330         if (ops && ops->currcon != -1)
102331                 vc = vc_cons[ops->currcon].d;
102332 @@ -3225,13 +3228,17 @@ static void fbcon_get_requirement(struct
102333  static int fbcon_event_notify(struct notifier_block *self,
102334                               unsigned long action, void *data)
102335  {
102336 -       struct fb_event *event = data;
102337 -       struct fb_info *info = event->info;
102338 +       struct fb_event *event;
102339 +       struct fb_info *info;
102340         struct fb_videomode *mode;
102341         struct fb_con2fbmap *con2fb;
102342         struct fb_blit_caps *caps;
102343         int ret = 0;
102344
102345 +       printk(KERN_INFO "fbcon_event_notify action=%ld, data=%p\n", action, data);
102346 +
102347 +       event = data;
102348 +       info = event->info;
102349         /*
102350          * ignore all events except driver registration and deregistration
102351          * if fbcon is not active
102352 Index: linux-2.6.28/drivers/video/display/jbt6k74.c
102353 ===================================================================
102354 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
102355 +++ linux-2.6.28/drivers/video/display/jbt6k74.c        2009-01-02 00:01:56.000000000 +0100
102356 @@ -0,0 +1,809 @@
102357 +/* Linux kernel driver for the tpo JBT6K74-AS LCM ASIC
102358 + *
102359 + * Copyright (C) 2006-2007 by Openmoko, Inc.
102360 + * Author: Harald Welte <laforge@openmoko.org>,
102361 + *        Stefan Schmidt <stefan@openmoko.org>
102362 + * Copyright (C) 2008 by Harald Welte <laforge@openmoko.org>
102363 + * All rights reserved.
102364 + *
102365 + * This program is free software; you can redistribute it and/or
102366 + * modify it under the terms of the GNU General Public License as
102367 + * published by the Free Software Foundation; either version 2 of
102368 + * the License, or (at your option) any later version.
102369 + *
102370 + * This program is distributed in the hope that it will be useful,
102371 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
102372 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
102373 + * GNU General Public License for more details.
102374 + *
102375 + * You should have received a copy of the GNU General Public License
102376 + * along with this program; if not, write to the Free Software
102377 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
102378 + * MA 02111-1307 USA
102379 + *
102380 + */
102381 +
102382 +#include <linux/kernel.h>
102383 +#include <linux/types.h>
102384 +#include <linux/module.h>
102385 +#include <linux/device.h>
102386 +#include <linux/platform_device.h>
102387 +#include <linux/delay.h>
102388 +#include <linux/jbt6k74.h>
102389 +#include <linux/fb.h>
102390 +
102391 +enum jbt_register {
102392 +       JBT_REG_SLEEP_IN                = 0x10,
102393 +       JBT_REG_SLEEP_OUT               = 0x11,
102394 +
102395 +       JBT_REG_DISPLAY_OFF             = 0x28,
102396 +       JBT_REG_DISPLAY_ON              = 0x29,
102397 +
102398 +       JBT_REG_RGB_FORMAT              = 0x3a,
102399 +       JBT_REG_QUAD_RATE               = 0x3b,
102400 +
102401 +       JBT_REG_POWER_ON_OFF            = 0xb0,
102402 +       JBT_REG_BOOSTER_OP              = 0xb1,
102403 +       JBT_REG_BOOSTER_MODE            = 0xb2,
102404 +       JBT_REG_BOOSTER_FREQ            = 0xb3,
102405 +       JBT_REG_OPAMP_SYSCLK            = 0xb4,
102406 +       JBT_REG_VSC_VOLTAGE             = 0xb5,
102407 +       JBT_REG_VCOM_VOLTAGE            = 0xb6,
102408 +       JBT_REG_EXT_DISPL               = 0xb7,
102409 +       JBT_REG_OUTPUT_CONTROL          = 0xb8,
102410 +       JBT_REG_DCCLK_DCEV              = 0xb9,
102411 +       JBT_REG_DISPLAY_MODE1           = 0xba,
102412 +       JBT_REG_DISPLAY_MODE2           = 0xbb,
102413 +       JBT_REG_DISPLAY_MODE            = 0xbc,
102414 +       JBT_REG_ASW_SLEW                = 0xbd,
102415 +       JBT_REG_DUMMY_DISPLAY           = 0xbe,
102416 +       JBT_REG_DRIVE_SYSTEM            = 0xbf,
102417 +
102418 +       JBT_REG_SLEEP_OUT_FR_A          = 0xc0,
102419 +       JBT_REG_SLEEP_OUT_FR_B          = 0xc1,
102420 +       JBT_REG_SLEEP_OUT_FR_C          = 0xc2,
102421 +       JBT_REG_SLEEP_IN_LCCNT_D        = 0xc3,
102422 +       JBT_REG_SLEEP_IN_LCCNT_E        = 0xc4,
102423 +       JBT_REG_SLEEP_IN_LCCNT_F        = 0xc5,
102424 +       JBT_REG_SLEEP_IN_LCCNT_G        = 0xc6,
102425 +
102426 +       JBT_REG_GAMMA1_FINE_1           = 0xc7,
102427 +       JBT_REG_GAMMA1_FINE_2           = 0xc8,
102428 +       JBT_REG_GAMMA1_INCLINATION      = 0xc9,
102429 +       JBT_REG_GAMMA1_BLUE_OFFSET      = 0xca,
102430 +
102431 +       /* VGA */
102432 +       JBT_REG_BLANK_CONTROL           = 0xcf,
102433 +       JBT_REG_BLANK_TH_TV             = 0xd0,
102434 +       JBT_REG_CKV_ON_OFF              = 0xd1,
102435 +       JBT_REG_CKV_1_2                 = 0xd2,
102436 +       JBT_REG_OEV_TIMING              = 0xd3,
102437 +       JBT_REG_ASW_TIMING_1            = 0xd4,
102438 +       JBT_REG_ASW_TIMING_2            = 0xd5,
102439 +
102440 +       /* QVGA */
102441 +       JBT_REG_BLANK_CONTROL_QVGA      = 0xd6,
102442 +       JBT_REG_BLANK_TH_TV_QVGA        = 0xd7,
102443 +       JBT_REG_CKV_ON_OFF_QVGA         = 0xd8,
102444 +       JBT_REG_CKV_1_2_QVGA            = 0xd9,
102445 +       JBT_REG_OEV_TIMING_QVGA         = 0xde,
102446 +       JBT_REG_ASW_TIMING_1_QVGA       = 0xdf,
102447 +       JBT_REG_ASW_TIMING_2_QVGA       = 0xe0,
102448 +
102449 +
102450 +       JBT_REG_HCLOCK_VGA              = 0xec,
102451 +       JBT_REG_HCLOCK_QVGA             = 0xed,
102452 +
102453 +};
102454 +
102455 +enum jbt_state {
102456 +       JBT_STATE_DEEP_STANDBY,
102457 +       JBT_STATE_SLEEP,
102458 +       JBT_STATE_NORMAL,
102459 +       JBT_STATE_QVGA_NORMAL,
102460 +};
102461 +
102462 +static const char *jbt_state_names[] = {
102463 +       [JBT_STATE_DEEP_STANDBY]        = "deep-standby",
102464 +       [JBT_STATE_SLEEP]               = "sleep",
102465 +       [JBT_STATE_NORMAL]              = "normal",
102466 +       [JBT_STATE_QVGA_NORMAL]         = "qvga-normal",
102467 +};
102468 +
102469 +struct jbt_info {
102470 +       enum jbt_state state, last_state;
102471 +       struct spi_device *spi_dev;
102472 +       struct mutex lock;              /* protects tx_buf and reg_cache */
102473 +       struct notifier_block fb_notif;
102474 +       u16 tx_buf[8];
102475 +       u16 reg_cache[0xEE];
102476 +       int have_resumed;
102477 +};
102478 +
102479 +#define JBT_COMMAND    0x000
102480 +#define JBT_DATA       0x100
102481 +
102482 +
102483 +static int jbt_reg_write_nodata(struct jbt_info *jbt, u8 reg)
102484 +{
102485 +       int rc;
102486 +
102487 +       mutex_lock(&jbt->lock);
102488 +
102489 +       jbt->tx_buf[0] = JBT_COMMAND | reg;
102490 +       rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
102491 +                      1*sizeof(u16));
102492 +       if (rc == 0)
102493 +               jbt->reg_cache[reg] = 0;
102494 +       else
102495 +               printk(KERN_ERR"jbt_reg_write_nodata spi_write ret %d\n",
102496 +                      rc);
102497 +
102498 +       mutex_unlock(&jbt->lock);
102499 +
102500 +       return rc;
102501 +}
102502 +
102503 +
102504 +static int jbt_reg_write(struct jbt_info *jbt, u8 reg, u8 data)
102505 +{
102506 +       int rc;
102507 +
102508 +       mutex_lock(&jbt->lock);
102509 +
102510 +       jbt->tx_buf[0] = JBT_COMMAND | reg;
102511 +       jbt->tx_buf[1] = JBT_DATA | data;
102512 +       rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
102513 +                      2*sizeof(u16));
102514 +       if (rc == 0)
102515 +               jbt->reg_cache[reg] = data;
102516 +       else
102517 +               printk(KERN_ERR"jbt_reg_write spi_write ret %d\n", rc);
102518 +
102519 +       mutex_unlock(&jbt->lock);
102520 +
102521 +       return rc;
102522 +}
102523 +
102524 +static int jbt_reg_write16(struct jbt_info *jbt, u8 reg, u16 data)
102525 +{
102526 +       int rc;
102527 +
102528 +       mutex_lock(&jbt->lock);
102529 +
102530 +       jbt->tx_buf[0] = JBT_COMMAND | reg;
102531 +       jbt->tx_buf[1] = JBT_DATA | (data >> 8);
102532 +       jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
102533 +
102534 +       rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
102535 +                      3*sizeof(u16));
102536 +       if (rc == 0)
102537 +               jbt->reg_cache[reg] = data;
102538 +       else
102539 +               printk(KERN_ERR"jbt_reg_write16 spi_write ret %d\n", rc);
102540 +
102541 +       mutex_unlock(&jbt->lock);
102542 +
102543 +       return rc;
102544 +}
102545 +
102546 +static int jbt_init_regs(struct jbt_info *jbt, int qvga)
102547 +{
102548 +       int rc;
102549 +
102550 +       dev_dbg(&jbt->spi_dev->dev, "entering %cVGA mode\n", qvga ? 'Q' : ' ');
102551 +
102552 +       rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
102553 +       rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
102554 +       rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
102555 +       rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
102556 +       rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
102557 +       rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
102558 +       rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
102559 +       rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
102560 +       rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
102561 +       rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
102562 +       rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
102563 +       rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
102564 +       /*
102565 +        * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
102566 +        * to avoid red / blue flicker
102567 +        */
102568 +       rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04);
102569 +       rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
102570 +
102571 +       rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
102572 +       rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
102573 +       rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
102574 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
102575 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
102576 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
102577 +       rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
102578 +
102579 +       rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
102580 +       rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
102581 +       rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
102582 +       rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
102583 +
102584 +       if (!qvga) {
102585 +               rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
102586 +               rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
102587 +               rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
102588 +
102589 +               rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
102590 +               rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
102591 +
102592 +               rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
102593 +               rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
102594 +               rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
102595 +       } else {
102596 +               rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
102597 +               rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL_QVGA, 0x02);
102598 +               rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV_QVGA, 0x0804);
102599 +
102600 +               rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF_QVGA, 0x01);
102601 +               rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2_QVGA, 0x0008);
102602 +
102603 +               rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING_QVGA, 0x050a);
102604 +               rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1_QVGA, 0x0a19);
102605 +               rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2_QVGA, 0x0a);
102606 +       }
102607 +
102608 +       return rc ? -EIO : 0;
102609 +}
102610 +
102611 +static int standby_to_sleep(struct jbt_info *jbt)
102612 +{
102613 +       int rc;
102614 +
102615 +       /* three times command zero */
102616 +       rc = jbt_reg_write_nodata(jbt, 0x00);
102617 +       mdelay(1);
102618 +       rc |= jbt_reg_write_nodata(jbt, 0x00);
102619 +       mdelay(1);
102620 +       rc |= jbt_reg_write_nodata(jbt, 0x00);
102621 +       mdelay(1);
102622 +
102623 +       /* deep standby out */
102624 +       rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);
102625 +
102626 +       return rc ? -EIO : 0;
102627 +}
102628 +
102629 +static int sleep_to_normal(struct jbt_info *jbt)
102630 +{
102631 +       int rc;
102632 +
102633 +       /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
102634 +       rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
102635 +
102636 +       /* Quad mode off */
102637 +       rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
102638 +
102639 +       /* AVDD on, XVDD on */
102640 +       rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
102641 +
102642 +       /* Output control */
102643 +       rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
102644 +
102645 +       /* Sleep mode off */
102646 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
102647 +
102648 +       /* initialize register set */
102649 +       rc |= jbt_init_regs(jbt, 0);
102650 +
102651 +       /* Turn on display */
102652 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
102653 +
102654 +       return rc ? -EIO : 0;
102655 +}
102656 +
102657 +static int sleep_to_qvga_normal(struct jbt_info *jbt)
102658 +{
102659 +       int rc;
102660 +
102661 +       /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
102662 +       rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x81);
102663 +
102664 +       /* Quad mode on */
102665 +       rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x22);
102666 +
102667 +       /* AVDD on, XVDD on */
102668 +       rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
102669 +
102670 +       /* Output control */
102671 +       rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
102672 +
102673 +       /* Sleep mode off */
102674 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
102675 +
102676 +       /* initialize register set for qvga*/
102677 +       rc |= jbt_init_regs(jbt, 1);
102678 +
102679 +       /* Turn on display */
102680 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
102681 +
102682 +       return rc ? -EIO : 0;
102683 +}
102684 +
102685 +static int normal_to_sleep(struct jbt_info *jbt)
102686 +{
102687 +       int rc;
102688 +
102689 +       rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
102690 +       rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
102691 +       rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
102692 +
102693 +       return rc ? -EIO : 0;
102694 +}
102695 +
102696 +static int sleep_to_standby(struct jbt_info *jbt)
102697 +{
102698 +       return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
102699 +}
102700 +
102701 +/* frontend function */
102702 +int jbt6k74_enter_state(struct jbt_info *jbt, enum jbt_state new_state)
102703 +{
102704 +       int rc = -EINVAL;
102705 +
102706 +       dev_dbg(&jbt->spi_dev->dev, "entering (old_state=%u, "
102707 +               "new_state=%u)\n", jbt->state, new_state);
102708 +
102709 +       switch (jbt->state) {
102710 +       case JBT_STATE_DEEP_STANDBY:
102711 +               switch (new_state) {
102712 +               case JBT_STATE_DEEP_STANDBY:
102713 +                       rc = 0;
102714 +                       break;
102715 +               case JBT_STATE_SLEEP:
102716 +                       rc = standby_to_sleep(jbt);
102717 +                       break;
102718 +               case JBT_STATE_NORMAL:
102719 +                       /* first transition into sleep */
102720 +                       rc = standby_to_sleep(jbt);
102721 +                       /* then transition into normal */
102722 +                       rc |= sleep_to_normal(jbt);
102723 +                       break;
102724 +               case JBT_STATE_QVGA_NORMAL:
102725 +                       /* first transition into sleep */
102726 +                       rc = standby_to_sleep(jbt);
102727 +                       /* then transition into normal */
102728 +                       rc |= sleep_to_qvga_normal(jbt);
102729 +                       break;
102730 +               }
102731 +               break;
102732 +       case JBT_STATE_SLEEP:
102733 +               switch (new_state) {
102734 +               case JBT_STATE_SLEEP:
102735 +                       rc = 0;
102736 +                       break;
102737 +               case JBT_STATE_DEEP_STANDBY:
102738 +                       rc = sleep_to_standby(jbt);
102739 +                       break;
102740 +               case JBT_STATE_NORMAL:
102741 +                       rc = sleep_to_normal(jbt);
102742 +                       break;
102743 +               case JBT_STATE_QVGA_NORMAL:
102744 +                       rc = sleep_to_qvga_normal(jbt);
102745 +                       break;
102746 +               }
102747 +               break;
102748 +       case JBT_STATE_NORMAL:
102749 +               switch (new_state) {
102750 +               case JBT_STATE_NORMAL:
102751 +                       rc = 0;
102752 +                       break;
102753 +               case JBT_STATE_DEEP_STANDBY:
102754 +                       /* first transition into sleep */
102755 +                       rc = normal_to_sleep(jbt);
102756 +                       /* then transition into deep standby */
102757 +                       rc |= sleep_to_standby(jbt);
102758 +                       break;
102759 +               case JBT_STATE_SLEEP:
102760 +                       rc = normal_to_sleep(jbt);
102761 +                       break;
102762 +               case JBT_STATE_QVGA_NORMAL:
102763 +                       /* first transition into sleep */
102764 +                       rc = normal_to_sleep(jbt);
102765 +                       /* second transition into deep standby */
102766 +                       rc |= sleep_to_standby(jbt);
102767 +                       /* third transition into sleep */
102768 +                       rc |= standby_to_sleep(jbt);
102769 +                       /* fourth transition into normal */
102770 +                       rc |= sleep_to_qvga_normal(jbt);
102771 +                       break;
102772 +               }
102773 +               break;
102774 +       case JBT_STATE_QVGA_NORMAL:
102775 +               switch (new_state) {
102776 +               case JBT_STATE_QVGA_NORMAL:
102777 +                       rc = 0;
102778 +                       break;
102779 +               case JBT_STATE_DEEP_STANDBY:
102780 +                       /* first transition into sleep */
102781 +                       rc = normal_to_sleep(jbt);
102782 +                       /* then transition into deep standby */
102783 +                       rc |= sleep_to_standby(jbt);
102784 +                       break;
102785 +               case JBT_STATE_SLEEP:
102786 +                       rc = normal_to_sleep(jbt);
102787 +                       break;
102788 +               case JBT_STATE_NORMAL:
102789 +                       /* first transition into sleep */
102790 +                       rc = normal_to_sleep(jbt);
102791 +                       /* second transition into deep standby */
102792 +                       rc |= sleep_to_standby(jbt);
102793 +                       /* third transition into sleep */
102794 +                       rc |= standby_to_sleep(jbt);
102795 +                       /* fourth transition into normal */
102796 +                       rc |= sleep_to_normal(jbt);
102797 +                       break;
102798 +               }
102799 +               break;
102800 +       }
102801 +
102802 +       if (rc == 0)
102803 +               jbt->state = new_state;
102804 +
102805 +       return rc;
102806 +}
102807 +EXPORT_SYMBOL_GPL(jbt6k74_enter_state);
102808 +
102809 +static ssize_t state_read(struct device *dev, struct device_attribute *attr,
102810 +                         char *buf)
102811 +{
102812 +       struct jbt_info *jbt = dev_get_drvdata(dev);
102813 +
102814 +       if (jbt->state >= ARRAY_SIZE(jbt_state_names))
102815 +               return -EIO;
102816 +
102817 +       return sprintf(buf, "%s\n", jbt_state_names[jbt->state]);
102818 +}
102819 +
102820 +static ssize_t state_write(struct device *dev, struct device_attribute *attr,
102821 +                          const char *buf, size_t count)
102822 +{
102823 +       struct jbt_info *jbt = dev_get_drvdata(dev);
102824 +       int i, rc;
102825 +
102826 +       for (i = 0; i < ARRAY_SIZE(jbt_state_names); i++) {
102827 +               if (!strncmp(buf, jbt_state_names[i],
102828 +                            strlen(jbt_state_names[i]))) {
102829 +                       rc = jbt6k74_enter_state(jbt, i);
102830 +                       if (rc)
102831 +                               return rc;
102832 +                       return count;
102833 +               }
102834 +       }
102835 +
102836 +       return -EINVAL;
102837 +}
102838 +
102839 +static DEVICE_ATTR(state, 0644, state_read, state_write);
102840 +
102841 +static int reg_by_string(const char *name)
102842 +{
102843 +       if (!strcmp(name, "gamma_fine1"))
102844 +               return JBT_REG_GAMMA1_FINE_1;
102845 +       else if (!strcmp(name, "gamma_fine2"))
102846 +               return JBT_REG_GAMMA1_FINE_2;
102847 +       else if (!strcmp(name, "gamma_inclination"))
102848 +               return JBT_REG_GAMMA1_INCLINATION;
102849 +       else
102850 +               return JBT_REG_GAMMA1_BLUE_OFFSET;
102851 +}
102852 +
102853 +static ssize_t gamma_read(struct device *dev, struct device_attribute *attr,
102854 +                         char *buf)
102855 +{
102856 +       struct jbt_info *jbt = dev_get_drvdata(dev);
102857 +       int reg = reg_by_string(attr->attr.name);
102858 +       u16 val;
102859 +
102860 +       mutex_lock(&jbt->lock);
102861 +       val = jbt->reg_cache[reg];
102862 +       mutex_unlock(&jbt->lock);
102863 +
102864 +       return sprintf(buf, "0x%04x\n", val);
102865 +}
102866 +
102867 +static ssize_t gamma_write(struct device *dev, struct device_attribute *attr,
102868 +                          const char *buf, size_t count)
102869 +{
102870 +       struct jbt_info *jbt = dev_get_drvdata(dev);
102871 +       int reg = reg_by_string(attr->attr.name);
102872 +       unsigned long val = simple_strtoul(buf, NULL, 10);
102873 +
102874 +       dev_info(dev, "**** jbt6k74 writing gama %lu\n", val & 0xff);
102875 +
102876 +       jbt_reg_write(jbt, reg, val & 0xff);
102877 +
102878 +       return count;
102879 +}
102880 +
102881 +static ssize_t reset_write(struct device *dev, struct device_attribute *attr,
102882 +                          const char *buf, size_t count)
102883 +{
102884 +       struct jbt_info *jbt = dev_get_drvdata(dev);
102885 +       struct jbt6k74_platform_data *jbt6k74_pdata = jbt->spi_dev->dev.platform_data;
102886 +       int rc;
102887 +
102888 +       dev_info(dev, "**** jbt6k74 reset\n");
102889 +
102890 +       /* hard reset the jbt6k74 */
102891 +
102892 +       (jbt6k74_pdata->reset)(0, 0);
102893 +       mdelay(1);
102894 +       (jbt6k74_pdata->reset)(0, 1);
102895 +       mdelay(120);
102896 +
102897 +       rc = jbt_reg_write_nodata(jbt, 0x01);
102898 +       if (rc < 0)
102899 +               dev_err(dev, "cannot soft reset\n");
102900 +
102901 +       mdelay(120);
102902 +
102903 +       jbt->state = JBT_STATE_DEEP_STANDBY;
102904 +
102905 +       switch (jbt->last_state) {
102906 +       case JBT_STATE_QVGA_NORMAL:
102907 +               jbt6k74_enter_state(jbt, JBT_STATE_QVGA_NORMAL);
102908 +               break;
102909 +       default:
102910 +               jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
102911 +               break;
102912 +       }
102913 +
102914 +       return count;
102915 +}
102916 +
102917 +static DEVICE_ATTR(gamma_fine1, 0644, gamma_read, gamma_write);
102918 +static DEVICE_ATTR(gamma_fine2, 0644, gamma_read, gamma_write);
102919 +static DEVICE_ATTR(gamma_inclination, 0644, gamma_read, gamma_write);
102920 +static DEVICE_ATTR(gamma_blue_offset, 0644, gamma_read, gamma_write);
102921 +static DEVICE_ATTR(reset, 0600, NULL, reset_write);
102922 +
102923 +static struct attribute *jbt_sysfs_entries[] = {
102924 +       &dev_attr_state.attr,
102925 +       &dev_attr_gamma_fine1.attr,
102926 +       &dev_attr_gamma_fine2.attr,
102927 +       &dev_attr_gamma_inclination.attr,
102928 +       &dev_attr_gamma_blue_offset.attr,
102929 +       &dev_attr_reset.attr,
102930 +       NULL,
102931 +};
102932 +
102933 +static struct attribute_group jbt_attr_group = {
102934 +       .name   = NULL,
102935 +       .attrs  = jbt_sysfs_entries,
102936 +};
102937 +
102938 +static int fb_notifier_callback(struct notifier_block *self,
102939 +                               unsigned long event, void *data)
102940 +{
102941 +       struct jbt_info *jbt;
102942 +       struct fb_event *evdata = data;
102943 +       int fb_blank;
102944 +
102945 +       if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK)
102946 +               return 0;
102947 +
102948 +       fb_blank = *(int *)evdata->data;
102949 +       jbt = container_of(self, struct jbt_info, fb_notif);
102950 +
102951 +       switch (fb_blank) {
102952 +       case FB_BLANK_UNBLANK:
102953 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 unblank\n");
102954 +               jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
102955 +               break;
102956 +       case FB_BLANK_NORMAL:
102957 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 normal\n");
102958 +               break;
102959 +       case FB_BLANK_VSYNC_SUSPEND:
102960 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 vsync suspend\n");
102961 +               break;
102962 +       case FB_BLANK_HSYNC_SUSPEND:
102963 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 hsync suspend\n");
102964 +               /* FIXME: we disable SLEEP since it would result in
102965 +                * a visible artefact (white screen) before the backlight
102966 +                * is dimmed to a dark enough level */
102967 +               /* jbt6k74_enter_state(jbt, JBT_STATE_SLEEP); */
102968 +               break;
102969 +       case FB_BLANK_POWERDOWN:
102970 +               dev_info(&jbt->spi_dev->dev, "**** jbt6k74 powerdown\n");
102971 +       /* FIXME: deep standby causes WSOD on certain devices. We use
102972 +        * sleep as workaround */
102973 +               jbt6k74_enter_state(jbt, JBT_STATE_SLEEP);
102974 +               break;
102975 +       }
102976 +
102977 +       return 0;
102978 +}
102979 +
102980 +/* linux device model infrastructure */
102981 +
102982 +static int __devinit jbt_probe(struct spi_device *spi)
102983 +{
102984 +       int rc;
102985 +       struct jbt_info *jbt;
102986 +       struct jbt6k74_platform_data *jbt6k74_pdata = spi->dev.platform_data;
102987 +
102988 +       /* the controller doesn't have a MISO pin; we can't do detection */
102989 +
102990 +       spi->mode = SPI_CPOL | SPI_CPHA;
102991 +       spi->bits_per_word = 9;
102992 +
102993 +       rc = spi_setup(spi);
102994 +       if (rc < 0) {
102995 +               dev_err(&spi->dev,
102996 +                       "error during spi_setup of jbt6k74 driver\n");
102997 +               return rc;
102998 +       }
102999 +
103000 +       jbt = kzalloc(sizeof(*jbt), GFP_KERNEL);
103001 +       if (!jbt)
103002 +               return -ENOMEM;
103003 +
103004 +       jbt->spi_dev = spi;
103005 +       jbt->state = JBT_STATE_DEEP_STANDBY;
103006 +       mutex_init(&jbt->lock);
103007 +
103008 +       dev_set_drvdata(&spi->dev, jbt);
103009 +
103010 +       /* hard reset the jbt6k74 */
103011 +
103012 +       (jbt6k74_pdata->reset)(0, 0);
103013 +       mdelay(1);
103014 +       (jbt6k74_pdata->reset)(0, 1);
103015 +       mdelay(120);
103016 +
103017 +       rc = jbt_reg_write_nodata(jbt, 0x01);
103018 +       if (rc < 0)
103019 +               dev_err(&spi->dev, "cannot soft reset\n");
103020 +
103021 +       mdelay(120);
103022 +
103023 +
103024 +       rc = jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
103025 +       if (rc < 0) {
103026 +               dev_err(&spi->dev, "cannot enter NORMAL state\n");
103027 +               goto err_free_drvdata;
103028 +       }
103029 +
103030 +       rc = sysfs_create_group(&spi->dev.kobj, &jbt_attr_group);
103031 +       if (rc < 0) {
103032 +               dev_err(&spi->dev, "cannot create sysfs group\n");
103033 +               goto err_standby;
103034 +       }
103035 +
103036 +       jbt->fb_notif.notifier_call = fb_notifier_callback;
103037 +       rc = fb_register_client(&jbt->fb_notif);
103038 +       if (rc < 0) {
103039 +               dev_err(&spi->dev, "cannot register notifier\n");
103040 +               goto err_sysfs;
103041 +       }
103042 +
103043 +       if (jbt6k74_pdata->probe_completed)
103044 +               jbt6k74_pdata->probe_completed(&spi->dev);
103045 +
103046 +       return 0;
103047 +
103048 +err_sysfs:
103049 +       sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
103050 +err_standby:
103051 +       jbt6k74_enter_state(jbt, JBT_STATE_DEEP_STANDBY);
103052 +err_free_drvdata:
103053 +       dev_set_drvdata(&spi->dev, NULL);
103054 +       kfree(jbt);
103055 +
103056 +       return rc;
103057 +}
103058 +
103059 +static int __devexit jbt_remove(struct spi_device *spi)
103060 +{
103061 +       struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
103062 +
103063 +       /* We don't want to switch off the display in case the user
103064 +        * accidentially onloads the module (whose use count normally is 0) */
103065 +
103066 +       fb_unregister_client(&jbt->fb_notif);
103067 +       sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
103068 +       dev_set_drvdata(&spi->dev, NULL);
103069 +       kfree(jbt);
103070 +
103071 +       return 0;
103072 +}
103073 +
103074 +#ifdef CONFIG_PM
103075 +static int jbt_suspend(struct spi_device *spi, pm_message_t state)
103076 +{
103077 +       struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
103078 +
103079 +       /* Save mode for resume */
103080 +       jbt->last_state = jbt->state;
103081 +       /* FIXME: deep standby causes WSOD on certain devices. We use
103082 +        * sleep as workaround */
103083 +       jbt6k74_enter_state(jbt, JBT_STATE_SLEEP);
103084 +
103085 +       jbt->have_resumed = 0;
103086 +
103087 +       dev_info(&spi->dev, "**** jbt6k74 suspend end\n");
103088 +
103089 +       return 0;
103090 +}
103091 +
103092 +int jbt6k74_resume(struct spi_device *spi)
103093 +{
103094 +       struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
103095 +       struct jbt6k74_platform_data *jbt6k74_pdata = spi->dev.platform_data;
103096 +       int rc;
103097 +
103098 +       dev_info(&spi->dev, "**** jbt6k74 resume start\n");
103099 +
103100 +       /* hard reset the jbt6k74 */
103101 +
103102 +       (jbt6k74_pdata->reset)(0, 0);
103103 +       mdelay(1);
103104 +       (jbt6k74_pdata->reset)(0, 1);
103105 +       mdelay(120);
103106 +
103107 +       rc = jbt_reg_write_nodata(jbt, 0x01);
103108 +       if (rc < 0)
103109 +               dev_err(&spi->dev, "cannot soft reset\n");
103110 +
103111 +       mdelay(120);
103112 +
103113 +       jbt->state = JBT_STATE_DEEP_STANDBY;
103114 +
103115 +       switch (jbt->last_state) {
103116 +       case JBT_STATE_QVGA_NORMAL:
103117 +               jbt6k74_enter_state(jbt, JBT_STATE_QVGA_NORMAL);
103118 +               break;
103119 +       default:
103120 +               jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
103121 +               break;
103122 +       }
103123 +
103124 +       if (jbt6k74_pdata->resuming)
103125 +               (jbt6k74_pdata->resuming)(0);
103126 +
103127 +       dev_info(&spi->dev, "**** jbt6k74 resume end\n");
103128 +
103129 +       return 0;
103130 +}
103131 +EXPORT_SYMBOL_GPL(jbt6k74_resume);
103132 +
103133 +#else
103134 +#define jbt_suspend    NULL
103135 +#define jbt_resume     NULL
103136 +#endif
103137 +
103138 +static struct spi_driver jbt6k74_driver = {
103139 +       .driver = {
103140 +               .name   = "jbt6k74",
103141 +               .owner  = THIS_MODULE,
103142 +       },
103143 +
103144 +       .probe   = jbt_probe,
103145 +       .remove  = __devexit_p(jbt_remove),
103146 +       .suspend = jbt_suspend,
103147 +       .resume  = jbt6k74_resume,
103148 +};
103149 +
103150 +static int __init jbt_init(void)
103151 +{
103152 +       return spi_register_driver(&jbt6k74_driver);
103153 +}
103154 +
103155 +static void __exit jbt_exit(void)
103156 +{
103157 +       spi_unregister_driver(&jbt6k74_driver);
103158 +}
103159 +
103160 +MODULE_DESCRIPTION("SPI driver for tpo JBT6K74-AS LCM control interface");
103161 +MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
103162 +MODULE_LICENSE("GPL");
103163 +
103164 +module_init(jbt_init);
103165 +module_exit(jbt_exit);
103166 Index: linux-2.6.28/drivers/video/display/Kconfig
103167 ===================================================================
103168 --- linux-2.6.28.orig/drivers/video/display/Kconfig     2008-12-25 00:26:37.000000000 +0100
103169 +++ linux-2.6.28/drivers/video/display/Kconfig  2009-01-02 00:01:56.000000000 +0100
103170 @@ -21,4 +21,15 @@ config DISPLAY_SUPPORT
103171  comment "Display hardware drivers"
103172         depends on DISPLAY_SUPPORT
103173
103174 +config DISPLAY_JBT6K74
103175 +       tristate "TPO JBT6K74-AS TFT display ASIC control interface"
103176 +       depends on SPI_MASTER && SYSFS
103177 +       help
103178 +         SPI driver for the control interface of TFT panels containing
103179 +         the TPO JBT6K74-AS controller ASIC, such as the TPO TD028TTEC1
103180 +         TFT diplay module used in the FIC/Openmoko Neo1973 GSM phones.
103181 +
103182 +         The control interface is required for display operation, as it
103183 +         controls power management, display timing and gamma calibration.
103184 +
103185  endmenu
103186 Index: linux-2.6.28/drivers/video/display/Makefile
103187 ===================================================================
103188 --- linux-2.6.28.orig/drivers/video/display/Makefile    2008-12-25 00:26:37.000000000 +0100
103189 +++ linux-2.6.28/drivers/video/display/Makefile 2009-01-02 00:01:56.000000000 +0100
103190 @@ -3,4 +3,5 @@
103191  display-objs                           := display-sysfs.o
103192
103193  obj-$(CONFIG_DISPLAY_SUPPORT)          += display.o
103194 +obj-$(CONFIG_DISPLAY_JBT6K74)          += jbt6k74.o
103195
103196 Index: linux-2.6.28/drivers/video/Kconfig
103197 ===================================================================
103198 --- linux-2.6.28.orig/drivers/video/Kconfig     2008-12-25 00:26:37.000000000 +0100
103199 +++ linux-2.6.28/drivers/video/Kconfig  2009-01-02 00:01:56.000000000 +0100
103200 @@ -1918,6 +1918,30 @@ config FB_TMIO_ACCELL
103201         depends on FB_TMIO
103202         default y
103203
103204 +config FB_S3C
103205 +       tristate "Samsung S3C framebuffer support"
103206 +       depends on FB && ARCH_S3C64XX
103207 +       select FB_CFB_FILLRECT
103208 +       select FB_CFB_COPYAREA
103209 +       select FB_CFB_IMAGEBLIT
103210 +       ---help---
103211 +         Frame buffer driver for the built-in FB controller in the Samsung
103212 +         SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
103213 +         and the S3C64XX series such as the S3C6400 and S3C6410.
103214 +
103215 +         These chips all have the same basic framebuffer design with the
103216 +         actual capabilities depending on the chip. For instance the S3C6400
103217 +         and S3C6410 support 4 hardware windows whereas the S3C24XX series
103218 +         currently only have two.
103219 +
103220 +         Currently the support is only for the S3C6400 and S3C6410 SoCs.
103221 +
103222 +config FB_S3C_DEBUG_REGWRITE
103223 +       bool "Debug register writes"
103224 +       depends on FB_S3C
103225 +       ---help---
103226 +         Show all register writes via printk(KERN_DEBUG)
103227 +
103228  config FB_S3C2410
103229         tristate "S3C2410 LCD framebuffer support"
103230         depends on FB && ARCH_S3C2410
103231 Index: linux-2.6.28/drivers/video/logo/Kconfig
103232 ===================================================================
103233 --- linux-2.6.28.orig/drivers/video/logo/Kconfig        2008-12-25 00:26:37.000000000 +0100
103234 +++ linux-2.6.28/drivers/video/logo/Kconfig     2009-01-02 00:01:56.000000000 +0100
103235 @@ -77,6 +77,11 @@ config LOGO_SUPERH_CLUT224
103236         depends on SUPERH
103237         default y
103238
103239 +config LOGO_OPENMOKO_CLUT224
103240 +       bool "224-color Openmoko Linux logo"
103241 +       depends on MACH_NEO1973_GTA01 || MACH_NEO1973_GTA02
103242 +       default y
103243 +
103244  config LOGO_M32R_CLUT224
103245         bool "224-color M32R Linux logo"
103246         depends on M32R
103247 Index: linux-2.6.28/drivers/video/logo/logo.c
103248 ===================================================================
103249 --- linux-2.6.28.orig/drivers/video/logo/logo.c 2008-12-25 00:26:37.000000000 +0100
103250 +++ linux-2.6.28/drivers/video/logo/logo.c      2009-01-02 00:01:56.000000000 +0100
103251 @@ -35,6 +35,7 @@ extern const struct linux_logo logo_supe
103252  extern const struct linux_logo logo_superh_vga16;
103253  extern const struct linux_logo logo_superh_clut224;
103254  extern const struct linux_logo logo_m32r_clut224;
103255 +extern const struct linux_logo logo_openmoko_clut224;
103256
103257  static int nologo;
103258  module_param(nologo, bool, 0);
103259 @@ -115,6 +116,10 @@ const struct linux_logo * __init_refok f
103260                 /* M32R Linux logo */
103261                 logo = &logo_m32r_clut224;
103262  #endif
103263 +#ifdef CONFIG_LOGO_OPENMOKO_CLUT224
103264 +               /* Openmoko Linux logo */
103265 +               logo = &logo_openmoko_clut224;
103266 +#endif
103267         }
103268         return logo;
103269  }
103270 Index: linux-2.6.28/drivers/video/logo/logo_openmoko_clut224.ppm
103271 ===================================================================
103272 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
103273 +++ linux-2.6.28/drivers/video/logo/logo_openmoko_clut224.ppm   2009-01-02 00:01:57.000000000 +0100
103274 @@ -0,0 +1,40003 @@
103275 +P3
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121470 +1 0 0  4 3 1  5 4 1  7 5 2  7 5 2  11 9 3
121471 +11 9 3  14 11 4  17 13 4  17 13 4  17 13 4  14 11 4
121472 +30 16 4  17 13 4  30 16 4  30 16 4  30 16 4  30 16 4
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121474 +48 30 8  48 30 8  48 30 8  56 33 8  56 33 8  56 33 8
121475 +56 33 8  62 38 11  62 38 11  62 38 11  62 38 11  62 38 11
121476 +75 50 15  75 50 15  75 50 15  75 50 15  75 50 15  75 50 15
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121478 +90 63 20  90 63 20  90 63 20  90 63 20  90 63 20  90 63 20
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121483 +143 92 37  143 92 37  131 88 37  154 97 33  156 118 66  156 118 66
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126434 +104 73 28  104 73 28  104 73 28  104 73 28  104 73 28  104 73 28
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143263 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143264 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143265 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143266 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143267 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143268 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143269 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143270 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143271 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143272 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143273 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143274 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143275 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143276 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143277 +0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0
143278 Index: linux-2.6.28/drivers/video/logo/Makefile
143279 ===================================================================
143280 --- linux-2.6.28.orig/drivers/video/logo/Makefile       2008-12-25 00:26:37.000000000 +0100
143281 +++ linux-2.6.28/drivers/video/logo/Makefile    2009-01-02 00:01:57.000000000 +0100
143282 @@ -15,6 +15,7 @@ obj-$(CONFIG_LOGO_SUPERH_MONO)                += logo_
143283  obj-$(CONFIG_LOGO_SUPERH_VGA16)                += logo_superh_vga16.o
143284  obj-$(CONFIG_LOGO_SUPERH_CLUT224)      += logo_superh_clut224.o
143285  obj-$(CONFIG_LOGO_M32R_CLUT224)                += logo_m32r_clut224.o
143286 +obj-$(CONFIG_LOGO_OPENMOKO_CLUT224)    += logo_openmoko_clut224.o
143287
143288  obj-$(CONFIG_SPU_BASE)                 += logo_spe_clut224.o
143289
143290 Index: linux-2.6.28/drivers/video/Makefile
143291 ===================================================================
143292 --- linux-2.6.28.orig/drivers/video/Makefile    2008-12-25 00:26:37.000000000 +0100
143293 +++ linux-2.6.28/drivers/video/Makefile 2009-01-02 00:01:57.000000000 +0100
143294 @@ -109,6 +109,7 @@ obj-$(CONFIG_FB_METRONOME)        += met
143295  obj-$(CONFIG_FB_S1D13XXX)        += s1d13xxxfb.o
143296  obj-$(CONFIG_FB_SH7760)                  += sh7760fb.o
143297  obj-$(CONFIG_FB_IMX)              += imxfb.o
143298 +obj-$(CONFIG_FB_S3C)             += s3c-fb.o
143299  obj-$(CONFIG_FB_S3C2410)         += s3c2410fb.o
143300  obj-$(CONFIG_FB_FSL_DIU)         += fsl-diu-fb.o
143301  obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o
143302 Index: linux-2.6.28/drivers/video/s3c2410fb.c
143303 ===================================================================
143304 --- linux-2.6.28.orig/drivers/video/s3c2410fb.c 2008-12-25 00:26:37.000000000 +0100
143305 +++ linux-2.6.28/drivers/video/s3c2410fb.c      2009-01-02 00:01:57.000000000 +0100
143306 @@ -1017,6 +1017,8 @@ static int s3c2410fb_resume(struct platf
143307
143308         s3c2410fb_init_registers(fbinfo);
143309
143310 +       s3c2410fb_set_par(fbinfo);
143311 +
143312         return 0;
143313  }
143314
143315 Index: linux-2.6.28/drivers/video/s3c-fb.c
143316 ===================================================================
143317 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
143318 +++ linux-2.6.28/drivers/video/s3c-fb.c 2009-01-02 00:01:57.000000000 +0100
143319 @@ -0,0 +1,1036 @@
143320 +/* linux/drivers/video/s3c-fb.c
143321 + *
143322 + * Copyright 2008 Openmoko Inc.
143323 + * Copyright 2008 Simtec Electronics
143324 + *      Ben Dooks <ben@simtec.co.uk>
143325 + *      http://armlinux.simtec.co.uk/
143326 + *
143327 + * Samsung SoC Framebuffer driver
143328 + *
143329 + * This program is free software; you can redistribute it and/or modify
143330 + * it under the terms of the GNU General Public License version 2 as
143331 + * published by the Free Software Foundation.
143332 +*/
143333 +
143334 +#include <linux/kernel.h>
143335 +#include <linux/module.h>
143336 +#include <linux/platform_device.h>
143337 +#include <linux/dma-mapping.h>
143338 +#include <linux/init.h>
143339 +#include <linux/gfp.h>
143340 +#include <linux/clk.h>
143341 +#include <linux/fb.h>
143342 +#include <linux/io.h>
143343 +
143344 +#include <mach/map.h>
143345 +#include <mach/regs-fb.h>
143346 +#include <plat/fb.h>
143347 +
143348 +/* This driver will export a number of framebuffer interfaces depending
143349 + * on the configuration passed in via the platform data. Each fb instance
143350 + * maps to a hardware window. Currently there is no support for runtime
143351 + * setting of the alpha-blending functions that each window has, so only
143352 + * window 0 is actually useful.
143353 + *
143354 + * Window 0 is treated specially, it is used for the basis of the LCD
143355 + * output timings and as the control for the output power-down state.
143356 +*/
143357 +
143358 +/* note, some of the functions that get called are derived from including
143359 + * <mach/regs-fb.h> as they are specific to the architecture that the code
143360 + * is being built for.
143361 +*/
143362 +
143363 +#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
143364 +#undef writel
143365 +#define writel(v, r) do { \
143366 +       printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
143367 +       __raw_writel(v, r); } while(0)
143368 +#endif /* FB_S3C_DEBUG_REGWRITE */
143369 +
143370 +struct s3c_fb;
143371 +
143372 +/**
143373 + * struct s3c_fb_win - per window private data for each framebuffer.
143374 + * @windata: The platform data supplied for the window configuration.
143375 + * @parent: The hardware that this window is part of.
143376 + * @fbinfo: Pointer pack to the framebuffer info for this window.
143377 + * @palette_buffer: Buffer/cache to hold palette entries.
143378 + * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
143379 + * @index: The window number of this window.
143380 + * @palette: The bitfields for changing r/g/b into a hardware palette entry.
143381 + */
143382 +struct s3c_fb_win {
143383 +       struct s3c_fb_pd_win    *windata;
143384 +       struct s3c_fb           *parent;
143385 +       struct fb_info          *fbinfo;
143386 +       struct s3c_fb_palette    palette;
143387 +
143388 +       u32                     *palette_buffer;
143389 +       u32                      pseudo_palette[16];
143390 +       unsigned int             index;
143391 +};
143392 +
143393 +/**
143394 + * struct s3c_fb - overall hardware state of the hardware
143395 + * @dev: The device that we bound to, for printing, etc.
143396 + * @regs_res: The resource we claimed for the IO registers.
143397 + * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
143398 + * @regs: The mapped hardware registers.
143399 + * @enabled: A bitmask of enabled hardware windows.
143400 + * @pdata: The platform configuration data passed with the device.
143401 + * @windows: The hardware windows that have been claimed.
143402 + */
143403 +struct s3c_fb {
143404 +       struct device           *dev;
143405 +       struct resource         *regs_res;
143406 +       struct clk              *bus_clk;
143407 +       void __iomem            *regs;
143408 +
143409 +       unsigned char            enabled;
143410 +
143411 +       struct s3c_fb_platdata  *pdata;
143412 +       struct s3c_fb_win       *windows[S3C_FB_MAX_WIN];
143413 +};
143414 +
143415 +/**
143416 + * s3c_fb_win_has_palette() - determine if a mode has a palette
143417 + * @win: The window number being queried.
143418 + * @bpp: The number of bits per pixel to test.
143419 + *
143420 + * Work out if the given window supports palletised data at the specified bpp.
143421 + */
143422 +static int s3c_fb_win_has_palette(unsigned int win, unsigned int bpp)
143423 +{
143424 +       return s3c_fb_win_pal_size(win) <= (1 << bpp);
143425 +}
143426 +
143427 +/**
143428 + * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
143429 + * @var: The screen information to verify.
143430 + * @info: The framebuffer device.
143431 + *
143432 + * Framebuffer layer call to verify the given information and allow us to
143433 + * update various information depending on the hardware capabilities.
143434 + */
143435 +static int s3c_fb_check_var(struct fb_var_screeninfo *var,
143436 +                           struct fb_info *info)
143437 +{
143438 +       struct s3c_fb_win *win = info->par;
143439 +       struct s3c_fb_pd_win *windata = win->windata;
143440 +       struct s3c_fb *sfb = win->parent;
143441 +
143442 +       dev_dbg(sfb->dev, "checking parameters\n");
143443 +
143444 +       var->xres_virtual = max((unsigned int)windata->virtual_x, var->xres);
143445 +       var->yres_virtual = max((unsigned int)windata->virtual_y, var->yres);
143446 +
143447 +       if (!s3c_fb_validate_win_bpp(win->index, var->bits_per_pixel)) {
143448 +               dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
143449 +                       win->index, var->bits_per_pixel);
143450 +               return -EINVAL;
143451 +       }
143452 +
143453 +       /* always ensure these are zero, for drop through cases below */
143454 +       var->transp.offset = 0;
143455 +       var->transp.length = 0;
143456 +
143457 +       switch (var->bits_per_pixel) {
143458 +       case 1:
143459 +       case 2:
143460 +       case 4:
143461 +       case 8:
143462 +               if (!s3c_fb_win_has_palette(win->index, var->bits_per_pixel)) {
143463 +                       /* non palletised, A:1,R:2,G:3,B:2 mode */
143464 +                       var->red.offset         = 4;
143465 +                       var->green.offset       = 2;
143466 +                       var->blue.offset        = 0;
143467 +                       var->red.length         = 5;
143468 +                       var->green.length       = 3;
143469 +                       var->blue.length        = 2;
143470 +                       var->transp.offset      = 7;
143471 +                       var->transp.length      = 1;
143472 +               } else {
143473 +                       var->red.offset = 0;
143474 +                       var->red.length = var->bits_per_pixel;
143475 +                       var->green      = var->red;
143476 +                       var->blue       = var->red;
143477 +               }
143478 +               break;
143479 +
143480 +       case 19:
143481 +               /* 666 with one bit alpha/transparency */
143482 +               var->transp.offset      = 18;
143483 +               var->transp.length      = 1;
143484 +       case 18:
143485 +               var->bits_per_pixel     = 32;
143486 +
143487 +               /* 666 format */
143488 +               var->red.offset         = 12;
143489 +               var->green.offset       = 6;
143490 +               var->blue.offset        = 0;
143491 +               var->red.length         = 6;
143492 +               var->green.length       = 6;
143493 +               var->blue.length        = 6;
143494 +               break;
143495 +
143496 +       case 16:
143497 +               /* 16 bpp, 565 format */
143498 +               var->red.offset         = 11;
143499 +               var->green.offset       = 5;
143500 +               var->blue.offset        = 0;
143501 +               var->red.length         = 5;
143502 +               var->green.length       = 6;
143503 +               var->blue.length        = 5;
143504 +               break;
143505 +
143506 +       case 28:
143507 +       case 25:
143508 +               var->transp.length      = var->bits_per_pixel - 24;
143509 +               var->transp.offset      = 24;
143510 +               /* drop through */
143511 +       case 24:
143512 +               /* our 24bpp is unpacked, so 32bpp */
143513 +               var->bits_per_pixel     = 32;
143514 +       case 32:
143515 +               var->red.offset         = 16;
143516 +               var->red.length         = 8;
143517 +               var->green.offset       = 8;
143518 +               var->green.length       = 8;
143519 +               var->blue.offset        = 0;
143520 +               var->blue.length        = 8;
143521 +               break;
143522 +
143523 +       default:
143524 +               dev_err(sfb->dev, "invalid bpp\n");
143525 +       }
143526 +
143527 +       dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
143528 +       return 0;
143529 +}
143530 +
143531 +/**
143532 + * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
143533 + * @sfb: The hardware state.
143534 + * @pixclock: The pixel clock wanted, in picoseconds.
143535 + *
143536 + * Given the specified pixel clock, work out the necessary divider to get
143537 + * close to the output frequency.
143538 + */
143539 +static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
143540 +{
143541 +       unsigned long clk = clk_get_rate(sfb->bus_clk);
143542 +       unsigned long long tmp;
143543 +       unsigned int result;
143544 +
143545 +       tmp = (unsigned long long)clk;
143546 +       tmp *= pixclk;
143547 +
143548 +       do_div(tmp, 1000000000UL);
143549 +       result = (unsigned int)tmp / 1000;
143550 +
143551 +       dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
143552 +               pixclk, clk, result, clk / result);
143553 +
143554 +       return result;
143555 +}
143556 +
143557 +/**
143558 + * s3c_fb_align_word() - align pixel count to word boundary
143559 + * @bpp: The number of bits per pixel
143560 + * @pix: The value to be aligned.
143561 + *
143562 + * Align the given pixel count so that it will start on an 32bit word
143563 + * boundary.
143564 + */
143565 +static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
143566 +{
143567 +       int pix_per_word;
143568 +
143569 +       if (bpp > 16)
143570 +               return pix;
143571 +
143572 +       pix_per_word = (8 * 32) / bpp;
143573 +       return ALIGN(pix, pix_per_word);
143574 +}
143575 +
143576 +/**
143577 + * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
143578 + * @info: The framebuffer to change.
143579 + *
143580 + * Framebuffer layer request to set a new mode for the specified framebuffer
143581 + */
143582 +static int s3c_fb_set_par(struct fb_info *info)
143583 +{
143584 +       struct fb_var_screeninfo *var = &info->var;
143585 +       struct s3c_fb_win *win = info->par;
143586 +       struct s3c_fb *sfb = win->parent;
143587 +       void __iomem *regs = sfb->regs;
143588 +       int win_no = win->index;
143589 +       u32 data;
143590 +       u32 pagewidth;
143591 +       int clkdiv;
143592 +
143593 +       dev_dbg(sfb->dev, "setting framebuffer parameters\n");
143594 +
143595 +       switch (var->bits_per_pixel) {
143596 +       case 32:
143597 +       case 24:
143598 +       case 16:
143599 +       case 12:
143600 +               info->fix.visual = FB_VISUAL_TRUECOLOR;
143601 +               break;
143602 +       case 8:
143603 +               if (s3c_fb_win_has_palette(win_no, 8))
143604 +                       info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
143605 +               else
143606 +                       info->fix.visual = FB_VISUAL_TRUECOLOR;
143607 +               break;
143608 +       case 1:
143609 +               info->fix.visual = FB_VISUAL_MONO01;
143610 +               break;
143611 +       default:
143612 +               info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
143613 +               break;
143614 +       }
143615 +
143616 +       info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
143617 +
143618 +       /* disable the window whilst we update it */
143619 +       writel(0, regs + WINCON(win_no));
143620 +
143621 +       /* use window 0 as the basis for the lcd output timings */
143622 +
143623 +       if (win_no == 0) {
143624 +               clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
143625 +
143626 +               data = sfb->pdata->vidcon0;
143627 +               data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
143628 +
143629 +               if (clkdiv > 1)
143630 +                       data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
143631 +               else
143632 +                       data &= ~VIDCON0_CLKDIR;        /* 1:1 clock */
143633 +
143634 +               /* write the timing data to the panel */
143635 +
143636 +               data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
143637 +               writel(data, regs + VIDCON0);
143638 +
143639 +               data = VIDTCON0_VBPD(var->upper_margin - 1) |
143640 +                      VIDTCON0_VFPD(var->lower_margin - 1) |
143641 +                      VIDTCON0_VSPW(var->vsync_len - 1);
143642 +
143643 +               writel(data, regs + VIDTCON0);
143644 +
143645 +               data = VIDTCON1_HBPD(var->left_margin - 1) |
143646 +                      VIDTCON1_HFPD(var->right_margin - 1) |
143647 +                      VIDTCON1_HSPW(var->hsync_len - 1);
143648 +
143649 +               writel(data, regs + VIDTCON1);
143650 +
143651 +               data = VIDTCON2_LINEVAL(var->yres - 1) |
143652 +                      VIDTCON2_HOZVAL(var->xres - 1);
143653 +               writel(data, regs + VIDTCON2);
143654 +       }
143655 +
143656 +       /* write the buffer address */
143657 +
143658 +       writel(info->fix.smem_start, regs + VIDW_BUF_START(win_no));
143659 +
143660 +       data = info->fix.smem_start + info->fix.line_length * var->yres;
143661 +       writel(data, regs + VIDW_BUF_END(win_no));
143662 +
143663 +       pagewidth = (var->xres * var->bits_per_pixel) >> 3;
143664 +       data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
143665 +              VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
143666 +       writel(data, regs + VIDW_BUF_SIZE(win_no));
143667 +
143668 +       /* write 'OSD' registers to control position of framebuffer */
143669 +
143670 +       data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
143671 +       writel(data, regs + VIDOSD_A(win_no));
143672 +
143673 +       data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
143674 +                                                    var->xres - 1)) |
143675 +              VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
143676 +
143677 +       writel(data, regs + VIDOSD_B(win_no));
143678 +
143679 +       data = var->xres * var->yres;
143680 +       if (s3c_fb_has_osd_d(win_no)) {
143681 +               writel(data, regs + VIDOSD_D(win_no));
143682 +               writel(0, regs + VIDOSD_C(win_no));
143683 +       } else
143684 +               writel(data, regs + VIDOSD_C(win_no));
143685 +
143686 +       data = WINCONx_ENWIN;
143687 +
143688 +       /* note, since we have to round up the bits-per-pixel, we end up
143689 +        * relying on the bitfield information for r/g/b/a to work out
143690 +        * exactly which mode of operation is intended. */
143691 +
143692 +       switch (var->bits_per_pixel) {
143693 +       case 1:
143694 +               data |= WINCON0_BPPMODE_1BPP;
143695 +               data |= WINCONx_BITSWP;
143696 +               data |= WINCONx_BURSTLEN_4WORD;
143697 +               break;
143698 +       case 2:
143699 +               data |= WINCON0_BPPMODE_2BPP;
143700 +               data |= WINCONx_BITSWP;
143701 +               data |= WINCONx_BURSTLEN_8WORD;
143702 +               break;
143703 +       case 4:
143704 +               data |= WINCON0_BPPMODE_4BPP;
143705 +               data |= WINCONx_BITSWP;
143706 +               data |= WINCONx_BURSTLEN_8WORD;
143707 +               break;
143708 +       case 8:
143709 +               if (var->transp.length != 0)
143710 +                       data |= WINCON1_BPPMODE_8BPP_1232;
143711 +               else
143712 +                       data |= WINCON0_BPPMODE_8BPP_PALETTE;
143713 +               data |= WINCONx_BURSTLEN_8WORD;
143714 +               data |= WINCONx_BYTSWP;
143715 +               break;
143716 +       case 16:
143717 +               if (var->transp.length != 0)
143718 +                       data |= WINCON1_BPPMODE_16BPP_A1555;
143719 +               else
143720 +                       data |= WINCON0_BPPMODE_16BPP_565;
143721 +               data |= WINCONx_HAWSWP;
143722 +               data |= WINCONx_BURSTLEN_16WORD;
143723 +               break;
143724 +       case 24:
143725 +       case 32:
143726 +               if (var->red.length == 6) {
143727 +                       if (var->transp.length != 0)
143728 +                               data |= WINCON1_BPPMODE_19BPP_A1666;
143729 +                       else
143730 +                               data |= WINCON1_BPPMODE_18BPP_666;
143731 +               } else if (var->transp.length != 0)
143732 +                       data |= WINCON1_BPPMODE_25BPP_A1888;
143733 +               else
143734 +                       data |= WINCON0_BPPMODE_24BPP_888;
143735 +
143736 +               data |= WINCONx_BURSTLEN_16WORD;
143737 +               break;
143738 +       }
143739 +
143740 +       writel(data, regs + WINCON(win_no));
143741 +       writel(0x0, regs + WINxMAP(win_no));
143742 +
143743 +       return 0;
143744 +}
143745 +
143746 +/**
143747 + * s3c_fb_update_palette() - set or schedule a palette update.
143748 + * @sfb: The hardware information.
143749 + * @win: The window being updated.
143750 + * @reg: The palette index being changed.
143751 + * @value: The computed palette value.
143752 + *
143753 + * Change the value of a palette register, either by directly writing to
143754 + * the palette (this requires the palette RAM to be disconnected from the
143755 + * hardware whilst this is in progress) or schedule the update for later.
143756 + *
143757 + * At the moment, since we have no VSYNC interrupt support, we simply set
143758 + * the palette entry directly.
143759 + */
143760 +static void s3c_fb_update_palette(struct s3c_fb *sfb,
143761 +                                 struct s3c_fb_win *win,
143762 +                                 unsigned int reg,
143763 +                                 u32 value)
143764 +{
143765 +       void __iomem *palreg;
143766 +       u32 palcon;
143767 +
143768 +       palreg = sfb->regs + s3c_fb_pal_reg(win->index, reg);
143769 +
143770 +       dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
143771 +               __func__, win->index, reg, palreg, value);
143772 +
143773 +       win->palette_buffer[reg] = value;
143774 +
143775 +       palcon = readl(sfb->regs + WPALCON);
143776 +       writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
143777 +
143778 +       if (s3c_fb_pal_is16(win->index))
143779 +               writew(value, palreg);
143780 +       else
143781 +               writel(value, palreg);
143782 +
143783 +       writel(palcon, sfb->regs + WPALCON);
143784 +}
143785 +
143786 +static inline unsigned int chan_to_field(unsigned int chan,
143787 +                                        struct fb_bitfield *bf)
143788 +{
143789 +       chan &= 0xffff;
143790 +       chan >>= 16 - bf->length;
143791 +       return chan << bf->offset;
143792 +}
143793 +
143794 +/**
143795 + * s3c_fb_setcolreg() - framebuffer layer request to change palette.
143796 + * @regno: The palette index to change.
143797 + * @red: The red field for the palette data.
143798 + * @green: The green field for the palette data.
143799 + * @blue: The blue field for the palette data.
143800 + * @trans: The transparency (alpha) field for the palette data.
143801 + * @info: The framebuffer being changed.
143802 + */
143803 +static int s3c_fb_setcolreg(unsigned regno,
143804 +                           unsigned red, unsigned green, unsigned blue,
143805 +                           unsigned transp, struct fb_info *info)
143806 +{
143807 +       struct s3c_fb_win *win = info->par;
143808 +       struct s3c_fb *sfb = win->parent;
143809 +       unsigned int val;
143810 +
143811 +       dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
143812 +               __func__, win->index, regno, red, green, blue);
143813 +
143814 +       switch (info->fix.visual) {
143815 +       case FB_VISUAL_TRUECOLOR:
143816 +               /* true-colour, use pseudo-palette */
143817 +
143818 +               if (regno < 16) {
143819 +                       u32 *pal = info->pseudo_palette;
143820 +
143821 +                       val  = chan_to_field(red,   &info->var.red);
143822 +                       val |= chan_to_field(green, &info->var.green);
143823 +                       val |= chan_to_field(blue,  &info->var.blue);
143824 +
143825 +                       pal[regno] = val;
143826 +               }
143827 +               break;
143828 +
143829 +       case FB_VISUAL_PSEUDOCOLOR:
143830 +               if (regno < s3c_fb_win_pal_size(win->index)) {
143831 +                       val  = chan_to_field(red, &win->palette.r);
143832 +                       val |= chan_to_field(green, &win->palette.g);
143833 +                       val |= chan_to_field(blue, &win->palette.b);
143834 +
143835 +                       s3c_fb_update_palette(sfb, win, regno, val);
143836 +               }
143837 +
143838 +               break;
143839 +
143840 +       default:
143841 +               return 1;       /* unknown type */
143842 +       }
143843 +
143844 +       return 0;
143845 +}
143846 +
143847 +/**
143848 + * s3c_fb_enable() - Set the state of the main LCD output
143849 + * @sfb: The main framebuffer state.
143850 + * @enable: The state to set.
143851 + */
143852 +static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
143853 +{
143854 +       u32 vidcon0 = readl(sfb->regs + VIDCON0);
143855 +
143856 +       if (enable)
143857 +               vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
143858 +       else {
143859 +               /* see the note in the framebuffer datasheet about
143860 +                * why you cannot take both of these bits down at the
143861 +                * same time. */
143862 +
143863 +               if (!(vidcon0 & VIDCON0_ENVID))
143864 +                       return;
143865 +
143866 +               vidcon0 |= VIDCON0_ENVID;
143867 +               vidcon0 &= ~VIDCON0_ENVID_F;
143868 +       }
143869 +
143870 +       writel(vidcon0, sfb->regs + VIDCON0);
143871 +}
143872 +
143873 +/**
143874 + * s3c_fb_blank() - blank or unblank the given window
143875 + * @blank_mode: The blank state from FB_BLANK_*
143876 + * @info: The framebuffer to blank.
143877 + *
143878 + * Framebuffer layer request to change the power state.
143879 + */
143880 +static int s3c_fb_blank(int blank_mode, struct fb_info *info)
143881 +{
143882 +       struct s3c_fb_win *win = info->par;
143883 +       struct s3c_fb *sfb = win->parent;
143884 +       unsigned int index = win->index;
143885 +       u32 wincon;
143886 +
143887 +       dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
143888 +
143889 +       wincon = readl(sfb->regs + WINCON(index));
143890 +
143891 +       switch (blank_mode) {
143892 +       case FB_BLANK_POWERDOWN:
143893 +               wincon &= ~WINCONx_ENWIN;
143894 +               sfb->enabled &= ~(1 << index);
143895 +               /* fall through to FB_BLANK_NORMAL */
143896 +
143897 +       case FB_BLANK_NORMAL:
143898 +               /* disable the DMA and display 0x0 (black) */
143899 +               writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
143900 +                      sfb->regs + WINxMAP(index));
143901 +               break;
143902 +
143903 +       case FB_BLANK_UNBLANK:
143904 +               writel(0x0, sfb->regs + WINxMAP(index));
143905 +               wincon |= WINCONx_ENWIN;
143906 +               sfb->enabled |= (1 << index);
143907 +               break;
143908 +
143909 +       case FB_BLANK_VSYNC_SUSPEND:
143910 +       case FB_BLANK_HSYNC_SUSPEND:
143911 +       default:
143912 +               return 1;
143913 +       }
143914 +
143915 +       writel(wincon, sfb->regs + WINCON(index));
143916 +
143917 +       /* Check the enabled state to see if we need to be running the
143918 +        * main LCD interface, as if there are no active windows then
143919 +        * it is highly likely that we also do not need to output
143920 +        * anything.
143921 +        */
143922 +
143923 +       /* We could do something like the following code, but the current
143924 +        * system of using framebuffer events means that we cannot make
143925 +        * the distinction between just window 0 being inactive and all
143926 +        * the windows being down.
143927 +        *
143928 +        * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
143929 +       */
143930 +
143931 +       /* we're stuck with this until we can do something about overriding
143932 +        * the power control using the blanking event for a single fb.
143933 +        */
143934 +       if (index == 0)
143935 +               s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
143936 +
143937 +       return 0;
143938 +}
143939 +
143940 +static struct fb_ops s3c_fb_ops = {
143941 +       .owner          = THIS_MODULE,
143942 +       .fb_check_var   = s3c_fb_check_var,
143943 +       .fb_set_par     = s3c_fb_set_par,
143944 +       .fb_blank       = s3c_fb_blank,
143945 +       .fb_setcolreg   = s3c_fb_setcolreg,
143946 +       .fb_fillrect    = cfb_fillrect,
143947 +       .fb_copyarea    = cfb_copyarea,
143948 +       .fb_imageblit   = cfb_imageblit,
143949 +};
143950 +
143951 +/**
143952 + * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
143953 + * @sfb: The base resources for the hardware.
143954 + * @win: The window to initialise memory for.
143955 + *
143956 + * Allocate memory for the given framebuffer.
143957 + */
143958 +static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
143959 +                                        struct s3c_fb_win *win)
143960 +{
143961 +       struct s3c_fb_pd_win *windata = win->windata;
143962 +       unsigned int real_size, virt_size, size;
143963 +       struct fb_info *fbi = win->fbinfo;
143964 +       dma_addr_t map_dma;
143965 +
143966 +       dev_dbg(sfb->dev, "allocating memory for display\n");
143967 +
143968 +       real_size = windata->win_mode.xres * windata->win_mode.yres;
143969 +       virt_size = windata->virtual_x * windata->virtual_y;
143970 +
143971 +       dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
143972 +               real_size, windata->win_mode.xres, windata->win_mode.yres,
143973 +               virt_size, windata->virtual_x, windata->virtual_y);
143974 +
143975 +       size = (real_size > virt_size) ? real_size : virt_size;
143976 +       size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
143977 +       size /= 8;
143978 +
143979 +       fbi->fix.smem_len = size;
143980 +       size = PAGE_ALIGN(size);
143981 +
143982 +       dev_dbg(sfb->dev, "want %u bytes for window\n", size);
143983 +
143984 +       fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
143985 +                                                 &map_dma, GFP_KERNEL);
143986 +       if (!fbi->screen_base)
143987 +               return -ENOMEM;
143988 +
143989 +       dev_dbg(sfb->dev, "mapped %x to %p\n",
143990 +               (unsigned int)map_dma, fbi->screen_base);
143991 +
143992 +       memset(fbi->screen_base, 0x0, size);
143993 +       fbi->fix.smem_start = map_dma;
143994 +
143995 +       return 0;
143996 +}
143997 +
143998 +/**
143999 + * s3c_fb_free_memory() - free the display memory for the given window
144000 + * @sfb: The base resources for the hardware.
144001 + * @win: The window to free the display memory for.
144002 + *
144003 + * Free the display memory allocated by s3c_fb_alloc_memory().
144004 + */
144005 +static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
144006 +{
144007 +       struct fb_info *fbi = win->fbinfo;
144008 +
144009 +       dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
144010 +                             fbi->screen_base, fbi->fix.smem_start);
144011 +}
144012 +
144013 +/**
144014 + * s3c_fb_release_win() - release resources for a framebuffer window.
144015 + * @win: The window to cleanup the resources for.
144016 + *
144017 + * Release the resources that where claimed for the hardware window,
144018 + * such as the framebuffer instance and any memory claimed for it.
144019 + */
144020 +static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
144021 +{
144022 +       fb_dealloc_cmap(&win->fbinfo->cmap);
144023 +       unregister_framebuffer(win->fbinfo);
144024 +       s3c_fb_free_memory(sfb, win);
144025 +}
144026 +
144027 +/**
144028 + * s3c_fb_probe_win() - register an hardware window
144029 + * @sfb: The base resources for the hardware
144030 + * @res: Pointer to where to place the resultant window.
144031 + *
144032 + * Allocate and do the basic initialisation for one of the hardware's graphics
144033 + * windows.
144034 + */
144035 +static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
144036 +                                     struct s3c_fb_win **res)
144037 +{
144038 +       struct fb_var_screeninfo *var;
144039 +       struct fb_videomode *initmode;
144040 +       struct s3c_fb_pd_win *windata;
144041 +       struct s3c_fb_win *win;
144042 +       struct fb_info *fbinfo;
144043 +       int palette_size;
144044 +       int ret;
144045 +
144046 +       dev_dbg(sfb->dev, "probing window %d\n", win_no);
144047 +
144048 +       palette_size = s3c_fb_win_pal_size(win_no);
144049 +
144050 +       fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
144051 +                                  palette_size * sizeof(u32), sfb->dev);
144052 +       if (!fbinfo) {
144053 +               dev_err(sfb->dev, "failed to allocate framebuffer\n");
144054 +               return -ENOENT;
144055 +       }
144056 +
144057 +       windata = sfb->pdata->win[win_no];
144058 +       initmode = &windata->win_mode;
144059 +
144060 +       WARN_ON(windata->max_bpp == 0);
144061 +       WARN_ON(windata->win_mode.xres == 0);
144062 +       WARN_ON(windata->win_mode.yres == 0);
144063 +
144064 +       win = fbinfo->par;
144065 +       var = &fbinfo->var;
144066 +       win->fbinfo = fbinfo;
144067 +       win->parent = sfb;
144068 +       win->windata = windata;
144069 +       win->index = win_no;
144070 +       win->palette_buffer = (u32 *)(win + 1);
144071 +
144072 +       ret = s3c_fb_alloc_memory(sfb, win);
144073 +       if (ret) {
144074 +               dev_err(sfb->dev, "failed to allocate display memory\n");
144075 +               goto err_framebuffer;
144076 +       }
144077 +
144078 +       /* setup the r/b/g positions for the window's palette */
144079 +       s3c_fb_init_palette(win_no, &win->palette);
144080 +
144081 +       /* setup the initial video mode from the window */
144082 +       fb_videomode_to_var(&fbinfo->var, initmode);
144083 +
144084 +       fbinfo->fix.type        = FB_TYPE_PACKED_PIXELS;
144085 +       fbinfo->fix.accel       = FB_ACCEL_NONE;
144086 +       fbinfo->var.activate    = FB_ACTIVATE_NOW;
144087 +       fbinfo->var.vmode       = FB_VMODE_NONINTERLACED;
144088 +       fbinfo->var.bits_per_pixel = windata->default_bpp;
144089 +       fbinfo->fbops           = &s3c_fb_ops;
144090 +       fbinfo->flags           = FBINFO_FLAG_DEFAULT;
144091 +       fbinfo->pseudo_palette  = &win->pseudo_palette;
144092 +
144093 +       /* prepare to actually start the framebuffer */
144094 +
144095 +       ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
144096 +       if (ret < 0) {
144097 +               dev_err(sfb->dev, "check_var failed on initial video params\n");
144098 +               goto err_alloc_mem;
144099 +       }
144100 +
144101 +       /* create initial colour map */
144102 +
144103 +       ret = fb_alloc_cmap(&fbinfo->cmap, s3c_fb_win_pal_size(win_no), 1);
144104 +       if (ret == 0)
144105 +               fb_set_cmap(&fbinfo->cmap, fbinfo);
144106 +       else
144107 +               dev_err(sfb->dev, "failed to allocate fb cmap\n");
144108 +
144109 +       s3c_fb_set_par(fbinfo);
144110 +
144111 +       dev_dbg(sfb->dev, "about to register framebuffer\n");
144112 +
144113 +       /* run the check_var and set_par on our configuration. */
144114 +
144115 +       ret = register_framebuffer(fbinfo);
144116 +       if (ret < 0) {
144117 +               dev_err(sfb->dev, "failed to register framebuffer\n");
144118 +               goto err_alloc_mem;
144119 +       }
144120 +
144121 +       *res = win;
144122 +       dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
144123 +
144124 +       return 0;
144125 +
144126 +err_alloc_mem:
144127 +       s3c_fb_free_memory(sfb, win);
144128 +
144129 +err_framebuffer:
144130 +       unregister_framebuffer(fbinfo);
144131 +       return ret;
144132 +}
144133 +
144134 +/**
144135 + * s3c_fb_clear_win() - clear hardware window registers.
144136 + * @sfb: The base resources for the hardware.
144137 + * @win: The window to process.
144138 + *
144139 + * Reset the specific window registers to a known state.
144140 + */
144141 +static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
144142 +{
144143 +       void __iomem *regs = sfb->regs;
144144 +
144145 +       writel(0, regs + WINCON(win));
144146 +       writel(0xffffff, regs + WxKEYCONy(win, 0));
144147 +       writel(0xffffff, regs + WxKEYCONy(win, 1));
144148 +
144149 +       writel(0, regs + VIDOSD_A(win));
144150 +       writel(0, regs + VIDOSD_B(win));
144151 +       writel(0, regs + VIDOSD_C(win));
144152 +}
144153 +
144154 +static int __devinit s3c_fb_probe(struct platform_device *pdev)
144155 +{
144156 +       struct device *dev = &pdev->dev;
144157 +       struct s3c_fb_platdata *pd;
144158 +       struct s3c_fb *sfb;
144159 +       struct resource *res;
144160 +       int win;
144161 +       int ret = 0;
144162 +
144163 +       pd = pdev->dev.platform_data;
144164 +       if (!pd) {
144165 +               dev_err(dev, "no platform data specified\n");
144166 +               return -EINVAL;
144167 +       }
144168 +
144169 +       sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
144170 +       if (!sfb) {
144171 +               dev_err(dev, "no memory for framebuffers\n");
144172 +               return -ENOMEM;
144173 +       }
144174 +
144175 +       sfb->dev = dev;
144176 +       sfb->pdata = pd;
144177 +
144178 +       sfb->bus_clk = clk_get(dev, "lcd");
144179 +       if (IS_ERR(sfb->bus_clk)) {
144180 +               dev_err(dev, "failed to get bus clock\n");
144181 +               goto err_sfb;
144182 +       }
144183 +
144184 +       clk_enable(sfb->bus_clk);
144185 +
144186 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
144187 +       if (!res) {
144188 +               dev_err(dev, "failed to find registers\n");
144189 +               ret = -ENOENT;
144190 +               goto err_clk;
144191 +       }
144192 +
144193 +       sfb->regs_res = request_mem_region(res->start, resource_size(res),
144194 +                                          dev_name(dev));
144195 +       if (!sfb->regs_res) {
144196 +               dev_err(dev, "failed to claim register region\n");
144197 +               ret = -ENOENT;
144198 +               goto err_clk;
144199 +       }
144200 +
144201 +       sfb->regs = ioremap(res->start, resource_size(res));
144202 +       if (!sfb->regs) {
144203 +               dev_err(dev, "failed to map registers\n");
144204 +               ret = -ENXIO;
144205 +               goto err_req_region;
144206 +       }
144207 +
144208 +       dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
144209 +
144210 +       /* setup gpio and output polarity controls */
144211 +
144212 +       pd->setup_gpio();
144213 +
144214 +       writel(pd->vidcon1, sfb->regs + VIDCON1);
144215 +
144216 +       /* zero all windows before we do anything */
144217 +
144218 +       for (win = 0; win < S3C_FB_MAX_WIN; win++)
144219 +               s3c_fb_clear_win(sfb, win);
144220 +
144221 +       /* we have the register setup, start allocating framebuffers */
144222 +
144223 +       for (win = 0; win < S3C_FB_MAX_WIN; win++) {
144224 +               if (!pd->win[win])
144225 +                       continue;
144226 +
144227 +               ret = s3c_fb_probe_win(sfb, win, &sfb->windows[win]);
144228 +               if (ret < 0) {
144229 +                       dev_err(dev, "failed to create window %d\n", win);
144230 +                       for (; win >= 0; win--)
144231 +                               s3c_fb_release_win(sfb, sfb->windows[win]);
144232 +                       goto err_ioremap;
144233 +               }
144234 +       }
144235 +
144236 +       platform_set_drvdata(pdev, sfb);
144237 +
144238 +       return 0;
144239 +
144240 +err_ioremap:
144241 +       iounmap(sfb->regs);
144242 +
144243 +err_req_region:
144244 +       release_resource(sfb->regs_res);
144245 +       kfree(sfb->regs_res);
144246 +
144247 +err_clk:
144248 +       clk_disable(sfb->bus_clk);
144249 +       clk_put(sfb->bus_clk);
144250 +
144251 +err_sfb:
144252 +       kfree(sfb);
144253 +       return ret;
144254 +}
144255 +
144256 +/**
144257 + * s3c_fb_remove() - Cleanup on module finalisation
144258 + * @pdev: The platform device we are bound to.
144259 + *
144260 + * Shutdown and then release all the resources that the driver allocated
144261 + * on initialisation.
144262 + */
144263 +static int __devexit s3c_fb_remove(struct platform_device *pdev)
144264 +{
144265 +       struct s3c_fb *sfb = platform_get_drvdata(pdev);
144266 +       int win;
144267 +
144268 +       for (win = 0; win <= S3C_FB_MAX_WIN; win++)
144269 +               s3c_fb_release_win(sfb, sfb->windows[win]);
144270 +
144271 +       iounmap(sfb->regs);
144272 +
144273 +       clk_disable(sfb->bus_clk);
144274 +       clk_put(sfb->bus_clk);
144275 +
144276 +       release_resource(sfb->regs_res);
144277 +       kfree(sfb->regs_res);
144278 +
144279 +       kfree(sfb);
144280 +
144281 +       return 0;
144282 +}
144283 +
144284 +#ifdef CONFIG_PM
144285 +static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
144286 +{
144287 +       struct s3c_fb *sfb = platform_get_drvdata(pdev);
144288 +       struct s3c_fb_win *win;
144289 +       int win_no;
144290 +
144291 +       for (win_no = S3C_FB_MAX_WIN; win_no >= 0; win_no--) {
144292 +               win = sfb->windows[win_no];
144293 +               if (!win)
144294 +                       continue;
144295 +
144296 +               /* use the blank function to push into power-down */
144297 +               s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
144298 +       }
144299 +
144300 +       clk_disable(sfb->bus_clk);
144301 +       return 0;
144302 +}
144303 +
144304 +static int s3c_fb_resume(struct platform_device *pdev)
144305 +{
144306 +       struct s3c_fb *sfb = platform_get_drvdata(pdev);
144307 +       struct s3c_fb_win *win;
144308 +       int win_no;
144309 +
144310 +       clk_enable(sfb->bus_clk);
144311 +
144312 +       for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
144313 +               win = sfb->windows[win_no];
144314 +               if (!win)
144315 +                       continue;
144316 +
144317 +               dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
144318 +               s3c_fb_set_par(win->fbinfo);
144319 +       }
144320 +
144321 +       return 0;
144322 +}
144323 +#else
144324 +#define s3c_fb_suspend NULL
144325 +#define s3c_fb_resume  NULL
144326 +#endif
144327 +
144328 +static struct platform_driver s3c_fb_driver = {
144329 +       .probe          = s3c_fb_probe,
144330 +       .remove         = s3c_fb_remove,
144331 +       .suspend        = s3c_fb_suspend,
144332 +       .resume         = s3c_fb_resume,
144333 +       .driver         = {
144334 +               .name   = "s3c-fb",
144335 +               .owner  = THIS_MODULE,
144336 +       },
144337 +};
144338 +
144339 +static int __init s3c_fb_init(void)
144340 +{
144341 +       return platform_driver_register(&s3c_fb_driver);
144342 +}
144343 +
144344 +static void __exit s3c_fb_cleanup(void)
144345 +{
144346 +       platform_driver_unregister(&s3c_fb_driver);
144347 +}
144348 +
144349 +module_init(s3c_fb_init);
144350 +module_exit(s3c_fb_cleanup);
144351 +
144352 +MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
144353 +MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
144354 +MODULE_LICENSE("GPL");
144355 +MODULE_ALIAS("platform:s3c-fb");
144356 Index: linux-2.6.28/drivers/watchdog/Kconfig
144357 ===================================================================
144358 --- linux-2.6.28.orig/drivers/watchdog/Kconfig  2008-12-25 00:26:37.000000000 +0100
144359 +++ linux-2.6.28/drivers/watchdog/Kconfig       2009-01-02 00:01:57.000000000 +0100
144360 @@ -233,6 +233,12 @@ config ORION5X_WATCHDOG
144361           To compile this driver as a module, choose M here: the
144362           module will be called orion5x_wdt.
144363
144364 +config PCF50606_WATCHDOG
144365 +       tristate "NXP PCF50606 Watchdog"
144366 +       depends on MFD_PCF50606
144367 +       help
144368 +        Say Y here to include support for NXP PCF50606 watchdog timer.
144369 +
144370  # ARM26 Architecture
144371
144372  # AVR32 Architecture
144373 @@ -784,7 +790,7 @@ config WATCHDOG_RTAS
144374         tristate "RTAS watchdog"
144375         depends on PPC_RTAS
144376         help
144377 -         This driver adds watchdog support for the RTAS watchdog.
144378 +         his driver adds watchdog support for the RTAS watchdog.
144379
144380           To compile this driver as a module, choose M here. The module
144381           will be called wdrtas.
144382 Index: linux-2.6.28/drivers/watchdog/Makefile
144383 ===================================================================
144384 --- linux-2.6.28.orig/drivers/watchdog/Makefile 2008-12-25 00:26:37.000000000 +0100
144385 +++ linux-2.6.28/drivers/watchdog/Makefile      2009-01-02 00:01:57.000000000 +0100
144386 @@ -41,6 +41,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx400
144387  obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
144388  obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
144389  obj-$(CONFIG_ORION5X_WATCHDOG) += orion5x_wdt.o
144390 +obj-$(CONFIG_PCF50606_WATCHDOG) += pcf50606_wdt.o
144391
144392  # ARM26 Architecture
144393
144394 Index: linux-2.6.28/drivers/watchdog/pcf50606_wdt.c
144395 ===================================================================
144396 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
144397 +++ linux-2.6.28/drivers/watchdog/pcf50606_wdt.c        2009-01-02 00:01:57.000000000 +0100
144398 @@ -0,0 +1,213 @@
144399 +/* Philips PCF50606 Watchdog Timer Driver
144400 + *
144401 + * (C) 2006-2008 by Openmoko, Inc.
144402 + * Author: Balaji Rao <balajirrao@openmoko.org>
144403 + * All rights reserved.
144404 + *
144405 + * Broken down from monstrous PCF50606 driver mainly by
144406 + * Harald Welte, Matt Hsu, Andy Green and Werner Almesberger
144407 + *
144408 + * This program is free software; you can redistribute it and/or
144409 + * modify it under the terms of the GNU General Public License as
144410 + * published by the Free Software Foundation; either version 2 of
144411 + * the License, or (at your option) any later version.
144412 + *
144413 + * This program is distributed in the hope that it will be useful,
144414 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
144415 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
144416 + * GNU General Public License for more details.
144417 + *
144418 + * You should have received a copy of the GNU General Public License
144419 + * along with this program; if not, write to the Free Software
144420 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
144421 + * MA 02111-1307 USA
144422 + */
144423 +
144424 +#include <linux/miscdevice.h>
144425 +#include <linux/watchdog.h>
144426 +
144427 +#include <linux/mfd/pcf50606/core.h>
144428 +#include <linux/mfd/pcf50606/wdt.h>
144429 +
144430 +static struct pcf50606 *pcf;
144431 +static unsigned long wdt_status;
144432 +#define WDT_IN_USE        0
144433 +#define WDT_OK_TO_CLOSE   1
144434 +#define WDT_REGION_INITED 2
144435 +#define WDT_DEVICE_INITED 3
144436 +
144437 +static int allow_close;
144438 +#define CLOSE_STATE_NOT                0x0000
144439 +#define CLOSE_STATE_ALLOW      0x2342
144440 +
144441 +static void pcf50606_wdt_start(void)
144442 +{
144443 +       pcf50606_reg_set_bit_mask(pcf, PCF50606_REG_OOCC1, PCF50606_OOCC1_WDTRST,
144444 +                        PCF50606_OOCC1_WDTRST);
144445 +}
144446 +
144447 +static void pcf50606_wdt_stop(void)
144448 +{
144449 +       pcf50606_reg_clear_bits(pcf, PCF50606_REG_OOCS, PCF50606_OOCS_WDTEXP);
144450 +}
144451 +
144452 +static void pcf50606_wdt_keepalive(void)
144453 +{
144454 +       pcf50606_wdt_start();
144455 +}
144456 +
144457 +static int pcf50606_wdt_open(struct inode *inode, struct file *file)
144458 +{
144459 +       if (test_and_set_bit(WDT_IN_USE, &wdt_status))
144460 +               return -EBUSY;
144461 +
144462 +       pcf50606_wdt_start();
144463 +
144464 +       return nonseekable_open(inode, file);
144465 +}
144466 +
144467 +static int pcf50606_wdt_release(struct inode *inode, struct file *file)
144468 +{
144469 +       if (allow_close == CLOSE_STATE_ALLOW)
144470 +               pcf50606_wdt_stop();
144471 +       else {
144472 +               printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n");
144473 +               pcf50606_wdt_keepalive();
144474 +       }
144475 +
144476 +       allow_close = CLOSE_STATE_NOT;
144477 +       clear_bit(WDT_IN_USE, &wdt_status);
144478 +
144479 +       return 0;
144480 +}
144481 +
144482 +static ssize_t pcf50606_wdt_write(struct file *file, const char __user *data,
144483 +                                 size_t len, loff_t *ppos)
144484 +{
144485 +       if (len) {
144486 +               size_t i;
144487 +
144488 +               for (i = 0; i != len; i++) {
144489 +                       char c;
144490 +                       if (get_user(c, data + i))
144491 +                               return -EFAULT;
144492 +                       if (c == 'V')
144493 +                               allow_close = CLOSE_STATE_ALLOW;
144494 +               }
144495 +               pcf50606_wdt_keepalive();
144496 +       }
144497 +
144498 +       return len;
144499 +}
144500 +
144501 +static struct watchdog_info pcf50606_wdt_ident = {
144502 +       .options        = WDIOF_MAGICCLOSE,
144503 +       .firmware_version = 0,
144504 +       .identity       = "PCF50606 Watchdog",
144505 +};
144506 +
144507 +static int pcf50606_wdt_ioctl(struct inode *inode, struct file *file,
144508 +                             unsigned int cmd, unsigned long arg)
144509 +{
144510 +       void __user *argp = (void __user *)arg;
144511 +       int __user *p = argp;
144512 +
144513 +       switch (cmd) {
144514 +       case WDIOC_GETSUPPORT:
144515 +               return copy_to_user(argp, &pcf50606_wdt_ident,
144516 +                                   sizeof(pcf50606_wdt_ident)) ? -EFAULT : 0;
144517 +               break;
144518 +       case WDIOC_GETSTATUS:
144519 +       case WDIOC_GETBOOTSTATUS:
144520 +               return put_user(0, p);
144521 +       case WDIOC_KEEPALIVE:
144522 +               pcf50606_wdt_keepalive();
144523 +               return 0;
144524 +       case WDIOC_GETTIMEOUT:
144525 +               return put_user(8, p);
144526 +       default:
144527 +               return -ENOIOCTLCMD;
144528 +       }
144529 +}
144530 +
144531 +static struct file_operations pcf50606_wdt_fops = {
144532 +       .owner          = THIS_MODULE,
144533 +       .llseek         = no_llseek,
144534 +       .write          = &pcf50606_wdt_write,
144535 +       .ioctl          = &pcf50606_wdt_ioctl,
144536 +       .open           = &pcf50606_wdt_open,
144537 +       .release        = &pcf50606_wdt_release,
144538 +};
144539 +
144540 +static struct miscdevice pcf50606_wdt_miscdev = {
144541 +       .minor          = WATCHDOG_MINOR,
144542 +       .name           = "watchdog",
144543 +       .fops           = &pcf50606_wdt_fops,
144544 +};
144545 +
144546 +static void pcf50606_wdt_irq(struct pcf50606 *pcf, int irq, void *unused)
144547 +{
144548 +       pcf50606_reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
144549 +                                PCF50606_OOCC1_WDTRST,
144550 +                                PCF50606_OOCC1_WDTRST);
144551 +}
144552 +
144553 +int __init pcf50606_wdt_probe(struct platform_device *pdev)
144554 +{
144555 +       struct pcf50606 *pcf;
144556 +       int err;
144557 +
144558 +       pcf = platform_get_drvdata(pdev);
144559 +
144560 +       err = misc_register(&pcf50606_wdt_miscdev);
144561 +       if (err) {
144562 +               dev_err(&pdev->dev, "cannot register miscdev on "
144563 +                      "minor=%d (%d)\n", WATCHDOG_MINOR, err);
144564 +               return err;
144565 +       }
144566 +       set_bit(WDT_DEVICE_INITED, &wdt_status);
144567 +
144568 +       /* Set up IRQ handlers */
144569 +       pcf->irq_handler[PCF50606_IRQ_CHGWD10S].handler = pcf50606_wdt_irq;
144570 +
144571 +       return 0;
144572 +}
144573 +
144574 +static int __devexit pcf50606_wdt_remove(struct platform_device *pdev)
144575 +{
144576 +       struct pcf50606 *pcf;
144577 +
144578 +       pcf = platform_get_drvdata(pdev);
144579 +
144580 +       misc_deregister(&pcf50606_wdt_miscdev);
144581 +
144582 +       pcf->irq_handler[PCF50606_IRQ_CHGWD10S].handler = NULL;
144583 +
144584 +       return 0;
144585 +}
144586 +
144587 +struct platform_driver pcf50606_wdt_driver = {
144588 +       .driver = {
144589 +               .name = "pcf50606-wdt",
144590 +       },
144591 +       .probe = pcf50606_wdt_probe,
144592 +       .remove = __devexit_p(pcf50606_wdt_remove),
144593 +};
144594 +
144595 +static int __init pcf50606_wdt_init(void)
144596 +{
144597 +               return platform_driver_register(&pcf50606_wdt_driver);
144598 +}
144599 +module_init(pcf50606_wdt_init);
144600 +
144601 +static void __exit pcf50606_wdt_exit(void)
144602 +{
144603 +               platform_driver_unregister(&pcf50606_wdt_driver);
144604 +}
144605 +module_exit(pcf50606_wdt_exit);
144606 +
144607 +MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
144608 +MODULE_DESCRIPTION("PCF50606 wdt driver");
144609 +MODULE_LICENSE("GPL");
144610 +MODULE_ALIAS("platform:pcf50606-wdt");
144611 +
144612 Index: linux-2.6.28/drivers/watchdog/s3c2410_wdt.c
144613 ===================================================================
144614 --- linux-2.6.28.orig/drivers/watchdog/s3c2410_wdt.c    2008-12-25 00:26:37.000000000 +0100
144615 +++ linux-2.6.28/drivers/watchdog/s3c2410_wdt.c 2009-01-02 00:01:57.000000000 +0100
144616 @@ -42,7 +42,7 @@
144617  #undef S3C_VA_WATCHDOG
144618  #define S3C_VA_WATCHDOG (0)
144619
144620 -#include <asm/plat-s3c/regs-watchdog.h>
144621 +#include <plat/regs-watchdog.h>
144622
144623  #define PFX "s3c2410-wdt: "
144624
144625 Index: linux-2.6.28/fs/jffs2/background.c
144626 ===================================================================
144627 --- linux-2.6.28.orig/fs/jffs2/background.c     2008-12-25 00:26:37.000000000 +0100
144628 +++ linux-2.6.28/fs/jffs2/background.c  2009-01-02 00:01:57.000000000 +0100
144629 @@ -95,13 +95,17 @@ static int jffs2_garbage_collect_thread(
144630                         spin_unlock(&c->erase_completion_lock);
144631
144632
144633 -               /* This thread is purely an optimisation. But if it runs when
144634 -                  other things could be running, it actually makes things a
144635 -                  lot worse. Use yield() and put it at the back of the runqueue
144636 -                  every time. Especially during boot, pulling an inode in
144637 -                  with read_inode() is much preferable to having the GC thread
144638 -                  get there first. */
144639 -               yield();
144640 +               /* Problem - immediately after bootup, the GCD spends a lot
144641 +                * of time in places like jffs2_kill_fragtree(); so much so
144642 +                * that userspace processes (like gdm and X) are starved
144643 +                * despite plenty of cond_resched()s and renicing.  Yield()
144644 +                * doesn't help, either (presumably because userspace and GCD
144645 +                * are generally competing for a higher latency resource -
144646 +                * disk).
144647 +                * This forces the GCD to slow the hell down.   Pulling an
144648 +                * inode in with read_inode() is much preferable to having
144649 +                * the GC thread get there first. */
144650 +               schedule_timeout_interruptible(msecs_to_jiffies(50));
144651
144652                 /* Put_super will send a SIGKILL and then wait on the sem.
144653                  */
144654 Index: linux-2.6.28/include/asm-arm/plat-s3c/iic.h
144655 ===================================================================
144656 --- linux-2.6.28.orig/include/asm-arm/plat-s3c/iic.h    2008-12-25 00:26:37.000000000 +0100
144657 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
144658 @@ -1,33 +0,0 @@
144659 -/* arch/arm/mach-s3c2410/include/mach/iic.h
144660 - *
144661 - * Copyright (c) 2004 Simtec Electronics
144662 - *     Ben Dooks <ben@simtec.co.uk>
144663 - *
144664 - * S3C2410 - I2C Controller platfrom_device info
144665 - *
144666 - * This program is free software; you can redistribute it and/or modify
144667 - * it under the terms of the GNU General Public License version 2 as
144668 - * published by the Free Software Foundation.
144669 -*/
144670 -
144671 -#ifndef __ASM_ARCH_IIC_H
144672 -#define __ASM_ARCH_IIC_H __FILE__
144673 -
144674 -#define S3C_IICFLG_FILTER      (1<<0)  /* enable s3c2440 filter */
144675 -
144676 -/* Notes:
144677 - *     1) All frequencies are expressed in Hz
144678 - *     2) A value of zero is `do not care`
144679 -*/
144680 -
144681 -struct s3c2410_platform_i2c {
144682 -       int             bus_num;        /* bus number to use */
144683 -       unsigned int    flags;
144684 -       unsigned int    slave_addr;     /* slave address for controller */
144685 -       unsigned long   bus_freq;       /* standard bus frequency */
144686 -       unsigned long   max_freq;       /* max frequency for the bus */
144687 -       unsigned long   min_freq;       /* min frequency for the bus */
144688 -       unsigned int    sda_delay;      /* pclks (s3c2440 only) */
144689 -};
144690 -
144691 -#endif /* __ASM_ARCH_IIC_H */
144692 Index: linux-2.6.28/include/asm-arm/plat-s3c/nand.h
144693 ===================================================================
144694 --- linux-2.6.28.orig/include/asm-arm/plat-s3c/nand.h   2008-12-25 00:26:37.000000000 +0100
144695 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
144696 @@ -1,50 +0,0 @@
144697 -/* arch/arm/mach-s3c2410/include/mach/nand.h
144698 - *
144699 - * Copyright (c) 2004 Simtec Electronics
144700 - *     Ben Dooks <ben@simtec.co.uk>
144701 - *
144702 - * S3C2410 - NAND device controller platfrom_device info
144703 - *
144704 - * This program is free software; you can redistribute it and/or modify
144705 - * it under the terms of the GNU General Public License version 2 as
144706 - * published by the Free Software Foundation.
144707 -*/
144708 -
144709 -/* struct s3c2410_nand_set
144710 - *
144711 - * define an set of one or more nand chips registered with an unique mtd
144712 - *
144713 - * nr_chips     = number of chips in this set
144714 - * nr_partitions = number of partitions pointed to be partitoons (or zero)
144715 - * name                 = name of set (optional)
144716 - * nr_map       = map for low-layer logical to physical chip numbers (option)
144717 - * partitions   = mtd partition list
144718 -*/
144719 -
144720 -struct s3c2410_nand_set {
144721 -       unsigned int            disable_ecc : 1;
144722 -
144723 -       int                     nr_chips;
144724 -       int                     nr_partitions;
144725 -       char                    *name;
144726 -       int                     *nr_map;
144727 -       struct mtd_partition    *partitions;
144728 -       struct nand_ecclayout   *ecc_layout;
144729 -};
144730 -
144731 -struct s3c2410_platform_nand {
144732 -       /* timing information for controller, all times in nanoseconds */
144733 -
144734 -       int     tacls;  /* time for active CLE/ALE to nWE/nOE */
144735 -       int     twrph0; /* active time for nWE/nOE */
144736 -       int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
144737 -
144738 -       unsigned int    ignore_unset_ecc : 1;
144739 -
144740 -       int                     nr_sets;
144741 -       struct s3c2410_nand_set *sets;
144742 -
144743 -       void                    (*select_chip)(struct s3c2410_nand_set *,
144744 -                                              int chip);
144745 -};
144746 -
144747 Index: linux-2.6.28/include/asm-arm/plat-s3c/regs-ac97.h
144748 ===================================================================
144749 --- linux-2.6.28.orig/include/asm-arm/plat-s3c/regs-ac97.h      2008-12-25 00:26:37.000000000 +0100
144750 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
144751 @@ -1,67 +0,0 @@
144752 -/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
144753 - *
144754 - * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
144755 - *             http://www.simtec.co.uk/products/SWLINUX/
144756 - *
144757 - * This program is free software; you can redistribute it and/or modify
144758 - * it under the terms of the GNU General Public License version 2 as
144759 - * published by the Free Software Foundation.
144760 - *
144761 - * S3C2440 AC97 Controller
144762 -*/
144763 -
144764 -#ifndef __ASM_ARCH_REGS_AC97_H
144765 -#define __ASM_ARCH_REGS_AC97_H __FILE__
144766 -
144767 -#define S3C_AC97_GLBCTRL                               (0x00)
144768 -
144769 -#define S3C_AC97_GLBCTRL_CODECREADYIE                  (1<<22)
144770 -#define S3C_AC97_GLBCTRL_PCMOUTURIE                    (1<<21)
144771 -#define S3C_AC97_GLBCTRL_PCMINORIE                     (1<<20)
144772 -#define S3C_AC97_GLBCTRL_MICINORIE                     (1<<19)
144773 -#define S3C_AC97_GLBCTRL_PCMOUTTIE                     (1<<18)
144774 -#define S3C_AC97_GLBCTRL_PCMINTIE                      (1<<17)
144775 -#define S3C_AC97_GLBCTRL_MICINTIE                      (1<<16)
144776 -#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                  (0<<12)
144777 -#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                  (1<<12)
144778 -#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                  (2<<12)
144779 -#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                 (3<<12)
144780 -#define S3C_AC97_GLBCTRL_PCMINTM_OFF                   (0<<10)
144781 -#define S3C_AC97_GLBCTRL_PCMINTM_PIO                   (1<<10)
144782 -#define S3C_AC97_GLBCTRL_PCMINTM_DMA                   (2<<10)
144783 -#define S3C_AC97_GLBCTRL_PCMINTM_MASK                  (3<<10)
144784 -#define S3C_AC97_GLBCTRL_MICINTM_OFF                   (0<<8)
144785 -#define S3C_AC97_GLBCTRL_MICINTM_PIO                   (1<<8)
144786 -#define S3C_AC97_GLBCTRL_MICINTM_DMA                   (2<<8)
144787 -#define S3C_AC97_GLBCTRL_MICINTM_MASK                  (3<<8)
144788 -#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE            (1<<3)
144789 -#define S3C_AC97_GLBCTRL_ACLINKON                      (1<<2)
144790 -#define S3C_AC97_GLBCTRL_WARMRESET                     (1<<1)
144791 -#define S3C_AC97_GLBCTRL_COLDRESET                     (1<<0)
144792 -
144793 -#define S3C_AC97_GLBSTAT                               (0x04)
144794 -
144795 -#define S3C_AC97_GLBSTAT_CODECREADY                    (1<<22)
144796 -#define S3C_AC97_GLBSTAT_PCMOUTUR                      (1<<21)
144797 -#define S3C_AC97_GLBSTAT_PCMINORI                      (1<<20)
144798 -#define S3C_AC97_GLBSTAT_MICINORI                      (1<<19)
144799 -#define S3C_AC97_GLBSTAT_PCMOUTTI                      (1<<18)
144800 -#define S3C_AC97_GLBSTAT_PCMINTI                       (1<<17)
144801 -#define S3C_AC97_GLBSTAT_MICINTI                       (1<<16)
144802 -#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                        (0<<0)
144803 -#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                        (1<<0)
144804 -#define S3C_AC97_GLBSTAT_MAINSTATE_READY               (2<<0)
144805 -#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE              (3<<0)
144806 -#define S3C_AC97_GLBSTAT_MAINSTATE_LP                  (4<<0)
144807 -#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                        (5<<0)
144808 -
144809 -#define S3C_AC97_CODEC_CMD                             (0x08)
144810 -
144811 -#define S3C_AC97_CODEC_CMD_READ                                (1<<23)
144812 -
144813 -#define S3C_AC97_STAT                                  (0x0c)
144814 -#define S3C_AC97_PCM_ADDR                              (0x10)
144815 -#define S3C_AC97_PCM_DATA                              (0x18)
144816 -#define S3C_AC97_MIC_DATA                              (0x1C)
144817 -
144818 -#endif /* __ASM_ARCH_REGS_AC97_H */
144819 Index: linux-2.6.28/include/asm-arm/plat-s3c/regs-iic.h
144820 ===================================================================
144821 --- linux-2.6.28.orig/include/asm-arm/plat-s3c/regs-iic.h       2008-12-25 00:26:37.000000000 +0100
144822 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
144823 @@ -1,56 +0,0 @@
144824 -/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
144825 - *
144826 - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
144827 - *             http://www.simtec.co.uk/products/SWLINUX/
144828 - *
144829 - * This program is free software; you can redistribute it and/or modify
144830 - * it under the terms of the GNU General Public License version 2 as
144831 - * published by the Free Software Foundation.
144832 - *
144833 - * S3C2410 I2C Controller
144834 -*/
144835 -
144836 -#ifndef __ASM_ARCH_REGS_IIC_H
144837 -#define __ASM_ARCH_REGS_IIC_H __FILE__
144838 -
144839 -/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
144840 -
144841 -#define S3C2410_IICREG(x) (x)
144842 -
144843 -#define S3C2410_IICCON    S3C2410_IICREG(0x00)
144844 -#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
144845 -#define S3C2410_IICADD    S3C2410_IICREG(0x08)
144846 -#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
144847 -#define S3C2440_IICLC    S3C2410_IICREG(0x10)
144848 -
144849 -#define S3C2410_IICCON_ACKEN           (1<<7)
144850 -#define S3C2410_IICCON_TXDIV_16                (0<<6)
144851 -#define S3C2410_IICCON_TXDIV_512       (1<<6)
144852 -#define S3C2410_IICCON_IRQEN           (1<<5)
144853 -#define S3C2410_IICCON_IRQPEND         (1<<4)
144854 -#define S3C2410_IICCON_SCALE(x)                ((x)&15)
144855 -#define S3C2410_IICCON_SCALEMASK       (0xf)
144856 -
144857 -#define S3C2410_IICSTAT_MASTER_RX      (2<<6)
144858 -#define S3C2410_IICSTAT_MASTER_TX      (3<<6)
144859 -#define S3C2410_IICSTAT_SLAVE_RX       (0<<6)
144860 -#define S3C2410_IICSTAT_SLAVE_TX       (1<<6)
144861 -#define S3C2410_IICSTAT_MODEMASK       (3<<6)
144862 -
144863 -#define S3C2410_IICSTAT_START          (1<<5)
144864 -#define S3C2410_IICSTAT_BUSBUSY                (1<<5)
144865 -#define S3C2410_IICSTAT_TXRXEN         (1<<4)
144866 -#define S3C2410_IICSTAT_ARBITR         (1<<3)
144867 -#define S3C2410_IICSTAT_ASSLAVE                (1<<2)
144868 -#define S3C2410_IICSTAT_ADDR0          (1<<1)
144869 -#define S3C2410_IICSTAT_LASTBIT                (1<<0)
144870 -
144871 -#define S3C2410_IICLC_SDA_DELAY0       (0 << 0)
144872 -#define S3C2410_IICLC_SDA_DELAY5       (1 << 0)
144873 -#define S3C2410_IICLC_SDA_DELAY10      (2 << 0)
144874 -#define S3C2410_IICLC_SDA_DELAY15      (3 << 0)
144875 -#define S3C2410_IICLC_SDA_DELAY_MASK   (3 << 0)
144876 -
144877 -#define S3C2410_IICLC_FILTER_ON                (1<<2)
144878 -
144879 -#endif /* __ASM_ARCH_REGS_IIC_H */
144880 Index: linux-2.6.28/include/asm-arm/plat-s3c/regs-nand.h
144881 ===================================================================
144882 --- linux-2.6.28.orig/include/asm-arm/plat-s3c/regs-nand.h      2008-12-25 00:26:37.000000000 +0100
144883 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
144884 @@ -1,123 +0,0 @@
144885 -/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
144886 - *
144887 - * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
144888 - *                   http://www.simtec.co.uk/products/SWLINUX/
144889 - *
144890 - * This program is free software; you can redistribute it and/or modify
144891 - * it under the terms of the GNU General Public License version 2 as
144892 - * published by the Free Software Foundation.
144893 - *
144894 - * S3C2410 NAND register definitions
144895 -*/
144896 -
144897 -#ifndef __ASM_ARM_REGS_NAND
144898 -#define __ASM_ARM_REGS_NAND
144899 -
144900 -
144901 -#define S3C2410_NFREG(x) (x)
144902 -
144903 -#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
144904 -#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
144905 -#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
144906 -#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
144907 -#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
144908 -#define S3C2410_NFECC   S3C2410_NFREG(0x14)
144909 -
144910 -#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
144911 -#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
144912 -#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
144913 -#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
144914 -#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
144915 -#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
144916 -#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
144917 -#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
144918 -#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
144919 -#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
144920 -#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
144921 -#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
144922 -#define S3C2440_NFSECC   S3C2410_NFREG(0x34)
144923 -#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
144924 -#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
144925 -
144926 -#define S3C2412_NFSBLK         S3C2410_NFREG(0x20)
144927 -#define S3C2412_NFEBLK         S3C2410_NFREG(0x24)
144928 -#define S3C2412_NFSTAT         S3C2410_NFREG(0x28)
144929 -#define S3C2412_NFMECC_ERR0    S3C2410_NFREG(0x2C)
144930 -#define S3C2412_NFMECC_ERR1    S3C2410_NFREG(0x30)
144931 -#define S3C2412_NFMECC0                S3C2410_NFREG(0x34)
144932 -#define S3C2412_NFMECC1                S3C2410_NFREG(0x38)
144933 -#define S3C2412_NFSECC         S3C2410_NFREG(0x3C)
144934 -
144935 -#define S3C2410_NFCONF_EN          (1<<15)
144936 -#define S3C2410_NFCONF_512BYTE     (1<<14)
144937 -#define S3C2410_NFCONF_4STEP       (1<<13)
144938 -#define S3C2410_NFCONF_INITECC     (1<<12)
144939 -#define S3C2410_NFCONF_nFCE        (1<<11)
144940 -#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
144941 -#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
144942 -#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
144943 -
144944 -#define S3C2410_NFSTAT_BUSY        (1<<0)
144945 -
144946 -#define S3C2440_NFCONF_BUSWIDTH_8      (0<<0)
144947 -#define S3C2440_NFCONF_BUSWIDTH_16     (1<<0)
144948 -#define S3C2440_NFCONF_ADVFLASH                (1<<3)
144949 -#define S3C2440_NFCONF_TACLS(x)                ((x)<<12)
144950 -#define S3C2440_NFCONF_TWRPH0(x)       ((x)<<8)
144951 -#define S3C2440_NFCONF_TWRPH1(x)       ((x)<<4)
144952 -
144953 -#define S3C2440_NFCONT_LOCKTIGHT       (1<<13)
144954 -#define S3C2440_NFCONT_SOFTLOCK                (1<<12)
144955 -#define S3C2440_NFCONT_ILLEGALACC_EN   (1<<10)
144956 -#define S3C2440_NFCONT_RNBINT_EN       (1<<9)
144957 -#define S3C2440_NFCONT_RN_FALLING      (1<<8)
144958 -#define S3C2440_NFCONT_SPARE_ECCLOCK   (1<<6)
144959 -#define S3C2440_NFCONT_MAIN_ECCLOCK    (1<<5)
144960 -#define S3C2440_NFCONT_INITECC         (1<<4)
144961 -#define S3C2440_NFCONT_nFCE            (1<<1)
144962 -#define S3C2440_NFCONT_ENABLE          (1<<0)
144963 -
144964 -#define S3C2440_NFSTAT_READY           (1<<0)
144965 -#define S3C2440_NFSTAT_nCE             (1<<1)
144966 -#define S3C2440_NFSTAT_RnB_CHANGE      (1<<2)
144967 -#define S3C2440_NFSTAT_ILLEGAL_ACCESS  (1<<3)
144968 -
144969 -#define S3C2412_NFCONF_NANDBOOT                (1<<31)
144970 -#define S3C2412_NFCONF_ECCCLKCON       (1<<30)
144971 -#define S3C2412_NFCONF_ECC_MLC         (1<<24)
144972 -#define S3C2412_NFCONF_TACLS_MASK      (7<<12) /* 1 extra bit of Tacls */
144973 -
144974 -#define S3C2412_NFCONT_ECC4_DIRWR      (1<<18)
144975 -#define S3C2412_NFCONT_LOCKTIGHT       (1<<17)
144976 -#define S3C2412_NFCONT_SOFTLOCK                (1<<16)
144977 -#define S3C2412_NFCONT_ECC4_ENCINT     (1<<13)
144978 -#define S3C2412_NFCONT_ECC4_DECINT     (1<<12)
144979 -#define S3C2412_NFCONT_MAIN_ECC_LOCK   (1<<7)
144980 -#define S3C2412_NFCONT_INIT_MAIN_ECC   (1<<5)
144981 -#define S3C2412_NFCONT_nFCE1           (1<<2)
144982 -#define S3C2412_NFCONT_nFCE0           (1<<1)
144983 -
144984 -#define S3C2412_NFSTAT_ECC_ENCDONE     (1<<7)
144985 -#define S3C2412_NFSTAT_ECC_DECDONE     (1<<6)
144986 -#define S3C2412_NFSTAT_ILLEGAL_ACCESS  (1<<5)
144987 -#define S3C2412_NFSTAT_RnB_CHANGE      (1<<4)
144988 -#define S3C2412_NFSTAT_nFCE1           (1<<3)
144989 -#define S3C2412_NFSTAT_nFCE0           (1<<2)
144990 -#define S3C2412_NFSTAT_Res1            (1<<1)
144991 -#define S3C2412_NFSTAT_READY           (1<<0)
144992 -
144993 -#define S3C2412_NFECCERR_SERRDATA(x)   (((x) >> 21) & 0xf)
144994 -#define S3C2412_NFECCERR_SERRBIT(x)    (((x) >> 18) & 0x7)
144995 -#define S3C2412_NFECCERR_MERRDATA(x)   (((x) >> 7) & 0x3ff)
144996 -#define S3C2412_NFECCERR_MERRBIT(x)    (((x) >> 4) & 0x7)
144997 -#define S3C2412_NFECCERR_SPARE_ERR(x)  (((x) >> 2) & 0x3)
144998 -#define S3C2412_NFECCERR_MAIN_ERR(x)   (((x) >> 2) & 0x3)
144999 -#define S3C2412_NFECCERR_NONE          (0)
145000 -#define S3C2412_NFECCERR_1BIT          (1)
145001 -#define S3C2412_NFECCERR_MULTIBIT      (2)
145002 -#define S3C2412_NFECCERR_ECCAREA       (3)
145003 -
145004 -
145005 -
145006 -#endif /* __ASM_ARM_REGS_NAND */
145007 -
145008 Index: linux-2.6.28/include/asm-arm/plat-s3c/regs-rtc.h
145009 ===================================================================
145010 --- linux-2.6.28.orig/include/asm-arm/plat-s3c/regs-rtc.h       2008-12-25 00:26:37.000000000 +0100
145011 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
145012 @@ -1,61 +0,0 @@
145013 -/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
145014 - *
145015 - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
145016 - *                   http://www.simtec.co.uk/products/SWLINUX/
145017 - *
145018 - * This program is free software; you can redistribute it and/or modify
145019 - * it under the terms of the GNU General Public License version 2 as
145020 - * published by the Free Software Foundation.
145021 - *
145022 - * S3C2410 Internal RTC register definition
145023 -*/
145024 -
145025 -#ifndef __ASM_ARCH_REGS_RTC_H
145026 -#define __ASM_ARCH_REGS_RTC_H __FILE__
145027 -
145028 -#define S3C2410_RTCREG(x) (x)
145029 -
145030 -#define S3C2410_RTCCON       S3C2410_RTCREG(0x40)
145031 -#define S3C2410_RTCCON_RTCEN  (1<<0)
145032 -#define S3C2410_RTCCON_CLKSEL (1<<1)
145033 -#define S3C2410_RTCCON_CNTSEL (1<<2)
145034 -#define S3C2410_RTCCON_CLKRST (1<<3)
145035 -
145036 -#define S3C2410_TICNT        S3C2410_RTCREG(0x44)
145037 -#define S3C2410_TICNT_ENABLE  (1<<7)
145038 -
145039 -#define S3C2410_RTCALM       S3C2410_RTCREG(0x50)
145040 -#define S3C2410_RTCALM_ALMEN  (1<<6)
145041 -#define S3C2410_RTCALM_YEAREN (1<<5)
145042 -#define S3C2410_RTCALM_MONEN  (1<<4)
145043 -#define S3C2410_RTCALM_DAYEN  (1<<3)
145044 -#define S3C2410_RTCALM_HOUREN (1<<2)
145045 -#define S3C2410_RTCALM_MINEN  (1<<1)
145046 -#define S3C2410_RTCALM_SECEN  (1<<0)
145047 -
145048 -#define S3C2410_RTCALM_ALL \
145049 -  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
145050 -  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
145051 -  S3C2410_RTCALM_SECEN
145052 -
145053 -
145054 -#define S3C2410_ALMSEC       S3C2410_RTCREG(0x54)
145055 -#define S3C2410_ALMMIN       S3C2410_RTCREG(0x58)
145056 -#define S3C2410_ALMHOUR              S3C2410_RTCREG(0x5c)
145057 -
145058 -#define S3C2410_ALMDATE              S3C2410_RTCREG(0x60)
145059 -#define S3C2410_ALMMON       S3C2410_RTCREG(0x64)
145060 -#define S3C2410_ALMYEAR              S3C2410_RTCREG(0x68)
145061 -
145062 -#define S3C2410_RTCRST       S3C2410_RTCREG(0x6c)
145063 -
145064 -#define S3C2410_RTCSEC       S3C2410_RTCREG(0x70)
145065 -#define S3C2410_RTCMIN       S3C2410_RTCREG(0x74)
145066 -#define S3C2410_RTCHOUR              S3C2410_RTCREG(0x78)
145067 -#define S3C2410_RTCDATE              S3C2410_RTCREG(0x7c)
145068 -#define S3C2410_RTCDAY       S3C2410_RTCREG(0x80)
145069 -#define S3C2410_RTCMON       S3C2410_RTCREG(0x84)
145070 -#define S3C2410_RTCYEAR              S3C2410_RTCREG(0x88)
145071 -
145072 -
145073 -#endif /* __ASM_ARCH_REGS_RTC_H */
145074 Index: linux-2.6.28/include/asm-arm/plat-s3c/regs-watchdog.h
145075 ===================================================================
145076 --- linux-2.6.28.orig/include/asm-arm/plat-s3c/regs-watchdog.h  2008-12-25 00:26:37.000000000 +0100
145077 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
145078 @@ -1,41 +0,0 @@
145079 -/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
145080 - *
145081 - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
145082 - *                   http://www.simtec.co.uk/products/SWLINUX/
145083 - *
145084 - * This program is free software; you can redistribute it and/or modify
145085 - * it under the terms of the GNU General Public License version 2 as
145086 - * published by the Free Software Foundation.
145087 - *
145088 - * S3C2410 Watchdog timer control
145089 -*/
145090 -
145091 -
145092 -#ifndef __ASM_ARCH_REGS_WATCHDOG_H
145093 -#define __ASM_ARCH_REGS_WATCHDOG_H
145094 -
145095 -#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
145096 -
145097 -#define S3C2410_WTCON     S3C_WDOGREG(0x00)
145098 -#define S3C2410_WTDAT     S3C_WDOGREG(0x04)
145099 -#define S3C2410_WTCNT     S3C_WDOGREG(0x08)
145100 -
145101 -/* the watchdog can either generate a reset pulse, or an
145102 - * interrupt.
145103 - */
145104 -
145105 -#define S3C2410_WTCON_RSTEN   (0x01)
145106 -#define S3C2410_WTCON_INTEN   (1<<2)
145107 -#define S3C2410_WTCON_ENABLE  (1<<5)
145108 -
145109 -#define S3C2410_WTCON_DIV16   (0<<3)
145110 -#define S3C2410_WTCON_DIV32   (1<<3)
145111 -#define S3C2410_WTCON_DIV64   (2<<3)
145112 -#define S3C2410_WTCON_DIV128  (3<<3)
145113 -
145114 -#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
145115 -#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
145116 -
145117 -#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
145118 -
145119 -
145120 Index: linux-2.6.28/include/asm-arm/plat-s3c24xx/mci.h
145121 ===================================================================
145122 --- linux-2.6.28.orig/include/asm-arm/plat-s3c24xx/mci.h        2008-12-25 00:26:37.000000000 +0100
145123 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
145124 @@ -1,15 +0,0 @@
145125 -#ifndef _ARCH_MCI_H
145126 -#define _ARCH_MCI_H
145127 -
145128 -struct s3c24xx_mci_pdata {
145129 -       unsigned int    wprotect_invert : 1;
145130 -       unsigned int    detect_invert : 1;   /* set => detect active high. */
145131 -
145132 -       unsigned int    gpio_detect;
145133 -       unsigned int    gpio_wprotect;
145134 -       unsigned long   ocr_avail;
145135 -       void            (*set_power)(unsigned char power_mode,
145136 -                                    unsigned short vdd);
145137 -};
145138 -
145139 -#endif /* _ARCH_NCI_H */
145140 Index: linux-2.6.28/include/asm-arm/plat-s3c24xx/neo1973.h
145141 ===================================================================
145142 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
145143 +++ linux-2.6.28/include/asm-arm/plat-s3c24xx/neo1973.h 2009-01-02 00:01:57.000000000 +0100
145144 @@ -0,0 +1,33 @@
145145 +/*
145146 + * include/asm-arm/plat-s3c24xx/neo1973.h
145147 + *
145148 + * Common utility code for GTA01 and GTA02
145149 + *
145150 + * Copyright (C) 2008 by Openmoko, Inc.
145151 + * Author: Holger Hans Peter Freyther <freyther@openmoko.org>
145152 + * All rights reserved.
145153 + *
145154 + * This program is free software; you can redistribute it and/or
145155 + * modify it under the terms of the GNU General Public License as
145156 + * published by the Free Software Foundation; either version 2 of
145157 + * the License, or (at your option) any later version.
145158 + *
145159 + * This program is distributed in the hope that it will be useful,
145160 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
145161 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145162 + * GNU General Public License for more details.
145163 + *
145164 + * You should have received a copy of the GNU General Public License
145165 + * along with this program; if not, write to the Free Software
145166 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
145167 + * MA 02111-1307 USA
145168 + *
145169 + */
145170 +
145171 +#ifndef NEO1973_H
145172 +#define NEO1973_H
145173 +
145174 +void neo1973_gpb_add_shadow_gpio(unsigned int gpio);
145175 +void neo1973_gpb_setpin(unsigned int pin, unsigned to);
145176 +
145177 +#endif
145178 Index: linux-2.6.28/include/asm-arm/plat-s3c24xx/regs-spi.h
145179 ===================================================================
145180 --- linux-2.6.28.orig/include/asm-arm/plat-s3c24xx/regs-spi.h   2008-12-25 00:26:37.000000000 +0100
145181 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
145182 @@ -1,82 +0,0 @@
145183 -/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
145184 - *
145185 - * Copyright (c) 2004 Fetron GmbH
145186 - *
145187 - * This program is free software; you can redistribute it and/or modify
145188 - * it under the terms of the GNU General Public License version 2 as
145189 - * published by the Free Software Foundation.
145190 - *
145191 - * S3C2410 SPI register definition
145192 -*/
145193 -
145194 -#ifndef __ASM_ARCH_REGS_SPI_H
145195 -#define __ASM_ARCH_REGS_SPI_H
145196 -
145197 -#define S3C2410_SPI1   (0x20)
145198 -#define S3C2412_SPI1   (0x100)
145199 -
145200 -#define S3C2410_SPCON  (0x00)
145201 -
145202 -#define S3C2412_SPCON_RXFIFO_RB2       (0<<14)
145203 -#define S3C2412_SPCON_RXFIFO_RB4       (1<<14)
145204 -#define S3C2412_SPCON_RXFIFO_RB12      (2<<14)
145205 -#define S3C2412_SPCON_RXFIFO_RB14      (3<<14)
145206 -#define S3C2412_SPCON_TXFIFO_RB2       (0<<12)
145207 -#define S3C2412_SPCON_TXFIFO_RB4       (1<<12)
145208 -#define S3C2412_SPCON_TXFIFO_RB12      (2<<12)
145209 -#define S3C2412_SPCON_TXFIFO_RB14      (3<<12)
145210 -#define S3C2412_SPCON_RXFIFO_RESET     (1<<11) /* RxFIFO reset */
145211 -#define S3C2412_SPCON_TXFIFO_RESET     (1<<10) /* TxFIFO reset */
145212 -#define S3C2412_SPCON_RXFIFO_EN                (1<<9)  /* RxFIFO Enable */
145213 -#define S3C2412_SPCON_TXFIFO_EN                (1<<8)  /* TxFIFO Enable */
145214 -
145215 -#define S3C2412_SPCON_DIRC_RX    (1<<7)
145216 -
145217 -#define S3C2410_SPCON_SMOD_DMA   (2<<5)        /* DMA mode */
145218 -#define S3C2410_SPCON_SMOD_INT   (1<<5)        /* interrupt mode */
145219 -#define S3C2410_SPCON_SMOD_POLL   (0<<5)       /* polling mode */
145220 -#define S3C2410_SPCON_ENSCK      (1<<4)        /* Enable SCK */
145221 -#define S3C2410_SPCON_MSTR       (1<<3)        /* Master/Slave select
145222 -                                                  0: slave, 1: master */
145223 -#define S3C2410_SPCON_CPOL_HIGH          (1<<2)        /* Clock polarity select */
145224 -#define S3C2410_SPCON_CPOL_LOW   (0<<2)        /* Clock polarity select */
145225 -
145226 -#define S3C2410_SPCON_CPHA_FMTB          (1<<1)        /* Clock Phase Select */
145227 -#define S3C2410_SPCON_CPHA_FMTA          (0<<1)        /* Clock Phase Select */
145228 -
145229 -#define S3C2410_SPCON_TAGD       (1<<0)        /* Tx auto garbage data mode */
145230 -
145231 -
145232 -#define S3C2410_SPSTA   (0x04)
145233 -
145234 -#define S3C2412_SPSTA_RXFIFO_AE                (1<<11)
145235 -#define S3C2412_SPSTA_TXFIFO_AE                (1<<10)
145236 -#define S3C2412_SPSTA_RXFIFO_ERROR     (1<<9)
145237 -#define S3C2412_SPSTA_TXFIFO_ERROR     (1<<8)
145238 -#define S3C2412_SPSTA_RXFIFO_FIFO      (1<<7)
145239 -#define S3C2412_SPSTA_RXFIFO_EMPTY     (1<<6)
145240 -#define S3C2412_SPSTA_TXFIFO_NFULL     (1<<5)
145241 -#define S3C2412_SPSTA_TXFIFO_EMPTY     (1<<4)
145242 -
145243 -#define S3C2410_SPSTA_DCOL       (1<<2)        /* Data Collision Error */
145244 -#define S3C2410_SPSTA_MULD       (1<<1)        /* Multi Master Error */
145245 -#define S3C2410_SPSTA_READY      (1<<0)        /* Data Tx/Rx ready */
145246 -#define S3C2412_SPSTA_READY_ORG          (1<<3)
145247 -
145248 -#define S3C2410_SPPIN   (0x08)
145249 -
145250 -#define S3C2410_SPPIN_ENMUL      (1<<2)        /* Multi Master Error detect */
145251 -#define S3C2410_SPPIN_RESERVED   (1<<1)
145252 -#define S3C2400_SPPIN_nCS        (1<<1)        /* SPI Card Select */
145253 -#define S3C2410_SPPIN_KEEP       (1<<0)        /* Master Out keep */
145254 -
145255 -#define S3C2410_SPPRE   (0x0C)
145256 -#define S3C2410_SPTDAT  (0x10)
145257 -#define S3C2410_SPRDAT  (0x14)
145258 -
145259 -#define S3C2412_TXFIFO  (0x18)
145260 -#define S3C2412_RXFIFO  (0x18)
145261 -#define S3C2412_SPFIC   (0x24)
145262 -
145263 -
145264 -#endif /* __ASM_ARCH_REGS_SPI_H */
145265 Index: linux-2.6.28/include/asm-arm/plat-s3c24xx/regs-udc.h
145266 ===================================================================
145267 --- linux-2.6.28.orig/include/asm-arm/plat-s3c24xx/regs-udc.h   2008-12-25 00:26:37.000000000 +0100
145268 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
145269 @@ -1,153 +0,0 @@
145270 -/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
145271 - *
145272 - * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
145273 - *
145274 - * This include file is free software; you can redistribute it and/or
145275 - * modify it under the terms of the GNU General Public License as
145276 - * published by the Free Software Foundation; either version 2 of
145277 - * the License, or (at your option) any later version.
145278 -*/
145279 -
145280 -#ifndef __ASM_ARCH_REGS_UDC_H
145281 -#define __ASM_ARCH_REGS_UDC_H
145282 -
145283 -#define S3C2410_USBDREG(x) (x)
145284 -
145285 -#define S3C2410_UDC_FUNC_ADDR_REG      S3C2410_USBDREG(0x0140)
145286 -#define S3C2410_UDC_PWR_REG            S3C2410_USBDREG(0x0144)
145287 -#define S3C2410_UDC_EP_INT_REG         S3C2410_USBDREG(0x0148)
145288 -
145289 -#define S3C2410_UDC_USB_INT_REG                S3C2410_USBDREG(0x0158)
145290 -#define S3C2410_UDC_EP_INT_EN_REG      S3C2410_USBDREG(0x015c)
145291 -
145292 -#define S3C2410_UDC_USB_INT_EN_REG     S3C2410_USBDREG(0x016c)
145293 -
145294 -#define S3C2410_UDC_FRAME_NUM1_REG     S3C2410_USBDREG(0x0170)
145295 -#define S3C2410_UDC_FRAME_NUM2_REG     S3C2410_USBDREG(0x0174)
145296 -
145297 -#define S3C2410_UDC_EP0_FIFO_REG       S3C2410_USBDREG(0x01c0)
145298 -#define S3C2410_UDC_EP1_FIFO_REG       S3C2410_USBDREG(0x01c4)
145299 -#define S3C2410_UDC_EP2_FIFO_REG       S3C2410_USBDREG(0x01c8)
145300 -#define S3C2410_UDC_EP3_FIFO_REG       S3C2410_USBDREG(0x01cc)
145301 -#define S3C2410_UDC_EP4_FIFO_REG       S3C2410_USBDREG(0x01d0)
145302 -
145303 -#define S3C2410_UDC_EP1_DMA_CON                S3C2410_USBDREG(0x0200)
145304 -#define S3C2410_UDC_EP1_DMA_UNIT       S3C2410_USBDREG(0x0204)
145305 -#define S3C2410_UDC_EP1_DMA_FIFO       S3C2410_USBDREG(0x0208)
145306 -#define S3C2410_UDC_EP1_DMA_TTC_L      S3C2410_USBDREG(0x020c)
145307 -#define S3C2410_UDC_EP1_DMA_TTC_M      S3C2410_USBDREG(0x0210)
145308 -#define S3C2410_UDC_EP1_DMA_TTC_H      S3C2410_USBDREG(0x0214)
145309 -
145310 -#define S3C2410_UDC_EP2_DMA_CON                S3C2410_USBDREG(0x0218)
145311 -#define S3C2410_UDC_EP2_DMA_UNIT       S3C2410_USBDREG(0x021c)
145312 -#define S3C2410_UDC_EP2_DMA_FIFO       S3C2410_USBDREG(0x0220)
145313 -#define S3C2410_UDC_EP2_DMA_TTC_L      S3C2410_USBDREG(0x0224)
145314 -#define S3C2410_UDC_EP2_DMA_TTC_M      S3C2410_USBDREG(0x0228)
145315 -#define S3C2410_UDC_EP2_DMA_TTC_H      S3C2410_USBDREG(0x022c)
145316 -
145317 -#define S3C2410_UDC_EP3_DMA_CON                S3C2410_USBDREG(0x0240)
145318 -#define S3C2410_UDC_EP3_DMA_UNIT       S3C2410_USBDREG(0x0244)
145319 -#define S3C2410_UDC_EP3_DMA_FIFO       S3C2410_USBDREG(0x0248)
145320 -#define S3C2410_UDC_EP3_DMA_TTC_L      S3C2410_USBDREG(0x024c)
145321 -#define S3C2410_UDC_EP3_DMA_TTC_M      S3C2410_USBDREG(0x0250)
145322 -#define S3C2410_UDC_EP3_DMA_TTC_H      S3C2410_USBDREG(0x0254)
145323 -
145324 -#define S3C2410_UDC_EP4_DMA_CON                S3C2410_USBDREG(0x0258)
145325 -#define S3C2410_UDC_EP4_DMA_UNIT       S3C2410_USBDREG(0x025c)
145326 -#define S3C2410_UDC_EP4_DMA_FIFO       S3C2410_USBDREG(0x0260)
145327 -#define S3C2410_UDC_EP4_DMA_TTC_L      S3C2410_USBDREG(0x0264)
145328 -#define S3C2410_UDC_EP4_DMA_TTC_M      S3C2410_USBDREG(0x0268)
145329 -#define S3C2410_UDC_EP4_DMA_TTC_H      S3C2410_USBDREG(0x026c)
145330 -
145331 -#define S3C2410_UDC_INDEX_REG          S3C2410_USBDREG(0x0178)
145332 -
145333 -/* indexed registers */
145334 -
145335 -#define S3C2410_UDC_MAXP_REG           S3C2410_USBDREG(0x0180)
145336 -
145337 -#define S3C2410_UDC_EP0_CSR_REG                S3C2410_USBDREG(0x0184)
145338 -
145339 -#define S3C2410_UDC_IN_CSR1_REG                S3C2410_USBDREG(0x0184)
145340 -#define S3C2410_UDC_IN_CSR2_REG                S3C2410_USBDREG(0x0188)
145341 -
145342 -#define S3C2410_UDC_OUT_CSR1_REG       S3C2410_USBDREG(0x0190)
145343 -#define S3C2410_UDC_OUT_CSR2_REG       S3C2410_USBDREG(0x0194)
145344 -#define S3C2410_UDC_OUT_FIFO_CNT1_REG  S3C2410_USBDREG(0x0198)
145345 -#define S3C2410_UDC_OUT_FIFO_CNT2_REG  S3C2410_USBDREG(0x019c)
145346 -
145347 -#define S3C2410_UDC_FUNCADDR_UPDATE    (1<<7)
145348 -
145349 -#define S3C2410_UDC_PWR_ISOUP          (1<<7) // R/W
145350 -#define S3C2410_UDC_PWR_RESET          (1<<3) // R
145351 -#define S3C2410_UDC_PWR_RESUME         (1<<2) // R/W
145352 -#define S3C2410_UDC_PWR_SUSPEND                (1<<1) // R
145353 -#define S3C2410_UDC_PWR_ENSUSPEND      (1<<0) // R/W
145354 -
145355 -#define S3C2410_UDC_PWR_DEFAULT                0x00
145356 -
145357 -#define S3C2410_UDC_INT_EP4            (1<<4) // R/W (clear only)
145358 -#define S3C2410_UDC_INT_EP3            (1<<3) // R/W (clear only)
145359 -#define S3C2410_UDC_INT_EP2            (1<<2) // R/W (clear only)
145360 -#define S3C2410_UDC_INT_EP1            (1<<1) // R/W (clear only)
145361 -#define S3C2410_UDC_INT_EP0            (1<<0) // R/W (clear only)
145362 -
145363 -#define S3C2410_UDC_USBINT_RESET       (1<<2) // R/W (clear only)
145364 -#define S3C2410_UDC_USBINT_RESUME      (1<<1) // R/W (clear only)
145365 -#define S3C2410_UDC_USBINT_SUSPEND     (1<<0) // R/W (clear only)
145366 -
145367 -#define S3C2410_UDC_INTE_EP4           (1<<4) // R/W
145368 -#define S3C2410_UDC_INTE_EP3           (1<<3) // R/W
145369 -#define S3C2410_UDC_INTE_EP2           (1<<2) // R/W
145370 -#define S3C2410_UDC_INTE_EP1           (1<<1) // R/W
145371 -#define S3C2410_UDC_INTE_EP0           (1<<0) // R/W
145372 -
145373 -#define S3C2410_UDC_USBINTE_RESET      (1<<2) // R/W
145374 -#define S3C2410_UDC_USBINTE_SUSPEND    (1<<0) // R/W
145375 -
145376 -
145377 -#define S3C2410_UDC_INDEX_EP0          (0x00)
145378 -#define S3C2410_UDC_INDEX_EP1          (0x01) // ??
145379 -#define S3C2410_UDC_INDEX_EP2          (0x02) // ??
145380 -#define S3C2410_UDC_INDEX_EP3          (0x03) // ??
145381 -#define S3C2410_UDC_INDEX_EP4          (0x04) // ??
145382 -
145383 -#define S3C2410_UDC_ICSR1_CLRDT                (1<<6) // R/W
145384 -#define S3C2410_UDC_ICSR1_SENTSTL      (1<<5) // R/W (clear only)
145385 -#define S3C2410_UDC_ICSR1_SENDSTL      (1<<4) // R/W
145386 -#define S3C2410_UDC_ICSR1_FFLUSH       (1<<3) // W   (set only)
145387 -#define S3C2410_UDC_ICSR1_UNDRUN       (1<<2) // R/W (clear only)
145388 -#define S3C2410_UDC_ICSR1_PKTRDY       (1<<0) // R/W (set only)
145389 -
145390 -#define S3C2410_UDC_ICSR2_AUTOSET      (1<<7) // R/W
145391 -#define S3C2410_UDC_ICSR2_ISO          (1<<6) // R/W
145392 -#define S3C2410_UDC_ICSR2_MODEIN       (1<<5) // R/W
145393 -#define S3C2410_UDC_ICSR2_DMAIEN       (1<<4) // R/W
145394 -
145395 -#define S3C2410_UDC_OCSR1_CLRDT                (1<<7) // R/W
145396 -#define S3C2410_UDC_OCSR1_SENTSTL      (1<<6) // R/W (clear only)
145397 -#define S3C2410_UDC_OCSR1_SENDSTL      (1<<5) // R/W
145398 -#define S3C2410_UDC_OCSR1_FFLUSH       (1<<4) // R/W
145399 -#define S3C2410_UDC_OCSR1_DERROR       (1<<3) // R
145400 -#define S3C2410_UDC_OCSR1_OVRRUN       (1<<2) // R/W (clear only)
145401 -#define S3C2410_UDC_OCSR1_PKTRDY       (1<<0) // R/W (clear only)
145402 -
145403 -#define S3C2410_UDC_OCSR2_AUTOCLR      (1<<7) // R/W
145404 -#define S3C2410_UDC_OCSR2_ISO          (1<<6) // R/W
145405 -#define S3C2410_UDC_OCSR2_DMAIEN       (1<<5) // R/W
145406 -
145407 -#define S3C2410_UDC_EP0_CSR_OPKRDY     (1<<0)
145408 -#define S3C2410_UDC_EP0_CSR_IPKRDY     (1<<1)
145409 -#define S3C2410_UDC_EP0_CSR_SENTSTL    (1<<2)
145410 -#define S3C2410_UDC_EP0_CSR_DE         (1<<3)
145411 -#define S3C2410_UDC_EP0_CSR_SE         (1<<4)
145412 -#define S3C2410_UDC_EP0_CSR_SENDSTL    (1<<5)
145413 -#define S3C2410_UDC_EP0_CSR_SOPKTRDY   (1<<6)
145414 -#define S3C2410_UDC_EP0_CSR_SSE        (1<<7)
145415 -
145416 -#define S3C2410_UDC_MAXP_8             (1<<0)
145417 -#define S3C2410_UDC_MAXP_16            (1<<1)
145418 -#define S3C2410_UDC_MAXP_32            (1<<2)
145419 -#define S3C2410_UDC_MAXP_64            (1<<3)
145420 -
145421 -
145422 -#endif
145423 Index: linux-2.6.28/include/asm-arm/plat-s3c24xx/udc.h
145424 ===================================================================
145425 --- linux-2.6.28.orig/include/asm-arm/plat-s3c24xx/udc.h        2008-12-25 00:26:37.000000000 +0100
145426 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
145427 @@ -1,36 +0,0 @@
145428 -/* arch/arm/mach-s3c2410/include/mach/udc.h
145429 - *
145430 - * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
145431 - *
145432 - *
145433 - * This program is free software; you can redistribute it and/or modify
145434 - * it under the terms of the GNU General Public License version 2 as
145435 - * published by the Free Software Foundation.
145436 - *
145437 - *
145438 - *  Changelog:
145439 - *     14-Mar-2005     RTP     Created file
145440 - *     02-Aug-2005     RTP     File rename
145441 - *     07-Sep-2005     BJD     Minor cleanups, changed cmd to enum
145442 - *     18-Jan-2007     HMW     Add per-platform vbus_draw function
145443 -*/
145444 -
145445 -#ifndef __ASM_ARM_ARCH_UDC_H
145446 -#define __ASM_ARM_ARCH_UDC_H
145447 -
145448 -enum s3c2410_udc_cmd_e {
145449 -       S3C2410_UDC_P_ENABLE    = 1,    /* Pull-up enable        */
145450 -       S3C2410_UDC_P_DISABLE   = 2,    /* Pull-up disable       */
145451 -       S3C2410_UDC_P_RESET     = 3,    /* UDC reset, in case of */
145452 -};
145453 -
145454 -struct s3c2410_udc_mach_info {
145455 -       void    (*udc_command)(enum s3c2410_udc_cmd_e);
145456 -       void    (*vbus_draw)(unsigned int ma);
145457 -       unsigned int vbus_pin;
145458 -       unsigned char vbus_pin_inverted;
145459 -};
145460 -
145461 -extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
145462 -
145463 -#endif /* __ASM_ARM_ARCH_UDC_H */
145464 Index: linux-2.6.28/include/linux/android_aid.h
145465 ===================================================================
145466 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
145467 +++ linux-2.6.28/include/linux/android_aid.h    2009-01-02 00:01:57.000000000 +0100
145468 @@ -0,0 +1,25 @@
145469 +/* include/linux/android_aid.h
145470 + *
145471 + * Copyright (C) 2008 Google, Inc.
145472 + *
145473 + * This software is licensed under the terms of the GNU General Public
145474 + * License version 2, as published by the Free Software Foundation, and
145475 + * may be copied, distributed, and modified under those terms.
145476 + *
145477 + * This program is distributed in the hope that it will be useful,
145478 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
145479 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145480 + * GNU General Public License for more details.
145481 + *
145482 + */
145483 +
145484 +#ifndef _LINUX_ANDROID_AID_H
145485 +#define _LINUX_ANDROID_AID_H
145486 +
145487 +/* AIDs that the kernel treats differently */
145488 +#define AID_NET_BT_ADMIN 3001
145489 +#define AID_NET_BT       3002
145490 +#define AID_INET         3003
145491 +#define AID_NET_RAW      3004
145492 +
145493 +#endif
145494 Index: linux-2.6.28/include/linux/android_alarm.h
145495 ===================================================================
145496 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
145497 +++ linux-2.6.28/include/linux/android_alarm.h  2009-01-02 00:01:57.000000000 +0100
145498 @@ -0,0 +1,59 @@
145499 +/* include/linux/android_alarm.h
145500 + *
145501 + * Copyright (C) 2006-2007 Google, Inc.
145502 + *
145503 + * This software is licensed under the terms of the GNU General Public
145504 + * License version 2, as published by the Free Software Foundation, and
145505 + * may be copied, distributed, and modified under those terms.
145506 + *
145507 + * This program is distributed in the hope that it will be useful,
145508 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
145509 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145510 + * GNU General Public License for more details.
145511 + *
145512 + */
145513 +
145514 +#ifndef _LINUX_ANDROID_ALARM_H
145515 +#define _LINUX_ANDROID_ALARM_H
145516 +
145517 +#include <asm/ioctl.h>
145518 +#include <linux/time.h>
145519 +
145520 +typedef enum {
145521 +       /* return code bit numbers or set alarm arg */
145522 +       ANDROID_ALARM_RTC_WAKEUP,
145523 +       ANDROID_ALARM_RTC,
145524 +       ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
145525 +       ANDROID_ALARM_ELAPSED_REALTIME,
145526 +       ANDROID_ALARM_SYSTEMTIME,
145527 +
145528 +       ANDROID_ALARM_TYPE_COUNT,
145529 +
145530 +       /* return code bit numbers */
145531 +       /* ANDROID_ALARM_TIME_CHANGE = 16 */
145532 +} android_alarm_type_t;
145533 +
145534 +typedef enum {
145535 +       ANDROID_ALARM_RTC_WAKEUP_MASK = 1U << ANDROID_ALARM_RTC_WAKEUP,
145536 +       ANDROID_ALARM_RTC_MASK = 1U << ANDROID_ALARM_RTC,
145537 +       ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK = 1U << ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
145538 +       ANDROID_ALARM_ELAPSED_REALTIME_MASK = 1U << ANDROID_ALARM_ELAPSED_REALTIME,
145539 +       ANDROID_ALARM_SYSTEMTIME_MASK = 1U << ANDROID_ALARM_SYSTEMTIME,
145540 +       ANDROID_ALARM_TIME_CHANGE_MASK = 1U << 16
145541 +} android_alarm_return_flags_t;
145542 +
145543 +/* Disable alarm */
145544 +#define ANDROID_ALARM_CLEAR(type)           _IO('a', 0 | ((type) << 4))
145545 +
145546 +/* Ack last alarm and wait for next */
145547 +#define ANDROID_ALARM_WAIT                  _IO('a', 1)
145548 +
145549 +/* Set alarm */
145550 +#define ANDROID_ALARM_SET(type)             _IOW('a', 2 | ((type) << 4), struct timespec)
145551 +#define ANDROID_ALARM_SET_AND_WAIT(type)    _IOW('a', 3 | ((type) << 4), struct timespec)
145552 +#define ANDROID_ALARM_GET_TIME(type)        _IOW('a', 4 | ((type) << 4), struct timespec)
145553 +#define ANDROID_ALARM_SET_RTC               _IOW('a', 5, struct timespec)
145554 +#define ANDROID_ALARM_BASE_CMD(cmd) (cmd & ~(_IOC(0, 0, 0xf0, 0)))
145555 +#define ANDROID_ALARM_IOCTL_TO_TYPE(cmd) (_IOC_NR(cmd) >> 4)
145556 +
145557 +#endif
145558 Index: linux-2.6.28/include/linux/android_power.h
145559 ===================================================================
145560 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
145561 +++ linux-2.6.28/include/linux/android_power.h  2009-01-02 00:01:57.000000000 +0100
145562 @@ -0,0 +1,98 @@
145563 +/* include/linux/android_power.h
145564 + *
145565 + * Copyright (C) 2007-2008 Google, Inc.
145566 + *
145567 + * This software is licensed under the terms of the GNU General Public
145568 + * License version 2, as published by the Free Software Foundation, and
145569 + * may be copied, distributed, and modified under those terms.
145570 + *
145571 + * This program is distributed in the hope that it will be useful,
145572 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
145573 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145574 + * GNU General Public License for more details.
145575 + *
145576 + */
145577 +
145578 +#ifndef _LINUX_ANDROID_POWER_H
145579 +#define _LINUX_ANDROID_POWER_H
145580 +
145581 +#include <linux/list.h>
145582 +#include <linux/ktime.h>
145583 +
145584 +typedef struct
145585 +{
145586 +       struct list_head    link;
145587 +       int                 flags;
145588 +       const char         *name;
145589 +       int                 expires;
145590 +#ifdef CONFIG_ANDROID_POWER_STAT
145591 +       struct {
145592 +               int             count;
145593 +               int             expire_count;
145594 +               ktime_t         total_time;
145595 +               ktime_t         max_time;
145596 +               ktime_t         last_time;
145597 +       } stat;
145598 +#endif
145599 +} android_suspend_lock_t;
145600 +
145601 +#if 0 /* none of these flags are implemented */
145602 +#define ANDROID_SUSPEND_LOCK_FLAG_COUNTED (1U << 0)
145603 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_READABLE (1U << 1)
145604 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_SET (1U << 2)
145605 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_CLEAR (1U << 3)
145606 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_INC (1U << 4)
145607 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_DEC (1U << 5)
145608 +#define ANDROID_SUSPEND_LOCK_FLAG_USER_VISIBLE_MASK (0x1fU << 1)
145609 +#endif
145610 +#define ANDROID_SUSPEND_LOCK_AUTO_EXPIRE (1U << 6)
145611 +#define ANDROID_SUSPEND_LOCK_ACTIVE      (1U << 7)
145612 +
145613 +enum {
145614 +       ANDROID_STOPPED_DRAWING,
145615 +       ANDROID_REQUEST_STOP_DRAWING,
145616 +       ANDROID_DRAWING_OK,
145617 +};
145618 +
145619 +enum {
145620 +       ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN = 50,
145621 +       ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH = 100,
145622 +       ANDROID_EARLY_SUSPEND_LEVEL_DISABLE_FB = 150,
145623 +};
145624 +typedef struct android_early_suspend android_early_suspend_t;
145625 +struct android_early_suspend
145626 +{
145627 +       struct list_head link;
145628 +       int level;
145629 +       void (*suspend)(android_early_suspend_t *h);
145630 +       void (*resume)(android_early_suspend_t *h);
145631 +};
145632 +
145633 +typedef enum {
145634 +       ANDROID_CHARGING_STATE_UNKNOWN,
145635 +       ANDROID_CHARGING_STATE_DISCHARGE,
145636 +       ANDROID_CHARGING_STATE_MAINTAIN, /* or trickle */
145637 +       ANDROID_CHARGING_STATE_SLOW,
145638 +       ANDROID_CHARGING_STATE_NORMAL,
145639 +       ANDROID_CHARGING_STATE_FAST,
145640 +       ANDROID_CHARGING_STATE_OVERHEAT
145641 +} android_charging_state_t;
145642 +
145643 +/* android_suspend_lock_t *android_allocate_suspend_lock(const char *debug_name); */
145644 +/* void android_free_suspend_lock(android_suspend_lock_t *lock); */
145645 +int android_init_suspend_lock(android_suspend_lock_t *lock);
145646 +void android_uninit_suspend_lock(android_suspend_lock_t *lock);
145647 +void android_lock_idle(android_suspend_lock_t *lock);
145648 +void android_lock_idle_auto_expire(android_suspend_lock_t *lock, int timeout);
145649 +void android_lock_suspend(android_suspend_lock_t *lock);
145650 +void android_lock_suspend_auto_expire(android_suspend_lock_t *lock, int timeout);
145651 +void android_unlock_suspend(android_suspend_lock_t *lock);
145652 +
145653 +int android_power_is_driver_suspended(void);
145654 +int android_power_is_low_power_idle_ok(void);
145655 +
145656 +void android_register_early_suspend(android_early_suspend_t *handler);
145657 +void android_unregister_early_suspend(android_early_suspend_t *handler);
145658 +
145659 +#endif
145660 +
145661 Index: linux-2.6.28/include/linux/android_timed_gpio.h
145662 ===================================================================
145663 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
145664 +++ linux-2.6.28/include/linux/android_timed_gpio.h     2009-01-02 00:01:57.000000000 +0100
145665 @@ -0,0 +1,31 @@
145666 +/* include/linux/android_timed_gpio.h
145667 + *
145668 + * Copyright (C) 2008 Google, Inc.
145669 + *
145670 + * This software is licensed under the terms of the GNU General Public
145671 + * License version 2, as published by the Free Software Foundation, and
145672 + * may be copied, distributed, and modified under those terms.
145673 + *
145674 + * This program is distributed in the hope that it will be useful,
145675 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
145676 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145677 + * GNU General Public License for more details.
145678 + *
145679 +*/
145680 +
145681 +#ifndef _LINUX_ANDROID_TIMED_GPIO_H
145682 +#define _LINUX_ANDROID_TIMED_GPIO_H
145683 +
145684 +struct timed_gpio {
145685 +       const char *name;
145686 +       unsigned        gpio;
145687 +       int     max_timeout;
145688 +       u8              active_low;
145689 +};
145690 +
145691 +struct timed_gpio_platform_data {
145692 +       int             num_gpios;
145693 +       struct timed_gpio *gpios;
145694 +};
145695 +
145696 +#endif
145697 Index: linux-2.6.28/include/linux/ashmem.h
145698 ===================================================================
145699 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
145700 +++ linux-2.6.28/include/linux/ashmem.h 2009-01-02 00:01:57.000000000 +0100
145701 @@ -0,0 +1,48 @@
145702 +/*
145703 + * include/linux/ashmem.h
145704 + *
145705 + * Copyright 2008 Google Inc.
145706 + * Author: Robert Love
145707 + *
145708 + * This file is dual licensed.  It may be redistributed and/or modified
145709 + * under the terms of the Apache 2.0 License OR version 2 of the GNU
145710 + * General Public License.
145711 + */
145712 +
145713 +#ifndef _LINUX_ASHMEM_H
145714 +#define _LINUX_ASHMEM_H
145715 +
145716 +#include <linux/limits.h>
145717 +#include <linux/ioctl.h>
145718 +
145719 +#define ASHMEM_NAME_LEN                256
145720 +
145721 +#define ASHMEM_NAME_DEF                "dev/ashmem"
145722 +
145723 +/* Return values from ASHMEM_PIN: Was the mapping purged while unpinned? */
145724 +#define ASHMEM_NOT_PURGED      0
145725 +#define ASHMEM_WAS_PURGED      1
145726 +
145727 +/* Return values from ASHMEM_GET_PIN_STATUS: Is the mapping pinned? */
145728 +#define ASHMEM_IS_UNPINNED     0
145729 +#define ASHMEM_IS_PINNED       1
145730 +
145731 +struct ashmem_pin {
145732 +       __u32 offset;   /* offset into region, in bytes, page-aligned */
145733 +       __u32 len;      /* length forward from offset, in bytes, page-aligned */
145734 +};
145735 +
145736 +#define __ASHMEMIOC            0x77
145737 +
145738 +#define ASHMEM_SET_NAME                _IOW(__ASHMEMIOC, 1, char[ASHMEM_NAME_LEN])
145739 +#define ASHMEM_GET_NAME                _IOR(__ASHMEMIOC, 2, char[ASHMEM_NAME_LEN])
145740 +#define ASHMEM_SET_SIZE                _IOW(__ASHMEMIOC, 3, size_t)
145741 +#define ASHMEM_GET_SIZE                _IO(__ASHMEMIOC, 4)
145742 +#define ASHMEM_SET_PROT_MASK   _IOW(__ASHMEMIOC, 5, unsigned long)
145743 +#define ASHMEM_GET_PROT_MASK   _IO(__ASHMEMIOC, 6)
145744 +#define ASHMEM_PIN             _IOW(__ASHMEMIOC, 7, struct ashmem_pin)
145745 +#define ASHMEM_UNPIN           _IOW(__ASHMEMIOC, 8, struct ashmem_pin)
145746 +#define ASHMEM_GET_PIN_STATUS  _IO(__ASHMEMIOC, 9)
145747 +#define ASHMEM_PURGE_ALL_CACHES        _IO(__ASHMEMIOC, 10)
145748 +
145749 +#endif /* _LINUX_ASHMEM_H */
145750 Index: linux-2.6.28/include/linux/binder.h
145751 ===================================================================
145752 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
145753 +++ linux-2.6.28/include/linux/binder.h 2009-01-02 00:01:57.000000000 +0100
145754 @@ -0,0 +1,330 @@
145755 +/*
145756 + * Copyright (C) 2008 Google, Inc.
145757 + *
145758 + * Based on, but no longer compatible with, the original
145759 + * OpenBinder.org binder driver interface, which is:
145760 + *
145761 + * Copyright (c) 2005 Palmsource, Inc.
145762 + *
145763 + * This software is licensed under the terms of the GNU General Public
145764 + * License version 2, as published by the Free Software Foundation, and
145765 + * may be copied, distributed, and modified under those terms.
145766 + *
145767 + * This program is distributed in the hope that it will be useful,
145768 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
145769 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
145770 + * GNU General Public License for more details.
145771 + *
145772 + */
145773 +
145774 +#ifndef _LINUX_BINDER_H
145775 +#define _LINUX_BINDER_H
145776 +
145777 +#include <linux/ioctl.h>
145778 +
145779 +#define B_PACK_CHARS(c1, c2, c3, c4) \
145780 +       ((((c1)<<24)) | (((c2)<<16)) | (((c3)<<8)) | (c4))
145781 +#define B_TYPE_LARGE 0x85
145782 +
145783 +enum {
145784 +       BINDER_TYPE_BINDER      = B_PACK_CHARS('s', 'b', '*', B_TYPE_LARGE),
145785 +       BINDER_TYPE_WEAK_BINDER = B_PACK_CHARS('w', 'b', '*', B_TYPE_LARGE),
145786 +       BINDER_TYPE_HANDLE      = B_PACK_CHARS('s', 'h', '*', B_TYPE_LARGE),
145787 +       BINDER_TYPE_WEAK_HANDLE = B_PACK_CHARS('w', 'h', '*', B_TYPE_LARGE),
145788 +       BINDER_TYPE_FD          = B_PACK_CHARS('f', 'd', '*', B_TYPE_LARGE),
145789 +};
145790 +
145791 +enum {
145792 +       FLAT_BINDER_FLAG_PRIORITY_MASK = 0xff,
145793 +       FLAT_BINDER_FLAG_ACCEPTS_FDS = 0x100,
145794 +};
145795 +
145796 +/*
145797 + * This is the flattened representation of a Binder object for transfer
145798 + * between processes.  The 'offsets' supplied as part of a binder transaction
145799 + * contains offsets into the data where these structures occur.  The Binder
145800 + * driver takes care of re-writing the structure type and data as it moves
145801 + * between processes.
145802 + */
145803 +struct flat_binder_object {
145804 +       /* 8 bytes for large_flat_header. */
145805 +       unsigned long           type;
145806 +       unsigned long           flags;
145807 +
145808 +       /* 8 bytes of data. */
145809 +       union {
145810 +               void            *binder;        /* local object */
145811 +               signed long     handle;         /* remote object */
145812 +       };
145813 +
145814 +       /* extra data associated with local object */
145815 +       void                    *cookie;
145816 +};
145817 +
145818 +/*
145819 + * On 64-bit platforms where user code may run in 32-bits the driver must
145820 + * translate the buffer (and local binder) addresses apropriately.
145821 + */
145822 +
145823 +struct binder_write_read {
145824 +       signed long     write_size;     /* bytes to write */
145825 +       signed long     write_consumed; /* bytes consumed by driver */
145826 +       unsigned long   write_buffer;
145827 +       signed long     read_size;      /* bytes to read */
145828 +       signed long     read_consumed;  /* bytes consumed by driver */
145829 +       unsigned long   read_buffer;
145830 +};
145831 +
145832 +/* Use with BINDER_VERSION, driver fills in fields. */
145833 +struct binder_version {
145834 +       /* driver protocol version -- increment with incompatible change */
145835 +       signed long     protocol_version;
145836 +};
145837 +
145838 +/* This is the current protocol version. */
145839 +#define BINDER_CURRENT_PROTOCOL_VERSION 7
145840 +
145841 +#define BINDER_WRITE_READ              _IOWR('b', 1, struct binder_write_read)
145842 +#define        BINDER_SET_IDLE_TIMEOUT         _IOW('b', 3, int64_t)
145843 +#define        BINDER_SET_MAX_THREADS          _IOW('b', 5, size_t)
145844 +#define        BINDER_SET_IDLE_PRIORITY        _IOW('b', 6, int)
145845 +#define        BINDER_SET_CONTEXT_MGR          _IOW('b', 7, int)
145846 +#define        BINDER_THREAD_EXIT              _IOW('b', 8, int)
145847 +#define BINDER_VERSION                 _IOWR('b', 9, struct binder_version)
145848 +
145849 +/*
145850 + * NOTE: Two special error codes you should check for when calling
145851 + * in to the driver are:
145852 + *
145853 + * EINTR -- The operation has been interupted.  This should be
145854 + * handled by retrying the ioctl() until a different error code
145855 + * is returned.
145856 + *
145857 + * ECONNREFUSED -- The driver is no longer accepting operations
145858 + * from your process.  That is, the process is being destroyed.
145859 + * You should handle this by exiting from your process.  Note
145860 + * that once this error code is returned, all further calls to
145861 + * the driver from any thread will return this same code.
145862 + */
145863 +
145864 +enum transaction_flags {
145865 +       TF_ONE_WAY      = 0x01, /* this is a one-way call: async, no return */
145866 +       TF_ROOT_OBJECT  = 0x04, /* contents are the component's root object */
145867 +       TF_STATUS_CODE  = 0x08, /* contents are a 32-bit status code */
145868 +       TF_ACCEPT_FDS   = 0x10, /* allow replies with file descriptors */
145869 +};
145870 +
145871 +struct binder_transaction_data {
145872 +       /* The first two are only used for bcTRANSACTION and brTRANSACTION,
145873 +        * identifying the target and contents of the transaction.
145874 +        */
145875 +       union {
145876 +               size_t  handle; /* target descriptor of command transaction */
145877 +               void    *ptr;   /* target descriptor of return transaction */
145878 +       } target;
145879 +       void            *cookie;        /* target object cookie */
145880 +       unsigned int    code;           /* transaction command */
145881 +
145882 +       /* General information about the transaction. */
145883 +       unsigned int    flags;
145884 +       pid_t           sender_pid;
145885 +       uid_t           sender_euid;
145886 +       size_t          data_size;      /* number of bytes of data */
145887 +       size_t          offsets_size;   /* number of bytes of offsets */
145888 +
145889 +       /* If this transaction is inline, the data immediately
145890 +        * follows here; otherwise, it ends with a pointer to
145891 +        * the data buffer.
145892 +        */
145893 +       union {
145894 +               struct {
145895 +                       /* transaction data */
145896 +                       const void      *buffer;
145897 +                       /* offsets from buffer to flat_binder_object structs */
145898 +                       const void      *offsets;
145899 +               } ptr;
145900 +               uint8_t buf[8];
145901 +       } data;
145902 +};
145903 +
145904 +struct binder_ptr_cookie {
145905 +       void *ptr;
145906 +       void *cookie;
145907 +};
145908 +
145909 +struct binder_pri_desc {
145910 +       int priority;
145911 +       int desc;
145912 +};
145913 +
145914 +struct binder_pri_ptr_cookie {
145915 +       int priority;
145916 +       void *ptr;
145917 +       void *cookie;
145918 +};
145919 +
145920 +enum BinderDriverReturnProtocol {
145921 +       BR_ERROR = _IOR('r', 0, int),
145922 +       /*
145923 +        * int: error code
145924 +        */
145925 +
145926 +       BR_OK = _IO('r', 1),
145927 +       /* No parameters! */
145928 +
145929 +       BR_TRANSACTION = _IOR('r', 2, struct binder_transaction_data),
145930 +       BR_REPLY = _IOR('r', 3, struct binder_transaction_data),
145931 +       /*
145932 +        * binder_transaction_data: the received command.
145933 +        */
145934 +
145935 +       BR_ACQUIRE_RESULT = _IOR('r', 4, int),
145936 +       /*
145937 +        * not currently supported
145938 +        * int: 0 if the last bcATTEMPT_ACQUIRE was not successful.
145939 +        * Else the remote object has acquired a primary reference.
145940 +        */
145941 +
145942 +       BR_DEAD_REPLY = _IO('r', 5),
145943 +       /*
145944 +        * The target of the last transaction (either a bcTRANSACTION or
145945 +        * a bcATTEMPT_ACQUIRE) is no longer with us.  No parameters.
145946 +        */
145947 +
145948 +       BR_TRANSACTION_COMPLETE = _IO('r', 6),
145949 +       /*
145950 +        * No parameters... always refers to the last transaction requested
145951 +        * (including replies).  Note that this will be sent even for
145952 +        * asynchronous transactions.
145953 +        */
145954 +
145955 +       BR_INCREFS = _IOR('r', 7, struct binder_ptr_cookie),
145956 +       BR_ACQUIRE = _IOR('r', 8, struct binder_ptr_cookie),
145957 +       BR_RELEASE = _IOR('r', 9, struct binder_ptr_cookie),
145958 +       BR_DECREFS = _IOR('r', 10, struct binder_ptr_cookie),
145959 +       /*
145960 +        * void *:      ptr to binder
145961 +        * void *: cookie for binder
145962 +        */
145963 +
145964 +       BR_ATTEMPT_ACQUIRE = _IOR('r', 11, struct binder_pri_ptr_cookie),
145965 +       /*
145966 +        * not currently supported
145967 +        * int: priority
145968 +        * void *: ptr to binder
145969 +        * void *: cookie for binder
145970 +        */
145971 +
145972 +       BR_NOOP = _IO('r', 12),
145973 +       /*
145974 +        * No parameters.  Do nothing and examine the next command.  It exists
145975 +        * primarily so that we can replace it with a BR_SPAWN_LOOPER command.
145976 +        */
145977 +
145978 +       BR_SPAWN_LOOPER = _IO('r', 13),
145979 +       /*
145980 +        * No parameters.  The driver has determined that a process has no
145981 +        * threads waiting to service incomming transactions.  When a process
145982 +        * receives this command, it must spawn a new service thread and
145983 +        * register it via bcENTER_LOOPER.
145984 +        */
145985 +
145986 +       BR_FINISHED = _IO('r', 14),
145987 +       /*
145988 +        * not currently supported
145989 +        * stop threadpool thread
145990 +        */
145991 +
145992 +       BR_DEAD_BINDER = _IOR('r', 15, void *),
145993 +       /*
145994 +        * void *: cookie
145995 +        */
145996 +       BR_CLEAR_DEATH_NOTIFICATION_DONE = _IOR('r', 16, void *),
145997 +       /*
145998 +        * void *: cookie
145999 +        */
146000 +
146001 +       BR_FAILED_REPLY = _IO('r', 17),
146002 +       /*
146003 +        * The the last transaction (either a bcTRANSACTION or
146004 +        * a bcATTEMPT_ACQUIRE) failed (e.g. out of memory).  No parameters.
146005 +        */
146006 +};
146007 +
146008 +enum BinderDriverCommandProtocol {
146009 +       BC_TRANSACTION = _IOW('c', 0, struct binder_transaction_data),
146010 +       BC_REPLY = _IOW('c', 1, struct binder_transaction_data),
146011 +       /*
146012 +        * binder_transaction_data: the sent command.
146013 +        */
146014 +
146015 +       BC_ACQUIRE_RESULT = _IOW('c', 2, int),
146016 +       /*
146017 +        * not currently supported
146018 +        * int:  0 if the last BR_ATTEMPT_ACQUIRE was not successful.
146019 +        * Else you have acquired a primary reference on the object.
146020 +        */
146021 +
146022 +       BC_FREE_BUFFER = _IOW('c', 3, int),
146023 +       /*
146024 +        * void *: ptr to transaction data received on a read
146025 +        */
146026 +
146027 +       BC_INCREFS = _IOW('c', 4, int),
146028 +       BC_ACQUIRE = _IOW('c', 5, int),
146029 +       BC_RELEASE = _IOW('c', 6, int),
146030 +       BC_DECREFS = _IOW('c', 7, int),
146031 +       /*
146032 +        * int: descriptor
146033 +        */
146034 +
146035 +       BC_INCREFS_DONE = _IOW('c', 8, struct binder_ptr_cookie),
146036 +       BC_ACQUIRE_DONE = _IOW('c', 9, struct binder_ptr_cookie),
146037 +       /*
146038 +        * void *: ptr to binder
146039 +        * void *: cookie for binder
146040 +        */
146041 +
146042 +       BC_ATTEMPT_ACQUIRE = _IOW('c', 10, struct binder_pri_desc),
146043 +       /*
146044 +        * not currently supported
146045 +        * int: priority
146046 +        * int: descriptor
146047 +        */
146048 +
146049 +       BC_REGISTER_LOOPER = _IO('c', 11),
146050 +       /*
146051 +        * No parameters.
146052 +        * Register a spawned looper thread with the device.
146053 +        */
146054 +
146055 +       BC_ENTER_LOOPER = _IO('c', 12),
146056 +       BC_EXIT_LOOPER = _IO('c', 13),
146057 +       /*
146058 +        * No parameters.
146059 +        * These two commands are sent as an application-level thread
146060 +        * enters and exits the binder loop, respectively.  They are
146061 +        * used so the binder can have an accurate count of the number
146062 +        * of looping threads it has available.
146063 +        */
146064 +
146065 +       BC_REQUEST_DEATH_NOTIFICATION = _IOW('c', 14, struct binder_ptr_cookie),
146066 +       /*
146067 +        * void *: ptr to binder
146068 +        * void *: cookie
146069 +        */
146070 +
146071 +       BC_CLEAR_DEATH_NOTIFICATION = _IOW('c', 15, struct binder_ptr_cookie),
146072 +       /*
146073 +        * void *: ptr to binder
146074 +        * void *: cookie
146075 +        */
146076 +
146077 +       BC_DEAD_BINDER_DONE = _IOW('c', 16, void *),
146078 +       /*
146079 +        * void *: cookie
146080 +        */
146081 +};
146082 +
146083 +#endif /* _LINUX_BINDER_H */
146084 +
146085 Index: linux-2.6.28/include/linux/bq27000_battery.h
146086 ===================================================================
146087 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146088 +++ linux-2.6.28/include/linux/bq27000_battery.h        2009-01-02 00:01:57.000000000 +0100
146089 @@ -0,0 +1,14 @@
146090 +#ifndef __BQ27000_BATTERY_H__
146091 +#define __BQ27000_BATTERY_H__
146092 +
146093 +struct bq27000_platform_data {
146094 +       const char      *name;
146095 +       int             rsense_mohms;
146096 +       int (*hdq_read)(int);
146097 +       int (*hdq_write)(int, u8);
146098 +       int (*hdq_initialized)(void);
146099 +       int (*get_charger_online_status)(void);
146100 +       int (*get_charger_active_status)(void);
146101 +};
146102 +
146103 +#endif
146104 Index: linux-2.6.28/include/linux/device.h
146105 ===================================================================
146106 --- linux-2.6.28.orig/include/linux/device.h    2008-12-25 00:26:37.000000000 +0100
146107 +++ linux-2.6.28/include/linux/device.h 2009-01-02 00:01:57.000000000 +0100
146108 @@ -48,6 +48,11 @@ extern int __must_check bus_create_file(
146109                                         struct bus_attribute *);
146110  extern void bus_remove_file(struct bus_type *, struct bus_attribute *);
146111
146112 +extern int __must_check bus_create_device_link(struct bus_type *bus,
146113 +                                              struct kobject *target,
146114 +                                              const char *name);
146115 +extern void bus_remove_device_link(struct bus_type *bus, const char *name);
146116 +
146117  struct bus_type {
146118         const char              *name;
146119         struct bus_attribute    *bus_attrs;
146120 Index: linux-2.6.28/include/linux/fb.h
146121 ===================================================================
146122 --- linux-2.6.28.orig/include/linux/fb.h        2008-12-25 00:26:37.000000000 +0100
146123 +++ linux-2.6.28/include/linux/fb.h     2009-01-02 00:01:57.000000000 +0100
146124 @@ -123,6 +123,7 @@ struct dentry;
146125  #define FB_ACCEL_TRIDENT_3DIMAGE 51    /* Trident 3DImage              */
146126  #define FB_ACCEL_TRIDENT_BLADE3D 52    /* Trident Blade3D              */
146127  #define FB_ACCEL_TRIDENT_BLADEXP 53    /* Trident BladeXP              */
146128 +#define FB_ACCEL_GLAMO         50      /* SMedia Glamo                 */
146129  #define FB_ACCEL_NEOMAGIC_NM2070 90    /* NeoMagic NM2070              */
146130  #define FB_ACCEL_NEOMAGIC_NM2090 91    /* NeoMagic NM2090              */
146131  #define FB_ACCEL_NEOMAGIC_NM2093 92    /* NeoMagic NM2093              */
146132 Index: linux-2.6.28/include/linux/glamofb.h
146133 ===================================================================
146134 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146135 +++ linux-2.6.28/include/linux/glamofb.h        2009-01-02 00:01:57.000000000 +0100
146136 @@ -0,0 +1,45 @@
146137 +#ifndef _LINUX_GLAMOFB_H
146138 +#define _LINUX_GLAMOFB_H
146139 +
146140 +#include <linux/spi/glamo.h>
146141 +
146142 +struct glamofb_val {
146143 +       unsigned int defval;
146144 +       unsigned int min;
146145 +       unsigned int max;
146146 +};
146147 +
146148 +struct glamo_core;
146149 +
146150 +struct glamofb_platform_data {
146151 +       int width, height;
146152 +       int pixclock;
146153 +       int left_margin, right_margin;
146154 +       int upper_margin, lower_margin;
146155 +       int hsync_len, vsync_len;
146156 +       int fb_mem_size;
146157 +
146158 +       struct glamofb_val xres;
146159 +       struct glamofb_val yres;
146160 +       struct glamofb_val bpp;
146161 +
146162 +       struct glamo_spi_info *spi_info;
146163 +       struct glamo_spigpio_info *spigpio_info;
146164 +       struct glamo_core *glamo;
146165 +
146166 +       struct platform_device *mmc_dev;
146167 +
146168 +       /* glamo mmc platform specific info */
146169 +       int             (*glamo_can_set_mci_power)(void);
146170 +
146171 +       /* glamo-mci asking if it should use the slow clock to card */
146172 +       int             (*glamo_mci_use_slow)(void);
146173 +       int             (*glamo_irq_is_wired)(void);
146174 +       void            (*glamo_external_reset)(int);
146175 +};
146176 +
146177 +int glamofb_cmd_mode(struct glamofb_handle *gfb, int on);
146178 +int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val);
146179 +void glamo_lcm_reset(int level);
146180 +
146181 +#endif
146182 Index: linux-2.6.28/include/linux/glamo-gpio.h
146183 ===================================================================
146184 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146185 +++ linux-2.6.28/include/linux/glamo-gpio.h     2009-01-02 00:01:57.000000000 +0100
146186 @@ -0,0 +1,99 @@
146187 +#ifndef __GLAMO_GPIO_H
146188 +#define __GLAMO_GPIO_H
146189 +
146190 +struct glamo_core;
146191 +
146192 +#define GLAMO_GPIO_BANKA       0x0000
146193 +#define GLAMO_GPIO_BANKB       0x1000
146194 +#define GLAMO_GPIO_BANKC       0x2000
146195 +#define GLAMO_GPIO_BANKD       0x3000
146196 +
146197 +#define GLAMO_GPIONO(bank, pin)        ((bank & 0xf000) | ((pin & 0xf) << 8))
146198 +
146199 +#define GLAMO_GPIO_F_IN                0x0010
146200 +#define GLAMO_GPIO_F_OUT       0x0020
146201 +#define GLAMO_GPIO_F_FUNC      0x0030
146202 +
146203 +#define GLAMO_GPIO0            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 0)
146204 +#define GLAMO_GPIO0_INPUT      (GLAMO_GPIO0 | GLAMO_GPIO_F_IN)
146205 +#define GLAMO_GPIO0_OUTPUT     (GLAMO_GPIO0 | GLAMO_GPIO_F_OUT)
146206 +#define GLAMO_GPIO0_HA20       (GLAMO_GPIO0 | GLAMO_GPIO_F_FUNC)
146207 +
146208 +#define GLAMO_GPIO1            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 1)
146209 +#define GLAMO_GPIO1_INPUT      (GLAMO_GPIO1 | GLAMO_GPIO_F_IN)
146210 +#define GLAMO_GPIO1_OUTPUT     (GLAMO_GPIO1 | GLAMO_GPIO_F_OUT)
146211 +#define GLAMO_GPIO1_HA21       (GLAMO_GPIO1 | GLAMO_GPIO_F_FUNC)
146212 +
146213 +#define GLAMO_GPIO2            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 2)
146214 +#define GLAMO_GPIO2_INPUT      (GLAMO_GPIO2 | GLAMO_GPIO_F_IN)
146215 +#define GLAMO_GPIO2_OUTPUT     (GLAMO_GPIO2 | GLAMO_GPIO_F_OUT)
146216 +#define GLAMO_GPIO2_HA22       (GLAMO_GPIO2 | GLAMO_GPIO_F_FUNC)
146217 +
146218 +#define GLAMO_GPIO3            GLAMO_GPIONO(GLAMO_GPIO_BANKA, 3)
146219 +#define GLAMO_GPIO3_INPUT      (GLAMO_GPIO3 | GLAMO_GPIO_F_IN)
146220 +#define GLAMO_GPIO3_OUTPUT     (GLAMO_GPIO3 | GLAMO_GPIO_F_OUT)
146221 +#define        GLAMO_GPIO3_HA23        (GLAMO_GPIO3 | GLAMO_GPIO_F_FUNC)
146222 +
146223 +#define GLAMO_GPIO4            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 0)
146224 +#define GLAMO_GPIO4_INPUT      (GLAMO_GPIO4 | GLAMO_GPIO_F_IN)
146225 +#define GLAMO_GPIO4_OUTPUT     (GLAMO_GPIO4 | GLAMO_GPIO_F_OUT)
146226 +#define GLAMO_GPIO4_nLCS0      (GLAMO_GPIO4 | GLAMO_GPIO_F_FUNC)
146227 +
146228 +#define GLAMO_GPIO5            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 1)
146229 +#define GLAMO_GPIO5_INPUT      (GLAMO_GPIO5 | GLAMO_GPIO_F_IN)
146230 +#define GLAMO_GPIO5_OUTPUT     (GLAMO_GPIO5 | GLAMO_GPIO_F_OUT)
146231 +#define GLAMO_GPIO5_nLCS1      (GLAMO_GPIO5 | GLAMO_GPIO_F_FUNC)
146232 +
146233 +#define GLAMO_GPIO6            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 2)
146234 +#define GLAMO_GPIO6_INPUT      (GLAMO_GPIO6 | GLAMO_GPIO_F_IN)
146235 +#define GLAMO_GPIO6_OUTPUT     (GLAMO_GPIO6 | GLAMO_GPIO_F_OUT)
146236 +#define GLAMO_GPIO6_LDCLK      (GLAMO_GPIO6 | GLAMO_GPIO_F_FUNC)
146237 +
146238 +#define GLAMO_GPIO7            GLAMO_GPIONO(GLAMO_GPIO_BANKB, 3)
146239 +#define GLAMO_GPIO7_INPUT      (GLAMO_GPIO7 | GLAMO_GPIO_F_IN)
146240 +#define GLAMO_GPIO7_OUTPUT     (GLAMO_GPIO7 | GLAMO_GPIO_F_OUT)
146241 +#define GLAMO_GPIO7_nLDE       (GLAMO_GPIO7 | GLAMO_GPIO_F_FUNC)
146242 +
146243 +#define GLAMO_GPIO8            GLAMO_GPIONO(GLAMO_GPIO_BANKC, 0)
146244 +#define GLAMO_GPIO8_INPUT      (GLAMO_GPIO8 | GLAMO_GPIO_F_IN)
146245 +#define GLAMO_GPIO8_OUTPUT     (GLAMO_GPIO8 | GLAMO_GPIO_F_OUT)
146246 +#define GLAMO_GPIO8_LD16       (GLAMO_GPIO8 | GLAMO_GPIO_F_FUNC)
146247 +
146248 +#define GLAMO_GPIO9            GLAMO_GPIONO(GLAMO_GPIO_BANKC, 1)
146249 +#define GLAMO_GPIO9_INPUT      (GLAMO_GPIO9 | GLAMO_GPIO_F_IN)
146250 +#define GLAMO_GPIO9_OUTPUT     (GLAMO_GPIO9 | GLAMO_GPIO_F_OUT)
146251 +#define GLAMO_GPIO9_LD17       (GLAMO_GPIO9 | GLAMO_GPIO_F_FUNC)
146252 +
146253 +#define GLAMO_GPIO10           GLAMO_GPIONO(GLAMO_GPIO_BANKC, 2)
146254 +#define GLAMO_GPIO10_INPUT     (GLAMO_GPIO10 | GLAMO_GPIO_F_IN)
146255 +#define GLAMO_GPIO10_OUTPUT    (GLAMO_GPIO10 | GLAMO_GPIO_F_OUT)
146256 +#define GLAMO_GPIO10_LSCK      (GLAMO_GPIO10 | GLAMO_GPIO_F_FUNC)
146257 +
146258 +#define GLAMO_GPIO11           GLAMO_GPIONO(GLAMO_GPIO_BANKC, 3)
146259 +#define GLAMO_GPIO11_INPUT     (GLAMO_GPIO11 | GLAMO_GPIO_F_IN)
146260 +#define GLAMO_GPIO11_OUTPUT    (GLAMO_GPIO11 | GLAMO_GPIO_F_OUT)
146261 +#define GLAMO_GPIO11_LSDA      (GLAMO_GPIO11 | GLAMO_GPIO_F_FUNC)
146262 +
146263 +#define GLAMO_GPIO12           GLAMO_GPIONO(GLAMO_GPIO_BANKD, 0)
146264 +#define GLAMO_GPIO12_INPUT     (GLAMO_GPIO12 | GLAMO_GPIO_F_IN)
146265 +#define GLAMO_GPIO12_OUTPUT    (GLAMO_GPIO12 | GLAMO_GPIO_F_OUT)
146266 +#define GLAMO_GPIO12_LSA0      (GLAMO_GPIO12 | GLAMO_GPIO_F_FUNC)
146267 +
146268 +
146269 +#define REG_OF_GPIO(gpio)      (((gpio & 0xf000) >> 12)*2 \
146270 +                                               + GLAMO_REG_GPIO_GEN1)
146271 +#define NUM_OF_GPIO(gpio)      ((gpio & 0x0f00) >> 8)
146272 +#define GPIO_OUT_BIT(gpio)     (1 << (NUM_OF_GPIO(gpio) + 0))
146273 +#define OUTPUT_BIT(gpio)       (1 << (NUM_OF_GPIO(gpio) + 4))
146274 +#define INPUT_BIT(gpio)                (1 << (NUM_OF_GPIO(gpio) + 8))
146275 +#define FUNC_BIT(gpio)         (1 << (NUM_OF_GPIO(gpio) + 12))
146276 +
146277 +void glamo_gpio_setpin(struct glamo_core *glamo, unsigned int pin,
146278 +                      unsigned int value);
146279 +
146280 +int glamo_gpio_getpin(struct glamo_core *glamo, unsigned int pin);
146281 +
146282 +void glamo_gpio_cfgpin(struct glamo_core *glamo, unsigned int pinfunc);
146283 +
146284 +
146285 +#endif /* _GLAMO_GPIO */
146286 Index: linux-2.6.28/include/linux/gta02_hdq.h
146287 ===================================================================
146288 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146289 +++ linux-2.6.28/include/linux/gta02_hdq.h      2009-01-02 00:01:57.000000000 +0100
146290 @@ -0,0 +1,18 @@
146291 +#ifndef __GTA02HDQ_H__
146292 +#define __GTA02HDQ_H__
146293 +
146294 +/* platform data */
146295 +
146296 +struct gta02_hdq_platform_data {
146297 +       /*
146298 +        * give an opportunity to use us as parent for
146299 +        * devices that depend on us
146300 +        */
146301 +       void (*attach_child_devices)(struct device *parent_device);
146302 +};
146303 +
146304 +int gta02hdq_read(int address);
146305 +int gta02hdq_write(int address, u8 data);
146306 +int gta02hdq_initialized(void);
146307 +
146308 +#endif
146309 Index: linux-2.6.28/include/linux/i2c-id.h
146310 ===================================================================
146311 --- linux-2.6.28.orig/include/linux/i2c-id.h    2008-12-25 00:26:37.000000000 +0100
146312 +++ linux-2.6.28/include/linux/i2c-id.h 2009-01-02 00:01:57.000000000 +0100
146313 @@ -83,6 +83,9 @@
146314  #define I2C_DRIVERID_CS5345    96      /* cs5345 audio processor       */
146315
146316  #define I2C_DRIVERID_OV7670 1048       /* Omnivision 7670 camera */
146317 +#define I2C_DRIVERID_PCF50606 1049
146318 +#define I2C_DRIVERID_PCF50633 1051
146319 +#define I2C_DRIVERID_PCA9632  1052
146320
146321  /*
146322   * ---- Adapter types ----------------------------------------------------
146323 Index: linux-2.6.28/include/linux/jbt6k74.h
146324 ===================================================================
146325 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146326 +++ linux-2.6.28/include/linux/jbt6k74.h        2009-01-02 00:01:57.000000000 +0100
146327 @@ -0,0 +1,14 @@
146328 +#ifndef __JBT6K74_H__
146329 +#define __JBT6K74_H__
146330 +
146331 +#include <linux/spi/spi.h>
146332 +#include <linux/device.h>
146333 +
146334 +
146335 +struct jbt6k74_platform_data {
146336 +       void (*reset)(int devindex, int level);
146337 +       void (*resuming)(int devindex); /* called when LCM is resumed */
146338 +       void (*probe_completed)(struct device *dev);
146339 +};
146340 +
146341 +#endif
146342 Index: linux-2.6.28/include/linux/kernel.h
146343 ===================================================================
146344 --- linux-2.6.28.orig/include/linux/kernel.h    2008-12-25 00:26:37.000000000 +0100
146345 +++ linux-2.6.28/include/linux/kernel.h 2009-01-02 00:01:57.000000000 +0100
146346 @@ -225,6 +225,8 @@ extern struct ratelimit_state printk_rat
146347  extern int printk_ratelimit(void);
146348  extern bool printk_timed_ratelimit(unsigned long *caller_jiffies,
146349                                    unsigned int interval_msec);
146350 +extern void (*printk_emergency_debug_spew_init)(void);
146351 +extern void (*printk_emergency_debug_spew_send_string)(const char *);
146352  #else
146353  static inline int vprintk(const char *s, va_list args)
146354         __attribute__ ((format (printf, 1, 0)));
146355 Index: linux-2.6.28/include/linux/kexec.h
146356 ===================================================================
146357 --- linux-2.6.28.orig/include/linux/kexec.h     2008-12-25 00:26:37.000000000 +0100
146358 +++ linux-2.6.28/include/linux/kexec.h  2009-01-02 00:01:57.000000000 +0100
146359 @@ -1,7 +1,6 @@
146360  #ifndef LINUX_KEXEC_H
146361  #define LINUX_KEXEC_H
146362
146363 -#ifdef CONFIG_KEXEC
146364  #include <linux/types.h>
146365  #include <linux/list.h>
146366  #include <linux/linkage.h>
146367 @@ -11,6 +10,8 @@
146368  #include <linux/elf.h>
146369  #include <asm/kexec.h>
146370
146371 +#ifdef CONFIG_KEXEC
146372 +
146373  /* Verify architecture specific macros are defined */
146374
146375  #ifndef KEXEC_SOURCE_MEMORY_LIMIT
146376 Index: linux-2.6.28/include/linux/lis302dl.h
146377 ===================================================================
146378 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146379 +++ linux-2.6.28/include/linux/lis302dl.h       2009-01-02 00:01:57.000000000 +0100
146380 @@ -0,0 +1,154 @@
146381 +#ifndef _LINUX_LIS302DL_H
146382 +#define _LINUX_LIS302DL_H
146383 +
146384 +#include <linux/types.h>
146385 +#include <linux/spi/spi.h>
146386 +#include <linux/input.h>
146387 +
146388 +
146389 +struct lis302dl_info;
146390 +
146391 +struct lis302dl_platform_data {
146392 +       char *name;
146393 +       unsigned long pin_chip_select;
146394 +       unsigned long pin_clk;
146395 +       unsigned long pin_mosi;
146396 +       unsigned long pin_miso;
146397 +       int open_drain;
146398 +       int interrupt;
146399 +       void (*lis302dl_bitbang)(struct lis302dl_info *lis, u8 *tx,
146400 +                       int tx_bytes, u8 *rx, int rx_bytes);
146401 +       void (*lis302dl_suspend_io)(struct lis302dl_info *, int resuming);
146402 +       int (*lis302dl_bitbang_reg_read)(struct lis302dl_info *, u8 reg);
146403 +       void (*lis302dl_bitbang_reg_write)(struct lis302dl_info *, u8 reg,
146404 +                                                                       u8 val);
146405 +};
146406 +
146407 +struct lis302dl_info {
146408 +       struct lis302dl_platform_data *pdata;
146409 +       struct device *dev;
146410 +       struct input_dev *input_dev;
146411 +       unsigned int flags;
146412 +       unsigned int threshold;
146413 +       unsigned int duration;
146414 +       struct {
146415 +               unsigned int threshold; /* mg */
146416 +               unsigned int duration;  /* ms */
146417 +       } wakeup;
146418 +       u_int8_t regs[0x40];
146419 +};
146420 +
146421 +enum lis302dl_reg {
146422 +       LIS302DL_REG_WHO_AM_I           = 0x0f,
146423 +       LIS302DL_REG_CTRL1              = 0x20,
146424 +       LIS302DL_REG_CTRL2              = 0x21,
146425 +       LIS302DL_REG_CTRL3              = 0x22,
146426 +       LIS302DL_REG_HP_FILTER_RESET    = 0x23,
146427 +       LIS302DL_REG_STATUS             = 0x27,
146428 +       LIS302DL_REG_OUT_X              = 0x29,
146429 +       LIS302DL_REG_OUT_Y              = 0x2b,
146430 +       LIS302DL_REG_OUT_Z              = 0x2d,
146431 +       LIS302DL_REG_FF_WU_CFG_1        = 0x30,
146432 +       LIS302DL_REG_FF_WU_SRC_1        = 0x31,
146433 +       LIS302DL_REG_FF_WU_THS_1        = 0x32,
146434 +       LIS302DL_REG_FF_WU_DURATION_1   = 0x33,
146435 +       LIS302DL_REG_FF_WU_CFG_2        = 0x34,
146436 +       LIS302DL_REG_FF_WU_SRC_2        = 0x35,
146437 +       LIS302DL_REG_FF_WU_THS_2        = 0x36,
146438 +       LIS302DL_REG_FF_WU_DURATION_2   = 0x37,
146439 +       LIS302DL_REG_CLICK_CFG          = 0x38,
146440 +       LIS302DL_REG_CLICK_SRC          = 0x39,
146441 +       LIS302DL_REG_CLICK_THSY_X       = 0x3b,
146442 +       LIS302DL_REG_CLICK_THSZ         = 0x3c,
146443 +       LIS302DL_REG_CLICK_TIME_LIMIT   = 0x3d,
146444 +       LIS302DL_REG_CLICK_LATENCY      = 0x3e,
146445 +       LIS302DL_REG_CLICK_WINDOW       = 0x3f,
146446 +};
146447 +
146448 +enum lis302dl_reg_ctrl1 {
146449 +       LIS302DL_CTRL1_Xen              = 0x01,
146450 +       LIS302DL_CTRL1_Yen              = 0x02,
146451 +       LIS302DL_CTRL1_Zen              = 0x04,
146452 +       LIS302DL_CTRL1_STM              = 0x08,
146453 +       LIS302DL_CTRL1_STP              = 0x10,
146454 +       LIS302DL_CTRL1_FS               = 0x20,
146455 +       LIS302DL_CTRL1_PD               = 0x40,
146456 +       LIS302DL_CTRL1_DR               = 0x80,
146457 +};
146458 +
146459 +enum lis302dl_reg_ctrl2 {
146460 +       LIS302DL_CTRL2_HPC1             = 0x01,
146461 +       LIS302DL_CTRL2_HPC2             = 0x02,
146462 +       LIS302DL_CTRL2_HPFF1            = 0x04,
146463 +       LIS302DL_CTRL2_HPFF2            = 0x08,
146464 +       LIS302DL_CTRL2_FDS              = 0x10,
146465 +       LIS302DL_CTRL2_BOOT             = 0x40,
146466 +       LIS302DL_CTRL2_SIM              = 0x80,
146467 +};
146468 +enum lis302dl_reg_ctrl3 {
146469 +       LIS302DL_CTRL3_PP_OD            = 0x40,
146470 +       LIS302DL_CTRL3_IHL              = 0x80,
146471 +};
146472 +
146473 +enum lis302dl_reg_status {
146474 +       LIS302DL_STATUS_XDA             = 0x01,
146475 +       LIS302DL_STATUS_YDA             = 0x02,
146476 +       LIS302DL_STATUS_ZDA             = 0x04,
146477 +       LIS302DL_STATUS_XYZDA           = 0x08,
146478 +       LIS302DL_STATUS_XOR             = 0x10,
146479 +       LIS302DL_STATUS_YOR             = 0x20,
146480 +       LIS302DL_STATUS_ZOR             = 0x40,
146481 +       LIS302DL_STATUS_XYZOR           = 0x80,
146482 +};
146483 +
146484 +/* Wakeup/freefall interrupt defs */
146485 +enum lis302dl_reg_ffwucfg {
146486 +       LIS302DL_FFWUCFG_XLIE           = 0x01,
146487 +       LIS302DL_FFWUCFG_XHIE           = 0x02,
146488 +       LIS302DL_FFWUCFG_YLIE           = 0x04,
146489 +       LIS302DL_FFWUCFG_YHIE           = 0x08,
146490 +       LIS302DL_FFWUCFG_ZLIE           = 0x10,
146491 +       LIS302DL_FFWUCFG_ZHIE           = 0x20,
146492 +       LIS302DL_FFWUCFG_LIR            = 0x40,
146493 +       LIS302DL_FFWUCFG_AOI            = 0x80,
146494 +};
146495 +
146496 +enum lis302dl_reg_ffwuths {
146497 +       LIS302DL_FFWUTHS_DCRM           = 0x80,
146498 +};
146499 +
146500 +enum lis302dl_reg_ffwusrc {
146501 +       LIS302DL_FFWUSRC_XL             = 0x01,
146502 +       LIS302DL_FFWUSRC_XH             = 0x02,
146503 +       LIS302DL_FFWUSRC_YL             = 0x04,
146504 +       LIS302DL_FFWUSRC_YH             = 0x08,
146505 +       LIS302DL_FFWUSRC_ZL             = 0x10,
146506 +       LIS302DL_FFWUSRC_ZH             = 0x20,
146507 +       LIS302DL_FFWUSRC_IA             = 0x40,
146508 +};
146509 +
146510 +enum lis302dl_reg_cloik_src {
146511 +       LIS302DL_CLICKSRC_SINGLE_X      = 0x01,
146512 +       LIS302DL_CLICKSRC_DOUBLE_X      = 0x02,
146513 +       LIS302DL_CLICKSRC_SINGLE_Y      = 0x04,
146514 +       LIS302DL_CLICKSRC_DOUBLE_Y      = 0x08,
146515 +       LIS302DL_CLICKSRC_SINGLE_Z      = 0x10,
146516 +       LIS302DL_CLICKSRC_DOUBLE_Z      = 0x20,
146517 +       LIS302DL_CLICKSRC_IA            = 0x40,
146518 +};
146519 +
146520 +#define LIS302DL_WHO_AM_I_MAGIC                0x3b
146521 +
146522 +#define LIS302DL_F_WUP_FF_1            0x0001  /* wake up from free fall */
146523 +#define LIS302DL_F_WUP_FF_2            0x0002
146524 +#define LIS302DL_F_WUP_FF              0x0003
146525 +#define LIS302DL_F_WUP_CLICK   0x0004
146526 +#define LIS302DL_F_POWER               0x0010
146527 +#define LIS302DL_F_FS                  0x0020  /* ADC full scale */
146528 +#define LIS302DL_F_INPUT_OPEN  0x0040  /* Set if input device is opened */
146529 +#define LIS302DL_F_IRQ_WAKE    0x0080  /* IRQ is setup in wake mode */
146530 +#define LIS302DL_F_DR                  0x0100  /* Data rate, 400Hz/100Hz */
146531 +
146532 +
146533 +#endif /* _LINUX_LIS302DL_H */
146534 +
146535 Index: linux-2.6.28/include/linux/logger.h
146536 ===================================================================
146537 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146538 +++ linux-2.6.28/include/linux/logger.h 2009-01-02 00:01:57.000000000 +0100
146539 @@ -0,0 +1,48 @@
146540 +/* include/linux/logger.h
146541 + *
146542 + * Copyright (C) 2007-2008 Google, Inc.
146543 + * Author: Robert Love <rlove@android.com>
146544 + *
146545 + * This software is licensed under the terms of the GNU General Public
146546 + * License version 2, as published by the Free Software Foundation, and
146547 + * may be copied, distributed, and modified under those terms.
146548 + *
146549 + * This program is distributed in the hope that it will be useful,
146550 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
146551 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
146552 + * GNU General Public License for more details.
146553 + *
146554 + */
146555 +
146556 +#ifndef _LINUX_LOGGER_H
146557 +#define _LINUX_LOGGER_H
146558 +
146559 +#include <linux/types.h>
146560 +#include <linux/ioctl.h>
146561 +
146562 +struct logger_entry {
146563 +       __u16           len;    /* length of the payload */
146564 +       __u16           __pad;  /* no matter what, we get 2 bytes of padding */
146565 +       __s32           pid;    /* generating process's pid */
146566 +       __s32           tid;    /* generating process's tid */
146567 +       __s32           sec;    /* seconds since Epoch */
146568 +       __s32           nsec;   /* nanoseconds */
146569 +       char            msg[0]; /* the entry's payload */
146570 +};
146571 +
146572 +#define LOGGER_LOG_RADIO       "log_radio"     /* radio-related messages */
146573 +#define LOGGER_LOG_EVENTS      "log_events"    /* system/hardware events */
146574 +#define LOGGER_LOG_MAIN                "log_main"      /* everything else */
146575 +
146576 +#define LOGGER_ENTRY_MAX_LEN           (4*1024)
146577 +#define LOGGER_ENTRY_MAX_PAYLOAD       \
146578 +       (LOGGER_ENTRY_MAX_LEN - sizeof(struct logger_entry))
146579 +
146580 +#define __LOGGERIO     0xAE
146581 +
146582 +#define LOGGER_GET_LOG_BUF_SIZE                _IO(__LOGGERIO, 1) /* size of log */
146583 +#define LOGGER_GET_LOG_LEN             _IO(__LOGGERIO, 2) /* used log len */
146584 +#define LOGGER_GET_NEXT_ENTRY_LEN      _IO(__LOGGERIO, 3) /* next entry len */
146585 +#define LOGGER_FLUSH_LOG               _IO(__LOGGERIO, 4) /* flush log */
146586 +
146587 +#endif /* _LINUX_LOGGER_H */
146588 Index: linux-2.6.28/include/linux/mfd/pcf50606/adc.h
146589 ===================================================================
146590 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146591 +++ linux-2.6.28/include/linux/mfd/pcf50606/adc.h       2009-01-02 00:01:57.000000000 +0100
146592 @@ -0,0 +1,87 @@
146593 +/*
146594 + * adc.h  -- Driver for NXP PCF50606 ADC
146595 + *
146596 + * (C) 2006-2008 by Openmoko, Inc.
146597 + * All rights reserved.
146598 + *
146599 + * This program is free software; you can redistribute  it and/or modify it
146600 + * under  the terms of  the GNU General  Public License as published by the
146601 + * Free Software Foundation;  either version 2 of the  License, or (at your
146602 + * option) any later version.
146603 + */
146604 +
146605 +#ifndef __LINUX_MFD_PCF50606_ADC_H
146606 +#define __LINUX_MFD_PCF50606_ADC_H
146607 +
146608 +#include <linux/platform_device.h>
146609 +
146610 +/* ADC Registers */
146611 +#define PCF50606_REG_ADCC1 0x2e
146612 +#define PCF50606_REG_ADCC2 0x2f
146613 +#define PCF50606_REG_ADCS1 0x30
146614 +#define PCF50606_REG_ADCS2 0x31
146615 +#define PCF50606_REG_ADCS3 0x32
146616 +
146617 +#define PCF50606_ADCC1_TSCMODACT        0x01
146618 +#define PCF50606_ADCC1_TSCMODSTB        0x02
146619 +#define PCF50606_ADCC1_TRATSET          0x04
146620 +#define PCF50606_ADCC1_NTCSWAPE                 0x08
146621 +#define PCF50606_ADCC1_NTCSWAOFF        0x10
146622 +#define PCF50606_ADCC1_EXTSYNCBREAK     0x20
146623 +       /* reserved */
146624 +#define PCF50606_ADCC1_TSCINT           0x80
146625 +
146626 +#define PCF50606_ADCC2_ADCSTART                 0x01
146627 +       /* see enum pcf50606_adcc2_adcmux */
146628 +#define PCF50606_ADCC2_SYNC_NONE        0x00
146629 +#define PCF50606_ADCC2_SYNC_TXON        0x20
146630 +#define PCF50606_ADCC2_SYNC_PWREN1      0x40
146631 +#define PCF50606_ADCC2_SYNC_PWREN2      0x60
146632 +#define PCF50606_ADCC2_RES_10BIT        0x00
146633 +#define PCF50606_ADCC2_RES_8BIT                 0x80
146634 +
146635 +#define PCF50606_ADCC2_ADCMUX_MASK     (0xf << 1)
146636 +
146637 +#define ADCMUX_SHIFT   1
146638 +#define PCF50606_ADCMUX_BATVOLT_RES     (0x0 << ADCMUX_SHIFT)
146639 +#define PCF50606_ADCMUX_BATVOLT_SUBTR   (0x1 << ADCMUX_SHIFT)
146640 +#define PCF50606_ADCMUX_ADCIN1_RES      (0x2 << ADCMUX_SHIFT)
146641 +#define PCF50606_ADCMUX_ADCIN1_SUBTR    (0x3 << ADCMUX_SHIFT)
146642 +#define PCF50606_ADCMUX_BATTEMP                 (0x4 << ADCMUX_SHIFT)
146643 +#define PCF50606_ADCMUX_ADCIN2          (0x5 << ADCMUX_SHIFT)
146644 +#define PCF50606_ADCMUX_ADCIN3          (0x6 << ADCMUX_SHIFT)
146645 +#define PCF50606_ADCMUX_ADCIN3_RATIO    (0x7 << ADCMUX_SHIFT)
146646 +#define PCF50606_ADCMUX_XPOS            (0x8 << ADCMUX_SHIFT)
146647 +#define PCF50606_ADCMUX_YPOS            (0x9 << ADCMUX_SHIFT)
146648 +#define PCF50606_ADCMUX_P1              (0xa << ADCMUX_SHIFT)
146649 +#define PCF50606_ADCMUX_P2              (0xb << ADCMUX_SHIFT)
146650 +#define PCF50606_ADCMUX_BATVOLT_ADCIN1  (0xc << ADCMUX_SHIFT)
146651 +#define PCF50606_ADCMUX_XY_SEQUENCE     (0xe << ADCMUX_SHIFT)
146652 +#define PCF50606_P1_P2_RESISTANCE       (0xf << ADCMUX_SHIFT)
146653 +
146654 +#define PCF50606_ADCS2_ADCRDY           0x80
146655 +
146656 +struct pcf50606;
146657 +
146658 +#define PCF50606_MAX_ADC_FIFO_DEPTH 8
146659 +
146660 +struct pcf50606_adc_request;
146661 +
146662 +struct pcf50606_adc {
146663 +       struct platform_device *pdev;
146664 +
146665 +       /* Private stuff */
146666 +       struct pcf50606_adc_request *queue[PCF50606_MAX_ADC_FIFO_DEPTH];
146667 +       int queue_head;
146668 +       int queue_tail;
146669 +       struct mutex queue_mutex;
146670 +};
146671 +
146672 +extern int
146673 +pcf50606_adc_async_read(struct pcf50606 *pcf, int mux, int avg,
146674 +               void (*callback)(struct pcf50606 *, void *, int),
146675 +               void *callback_param);
146676 +extern int
146677 +pcf50606_adc_sync_read(struct pcf50606 *pcf, int mux, int avg);
146678 +
146679 +#endif /* __LINUX_PCF50606_ADC_H */
146680 Index: linux-2.6.28/include/linux/mfd/pcf50606/core.h
146681 ===================================================================
146682 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146683 +++ linux-2.6.28/include/linux/mfd/pcf50606/core.h      2009-01-02 00:01:57.000000000 +0100
146684 @@ -0,0 +1,163 @@
146685 +/*
146686 + * core.h  -- Core driver for NXP PCF50606
146687 + *
146688 + * (C) 2006-2008 by Openmoko, Inc.
146689 + * All rights reserved.
146690 + *
146691 + * This program is free software; you can redistribute  it and/or modify it
146692 + * under  the terms of  the GNU General  Public License as published by the
146693 + * Free Software Foundation;  either version 2 of the  License, or (at your
146694 + * option) any later version.
146695 + */
146696 +
146697 +#ifndef __LINUX_MFD_PCF50606_CORE_H
146698 +#define __LINUX_MFD_PCF50606_CORE_H
146699 +
146700 +#include <linux/i2c.h>
146701 +#include <linux/workqueue.h>
146702 +#include <linux/regulator/driver.h>
146703 +#include <linux/regulator/machine.h>
146704 +#include <linux/power_supply.h>
146705 +
146706 +#include <linux/mfd/pcf50606/pmic.h>
146707 +#include <linux/mfd/pcf50606/input.h>
146708 +#include <linux/mfd/pcf50606/mbc.h>
146709 +#include <linux/mfd/pcf50606/rtc.h>
146710 +#include <linux/mfd/pcf50606/adc.h>
146711 +#include <linux/mfd/pcf50606/wdt.h>
146712 +
146713 +struct pcf50606;
146714 +
146715 +struct pcf50606_platform_data {
146716 +       struct regulator_init_data reg_init_data[PCF50606_NUM_REGULATORS];
146717 +
146718 +       char **batteries;
146719 +       int num_batteries;
146720 +
146721 +       /* Callbacks */
146722 +       void (*probe_done)(struct pcf50606 *);
146723 +       void (*mbc_event_callback)(struct pcf50606 *, int);
146724 +       void (*regulator_registered)(struct pcf50606 *, int);
146725 +       void (*force_shutdown)(struct pcf50606 *);
146726 +
146727 +       u8 resumers[3];
146728 +
146729 +       /* Runtime data - filled by driver afer probe */
146730 +       struct pcf50606 *pcf;
146731 +};
146732 +
146733 +struct pcf50606_irq {
146734 +       void (*handler)(struct pcf50606 *, int, void *);
146735 +       void *data;
146736 +};
146737 +
146738 +int pcf50606_irq_mask(struct pcf50606 *pcf, int irq);
146739 +int pcf50606_irq_unmask(struct pcf50606 *pcf, int irq);
146740 +int pcf50606_irq_mask_get(struct pcf50606 *pcf, int irq);
146741 +
146742 +int pcf50606_read_block(struct pcf50606 *, u8 reg,
146743 +                                       int nr_regs, u8 *data);
146744 +int pcf50606_write_block(struct pcf50606 *pcf, u8 reg,
146745 +                                       int nr_regs, u8 *data);
146746 +u8 pcf50606_reg_read(struct pcf50606 *, u8 reg);
146747 +int pcf50606_reg_write(struct pcf50606 *pcf, u8 reg, u8 val);
146748 +
146749 +int pcf50606_reg_set_bit_mask(struct pcf50606 *pcf, u8 reg, u8 mask, u8 val);
146750 +int pcf50606_reg_clear_bits(struct pcf50606 *pcf, u8 reg, u8 bits);
146751 +
146752 +/* Interrupt registers */
146753 +
146754 +#define PCF50606_REG_INT1      0x02
146755 +#define        PCF50606_REG_INT2       0x03
146756 +#define        PCF50606_REG_INT3       0x04
146757 +
146758 +#define PCF50606_REG_INT1M     0x05
146759 +#define        PCF50606_REG_INT2M      0x06
146760 +#define        PCF50606_REG_INT3M      0x07
146761 +
146762 +enum {
146763 +       /* Chip IRQs */
146764 +       PCF50606_IRQ_ONKEYR,
146765 +       PCF50606_IRQ_ONKEYF,
146766 +       PCF50606_IRQ_ONKEY1S,
146767 +       PCF50606_IRQ_EXTONR,
146768 +       PCF50606_IRQ_EXTONF,
146769 +       PCF50606_IRQ_SECOND,
146770 +       PCF50606_IRQ_ALARM,
146771 +       PCF50606_IRQ_CHGINS,
146772 +       PCF50606_IRQ_CHGRM,
146773 +       PCF50606_IRQ_CHGFOK,
146774 +       PCF50606_IRQ_CHGERR,
146775 +       PCF50606_IRQ_CHGFRDY,
146776 +       PCF50606_IRQ_CHGPROT,
146777 +       PCF50606_IRQ_CHGWD10S,
146778 +       PCF50606_IRQ_CHGWDEXP,
146779 +       PCF50606_IRQ_ADCRDY,
146780 +       PCF50606_IRQ_ACDINS,
146781 +       PCF50606_IRQ_ACDREM,
146782 +       PCF50606_IRQ_TSCPRES,
146783 +       PCF50606_IRQ_LOWBAT,
146784 +       PCF50606_IRQ_HIGHTMP,
146785 +
146786 +       /* Always last */
146787 +       PCF50606_NUM_IRQ,
146788 +};
146789 +
146790 +struct pcf50606 {
146791 +       struct device *dev;
146792 +       struct i2c_client *i2c_client;
146793 +
146794 +       struct pcf50606_platform_data *pdata;
146795 +       int irq;
146796 +       struct pcf50606_irq irq_handler[PCF50606_NUM_IRQ];
146797 +       struct work_struct irq_work;
146798 +       struct mutex lock;
146799 +
146800 +       u8 mask_regs[3];
146801 +
146802 +       u8 suspend_irq_masks[3];
146803 +       u8 resume_reason[3];
146804 +       int is_suspended;
146805 +
146806 +       int onkey1s_held;
146807 +
146808 +       struct pcf50606_pmic pmic;
146809 +       struct pcf50606_input input;
146810 +       struct pcf50606_mbc mbc;
146811 +       struct pcf50606_rtc rtc;
146812 +       struct pcf50606_adc adc;
146813 +       struct pcf50606_wdt wdt;
146814 +};
146815 +
146816 +enum pcf50606_reg_int1 {
146817 +       PCF50606_INT1_ONKEYR    = 0x01, /* ONKEY rising edge */
146818 +       PCF50606_INT1_ONKEYF    = 0x02, /* ONKEY falling edge */
146819 +       PCF50606_INT1_ONKEY1S   = 0x04, /* OMKEY at least 1sec low */
146820 +       PCF50606_INT1_EXTONR    = 0x08, /* EXTON rising edge */
146821 +       PCF50606_INT1_EXTONF    = 0x10, /* EXTON falling edge */
146822 +       PCF50606_INT1_SECOND    = 0x40, /* RTC periodic second interrupt */
146823 +       PCF50606_INT1_ALARM     = 0x80, /* RTC alarm time is reached */
146824 +};
146825 +
146826 +enum pcf50606_reg_int2 {
146827 +       PCF50606_INT2_CHGINS    = 0x01, /* Charger inserted */
146828 +       PCF50606_INT2_CHGRM     = 0x02, /* Charger removed */
146829 +       PCF50606_INT2_CHGFOK    = 0x04, /* Fast charging OK */
146830 +       PCF50606_INT2_CHGERR    = 0x08, /* Error in charging mode */
146831 +       PCF50606_INT2_CHGFRDY   = 0x10, /* Fast charge completed */
146832 +       PCF50606_INT2_CHGPROT   = 0x20, /* Charging protection interrupt */
146833 +       PCF50606_INT2_CHGWD10S  = 0x40, /* Charger watchdig expires in 10s */
146834 +       PCF50606_INT2_CHGWDEXP  = 0x80, /* Charger watchdog expires */
146835 +};
146836 +
146837 +enum pcf50606_reg_int3 {
146838 +       PCF50606_INT3_ADCRDY    = 0x01, /* ADC conversion finished */
146839 +       PCF50606_INT3_ACDINS    = 0x02, /* Accessory inserted */
146840 +       PCF50606_INT3_ACDREM    = 0x04, /* Accessory removed */
146841 +       PCF50606_INT3_TSCPRES   = 0x08, /* Touch screen pressed */
146842 +       PCF50606_INT3_LOWBAT    = 0x40, /* Low battery voltage */
146843 +       PCF50606_INT3_HIGHTMP   = 0x80, /* High temperature */
146844 +};
146845 +
146846 +#endif
146847 +
146848 Index: linux-2.6.28/include/linux/mfd/pcf50606/gpo.h
146849 ===================================================================
146850 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146851 +++ linux-2.6.28/include/linux/mfd/pcf50606/gpo.h       2009-01-02 00:01:57.000000000 +0100
146852 @@ -0,0 +1,43 @@
146853 +/*
146854 + * gpo.h -- GPO driver for NXP PCF50606
146855 + *
146856 + * (C) 2006-2008 by Openmoko, Inc.
146857 + * All rights reserved.
146858 + *
146859 + * This program is free software; you can redistribute  it and/or modify it
146860 + * under  the terms of  the GNU General  Public License as published by the
146861 + * Free Software Foundation;  either version 2 of the  License, or (at your
146862 + * option) any later version.
146863 + */
146864 +
146865 +#ifndef __LINUX_MFD_PCF50606_GPO_H
146866 +#define __LINUX_MFD_PCF50606_GPO_H
146867 +
146868 +#define PCF50606_REG_GPOC1 0x38
146869 +#define PCF50606_REG_GPOC2 0x39
146870 +#define PCF50606_REG_GPOC3 0x3a
146871 +#define PCF50606_REG_GPOC4 0x3b
146872 +#define PCF50606_REG_GPOC5 0x3c
146873 +
146874 +#define PCF50606_GPO1  PCF50606_REG_GPOC1
146875 +#define PCF50606_GPO2  PCF50606_REG_GPOC1
146876 +#define PCF50606_GPOOD1        PCF50606_REG_GPOC2
146877 +#define PCF50606_GPOOD2        PCF50606_REG_GPOC3
146878 +#define PCF50606_GPOOD3        PCF50606_REG_GPOC4
146879 +#define PCF50606_GPOOD4        PCF50606_REG_GPOC5
146880 +
146881 +#define PCF50606_GPOCFG_GPOSEL_MASK    0x07
146882 +
146883 +struct pcf50606;
146884 +
146885 +void pcf50606_gpo_set_active(struct pcf50606 *pcf, int gpo, int value);
146886 +int pcf50606_gpo_get_active(struct pcf50606 *pcf, int gpo);
146887 +void pcf50606_gpo_set_standby(struct pcf50606 *pcf, int gpo, int value);
146888 +int pcf50606_gpo_get_standby(struct pcf50606 *pcf, int gpo);
146889 +
146890 +void pcf50606_gpo_invert_set(struct pcf50606 *, int gpo, int invert);
146891 +int pcf50606_gpo_invert_get(struct pcf50606 *pcf, int gpo);
146892 +
146893 +#endif /* __LINUX_MFD_PCF50606_GPIO_H */
146894 +
146895 +
146896 Index: linux-2.6.28/include/linux/mfd/pcf50606/input.h
146897 ===================================================================
146898 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146899 +++ linux-2.6.28/include/linux/mfd/pcf50606/input.h     2009-01-02 00:01:57.000000000 +0100
146900 @@ -0,0 +1,37 @@
146901 +/*
146902 + * input.h  -- Input driver for NXP PCF50606
146903 + *
146904 + * (C) 2006-2008 by Openmoko, Inc.
146905 + * All rights reserved.
146906 + *
146907 + * This program is free software; you can redistribute  it and/or modify it
146908 + * under  the terms of  the GNU General  Public License as published by the
146909 + * Free Software Foundation;  either version 2 of the  License, or (at your
146910 + * option) any later version.
146911 + */
146912 +
146913 +#ifndef __LINUX_MFD_PCF50606_INPUT_H
146914 +#define __LINUX_MFD_PCF50606_INPUT_H
146915 +
146916 +#include <linux/platform_device.h>
146917 +#include <linux/input.h>
146918 +
146919 +#define PFC50606_OOCS_ONKEY     0x01
146920 +#define PCF50606_OOCS_EXTON     0x02
146921 +
146922 +#define PCF50606_OOCC2_ONKEYDB_NONE     0x00
146923 +#define PCF50606_OOCC2_ONKEYDB_14ms     0x01
146924 +#define PCF50606_OOCC2_ONKEYDB_62ms     0x02
146925 +#define PCF50606_OOCC2_ONKEYDB_500ms    0x03
146926 +#define PCF50606_OOCC2_EXTONDB_NONE     0x00
146927 +#define PCF50606_OOCC2_EXTONDB_14ms     0x04
146928 +#define PCF50606_OOCC2_EXTONDB_62ms     0x08
146929 +#define PCF50606_OOCC2_EXTONDB_500ms    0x0c
146930 +
146931 +struct pcf50606_input {
146932 +       struct input_dev *input_dev;
146933 +       struct platform_device *pdev;
146934 +};
146935 +
146936 +#endif
146937 +
146938 Index: linux-2.6.28/include/linux/mfd/pcf50606/led.h
146939 ===================================================================
146940 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146941 +++ linux-2.6.28/include/linux/mfd/pcf50606/led.h       2009-01-02 00:01:57.000000000 +0100
146942 @@ -0,0 +1,22 @@
146943 +/*
146944 + * led.h  -- LED driver for NXP PCF50606
146945 + *
146946 + * (C) 2006-2008 by Openmoko, Inc.
146947 + * All rights reserved.
146948 + *
146949 + * This program is free software; you can redistribute  it and/or modify it
146950 + * under  the terms of  the GNU General  Public License as published by the
146951 + * Free Software Foundation;  either version 2 of the  License, or (at your
146952 + * option) any later version.
146953 + */
146954 +
146955 +#ifndef __LINUX_MFD_PCF50606_LED_H
146956 +#define __LINUX_MFD_PCF50606_LED_H
146957 +
146958 +#define PCF50606_REG_LEDC1 0x36
146959 +#define PCF50606_REG_LEDC2 0x37
146960 +
146961 +#include <linux/platform_device.h>
146962 +
146963 +#endif
146964 +
146965 Index: linux-2.6.28/include/linux/mfd/pcf50606/mbc.h
146966 ===================================================================
146967 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
146968 +++ linux-2.6.28/include/linux/mfd/pcf50606/mbc.h       2009-01-02 00:01:57.000000000 +0100
146969 @@ -0,0 +1,53 @@
146970 +/*
146971 + * mbc.h  -- Driver for NXP PCF50606 Main Battery Charger
146972 + *
146973 + * (C) 2006-2008 by Openmoko, Inc.
146974 + * All rights reserved.
146975 + *
146976 + * This program is free software; you can redistribute  it and/or modify it
146977 + * under  the terms of  the GNU General  Public License as published by the
146978 + * Free Software Foundation;  either version 2 of the  License, or (at your
146979 + * option) any later version.
146980 + */
146981 +
146982 +#ifndef __LINUX_MFD_PCF50606_MBC_H
146983 +#define __LINUX_MFD_PCF50606_MBC_H
146984 +
146985 +#include <linux/platform_device.h>
146986 +
146987 +#define PCF50606_REG_MBCC1      0x29
146988 +#define PCF50606_REG_MBCC2      0x2a
146989 +#define PCF50606_REG_MBCC3      0x2b
146990 +#define PCF50606_REG_MBCS1      0x2c
146991 +
146992 +enum pcf50606_reg_mbcc1 {
146993 +       PCF50606_MBCC1_CHGAPE           = 0x01,
146994 +       PCF50606_MBCC1_AUTOFST          = 0x02,
146995 +#define        PCF50606_MBCC1_CHGMOD_MASK        0x1c
146996 +#define        PCF50606_MBCC1_CHGMOD_SHIFT       2
146997 +       PCF50606_MBCC1_CHGMOD_QUAL      = 0x00,
146998 +       PCF50606_MBCC1_CHGMOD_PRE       = 0x04,
146999 +       PCF50606_MBCC1_CHGMOD_TRICKLE   = 0x08,
147000 +       PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c,
147001 +       PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10,
147002 +       PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14,
147003 +       PCF50606_MBCC1_CHGMOD_FAST_SW   = 0x18,
147004 +       PCF50606_MBCC1_CHGMOD_IDLE      = 0x1c,
147005 +       PCF50606_MBCC1_DETMOD_LOWCHG    = 0x20,
147006 +       PCF50606_MBCC1_DETMOD_WDRST     = 0x40,
147007 +};
147008 +
147009 +struct pcf50606;
147010 +
147011 +void pcf50606_mbc_usb_curlim_set(struct pcf50606 *pcf, int ma);
147012 +
147013 +struct pcf50606_mbc {
147014 +       int charger_online;
147015 +       int charger_active;
147016 +
147017 +       struct power_supply charger;
147018 +
147019 +       struct platform_device *pdev;
147020 +};
147021 +#endif
147022 +
147023 Index: linux-2.6.28/include/linux/mfd/pcf50606/pmic.h
147024 ===================================================================
147025 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147026 +++ linux-2.6.28/include/linux/mfd/pcf50606/pmic.h      2009-01-02 00:01:57.000000000 +0100
147027 @@ -0,0 +1,82 @@
147028 +#ifndef __LINUX_MFD_PCF50606_PMIC_H
147029 +#define __LINUX_MFD_PCF50606_PMIC_H
147030 +
147031 +#include <linux/platform_device.h>
147032 +
147033 +#define PCF50606_REG_DCDC1      0x1b
147034 +#define PCF50606_REG_DCDC2      0x1c
147035 +#define PCF50606_REG_DCDC3      0x1d
147036 +#define PCF50606_REG_DCDC4      0x1e
147037 +#define PCF50606_REG_DCDEC1     0x1f
147038 +#define PCF50606_REG_DCDEC2     0x20
147039 +#define PCF50606_REG_DCUDC1     0x21
147040 +#define PCF50606_REG_DCUDC2     0x22
147041 +#define PCF50606_REG_IOREGC     0x23
147042 +#define PCF50606_REG_D1REGC1    0x24
147043 +#define PCF50606_REG_D2REGC1    0x25
147044 +#define PCF50606_REG_D3REGC1    0x26
147045 +#define PCF50606_REG_LPREGC1    0x27
147046 +#define PCF50606_REG_LPREGC2    0x28
147047 +
147048 +/* used by PSSC, PWROKM, PWROKS, */
147049 +enum pcf50606_regu {
147050 +       PCF50606_REGU_DCD       = 0x01, /* DCD in phase 2 */
147051 +       PCF50606_REGU_DCDE      = 0x02, /* DCDE in phase 2 */
147052 +       PCF50606_REGU_DCUD      = 0x04, /* DCDU in phase 2 */
147053 +       PCF50606_REGU_IO        = 0x08, /* IO in phase 2 */
147054 +       PCF50606_REGU_D1        = 0x10, /* D1 in phase 2 */
147055 +       PCF50606_REGU_D2        = 0x20, /* D2 in phase 2 */
147056 +       PCF50606_REGU_D3        = 0x40, /* D3 in phase 2 */
147057 +       PCF50606_REGU_LP        = 0x80, /* LP in phase 2 */
147058 +};
147059 +
147060 +enum pcf50606_reg_dcdc4 {
147061 +       PCF50606_DCDC4_MODE_AUTO        = 0x00,
147062 +       PCF50606_DCDC4_MODE_PWM         = 0x01,
147063 +       PCF50606_DCDC4_MODE_PCF         = 0x02,
147064 +       PCF50606_DCDC4_OFF_FLOAT        = 0x00,
147065 +       PCF50606_DCDC4_OFF_BYPASS       = 0x04,
147066 +       PCF50606_DCDC4_OFF_PULLDOWN     = 0x08,
147067 +       PCF50606_DCDC4_CURLIM_500mA     = 0x00,
147068 +       PCF50606_DCDC4_CURLIM_750mA     = 0x10,
147069 +       PCF50606_DCDC4_CURLIM_1000mA    = 0x20,
147070 +       PCF50606_DCDC4_CURLIM_1250mA    = 0x30,
147071 +       PCF50606_DCDC4_TOGGLE           = 0x40,
147072 +       PCF50606_DCDC4_REGSEL_DCDC2     = 0x80,
147073 +};
147074 +
147075 +enum pcf50606_reg_dcdec2 {
147076 +       PCF50606_DCDEC2_MODE_AUTO       = 0x00,
147077 +       PCF50606_DCDEC2_MODE_PWM        = 0x01,
147078 +       PCF50606_DCDEC2_MODE_PCF        = 0x02,
147079 +       PCF50606_DCDEC2_OFF_FLOAT       = 0x00,
147080 +       PCF50606_DCDEC2_OFF_BYPASS      = 0x04,
147081 +};
147082 +
147083 +enum pcf50606_reg_dcudc2 {
147084 +       PCF50606_DCUDC2_MODE_AUTO       = 0x00,
147085 +       PCF50606_DCUDC2_MODE_PWM        = 0x01,
147086 +       PCF50606_DCUDC2_MODE_PCF        = 0x02,
147087 +       PCF50606_DCUDC2_OFF_FLOAT       = 0x00,
147088 +       PCF50606_DCUDC2_OFF_BYPASS      = 0x04,
147089 +};
147090 +
147091 +enum pcf50606_regulator_id {
147092 +       PCF50606_REGULATOR_DCD,
147093 +       PCF50606_REGULATOR_DCDE,
147094 +       PCF50606_REGULATOR_DCUD,
147095 +       PCF50606_REGULATOR_D1REG,
147096 +       PCF50606_REGULATOR_D2REG,
147097 +       PCF50606_REGULATOR_D3REG,
147098 +       PCF50606_REGULATOR_LPREG,
147099 +       PCF50606_REGULATOR_IOREG,
147100 +
147101 +       /* Always last */
147102 +       PCF50606_NUM_REGULATORS
147103 +};
147104 +
147105 +struct pcf50606_pmic {
147106 +       struct platform_device *pdev[PCF50606_NUM_REGULATORS];
147107 +};
147108 +#endif
147109 +
147110 Index: linux-2.6.28/include/linux/mfd/pcf50606/rtc.h
147111 ===================================================================
147112 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147113 +++ linux-2.6.28/include/linux/mfd/pcf50606/rtc.h       2009-01-02 00:01:57.000000000 +0100
147114 @@ -0,0 +1,43 @@
147115 +/*
147116 + * rtc.h  -- RTC driver for NXP PCF50606
147117 + *
147118 + * (C) 2006-2008 by Openmoko, Inc.
147119 + * All rights reserved.
147120 + *
147121 + * This program is free software; you can redistribute  it and/or modify it
147122 + * under  the terms of  the GNU General  Public License as published by the
147123 + * Free Software Foundation;  either version 2 of the  License, or (at your
147124 + * option) any later version.
147125 + */
147126 +
147127 +#ifndef __LINUX_MFD_PCF50606_RTC_H
147128 +#define __LINUX_MFD_PCF50606_RTC_H
147129 +
147130 +#include <linux/rtc.h>
147131 +#include <linux/platform_device.h>
147132 +
147133 +#define PCF50606_REG_RTCSC      0x0a   /* Second */
147134 +#define PCF50606_REG_RTCMN      0x0b   /* Minute */
147135 +#define PCF50606_REG_RTCHR      0x0c   /* Hour */
147136 +#define PCF50606_REG_RTCWD      0x0d   /* Weekday */
147137 +#define PCF50606_REG_RTCDT      0x0e   /* Day */
147138 +#define PCF50606_REG_RTCMT      0x0f   /* Month */
147139 +#define PCF50606_REG_RTCYR      0x10   /* Year */
147140 +#define PCF50606_REG_RTCSCA     0x11 /* Alarm Second */
147141 +#define PCF50606_REG_RTCMNA     0x12 /* Alarm Minute */
147142 +#define PCF50606_REG_RTCHRA     0x13 /* Alarm Hour */
147143 +#define PCF50606_REG_RTCWDA     0x14 /* Alarm Weekday */
147144 +#define PCF50606_REG_RTCDTA     0x15 /* Alarm Day */
147145 +#define PCF50606_REG_RTCMTA     0x16 /* Alarm Month */
147146 +#define PCF50606_REG_RTCYRA     0x17 /* Alarm Year */
147147 +
147148 +struct pcf50606_rtc {
147149 +       int alarm_enabled;
147150 +       int second_enabled;
147151 +
147152 +       struct rtc_device *rtc_dev;
147153 +       struct platform_device *pdev;
147154 +};
147155 +
147156 +#endif
147157 +
147158 Index: linux-2.6.28/include/linux/mfd/pcf50606/wdt.h
147159 ===================================================================
147160 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147161 +++ linux-2.6.28/include/linux/mfd/pcf50606/wdt.h       2009-01-02 00:01:57.000000000 +0100
147162 @@ -0,0 +1,32 @@
147163 +/*
147164 + * wdt.h -- WDT driver for NXP PCF50606
147165 + *
147166 + * (C) 2006-2008 by Openmoko, Inc.
147167 + * All rights reserved.
147168 + *
147169 + * This program is free software; you can redistribute  it and/or modify it
147170 + * under  the terms of  the GNU General  Public License as published by the
147171 + * Free Software Foundation;  either version 2 of the  License, or (at your
147172 + * option) any later version.
147173 + */
147174 +
147175 +#ifndef __LINUX_MFD_PCF50606_WDT_H
147176 +#define __LINUX_MFD_PCF50606_WDT_H
147177 +
147178 +#define PCF50606_REG_OOCC1     0x08
147179 +#define PCF50606_REG_OOCS      0x01
147180 +
147181 +#define PCF50606_OOCS_WDTEXP   0x80
147182 +#define PCF50606_OOCC1_WDTRST  0x08
147183 +
147184 +#define CLOSE_STATE_NOT                0x0000
147185 +#define CLOSE_STATE_ALLOW      0x2342
147186 +
147187 +struct pcf50606;
147188 +
147189 +struct pcf50606_wdt {
147190 +       struct platform_device *pdev;
147191 +};
147192 +#endif /* __LINUX_MFD_PCF50606_WDT_H */
147193 +
147194 +
147195 Index: linux-2.6.28/include/linux/mfd/pcf50633/adc.h
147196 ===================================================================
147197 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147198 +++ linux-2.6.28/include/linux/mfd/pcf50633/adc.h       2009-01-02 00:01:57.000000000 +0100
147199 @@ -0,0 +1,88 @@
147200 +/*
147201 + * adc.h  -- Driver for NXP PCF50633 ADC
147202 + *
147203 + * (C) 2006-2008 by Openmoko, Inc.
147204 + * All rights reserved.
147205 + *
147206 + * This program is free software; you can redistribute  it and/or modify it
147207 + * under  the terms of  the GNU General  Public License as published by the
147208 + * Free Software Foundation;  either version 2 of the  License, or (at your
147209 + * option) any later version.
147210 + */
147211 +
147212 +#ifndef __LINUX_MFD_PCF50633_ADC_H
147213 +#define __LINUX_MFD_PCF50633_ADC_H
147214 +
147215 +#include <linux/platform_device.h>
147216 +
147217 +/* ADC Registers */
147218 +#define        PCF50633_REG_ADCC3 0x52
147219 +#define        PCF50633_REG_ADCC2 0x53
147220 +#define        PCF50633_REG_ADCC1 0x54
147221 +#define        PCF50633_REG_ADCS1 0x55
147222 +#define        PCF50633_REG_ADCS2 0x56
147223 +#define        PCF50633_REG_ADCS3 0x57
147224 +
147225 +#define        PCF50633_ADCC1_ADCSTART         0x01
147226 +#define        PCF50633_ADCC1_RES_10BIT        0x02
147227 +#define        PCF50633_ADCC1_AVERAGE_NO       0x00
147228 +#define        PCF50633_ADCC1_AVERAGE_4        0x04
147229 +#define        PCF50633_ADCC1_AVERAGE_8        0x08
147230 +#define        PCF50633_ADCC1_AVERAGE_16       0x0c
147231 +#define        PCF50633_ADCC1_MUX_BATSNS_RES   0x00
147232 +#define        PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10
147233 +#define        PCF50633_ADCC1_MUX_ADCIN2_RES   0x20
147234 +#define        PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30
147235 +#define        PCF50633_ADCC1_MUX_BATTEMP      0x60
147236 +#define        PCF50633_ADCC1_MUX_ADCIN1       0x70
147237 +#define PCF50633_ADCC1_AVERAGE_MASK    0x0c
147238 +#define        PCF50633_ADCC1_ADCMUX_MASK      0xf0
147239 +
147240 +#define        PCF50633_ADCC2_RATIO_NONE       0x00
147241 +#define        PCF50633_ADCC2_RATIO_BATTEMP    0x01
147242 +#define        PCF50633_ADCC2_RATIO_ADCIN1     0x02
147243 +#define        PCF50633_ADCC2_RATIO_BOTH       0x03
147244 +#define        PCF50633_ADCC2_RATIOSETTL_100US 0x04
147245 +
147246 +#define        PCF50633_ADCC3_ACCSW_EN         0x01
147247 +#define        PCF50633_ADCC3_NTCSW_EN         0x04
147248 +#define        PCF50633_ADCC3_RES_DIV_TWO      0x10
147249 +#define        PCF50633_ADCC3_RES_DIV_THREE    0x00
147250 +
147251 +#define        PCF50633_ADCS3_REF_NTCSW        0x00
147252 +#define        PCF50633_ADCS3_REF_ACCSW        0x10
147253 +#define        PCF50633_ADCS3_REF_2V0          0x20
147254 +#define        PCF50633_ADCS3_REF_VISA         0x30
147255 +#define        PCF50633_ADCS3_REF_2V0_2        0x70
147256 +#define        PCF50633_ADCS3_ADCRDY           0x80
147257 +
147258 +#define PCF50633_ADCS3_ADCDAT1L_MASK   0x03
147259 +#define PCF50633_ADCS3_ADCDAT2L_MASK   0x0c
147260 +#define PCF50633_ADCS3_ADCDAT2L_SHIFT  2
147261 +#define PCF50633_ASCS3_REF_MASK                0x70
147262 +
147263 +
147264 +struct pcf50633;
147265 +
147266 +#define PCF50633_MAX_ADC_FIFO_DEPTH 8
147267 +
147268 +struct pcf50633_adc_request;
147269 +
147270 +struct pcf50633_adc {
147271 +       struct platform_device *pdev;
147272 +
147273 +       /* Private stuff */
147274 +       struct pcf50633_adc_request *queue[PCF50633_MAX_ADC_FIFO_DEPTH];
147275 +       int queue_head;
147276 +       int queue_tail;
147277 +       struct mutex queue_mutex;
147278 +};
147279 +
147280 +extern int
147281 +pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
147282 +               void (*callback)(struct pcf50633 *, void *, int),
147283 +               void *callback_param);
147284 +extern int
147285 +pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg);
147286 +
147287 +#endif /* __LINUX_PCF50633_ADC_H */
147288 Index: linux-2.6.28/include/linux/mfd/pcf50633/core.h
147289 ===================================================================
147290 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147291 +++ linux-2.6.28/include/linux/mfd/pcf50633/core.h      2009-01-02 00:01:57.000000000 +0100
147292 @@ -0,0 +1,212 @@
147293 +/*
147294 + * core.h  -- Core driver for NXP PCF50633
147295 + *
147296 + * (C) 2006-2008 by Openmoko, Inc.
147297 + * All rights reserved.
147298 + *
147299 + * This program is free software; you can redistribute  it and/or modify it
147300 + * under  the terms of  the GNU General  Public License as published by the
147301 + * Free Software Foundation;  either version 2 of the  License, or (at your
147302 + * option) any later version.
147303 + */
147304 +
147305 +#ifndef __LINUX_MFD_PCF50633_CORE_H
147306 +#define __LINUX_MFD_PCF50633_CORE_H
147307 +
147308 +#include <linux/i2c.h>
147309 +#include <linux/workqueue.h>
147310 +#include <linux/regulator/driver.h>
147311 +#include <linux/regulator/machine.h>
147312 +#include <linux/power_supply.h>
147313 +
147314 +#include <linux/mfd/pcf50633/pmic.h>
147315 +#include <linux/mfd/pcf50633/input.h>
147316 +#include <linux/mfd/pcf50633/mbc.h>
147317 +#include <linux/mfd/pcf50633/rtc.h>
147318 +#include <linux/mfd/pcf50633/adc.h>
147319 +#include <linux/mfd/pcf50633/gpio.h>
147320 +
147321 +struct pcf50633;
147322 +
147323 +struct pcf50633_platform_data {
147324 +       struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
147325 +
147326 +       char **batteries;
147327 +       int num_batteries;
147328 +
147329 +       /* Callbacks */
147330 +       void (*probe_done)(struct pcf50633 *);
147331 +       void (*mbc_event_callback)(struct pcf50633 *, int);
147332 +       void (*regulator_registered)(struct pcf50633 *, int);
147333 +       void (*force_shutdown)(struct pcf50633 *);
147334 +
147335 +       u8 resumers[5];
147336 +
147337 +       /* Runtime data - filled by driver afer probe */
147338 +       struct pcf50633 *pcf;
147339 +};
147340 +
147341 +struct pcf50633_irq {
147342 +       void (*handler)(struct pcf50633 *, int, void *);
147343 +       void *data;
147344 +};
147345 +
147346 +int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
147347 +int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
147348 +int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
147349 +
147350 +int pcf50633_read_block(struct pcf50633 *, u8 reg,
147351 +                                       int nr_regs, u8 *data);
147352 +int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
147353 +                                       int nr_regs, u8 *data);
147354 +u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
147355 +int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
147356 +
147357 +int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
147358 +int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
147359 +
147360 +/* Interrupt registers */
147361 +
147362 +#define PCF50633_REG_INT1      0x02
147363 +#define        PCF50633_REG_INT2       0x03
147364 +#define        PCF50633_REG_INT3       0x04
147365 +#define        PCF50633_REG_INT4       0x05
147366 +#define        PCF50633_REG_INT5       0x06
147367 +
147368 +#define PCF50633_REG_INT1M     0x07
147369 +#define        PCF50633_REG_INT2M      0x08
147370 +#define        PCF50633_REG_INT3M      0x09
147371 +#define        PCF50633_REG_INT4M      0x0a
147372 +#define        PCF50633_REG_INT5M      0x0b
147373 +
147374 +enum {
147375 +       /* Chip IRQs */
147376 +       PCF50633_IRQ_ADPINS = 0,
147377 +       PCF50633_IRQ_ADPREM,
147378 +       PCF50633_IRQ_USBINS,
147379 +       PCF50633_IRQ_USBREM,
147380 +       PCF50633_IRQ_RESERVED1,
147381 +       PCF50633_IRQ_RESERVED2,
147382 +       PCF50633_IRQ_ALARM,
147383 +       PCF50633_IRQ_SECOND,
147384 +       PCF50633_IRQ_ONKEYR,
147385 +       PCF50633_IRQ_ONKEYF,
147386 +       PCF50633_IRQ_EXTON1R,
147387 +       PCF50633_IRQ_EXTON1F,
147388 +       PCF50633_IRQ_EXTON2R,
147389 +       PCF50633_IRQ_EXTON2F,
147390 +       PCF50633_IRQ_EXTON3R,
147391 +       PCF50633_IRQ_EXTON3F,
147392 +       PCF50633_IRQ_BATFULL,
147393 +       PCF50633_IRQ_CHGHALT,
147394 +       PCF50633_IRQ_THLIMON,
147395 +       PCF50633_IRQ_THLIMOFF,
147396 +       PCF50633_IRQ_USBLIMON,
147397 +       PCF50633_IRQ_USBLIMOFF,
147398 +       PCF50633_IRQ_ADCRDY,
147399 +       PCF50633_IRQ_ONKEY1S,
147400 +       PCF50633_IRQ_LOWSYS,
147401 +       PCF50633_IRQ_LOWBAT,
147402 +       PCF50633_IRQ_HIGHTMP,
147403 +       PCF50633_IRQ_AUTOPWRFAIL,
147404 +       PCF50633_IRQ_DWN1PWRFAIL,
147405 +       PCF50633_IRQ_DWN2PWRFAIL,
147406 +       PCF50633_IRQ_LEDPWRFAIL,
147407 +       PCF50633_IRQ_LEDOVP,
147408 +       PCF50633_IRQ_LDO1PWRFAIL,
147409 +       PCF50633_IRQ_LDO2PWRFAIL,
147410 +       PCF50633_IRQ_LDO3PWRFAIL,
147411 +       PCF50633_IRQ_LDO4PWRFAIL,
147412 +       PCF50633_IRQ_LDO5PWRFAIL,
147413 +       PCF50633_IRQ_LDO6PWRFAIL,
147414 +       PCF50633_IRQ_HCLDOPWRFAIL,
147415 +       PCF50633_IRQ_HCLDOOVL,
147416 +
147417 +       /* Always last */
147418 +       PCF50633_NUM_IRQ,
147419 +};
147420 +
147421 +struct pcf50633 {
147422 +       struct device *dev;
147423 +       struct i2c_client *i2c_client;
147424 +
147425 +       struct pcf50633_platform_data *pdata;
147426 +       int irq;
147427 +       struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
147428 +       struct work_struct irq_work;
147429 +       struct mutex lock;
147430 +
147431 +       u8 mask_regs[5];
147432 +
147433 +       u8 suspend_irq_masks[5];
147434 +       u8 resume_reason[5];
147435 +       int is_suspended;
147436 +
147437 +       int onkey1s_held;
147438 +
147439 +       struct pcf50633_pmic pmic;
147440 +       struct pcf50633_input input;
147441 +       struct pcf50633_mbc mbc;
147442 +       struct pcf50633_rtc rtc;
147443 +       struct pcf50633_adc adc;
147444 +};
147445 +
147446 +enum pcf50633_reg_int1 {
147447 +       PCF50633_INT1_ADPINS    = 0x01, /* Adapter inserted */
147448 +       PCF50633_INT1_ADPREM    = 0x02, /* Adapter removed */
147449 +       PCF50633_INT1_USBINS    = 0x04, /* USB inserted */
147450 +       PCF50633_INT1_USBREM    = 0x08, /* USB removed */
147451 +       /* reserved */
147452 +       PCF50633_INT1_ALARM     = 0x40, /* RTC alarm time is reached */
147453 +       PCF50633_INT1_SECOND    = 0x80, /* RTC periodic second interrupt */
147454 +};
147455 +
147456 +enum pcf50633_reg_int2 {
147457 +       PCF50633_INT2_ONKEYR    = 0x01, /* ONKEY rising edge */
147458 +       PCF50633_INT2_ONKEYF    = 0x02, /* ONKEY falling edge */
147459 +       PCF50633_INT2_EXTON1R   = 0x04, /* EXTON1 rising edge */
147460 +       PCF50633_INT2_EXTON1F   = 0x08, /* EXTON1 falling edge */
147461 +       PCF50633_INT2_EXTON2R   = 0x10, /* EXTON2 rising edge */
147462 +       PCF50633_INT2_EXTON2F   = 0x20, /* EXTON2 falling edge */
147463 +       PCF50633_INT2_EXTON3R   = 0x40, /* EXTON3 rising edge */
147464 +       PCF50633_INT2_EXTON3F   = 0x80, /* EXTON3 falling edge */
147465 +};
147466 +
147467 +enum pcf50633_reg_int3 {
147468 +       PCF50633_INT3_BATFULL   = 0x01, /* Battery full */
147469 +       PCF50633_INT3_CHGHALT   = 0x02, /* Charger halt */
147470 +       PCF50633_INT3_THLIMON   = 0x04,
147471 +       PCF50633_INT3_THLIMOFF  = 0x08,
147472 +       PCF50633_INT3_USBLIMON  = 0x10,
147473 +       PCF50633_INT3_USBLIMOFF = 0x20,
147474 +       PCF50633_INT3_ADCRDY    = 0x40, /* ADC result ready */
147475 +       PCF50633_INT3_ONKEY1S   = 0x80, /* ONKEY pressed 1 second */
147476 +};
147477 +
147478 +enum pcf50633_reg_int4 {
147479 +       PCF50633_INT4_LOWSYS            = 0x01,
147480 +       PCF50633_INT4_LOWBAT            = 0x02,
147481 +       PCF50633_INT4_HIGHTMP           = 0x04,
147482 +       PCF50633_INT4_AUTOPWRFAIL       = 0x08,
147483 +       PCF50633_INT4_DWN1PWRFAIL       = 0x10,
147484 +       PCF50633_INT4_DWN2PWRFAIL       = 0x20,
147485 +       PCF50633_INT4_LEDPWRFAIL        = 0x40,
147486 +       PCF50633_INT4_LEDOVP            = 0x80,
147487 +};
147488 +
147489 +enum pcf50633_reg_int5 {
147490 +       PCF50633_INT5_LDO1PWRFAIL       = 0x01,
147491 +       PCF50633_INT5_LDO2PWRFAIL       = 0x02,
147492 +       PCF50633_INT5_LDO3PWRFAIL       = 0x04,
147493 +       PCF50633_INT5_LDO4PWRFAIL       = 0x08,
147494 +       PCF50633_INT5_LDO5PWRFAIL       = 0x10,
147495 +       PCF50633_INT5_LDO6PWRFAIL       = 0x20,
147496 +       PCF50633_INT5_HCLDOPWRFAIL      = 0x40,
147497 +       PCF50633_INT5_HCLDOOVL          = 0x80,
147498 +};
147499 +
147500 +/* misc. registers */
147501 +#define PCF50633_REG_OOCSHDWN  0x0c
147502 +
147503 +#endif
147504 +
147505 Index: linux-2.6.28/include/linux/mfd/pcf50633/gpio.h
147506 ===================================================================
147507 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147508 +++ linux-2.6.28/include/linux/mfd/pcf50633/gpio.h      2009-01-02 00:01:57.000000000 +0100
147509 @@ -0,0 +1,51 @@
147510 +/*
147511 + * gpio.h -- GPIO driver for NXP PCF50633
147512 + *
147513 + * (C) 2006-2008 by Openmoko, Inc.
147514 + * All rights reserved.
147515 + *
147516 + * This program is free software; you can redistribute  it and/or modify it
147517 + * under  the terms of  the GNU General  Public License as published by the
147518 + * Free Software Foundation;  either version 2 of the  License, or (at your
147519 + * option) any later version.
147520 + */
147521 +
147522 +#ifndef __LINUX_MFD_PCF50633_GPIO_H
147523 +#define __LINUX_MFD_PCF50633_GPIO_H
147524 +
147525 +#define PCF50633_GPIO1 1
147526 +#define PCF50633_GPIO2 2
147527 +#define PCF50633_GPIO3 3
147528 +#define PCF50633_GPO   4
147529 +
147530 +#define PCF50633_REG_GPIO1CFG  0x14
147531 +#define PCF50633_REG_GPIO2CFG  0x15
147532 +#define PCF50633_REG_GPIO3CFG  0x16
147533 +#define PCF50633_REG_GPOCFG    0x17
147534 +
147535 +enum pcf50633_reg_gpocfg {
147536 +       PCF50633_GPOCFG_GPOSEL_0        = 0x00,
147537 +       PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
147538 +       PCF50633_GPOCFG_GPOSEL_SYSxOK   = 0x02,
147539 +       PCF50633_GPOCFG_GPOSEL_CLK32K   = 0x03,
147540 +       PCF50633_GPOCFG_GPOSEL_ADAPUSB  = 0x04,
147541 +       PCF50633_GPOCFG_GPOSEL_USBxOK   = 0x05,
147542 +       PCF50633_GPOCFG_GPOSEL_ACTPH4   = 0x06,
147543 +       PCF50633_GPOCFG_GPOSEL_1        = 0x07,
147544 +       PCF50633_GPOCFG_GPOSEL_INVERSE  = 0x08,
147545 +};
147546 +#define PCF50633_GPOCFG_GPOSEL_MASK    0x07
147547 +
147548 +struct pcf50633;
147549 +
147550 +void pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, int on);
147551 +int pcf50633_gpio_get(struct pcf50633 *pcf, int gpio);
147552 +
147553 +void pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert);
147554 +int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio);
147555 +
147556 +void pcf50633_gpio_power_supply_set(struct pcf50633 *,
147557 +                                       int gpio, int regulator, int on);
147558 +#endif /* __LINUX_MFD_PCF50633_GPIO_H */
147559 +
147560 +
147561 Index: linux-2.6.28/include/linux/mfd/pcf50633/input.h
147562 ===================================================================
147563 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147564 +++ linux-2.6.28/include/linux/mfd/pcf50633/input.h     2009-01-02 00:01:57.000000000 +0100
147565 @@ -0,0 +1,29 @@
147566 +/*
147567 + * input.h  -- Input driver for NXP PCF50633
147568 + *
147569 + * (C) 2006-2008 by Openmoko, Inc.
147570 + * All rights reserved.
147571 + *
147572 + * This program is free software; you can redistribute  it and/or modify it
147573 + * under  the terms of  the GNU General  Public License as published by the
147574 + * Free Software Foundation;  either version 2 of the  License, or (at your
147575 + * option) any later version.
147576 + */
147577 +
147578 +#ifndef __LINUX_MFD_PCF50633_INPUT_H
147579 +#define __LINUX_MFD_PCF50633_INPUT_H
147580 +
147581 +#include <linux/platform_device.h>
147582 +#include <linux/input.h>
147583 +
147584 +#define PCF50633_OOCSTAT_ONKEY 0x01
147585 +#define PCF50633_REG_OOCSTAT   0x12
147586 +#define PCF50633_REG_OOCMODE   0x10
147587 +
147588 +struct pcf50633_input {
147589 +       struct input_dev *input_dev;
147590 +       struct platform_device *pdev;
147591 +};
147592 +
147593 +#endif
147594 +
147595 Index: linux-2.6.28/include/linux/mfd/pcf50633/led.h
147596 ===================================================================
147597 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147598 +++ linux-2.6.28/include/linux/mfd/pcf50633/led.h       2009-01-02 00:01:57.000000000 +0100
147599 @@ -0,0 +1,24 @@
147600 +/*
147601 + * led.h  -- LED driver for NXP PCF50633
147602 + *
147603 + * (C) 2006-2008 by Openmoko, Inc.
147604 + * All rights reserved.
147605 + *
147606 + * This program is free software; you can redistribute  it and/or modify it
147607 + * under  the terms of  the GNU General  Public License as published by the
147608 + * Free Software Foundation;  either version 2 of the  License, or (at your
147609 + * option) any later version.
147610 + */
147611 +
147612 +#ifndef __LINUX_MFD_PCF50633_LED_H
147613 +#define __LINUX_MFD_PCF50633_LED_H
147614 +
147615 +#include <linux/platform_device.h>
147616 +
147617 +#define PCF50633_REG_LEDOUT 0x28
147618 +#define PCF50633_REG_LEDENA 0x29
147619 +#define PCF50633_REG_LEDCTL 0x2a
147620 +#define PCF50633_REG_LEDDIM 0x2b
147621 +
147622 +#endif
147623 +
147624 Index: linux-2.6.28/include/linux/mfd/pcf50633/mbc.h
147625 ===================================================================
147626 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147627 +++ linux-2.6.28/include/linux/mfd/pcf50633/mbc.h       2009-01-02 00:01:57.000000000 +0100
147628 @@ -0,0 +1,140 @@
147629 +/*
147630 + * mbc.h  -- Driver for NXP PCF50633 Main Battery Charger
147631 + *
147632 + * (C) 2006-2008 by Openmoko, Inc.
147633 + * All rights reserved.
147634 + *
147635 + * This program is free software; you can redistribute  it and/or modify it
147636 + * under  the terms of  the GNU General  Public License as published by the
147637 + * Free Software Foundation;  either version 2 of the  License, or (at your
147638 + * option) any later version.
147639 + */
147640 +
147641 +#ifndef __LINUX_MFD_PCF50633_MBC_H
147642 +#define __LINUX_MFD_PCF50633_MBC_H
147643 +
147644 +#include <linux/platform_device.h>
147645 +
147646 +#define PCF50633_REG_MBCC1     0x43
147647 +#define PCF50633_REG_MBCC2     0x44
147648 +#define PCF50633_REG_MBCC3     0x45
147649 +#define PCF50633_REG_MBCC4     0x46
147650 +#define PCF50633_REG_MBCC5     0x47
147651 +#define PCF50633_REG_MBCC6     0x48
147652 +#define PCF50633_REG_MBCC7     0x49
147653 +#define PCF50633_REG_MBCC8     0x4a
147654 +#define PCF50633_REG_MBCS1     0x4b
147655 +#define PCF50633_REG_MBCS2     0x4c
147656 +#define PCF50633_REG_MBCS3     0x4d
147657 +
147658 +enum pcf50633_reg_mbcc1 {
147659 +       PCF50633_MBCC1_CHGENA           = 0x01, /* Charger enable */
147660 +       PCF50633_MBCC1_AUTOSTOP         = 0x02,
147661 +       PCF50633_MBCC1_AUTORES          = 0x04, /* automatic resume */
147662 +       PCF50633_MBCC1_RESUME           = 0x08, /* explicit resume cmd */
147663 +       PCF50633_MBCC1_RESTART          = 0x10, /* restart charging */
147664 +       PCF50633_MBCC1_PREWDTIME_60M    = 0x20, /* max. precharging time */
147665 +       PCF50633_MBCC1_WDTIME_1H        = 0x00,
147666 +       PCF50633_MBCC1_WDTIME_2H        = 0x40,
147667 +       PCF50633_MBCC1_WDTIME_4H        = 0x80,
147668 +       PCF50633_MBCC1_WDTIME_6H        = 0xc0,
147669 +};
147670 +#define PCF50633_MBCC1_WDTIME_MASK       0xc0
147671 +
147672 +enum pcf50633_reg_mbcc2 {
147673 +       PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
147674 +       PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
147675 +       PCF50633_MBCC2_VBATCOND_3V0     = 0x02,
147676 +       PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
147677 +       PCF50633_MBCC2_VMAX_4V          = 0x00,
147678 +       PCF50633_MBCC2_VMAX_4V20        = 0x28,
147679 +       PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80, /* debounce time (32/64sec) */
147680 +};
147681 +
147682 +enum pcf50633_reg_mbcc7 {
147683 +       PCF50633_MBCC7_USB_100mA        = 0x00,
147684 +       PCF50633_MBCC7_USB_500mA        = 0x01,
147685 +       PCF50633_MBCC7_USB_1000mA       = 0x02,
147686 +       PCF50633_MBCC7_USB_SUSPEND      = 0x03,
147687 +       PCF50633_MBCC7_BATTEMP_EN       = 0x04,
147688 +       PCF50633_MBCC7_BATSYSIMAX_1A6   = 0x00,
147689 +       PCF50633_MBCC7_BATSYSIMAX_1A8   = 0x40,
147690 +       PCF50633_MBCC7_BATSYSIMAX_2A0   = 0x80,
147691 +       PCF50633_MBCC7_BATSYSIMAX_2A2   = 0xc0,
147692 +};
147693 +#define PCF50633_MBCC7_USB_MASK 0x03
147694 +
147695 +enum pcf50633_reg_mbcc8 {
147696 +       PCF50633_MBCC8_USBENASUS        = 0x10,
147697 +};
147698 +
147699 +enum pcf50633_reg_mbcs1 {
147700 +       PCF50633_MBCS1_USBPRES          = 0x01,
147701 +       PCF50633_MBCS1_USBOK            = 0x02,
147702 +       PCF50633_MBCS1_ADAPTPRES        = 0x04,
147703 +       PCF50633_MBCS1_ADAPTOK          = 0x08,
147704 +       PCF50633_MBCS1_TBAT_OK          = 0x00,
147705 +       PCF50633_MBCS1_TBAT_ABOVE       = 0x10,
147706 +       PCF50633_MBCS1_TBAT_BELOW       = 0x20,
147707 +       PCF50633_MBCS1_TBAT_UNDEF       = 0x30,
147708 +       PCF50633_MBCS1_PREWDTEXP        = 0x40,
147709 +       PCF50633_MBCS1_WDTEXP           = 0x80,
147710 +};
147711 +
147712 +enum pcf50633_reg_mbcs2_mbcmod {
147713 +       PCF50633_MBCS2_MBC_PLAY         = 0x00,
147714 +       PCF50633_MBCS2_MBC_USB_PRE      = 0x01,
147715 +       PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
147716 +       PCF50633_MBCS2_MBC_USB_FAST     = 0x03,
147717 +       PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04,
147718 +       PCF50633_MBCS2_MBC_USB_SUSPEND  = 0x05,
147719 +       PCF50633_MBCS2_MBC_ADP_PRE      = 0x06,
147720 +       PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
147721 +       PCF50633_MBCS2_MBC_ADP_FAST     = 0x08,
147722 +       PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09,
147723 +       PCF50633_MBCS2_MBC_BAT_FULL     = 0x0a,
147724 +       PCF50633_MBCS2_MBC_HALT         = 0x0b,
147725 +};
147726 +#define PCF50633_MBCS2_MBC_MASK                0x0f
147727 +enum pcf50633_reg_mbcs2_chgstat {
147728 +       PCF50633_MBCS2_CHGS_NONE        = 0x00,
147729 +       PCF50633_MBCS2_CHGS_ADAPTER     = 0x10,
147730 +       PCF50633_MBCS2_CHGS_USB         = 0x20,
147731 +       PCF50633_MBCS2_CHGS_BOTH        = 0x30,
147732 +};
147733 +#define PCF50633_MBCS2_RESSTAT_AUTO    0x40
147734 +
147735 +enum pcf50633_reg_mbcs3 {
147736 +       PCF50633_MBCS3_USBLIM_PLAY      = 0x01,
147737 +       PCF50633_MBCS3_USBLIM_CGH       = 0x02,
147738 +       PCF50633_MBCS3_TLIM_PLAY        = 0x04,
147739 +       PCF50633_MBCS3_TLIM_CHG         = 0x08,
147740 +       PCF50633_MBCS3_ILIM             = 0x10, /* 1: Ibat > Icutoff */
147741 +       PCF50633_MBCS3_VLIM             = 0x20, /* 1: Vbat == Vmax */
147742 +       PCF50633_MBCS3_VBATSTAT         = 0x40, /* 1: Vbat > Vbatcond */
147743 +       PCF50633_MBCS3_VRES             = 0x80, /* 1: Vbat > Vth(RES) */
147744 +};
147745 +
147746 +#define        PCF50633_MBCC2_VBATCOND_MASK      0x03
147747 +#define PCF50633_MBCC2_VMAX_MASK         0x3c
147748 +
147749 +struct pcf50633;
147750 +
147751 +void pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma);
147752 +
147753 +struct pcf50633_mbc {
147754 +       int adapter_active;
147755 +       int adapter_online;
147756 +       int usb_active;
147757 +       int usb_online;
147758 +
147759 +       struct power_supply ac;
147760 +       struct power_supply usb;
147761 +       struct power_supply adapter;
147762 +
147763 +       struct delayed_work charging_restart_work;
147764 +
147765 +       struct platform_device *pdev;
147766 +};
147767 +#endif
147768 +
147769 Index: linux-2.6.28/include/linux/mfd/pcf50633/pmic.h
147770 ===================================================================
147771 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147772 +++ linux-2.6.28/include/linux/mfd/pcf50633/pmic.h      2009-01-02 00:01:57.000000000 +0100
147773 @@ -0,0 +1,73 @@
147774 +#ifndef __LINUX_MFD_PCF50633_PMIC_H
147775 +#define __LINUX_MFD_PCF50633_PMIC_H
147776 +
147777 +#include <linux/platform_device.h>
147778 +
147779 +#define PCF50633_REG_AUTOOUT   0x1a
147780 +#define PCF50633_REG_AUTOENA   0x1b
147781 +#define PCF50633_REG_AUTOCTL   0x1c
147782 +#define PCF50633_REG_AUTOMXC   0x1d
147783 +#define PCF50633_REG_DOWN1OUT  0x1e
147784 +#define PCF50633_REG_DOWN1ENA  0x1f
147785 +#define PCF50633_REG_DOWN1CTL  0x20
147786 +#define PCF50633_REG_DOWN1MXC  0x21
147787 +#define        PCF50633_REG_DOWN2OUT   0x22
147788 +#define PCF50633_REG_DOWN2ENA  0x23
147789 +#define PCF50633_REG_DOWN2CTL  0x24
147790 +#define PCF50633_REG_DOWN2MXC  0x25
147791 +#define PCF50633_REG_MEMLDOOUT 0x26
147792 +#define PCF50633_REG_MEMLDOENA 0x27
147793 +#define PCF50633_REG_LDO1OUT   0x2d
147794 +#define PCF50633_REG_LDO1ENA   0x2e
147795 +#define PCF50633_REG_LDO2OUT   0x2f
147796 +#define PCF50633_REG_LDO2ENA   0x30
147797 +#define        PCF50633_REG_LDO3OUT    0x31
147798 +#define        PCF50633_REG_LDO3ENA    0x32
147799 +#define        PCF50633_REG_LDO4OUT    0x33
147800 +#define        PCF50633_REG_LDO4ENA    0x34
147801 +#define        PCF50633_REG_LDO5OUT    0x35
147802 +#define        PCF50633_REG_LDO5ENA    0x36
147803 +#define        PCF50633_REG_LDO6OUT    0x37
147804 +#define        PCF50633_REG_LDO6ENA    0x38
147805 +#define        PCF50633_REG_HCLDOOUT   0x39
147806 +#define        PCF50633_REG_HCLDOENA   0x3a
147807 +#define PCF50633_REG_HCLDOOVL  0x40
147808 +
147809 +enum pcf50633_regulator_enable {
147810 +       PCF50633_REGULATOR_ON           = 0x01,
147811 +       PCF50633_REGULATOR_ON_GPIO1     = 0x02,
147812 +       PCF50633_REGULATOR_ON_GPIO2     = 0x04,
147813 +       PCF50633_REGULATOR_ON_GPIO3     = 0x08,
147814 +};
147815 +#define PCF50633_REGULATOR_ON_MASK     0x0f
147816 +
147817 +enum pcf50633_regulator_phase {
147818 +       PCF50633_REGULATOR_ACTPH1       = 0x00,
147819 +       PCF50633_REGULATOR_ACTPH2       = 0x10,
147820 +       PCF50633_REGULATOR_ACTPH3       = 0x20,
147821 +       PCF50633_REGULATOR_ACTPH4       = 0x30,
147822 +};
147823 +#define PCF50633_REGULATOR_ACTPH_MASK  0x30
147824 +
147825 +
147826 +enum pcf50633_regulator_id {
147827 +       PCF50633_REGULATOR_AUTO,
147828 +       PCF50633_REGULATOR_DOWN1,
147829 +       PCF50633_REGULATOR_DOWN2,
147830 +       PCF50633_REGULATOR_LDO1,
147831 +       PCF50633_REGULATOR_LDO2,
147832 +       PCF50633_REGULATOR_LDO3,
147833 +       PCF50633_REGULATOR_LDO4,
147834 +       PCF50633_REGULATOR_LDO5,
147835 +       PCF50633_REGULATOR_LDO6,
147836 +       PCF50633_REGULATOR_HCLDO,
147837 +       PCF50633_REGULATOR_MEMLDO,
147838 +
147839 +       PCF50633_NUM_REGULATORS
147840 +};
147841 +
147842 +struct pcf50633_pmic {
147843 +       struct platform_device *pdev[PCF50633_NUM_REGULATORS];
147844 +};
147845 +#endif
147846 +
147847 Index: linux-2.6.28/include/linux/mfd/pcf50633/rtc.h
147848 ===================================================================
147849 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147850 +++ linux-2.6.28/include/linux/mfd/pcf50633/rtc.h       2009-01-02 00:01:57.000000000 +0100
147851 @@ -0,0 +1,43 @@
147852 +/*
147853 + * rtc.h  -- RTC driver for NXP PCF50633
147854 + *
147855 + * (C) 2006-2008 by Openmoko, Inc.
147856 + * All rights reserved.
147857 + *
147858 + * This program is free software; you can redistribute  it and/or modify it
147859 + * under  the terms of  the GNU General  Public License as published by the
147860 + * Free Software Foundation;  either version 2 of the  License, or (at your
147861 + * option) any later version.
147862 + */
147863 +
147864 +#ifndef __LINUX_MFD_PCF50633_RTC_H
147865 +#define __LINUX_MFD_PCF50633_RTC_H
147866 +
147867 +#include <linux/rtc.h>
147868 +#include <linux/platform_device.h>
147869 +
147870 +#define PCF50633_REG_RTCSC     0x59 /* Second */
147871 +#define PCF50633_REG_RTCMN     0x5a /* Minute */
147872 +#define PCF50633_REG_RTCHR     0x5b /* Hour */
147873 +#define PCF50633_REG_RTCWD     0x5c /* Weekday */
147874 +#define PCF50633_REG_RTCDT     0x5d /* Day */
147875 +#define PCF50633_REG_RTCMT     0x5e /* Month */
147876 +#define PCF50633_REG_RTCYR     0x5f /* Year */
147877 +#define PCF50633_REG_RTCSCA    0x60 /* Alarm Second */
147878 +#define PCF50633_REG_RTCMNA    0x61 /* Alarm Minute */
147879 +#define PCF50633_REG_RTCHRA    0x62 /* Alarm Hour */
147880 +#define PCF50633_REG_RTCWDA    0x63 /* Alarm Weekday */
147881 +#define PCF50633_REG_RTCDTA    0x64 /* Alarm Day */
147882 +#define PCF50633_REG_RTCMTA    0x65 /* Alarm Month */
147883 +#define PCF50633_REG_RTCYRA    0x66 /* Alarm Year */
147884 +
147885 +struct pcf50633_rtc {
147886 +       int alarm_enabled;
147887 +       int second_enabled;
147888 +
147889 +       struct rtc_device *rtc_dev;
147890 +       struct platform_device *pdev;
147891 +};
147892 +
147893 +#endif
147894 +
147895 Index: linux-2.6.28/include/linux/mmc/core.h
147896 ===================================================================
147897 --- linux-2.6.28.orig/include/linux/mmc/core.h  2008-12-25 00:26:37.000000000 +0100
147898 +++ linux-2.6.28/include/linux/mmc/core.h       2009-01-02 00:01:57.000000000 +0100
147899 @@ -129,6 +129,8 @@ struct mmc_request {
147900  struct mmc_host;
147901  struct mmc_card;
147902
147903 +extern void mmc_flush_scheduled_work(void);
147904 +
147905  extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
147906  extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
147907  extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
147908 Index: linux-2.6.28/include/linux/mmc/sdio_ids.h
147909 ===================================================================
147910 --- linux-2.6.28.orig/include/linux/mmc/sdio_ids.h      2008-12-25 00:26:37.000000000 +0100
147911 +++ linux-2.6.28/include/linux/mmc/sdio_ids.h   2009-01-02 00:01:57.000000000 +0100
147912 @@ -25,5 +25,8 @@
147913
147914  #define SDIO_VENDOR_ID_MARVELL                 0x02df
147915  #define SDIO_DEVICE_ID_MARVELL_LIBERTAS                0x9103
147916 +#define SDIO_DEVICE_ID_MARVELL_88W8688         0x9104
147917 +#define SDIO_VENDOR_ID_ATHEROS                 0x0271
147918 +#define SDIO_DEVICE_ID_ATHEROS_AR6000          0x0100
147919
147920  #endif
147921 Index: linux-2.6.28/include/linux/mm.h
147922 ===================================================================
147923 --- linux-2.6.28.orig/include/linux/mm.h        2008-12-25 00:26:37.000000000 +0100
147924 +++ linux-2.6.28/include/linux/mm.h     2009-01-02 00:01:57.000000000 +0100
147925 @@ -714,7 +714,7 @@ static inline int shmem_lock(struct file
147926  }
147927  #endif
147928  struct file *shmem_file_setup(char *name, loff_t size, unsigned long flags);
147929 -
147930 +void shmem_set_file(struct vm_area_struct *, struct file *);
147931  int shmem_zero_setup(struct vm_area_struct *);
147932
147933  #ifndef CONFIG_MMU
147934 Index: linux-2.6.28/include/linux/pcf50606.h
147935 ===================================================================
147936 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
147937 +++ linux-2.6.28/include/linux/pcf50606.h       2009-01-02 00:01:57.000000000 +0100
147938 @@ -0,0 +1,91 @@
147939 +#ifndef _LINUX_PCF50606_H
147940 +#define _LINUX_PCF50606_H
147941 +
147942 +#include <linux/pcf506xx.h>
147943 +
147944 +
147945 +/* public in-kernel pcf50606 api */
147946 +enum pcf50606_regulator_id {
147947 +       PCF50606_REGULATOR_DCD,
147948 +       PCF50606_REGULATOR_DCDE,
147949 +       PCF50606_REGULATOR_DCUD,
147950 +       PCF50606_REGULATOR_D1REG,
147951 +       PCF50606_REGULATOR_D2REG,
147952 +       PCF50606_REGULATOR_D3REG,
147953 +       PCF50606_REGULATOR_LPREG,
147954 +       PCF50606_REGULATOR_IOREG,
147955 +       __NUM_PCF50606_REGULATORS
147956 +};
147957 +
147958 +struct pcf50606_data;
147959 +
147960 +/* This is an ugly construct on how to access the (currently single/global)
147961 + * pcf50606 handle from other code in the kernel.  I didn't really come up with
147962 + * a more decent method of dynamically resolving this */
147963 +extern struct pcf50606_data *pcf50606_global;
147964 +
147965 +extern void
147966 +pcf50606_go_standby(void);
147967 +
147968 +extern void
147969 +pcf50606_gpo0_set(struct pcf50606_data *pcf, int on);
147970 +
147971 +extern int
147972 +pcf50606_gpo0_get(struct pcf50606_data *pcf);
147973 +
147974 +extern int
147975 +pcf50606_voltage_set(struct pcf50606_data *pcf,
147976 +                    enum pcf50606_regulator_id reg,
147977 +                    unsigned int millivolts);
147978 +extern unsigned int
147979 +pcf50606_voltage_get(struct pcf50606_data *pcf,
147980 +                    enum pcf50606_regulator_id reg);
147981 +extern int
147982 +pcf50606_onoff_get(struct pcf50606_data *pcf,
147983 +                  enum pcf50606_regulator_id reg);
147984 +
147985 +extern int
147986 +pcf50606_onoff_set(struct pcf50606_data *pcf,
147987 +                  enum pcf50606_regulator_id reg, int on);
147988 +
147989 +extern void
147990 +pcf50606_charge_fast(struct pcf50606_data *pcf, int on);
147991 +
147992 +
147993 +#define PCF50606_FEAT_EXTON    0x00000001      /* not yet supported */
147994 +#define PCF50606_FEAT_MBC      0x00000002
147995 +#define PCF50606_FEAT_BBC      0x00000004      /* not yet supported */
147996 +#define PCF50606_FEAT_TSC      0x00000008      /* not yet supported */
147997 +#define PCF50606_FEAT_WDT      0x00000010
147998 +#define PCF50606_FEAT_ACD      0x00000020
147999 +#define PCF50606_FEAT_RTC      0x00000040
148000 +#define PCF50606_FEAT_PWM      0x00000080
148001 +#define PCF50606_FEAT_CHGCUR   0x00000100
148002 +#define PCF50606_FEAT_BATVOLT  0x00000200
148003 +#define PCF50606_FEAT_BATTEMP  0x00000400
148004 +#define PCF50606_FEAT_PWM_BL   0x00000800
148005 +
148006 +struct pcf50606_platform_data {
148007 +       /* general */
148008 +       unsigned int used_features;
148009 +       unsigned int onkey_seconds_required;
148010 +
148011 +       /* voltage regulator related */
148012 +       struct pmu_voltage_rail rails[__NUM_PCF50606_REGULATORS];
148013 +       unsigned int used_regulators;
148014 +
148015 +       /* charger related */
148016 +       unsigned int r_fix_batt;
148017 +       unsigned int r_fix_batt_par;
148018 +       unsigned int r_sense_milli;
148019 +
148020 +       /* backlight related */
148021 +       unsigned int init_brightness;
148022 +
148023 +       struct {
148024 +               u_int8_t mbcc3; /* charger voltage / current */
148025 +       } charger;
148026 +       pmu_cb cb;
148027 +};
148028 +
148029 +#endif
148030 Index: linux-2.6.28/include/linux/pcf50633.h
148031 ===================================================================
148032 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148033 +++ linux-2.6.28/include/linux/pcf50633.h       2009-01-02 00:01:57.000000000 +0100
148034 @@ -0,0 +1,618 @@
148035 +#ifndef _LINUX_PCF50633_H
148036 +#define _LINUX_PCF50633_H
148037 +
148038 +#include <linux/pcf506xx.h>
148039 +#include <linux/regulator/machine.h>
148040 +
148041 +#define PCF50633_FIDX_CHG_ENABLED      0       /* Charger enabled */
148042 +#define PCF50633_FIDX_CHG_PRESENT      1       /* Charger present */
148043 +#define PCF50633_FIDX_CHG_ERR          3       /* Charger Error */
148044 +#define PCF50633_FIDX_CHG_PROT         4       /* Charger Protection */
148045 +#define PCF50633_FIDX_CHG_READY                5       /* Charging completed */
148046 +#define PCF50633_FIDX_PWR_PRESSED      8
148047 +#define PCF50633_FIDX_RTC_SECOND       9
148048 +#define PCF50633_FIDX_USB_PRESENT      10
148049 +
148050 +#define PCF50633_F_CHG_ENABLED (1 << PCF50633_FIDX_CHG_ENABLED)
148051 +#define PCF50633_F_CHG_PRESENT (1 << PCF50633_FIDX_CHG_PRESENT)
148052 +#define PCF50633_F_CHG_ERR     (1 << PCF50633_FIDX_CHG_ERR)
148053 +#define PCF50633_F_CHG_PROT    (1 << PCF50633_FIDX_CHG_PROT)
148054 +#define PCF50633_F_CHG_READY   (1 << PCF50633_FIDX_CHG_READY)
148055 +
148056 +#define PCF50633_F_CHG_MASK    0x000000fc
148057 +
148058 +#define PCF50633_F_PWR_PRESSED (1 << PCF50633_FIDX_PWR_PRESSED)
148059 +
148060 +#define PCF50633_F_RTC_SECOND  (1 << PCF50633_FIDX_RTC_SECOND)
148061 +#define PCF50633_F_USB_PRESENT (1 << PCF50633_FIDX_USB_PRESENT)
148062 +
148063 +/* public in-kernel pcf50633 api */
148064 +enum pcf50633_regulator_id {
148065 +       PCF50633_REGULATOR_AUTO,
148066 +       PCF50633_REGULATOR_DOWN1,
148067 +       PCF50633_REGULATOR_DOWN2,
148068 +       PCF50633_REGULATOR_LDO1,
148069 +       PCF50633_REGULATOR_LDO2,
148070 +       PCF50633_REGULATOR_LDO3,
148071 +       PCF50633_REGULATOR_LDO4,
148072 +       PCF50633_REGULATOR_LDO5,
148073 +       PCF50633_REGULATOR_LDO6,
148074 +       PCF50633_REGULATOR_HCLDO,
148075 +       PCF50633_REGULATOR_MEMLDO,
148076 +       __NUM_PCF50633_REGULATORS
148077 +};
148078 +
148079 +enum pcf50633_reg_int1 {
148080 +       PCF50633_INT1_ADPINS    = 0x01, /* Adapter inserted */
148081 +       PCF50633_INT1_ADPREM    = 0x02, /* Adapter removed */
148082 +       PCF50633_INT1_USBINS    = 0x04, /* USB inserted */
148083 +       PCF50633_INT1_USBREM    = 0x08, /* USB removed */
148084 +       /* reserved */
148085 +       PCF50633_INT1_ALARM     = 0x40, /* RTC alarm time is reached */
148086 +       PCF50633_INT1_SECOND    = 0x80, /* RTC periodic second interrupt */
148087 +};
148088 +
148089 +enum pcf50633_reg_int2 {
148090 +       PCF50633_INT2_ONKEYR    = 0x01, /* ONKEY rising edge */
148091 +       PCF50633_INT2_ONKEYF    = 0x02, /* ONKEY falling edge */
148092 +       PCF50633_INT2_EXTON1R   = 0x04, /* EXTON1 rising edge */
148093 +       PCF50633_INT2_EXTON1F   = 0x08, /* EXTON1 falling edge */
148094 +       PCF50633_INT2_EXTON2R   = 0x10, /* EXTON2 rising edge */
148095 +       PCF50633_INT2_EXTON2F   = 0x20, /* EXTON2 falling edge */
148096 +       PCF50633_INT2_EXTON3R   = 0x40, /* EXTON3 rising edge */
148097 +       PCF50633_INT2_EXTON3F   = 0x80, /* EXTON3 falling edge */
148098 +};
148099 +
148100 +enum pcf50633_reg_int3 {
148101 +       PCF50633_INT3_BATFULL   = 0x01, /* Battery full */
148102 +       PCF50633_INT3_CHGHALT   = 0x02, /* Charger halt */
148103 +       PCF50633_INT3_THLIMON   = 0x04,
148104 +       PCF50633_INT3_THLIMOFF  = 0x08,
148105 +       PCF50633_INT3_USBLIMON  = 0x10,
148106 +       PCF50633_INT3_USBLIMOFF = 0x20,
148107 +       PCF50633_INT3_ADCRDY    = 0x40, /* ADC conversion finished */
148108 +       PCF50633_INT3_ONKEY1S   = 0x80, /* ONKEY pressed 1 second */
148109 +};
148110 +
148111 +enum pcf50633_reg_int4 {
148112 +       PCF50633_INT4_LOWSYS            = 0x01,
148113 +       PCF50633_INT4_LOWBAT            = 0x02,
148114 +       PCF50633_INT4_HIGHTMP           = 0x04,
148115 +       PCF50633_INT4_AUTOPWRFAIL       = 0x08,
148116 +       PCF50633_INT4_DWN1PWRFAIL       = 0x10,
148117 +       PCF50633_INT4_DWN2PWRFAIL       = 0x20,
148118 +       PCF50633_INT4_LEDPWRFAIL        = 0x40,
148119 +       PCF50633_INT4_LEDOVP            = 0x80,
148120 +};
148121 +
148122 +enum pcf50633_reg_int5 {
148123 +       PCF50633_INT5_LDO1PWRFAIL       = 0x01,
148124 +       PCF50633_INT5_LDO2PWRFAIL       = 0x02,
148125 +       PCF50633_INT5_LDO3PWRFAIL       = 0x04,
148126 +       PCF50633_INT5_LDO4PWRFAIL       = 0x08,
148127 +       PCF50633_INT5_LDO5PWRFAIL       = 0x10,
148128 +       PCF50633_INT5_LDO6PWRFAIL       = 0x20,
148129 +       PCF50633_INT5_HCLDOPWRFAIL      = 0x40,
148130 +       PCF50633_INT5_HCLDOOVL          = 0x80,
148131 +};
148132 +
148133 +struct pcf50633_data;
148134 +
148135 +extern void
148136 +pcf50633_go_standby(struct pcf50633_data *pcf);
148137 +
148138 +enum pcf50633_gpio {
148139 +       PCF50633_GPIO1 = 1,
148140 +       PCF50633_GPIO2 = 2,
148141 +       PCF50633_GPIO3 = 3,
148142 +       PCF50633_GPO = 4,
148143 +};
148144 +
148145 +extern void
148146 +pcf50633_gpio_set(struct pcf50633_data *pcf, enum pcf50633_gpio gpio, int on);
148147 +
148148 +extern int
148149 +pcf50633_gpio_get(struct pcf50633_data *pcf, enum pcf50633_gpio gpio);
148150 +
148151 +extern int
148152 +pcf50633_adc_async_read(struct pcf50633_data *pcf, int mux, int avg,
148153 +               void (*callback)(struct pcf50633_data *, void *, int),
148154 +               void *callback_param);
148155 +
148156 +extern int
148157 +pcf50633_adc_sync_read(struct pcf50633_data *pcf, int mux, int avg);
148158 +
148159 +extern void
148160 +pcf50633_backlight_resume(struct pcf50633_data *pcf);
148161 +
148162 +extern u_int16_t
148163 +pcf50633_battvolt(struct pcf50633_data *pcf);
148164 +
148165 +extern int
148166 +pcf50633_report_resumers(struct pcf50633_data *pcf, char *buf);
148167 +
148168 +extern int
148169 +pcf50633_notify_usb_current_limit_change(struct pcf50633_data *pcf,
148170 +                                                              unsigned int ma);
148171 +extern int
148172 +pcf50633_wait_for_ready(struct pcf50633_data *pcf, int timeout_ms,
148173 +                                                               char *name);
148174 +
148175 +/* 0 = initialized and resumed and ready to roll, !=0 = either not
148176 + * initialized or not resumed yet
148177 + */
148178 +extern int
148179 +pcf50633_ready(struct pcf50633_data *pcf);
148180 +
148181 +#define PCF50633_FEAT_EXTON    0x00000001      /* not yet supported */
148182 +#define PCF50633_FEAT_MBC      0x00000002
148183 +#define PCF50633_FEAT_BBC      0x00000004      /* not yet supported */
148184 +#define PCF50633_FEAT_RTC      0x00000040
148185 +#define PCF50633_FEAT_CHGCUR   0x00000100
148186 +#define PCF50633_FEAT_BATVOLT  0x00000200
148187 +#define PCF50633_FEAT_BATTEMP  0x00000400
148188 +#define PCF50633_FEAT_PWM_BL   0x00000800
148189 +
148190 +enum charger_type {
148191 +       CHARGER_TYPE_NONE = 0,
148192 +       CHARGER_TYPE_HOSTUSB,
148193 +       CHARGER_TYPE_1A
148194 +};
148195 +
148196 +#define ADC_NOM_CHG_DETECT_1A 6
148197 +#define ADC_NOM_CHG_DETECT_NONE 43
148198 +
148199 +#define MAX_ADC_FIFO_DEPTH 8
148200 +
148201 +enum pcf50633_suspend_states {
148202 +       PCF50633_SS_RUNNING,
148203 +       PCF50633_SS_STARTING_SUSPEND,
148204 +       PCF50633_SS_COMPLETED_SUSPEND,
148205 +       PCF50633_SS_RESUMING_BUT_NOT_US_YET,
148206 +       PCF50633_SS_STARTING_RESUME,
148207 +       PCF50633_SS_COMPLETED_RESUME,
148208 +};
148209 +
148210 +struct pcf50633_data;
148211 +
148212 +struct pcf50633_platform_data {
148213 +       /* general */
148214 +       unsigned int used_features;
148215 +       unsigned int onkey_seconds_sig_init;
148216 +       unsigned int onkey_seconds_shutdown;
148217 +
148218 +       /* callback to attach platform children (to enforce suspend / resume
148219 +        * ordering */
148220 +       void (*attach_child_devices)(struct device *parent_device);
148221 +
148222 +       /* charger related */
148223 +       unsigned int r_fix_batt;
148224 +       unsigned int r_fix_batt_par;
148225 +       unsigned int r_sense_milli;
148226 +       int flag_use_apm_emulation;
148227 +
148228 +       unsigned char resumers[5];
148229 +
148230 +       struct {
148231 +               u_int8_t mbcc3; /* charger voltage / current */
148232 +       } charger;
148233 +       pmu_cb cb;
148234 +
148235 +       struct regulator_init_data reg_init_data[__NUM_PCF50633_REGULATORS];
148236 +
148237 +       /* Called when a regulator has been registered */
148238 +       void (*regulator_registered)(struct pcf50633_data *pcf, int id);
148239 +
148240 +       /* Runtime data */
148241 +       struct pcf50633_data *pcf;
148242 +};
148243 +
148244 +enum pfc50633_regs {
148245 +       PCF50633_REG_VERSION    = 0x00,
148246 +       PCF50633_REG_VARIANT    = 0x01,
148247 +       PCF50633_REG_INT1       = 0x02, /* Interrupt Status */
148248 +       PCF50633_REG_INT2       = 0x03, /* Interrupt Status */
148249 +       PCF50633_REG_INT3       = 0x04, /* Interrupt Status */
148250 +       PCF50633_REG_INT4       = 0x05, /* Interrupt Status */
148251 +       PCF50633_REG_INT5       = 0x06, /* Interrupt Status */
148252 +       PCF50633_REG_INT1M      = 0x07, /* Interrupt Mask */
148253 +       PCF50633_REG_INT2M      = 0x08, /* Interrupt Mask */
148254 +       PCF50633_REG_INT3M      = 0x09, /* Interrupt Mask */
148255 +       PCF50633_REG_INT4M      = 0x0a, /* Interrupt Mask */
148256 +       PCF50633_REG_INT5M      = 0x0b, /* Interrupt Mask */
148257 +       PCF50633_REG_OOCSHDWN   = 0x0c,
148258 +       PCF50633_REG_OOCWAKE    = 0x0d,
148259 +       PCF50633_REG_OOCTIM1    = 0x0e,
148260 +       PCF50633_REG_OOCTIM2    = 0x0f,
148261 +       PCF50633_REG_OOCMODE    = 0x10,
148262 +       PCF50633_REG_OOCCTL     = 0x11,
148263 +       PCF50633_REG_OOCSTAT    = 0x12,
148264 +       PCF50633_REG_GPIOCTL    = 0x13,
148265 +       PCF50633_REG_GPIO1CFG   = 0x14,
148266 +       PCF50633_REG_GPIO2CFG   = 0x15,
148267 +       PCF50633_REG_GPIO3CFG   = 0x16,
148268 +       PCF50633_REG_GPOCFG     = 0x17,
148269 +       PCF50633_REG_BVMCTL     = 0x18,
148270 +       PCF50633_REG_SVMCTL     = 0x19,
148271 +       PCF50633_REG_AUTOOUT    = 0x1a,
148272 +       PCF50633_REG_AUTOENA    = 0x1b,
148273 +       PCF50633_REG_AUTOCTL    = 0x1c,
148274 +       PCF50633_REG_AUTOMXC    = 0x1d,
148275 +       PCF50633_REG_DOWN1OUT   = 0x1e,
148276 +       PCF50633_REG_DOWN1ENA   = 0x1f,
148277 +       PCF50633_REG_DOWN1CTL   = 0x20,
148278 +       PCF50633_REG_DOWN1MXC   = 0x21,
148279 +       PCF50633_REG_DOWN2OUT   = 0x22,
148280 +       PCF50633_REG_DOWN2ENA   = 0x23,
148281 +       PCF50633_REG_DOWN2CTL   = 0x24,
148282 +       PCF50633_REG_DOWN2MXC   = 0x25,
148283 +       PCF50633_REG_MEMLDOOUT  = 0x26,
148284 +       PCF50633_REG_MEMLDOENA  = 0x27,
148285 +       PCF50633_REG_LEDOUT     = 0x28,
148286 +       PCF50633_REG_LEDENA     = 0x29,
148287 +       PCF50633_REG_LEDCTL     = 0x2a,
148288 +       PCF50633_REG_LEDDIM     = 0x2b,
148289 +       /* reserved */
148290 +       PCF50633_REG_LDO1OUT    = 0x2d,
148291 +       PCF50633_REG_LDO1ENA    = 0x2e,
148292 +       PCF50633_REG_LDO2OUT    = 0x2f,
148293 +       PCF50633_REG_LDO2ENA    = 0x30,
148294 +       PCF50633_REG_LDO3OUT    = 0x31,
148295 +       PCF50633_REG_LDO3ENA    = 0x32,
148296 +       PCF50633_REG_LDO4OUT    = 0x33,
148297 +       PCF50633_REG_LDO4ENA    = 0x34,
148298 +       PCF50633_REG_LDO5OUT    = 0x35,
148299 +       PCF50633_REG_LDO5ENA    = 0x36,
148300 +       PCF50633_REG_LDO6OUT    = 0x37,
148301 +       PCF50633_REG_LDO6ENA    = 0x38,
148302 +       PCF50633_REG_HCLDOOUT   = 0x39,
148303 +       PCF50633_REG_HCLDOENA   = 0x3a,
148304 +       PCF50633_REG_STBYCTL1   = 0x3b,
148305 +       PCF50633_REG_STBYCTL2   = 0x3c,
148306 +       PCF50633_REG_DEBPF1     = 0x3d,
148307 +       PCF50633_REG_DEBPF2     = 0x3e,
148308 +       PCF50633_REG_DEBPF3     = 0x3f,
148309 +       PCF50633_REG_HCLDOOVL   = 0x40,
148310 +       PCF50633_REG_DCDCSTAT   = 0x41,
148311 +       PCF50633_REG_LDOSTAT    = 0x42,
148312 +       PCF50633_REG_MBCC1      = 0x43,
148313 +       PCF50633_REG_MBCC2      = 0x44,
148314 +       PCF50633_REG_MBCC3      = 0x45,
148315 +       PCF50633_REG_MBCC4      = 0x46,
148316 +       PCF50633_REG_MBCC5      = 0x47,
148317 +       PCF50633_REG_MBCC6      = 0x48,
148318 +       PCF50633_REG_MBCC7      = 0x49,
148319 +       PCF50633_REG_MBCC8      = 0x4a,
148320 +       PCF50633_REG_MBCS1      = 0x4b,
148321 +       PCF50633_REG_MBCS2      = 0x4c,
148322 +       PCF50633_REG_MBCS3      = 0x4d,
148323 +       PCF50633_REG_BBCCTL     = 0x4e,
148324 +       PCF50633_REG_ALMGAIN    = 0x4f,
148325 +       PCF50633_REG_ALMDATA    = 0x50,
148326 +       /* reserved */
148327 +       PCF50633_REG_ADCC3      = 0x52,
148328 +       PCF50633_REG_ADCC2      = 0x53,
148329 +       PCF50633_REG_ADCC1      = 0x54,
148330 +       PCF50633_REG_ADCS1      = 0x55,
148331 +       PCF50633_REG_ADCS2      = 0x56,
148332 +       PCF50633_REG_ADCS3      = 0x57,
148333 +       /* reserved */
148334 +       PCF50633_REG_RTCSC      = 0x59, /* Second */
148335 +       PCF50633_REG_RTCMN      = 0x5a, /* Minute */
148336 +       PCF50633_REG_RTCHR      = 0x5b, /* Hour */
148337 +       PCF50633_REG_RTCWD      = 0x5c, /* Weekday */
148338 +       PCF50633_REG_RTCDT      = 0x5d, /* Day */
148339 +       PCF50633_REG_RTCMT      = 0x5e, /* Month */
148340 +       PCF50633_REG_RTCYR      = 0x5f, /* Year */
148341 +       PCF50633_REG_RTCSCA     = 0x60, /* Alarm Second */
148342 +       PCF50633_REG_RTCMNA     = 0x61, /* Alarm Minute */
148343 +       PCF50633_REG_RTCHRA     = 0x62, /* Alarm Hour */
148344 +       PCF50633_REG_RTCWDA     = 0x63, /* Alarm Weekday */
148345 +       PCF50633_REG_RTCDTA     = 0x64, /* Alarm Day */
148346 +       PCF50633_REG_RTCMTA     = 0x65, /* Alarm Month */
148347 +       PCF50633_REG_RTCYRA     = 0x66, /* Alarm Year */
148348 +
148349 +       PCF50633_REG_MEMBYTE0   = 0x67,
148350 +       PCF50633_REG_MEMBYTE1   = 0x68,
148351 +       PCF50633_REG_MEMBYTE2   = 0x69,
148352 +       PCF50633_REG_MEMBYTE3   = 0x6a,
148353 +       PCF50633_REG_MEMBYTE4   = 0x6b,
148354 +       PCF50633_REG_MEMBYTE5   = 0x6c,
148355 +       PCF50633_REG_MEMBYTE6   = 0x6d,
148356 +       PCF50633_REG_MEMBYTE7   = 0x6e,
148357 +       /* reserved */
148358 +       PCF50633_REG_DCDCPFM    = 0x84,
148359 +       __NUM_PCF50633_REGS
148360 +};
148361 +
148362 +
148363 +enum pcf50633_reg_oocshdwn {
148364 +       PCF50633_OOCSHDWN_GOSTDBY       = 0x01,
148365 +       PCF50633_OOCSHDWN_TOTRST        = 0x04,
148366 +       PCF50633_OOCSHDWN_COLDBOOT      = 0x08,
148367 +};
148368 +
148369 +enum pcf50633_reg_oocwake {
148370 +       PCF50633_OOCWAKE_ONKEY          = 0x01,
148371 +       PCF50633_OOCWAKE_EXTON1         = 0x02,
148372 +       PCF50633_OOCWAKE_EXTON2         = 0x04,
148373 +       PCF50633_OOCWAKE_EXTON3         = 0x08,
148374 +       PCF50633_OOCWAKE_RTC            = 0x10,
148375 +       /* reserved */
148376 +       PCF50633_OOCWAKE_USB            = 0x40,
148377 +       PCF50633_OOCWAKE_ADP            = 0x80,
148378 +};
148379 +
148380 +enum pcf50633_reg_mbcc1 {
148381 +       PCF50633_MBCC1_CHGENA           = 0x01, /* Charger enable */
148382 +       PCF50633_MBCC1_AUTOSTOP         = 0x02,
148383 +       PCF50633_MBCC1_AUTORES          = 0x04, /* automatic resume */
148384 +       PCF50633_MBCC1_RESUME           = 0x08, /* explicit resume cmd */
148385 +       PCF50633_MBCC1_RESTART          = 0x10, /* restart charging */
148386 +       PCF50633_MBCC1_PREWDTIME_60M    = 0x20, /* max. precharging time */
148387 +       PCF50633_MBCC1_WDTIME_1H        = 0x00,
148388 +       PCF50633_MBCC1_WDTIME_2H        = 0x40,
148389 +       PCF50633_MBCC1_WDTIME_4H        = 0x80,
148390 +       PCF50633_MBCC1_WDTIME_6H        = 0xc0,
148391 +};
148392 +#define PCF50633_MBCC1_WDTIME_MASK       0xc0
148393 +
148394 +enum pcf50633_reg_mbcc2 {
148395 +       PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
148396 +       PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
148397 +       PCF50633_MBCC2_VBATCOND_3V0     = 0x02,
148398 +       PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
148399 +       PCF50633_MBCC2_VMAX_4V          = 0x00,
148400 +       PCF50633_MBCC2_VMAX_4V20        = 0x28,
148401 +       PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80, /* debounce time (32/64sec) */
148402 +};
148403 +#define        PCF50633_MBCC2_VBATCOND_MASK      0x03
148404 +#define PCF50633_MBCC2_VMAX_MASK         0x3c
148405 +
148406 +enum pcf50633_reg_adcc1 {
148407 +       PCF50633_ADCC1_ADCSTART         = 0x01,
148408 +       PCF50633_ADCC1_RES_10BIT        = 0x02,
148409 +       PCF50633_ADCC1_AVERAGE_NO       = 0x00,
148410 +       PCF50633_ADCC1_AVERAGE_4        = 0x04,
148411 +       PCF50633_ADCC1_AVERAGE_8        = 0x08,
148412 +       PCF50633_ADCC1_AVERAGE_16       = 0x0c,
148413 +
148414 +       PCF50633_ADCC1_MUX_BATSNS_RES   = 0x00,
148415 +       PCF50633_ADCC1_MUX_BATSNS_SUBTR = 0x10,
148416 +       PCF50633_ADCC1_MUX_ADCIN2_RES   = 0x20,
148417 +       PCF50633_ADCC1_MUX_ADCIN2_SUBTR = 0x30,
148418 +       PCF50633_ADCC1_MUX_BATTEMP      = 0x60,
148419 +       PCF50633_ADCC1_MUX_ADCIN1       = 0x70,
148420 +};
148421 +#define PCF50633_ADCC1_AVERAGE_MASK    0x0c
148422 +#define        PCF50633_ADCC1_ADCMUX_MASK      0xf0
148423 +
148424 +enum pcf50633_reg_adcc2 {
148425 +       PCF50633_ADCC2_RATIO_NONE       = 0x00,
148426 +       PCF50633_ADCC2_RATIO_BATTEMP    = 0x01,
148427 +       PCF50633_ADCC2_RATIO_ADCIN1     = 0x02,
148428 +       PCF50633_ADCC2_RATIO_BOTH       = 0x03,
148429 +       PCF50633_ADCC2_RATIOSETTL_100US = 0x04,
148430 +};
148431 +#define PCF50633_ADCC2_RATIO_MASK      0x03
148432 +
148433 +enum pcf50633_reg_adcc3 {
148434 +       PCF50633_ADCC3_ACCSW_EN         = 0x01,
148435 +       PCF50633_ADCC3_NTCSW_EN         = 0x04,
148436 +       PCF50633_ADCC3_RES_DIV_TWO      = 0x10,
148437 +       PCF50633_ADCC3_RES_DIV_THREE    = 0x00,
148438 +};
148439 +
148440 +enum pcf50633_reg_adcs3 {
148441 +       PCF50633_ADCS3_REF_NTCSW        = 0x00,
148442 +       PCF50633_ADCS3_REF_ACCSW        = 0x10,
148443 +       PCF50633_ADCS3_REF_2V0          = 0x20,
148444 +       PCF50633_ADCS3_REF_VISA         = 0x30,
148445 +       PCF50633_ADCS3_REF_2V0_2        = 0x70,
148446 +       PCF50633_ADCS3_ADCRDY           = 0x80,
148447 +};
148448 +#define PCF50633_ADCS3_ADCDAT1L_MASK   0x03
148449 +#define PCF50633_ADCS3_ADCDAT2L_MASK   0x0c
148450 +#define PCF50633_ADCS3_ADCDAT2L_SHIFT  2
148451 +#define PCF50633_ASCS3_REF_MASK                0x70
148452 +
148453 +enum pcf50633_regulator_enable {
148454 +       PCF50633_REGULATOR_ON           = 0x01,
148455 +       PCF50633_REGULATOR_ON_GPIO1     = 0x02,
148456 +       PCF50633_REGULATOR_ON_GPIO2     = 0x04,
148457 +       PCF50633_REGULATOR_ON_GPIO3     = 0x08,
148458 +};
148459 +#define PCF50633_REGULATOR_ON_MASK     0x0f
148460 +
148461 +enum pcf50633_regulator_phase {
148462 +       PCF50633_REGULATOR_ACTPH1       = 0x00,
148463 +       PCF50633_REGULATOR_ACTPH2       = 0x10,
148464 +       PCF50633_REGULATOR_ACTPH3       = 0x20,
148465 +       PCF50633_REGULATOR_ACTPH4       = 0x30,
148466 +};
148467 +#define PCF50633_REGULATOR_ACTPH_MASK  0x30
148468 +
148469 +enum pcf50633_reg_gpocfg {
148470 +       PCF50633_GPOCFG_GPOSEL_0        = 0x00,
148471 +       PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
148472 +       PCF50633_GPOCFG_GPOSEL_SYSxOK   = 0x02,
148473 +       PCF50633_GPOCFG_GPOSEL_CLK32K   = 0x03,
148474 +       PCF50633_GPOCFG_GPOSEL_ADAPUSB  = 0x04,
148475 +       PCF50633_GPOCFG_GPOSEL_USBxOK   = 0x05,
148476 +       PCF50633_GPOCFG_GPOSEL_ACTPH4   = 0x06,
148477 +       PCF50633_GPOCFG_GPOSEL_1        = 0x07,
148478 +       PCF50633_GPOCFG_GPOSEL_INVERSE  = 0x08,
148479 +};
148480 +#define PCF50633_GPOCFG_GPOSEL_MASK    0x07
148481 +
148482 +#if 0
148483 +enum pcf50633_reg_mbcc1 {
148484 +       PCF50633_MBCC1_CHGENA           = 0x01,
148485 +       PCF50633_MBCC1_AUTOSTOP         = 0x02,
148486 +       PCF50633_MBCC1_AUTORES          = 0x04,
148487 +       PCF50633_MBCC1_RESUME           = 0x08,
148488 +       PCF50633_MBCC1_RESTART          = 0x10,
148489 +       PCF50633_MBCC1_PREWDTIME_30MIN  = 0x00,
148490 +       PCF50633_MBCC1_PREWDTIME_60MIN  = 0x20,
148491 +       PCF50633_MBCC1_WDTIME_2HRS      = 0x40,
148492 +       PCF50633_MBCC1_WDTIME_4HRS      = 0x80,
148493 +       PCF50633_MBCC1_WDTIME_6HRS      = 0xc0,
148494 +};
148495 +
148496 +enum pcf50633_reg_mbcc2 {
148497 +       PCF50633_MBCC2_VBATCOND_2V7     = 0x00,
148498 +       PCF50633_MBCC2_VBATCOND_2V85    = 0x01,
148499 +       PCF50633_MBCC2_VBATCOND_3V0     = 0x02,
148500 +       PCF50633_MBCC2_VBATCOND_3V15    = 0x03,
148501 +       PCF50633_MBCC2_VRESDEBTIME_64S  = 0x80,
148502 +};
148503 +#define PCF50633_MBCC2_VMAX_MASK       0x3c
148504 +#endif
148505 +
148506 +enum pcf50633_reg_mbcc7 {
148507 +       PCF50633_MBCC7_USB_100mA        = 0x00,
148508 +       PCF50633_MBCC7_USB_500mA        = 0x01,
148509 +       PCF50633_MBCC7_USB_1000mA       = 0x02,
148510 +       PCF50633_MBCC7_USB_SUSPEND      = 0x03,
148511 +       PCF50633_MBCC7_BATTEMP_EN       = 0x04,
148512 +       PCF50633_MBCC7_BATSYSIMAX_1A6   = 0x00,
148513 +       PCF50633_MBCC7_BATSYSIMAX_1A8   = 0x40,
148514 +       PCF50633_MBCC7_BATSYSIMAX_2A0   = 0x80,
148515 +       PCF50633_MBCC7_BATSYSIMAX_2A2   = 0xc0,
148516 +};
148517 +#define PCF56033_MBCC7_USB_MASK                0x03
148518 +
148519 +enum pcf50633_reg_mbcc8 {
148520 +       PCF50633_MBCC8_USBENASUS        = 0x10,
148521 +};
148522 +
148523 +enum pcf50633_reg_mbcs1 {
148524 +       PCF50633_MBCS1_USBPRES          = 0x01,
148525 +       PCF50633_MBCS1_USBOK            = 0x02,
148526 +       PCF50633_MBCS1_ADAPTPRES        = 0x04,
148527 +       PCF50633_MBCS1_ADAPTOK          = 0x08,
148528 +       PCF50633_MBCS1_TBAT_OK          = 0x00,
148529 +       PCF50633_MBCS1_TBAT_ABOVE       = 0x10,
148530 +       PCF50633_MBCS1_TBAT_BELOW       = 0x20,
148531 +       PCF50633_MBCS1_TBAT_UNDEF       = 0x30,
148532 +       PCF50633_MBCS1_PREWDTEXP        = 0x40,
148533 +       PCF50633_MBCS1_WDTEXP           = 0x80,
148534 +};
148535 +
148536 +enum pcf50633_reg_mbcs2_mbcmod {
148537 +       PCF50633_MBCS2_MBC_PLAY         = 0x00,
148538 +       PCF50633_MBCS2_MBC_USB_PRE      = 0x01,
148539 +       PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
148540 +       PCF50633_MBCS2_MBC_USB_FAST     = 0x03,
148541 +       PCF50633_MBCS2_MBC_USB_FAST_WAIT= 0x04,
148542 +       PCF50633_MBCS2_MBC_USB_SUSPEND  = 0x05,
148543 +       PCF50633_MBCS2_MBC_ADP_PRE      = 0x06,
148544 +       PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
148545 +       PCF50633_MBCS2_MBC_ADP_FAST     = 0x08,
148546 +       PCF50633_MBCS2_MBC_ADP_FAST_WAIT= 0x09,
148547 +       PCF50633_MBCS2_MBC_BAT_FULL     = 0x0a,
148548 +       PCF50633_MBCS2_MBC_HALT         = 0x0b,
148549 +};
148550 +#define PCF50633_MBCS2_MBC_MASK                0x0f
148551 +enum pcf50633_reg_mbcs2_chgstat {
148552 +       PCF50633_MBCS2_CHGS_NONE        = 0x00,
148553 +       PCF50633_MBCS2_CHGS_ADAPTER     = 0x10,
148554 +       PCF50633_MBCS2_CHGS_USB         = 0x20,
148555 +       PCF50633_MBCS2_CHGS_BOTH        = 0x30,
148556 +};
148557 +#define PCF50633_MBCS2_RESSTAT_AUTO    0x40
148558 +
148559 +enum pcf50633_reg_mbcs3 {
148560 +       PCF50633_MBCS3_USBLIM_PLAY      = 0x01,
148561 +       PCF50633_MBCS3_USBLIM_CGH       = 0x02,
148562 +       PCF50633_MBCS3_TLIM_PLAY        = 0x04,
148563 +       PCF50633_MBCS3_TLIM_CHG         = 0x08,
148564 +       PCF50633_MBCS3_ILIM             = 0x10, /* 1: Ibat > Icutoff */
148565 +       PCF50633_MBCS3_VLIM             = 0x20, /* 1: Vbat == Vmax */
148566 +       PCF50633_MBCS3_VBATSTAT         = 0x40, /* 1: Vbat > Vbatcond */
148567 +       PCF50633_MBCS3_VRES             = 0x80, /* 1: Vbat > Vth(RES) */
148568 +};
148569 +
148570 +struct adc_request {
148571 +       int mux;
148572 +       int avg;
148573 +       int result;
148574 +       void (*callback)(struct pcf50633_data *, void *, int);
148575 +       void *callback_param;
148576 +
148577 +       /* Used in case of sync requests */
148578 +       struct completion completion;
148579 +};
148580 +
148581 +struct pcf50633_data {
148582 +       struct i2c_client *client;
148583 +       struct pcf50633_platform_data *pdata;
148584 +       struct backlight_device *backlight;
148585 +       struct mutex lock;
148586 +       unsigned int flags;
148587 +       unsigned int working;
148588 +       struct mutex working_lock;
148589 +       struct work_struct work;
148590 +       struct rtc_device *rtc;
148591 +       struct input_dev *input_dev;
148592 +       int allow_close;
148593 +       int onkey_seconds;
148594 +       int irq;
148595 +       enum pcf50633_suspend_states suspend_state;
148596 +       int usb_removal_count;
148597 +       u8 pcfirq_resume[5];
148598 +       int probe_completed;
148599 +       int suppress_onkey_events;
148600 +
148601 +       /* if he pulls battery while charging, we notice that and correctly
148602 +        * report that the charger is idle.  But there is no interrupt that
148603 +        * fires if he puts a battery back in and charging resumes.  So when
148604 +        * the battery is pulled, we run this work function looking for
148605 +        * either charger resumption or USB cable pull
148606 +        */
148607 +       struct mutex working_lock_nobat;
148608 +       struct work_struct work_nobat;
148609 +       int working_nobat;
148610 +       int usb_removal_count_nobat;
148611 +       int jiffies_last_bat_ins;
148612 +
148613 +       /* current limit notification handler stuff */
148614 +       struct mutex working_lock_usb_curlimit;
148615 +       struct work_struct work_usb_curlimit;
148616 +       int pending_curlimit;
148617 +       int usb_removal_count_usb_curlimit;
148618 +
148619 +       int last_curlim_set;
148620 +
148621 +       int coldplug_done; /* cleared by probe, set by first work service */
148622 +       int flag_bat_voltage_read; /* ipc to /sys batt voltage read func */
148623 +
148624 +       /* we have a FIFO of ADC measurement requests that are used only by
148625 +        * the workqueue service code after the ADC completion interrupt
148626 +        */
148627 +       struct adc_request *adc_queue[MAX_ADC_FIFO_DEPTH]; /* amount of averaging */
148628 +       int adc_queue_head; /* head owned by foreground code */
148629 +       int adc_queue_tail; /* tail owned by service code */
148630 +
148631 +       struct platform_device *regulator_pdev[__NUM_PCF50633_REGULATORS];
148632 +};
148633 +
148634 +/* this is to be provided by the board implementation */
148635 +extern const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS];
148636 +
148637 +int pcf50633_read(struct pcf50633_data *pcf, u_int8_t reg,
148638 +                                               int nr_regs, u_int8_t *data);
148639 +
148640 +int pcf50633_write(struct pcf50633_data *pcf, u_int8_t reg,
148641 +                                               int nr_regs, u_int8_t *data);
148642 +
148643 +int pcf50633_reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val);
148644 +
148645 +u_int8_t pcf50633_reg_read(struct pcf50633_data *pcf, u_int8_t reg);
148646 +
148647 +int pcf50633_reg_set_bit_mask(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t mask, u_int8_t val);
148648 +int pcf50633_reg_clear_bits(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t bits);
148649 +
148650 +void pcf50633_charge_autofast(int on);
148651 +#endif /* _PCF50633_H */
148652 +
148653 Index: linux-2.6.28/include/linux/pcf506xx.h
148654 ===================================================================
148655 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148656 +++ linux-2.6.28/include/linux/pcf506xx.h       2009-01-02 00:01:57.000000000 +0100
148657 @@ -0,0 +1,34 @@
148658 +#ifndef _LINUX_PCF506XX_H
148659 +#define _LINUX_PCF506XX_H
148660 +
148661 +
148662 +#define PMU_VRAIL_F_SUSPEND_ON 0x00000001      /* Remains on during suspend */
148663 +#define PMU_VRAIL_F_UNUSED     0x00000002      /* This rail is not used */
148664 +struct pmu_voltage_rail {
148665 +       char *name;
148666 +       unsigned int flags;
148667 +       struct {
148668 +               unsigned int init;
148669 +               unsigned int max;
148670 +       } voltage;
148671 +};
148672 +
148673 +enum pmu_event {
148674 +       PMU_EVT_NONE,
148675 +       PMU_EVT_INSERT,
148676 +       PMU_EVT_REMOVE,
148677 +#ifdef CONFIG_SENSORS_PCF50633
148678 +       PMU_EVT_USB_INSERT,
148679 +       PMU_EVT_USB_REMOVE,
148680 +#endif
148681 +       PMU_EVT_CHARGER_ACTIVE,
148682 +       PMU_EVT_CHARGER_IDLE,
148683 +       PMU_EVT_CHARGER_CHANGE,
148684 +       __NUM_PMU_EVTS
148685 +};
148686 +
148687 +typedef int (*pmu_cb)(struct device *dev, unsigned int feature,
148688 +                  enum pmu_event event);
148689 +
148690 +
148691 +#endif /* !_LINUX_PCF506XX_H */
148692 Index: linux-2.6.28/include/linux/regulator/pcf50633.h
148693 ===================================================================
148694 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148695 +++ linux-2.6.28/include/linux/regulator/pcf50633.h     2009-01-02 00:01:57.000000000 +0100
148696 @@ -0,0 +1,3 @@
148697 +#include <linux/pcf50633.h>
148698 +
148699 +int pcf50633_regulator_init(struct pcf50633_data *, int);
148700 Index: linux-2.6.28/include/linux/resume-dependency.h
148701 ===================================================================
148702 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148703 +++ linux-2.6.28/include/linux/resume-dependency.h      2009-01-02 00:01:57.000000000 +0100
148704 @@ -0,0 +1,114 @@
148705 +#ifndef __RESUME_DEPENDENCY_H__
148706 +#define __RESUME_DEPENDENCY_H__
148707 +
148708 +/* Resume dependency framework
148709 + *
148710 + * (C) 2008 Openmoko, Inc.
148711 + * Author: Andy Green <andy@openmoko.com>
148712 + *
148713 + * This program is free software; you can redistribute it and/or
148714 + * modify it under the terms of the GNU General Public License as
148715 + * published by the Free Software Foundation; version 2.1.
148716 + *
148717 + * This program is distributed in the hope that it will be useful,
148718 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
148719 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
148720 + * GNU General Public License for more details.
148721 + *
148722 + * You should have received a copy of the GNU General Public License
148723 + * along with this program; if not, write to the Free Software
148724 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
148725 + * MA 02111-1307 USA
148726 + *
148727 + */
148728 +
148729 +#include <linux/list.h>
148730 +
148731 +struct resume_dependency {
148732 +       struct list_head list;
148733 +
148734 +       void (*callback)(void *); /* called with context as arg */
148735 +       void * context;
148736 +       int called_flag; /* set to 1 after called, use for multi dep */
148737 +};
148738 +
148739 +/* if you are a driver accept to have other drivers as dependencies, you need to
148740 + * instantiate a struct resume_dependency above, then initialize it by invoking
148741 + * init_resume_dependency_list() on it
148742 + */
148743 +
148744 +#define init_resume_dependency_list(_head) \
148745 +       printk(KERN_INFO "##### init_resume_dependency_list(head=%p)\n", (_head)); \
148746 +       INIT_LIST_HEAD(&(_head)->list);
148747 +
148748 +
148749 +/* if your resume function depends on something else being resumed first, you
148750 + * can register the dependency by calling this in your suspend function with
148751 + * head being the list held by the thing you are dependent on, and dep being
148752 + * your struct resume_dependency
148753 + */
148754 +
148755 +#define register_resume_dependency(_head, _dep) { \
148756 +       struct list_head *_pos, *_q; \
148757 +       struct resume_dependency *_d; \
148758 +\
148759 +       printk(KERN_ERR "##### register_resume_dependency(head=%p, dep=%p)\n", (_head), (_dep)); \
148760 +       (_dep)->called_flag = 1; \
148761 +       list_for_each_safe(_pos, _q, &((_head)->list)) { \
148762 +               _d = list_entry(_pos, struct resume_dependency, list); \
148763 +               if (_d == (_dep)) { \
148764 +                       list_del(_pos); \
148765 +                       printk(KERN_ERR "#####   duplicate dependency removed first\n"); \
148766 +               } \
148767 +       } \
148768 +       list_add(&(_dep)->list, &(_head)->list); \
148769 +}
148770 +
148771 +/* In the resume function that things can be dependent on, at the end you
148772 + * invoke this macro.  This calls back the dependent resumes now it is safe to
148773 + * use the resumed thing they were dependent on.
148774 + */
148775 +
148776 +#define callback_all_resume_dependencies(_head) { \
148777 +       struct list_head *_pos, *_q; \
148778 +       struct resume_dependency *_dep; \
148779 +\
148780 +       printk(KERN_ERR "##### callback_all_resume_dependencies(head=%p)\n", (_head)); \
148781 +       list_for_each_safe(_pos, _q, &((_head)->list)) { \
148782 +               _dep = list_entry(_pos, struct resume_dependency, list); \
148783 +               printk(KERN_ERR "#####   callback list entry (head=%p, dep=%p)\n", (_head), (_dep)); \
148784 +               _dep->called_flag = 1; \
148785 +               printk(KERN_ERR "#####      callback=%p(context=%p))\n", (_dep->callback),(_dep->context)); \
148786 +               (_dep->callback)(_dep->context); \
148787 +               list_del(_pos); \
148788 +       } \
148789 +}
148790 +
148791 +/* When a dependency is added, it is not actually active; the dependent resume
148792 + * handler will function as normal.  The dependency is activated by the suspend
148793 + * handler for the driver that will be doing the callbacks.  This ensures that
148794 + * if the suspend is aborted for any reason (error, driver busy, etc), that all
148795 + * suspended drivers will resume, even if the driver upon which they are dependent
148796 + * did not suspend, and hence will not resume, and thus would be unable to perform
148797 + * the callbacks.
148798 + */
148799 +
148800 +#define activate_all_resume_dependencies(_head) { \
148801 +       struct list_head *_pos, *_q; \
148802 +       struct resume_dependency *_dep; \
148803 +\
148804 +       printk(KERN_ERR "##### activate_all_resume_dependencies(head=%p)\n", (_head)); \
148805 +       list_for_each_safe(_pos, _q, &((_head)->list)) { \
148806 +               _dep = list_entry(_pos, struct resume_dependency, list); \
148807 +               printk(KERN_ERR "#####   activating callback list entry (head=%p, dep=%p)\n", (_head), (_dep)); \
148808 +               _dep->called_flag = 0; \
148809 +       } \
148810 +}
148811 +
148812 +/* if your resume action is dependent on multiple drivers being resumed already,
148813 + * register the same callback with each driver you are dependent on, and check
148814 + * .called_flag for all of the struct resume_dependency.  When they are all 1
148815 + * you know it is the last callback and you can resume, otherwise just return
148816 + */
148817 +
148818 +#endif
148819 Index: linux-2.6.28/include/linux/rtc/pcf50633.h
148820 ===================================================================
148821 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148822 +++ linux-2.6.28/include/linux/rtc/pcf50633.h   2009-01-02 00:01:57.000000000 +0100
148823 @@ -0,0 +1,9 @@
148824 +enum pcf50633_rtc_event {
148825 +        PCF50633_RTC_EVENT_ALARM,
148826 +        PCF50633_RTC_EVENT_SECOND,
148827 +};
148828 +
148829 +extern void pcf50633_rtc_handle_event(struct pcf50633_data *pcf,
148830 +                                        enum pcf50633_rtc_event evt);
148831 +
148832 +
148833 Index: linux-2.6.28/include/linux/serial_core.h
148834 ===================================================================
148835 --- linux-2.6.28.orig/include/linux/serial_core.h       2008-12-25 00:26:37.000000000 +0100
148836 +++ linux-2.6.28/include/linux/serial_core.h    2009-01-02 00:01:57.000000000 +0100
148837 @@ -158,6 +158,8 @@
148838  /* SH-SCI */
148839  #define PORT_SCIFA     83
148840
148841 +#define PORT_S3C6400   83
148842 +
148843  #ifdef __KERNEL__
148844
148845  #include <linux/compiler.h>
148846 Index: linux-2.6.28/include/linux/spi/glamo.h
148847 ===================================================================
148848 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148849 +++ linux-2.6.28/include/linux/spi/glamo.h      2009-01-02 00:01:57.000000000 +0100
148850 @@ -0,0 +1,28 @@
148851 +#ifndef __GLAMO_SPI_H
148852 +#define __GLAMO_SPI_H
148853 +
148854 +#include <linux/glamo-gpio.h>
148855 +
148856 +struct spi_board_info;
148857 +struct glamofb_handle;
148858 +struct glamo_core;
148859 +
148860 +struct glamo_spi_info {
148861 +       unsigned long           board_size;
148862 +       struct spi_board_info   *board_info;
148863 +       struct glamofb_handle   *glamofb_handle;
148864 +};
148865 +
148866 +struct glamo_spigpio_info {
148867 +       unsigned int            pin_clk;
148868 +       unsigned int            pin_mosi;
148869 +       unsigned int            pin_miso;
148870 +       unsigned int            pin_cs;
148871 +
148872 +       unsigned int            board_size;
148873 +       struct spi_board_info   *board_info;
148874 +       struct glamo_core       *glamo;
148875 +};
148876 +
148877 +
148878 +#endif
148879 Index: linux-2.6.28/include/linux/suspend.h
148880 ===================================================================
148881 --- linux-2.6.28.orig/include/linux/suspend.h   2008-12-25 00:26:37.000000000 +0100
148882 +++ linux-2.6.28/include/linux/suspend.h        2009-01-02 00:01:57.000000000 +0100
148883 @@ -146,6 +146,12 @@ struct pbe {
148884         struct pbe *next;
148885  };
148886
148887 +/**
148888 + * global indication we are somewhere between start of suspend and end of
148889 + * resume, nonzero is true
148890 + */
148891 +extern int global_inside_suspend;
148892 +
148893  /* mm/page_alloc.c */
148894  extern void mark_free_pages(struct zone *zone);
148895
148896 Index: linux-2.6.28/include/linux/ts_filter_group.h
148897 ===================================================================
148898 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148899 +++ linux-2.6.28/include/linux/ts_filter_group.h        2009-01-02 00:01:57.000000000 +0100
148900 @@ -0,0 +1,39 @@
148901 +#ifndef __TS_FILTER_GROUP_H__
148902 +#define __TS_FILTER_GROUP_H__
148903 +
148904 +#include <linux/ts_filter.h>
148905 +
148906 +/*
148907 + * Touchscreen group filter.
148908 + *
148909 + * Copyright (C) 2008 by Openmoko, Inc.
148910 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
148911 + *
148912 + */
148913 +
148914 +struct ts_filter_group_configuration {
148915 +       int extent;
148916 +       int close_enough;
148917 +       int threshold;
148918 +       int attempts;
148919 +};
148920 +
148921 +struct ts_filter_group {
148922 +       struct ts_filter tsf;
148923 +       struct ts_filter_group_configuration *config;
148924 +
148925 +       int N;          /* How many samples we have */
148926 +       int *samples[MAX_TS_FILTER_COORDS];     /* the samples, our input */
148927 +
148928 +       int *group_size;        /* used for temporal computations */
148929 +       int *sorted_samples;    /* used for temporal computations */
148930 +
148931 +       int range_max[MAX_TS_FILTER_COORDS];    /* max computed ranges */
148932 +       int range_min[MAX_TS_FILTER_COORDS];    /* min computed ranges */
148933 +
148934 +       int tries_left;         /* We finish if we don't get enough samples */
148935 +};
148936 +
148937 +extern struct ts_filter_api ts_filter_group_api;
148938 +
148939 +#endif
148940 Index: linux-2.6.28/include/linux/ts_filter.h
148941 ===================================================================
148942 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
148943 +++ linux-2.6.28/include/linux/ts_filter.h      2009-01-02 00:01:57.000000000 +0100
148944 @@ -0,0 +1,56 @@
148945 +#ifndef __TS_FILTER_H__
148946 +#define __TS_FILTER_H__
148947 +
148948 +/*
148949 + * touchscreen filter
148950 + *
148951 + * (c) 2008 Andy Green <andy@openmoko.com>
148952 + */
148953 +
148954 +#include <linux/platform_device.h>
148955 +
148956 +#define MAX_TS_FILTER_CHAIN            4  /* max filters you can chain up */
148957 +#define MAX_TS_FILTER_COORDS           3  /* X, Y and Z (pressure) */
148958 +
148959 +struct ts_filter;
148960 +
148961 +/* operations that a filter can perform
148962 + */
148963 +struct ts_filter_api {
148964 +       struct ts_filter * (*create)(struct platform_device *pdev, void *config,
148965 +                                    int count_coords);
148966 +       void (*destroy)(struct platform_device *pdev, struct ts_filter *filter);
148967 +       void (*clear)(struct ts_filter *filter);
148968 +       int (*process)(struct ts_filter *filter, int *coords);
148969 +       void (*scale)(struct ts_filter *filter, int *coords);
148970 +};
148971 +
148972 +/* this is the common part of all filters, the result
148973 + * we use this type as an otherwise opaque handle on to
148974 + * the actual filter.  Therefore you need one of these
148975 + * at the start of your actual filter struct
148976 + */
148977 +
148978 +struct ts_filter {
148979 +       struct ts_filter *next; /* next in chain */
148980 +       struct ts_filter_api *api; /* operations to use for this object */
148981 +       int count_coords;
148982 +       int coords[MAX_TS_FILTER_COORDS];
148983 +};
148984 +
148985 +/*
148986 + * helper to create a filter chain from array of API pointers and
148987 + * array of config ints... leaves pointers to created filters in list
148988 + * array and fills in ->next pointers to create the chain
148989 + */
148990 +
148991 +extern int ts_filter_create_chain(struct platform_device *pdev,
148992 +                                 struct ts_filter_api **api, void **config,
148993 +                                 struct ts_filter **list, int count_coords);
148994 +
148995 +/* helper to destroy a whole chain from the list of filter pointers */
148996 +
148997 +extern void ts_filter_destroy_chain(struct platform_device *pdev,
148998 +                                   struct ts_filter **list);
148999 +
149000 +#endif
149001 Index: linux-2.6.28/include/linux/ts_filter_linear.h
149002 ===================================================================
149003 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
149004 +++ linux-2.6.28/include/linux/ts_filter_linear.h       2009-01-02 00:01:57.000000000 +0100
149005 @@ -0,0 +1,64 @@
149006 +#ifndef __TS_FILTER_LINEAR_H__
149007 +#define __TS_FILTER_LINEAR_H__
149008 +
149009 +#include <linux/ts_filter.h>
149010 +#include <linux/kobject.h>
149011 +
149012 +/*
149013 + * touchscreen linear filter.
149014 + *
149015 + * Copyright (C) 2008 by Openmoko, Inc.
149016 + * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
149017 + *
149018 + */
149019 +
149020 +#define TS_FILTER_LINEAR_NCONSTANTS 7
149021 +
149022 +/* sysfs */
149023 +
149024 +struct ts_filter_linear;
149025 +
149026 +struct const_obj {
149027 +       struct ts_filter_linear *tsfl;
149028 +       struct kobject kobj;
149029 +};
149030 +
149031 +#define to_const_obj(x) container_of(x, struct const_obj, kobj)
149032 +
149033 +struct const_attribute {
149034 +       struct attribute attr;
149035 +       ssize_t (*show)(struct const_obj *const, struct const_attribute *attr,
149036 +                       char *buf);
149037 +       ssize_t (*store)(struct const_obj *const, struct const_attribute *attr,
149038 +                        const char *buf, size_t count);
149039 +};
149040 +
149041 +#define to_const_attr(x) container_of(x, struct const_attribute, attr)
149042 +
149043 +/* filter configuration */
149044 +
149045 +struct ts_filter_linear_configuration {
149046 +       int constants[TS_FILTER_LINEAR_NCONSTANTS];
149047 +       int coord0;
149048 +       int coord1;
149049 +};
149050 +
149051 +/* the filter */
149052 +
149053 +struct ts_filter_linear {
149054 +       struct ts_filter tsf;
149055 +       struct ts_filter_linear_configuration *config;
149056 +
149057 +       int constants[TS_FILTER_LINEAR_NCONSTANTS];
149058 +
149059 +       /* sysfs */
149060 +       struct const_obj c_obj;
149061 +       struct kobj_type const_ktype;
149062 +       struct const_attribute kattrs[TS_FILTER_LINEAR_NCONSTANTS];
149063 +       struct attribute *attrs[TS_FILTER_LINEAR_NCONSTANTS + 1];
149064 +       char attr_names[TS_FILTER_LINEAR_NCONSTANTS][2];
149065 +};
149066 +
149067 +extern struct ts_filter_api ts_filter_linear_api;
149068 +
149069 +#endif
149070 Index: linux-2.6.28/include/linux/ts_filter_mean.h
149071 ===================================================================
149072 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
149073 +++ linux-2.6.28/include/linux/ts_filter_mean.h 2009-01-02 00:01:57.000000000 +0100
149074 @@ -0,0 +1,34 @@
149075 +#ifndef __TS_FILTER_MEAN_H__
149076 +#define __TS_FILTER_MEAN_H__
149077 +
149078 +#include <linux/ts_filter.h>
149079 +
149080 +/*
149081 + * touchscreen filter
149082 + *
149083 + * mean
149084 + *
149085 + * (c) 2008 Andy Green <andy@openmoko.com>
149086 + */
149087 +
149088 +struct ts_filter_mean_configuration {
149089 +       int bits_filter_length;
149090 +       int averaging_threshold;
149091 +
149092 +       int extent;
149093 +};
149094 +
149095 +struct ts_filter_mean {
149096 +       struct ts_filter tsf;
149097 +       struct ts_filter_mean_configuration *config;
149098 +
149099 +       int reported[MAX_TS_FILTER_COORDS];
149100 +       int lowpass[MAX_TS_FILTER_COORDS];
149101 +       int *fifo[MAX_TS_FILTER_COORDS];
149102 +       int fhead[MAX_TS_FILTER_COORDS];
149103 +       int ftail[MAX_TS_FILTER_COORDS];
149104 +};
149105 +
149106 +extern struct ts_filter_api ts_filter_mean_api;
149107 +
149108 +#endif
149109 Index: linux-2.6.28/include/linux/ts_filter_median.h
149110 ===================================================================
149111 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
149112 +++ linux-2.6.28/include/linux/ts_filter_median.h       2009-01-02 00:01:57.000000000 +0100
149113 @@ -0,0 +1,36 @@
149114 +#ifndef __TS_FILTER_MEDIAN_H__
149115 +#define __TS_FILTER_MEDIAN_H__
149116 +
149117 +#include <linux/ts_filter.h>
149118 +
149119 +/*
149120 + * touchscreen filter
149121 + *
149122 + * median
149123 + *
149124 + * (c) 2008 Andy Green <andy@openmoko.com>
149125 + */
149126 +
149127 +struct ts_filter_median_configuration {
149128 +       int extent;
149129 +       int midpoint;
149130 +       int decimation_threshold;
149131 +       int decimation_above;
149132 +       int decimation_below;
149133 +};
149134 +
149135 +struct ts_filter_median {
149136 +       struct ts_filter tsf;
149137 +       struct ts_filter_median_configuration *config;
149138 +
149139 +       int decimation_count;
149140 +       int last_issued[MAX_TS_FILTER_COORDS];
149141 +       int valid; /* how many samples in the sort buffer are valid */
149142 +       int *sort[MAX_TS_FILTER_COORDS]; /* samples taken for median */
149143 +       int *fifo[MAX_TS_FILTER_COORDS]; /* samples taken for median */
149144 +       int pos; /* where we are in the fifo sample memory */
149145 +};
149146 +
149147 +extern struct ts_filter_api ts_filter_median_api;
149148 +
149149 +#endif
149150 Index: linux-2.6.28/include/linux/vt.h
149151 ===================================================================
149152 --- linux-2.6.28.orig/include/linux/vt.h        2008-12-25 00:26:37.000000000 +0100
149153 +++ linux-2.6.28/include/linux/vt.h     2009-01-02 00:01:57.000000000 +0100
149154 @@ -18,8 +18,19 @@ extern int unregister_vt_notifier(struct
149155   * resizing).
149156   */
149157  #define MIN_NR_CONSOLES 1       /* must be at least 1 */
149158 +#if (CONFIG_NR_TTY_DEVICES < 4)
149159 +/* Lower Limit */
149160 +#define MAX_NR_CONSOLES        4       /* serial lines start at 64 */
149161 +#define MAX_NR_USER_CONSOLES 4 /* must be root to allocate above this */
149162 +#elif (CONFIG_NR_TTY_DEVICES > 63)
149163 +/* Upper Limit */
149164  #define MAX_NR_CONSOLES        63      /* serial lines start at 64 */
149165  #define MAX_NR_USER_CONSOLES 63        /* must be root to allocate above this */
149166 +#else
149167 +/* They chose a sensible number */
149168 +#define MAX_NR_CONSOLES CONFIG_NR_TTY_DEVICES
149169 +#define MAX_NR_USER_CONSOLES CONFIG_NR_TTY_DEVICES
149170 +#endif
149171                 /* Note: the ioctl VT_GETSTATE does not work for
149172                    consoles 16 and higher (since it returns a short) */
149173
149174 Index: linux-2.6.28/include/sound/soc-dapm.h
149175 ===================================================================
149176 --- linux-2.6.28.orig/include/sound/soc-dapm.h  2008-12-25 00:26:37.000000000 +0100
149177 +++ linux-2.6.28/include/sound/soc-dapm.h       2009-01-02 00:01:57.000000000 +0100
149178 @@ -244,6 +244,13 @@ int snd_soc_dapm_nc_pin(struct snd_soc_c
149179  int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, char *pin);
149180  int snd_soc_dapm_sync(struct snd_soc_codec *codec);
149181
149182 +/* dapm audio endpoint control */
149183 +int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec,
149184 +       char *pin, int status);
149185 +int snd_soc_dapm_get_endpoint(struct snd_soc_codec *codec,
149186 +       char *pin);
149187 +int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec);
149188 +
149189  /* dapm widget types */
149190  enum snd_soc_dapm_type {
149191         snd_soc_dapm_input = 0,         /* input pin */
149192 Index: linux-2.6.28/init/Kconfig
149193 ===================================================================
149194 --- linux-2.6.28.orig/init/Kconfig      2008-12-25 00:26:37.000000000 +0100
149195 +++ linux-2.6.28/init/Kconfig   2009-01-02 00:01:57.000000000 +0100
149196 @@ -732,6 +732,15 @@ config AIO
149197            by some high performance threaded applications. Disabling
149198            this option saves about 7k.
149199
149200 +config ASHMEM
149201 +       bool "Enable Android's Shared Memory Subsystem"
149202 +       default n
149203 +       depends on SHMEM || TINY_SHMEM
149204 +       help
149205 +         The ashmem subsystem is a new shared memory allocator, similar to
149206 +         POSIX SHM but with different behavior and sporting a simpler
149207 +         file-based API.
149208 +
149209  config VM_EVENT_COUNTERS
149210         default y
149211         bool "Enable VM event counters for /proc/vmstat" if EMBEDDED
149212 Index: linux-2.6.28/kernel/irq/chip.c
149213 ===================================================================
149214 --- linux-2.6.28.orig/kernel/irq/chip.c 2008-12-25 00:26:37.000000000 +0100
149215 +++ linux-2.6.28/kernel/irq/chip.c      2009-01-02 00:01:57.000000000 +0100
149216 @@ -380,6 +380,7 @@ handle_level_irq(unsigned int irq, struc
149217  out_unlock:
149218         spin_unlock(&desc->lock);
149219  }
149220 +EXPORT_SYMBOL(handle_level_irq);
149221
149222  /**
149223   *     handle_fasteoi_irq - irq handler for transparent controllers
149224 @@ -583,6 +584,7 @@ __set_irq_handler(unsigned int irq, irq_
149225         }
149226         spin_unlock_irqrestore(&desc->lock, flags);
149227  }
149228 +EXPORT_SYMBOL(__set_irq_handler);
149229
149230  void
149231  set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
149232 Index: linux-2.6.28/kernel/power/main.c
149233 ===================================================================
149234 --- linux-2.6.28.orig/kernel/power/main.c       2008-12-25 00:26:37.000000000 +0100
149235 +++ linux-2.6.28/kernel/power/main.c    2009-01-02 00:01:57.000000000 +0100
149236 @@ -132,6 +132,9 @@ static inline int suspend_test(int level
149237
149238  #endif /* CONFIG_PM_SLEEP */
149239
149240 +int global_inside_suspend;
149241 +EXPORT_SYMBOL(global_inside_suspend);
149242 +
149243  #ifdef CONFIG_SUSPEND
149244
149245  #ifdef CONFIG_PM_TEST_SUSPEND
149246 @@ -322,6 +325,8 @@ int suspend_devices_and_enter(suspend_st
149247         if (!suspend_ops)
149248                 return -ENOSYS;
149249
149250 +       global_inside_suspend = 1;
149251 +
149252         if (suspend_ops->begin) {
149253                 error = suspend_ops->begin(state);
149254                 if (error)
149255 @@ -365,6 +370,8 @@ int suspend_devices_and_enter(suspend_st
149256   Close:
149257         if (suspend_ops->end)
149258                 suspend_ops->end();
149259 +       global_inside_suspend = 0;
149260 +
149261         return error;
149262
149263   Recover_platform:
149264 @@ -427,6 +434,8 @@ static int enter_state(suspend_state_t s
149265                 return -EBUSY;
149266
149267         printk(KERN_INFO "PM: Syncing filesystems ... ");
149268 +       global_inside_suspend = 1;
149269 +
149270         sys_sync();
149271         printk("done.\n");
149272
149273 Index: linux-2.6.28/kernel/printk.c
149274 ===================================================================
149275 --- linux-2.6.28.orig/kernel/printk.c   2008-12-25 00:26:37.000000000 +0100
149276 +++ linux-2.6.28/kernel/printk.c        2009-01-02 00:01:57.000000000 +0100
149277 @@ -32,8 +32,11 @@
149278  #include <linux/security.h>
149279  #include <linux/bootmem.h>
149280  #include <linux/syscalls.h>
149281 +#include <linux/jiffies.h>
149282 +#include <linux/suspend.h>
149283
149284  #include <asm/uaccess.h>
149285 +#include <asm/plat-s3c24xx/neo1973.h>
149286
149287  /*
149288   * Architectures can override it:
149289 @@ -67,6 +70,12 @@ int console_printk[4] = {
149290  int oops_in_progress;
149291  EXPORT_SYMBOL(oops_in_progress);
149292
149293 +void (*printk_emergency_debug_spew_init)(void) = NULL;
149294 +EXPORT_SYMBOL(printk_emergency_debug_spew_init);
149295 +
149296 +void (*printk_emergency_debug_spew_send_string)(const char *) = NULL;
149297 +EXPORT_SYMBOL(printk_emergency_debug_spew_send_string);
149298 +
149299  /*
149300   * console_sem protects the console_drivers list, and also
149301   * provides serialisation for access to the entire console
149302 @@ -667,8 +676,39 @@ asmlinkage int vprintk(const char *fmt,
149303         /* Emit the output into the temporary buffer */
149304         printed_len += vscnprintf(printk_buf + printed_len,
149305                                   sizeof(printk_buf) - printed_len, fmt, args);
149306 -
149307 -
149308 +#ifdef CONFIG_MACH_NEO1973_GTA02
149309 +       /* if you're debugging resume, the normal methods can change resume
149310 +        * ordering behaviours because their debugging output is synchronous
149311 +        * (ie, CONFIG_DEBUG_LL).  If your problem is an OOPS, this code
149312 +        * will not affect the speed and duration and ordering of resume
149313 +        * actions, but will give you a chance to read the full undumped
149314 +        * syslog AND the OOPS data when it happens
149315 +        *
149316 +        * if you support it, your debug device init can override the exported
149317 +        * emergency_debug_spew_init and emergency_debug_spew_send_string to
149318 +        * usually force polling or bitbanging on your debug console device
149319 +        */
149320 +       if (oops_in_progress && global_inside_suspend &&
149321 +           printk_emergency_debug_spew_init &&
149322 +           printk_emergency_debug_spew_send_string) {
149323 +               unsigned long cur_index;
149324 +               char ch[2];
149325 +
149326 +               if (global_inside_suspend == 1) {
149327 +                       (printk_emergency_debug_spew_init)();
149328 +
149329 +                       ch[1] = '\0';
149330 +                       cur_index = con_start;
149331 +                       while (cur_index != log_end) {
149332 +                               ch[0] = LOG_BUF(cur_index);
149333 +                               (printk_emergency_debug_spew_send_string)(ch);
149334 +                               cur_index++;
149335 +                       }
149336 +                       global_inside_suspend++; /* only once */
149337 +               }
149338 +               (printk_emergency_debug_spew_send_string)(printk_buf);
149339 +       }
149340 +#endif
149341         /*
149342          * Copy the output into log_buf.  If the caller didn't provide
149343          * appropriate log level tags, we insert them here
149344 Index: linux-2.6.28/kernel/timer.c
149345 ===================================================================
149346 --- linux-2.6.28.orig/kernel/timer.c    2008-12-25 00:26:37.000000000 +0100
149347 +++ linux-2.6.28/kernel/timer.c 2009-01-02 00:01:57.000000000 +0100
149348 @@ -813,7 +813,11 @@ static int cascade(struct tvec_base *bas
149349          * don't have to detach them individually.
149350          */
149351         list_for_each_entry_safe(timer, tmp, &tv_list, entry) {
149352 -               BUG_ON(tbase_get_base(timer->base) != base);
149353 +               if (tbase_get_base(timer->base) != base) {
149354 +                       printk(KERN_ERR "cascade: timer %p: tbase_get_base(timer->base) 0x%x "
149355 +                               "!= base 0x%x\n", timer, tbase_get_base(timer->base), base);
149356 +                       BUG_ON(1);
149357 +               }
149358                 internal_add_timer(base, timer);
149359         }
149360
149361 Index: linux-2.6.28/MAINTAINERS
149362 ===================================================================
149363 --- linux-2.6.28.orig/MAINTAINERS       2009-01-02 00:00:02.000000000 +0100
149364 +++ linux-2.6.28/MAINTAINERS    2009-01-02 00:01:57.000000000 +0100
149365 @@ -1705,6 +1705,20 @@ FILE LOCKING (flock() and fcntl()/lockf(
149366  P:     Matthew Wilcox
149367  M:     matthew@wil.cx
149368  L:     linux-fsdevel@vger.kernel.org
149369 +
149370 +FIC/OPENMOKO NEO1973 GSM PHONE
149371 +P:     Harald Welte
149372 +M:     laforge@openmoko.org
149373 +L:     openmoko-kernel@lists.openmoko.org
149374 +W:     http://wiki.openmoko.org/wiki/Kernel
149375 +W:     http://wiki.openmoko.org/wiki/Neo1973
149376 +S:     Maintained
149377 +
149378 +FRAMEBUFFER LAYER
149379 +P:     Antonino Daplas
149380 +M:     adaplas@gmail.com
149381 +L:     linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers)
149382 +W:     http://linux-fbdev.sourceforge.net/
149383  S:     Maintained
149384
149385  FILESYSTEMS (VFS and infrastructure)
149386 Index: linux-2.6.28/makerecovery
149387 ===================================================================
149388 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
149389 +++ linux-2.6.28/makerecovery   2009-01-02 00:01:57.000000000 +0100
149390 @@ -0,0 +1,17 @@
149391 +#!/bin/sh
149392 +#
149393 +# make 6MB recovery image from two moredrivers type kernels
149394 +# placed at start and at +4MBytes
149395 +
149396 +if [ -z "$1" ] ; then
149397 + echo "Usage: $0 uImage-moredrivers-..."
149398 + exit 1
149399 +fi
149400 +cat $1 > recovery-$1
149401 +SIZE=`ls -l $1 | tr -s ' ' ' ' | cut -d' ' -f5`
149402 +SPACE=$(( 4 * 1024 * 1024 - $SIZE ))
149403 +dd if=/dev/zero of=_spacer bs=1 count=$SPACE
149404 +cat _spacer >> recovery-$1
149405 +rm -f _spacer
149406 +cat $1 >> recovery-$1
149407 +
149408 Index: linux-2.6.28/mm/ashmem.c
149409 ===================================================================
149410 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
149411 +++ linux-2.6.28/mm/ashmem.c    2009-01-02 00:01:57.000000000 +0100
149412 @@ -0,0 +1,657 @@
149413 +/* drivers/android/ashmem.c
149414 +**
149415 +** Android / Anonymous Shared Memory Subsystem, ashmem
149416 +**
149417 +** Copyright (C) 2008 Google, Inc.
149418 +**
149419 +** Robert Love <rlove@google.com>
149420 +**
149421 +** This software is licensed under the terms of the GNU General Public
149422 +** License version 2, as published by the Free Software Foundation, and
149423 +** may be copied, distributed, and modified under those terms.
149424 +**
149425 +** This program is distributed in the hope that it will be useful,
149426 +** but WITHOUT ANY WARRANTY; without even the implied warranty of
149427 +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
149428 +** GNU General Public License for more details.
149429 +*/
149430 +
149431 +#include <linux/module.h>
149432 +#include <linux/file.h>
149433 +#include <linux/fs.h>
149434 +#include <linux/miscdevice.h>
149435 +#include <linux/security.h>
149436 +#include <linux/mm.h>
149437 +#include <linux/mman.h>
149438 +#include <linux/uaccess.h>
149439 +#include <linux/personality.h>
149440 +#include <linux/bitops.h>
149441 +#include <linux/mutex.h>
149442 +#include <linux/shmem_fs.h>
149443 +#include <linux/ashmem.h>
149444 +
149445 +/*
149446 + * ashmem_area - android shared memory area
149447 + * Lifecycle: From our parent file's open() until its release()
149448 + * Locking: Protected by `ashmem_mutex'
149449 + * Big Note: Mappings do NOT pin this structure; it dies on close()
149450 + */
149451 +struct ashmem_area {
149452 +       char name[ASHMEM_NAME_LEN];     /* optional name for /proc/pid/maps */
149453 +       struct list_head unpinned_list; /* list of all ashmem areas */
149454 +       struct file *file;              /* the shmem-based backing file */
149455 +       size_t size;                    /* size of the mapping, in bytes */
149456 +       unsigned long prot_mask;        /* allowed prot bits, as vm_flags */
149457 +};
149458 +
149459 +/*
149460 + * ashmem_range - represents an interval of unpinned (evictable) pages
149461 + * Lifecycle: From unpin to pin
149462 + * Locking: Protected by `ashmem_mutex'
149463 + */
149464 +struct ashmem_range {
149465 +       struct list_head lru;           /* entry in LRU list */
149466 +       struct list_head unpinned;      /* entry in its area's unpinned list */
149467 +       struct ashmem_area *asma;       /* associated area */
149468 +       size_t pgstart;                 /* starting page, inclusive */
149469 +       size_t pgend;                   /* ending page, inclusive */
149470 +       unsigned int purged;            /* ASHMEM_NOT or ASHMEM_WAS_PURGED */
149471 +};
149472 +
149473 +/* LRU list of unpinned pages, protected by ashmem_mutex */
149474 +static LIST_HEAD(ashmem_lru_list);
149475 +
149476 +/* Count of pages on our LRU list, protected by ashmem_mutex */
149477 +static unsigned long lru_count;
149478 +
149479 +/*
149480 + * ashmem_mutex - protects the list of and each individual ashmem_area
149481 + *
149482 + * Lock Ordering: ashmex_mutex -> i_mutex -> i_alloc_sem
149483 + */
149484 +static DEFINE_MUTEX(ashmem_mutex);
149485 +
149486 +static struct kmem_cache *ashmem_area_cachep __read_mostly;
149487 +static struct kmem_cache *ashmem_range_cachep __read_mostly;
149488 +
149489 +#define range_size(range) \
149490 +  ((range)->pgend - (range)->pgstart + 1)
149491 +
149492 +#define range_on_lru(range) \
149493 +  ((range)->purged == ASHMEM_NOT_PURGED)
149494 +
149495 +#define page_range_subsumes_range(range, start, end) \
149496 +  (((range)->pgstart >= (start)) && ((range)->pgend <= (end)))
149497 +
149498 +#define page_range_subsumed_by_range(range, start, end) \
149499 +  (((range)->pgstart <= (start)) && ((range)->pgend >= (end)))
149500 +
149501 +#define page_in_range(range, page) \
149502 + (((range)->pgstart <= (page)) && ((range)->pgend >= (page)))
149503 +
149504 +#define page_range_in_range(range, start, end) \
149505 +  (page_in_range(range, start) || page_in_range(range, end) || \
149506 +   page_range_subsumes_range(range, start, end))
149507 +
149508 +#define range_before_page(range, page) \
149509 +  ((range)->pgend < (page))
149510 +
149511 +#define PROT_MASK              (PROT_EXEC | PROT_READ | PROT_WRITE)
149512 +
149513 +static inline void lru_add(struct ashmem_range *range)
149514 +{
149515 +       list_add_tail(&range->lru, &ashmem_lru_list);
149516 +       lru_count += range_size(range);
149517 +}
149518 +
149519 +static inline void lru_del(struct ashmem_range *range)
149520 +{
149521 +       list_del(&range->lru);
149522 +       lru_count -= range_size(range);
149523 +}
149524 +
149525 +/*
149526 + * range_alloc - allocate and initialize a new ashmem_range structure
149527 + *
149528 + * 'asma' - associated ashmem_area
149529 + * 'prev_range' - the previous ashmem_range in the sorted asma->unpinned list
149530 + * 'purged' - initial purge value (ASMEM_NOT_PURGED or ASHMEM_WAS_PURGED)
149531 + * 'start' - starting page, inclusive
149532 + * 'end' - ending page, inclusive
149533 + *
149534 + * Caller must hold ashmem_mutex.
149535 + */
149536 +static int range_alloc(struct ashmem_area *asma,
149537 +                      struct ashmem_range *prev_range, unsigned int purged,
149538 +                      size_t start, size_t end)
149539 +{
149540 +       struct ashmem_range *range;
149541 +
149542 +       range = kmem_cache_zalloc(ashmem_range_cachep, GFP_KERNEL);
149543 +       if (unlikely(!range))
149544 +               return -ENOMEM;
149545 +
149546 +       range->asma = asma;
149547 +       range->pgstart = start;
149548 +       range->pgend = end;
149549 +       range->purged = purged;
149550 +
149551 +       list_add_tail(&range->unpinned, &prev_range->unpinned);
149552 +
149553 +       if (range_on_lru(range))
149554 +               lru_add(range);
149555 +
149556 +       return 0;
149557 +}
149558 +
149559 +static void range_del(struct ashmem_range *range)
149560 +{
149561 +       list_del(&range->unpinned);
149562 +       if (range_on_lru(range))
149563 +               lru_del(range);
149564 +       kmem_cache_free(ashmem_range_cachep, range);
149565 +}
149566 +
149567 +/*
149568 + * range_shrink - shrinks a range
149569 + *
149570 + * Caller must hold ashmem_mutex.
149571 + */
149572 +static inline void range_shrink(struct ashmem_range *range,
149573 +                               size_t start, size_t end)
149574 +{
149575 +       size_t pre = range_size(range);
149576 +
149577 +       range->pgstart = start;
149578 +       range->pgend = end;
149579 +
149580 +       if (range_on_lru(range))
149581 +               lru_count -= pre - range_size(range);
149582 +}
149583 +
149584 +static int ashmem_open(struct inode *inode, struct file *file)
149585 +{
149586 +       struct ashmem_area *asma;
149587 +       int ret;
149588 +
149589 +       ret = nonseekable_open(inode, file);
149590 +       if (unlikely(ret))
149591 +               return ret;
149592 +
149593 +       asma = kmem_cache_zalloc(ashmem_area_cachep, GFP_KERNEL);
149594 +       if (unlikely(!asma))
149595 +               return -ENOMEM;
149596 +
149597 +       INIT_LIST_HEAD(&asma->unpinned_list);
149598 +       asma->prot_mask = PROT_MASK;
149599 +       file->private_data = asma;
149600 +
149601 +       return 0;
149602 +}
149603 +
149604 +static int ashmem_release(struct inode *ignored, struct file *file)
149605 +{
149606 +       struct ashmem_area *asma = file->private_data;
149607 +       struct ashmem_range *range, *next;
149608 +
149609 +       mutex_lock(&ashmem_mutex);
149610 +       list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned)
149611 +               range_del(range);
149612 +       mutex_unlock(&ashmem_mutex);
149613 +
149614 +       if (asma->file)
149615 +               fput(asma->file);
149616 +       kmem_cache_free(ashmem_area_cachep, asma);
149617 +
149618 +       return 0;
149619 +}
149620 +
149621 +static int ashmem_mmap(struct file *file, struct vm_area_struct *vma)
149622 +{
149623 +       struct ashmem_area *asma = file->private_data;
149624 +       int ret = 0;
149625 +
149626 +       mutex_lock(&ashmem_mutex);
149627 +
149628 +       /* user needs to SET_SIZE before mapping */
149629 +       if (unlikely(!asma->size)) {
149630 +               ret = -EINVAL;
149631 +               goto out;
149632 +       }
149633 +
149634 +       /* requested protection bits must match our allowed protection mask */
149635 +       if (unlikely((vma->vm_flags & ~asma->prot_mask) & PROT_MASK)) {
149636 +               ret = -EPERM;
149637 +               goto out;
149638 +       }
149639 +
149640 +       if (!asma->file) {
149641 +               char *name = ASHMEM_NAME_DEF;
149642 +               struct file *vmfile;
149643 +
149644 +               if (asma->name[0] != '\0')
149645 +                       name = asma->name;
149646 +
149647 +               /* ... and allocate the backing shmem file */
149648 +               vmfile = shmem_file_setup(name, asma->size, vma->vm_flags);
149649 +               if (unlikely(IS_ERR(vmfile))) {
149650 +                       ret = PTR_ERR(vmfile);
149651 +                       goto out;
149652 +               }
149653 +               asma->file = vmfile;
149654 +       }
149655 +       get_file(asma->file);
149656 +
149657 +       shmem_set_file(vma, asma->file);
149658 +       vma->vm_flags |= VM_CAN_NONLINEAR;
149659 +
149660 +out:
149661 +       mutex_unlock(&ashmem_mutex);
149662 +       return ret;
149663 +}
149664 +
149665 +/*
149666 + * ashmem_shrink - our cache shrinker, called from mm/vmscan.c :: shrink_slab
149667 + *
149668 + * 'nr_to_scan' is the number of objects (pages) to prune, or 0 to query how
149669 + * many objects (pages) we have in total.
149670 + *
149671 + * 'gfp_mask' is the mask of the allocation that got us into this mess.
149672 + *
149673 + * Return value is the number of objects (pages) remaining, or -1 if we cannot
149674 + * proceed without risk of deadlock (due to gfp_mask).
149675 + *
149676 + * We approximate LRU via least-recently-unpinned, jettisoning unpinned partial
149677 + * chunks of ashmem regions LRU-wise one-at-a-time until we hit 'nr_to_scan'
149678 + * pages freed.
149679 + */
149680 +static int ashmem_shrink(int nr_to_scan, gfp_t gfp_mask)
149681 +{
149682 +       struct ashmem_range *range, *next;
149683 +
149684 +       /* We might recurse into filesystem code, so bail out if necessary */
149685 +       if (nr_to_scan && !(gfp_mask & __GFP_FS))
149686 +               return -1;
149687 +       if (!nr_to_scan)
149688 +               return lru_count;
149689 +
149690 +       mutex_lock(&ashmem_mutex);
149691 +       list_for_each_entry_safe(range, next, &ashmem_lru_list, lru) {
149692 +               struct inode *inode = range->asma->file->f_dentry->d_inode;
149693 +               loff_t start = range->pgstart * PAGE_SIZE;
149694 +               loff_t end = (range->pgend + 1) * PAGE_SIZE - 1;
149695 +
149696 +               vmtruncate_range(inode, start, end);
149697 +               range->purged = ASHMEM_WAS_PURGED;
149698 +               lru_del(range);
149699 +
149700 +               nr_to_scan -= range_size(range);
149701 +               if (nr_to_scan <= 0)
149702 +                       break;
149703 +       }
149704 +       mutex_unlock(&ashmem_mutex);
149705 +
149706 +       return lru_count;
149707 +}
149708 +
149709 +static struct shrinker ashmem_shrinker = {
149710 +       .shrink = ashmem_shrink,
149711 +       .seeks = DEFAULT_SEEKS * 4,
149712 +};
149713 +
149714 +static int set_prot_mask(struct ashmem_area *asma, unsigned long prot)
149715 +{
149716 +       int ret = 0;
149717 +
149718 +       mutex_lock(&ashmem_mutex);
149719 +
149720 +       /* the user can only remove, not add, protection bits */
149721 +       if (unlikely((asma->prot_mask & prot) != prot)) {
149722 +               ret = -EINVAL;
149723 +               goto out;
149724 +       }
149725 +
149726 +       /* does the application expect PROT_READ to imply PROT_EXEC? */
149727 +       if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC))
149728 +               prot |= PROT_EXEC;
149729 +
149730 +       asma->prot_mask = prot;
149731 +
149732 +out:
149733 +       mutex_unlock(&ashmem_mutex);
149734 +       return ret;
149735 +}
149736 +
149737 +static int set_name(struct ashmem_area *asma, void __user *name)
149738 +{
149739 +       int ret = 0;
149740 +
149741 +       mutex_lock(&ashmem_mutex);
149742 +
149743 +       /* cannot change an existing mapping's name */
149744 +       if (unlikely(asma->file)) {
149745 +               ret = -EINVAL;
149746 +               goto out;
149747 +       }
149748 +
149749 +       if (unlikely(copy_from_user(asma->name, name, ASHMEM_NAME_LEN)))
149750 +               ret = -EFAULT;
149751 +       asma->name[ASHMEM_NAME_LEN-1] = '\0';
149752 +
149753 +out:
149754 +       mutex_unlock(&ashmem_mutex);
149755 +
149756 +       return ret;
149757 +}
149758 +
149759 +static int get_name(struct ashmem_area *asma, void __user *name)
149760 +{
149761 +       int ret = 0;
149762 +
149763 +       mutex_lock(&ashmem_mutex);
149764 +       if (asma->name[0] != '\0') {
149765 +               size_t len;
149766 +
149767 +               /*
149768 +                * Copying only `len', instead of ASHMEM_NAME_LEN, bytes
149769 +                * prevents us from revealing one user's stack to another.
149770 +                */
149771 +               len = strlen(asma->name) + 1;
149772 +               if (unlikely(copy_to_user(name, asma->name, len)))
149773 +                       ret = -EFAULT;
149774 +       } else {
149775 +               if (unlikely(copy_to_user(name, ASHMEM_NAME_DEF,
149776 +                                         sizeof(ASHMEM_NAME_DEF))))
149777 +                       ret = -EFAULT;
149778 +       }
149779 +       mutex_unlock(&ashmem_mutex);
149780 +
149781 +       return ret;
149782 +}
149783 +
149784 +/*
149785 + * ashmem_pin - pin the given ashmem region, returning whether it was
149786 + * previously purged (ASHMEM_WAS_PURGED) or not (ASHMEM_NOT_PURGED).
149787 + *
149788 + * Caller must hold ashmem_mutex.
149789 + */
149790 +static int ashmem_pin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
149791 +{
149792 +       struct ashmem_range *range, *next;
149793 +       int ret = ASHMEM_NOT_PURGED;
149794 +
149795 +       list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
149796 +               /* moved past last applicable page; we can short circuit */
149797 +               if (range_before_page(range, pgstart))
149798 +                       break;
149799 +
149800 +               /*
149801 +                * The user can ask us to pin pages that span multiple ranges,
149802 +                * or to pin pages that aren't even unpinned, so this is messy.
149803 +                *
149804 +                * Four cases:
149805 +                * 1. The requested range subsumes an existing range, so we
149806 +                *    just remove the entire matching range.
149807 +                * 2. The requested range overlaps the start of an existing
149808 +                *    range, so we just update that range.
149809 +                * 3. The requested range overlaps the end of an existing
149810 +                *    range, so we just update that range.
149811 +                * 4. The requested range punches a hole in an existing range,
149812 +                *    so we have to update one side of the range and then
149813 +                *    create a new range for the other side.
149814 +                */
149815 +               if (page_range_in_range(range, pgstart, pgend)) {
149816 +                       ret |= range->purged;
149817 +
149818 +                       /* Case #1: Easy. Just nuke the whole thing. */
149819 +                       if (page_range_subsumes_range(range, pgstart, pgend)) {
149820 +                               range_del(range);
149821 +                               continue;
149822 +                       }
149823 +
149824 +                       /* Case #2: We overlap from the start, so adjust it */
149825 +                       if (range->pgstart >= pgstart) {
149826 +                               range_shrink(range, pgend + 1, range->pgend);
149827 +                               continue;
149828 +                       }
149829 +
149830 +                       /* Case #3: We overlap from the rear, so adjust it */
149831 +                       if (range->pgend <= pgend) {
149832 +                               range_shrink(range, range->pgstart, pgstart-1);
149833 +                               continue;
149834 +                       }
149835 +
149836 +                       /*
149837 +                        * Case #4: We eat a chunk out of the middle. A bit
149838 +                        * more complicated, we allocate a new range for the
149839 +                        * second half and adjust the first chunk's endpoint.
149840 +                        */
149841 +                       range_alloc(asma, range, range->purged,
149842 +                                   pgend + 1, range->pgend);
149843 +                       range_shrink(range, range->pgstart, pgstart - 1);
149844 +                       break;
149845 +               }
149846 +       }
149847 +
149848 +       return ret;
149849 +}
149850 +
149851 +/*
149852 + * ashmem_unpin - unpin the given range of pages. Returns zero on success.
149853 + *
149854 + * Caller must hold ashmem_mutex.
149855 + */
149856 +static int ashmem_unpin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
149857 +{
149858 +       struct ashmem_range *range, *next;
149859 +       unsigned int purged = ASHMEM_NOT_PURGED;
149860 +
149861 +restart:
149862 +       list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
149863 +               /* short circuit: this is our insertion point */
149864 +               if (range_before_page(range, pgstart))
149865 +                       break;
149866 +
149867 +               /*
149868 +                * The user can ask us to unpin pages that are already entirely
149869 +                * or partially pinned. We handle those two cases here.
149870 +                */
149871 +               if (page_range_subsumed_by_range(range, pgstart, pgend))
149872 +                       return 0;
149873 +               if (page_range_in_range(range, pgstart, pgend)) {
149874 +                       pgstart = min_t(size_t, range->pgstart, pgstart),
149875 +                       pgend = max_t(size_t, range->pgend, pgend);
149876 +                       purged |= range->purged;
149877 +                       range_del(range);
149878 +                       goto restart;
149879 +               }
149880 +       }
149881 +
149882 +       return range_alloc(asma, range, purged, pgstart, pgend);
149883 +}
149884 +
149885 +/*
149886 + * ashmem_get_pin_status - Returns ASHMEM_IS_UNPINNED if _any_ pages in the
149887 + * given interval are unpinned and ASHMEM_IS_PINNED otherwise.
149888 + *
149889 + * Caller must hold ashmem_mutex.
149890 + */
149891 +static int ashmem_get_pin_status(struct ashmem_area *asma, size_t pgstart,
149892 +                                size_t pgend)
149893 +{
149894 +       struct ashmem_range *range;
149895 +       int ret = ASHMEM_IS_PINNED;
149896 +
149897 +       list_for_each_entry(range, &asma->unpinned_list, unpinned) {
149898 +               if (range_before_page(range, pgstart))
149899 +                       break;
149900 +               if (page_range_in_range(range, pgstart, pgend)) {
149901 +                       ret = ASHMEM_IS_UNPINNED;
149902 +                       break;
149903 +               }
149904 +       }
149905 +
149906 +       return ret;
149907 +}
149908 +
149909 +static int ashmem_pin_unpin(struct ashmem_area *asma, unsigned long cmd,
149910 +                           void __user *p)
149911 +{
149912 +       struct ashmem_pin pin;
149913 +       size_t pgstart, pgend;
149914 +       int ret = -EINVAL;
149915 +
149916 +       if (unlikely(!asma->file))
149917 +               return -EINVAL;
149918 +
149919 +       if (unlikely(copy_from_user(&pin, p, sizeof(pin))))
149920 +               return -EFAULT;
149921 +
149922 +       /* per custom, you can pass zero for len to mean "everything onward" */
149923 +       if (!pin.len)
149924 +               pin.len = asma->size - pin.offset;
149925 +
149926 +       if (unlikely((pin.offset | pin.len) & ~PAGE_MASK))
149927 +               return -EINVAL;
149928 +
149929 +       if (unlikely(((__u32) -1) - pin.offset < pin.len))
149930 +               return -EINVAL;
149931 +
149932 +       if (unlikely(asma->size < pin.offset + pin.len))
149933 +               return -EINVAL;
149934 +
149935 +       pgstart = pin.offset / PAGE_SIZE;
149936 +       pgend = pgstart + (pin.len / PAGE_SIZE) - 1;
149937 +
149938 +       mutex_lock(&ashmem_mutex);
149939 +
149940 +       switch (cmd) {
149941 +       case ASHMEM_PIN:
149942 +               ret = ashmem_pin(asma, pgstart, pgend);
149943 +               break;
149944 +       case ASHMEM_UNPIN:
149945 +               ret = ashmem_unpin(asma, pgstart, pgend);
149946 +               break;
149947 +       case ASHMEM_GET_PIN_STATUS:
149948 +               ret = ashmem_get_pin_status(asma, pgstart, pgend);
149949 +               break;
149950 +       }
149951 +
149952 +       mutex_unlock(&ashmem_mutex);
149953 +
149954 +       return ret;
149955 +}
149956 +
149957 +static long ashmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
149958 +{
149959 +       struct ashmem_area *asma = file->private_data;
149960 +       long ret = -ENOTTY;
149961 +
149962 +       switch (cmd) {
149963 +       case ASHMEM_SET_NAME:
149964 +               ret = set_name(asma, (void __user *) arg);
149965 +               break;
149966 +       case ASHMEM_GET_NAME:
149967 +               ret = get_name(asma, (void __user *) arg);
149968 +               break;
149969 +       case ASHMEM_SET_SIZE:
149970 +               ret = -EINVAL;
149971 +               if (!asma->file && !(arg & ~PAGE_MASK)) {
149972 +                       ret = 0;
149973 +                       asma->size = (size_t) arg;
149974 +               }
149975 +               break;
149976 +       case ASHMEM_GET_SIZE:
149977 +               ret = asma->size;
149978 +               break;
149979 +       case ASHMEM_SET_PROT_MASK:
149980 +               ret = set_prot_mask(asma, arg);
149981 +               break;
149982 +       case ASHMEM_GET_PROT_MASK:
149983 +               ret = asma->prot_mask;
149984 +               break;
149985 +       case ASHMEM_PIN:
149986 +       case ASHMEM_UNPIN:
149987 +       case ASHMEM_GET_PIN_STATUS:
149988 +               ret = ashmem_pin_unpin(asma, cmd, (void __user *) arg);
149989 +               break;
149990 +       case ASHMEM_PURGE_ALL_CACHES:
149991 +               ret = -EPERM;
149992 +               if (capable(CAP_SYS_ADMIN)) {
149993 +                       ret = ashmem_shrink(0, GFP_KERNEL);
149994 +                       ashmem_shrink(ret, GFP_KERNEL);
149995 +               }
149996 +               break;
149997 +       }
149998 +
149999 +       return ret;
150000 +}
150001 +
150002 +static struct file_operations ashmem_fops = {
150003 +       .owner = THIS_MODULE,
150004 +       .open = ashmem_open,
150005 +       .release = ashmem_release,
150006 +       .mmap = ashmem_mmap,
150007 +       .unlocked_ioctl = ashmem_ioctl,
150008 +       .compat_ioctl = ashmem_ioctl,
150009 +};
150010 +
150011 +static struct miscdevice ashmem_misc = {
150012 +       .minor = MISC_DYNAMIC_MINOR,
150013 +       .name = "ashmem",
150014 +       .fops = &ashmem_fops,
150015 +};
150016 +
150017 +static int __init ashmem_init(void)
150018 +{
150019 +       int ret;
150020 +
150021 +       ashmem_area_cachep = kmem_cache_create("ashmem_area_cache",
150022 +                                         sizeof(struct ashmem_area),
150023 +                                         0, 0, NULL);
150024 +       if (unlikely(!ashmem_area_cachep)) {
150025 +               printk(KERN_ERR "ashmem: failed to create slab cache\n");
150026 +               return -ENOMEM;
150027 +       }
150028 +
150029 +       ashmem_range_cachep = kmem_cache_create("ashmem_range_cache",
150030 +                                         sizeof(struct ashmem_range),
150031 +                                         0, 0, NULL);
150032 +       if (unlikely(!ashmem_range_cachep)) {
150033 +               printk(KERN_ERR "ashmem: failed to create slab cache\n");
150034 +               return -ENOMEM;
150035 +       }
150036 +
150037 +       ret = misc_register(&ashmem_misc);
150038 +       if (unlikely(ret)) {
150039 +               printk(KERN_ERR "ashmem: failed to register misc device!\n");
150040 +               return ret;
150041 +       }
150042 +
150043 +       register_shrinker(&ashmem_shrinker);
150044 +
150045 +       printk(KERN_INFO "ashmem: initialized\n");
150046 +
150047 +       return 0;
150048 +}
150049 +
150050 +static void __exit ashmem_exit(void)
150051 +{
150052 +       int ret;
150053 +
150054 +       unregister_shrinker(&ashmem_shrinker);
150055 +
150056 +       ret = misc_deregister(&ashmem_misc);
150057 +       if (unlikely(ret))
150058 +               printk(KERN_ERR "ashmem: failed to unregister misc device!\n");
150059 +
150060 +       kmem_cache_destroy(ashmem_range_cachep);
150061 +       kmem_cache_destroy(ashmem_area_cachep);
150062 +
150063 +       printk(KERN_INFO "ashmem: unloaded\n");
150064 +}
150065 +
150066 +module_init(ashmem_init);
150067 +module_exit(ashmem_exit);
150068 +
150069 +MODULE_LICENSE("GPL");
150070 Index: linux-2.6.28/mm/Makefile
150071 ===================================================================
150072 --- linux-2.6.28.orig/mm/Makefile       2008-12-25 00:26:37.000000000 +0100
150073 +++ linux-2.6.28/mm/Makefile    2009-01-02 00:01:57.000000000 +0100
150074 @@ -22,6 +22,7 @@ obj-$(CONFIG_NUMA)    += mempolicy.o
150075  obj-$(CONFIG_SPARSEMEM)        += sparse.o
150076  obj-$(CONFIG_SPARSEMEM_VMEMMAP) += sparse-vmemmap.o
150077  obj-$(CONFIG_SHMEM) += shmem.o
150078 +obj-$(CONFIG_ASHMEM) += ashmem.o
150079  obj-$(CONFIG_TMPFS_POSIX_ACL) += shmem_acl.o
150080  obj-$(CONFIG_TINY_SHMEM) += tiny-shmem.o
150081  obj-$(CONFIG_SLOB) += slob.o
150082 Index: linux-2.6.28/mm/shmem.c
150083 ===================================================================
150084 --- linux-2.6.28.orig/mm/shmem.c        2008-12-25 00:26:37.000000000 +0100
150085 +++ linux-2.6.28/mm/shmem.c     2009-01-02 00:01:57.000000000 +0100
150086 @@ -2587,6 +2587,14 @@ put_memory:
150087  }
150088  EXPORT_SYMBOL_GPL(shmem_file_setup);
150089
150090 +void shmem_set_file(struct vm_area_struct *vma, struct file *file)
150091 +{
150092 +       if (vma->vm_file)
150093 +               fput(vma->vm_file);
150094 +       vma->vm_file = file;
150095 +       vma->vm_ops = &shmem_vm_ops;
150096 +}
150097 +
150098  /**
150099   * shmem_zero_setup - setup a shared anonymous mapping
150100   * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
150101 @@ -2600,9 +2608,7 @@ int shmem_zero_setup(struct vm_area_stru
150102         if (IS_ERR(file))
150103                 return PTR_ERR(file);
150104
150105 -       if (vma->vm_file)
150106 -               fput(vma->vm_file);
150107 -       vma->vm_file = file;
150108 -       vma->vm_ops = &shmem_vm_ops;
150109 +       shmem_set_file(vma, file);
150110 +
150111         return 0;
150112  }
150113 Index: linux-2.6.28/mm/tiny-shmem.c
150114 ===================================================================
150115 --- linux-2.6.28.orig/mm/tiny-shmem.c   2008-12-25 00:26:37.000000000 +0100
150116 +++ linux-2.6.28/mm/tiny-shmem.c        2009-01-02 00:01:57.000000000 +0100
150117 @@ -97,6 +97,22 @@ put_memory:
150118  }
150119  EXPORT_SYMBOL_GPL(shmem_file_setup);
150120
150121 +void shmem_set_file(struct vm_area_struct *vma, struct file *file)
150122 +{
150123 +       if (vma->vm_file)
150124 +               fput(vma->vm_file);
150125 +       vma->vm_file = file;
150126 +       vma->vm_ops = &generic_file_vm_ops;
150127 +}
150128 +
150129 +void shmem_set_file(struct vm_area_struct *vma, struct file *file)
150130 +{
150131 +       if (vma->vm_file)
150132 +               fput(vma->vm_file);
150133 +       vma->vm_file = file;
150134 +       vma->vm_ops = &generic_file_vm_ops;
150135 +}
150136 +
150137  /**
150138   * shmem_zero_setup - setup a shared anonymous mapping
150139   * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
150140 @@ -110,10 +126,8 @@ int shmem_zero_setup(struct vm_area_stru
150141         if (IS_ERR(file))
150142                 return PTR_ERR(file);
150143
150144 -       if (vma->vm_file)
150145 -               fput(vma->vm_file);
150146 -       vma->vm_file = file;
150147 -       vma->vm_ops = &generic_file_vm_ops;
150148 +       shmem_set_file(vma, file);
150149 +
150150         return 0;
150151  }
150152
150153 Index: linux-2.6.28/remote_install_sdcard
150154 ===================================================================
150155 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
150156 +++ linux-2.6.28/remote_install_sdcard  2009-01-02 00:01:58.000000000 +0100
150157 @@ -0,0 +1,18 @@
150158 +#!/bin/sh
150159 +
150160 +# automatic kernel updater and reboot - Andy Green <andy@openmoko.com>
150161 +
150162 +GTA_DEVICE_IP=192.168.0.202
150163 +
150164 +# you should set up key-based auth on dropbear if you want
150165 +# to play this game.
150166 +#
150167 +# 1) mkdir /home/root/.ssh
150168 +# 2) chown root:root / /home /home/root
150169 +# 3) chmod 700 /home/root /home/root/.ssh
150170 +# 4) copy your id_*.pub into /home/root/.ssh/authorized_keys
150171 +# 5) chmod 600 /home/root/.ssh/*
150172 +
150173 +scp uImage.bin root@$GTA_DEVICE_IP:/boot
150174 +ssh root@$GTA_DEVICE_IP "mount /dev/mmcblk0p1 / -oremount,ro ; reboot -if &"
150175 +
150176 Index: linux-2.6.28/scripts/mkuboot.sh
150177 ===================================================================
150178 --- linux-2.6.28.orig/scripts/mkuboot.sh        2008-12-25 00:26:37.000000000 +0100
150179 +++ linux-2.6.28/scripts/mkuboot.sh     2009-01-02 00:01:58.000000000 +0100
150180 @@ -11,7 +11,7 @@ if [ -z "${MKIMAGE}" ]; then
150181         if [ -z "${MKIMAGE}" ]; then
150182                 # Doesn't exist
150183                 echo '"mkimage" command not found - U-Boot images will not be built' >&2
150184 -               exit 0;
150185 +               exit 1;
150186         fi
150187  fi
150188
150189 Index: linux-2.6.28/sound/soc/codecs/wm8753.c
150190 ===================================================================
150191 --- linux-2.6.28.orig/sound/soc/codecs/wm8753.c 2008-12-25 00:26:37.000000000 +0100
150192 +++ linux-2.6.28/sound/soc/codecs/wm8753.c      2009-01-02 00:01:58.000000000 +0100
150193 @@ -1584,6 +1584,9 @@ static int wm8753_init(struct snd_soc_de
150194         schedule_delayed_work(&codec->delayed_work,
150195                 msecs_to_jiffies(caps_charge));
150196
150197 +       /* Fix reg WM8753_ADCTL2 */
150198 +       wm8753_write(codec, WM8753_ADCTL2, 0x0000);
150199 +
150200         /* set the update bits */
150201         reg = wm8753_read_reg_cache(codec, WM8753_LDAC);
150202         wm8753_write(codec, WM8753_LDAC, reg | 0x0100);
150203 @@ -1644,17 +1647,20 @@ static int wm8753_i2c_probe(struct i2c_c
150204         struct snd_soc_codec *codec = socdev->codec;
150205         int ret;
150206
150207 +       /* codec->control_data must be set before call to wm8753_init */
150208         i2c_set_clientdata(i2c, codec);
150209         codec->control_data = i2c;
150210
150211         ret = wm8753_init(socdev);
150212 -       if (ret < 0)
150213 +       if (ret < 0) {
150214                 pr_err("failed to initialise WM8753\n");
150215 +               codec->control_data = NULL;
150216 +       }
150217
150218         return ret;
150219  }
150220
150221 -static int wm8753_i2c_remove(struct i2c_client *client)
150222 +static int __devexit wm8753_i2c_remove(struct i2c_client *client)
150223  {
150224         struct snd_soc_codec *codec = i2c_get_clientdata(client);
150225         kfree(codec->reg_cache);
150226 @@ -1675,6 +1681,7 @@ static struct i2c_driver wm8753_i2c_driv
150227         .probe =    wm8753_i2c_probe,
150228         .remove =   wm8753_i2c_remove,
150229         .id_table = wm8753_i2c_id,
150230 +       .class =    I2C_CLASS_SOUND
150231  };
150232
150233  static int wm8753_add_i2c_device(struct platform_device *pdev,
150234 @@ -1716,6 +1723,8 @@ err_driver:
150235         i2c_del_driver(&wm8753_i2c_driver);
150236         return -ENODEV;
150237  }
150238 +
150239 +
150240  #endif
150241
150242  #if defined(CONFIG_SPI_MASTER)
150243 @@ -1783,7 +1792,7 @@ static int wm8753_probe(struct platform_
150244         struct wm8753_priv *wm8753;
150245         int ret = 0;
150246
150247 -       pr_info("WM8753 Audio Codec %s", WM8753_VERSION);
150248 +       pr_info("WM8753 Audio Codec %s\n", WM8753_VERSION);
150249
150250         setup = socdev->codec_data;
150251         codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
150252 @@ -1820,6 +1829,7 @@ static int wm8753_probe(struct platform_
150253  #endif
150254
150255         if (ret != 0) {
150256 +               printk(KERN_ERR "can't add codec bus driver\n");
150257                 kfree(codec->private_data);
150258                 kfree(codec);
150259         }
150260 @@ -1857,7 +1867,6 @@ static int wm8753_remove(struct platform
150261         snd_soc_free_pcms(socdev);
150262         snd_soc_dapm_free(socdev);
150263  #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
150264 -       i2c_unregister_device(codec->control_data);
150265         i2c_del_driver(&wm8753_i2c_driver);
150266  #endif
150267  #if defined(CONFIG_SPI_MASTER)
150268 Index: linux-2.6.28/sound/soc/s3c24xx/Kconfig
150269 ===================================================================
150270 --- linux-2.6.28.orig/sound/soc/s3c24xx/Kconfig 2008-12-25 00:26:37.000000000 +0100
150271 +++ linux-2.6.28/sound/soc/s3c24xx/Kconfig      2009-01-02 00:01:58.000000000 +0100
150272 @@ -26,6 +26,15 @@ config SND_S3C24XX_SOC_NEO1973_WM8753
150273           Say Y if you want to add support for SoC audio on smdk2440
150274           with the WM8753.
150275
150276 +config SND_S3C24XX_SOC_NEO1973_GTA02_WM8753
150277 +       tristate "SoC I2S Audio support for NEO1973 GTA02 - WM8753"
150278 +       depends on SND_S3C24XX_SOC && MACH_NEO1973_GTA02
150279 +       select SND_S3C24XX_SOC_I2S
150280 +       select SND_SOC_WM8753
150281 +       help
150282 +         Say Y if you want to add support for SoC audio on neo1973 gta02
150283 +         with the WM8753 codec
150284 +
150285  config SND_S3C24XX_SOC_SMDK2443_WM9710
150286         tristate "SoC AC97 Audio support for SMDK2443 - WM9710"
150287         depends on SND_S3C24XX_SOC && MACH_SMDK2443
150288 Index: linux-2.6.28/sound/soc/s3c24xx/Makefile
150289 ===================================================================
150290 --- linux-2.6.28.orig/sound/soc/s3c24xx/Makefile        2008-12-25 00:26:37.000000000 +0100
150291 +++ linux-2.6.28/sound/soc/s3c24xx/Makefile     2009-01-02 00:01:58.000000000 +0100
150292 @@ -13,7 +13,10 @@ obj-$(CONFIG_SND_S3C2412_SOC_I2S) += snd
150293  snd-soc-neo1973-wm8753-objs := neo1973_wm8753.o
150294  snd-soc-smdk2443-wm9710-objs := smdk2443_wm9710.o
150295  snd-soc-ln2440sbc-alc650-objs := ln2440sbc_alc650.o
150296 +snd-soc-neo1973-gta02-wm8753-objs := neo1973_gta02_wm8753.o
150297
150298  obj-$(CONFIG_SND_S3C24XX_SOC_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
150299  obj-$(CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o
150300  obj-$(CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650) += snd-soc-ln2440sbc-alc650.o
150301 +obj-$(CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753) += snd-soc-neo1973-gta02-wm8753.o
150302 +
150303 Index: linux-2.6.28/sound/soc/s3c24xx/neo1973_gta02_wm8753.c
150304 ===================================================================
150305 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
150306 +++ linux-2.6.28/sound/soc/s3c24xx/neo1973_gta02_wm8753.c       2009-01-02 00:01:58.000000000 +0100
150307 @@ -0,0 +1,673 @@
150308 +/*
150309 + * neo1973_gta02_wm8753.c  --  SoC audio for Neo1973
150310 + *
150311 + * Copyright 2007 Openmoko Inc
150312 + * Author: Graeme Gregory <graeme@openmoko.org>
150313 + * Copyright 2007 Wolfson Microelectronics PLC.
150314 + * Author: Graeme Gregory <linux@wolfsonmicro.com>
150315 + *
150316 + *  This program is free software; you can redistribute  it and/or modify it
150317 + *  under  the terms of  the GNU General  Public License as published by the
150318 + *  Free Software Foundation;  either version 2 of the  License, or (at your
150319 + *  option) any later version.
150320 + *
150321 + *  Revision history
150322 + *    06th Nov 2007   Changed from GTA01 to GTA02
150323 + *    20th Jan 2007   Initial version.
150324 + *    05th Feb 2007   Rename all to Neo1973
150325 + *
150326 + */
150327 +
150328 +#include <linux/module.h>
150329 +#include <linux/moduleparam.h>
150330 +#include <linux/timer.h>
150331 +#include <linux/interrupt.h>
150332 +#include <linux/platform_device.h>
150333 +#include <linux/i2c.h>
150334 +#include <sound/core.h>
150335 +#include <sound/pcm.h>
150336 +#include <sound/soc.h>
150337 +#include <sound/soc-dapm.h>
150338 +
150339 +#include <asm/mach-types.h>
150340 +#include <asm/hardware/scoop.h>
150341 +#include <asm/plat-s3c24xx/regs-iis.h>
150342 +#include <mach/regs-clock.h>
150343 +#include <mach/regs-gpio.h>
150344 +#include <mach/hardware.h>
150345 +#include <mach/audio.h>
150346 +#include <asm/io.h>
150347 +#include <mach/spi-gpio.h>
150348 +#include <mach/regs-gpioj.h>
150349 +#include <mach/gta02.h>
150350 +#include "../codecs/wm8753.h"
150351 +#include "s3c24xx-pcm.h"
150352 +#include "s3c24xx-i2s.h"
150353 +
150354 +/* define the scenarios */
150355 +#define NEO_AUDIO_OFF                  0
150356 +#define NEO_GSM_CALL_AUDIO_HANDSET     1
150357 +#define NEO_GSM_CALL_AUDIO_HEADSET     2
150358 +#define NEO_GSM_CALL_AUDIO_BLUETOOTH   3
150359 +#define NEO_STEREO_TO_SPEAKERS         4
150360 +#define NEO_STEREO_TO_HEADPHONES       5
150361 +#define NEO_CAPTURE_HANDSET            6
150362 +#define NEO_CAPTURE_HEADSET            7
150363 +#define NEO_CAPTURE_BLUETOOTH          8
150364 +#define NEO_STEREO_TO_HANDSET_SPK      9
150365 +
150366 +static struct snd_soc_machine neo1973_gta02;
150367 +
150368 +static int neo1973_gta02_hifi_hw_params(struct snd_pcm_substream *substream,
150369 +       struct snd_pcm_hw_params *params)
150370 +{
150371 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
150372 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
150373 +       struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
150374 +       unsigned int pll_out = 0, bclk = 0;
150375 +       int ret = 0;
150376 +       unsigned long iis_clkrate;
150377 +
150378 +       iis_clkrate = s3c24xx_i2s_get_clockrate();
150379 +
150380 +       switch (params_rate(params)) {
150381 +       case 8000:
150382 +       case 16000:
150383 +               pll_out = 12288000;
150384 +               break;
150385 +       case 48000:
150386 +               bclk = WM8753_BCLK_DIV_4;
150387 +               pll_out = 12288000;
150388 +               break;
150389 +       case 96000:
150390 +               bclk = WM8753_BCLK_DIV_2;
150391 +               pll_out = 12288000;
150392 +               break;
150393 +       case 11025:
150394 +               bclk = WM8753_BCLK_DIV_16;
150395 +               pll_out = 11289600;
150396 +               break;
150397 +       case 22050:
150398 +               bclk = WM8753_BCLK_DIV_8;
150399 +               pll_out = 11289600;
150400 +               break;
150401 +       case 44100:
150402 +               bclk = WM8753_BCLK_DIV_4;
150403 +               pll_out = 11289600;
150404 +               break;
150405 +       case 88200:
150406 +               bclk = WM8753_BCLK_DIV_2;
150407 +               pll_out = 11289600;
150408 +               break;
150409 +       }
150410 +
150411 +       /* set codec DAI configuration */
150412 +       ret = codec_dai->dai_ops.set_fmt(codec_dai,
150413 +               SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
150414 +               SND_SOC_DAIFMT_CBM_CFM);
150415 +       if (ret < 0)
150416 +               return ret;
150417 +
150418 +       /* set cpu DAI configuration */
150419 +       ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
150420 +               SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
150421 +               SND_SOC_DAIFMT_CBM_CFM);
150422 +       if (ret < 0)
150423 +               return ret;
150424 +
150425 +       /* set the codec system clock for DAC and ADC */
150426 +       ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_MCLK, pll_out,
150427 +               SND_SOC_CLOCK_IN);
150428 +       if (ret < 0)
150429 +               return ret;
150430 +
150431 +       /* set MCLK division for sample rate */
150432 +       ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK,
150433 +               S3C2410_IISMOD_32FS );
150434 +       if (ret < 0)
150435 +               return ret;
150436 +
150437 +       /* set codec BCLK division for sample rate */
150438 +       ret = codec_dai->dai_ops.set_clkdiv(codec_dai,
150439 +                                       WM8753_BCLKDIV, bclk);
150440 +       if (ret < 0)
150441 +               return ret;
150442 +
150443 +       /* set prescaler division for sample rate */
150444 +       ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
150445 +               S3C24XX_PRESCALE(4,4));
150446 +       if (ret < 0)
150447 +               return ret;
150448 +
150449 +       /* codec PLL input is PCLK/4 */
150450 +       ret = codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1,
150451 +               iis_clkrate / 4, pll_out);
150452 +       if (ret < 0)
150453 +               return ret;
150454 +
150455 +       return 0;
150456 +}
150457 +
150458 +static int neo1973_gta02_hifi_hw_free(struct snd_pcm_substream *substream)
150459 +{
150460 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
150461 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
150462 +
150463 +       /* disable the PLL */
150464 +       return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1, 0, 0);
150465 +}
150466 +
150467 +/*
150468 + * Neo1973 WM8753 HiFi DAI opserations.
150469 + */
150470 +static struct snd_soc_ops neo1973_gta02_hifi_ops = {
150471 +       .hw_params = neo1973_gta02_hifi_hw_params,
150472 +       .hw_free = neo1973_gta02_hifi_hw_free,
150473 +};
150474 +
150475 +static int neo1973_gta02_voice_hw_params(
150476 +       struct snd_pcm_substream *substream,
150477 +       struct snd_pcm_hw_params *params)
150478 +{
150479 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
150480 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
150481 +       unsigned int pcmdiv = 0;
150482 +       int ret = 0;
150483 +       unsigned long iis_clkrate;
150484 +
150485 +       iis_clkrate = s3c24xx_i2s_get_clockrate();
150486 +
150487 +       if (params_rate(params) != 8000)
150488 +               return -EINVAL;
150489 +       if (params_channels(params) != 1)
150490 +               return -EINVAL;
150491 +
150492 +       pcmdiv = WM8753_PCM_DIV_6; /* 2.048 MHz */
150493 +
150494 +       /* todo: gg check mode (DSP_B) against CSR datasheet */
150495 +       /* set codec DAI configuration */
150496 +       ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B |
150497 +               SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
150498 +       if (ret < 0)
150499 +               return ret;
150500 +
150501 +       /* set the codec system clock for DAC and ADC */
150502 +       ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_PCMCLK,
150503 +               12288000, SND_SOC_CLOCK_IN);
150504 +       if (ret < 0)
150505 +               return ret;
150506 +
150507 +       /* set codec PCM division for sample rate */
150508 +       ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8753_PCMDIV,
150509 +                                       pcmdiv);
150510 +       if (ret < 0)
150511 +               return ret;
150512 +
150513 +       /* configue and enable PLL for 12.288MHz output */
150514 +       ret = codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL2,
150515 +               iis_clkrate / 4, 12288000);
150516 +       if (ret < 0)
150517 +               return ret;
150518 +
150519 +       return 0;
150520 +}
150521 +
150522 +static int neo1973_gta02_voice_hw_free(struct snd_pcm_substream *substream)
150523 +{
150524 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
150525 +       struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
150526 +
150527 +       /* disable the PLL */
150528 +       return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL2, 0, 0);
150529 +}
150530 +
150531 +static struct snd_soc_ops neo1973_gta02_voice_ops = {
150532 +       .hw_params = neo1973_gta02_voice_hw_params,
150533 +       .hw_free = neo1973_gta02_voice_hw_free,
150534 +};
150535 +
150536 +#define LM4853_AMP 1
150537 +#define LM4853_SPK 2
150538 +
150539 +static u8 lm4853_state=0;
150540 +
150541 +static int lm4853_set_state(struct snd_kcontrol *kcontrol,
150542 +       struct snd_ctl_elem_value *ucontrol)
150543 +{
150544 +       int val = ucontrol->value.integer.value[0];
150545 +
150546 +       if(val) {
150547 +               lm4853_state |= LM4853_AMP;
150548 +               s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT,0);
150549 +       } else {
150550 +               lm4853_state &= ~LM4853_AMP;
150551 +               s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT,1);
150552 +       }
150553 +
150554 +       return 0;
150555 +}
150556 +
150557 +static int lm4853_get_state(struct snd_kcontrol *kcontrol,
150558 +       struct snd_ctl_elem_value *ucontrol)
150559 +{
150560 +       ucontrol->value.integer.value[0] = lm4853_state & LM4853_AMP;
150561 +
150562 +       return 0;
150563 +}
150564 +
150565 +static int lm4853_set_spk(struct snd_kcontrol *kcontrol,
150566 +       struct snd_ctl_elem_value *ucontrol)
150567 +{
150568 +       int val = ucontrol->value.integer.value[0];
150569 +
150570 +       if(val) {
150571 +               lm4853_state |= LM4853_SPK;
150572 +               s3c2410_gpio_setpin(GTA02_GPIO_HP_IN,0);
150573 +       } else {
150574 +               lm4853_state &= ~LM4853_SPK;
150575 +               s3c2410_gpio_setpin(GTA02_GPIO_HP_IN,1);
150576 +       }
150577 +
150578 +       return 0;
150579 +}
150580 +
150581 +static int lm4853_get_spk(struct snd_kcontrol *kcontrol,
150582 +       struct snd_ctl_elem_value *ucontrol)
150583 +{
150584 +       ucontrol->value.integer.value[0] = (lm4853_state & LM4853_SPK) >> 1;
150585 +
150586 +       return 0;
150587 +}
150588 +
150589 +static int neo1973_gta02_set_stereo_out(struct snd_kcontrol *kcontrol,
150590 +       struct snd_ctl_elem_value *ucontrol)
150591 +{
150592 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150593 +       int val = ucontrol->value.integer.value[0];
150594 +
150595 +       snd_soc_dapm_set_endpoint(codec, "Stereo Out", val);
150596 +
150597 +       snd_soc_dapm_sync(codec);
150598 +
150599 +       return 0;
150600 +}
150601 +
150602 +static int neo1973_gta02_get_stereo_out(struct snd_kcontrol *kcontrol,
150603 +       struct snd_ctl_elem_value *ucontrol)
150604 +{
150605 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150606 +
150607 +       ucontrol->value.integer.value[0] =
150608 +               snd_soc_dapm_get_endpoint(codec, "Stereo Out");
150609 +
150610 +       return 0;
150611 +}
150612 +
150613 +
150614 +static int neo1973_gta02_set_gsm_out(struct snd_kcontrol *kcontrol,
150615 +       struct snd_ctl_elem_value *ucontrol)
150616 +{
150617 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150618 +       int val = ucontrol->value.integer.value[0];
150619 +
150620 +       snd_soc_dapm_set_endpoint(codec, "GSM Line Out", val);
150621 +
150622 +       snd_soc_dapm_sync(codec);
150623 +
150624 +       return 0;
150625 +}
150626 +
150627 +static int neo1973_gta02_get_gsm_out(struct snd_kcontrol *kcontrol,
150628 +       struct snd_ctl_elem_value *ucontrol)
150629 +{
150630 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150631 +
150632 +       ucontrol->value.integer.value[0] =
150633 +               snd_soc_dapm_get_endpoint(codec, "GSM Line Out");
150634 +
150635 +       return 0;
150636 +}
150637 +
150638 +static int neo1973_gta02_set_gsm_in(struct snd_kcontrol *kcontrol,
150639 +       struct snd_ctl_elem_value *ucontrol)
150640 +{
150641 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150642 +       int val = ucontrol->value.integer.value[0];
150643 +
150644 +       snd_soc_dapm_set_endpoint(codec, "GSM Line In", val);
150645 +
150646 +       snd_soc_dapm_sync(codec);
150647 +
150648 +       return 0;
150649 +}
150650 +
150651 +static int neo1973_gta02_get_gsm_in(struct snd_kcontrol *kcontrol,
150652 +       struct snd_ctl_elem_value *ucontrol)
150653 +{
150654 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150655 +
150656 +       ucontrol->value.integer.value[0] =
150657 +               snd_soc_dapm_get_endpoint(codec, "GSM Line In");
150658 +
150659 +       return 0;
150660 +}
150661 +
150662 +static int neo1973_gta02_set_headset_mic(struct snd_kcontrol *kcontrol,
150663 +       struct snd_ctl_elem_value *ucontrol)
150664 +{
150665 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150666 +       int val = ucontrol->value.integer.value[0];
150667 +
150668 +       snd_soc_dapm_set_endpoint(codec, "Headset Mic", val);
150669 +
150670 +       snd_soc_dapm_sync(codec);
150671 +
150672 +       return 0;
150673 +}
150674 +
150675 +static int neo1973_gta02_get_headset_mic(struct snd_kcontrol *kcontrol,
150676 +       struct snd_ctl_elem_value *ucontrol)
150677 +{
150678 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150679 +
150680 +       ucontrol->value.integer.value[0] =
150681 +               snd_soc_dapm_get_endpoint(codec, "Headset Mic");
150682 +
150683 +       return 0;
150684 +}
150685 +
150686 +static int neo1973_gta02_set_handset_mic(struct snd_kcontrol *kcontrol,
150687 +       struct snd_ctl_elem_value *ucontrol)
150688 +{
150689 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150690 +       int val = ucontrol->value.integer.value[0];
150691 +
150692 +       snd_soc_dapm_set_endpoint(codec, "Handset Mic", val);
150693 +
150694 +       snd_soc_dapm_sync(codec);
150695 +
150696 +       return 0;
150697 +}
150698 +
150699 +static int neo1973_gta02_get_handset_mic(struct snd_kcontrol *kcontrol,
150700 +       struct snd_ctl_elem_value *ucontrol)
150701 +{
150702 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150703 +
150704 +       ucontrol->value.integer.value[0] =
150705 +               snd_soc_dapm_get_endpoint(codec, "Handset Mic");
150706 +
150707 +       return 0;
150708 +}
150709 +
150710 +static int neo1973_gta02_set_handset_spk(struct snd_kcontrol *kcontrol,
150711 +       struct snd_ctl_elem_value *ucontrol)
150712 +{
150713 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150714 +       int val = ucontrol->value.integer.value[0];
150715 +
150716 +       snd_soc_dapm_set_endpoint(codec, "Handset Spk", val);
150717 +
150718 +       snd_soc_dapm_sync(codec);
150719 +
150720 +       return 0;
150721 +}
150722 +
150723 +static int neo1973_gta02_get_handset_spk(struct snd_kcontrol *kcontrol,
150724 +       struct snd_ctl_elem_value *ucontrol)
150725 +{
150726 +       struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
150727 +
150728 +       ucontrol->value.integer.value[0] =
150729 +               snd_soc_dapm_get_endpoint(codec, "Handset Spk");
150730 +
150731 +       return 0;
150732 +}
150733 +
150734 +static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
150735 +       SND_SOC_DAPM_LINE("Stereo Out", NULL),
150736 +       SND_SOC_DAPM_LINE("GSM Line Out", NULL),
150737 +       SND_SOC_DAPM_LINE("GSM Line In", NULL),
150738 +       SND_SOC_DAPM_MIC("Headset Mic", NULL),
150739 +       SND_SOC_DAPM_MIC("Handset Mic", NULL),
150740 +       SND_SOC_DAPM_SPK("Handset Spk", NULL),
150741 +};
150742 +
150743 +
150744 +/* example machine audio_mapnections */
150745 +static const char* audio_map[][3] = {
150746 +
150747 +       /* Connections to the lm4853 amp */
150748 +       {"Stereo Out", NULL, "LOUT1"},
150749 +       {"Stereo Out", NULL, "ROUT1"},
150750 +
150751 +       /* Connections to the GSM Module */
150752 +       {"GSM Line Out", NULL, "MONO1"},
150753 +       {"GSM Line Out", NULL, "MONO2"},
150754 +       {"RXP", NULL, "GSM Line In"},
150755 +       {"RXN", NULL, "GSM Line In"},
150756 +
150757 +       /* Connections to Headset */
150758 +       {"MIC1", NULL, "Mic Bias"},
150759 +       {"Mic Bias", NULL, "Headset Mic"},
150760 +
150761 +       /* Call Mic */
150762 +       {"MIC2", NULL, "Mic Bias"},
150763 +       {"MIC2N", NULL, "Mic Bias"},
150764 +       {"Mic Bias", NULL, "Handset Mic"},
150765 +
150766 +       /* Call Speaker */
150767 +       {"Handset Spk", NULL, "LOUT2"},
150768 +       {"Handset Spk", NULL, "ROUT2"},
150769 +
150770 +       /* Connect the ALC pins */
150771 +       {"ACIN", NULL, "ACOP"},
150772 +
150773 +       {NULL, NULL, NULL},
150774 +};
150775 +
150776 +static const struct snd_kcontrol_new wm8753_neo1973_gta02_controls[] = {
150777 +       SOC_SINGLE_EXT("DAPM Stereo Out Switch", 0, 0, 1, 0,
150778 +               neo1973_gta02_get_stereo_out,
150779 +               neo1973_gta02_set_stereo_out),
150780 +       SOC_SINGLE_EXT("DAPM GSM Line Out Switch", 1, 0, 1, 0,
150781 +               neo1973_gta02_get_gsm_out,
150782 +               neo1973_gta02_set_gsm_out),
150783 +       SOC_SINGLE_EXT("DAPM GSM Line In Switch", 2, 0, 1, 0,
150784 +               neo1973_gta02_get_gsm_in,
150785 +               neo1973_gta02_set_gsm_in),
150786 +       SOC_SINGLE_EXT("DAPM Headset Mic Switch", 3, 0, 1, 0,
150787 +               neo1973_gta02_get_headset_mic,
150788 +               neo1973_gta02_set_headset_mic),
150789 +       SOC_SINGLE_EXT("DAPM Handset Mic Switch", 4, 0, 1, 0,
150790 +               neo1973_gta02_get_handset_mic,
150791 +               neo1973_gta02_set_handset_mic),
150792 +       SOC_SINGLE_EXT("DAPM Handset Spk Switch", 5, 0, 1, 0,
150793 +               neo1973_gta02_get_handset_spk,
150794 +               neo1973_gta02_set_handset_spk),
150795 +       SOC_SINGLE_EXT("Amp State Switch", 6, 0, 1, 0,
150796 +               lm4853_get_state,
150797 +               lm4853_set_state),
150798 +       SOC_SINGLE_EXT("Amp Spk Switch", 7, 0, 1, 0,
150799 +               lm4853_get_spk,
150800 +               lm4853_set_spk),
150801 +};
150802 +
150803 +/*
150804 + * This is an example machine initialisation for a wm8753 connected to a
150805 + * neo1973 GTA02.
150806 + */
150807 +static int neo1973_gta02_wm8753_init(struct snd_soc_codec *codec)
150808 +{
150809 +       int i, err;
150810 +
150811 +       /* set up NC codec pins */
150812 +       snd_soc_dapm_set_endpoint(codec, "OUT3",  0);
150813 +       snd_soc_dapm_set_endpoint(codec, "OUT4",  0);
150814 +       snd_soc_dapm_set_endpoint(codec, "LINE1", 0);
150815 +       snd_soc_dapm_set_endpoint(codec, "LINE2", 0);
150816 +
150817 +       /* Add neo1973 gta02 specific widgets */
150818 +       for (i = 0; i < ARRAY_SIZE(wm8753_dapm_widgets); i++)
150819 +               snd_soc_dapm_new_control(codec, &wm8753_dapm_widgets[i]);
150820 +
150821 +       /* add neo1973 gta02 specific controls */
150822 +       for (i = 0; i < ARRAY_SIZE(wm8753_neo1973_gta02_controls); i++) {
150823 +               err = snd_ctl_add(codec->card,
150824 +                       snd_soc_cnew(&wm8753_neo1973_gta02_controls[i],
150825 +                       codec, NULL));
150826 +               if (err < 0)
150827 +                       return err;
150828 +       }
150829 +
150830 +       /* set up neo1973 gta02 specific audio path audio_mapnects */
150831 +       for (i = 0; audio_map[i][0] != NULL; i++) {
150832 +               snd_soc_dapm_connect_input(codec, audio_map[i][0],
150833 +                       audio_map[i][1], audio_map[i][2]);
150834 +       }
150835 +
150836 +       /* set endpoints to default off mode */
150837 +       snd_soc_dapm_set_endpoint(codec, "Stereo Out",  0);
150838 +       snd_soc_dapm_set_endpoint(codec, "GSM Line Out",0);
150839 +       snd_soc_dapm_set_endpoint(codec, "GSM Line In", 0);
150840 +       snd_soc_dapm_set_endpoint(codec, "Headset Mic", 0);
150841 +       snd_soc_dapm_set_endpoint(codec, "Handset Mic", 0);
150842 +       snd_soc_dapm_set_endpoint(codec, "Handset Spk", 0);
150843 +
150844 +       snd_soc_dapm_sync(codec);
150845 +
150846 +       return 0;
150847 +}
150848 +
150849 +/*
150850 + * BT Codec DAI
150851 + */
150852 +static struct snd_soc_dai bt_dai =
150853 +{      .name = "Bluetooth",
150854 +       .id = 0,
150855 +       .type = SND_SOC_DAI_PCM,
150856 +       .playback = {
150857 +               .channels_min = 1,
150858 +               .channels_max = 1,
150859 +               .rates = SNDRV_PCM_RATE_8000,
150860 +               .formats = SNDRV_PCM_FMTBIT_S16_LE,},
150861 +       .capture = {
150862 +               .channels_min = 1,
150863 +               .channels_max = 1,
150864 +               .rates = SNDRV_PCM_RATE_8000,
150865 +               .formats = SNDRV_PCM_FMTBIT_S16_LE,},
150866 +};
150867 +
150868 +static struct snd_soc_dai_link neo1973_gta02_dai[] = {
150869 +{ /* Hifi Playback - for similatious use with voice below */
150870 +       .name = "WM8753",
150871 +       .stream_name = "WM8753 HiFi",
150872 +       .cpu_dai = &s3c24xx_i2s_dai,
150873 +       .codec_dai = &wm8753_dai[WM8753_DAI_HIFI],
150874 +       .init = neo1973_gta02_wm8753_init,
150875 +       .ops = &neo1973_gta02_hifi_ops,
150876 +},
150877 +{ /* Voice via BT */
150878 +       .name = "Bluetooth",
150879 +       .stream_name = "Voice",
150880 +       .cpu_dai = &bt_dai,
150881 +       .codec_dai = &wm8753_dai[WM8753_DAI_VOICE],
150882 +       .ops = &neo1973_gta02_voice_ops,
150883 +},
150884 +};
150885 +
150886 +#ifdef CONFIG_PM
150887 +int neo1973_gta02_suspend(struct platform_device *pdev, pm_message_t state)
150888 +{
150889 +       s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 1);
150890 +
150891 +       return 0;
150892 +}
150893 +
150894 +int neo1973_gta02_resume(struct platform_device *pdev)
150895 +{
150896 +       if(lm4853_state & LM4853_AMP)
150897 +               s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 0);
150898 +
150899 +       return 0;
150900 +}
150901 +#else
150902 +#define neo1973_gta02_suspend NULL
150903 +#define neo1973_gta02_resume NULL
150904 +#endif
150905 +
150906 +static struct snd_soc_machine neo1973_gta02 = {
150907 +       .name = "neo1973-gta02",
150908 +       .suspend_pre = neo1973_gta02_suspend,
150909 +       .resume_post = neo1973_gta02_resume,
150910 +       .dai_link = neo1973_gta02_dai,
150911 +       .num_links = ARRAY_SIZE(neo1973_gta02_dai),
150912 +};
150913 +
150914 +/* Audio private data */
150915 +static struct wm8753_setup_data soc_codec_data_wm8753_gta02 = {
150916 +       .i2c_bus = 0,
150917 +       .i2c_address = 0x1a,
150918 +//     .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
150919 +//     .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
150920 +};
150921 +
150922 +static struct snd_soc_device neo1973_gta02_snd_devdata = {
150923 +       .machine = &neo1973_gta02,
150924 +       .platform = &s3c24xx_soc_platform,
150925 +       .codec_dev = &soc_codec_dev_wm8753,
150926 +       .codec_data = &soc_codec_data_wm8753_gta02,
150927 +};
150928 +
150929 +
150930 +
150931 +static struct platform_device *neo1973_gta02_snd_device;
150932 +
150933 +static int __init neo1973_gta02_init(void)
150934 +{
150935 +       int ret;
150936 +
150937 +       if (!machine_is_neo1973_gta02()) {
150938 +               printk(KERN_INFO
150939 +                      "Only GTA02 hardware supported by ASoc driver\n");
150940 +               return -ENODEV;
150941 +       }
150942 +
150943 +       neo1973_gta02_snd_device = platform_device_alloc("soc-audio", -1);
150944 +       if (!neo1973_gta02_snd_device)
150945 +               return -ENOMEM;
150946 +
150947 +       platform_set_drvdata(neo1973_gta02_snd_device,
150948 +                       &neo1973_gta02_snd_devdata);
150949 +       neo1973_gta02_snd_devdata.dev = &neo1973_gta02_snd_device->dev;
150950 +       ret = platform_device_add(neo1973_gta02_snd_device);
150951 +
150952 +       if (ret)
150953 +               platform_device_put(neo1973_gta02_snd_device);
150954 +
150955 +       /* Initialise GPIOs used by amp */
150956 +       s3c2410_gpio_cfgpin(GTA02_GPIO_HP_IN, S3C2410_GPIO_OUTPUT);
150957 +       s3c2410_gpio_cfgpin(GTA02_GPIO_AMP_SHUT, S3C2410_GPIO_OUTPUT);
150958 +
150959 +       /* Amp off by default */
150960 +       s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 1);
150961 +
150962 +       /* Speaker off by default */
150963 +       s3c2410_gpio_setpin(GTA02_GPIO_HP_IN, 1);
150964 +
150965 +       return ret;
150966 +}
150967 +
150968 +static void __exit neo1973_gta02_exit(void)
150969 +{
150970 +       platform_device_unregister(neo1973_gta02_snd_device);
150971 +}
150972 +
150973 +module_init(neo1973_gta02_init);
150974 +module_exit(neo1973_gta02_exit);
150975 +
150976 +/* Module information */
150977 +MODULE_AUTHOR("Graeme Gregory, graeme@openmoko.org");
150978 +MODULE_DESCRIPTION("ALSA SoC WM8753 Neo1973 GTA02");
150979 +MODULE_LICENSE("GPL");
150980 +
150981 Index: linux-2.6.28/sound/soc/s3c24xx/neo1973_wm8753.c
150982 ===================================================================
150983 --- linux-2.6.28.orig/sound/soc/s3c24xx/neo1973_wm8753.c        2008-12-25 00:26:37.000000000 +0100
150984 +++ linux-2.6.28/sound/soc/s3c24xx/neo1973_wm8753.c     2009-01-02 00:01:58.000000000 +0100
150985 @@ -32,7 +32,7 @@
150986  #include <mach/audio.h>
150987  #include <linux/io.h>
150988  #include <mach/spi-gpio.h>
150989 -
150990 +#include <asm/mach-types.h>
150991  #include <asm/plat-s3c24xx/regs-iis.h>
150992
150993  #include "../codecs/wm8753.h"
150994 @@ -585,7 +585,7 @@ static struct snd_soc_machine neo1973 =
150995         .num_links = ARRAY_SIZE(neo1973_dai),
150996  };
150997
150998 -static struct wm8753_setup_data neo1973_wm8753_setup = {
150999 +static struct wm8753_setup_data soc_codec_data_wm8753_gta01 = {
151000         .i2c_bus = 0,
151001         .i2c_address = 0x1a,
151002  };
151003 @@ -594,7 +594,7 @@ static struct snd_soc_device neo1973_snd
151004         .machine = &neo1973,
151005         .platform = &s3c24xx_soc_platform,
151006         .codec_dev = &soc_codec_dev_wm8753,
151007 -       .codec_data = &neo1973_wm8753_setup,
151008 +       .codec_data = &soc_codec_data_wm8753_gta01
151009  };
151010
151011  static int lm4857_i2c_probe(struct i2c_client *client,
151012 @@ -676,7 +676,7 @@ static int __init neo1973_init(void)
151013  {
151014         int ret;
151015
151016 -       DBG("Entered %s\n", __func__);
151017 +       printk(KERN_DEBUG "Entered %s\n", __func__);
151018
151019         if (!machine_is_neo1973_gta01()) {
151020                 printk(KERN_INFO
151021 Index: linux-2.6.28/sound/soc/s3c24xx/s3c2443-ac97.c
151022 ===================================================================
151023 --- linux-2.6.28.orig/sound/soc/s3c24xx/s3c2443-ac97.c  2008-12-25 00:26:37.000000000 +0100
151024 +++ linux-2.6.28/sound/soc/s3c24xx/s3c2443-ac97.c       2009-01-02 00:01:58.000000000 +0100
151025 @@ -28,7 +28,7 @@
151026  #include <sound/soc.h>
151027
151028  #include <mach/hardware.h>
151029 -#include <asm/plat-s3c/regs-ac97.h>
151030 +#include <plat/regs-ac97.h>
151031  #include <mach/regs-gpio.h>
151032  #include <mach/regs-clock.h>
151033  #include <mach/audio.h>
151034 Index: linux-2.6.28/sound/soc/s3c24xx/s3c24xx-i2s.c
151035 ===================================================================
151036 --- linux-2.6.28.orig/sound/soc/s3c24xx/s3c24xx-i2s.c   2008-12-25 00:26:37.000000000 +0100
151037 +++ linux-2.6.28/sound/soc/s3c24xx/s3c24xx-i2s.c        2009-01-02 00:01:58.000000000 +0100
151038 @@ -175,7 +175,7 @@ static void s3c24xx_snd_rxctrl(int on)
151039  static int s3c24xx_snd_lrsync(void)
151040  {
151041         u32 iiscon;
151042 -       int timeout = 50; /* 5ms */
151043 +       int timeout = 5; /* 500us, 125 should be enough at 8kHz */
151044
151045         DBG("Entered %s\n", __func__);
151046
151047 @@ -282,11 +282,14 @@ static int s3c24xx_i2s_trigger(struct sn
151048         case SNDRV_PCM_TRIGGER_START:
151049         case SNDRV_PCM_TRIGGER_RESUME:
151050         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
151051 -               if (!s3c24xx_snd_is_clkmaster()) {
151052 -                       ret = s3c24xx_snd_lrsync();
151053 -                       if (ret)
151054 -                               goto exit_err;
151055 -               }
151056 +               if (!s3c24xx_snd_is_clkmaster())
151057 +                       /* we ignore the return code, if it sync'd then fine,
151058 +                        * if it didn't sync, which happens after resume the
151059 +                        * first time when there was a live stream at suspend,
151060 +                        * just let it timeout, the stream picks up OK after
151061 +                        * that and LRCK is evidently working again.
151062 +                        */
151063 +                       s3c24xx_snd_lrsync();
151064
151065                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
151066                         s3c24xx_snd_rxctrl(1);
151067 @@ -306,7 +309,6 @@ static int s3c24xx_i2s_trigger(struct sn
151068                 break;
151069         }
151070
151071 -exit_err:
151072         return ret;
151073  }
151074
151075 Index: linux-2.6.28/sound/soc/s3c24xx/s3c24xx-pcm.c
151076 ===================================================================
151077 --- linux-2.6.28.orig/sound/soc/s3c24xx/s3c24xx-pcm.c   2008-12-25 00:26:37.000000000 +0100
151078 +++ linux-2.6.28/sound/soc/s3c24xx/s3c24xx-pcm.c        2009-01-02 00:01:58.000000000 +0100
151079 @@ -168,7 +168,7 @@ static int s3c24xx_pcm_hw_params(struct
151080                                           prtd->params->client, NULL);
151081
151082                 if (ret < 0) {
151083 -                       DBG(KERN_ERR "failed to get dma channel\n");
151084 +                       DBG(KERN_ERR "failed to get dma channel: %d\n", ret);
151085                         return ret;
151086                 }
151087         }
151088 Index: linux-2.6.28/sound/soc/soc-core.c
151089 ===================================================================
151090 --- linux-2.6.28.orig/sound/soc/soc-core.c      2008-12-25 00:26:37.000000000 +0100
151091 +++ linux-2.6.28/sound/soc/soc-core.c   2009-01-02 00:01:58.000000000 +0100
151092 @@ -1003,6 +1003,38 @@ static ssize_t codec_reg_show(struct dev
151093  }
151094  static DEVICE_ATTR(codec_reg, 0444, codec_reg_show, NULL);
151095
151096 +
151097 +static ssize_t codec_reg_write(struct device *dev,
151098 +                              struct device_attribute *attr,
151099 +                              const char *buf, size_t count)
151100 +{
151101 +       u32 address;
151102 +       u32 data;
151103 +       char * end;
151104 +       size_t left = count;
151105 +       struct snd_soc_device *devdata = dev_get_drvdata(dev);
151106 +       struct snd_soc_codec *codec = devdata->codec;
151107 +
151108 +       address = simple_strtoul(buf, &end, 16);
151109 +       left -= (int)(end - buf);
151110 +       while ((*end == ' ') && (left)) {
151111 +               end++;
151112 +               left--;
151113 +       }
151114 +       if (!left)
151115 +               return count;
151116 +       data = simple_strtoul(end, &end, 16);
151117 +
151118 +       printk(KERN_INFO"user writes Codec reg 0x%02X with Data 0x%04X\n",
151119 +                                                               address, data);
151120 +
151121 +       codec->write(codec, address, data);
151122 +
151123 +       return count;
151124 +}
151125 +
151126 +static DEVICE_ATTR(codec_reg_write, 0644, NULL, codec_reg_write);
151127 +
151128  /**
151129   * snd_soc_new_ac97_codec - initailise AC97 device
151130   * @codec: audio codec
151131 @@ -1218,6 +1250,9 @@ int snd_soc_register_card(struct snd_soc
151132
151133         mutex_unlock(&codec->mutex);
151134
151135 +       err = device_create_file(socdev->dev, &dev_attr_codec_reg_write);
151136 +       if (err < 0)
151137 +               printk(KERN_WARNING "asoc: failed to add codec sysfs entries\n");
151138  out:
151139         return ret;
151140  }
151141 Index: linux-2.6.28/sound/soc/soc-dapm.c
151142 ===================================================================
151143 --- linux-2.6.28.orig/sound/soc/soc-dapm.c      2008-12-25 00:26:37.000000000 +0100
151144 +++ linux-2.6.28/sound/soc/soc-dapm.c   2009-01-02 00:01:58.000000000 +0100
151145 @@ -1525,6 +1525,56 @@ int snd_soc_dapm_get_pin_status(struct s
151146  EXPORT_SYMBOL_GPL(snd_soc_dapm_get_pin_status);
151147
151148  /**
151149 + * snd_soc_dapm_get_endpoint - get audio endpoint status
151150 + * @codec: audio codec
151151 + * @endpoint: audio signal endpoint (or start point)
151152 + *
151153 + * Get audio endpoint status - connected or disconnected.
151154 + *
151155 + * Returns status
151156 + */
151157 +int snd_soc_dapm_get_endpoint(struct snd_soc_codec *codec,
151158 +       char *endpoint)
151159 +{
151160 +       struct snd_soc_dapm_widget *w;
151161 +
151162 +       list_for_each_entry(w, &codec->dapm_widgets, list) {
151163 +               if (!strcmp(w->name, endpoint)) {
151164 +                       return w->connected;
151165 +               }
151166 +       }
151167 +
151168 +       return 0;
151169 +}
151170 +EXPORT_SYMBOL_GPL(snd_soc_dapm_get_endpoint);
151171 +
151172 +/**
151173 + * snd_soc_dapm_set_endpoint - set audio endpoint status
151174 + * @codec: audio codec
151175 + * @endpoint: audio signal endpoint (or start point)
151176 + * @status: point status
151177 + *
151178 + * Set audio endpoint status - connected or disconnected.
151179 + *
151180 + * Returns 0 for success else error.
151181 + */
151182 +int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec,
151183 +        char *endpoint, int status)
151184 +{
151185 +        struct snd_soc_dapm_widget *w;
151186 +
151187 +        list_for_each_entry(w, &codec->dapm_widgets, list) {
151188 +               if (!strcmp(w->name, endpoint)) {
151189 +                        w->connected = status;
151190 +                        return 0;
151191 +                }
151192 +        }
151193 +
151194 +        return -ENODEV;
151195 +}
151196 +EXPORT_SYMBOL_GPL(snd_soc_dapm_set_endpoint);
151197 +
151198 +/**
151199   * snd_soc_dapm_free - free dapm resources
151200   * @socdev: SoC device
151201   *