1 From 0b4bf5a5200b9ac5ddf545665f171feb5594677d Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Sat, 5 Dec 2015 21:16:46 +0800
4 Subject: [PATCH] ARM: dts: sun7i: Add DRAM gates
6 The DRAM gates controls direct memory access for some peripherals.
7 These peripherals include the display pipeline, so add the required
8 gates to the simplefb nodes as well.
10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 arch/arm/boot/dts/sun7i-a20.dtsi | 32 +++++++++++++++++++++++++++++---
14 1 file changed, 29 insertions(+), 3 deletions(-)
16 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
17 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
20 allwinner,pipeline = "de_be0-lcd0-hdmi";
21 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
23 + <&ahb_gates 44>, <&dram_gates 26>;
28 compatible = "allwinner,simple-framebuffer",
30 allwinner,pipeline = "de_be0-lcd0";
31 - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
32 + clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
39 allwinner,pipeline = "de_be0-lcd0-tve0";
40 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
42 + <&ahb_gates 44>, <&dram_gates 26>;
47 clock-output-names = "spi3";
50 + dram_gates: clk@01c20100 {
52 + compatible = "allwinner,sun4i-a10-dram-gates-clk";
53 + reg = <0x01c20100 0x4>;
55 + clock-indices = <0>,
64 + clock-output-names = "dram_ve",
65 + "dram_csi0", "dram_csi1",
68 + "dram_tve0", "dram_tve1",
70 + "dram_de_fe1", "dram_de_fe0",
71 + "dram_de_be0", "dram_de_be1",
72 + "dram_de_mp", "dram_ace";
75 codec_clk: clk@01c20140 {
77 compatible = "allwinner,sun4i-a10-codec-clk";