1 From 317c5224795b41a08ba8c08573d74ba95096faa5 Mon Sep 17 00:00:00 2001
2 From: Reinder de Haan <patchesrdh@mveas.com>
3 Date: Fri, 11 Dec 2015 16:32:18 +0100
4 Subject: [PATCH] phy-sun4i-usb: Add support for the host usb-phys found on the
7 Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
8 not yet (fully) supported after this commit.
10 Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
11 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
12 Acked-by: Rob Herring <robh@kernel.org>
13 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
15 .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
16 drivers/phy/phy-sun4i-usb.c | 41 +++++++++++++++++-----
17 2 files changed, 33 insertions(+), 9 deletions(-)
19 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
20 +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
21 @@ -9,6 +9,7 @@ Required properties:
22 * allwinner,sun7i-a20-usb-phy
23 * allwinner,sun8i-a23-usb-phy
24 * allwinner,sun8i-a33-usb-phy
25 + * allwinner,sun8i-h3-usb-phy
26 - reg : a list of offset + length pairs
29 --- a/drivers/phy/phy-sun4i-usb.c
30 +++ b/drivers/phy/phy-sun4i-usb.c
32 #define REG_PHYBIST 0x08
33 #define REG_PHYTUNE 0x0c
34 #define REG_PHYCTL_A33 0x10
35 +#define REG_PHY_UNK_H3 0x20
37 +#define REG_PMU_UNK_H3 0x10
39 #define PHYCTL_DATA BIT(7)
42 #define PHY_DISCON_TH_SEL 0x2a
43 #define PHY_SQUELCH_DETECT 0x3c
49 * Note do not raise the debounce time, we must report Vusb high within 100ms
51 enum sun4i_usb_phy_type {
57 struct sun4i_usb_phy_cfg {
58 @@ -239,6 +243,7 @@ static int sun4i_usb_phy_init(struct phy
59 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
60 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
64 ret = clk_prepare_enable(phy->clk);
66 @@ -250,16 +255,26 @@ static int sun4i_usb_phy_init(struct phy
70 - /* Enable USB 45 Ohm resistor calibration */
71 - if (phy->index == 0)
72 - sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
74 - /* Adjust PHY's magnitude and rate */
75 - sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
77 - /* Disconnect threshold adjustment */
78 - sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
79 - data->cfg->disc_thresh, 2);
80 + if (data->cfg->type == sun8i_h3_phy) {
81 + if (phy->index == 0) {
82 + val = readl(data->base + REG_PHY_UNK_H3);
83 + writel(val & ~1, data->base + REG_PHY_UNK_H3);
86 + val = readl(phy->pmu + REG_PMU_UNK_H3);
87 + writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
89 + /* Enable USB 45 Ohm resistor calibration */
90 + if (phy->index == 0)
91 + sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
93 + /* Adjust PHY's magnitude and rate */
94 + sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
96 + /* Disconnect threshold adjustment */
97 + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
98 + data->cfg->disc_thresh, 2);
101 sun4i_usb_phy_passby(phy, 1);
103 @@ -726,6 +741,13 @@ static const struct sun4i_usb_phy_cfg su
104 .dedicated_clocks = true,
107 +static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
109 + .type = sun8i_h3_phy,
111 + .dedicated_clocks = true,
114 static const struct of_device_id sun4i_usb_phy_of_match[] = {
115 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
116 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
117 @@ -733,6 +755,7 @@ static const struct of_device_id sun4i_u
118 { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
119 { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
120 { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
121 + { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
124 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);