1 ; RUN: llc -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu -aarch64-atomic-cfg-tidy=0 | FileCheck %s
8 define void @addsub_i8rhs() minsize {
9 ; CHECK-LABEL: addsub_i8rhs:
10 %val8_tmp = load i8, i8* @var8
11 %lhs32 = load i32, i32* @var32
12 %lhs64 = load i64, i64* @var64
14 ; Need this to prevent extension upon load and give a vanilla i8 operand.
15 %val8 = add i8 %val8_tmp, 123
18 ; Zero-extending to 32-bits
19 %rhs32_zext = zext i8 %val8 to i32
20 %res32_zext = add i32 %lhs32, %rhs32_zext
21 store volatile i32 %res32_zext, i32* @var32
22 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
24 %rhs32_zext_shift = shl i32 %rhs32_zext, 3
25 %res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift
26 store volatile i32 %res32_zext_shift, i32* @var32
27 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
30 ; Zero-extending to 64-bits
31 %rhs64_zext = zext i8 %val8 to i64
32 %res64_zext = add i64 %lhs64, %rhs64_zext
33 store volatile i64 %res64_zext, i64* @var64
34 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
36 %rhs64_zext_shift = shl i64 %rhs64_zext, 1
37 %res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
38 store volatile i64 %res64_zext_shift, i64* @var64
39 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
41 ; Sign-extending to 32-bits
42 %rhs32_sext = sext i8 %val8 to i32
43 %res32_sext = add i32 %lhs32, %rhs32_sext
44 store volatile i32 %res32_sext, i32* @var32
45 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
47 %rhs32_sext_shift = shl i32 %rhs32_sext, 1
48 %res32_sext_shift = add i32 %lhs32, %rhs32_sext_shift
49 store volatile i32 %res32_sext_shift, i32* @var32
50 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
52 ; Sign-extending to 64-bits
53 %rhs64_sext = sext i8 %val8 to i64
54 %res64_sext = add i64 %lhs64, %rhs64_sext
55 store volatile i64 %res64_sext, i64* @var64
56 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
58 %rhs64_sext_shift = shl i64 %rhs64_sext, 4
59 %res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift
60 store volatile i64 %res64_sext_shift, i64* @var64
61 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
65 %tst = icmp slt i32 %lhs32, %rhs32_zext
66 br i1 %tst, label %end, label %test2
67 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxtb
70 %cmp_sext = sext i8 %val8 to i64
71 %tst2 = icmp eq i64 %lhs64, %cmp_sext
72 br i1 %tst2, label %other, label %end
73 ; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxtb
76 store volatile i32 %lhs32, i32* @var32
83 define void @sub_i8rhs() minsize {
84 ; CHECK-LABEL: sub_i8rhs:
85 %val8_tmp = load i8, i8* @var8
86 %lhs32 = load i32, i32* @var32
87 %lhs64 = load i64, i64* @var64
89 ; Need this to prevent extension upon load and give a vanilla i8 operand.
90 %val8 = add i8 %val8_tmp, 123
93 ; Zero-extending to 32-bits
94 %rhs32_zext = zext i8 %val8 to i32
95 %res32_zext = sub i32 %lhs32, %rhs32_zext
96 store volatile i32 %res32_zext, i32* @var32
97 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
99 %rhs32_zext_shift = shl i32 %rhs32_zext, 3
100 %res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
101 store volatile i32 %res32_zext_shift, i32* @var32
102 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
105 ; Zero-extending to 64-bits
106 %rhs64_zext = zext i8 %val8 to i64
107 %res64_zext = sub i64 %lhs64, %rhs64_zext
108 store volatile i64 %res64_zext, i64* @var64
109 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
111 %rhs64_zext_shift = shl i64 %rhs64_zext, 1
112 %res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
113 store volatile i64 %res64_zext_shift, i64* @var64
114 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
116 ; Sign-extending to 32-bits
117 %rhs32_sext = sext i8 %val8 to i32
118 %res32_sext = sub i32 %lhs32, %rhs32_sext
119 store volatile i32 %res32_sext, i32* @var32
120 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb
122 %rhs32_sext_shift = shl i32 %rhs32_sext, 1
123 %res32_sext_shift = sub i32 %lhs32, %rhs32_sext_shift
124 store volatile i32 %res32_sext_shift, i32* @var32
125 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxtb #1
127 ; Sign-extending to 64-bits
128 %rhs64_sext = sext i8 %val8 to i64
129 %res64_sext = sub i64 %lhs64, %rhs64_sext
130 store volatile i64 %res64_sext, i64* @var64
131 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb
133 %rhs64_sext_shift = shl i64 %rhs64_sext, 4
134 %res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
135 store volatile i64 %res64_sext_shift, i64* @var64
136 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtb #4
141 define void @addsub_i16rhs() minsize {
142 ; CHECK-LABEL: addsub_i16rhs:
143 %val16_tmp = load i16, i16* @var16
144 %lhs32 = load i32, i32* @var32
145 %lhs64 = load i64, i64* @var64
147 ; Need this to prevent extension upon load and give a vanilla i16 operand.
148 %val16 = add i16 %val16_tmp, 123
151 ; Zero-extending to 32-bits
152 %rhs32_zext = zext i16 %val16 to i32
153 %res32_zext = add i32 %lhs32, %rhs32_zext
154 store volatile i32 %res32_zext, i32* @var32
155 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
157 %rhs32_zext_shift = shl i32 %rhs32_zext, 3
158 %res32_zext_shift = add i32 %lhs32, %rhs32_zext_shift
159 store volatile i32 %res32_zext_shift, i32* @var32
160 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
163 ; Zero-extending to 64-bits
164 %rhs64_zext = zext i16 %val16 to i64
165 %res64_zext = add i64 %lhs64, %rhs64_zext
166 store volatile i64 %res64_zext, i64* @var64
167 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
169 %rhs64_zext_shift = shl i64 %rhs64_zext, 1
170 %res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
171 store volatile i64 %res64_zext_shift, i64* @var64
172 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
174 ; Sign-extending to 32-bits
175 %rhs32_sext = sext i16 %val16 to i32
176 %res32_sext = add i32 %lhs32, %rhs32_sext
177 store volatile i32 %res32_sext, i32* @var32
178 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
180 %rhs32_sext_shift = shl i32 %rhs32_sext, 1
181 %res32_sext_shift = add i32 %lhs32, %rhs32_sext_shift
182 store volatile i32 %res32_sext_shift, i32* @var32
183 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1
185 ; Sign-extending to 64-bits
186 %rhs64_sext = sext i16 %val16 to i64
187 %res64_sext = add i64 %lhs64, %rhs64_sext
188 store volatile i64 %res64_sext, i64* @var64
189 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth
191 %rhs64_sext_shift = shl i64 %rhs64_sext, 4
192 %res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift
193 store volatile i64 %res64_sext_shift, i64* @var64
194 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
198 %tst = icmp slt i32 %lhs32, %rhs32_zext
199 br i1 %tst, label %end, label %test2
200 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxth
203 %cmp_sext = sext i16 %val16 to i64
204 %tst2 = icmp eq i64 %lhs64, %cmp_sext
205 br i1 %tst2, label %other, label %end
206 ; CHECK: cmp {{x[0-9]+}}, {{w[0-9]+}}, sxth
209 store volatile i32 %lhs32, i32* @var32
216 define void @sub_i16rhs() minsize {
217 ; CHECK-LABEL: sub_i16rhs:
218 %val16_tmp = load i16, i16* @var16
219 %lhs32 = load i32, i32* @var32
220 %lhs64 = load i64, i64* @var64
222 ; Need this to prevent extension upon load and give a vanilla i16 operand.
223 %val16 = add i16 %val16_tmp, 123
226 ; Zero-extending to 32-bits
227 %rhs32_zext = zext i16 %val16 to i32
228 %res32_zext = sub i32 %lhs32, %rhs32_zext
229 store volatile i32 %res32_zext, i32* @var32
230 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
232 %rhs32_zext_shift = shl i32 %rhs32_zext, 3
233 %res32_zext_shift = sub i32 %lhs32, %rhs32_zext_shift
234 store volatile i32 %res32_zext_shift, i32* @var32
235 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
238 ; Zero-extending to 64-bits
239 %rhs64_zext = zext i16 %val16 to i64
240 %res64_zext = sub i64 %lhs64, %rhs64_zext
241 store volatile i64 %res64_zext, i64* @var64
242 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
244 %rhs64_zext_shift = shl i64 %rhs64_zext, 1
245 %res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
246 store volatile i64 %res64_zext_shift, i64* @var64
247 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
249 ; Sign-extending to 32-bits
250 %rhs32_sext = sext i16 %val16 to i32
251 %res32_sext = sub i32 %lhs32, %rhs32_sext
252 store volatile i32 %res32_sext, i32* @var32
253 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
255 %rhs32_sext_shift = shl i32 %rhs32_sext, 1
256 %res32_sext_shift = sub i32 %lhs32, %rhs32_sext_shift
257 store volatile i32 %res32_sext_shift, i32* @var32
258 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth #1
260 ; Sign-extending to 64-bits
261 %rhs64_sext = sext i16 %val16 to i64
262 %res64_sext = sub i64 %lhs64, %rhs64_sext
263 store volatile i64 %res64_sext, i64* @var64
264 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth
266 %rhs64_sext_shift = shl i64 %rhs64_sext, 4
267 %res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
268 store volatile i64 %res64_sext_shift, i64* @var64
269 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxth #4
274 ; N.b. we could probably check more here ("add w2, w3, w1, uxtw" for
275 ; example), but the remaining instructions are probably not idiomatic
276 ; in the face of "add/sub (shifted register)" so I don't intend to.
277 define void @addsub_i32rhs() minsize {
278 ; CHECK-LABEL: addsub_i32rhs:
279 %val32_tmp = load i32, i32* @var32
280 %lhs64 = load i64, i64* @var64
282 %val32 = add i32 %val32_tmp, 123
284 %rhs64_zext = zext i32 %val32 to i64
285 %res64_zext = add i64 %lhs64, %rhs64_zext
286 store volatile i64 %res64_zext, i64* @var64
287 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
289 %rhs64_zext_shift = shl i64 %rhs64_zext, 2
290 %res64_zext_shift = add i64 %lhs64, %rhs64_zext_shift
291 store volatile i64 %res64_zext_shift, i64* @var64
292 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
294 %rhs64_sext = sext i32 %val32 to i64
295 %res64_sext = add i64 %lhs64, %rhs64_sext
296 store volatile i64 %res64_sext, i64* @var64
297 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
299 %rhs64_sext_shift = shl i64 %rhs64_sext, 2
300 %res64_sext_shift = add i64 %lhs64, %rhs64_sext_shift
301 store volatile i64 %res64_sext_shift, i64* @var64
302 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
307 define void @sub_i32rhs() minsize {
308 ; CHECK-LABEL: sub_i32rhs:
309 %val32_tmp = load i32, i32* @var32
310 %lhs64 = load i64, i64* @var64
312 %val32 = add i32 %val32_tmp, 123
314 %rhs64_zext = zext i32 %val32 to i64
315 %res64_zext = sub i64 %lhs64, %rhs64_zext
316 store volatile i64 %res64_zext, i64* @var64
317 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw
319 %rhs64_zext_shift = shl i64 %rhs64_zext, 2
320 %res64_zext_shift = sub i64 %lhs64, %rhs64_zext_shift
321 store volatile i64 %res64_zext_shift, i64* @var64
322 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtw #2
324 %rhs64_sext = sext i32 %val32 to i64
325 %res64_sext = sub i64 %lhs64, %rhs64_sext
326 store volatile i64 %res64_sext, i64* @var64
327 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
329 %rhs64_sext_shift = shl i64 %rhs64_sext, 2
330 %res64_sext_shift = sub i64 %lhs64, %rhs64_sext_shift
331 store volatile i64 %res64_sext_shift, i64* @var64
332 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2