1 ; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s
3 @var = global i32 0, align 4
5 ; CHECK-LABEL: @test_i128_align
6 define i128 @test_i128_align(i32, i128 %arg, i32 %after) {
7 store i32 %after, i32* @var, align 4
8 ; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
15 ; CHECK-LABEL: @test_i64x2_align
16 define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) {
17 store i32 %after, i32* @var, align 4
18 ; CHECK: str w3, [{{x[0-9]+}}, :lo12:var]
25 @var64 = global i64 0, align 8
27 ; Check stack slots are 64-bit at all times.
28 define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short,
29 i32 %int, i64 %long) {
30 %ext_bool = zext i1 %bool to i64
31 store volatile i64 %ext_bool, i64* @var64, align 8
32 ; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
34 ; Part of last store. Blasted scheduler.
35 ; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32]
37 ; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1
38 ; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
40 %ext_char = zext i8 %char to i64
41 store volatile i64 %ext_char, i64* @var64, align 8
42 ; CHECK: ldrb w[[EXT:[0-9]+]], [sp, #8]
43 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
45 %ext_short = zext i16 %short to i64
46 store volatile i64 %ext_short, i64* @var64, align 8
47 ; CHECK: ldrh w[[EXT:[0-9]+]], [sp, #16]
48 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
50 %ext_int = zext i32 %int to i64
51 store volatile i64 %ext_int, i64* @var64, align 8
52 ; CHECK: ldr{{b?}} w[[EXT:[0-9]+]], [sp, #24]
53 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
55 store volatile i64 %long, i64* @var64, align 8
56 ; CHECK: str [[LONG]], [{{x[0-9]+}}, :lo12:var64]
61 ; Make sure the callee does extensions (in the absence of zext/sext
62 ; keyword on args) while we're here.
64 define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
65 %ext_bool = zext i1 %bool to i64
66 store volatile i64 %ext_bool, i64* @var64
67 ; CHECK: and w[[EXT:[0-9]+]], w0, #0x1
68 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
70 %ext_char = sext i8 %char to i64
71 store volatile i64 %ext_char, i64* @var64
72 ; CHECK: sxtb [[EXT:x[0-9]+]], w1
73 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
75 %ext_short = zext i16 %short to i64
76 store volatile i64 %ext_short, i64* @var64
77 ; CHECK: and w[[EXT:[0-9]+]], w2, #0xffff
78 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
80 %ext_int = zext i32 %int to i64
81 store volatile i64 %ext_int, i64* @var64
82 ; CHECK: mov w[[EXT:[0-9]+]], w3
83 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
88 declare void @variadic(i32 %a, ...)
90 ; Under AAPCS variadic functions have the same calling convention as
91 ; others. The extra arguments should go in registers rather than on the stack.
92 define void @test_variadic() {
93 call void(i32, ...) @variadic(i32 0, i64 1, double 2.0)
94 ; CHECK: fmov d0, #2.0
95 ; CHECK: orr w1, wzr, #0x1
100 ; We weren't marking x7 as used after deciding that the i128 didn't fit into
101 ; registers and putting the first half on the stack, so the *second* half went
103 define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) {
104 ; CHECK-LABEL: test_i128_shadow:
105 ; CHECK: ldp x0, x1, [sp]
110 ; This test is to check if fp128 can be correctly handled on stack.
111 define fp128 @test_fp128([8 x float] %arg0, fp128 %arg1) {
112 ; CHECK-LABEL: test_fp128:
113 ; CHECK: ldr {{q[0-9]+}}, [sp]
117 ; Check if VPR can be correctly pass by stack.
118 define <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) {
120 ; CHECK-LABEL: test_vreg_stack:
121 ; CHECK: ldr {{q[0-9]+}}, [sp]
122 ret <2 x double> %varg_stack;
125 ; Check that f16 can be passed and returned (ACLE 2.0 extension)
126 define half @test_half(float, half %arg) {
127 ; CHECK-LABEL: test_half:
128 ; CHECK: mov v0.16b, v1.16b
132 ; Check that f16 constants are materialized correctly
133 define half @test_half_const() {
134 ; CHECK-LABEL: test_half_const:
135 ; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}]
139 ; Check that v4f16 can be passed and returned in registers
140 define <4 x half> @test_v4_half_register(float, <4 x half> %arg) {
141 ; CHECK-LABEL: test_v4_half_register:
142 ; CHECK: mov v0.16b, v1.16b
146 ; Check that v8f16 can be passed and returned in registers
147 define <8 x half> @test_v8_half_register(float, <8 x half> %arg) {
148 ; CHECK-LABEL: test_v8_half_register:
149 ; CHECK: mov v0.16b, v1.16b
153 ; Check that v4f16 can be passed and returned on the stack
154 define <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) {
155 ; CHECK-LABEL: test_v4_half_stack:
156 ; CHECK: ldr d0, [sp]
160 ; Check that v8f16 can be passed and returned on the stack
161 define <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) {
162 ; CHECK-LABEL: test_v8_half_stack:
163 ; CHECK: ldr q0, [sp]