1 ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
3 ; Stackmap Header: no constants - 6 callsites
4 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
5 ; CHECK-NEXT: __LLVM_StackMaps:
17 ; Functions and stack size
18 ; CHECK-NEXT: .quad _test
19 ; CHECK-NEXT: .quad 16
20 ; CHECK-NEXT: .quad _property_access1
21 ; CHECK-NEXT: .quad 16
22 ; CHECK-NEXT: .quad _property_access2
23 ; CHECK-NEXT: .quad 32
24 ; CHECK-NEXT: .quad _property_access3
25 ; CHECK-NEXT: .quad 32
26 ; CHECK-NEXT: .quad _anyreg_test1
27 ; CHECK-NEXT: .quad 16
28 ; CHECK-NEXT: .quad _anyreg_test2
29 ; CHECK-NEXT: .quad 16
30 ; CHECK-NEXT: .quad _patchpoint_spilldef
31 ; CHECK-NEXT: .quad 112
32 ; CHECK-NEXT: .quad _patchpoint_spillargs
33 ; CHECK-NEXT: .quad 128
37 ; CHECK-LABEL: .long L{{.*}}-_test
38 ; CHECK-NEXT: .short 0
40 ; CHECK-NEXT: .short 3
44 ; CHECK-NEXT: .short {{[0-9]+}}
49 ; CHECK-NEXT: .short {{[0-9]+}}
54 ; CHECK-NEXT: .short 0
56 define i64 @test() nounwind ssp uwtable {
58 call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3)
62 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
63 ; CHECK-LABEL: .long L{{.*}}-_property_access1
64 ; CHECK-NEXT: .short 0
66 ; CHECK-NEXT: .short 2
67 ; Loc 0: Register <-- this is the return register
70 ; CHECK-NEXT: .short {{[0-9]+}}
75 ; CHECK-NEXT: .short {{[0-9]+}}
77 define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
79 %f = inttoptr i64 281474417671919 to i8*
80 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj)
84 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
85 ; CHECK-LABEL: .long L{{.*}}-_property_access2
86 ; CHECK-NEXT: .short 0
88 ; CHECK-NEXT: .short 2
89 ; Loc 0: Register <-- this is the return register
92 ; CHECK-NEXT: .short {{[0-9]+}}
97 ; CHECK-NEXT: .short {{[0-9]+}}
99 define i64 @property_access2() nounwind ssp uwtable {
101 %obj = alloca i64, align 8
102 %f = inttoptr i64 281474417671919 to i8*
103 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj)
107 ; property access 3 - %obj is a frame index
108 ; CHECK-LABEL: .long L{{.*}}-_property_access3
109 ; CHECK-NEXT: .short 0
111 ; CHECK-NEXT: .short 2
112 ; Loc 0: Register <-- this is the return register
113 ; CHECK-NEXT: .byte 1
114 ; CHECK-NEXT: .byte 8
115 ; CHECK-NEXT: .short {{[0-9]+}}
116 ; CHECK-NEXT: .long 0
117 ; Loc 1: Direct FP - 8
118 ; CHECK-NEXT: .byte 2
119 ; CHECK-NEXT: .byte 8
120 ; CHECK-NEXT: .short 29
121 ; CHECK-NEXT: .long -8
122 define i64 @property_access3() nounwind ssp uwtable {
124 %obj = alloca i64, align 8
125 %f = inttoptr i64 281474417671919 to i8*
126 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj)
131 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
132 ; CHECK-NEXT: .short 0
134 ; CHECK-NEXT: .short 14
135 ; Loc 0: Register <-- this is the return register
136 ; CHECK-NEXT: .byte 1
137 ; CHECK-NEXT: .byte 8
138 ; CHECK-NEXT: .short {{[0-9]+}}
139 ; CHECK-NEXT: .long 0
141 ; CHECK-NEXT: .byte 1
142 ; CHECK-NEXT: .byte 8
143 ; CHECK-NEXT: .short {{[0-9]+}}
144 ; CHECK-NEXT: .long 0
146 ; CHECK-NEXT: .byte 1
147 ; CHECK-NEXT: .byte 8
148 ; CHECK-NEXT: .short {{[0-9]+}}
149 ; CHECK-NEXT: .long 0
151 ; CHECK-NEXT: .byte 1
152 ; CHECK-NEXT: .byte 8
153 ; CHECK-NEXT: .short {{[0-9]+}}
154 ; CHECK-NEXT: .long 0
156 ; CHECK-NEXT: .byte 1
157 ; CHECK-NEXT: .byte 8
158 ; CHECK-NEXT: .short {{[0-9]+}}
159 ; CHECK-NEXT: .long 0
161 ; CHECK-NEXT: .byte 1
162 ; CHECK-NEXT: .byte 8
163 ; CHECK-NEXT: .short {{[0-9]+}}
164 ; CHECK-NEXT: .long 0
166 ; CHECK-NEXT: .byte 1
167 ; CHECK-NEXT: .byte 8
168 ; CHECK-NEXT: .short {{[0-9]+}}
169 ; CHECK-NEXT: .long 0
171 ; CHECK-NEXT: .byte 1
172 ; CHECK-NEXT: .byte 8
173 ; CHECK-NEXT: .short {{[0-9]+}}
174 ; CHECK-NEXT: .long 0
176 ; CHECK-NEXT: .byte 1
177 ; CHECK-NEXT: .byte 8
178 ; CHECK-NEXT: .short {{[0-9]+}}
179 ; CHECK-NEXT: .long 0
181 ; CHECK-NEXT: .byte 1
182 ; CHECK-NEXT: .byte 8
183 ; CHECK-NEXT: .short {{[0-9]+}}
184 ; CHECK-NEXT: .long 0
186 ; CHECK-NEXT: .byte 1
187 ; CHECK-NEXT: .byte 8
188 ; CHECK-NEXT: .short {{[0-9]+}}
189 ; CHECK-NEXT: .long 0
191 ; CHECK-NEXT: .byte 1
192 ; CHECK-NEXT: .byte 8
193 ; CHECK-NEXT: .short {{[0-9]+}}
194 ; CHECK-NEXT: .long 0
196 ; CHECK-NEXT: .byte 1
197 ; CHECK-NEXT: .byte 8
198 ; CHECK-NEXT: .short {{[0-9]+}}
199 ; CHECK-NEXT: .long 0
201 ; CHECK-NEXT: .byte 1
202 ; CHECK-NEXT: .byte 8
203 ; CHECK-NEXT: .short {{[0-9]+}}
204 ; CHECK-NEXT: .long 0
205 define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
207 %f = inttoptr i64 281474417671919 to i8*
208 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
213 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
214 ; CHECK-NEXT: .short 0
216 ; CHECK-NEXT: .short 14
217 ; Loc 0: Register <-- this is the return register
218 ; CHECK-NEXT: .byte 1
219 ; CHECK-NEXT: .byte 8
220 ; CHECK-NEXT: .short {{[0-9]+}}
221 ; CHECK-NEXT: .long 0
223 ; CHECK-NEXT: .byte 1
224 ; CHECK-NEXT: .byte 8
225 ; CHECK-NEXT: .short {{[0-9]+}}
226 ; CHECK-NEXT: .long 0
228 ; CHECK-NEXT: .byte 1
229 ; CHECK-NEXT: .byte 8
230 ; CHECK-NEXT: .short {{[0-9]+}}
231 ; CHECK-NEXT: .long 0
233 ; CHECK-NEXT: .byte 1
234 ; CHECK-NEXT: .byte 8
235 ; CHECK-NEXT: .short {{[0-9]+}}
236 ; CHECK-NEXT: .long 0
238 ; CHECK-NEXT: .byte 1
239 ; CHECK-NEXT: .byte 8
240 ; CHECK-NEXT: .short {{[0-9]+}}
241 ; CHECK-NEXT: .long 0
243 ; CHECK-NEXT: .byte 1
244 ; CHECK-NEXT: .byte 8
245 ; CHECK-NEXT: .short {{[0-9]+}}
246 ; CHECK-NEXT: .long 0
248 ; CHECK-NEXT: .byte 1
249 ; CHECK-NEXT: .byte 8
250 ; CHECK-NEXT: .short {{[0-9]+}}
251 ; CHECK-NEXT: .long 0
253 ; CHECK-NEXT: .byte 1
254 ; CHECK-NEXT: .byte 8
255 ; CHECK-NEXT: .short {{[0-9]+}}
256 ; CHECK-NEXT: .long 0
258 ; CHECK-NEXT: .byte 1
259 ; CHECK-NEXT: .byte 8
260 ; CHECK-NEXT: .short {{[0-9]+}}
261 ; CHECK-NEXT: .long 0
263 ; CHECK-NEXT: .byte 1
264 ; CHECK-NEXT: .byte 8
265 ; CHECK-NEXT: .short {{[0-9]+}}
266 ; CHECK-NEXT: .long 0
268 ; CHECK-NEXT: .byte 1
269 ; CHECK-NEXT: .byte 8
270 ; CHECK-NEXT: .short {{[0-9]+}}
271 ; CHECK-NEXT: .long 0
273 ; CHECK-NEXT: .byte 1
274 ; CHECK-NEXT: .byte 8
275 ; CHECK-NEXT: .short {{[0-9]+}}
276 ; CHECK-NEXT: .long 0
278 ; CHECK-NEXT: .byte 1
279 ; CHECK-NEXT: .byte 8
280 ; CHECK-NEXT: .short {{[0-9]+}}
281 ; CHECK-NEXT: .long 0
283 ; CHECK-NEXT: .byte 1
284 ; CHECK-NEXT: .byte 8
285 ; CHECK-NEXT: .short {{[0-9]+}}
286 ; CHECK-NEXT: .long 0
287 define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
289 %f = inttoptr i64 281474417671919 to i8*
290 %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
294 ; Test spilling the return value of an anyregcc call.
296 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
298 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
299 ; CHECK-NEXT: .short 0
300 ; CHECK-NEXT: .short 3
301 ; Loc 0: Register (some register that will be spilled to the stack)
302 ; CHECK-NEXT: .byte 1
303 ; CHECK-NEXT: .byte 8
304 ; CHECK-NEXT: .short {{[0-9]+}}
305 ; CHECK-NEXT: .long 0
307 ; CHECK-NEXT: .byte 1
308 ; CHECK-NEXT: .byte 8
309 ; CHECK-NEXT: .short {{[0-9]+}}
310 ; CHECK-NEXT: .long 0
312 ; CHECK-NEXT: .byte 1
313 ; CHECK-NEXT: .byte 8
314 ; CHECK-NEXT: .short {{[0-9]+}}
315 ; CHECK-NEXT: .long 0
316 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
318 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
319 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
323 ; Test spilling the arguments of an anyregcc call.
325 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
327 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
328 ; CHECK-NEXT: .short 0
329 ; CHECK-NEXT: .short 5
330 ; Loc 0: Return a register
331 ; CHECK-NEXT: .byte 1
332 ; CHECK-NEXT: .byte 8
333 ; CHECK-NEXT: .short {{[0-9]+}}
334 ; CHECK-NEXT: .long 0
335 ; Loc 1: Arg0 in a Register
336 ; CHECK-NEXT: .byte 1
337 ; CHECK-NEXT: .byte 8
338 ; CHECK-NEXT: .short {{[0-9]+}}
339 ; CHECK-NEXT: .long 0
340 ; Loc 2: Arg1 in a Register
341 ; CHECK-NEXT: .byte 1
342 ; CHECK-NEXT: .byte 8
343 ; CHECK-NEXT: .short {{[0-9]+}}
344 ; CHECK-NEXT: .long 0
345 ; Loc 3: Arg2 spilled to FP -96
346 ; CHECK-NEXT: .byte 3
347 ; CHECK-NEXT: .byte 8
348 ; CHECK-NEXT: .short 29
349 ; CHECK-NEXT: .long -96
350 ; Loc 4: Arg3 spilled to FP - 88
351 ; CHECK-NEXT: .byte 3
352 ; CHECK-NEXT: .byte 8
353 ; CHECK-NEXT: .short 29
354 ; CHECK-NEXT: .long -88
355 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
357 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
358 %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
362 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
363 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)