1 ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s
2 ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel < %s | FileCheck %s --check-prefix=FAST
4 ; One argument will be passed in register, the other will be pushed on the stack.
6 define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
8 ; CHECK-LABEL: jscall_patchpoint_codegen:
10 ; CHECK: str x{{.+}}, [sp]
11 ; CHECK-NEXT: mov x0, x{{.+}}
13 ; CHECK-NEXT: movz x16, #0xffff, lsl #32
14 ; CHECK-NEXT: movk x16, #0xdead, lsl #16
15 ; CHECK-NEXT: movk x16, #0xbeef
17 ; FAST-LABEL: jscall_patchpoint_codegen:
19 ; FAST: str x{{.+}}, [sp]
21 ; FAST-NEXT: movz x16, #0xffff, lsl #32
22 ; FAST-NEXT: movk x16, #0xdead, lsl #16
23 ; FAST-NEXT: movk x16, #0xbeef
25 %resolveCall2 = inttoptr i64 281474417671919 to i8*
26 %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
27 %resolveCall3 = inttoptr i64 244837814038255 to i8*
28 tail call webkit_jscc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
32 ; Test if the arguments are properly aligned and that we don't store undef arguments.
33 define i64 @jscall_patchpoint_codegen2(i64 %callee) {
35 ; CHECK-LABEL: jscall_patchpoint_codegen2:
37 ; CHECK: orr w[[REG:[0-9]+]], wzr, #0x6
38 ; CHECK-NEXT: str x[[REG]], [sp, #24]
39 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
40 ; CHECK-NEXT: str w[[REG]], [sp, #16]
41 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
42 ; CHECK-NEXT: str x[[REG]], [sp]
44 ; CHECK-NEXT: movz x16, #0xffff, lsl #32
45 ; CHECK-NEXT: movk x16, #0xdead, lsl #16
46 ; CHECK-NEXT: movk x16, #0xbeef
48 ; FAST-LABEL: jscall_patchpoint_codegen2:
50 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
51 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
52 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
53 ; FAST-NEXT: str [[REG1]], [sp]
54 ; FAST-NEXT: str [[REG2]], [sp, #16]
55 ; FAST-NEXT: str [[REG3]], [sp, #24]
57 ; FAST-NEXT: movz x16, #0xffff, lsl #32
58 ; FAST-NEXT: movk x16, #0xdead, lsl #16
59 ; FAST-NEXT: movk x16, #0xbeef
61 %call = inttoptr i64 281474417671919 to i8*
62 %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
66 ; Test if the arguments are properly aligned and that we don't store undef arguments.
67 define i64 @jscall_patchpoint_codegen3(i64 %callee) {
69 ; CHECK-LABEL: jscall_patchpoint_codegen3:
71 ; CHECK: movz w[[REG:[0-9]+]], #0xa
72 ; CHECK-NEXT: str x[[REG]], [sp, #48]
73 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8
74 ; CHECK-NEXT: str w[[REG]], [sp, #36]
75 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x6
76 ; CHECK-NEXT: str x[[REG]], [sp, #24]
77 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x4
78 ; CHECK-NEXT: str w[[REG]], [sp, #16]
79 ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2
80 ; CHECK-NEXT: str x[[REG]], [sp]
82 ; CHECK-NEXT: movz x16, #0xffff, lsl #32
83 ; CHECK-NEXT: movk x16, #0xdead, lsl #16
84 ; CHECK-NEXT: movk x16, #0xbeef
86 ; FAST-LABEL: jscall_patchpoint_codegen3:
88 ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2
89 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4
90 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6
91 ; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8
92 ; FAST-NEXT: movz [[REG5:x[0-9]+]], #0xa
93 ; FAST-NEXT: str [[REG1]], [sp]
94 ; FAST-NEXT: str [[REG2]], [sp, #16]
95 ; FAST-NEXT: str [[REG3]], [sp, #24]
96 ; FAST-NEXT: str [[REG4]], [sp, #36]
97 ; FAST-NEXT: str [[REG5]], [sp, #48]
99 ; FAST-NEXT: movz x16, #0xffff, lsl #32
100 ; FAST-NEXT: movk x16, #0xdead, lsl #16
101 ; FAST-NEXT: movk x16, #0xbeef
103 %call = inttoptr i64 281474417671919 to i8*
104 %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
108 ; CHECK-LABEL: test_i16:
109 ; CHECK: ldrh [[BREG:w[0-9]+]], [sp]
110 ; CHECK: add {{w[0-9]+}}, w0, [[BREG]]
111 define webkit_jscc zeroext i16 @test_i16(i16 zeroext %a, i16 zeroext %b) {
112 %sum = add i16 %a, %b
116 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
117 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)