1 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
2 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
5 ; Get the actual value of the overflow bit.
7 define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) {
9 ; CHECK-LABEL: saddo1.i32
10 ; CHECK: adds {{w[0-9]+}}, w0, w1
11 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
12 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
13 %val = extractvalue {i32, i1} %t, 0
14 %obit = extractvalue {i32, i1} %t, 1
15 store i32 %val, i32* %res
19 ; Test the immediate version.
20 define zeroext i1 @saddo2.i32(i32 %v1, i32* %res) {
22 ; CHECK-LABEL: saddo2.i32
23 ; CHECK: adds {{w[0-9]+}}, w0, #4
24 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
25 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 4)
26 %val = extractvalue {i32, i1} %t, 0
27 %obit = extractvalue {i32, i1} %t, 1
28 store i32 %val, i32* %res
32 ; Test negative immediates.
33 define zeroext i1 @saddo3.i32(i32 %v1, i32* %res) {
35 ; CHECK-LABEL: saddo3.i32
36 ; CHECK: subs {{w[0-9]+}}, w0, #4
37 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
38 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 -4)
39 %val = extractvalue {i32, i1} %t, 0
40 %obit = extractvalue {i32, i1} %t, 1
41 store i32 %val, i32* %res
45 ; Test immediates that are too large to be encoded.
46 define zeroext i1 @saddo4.i32(i32 %v1, i32* %res) {
48 ; CHECK-LABEL: saddo4.i32
49 ; CHECK: adds {{w[0-9]+}}, w0, {{w[0-9]+}}
50 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
51 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 16777215)
52 %val = extractvalue {i32, i1} %t, 0
53 %obit = extractvalue {i32, i1} %t, 1
54 store i32 %val, i32* %res
59 define zeroext i1 @saddo5.i32(i32 %v1, i32 %v2, i32* %res) {
61 ; CHECK-LABEL: saddo5.i32
62 ; CHECK: adds {{w[0-9]+}}, w0, w1
63 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
64 %lsl = shl i32 %v2, 16
65 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %lsl)
66 %val = extractvalue {i32, i1} %t, 0
67 %obit = extractvalue {i32, i1} %t, 1
68 store i32 %val, i32* %res
72 define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) {
74 ; CHECK-LABEL: saddo1.i64
75 ; CHECK: adds {{x[0-9]+}}, x0, x1
76 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
77 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
78 %val = extractvalue {i64, i1} %t, 0
79 %obit = extractvalue {i64, i1} %t, 1
80 store i64 %val, i64* %res
84 define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) {
86 ; CHECK-LABEL: saddo2.i64
87 ; CHECK: adds {{x[0-9]+}}, x0, #4
88 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
89 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
90 %val = extractvalue {i64, i1} %t, 0
91 %obit = extractvalue {i64, i1} %t, 1
92 store i64 %val, i64* %res
96 define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) {
98 ; CHECK-LABEL: saddo3.i64
99 ; CHECK: subs {{x[0-9]+}}, x0, #4
100 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
101 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -4)
102 %val = extractvalue {i64, i1} %t, 0
103 %obit = extractvalue {i64, i1} %t, 1
104 store i64 %val, i64* %res
108 define zeroext i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
110 ; CHECK-LABEL: uaddo.i32
111 ; CHECK: adds {{w[0-9]+}}, w0, w1
112 ; CHECK-NEXT: cset {{w[0-9]+}}, hs
113 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
114 %val = extractvalue {i32, i1} %t, 0
115 %obit = extractvalue {i32, i1} %t, 1
116 store i32 %val, i32* %res
120 define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
122 ; CHECK-LABEL: uaddo.i64
123 ; CHECK: adds {{x[0-9]+}}, x0, x1
124 ; CHECK-NEXT: cset {{w[0-9]+}}, hs
125 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
126 %val = extractvalue {i64, i1} %t, 0
127 %obit = extractvalue {i64, i1} %t, 1
128 store i64 %val, i64* %res
132 define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) {
134 ; CHECK-LABEL: ssubo1.i32
135 ; CHECK: subs {{w[0-9]+}}, w0, w1
136 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
137 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
138 %val = extractvalue {i32, i1} %t, 0
139 %obit = extractvalue {i32, i1} %t, 1
140 store i32 %val, i32* %res
144 define zeroext i1 @ssubo2.i32(i32 %v1, i32* %res) {
146 ; CHECK-LABEL: ssubo2.i32
147 ; CHECK: adds {{w[0-9]+}}, w0, #4
148 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
149 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 -4)
150 %val = extractvalue {i32, i1} %t, 0
151 %obit = extractvalue {i32, i1} %t, 1
152 store i32 %val, i32* %res
156 define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
158 ; CHECK-LABEL: ssubo.i64
159 ; CHECK: subs {{x[0-9]+}}, x0, x1
160 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
161 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
162 %val = extractvalue {i64, i1} %t, 0
163 %obit = extractvalue {i64, i1} %t, 1
164 store i64 %val, i64* %res
168 define zeroext i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
170 ; CHECK-LABEL: usubo.i32
171 ; CHECK: subs {{w[0-9]+}}, w0, w1
172 ; CHECK-NEXT: cset {{w[0-9]+}}, lo
173 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
174 %val = extractvalue {i32, i1} %t, 0
175 %obit = extractvalue {i32, i1} %t, 1
176 store i32 %val, i32* %res
180 define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
182 ; CHECK-LABEL: usubo.i64
183 ; CHECK: subs {{x[0-9]+}}, x0, x1
184 ; CHECK-NEXT: cset {{w[0-9]+}}, lo
185 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
186 %val = extractvalue {i64, i1} %t, 0
187 %obit = extractvalue {i64, i1} %t, 1
188 store i64 %val, i64* %res
192 define zeroext i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
194 ; CHECK-LABEL: smulo.i32
195 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
196 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
197 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
198 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
199 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
200 %val = extractvalue {i32, i1} %t, 0
201 %obit = extractvalue {i32, i1} %t, 1
202 store i32 %val, i32* %res
206 define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
208 ; CHECK-LABEL: smulo.i64
209 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
210 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
211 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
212 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
213 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
214 %val = extractvalue {i64, i1} %t, 0
215 %obit = extractvalue {i64, i1} %t, 1
216 store i64 %val, i64* %res
220 define zeroext i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
222 ; CHECK-LABEL: umulo.i32
223 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
224 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
225 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
226 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
227 %val = extractvalue {i32, i1} %t, 0
228 %obit = extractvalue {i32, i1} %t, 1
229 store i32 %val, i32* %res
233 define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
235 ; CHECK-LABEL: umulo.i64
236 ; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
237 ; CHECK-NEXT: cmp xzr, [[MREG]]
238 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
239 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
240 %val = extractvalue {i64, i1} %t, 0
241 %obit = extractvalue {i64, i1} %t, 1
242 store i64 %val, i64* %res
248 ; Check the use of the overflow bit in combination with a select instruction.
250 define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
252 ; CHECK-LABEL: saddo.select.i32
254 ; CHECK-NEXT: csel w0, w0, w1, vs
255 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
256 %obit = extractvalue {i32, i1} %t, 1
257 %ret = select i1 %obit, i32 %v1, i32 %v2
261 define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
263 ; CHECK-LABEL: saddo.select.i64
265 ; CHECK-NEXT: csel x0, x0, x1, vs
266 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
267 %obit = extractvalue {i64, i1} %t, 1
268 %ret = select i1 %obit, i64 %v1, i64 %v2
272 define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
274 ; CHECK-LABEL: uaddo.select.i32
276 ; CHECK-NEXT: csel w0, w0, w1, hs
277 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
278 %obit = extractvalue {i32, i1} %t, 1
279 %ret = select i1 %obit, i32 %v1, i32 %v2
283 define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
285 ; CHECK-LABEL: uaddo.select.i64
287 ; CHECK-NEXT: csel x0, x0, x1, hs
288 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
289 %obit = extractvalue {i64, i1} %t, 1
290 %ret = select i1 %obit, i64 %v1, i64 %v2
294 define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
296 ; CHECK-LABEL: ssubo.select.i32
298 ; CHECK-NEXT: csel w0, w0, w1, vs
299 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
300 %obit = extractvalue {i32, i1} %t, 1
301 %ret = select i1 %obit, i32 %v1, i32 %v2
305 define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
307 ; CHECK-LABEL: ssubo.select.i64
309 ; CHECK-NEXT: csel x0, x0, x1, vs
310 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
311 %obit = extractvalue {i64, i1} %t, 1
312 %ret = select i1 %obit, i64 %v1, i64 %v2
316 define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
318 ; CHECK-LABEL: usubo.select.i32
320 ; CHECK-NEXT: csel w0, w0, w1, lo
321 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
322 %obit = extractvalue {i32, i1} %t, 1
323 %ret = select i1 %obit, i32 %v1, i32 %v2
327 define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
329 ; CHECK-LABEL: usubo.select.i64
331 ; CHECK-NEXT: csel x0, x0, x1, lo
332 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
333 %obit = extractvalue {i64, i1} %t, 1
334 %ret = select i1 %obit, i64 %v1, i64 %v2
338 define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
340 ; CHECK-LABEL: smulo.select.i32
341 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
342 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
343 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
344 ; CHECK-NEXT: csel w0, w0, w1, ne
345 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
346 %obit = extractvalue {i32, i1} %t, 1
347 %ret = select i1 %obit, i32 %v1, i32 %v2
351 define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
353 ; CHECK-LABEL: smulo.select.i64
354 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
355 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
356 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
357 ; CHECK-NEXT: csel x0, x0, x1, ne
358 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
359 %obit = extractvalue {i64, i1} %t, 1
360 %ret = select i1 %obit, i64 %v1, i64 %v2
364 define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
366 ; CHECK-LABEL: umulo.select.i32
367 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
368 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
369 ; CHECK-NEXT: csel w0, w0, w1, ne
370 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
371 %obit = extractvalue {i32, i1} %t, 1
372 %ret = select i1 %obit, i32 %v1, i32 %v2
376 define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
378 ; CHECK-LABEL: umulo.select.i64
379 ; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
380 ; CHECK-NEXT: cmp xzr, [[MREG]]
381 ; CHECK-NEXT: csel x0, x0, x1, ne
382 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
383 %obit = extractvalue {i64, i1} %t, 1
384 %ret = select i1 %obit, i64 %v1, i64 %v2
390 ; Check the use of the overflow bit in combination with a branch instruction.
392 define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
394 ; CHECK-LABEL: saddo.br.i32
397 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
398 %val = extractvalue {i32, i1} %t, 0
399 %obit = extractvalue {i32, i1} %t, 1
400 br i1 %obit, label %overflow, label %continue
409 define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
411 ; CHECK-LABEL: saddo.br.i64
414 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
415 %val = extractvalue {i64, i1} %t, 0
416 %obit = extractvalue {i64, i1} %t, 1
417 br i1 %obit, label %overflow, label %continue
426 define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
428 ; CHECK-LABEL: uaddo.br.i32
431 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
432 %val = extractvalue {i32, i1} %t, 0
433 %obit = extractvalue {i32, i1} %t, 1
434 br i1 %obit, label %overflow, label %continue
443 define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
445 ; CHECK-LABEL: uaddo.br.i64
448 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
449 %val = extractvalue {i64, i1} %t, 0
450 %obit = extractvalue {i64, i1} %t, 1
451 br i1 %obit, label %overflow, label %continue
460 define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
462 ; CHECK-LABEL: ssubo.br.i32
465 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
466 %val = extractvalue {i32, i1} %t, 0
467 %obit = extractvalue {i32, i1} %t, 1
468 br i1 %obit, label %overflow, label %continue
477 define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
479 ; CHECK-LABEL: ssubo.br.i64
482 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
483 %val = extractvalue {i64, i1} %t, 0
484 %obit = extractvalue {i64, i1} %t, 1
485 br i1 %obit, label %overflow, label %continue
494 define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
496 ; CHECK-LABEL: usubo.br.i32
499 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
500 %val = extractvalue {i32, i1} %t, 0
501 %obit = extractvalue {i32, i1} %t, 1
502 br i1 %obit, label %overflow, label %continue
511 define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
513 ; CHECK-LABEL: usubo.br.i64
516 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
517 %val = extractvalue {i64, i1} %t, 0
518 %obit = extractvalue {i64, i1} %t, 1
519 br i1 %obit, label %overflow, label %continue
528 define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
530 ; CHECK-LABEL: smulo.br.i32
531 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
532 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x8, #32
533 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
535 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
536 %val = extractvalue {i32, i1} %t, 0
537 %obit = extractvalue {i32, i1} %t, 1
538 br i1 %obit, label %overflow, label %continue
547 define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
549 ; CHECK-LABEL: smulo.br.i64
550 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
551 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
552 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
554 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
555 %val = extractvalue {i64, i1} %t, 0
556 %obit = extractvalue {i64, i1} %t, 1
557 br i1 %obit, label %overflow, label %continue
566 define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
568 ; CHECK-LABEL: umulo.br.i32
569 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
570 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
572 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
573 %val = extractvalue {i32, i1} %t, 0
574 %obit = extractvalue {i32, i1} %t, 1
575 br i1 %obit, label %overflow, label %continue
584 define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
586 ; CHECK-LABEL: umulo.br.i64
587 ; CHECK: umulh [[REG:x[0-9]+]], x0, x1
588 ; CHECK-NEXT: {{cbz|cmp}}
589 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
590 %val = extractvalue {i64, i1} %t, 0
591 %obit = extractvalue {i64, i1} %t, 1
592 br i1 %obit, label %overflow, label %continue
601 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
602 declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
603 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
604 declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
605 declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
606 declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
607 declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
608 declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
609 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
610 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
611 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
612 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone