1 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
2 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
5 ; Get the actual value of the overflow bit.
7 define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) {
9 ; CHECK-LABEL: saddo1.i32
10 ; CHECK: adds {{w[0-9]+}}, w0, w1
11 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
12 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
13 %val = extractvalue {i32, i1} %t, 0
14 %obit = extractvalue {i32, i1} %t, 1
15 store i32 %val, i32* %res
19 ; Test the immediate version.
20 define zeroext i1 @saddo2.i32(i32 %v1, i32* %res) {
22 ; CHECK-LABEL: saddo2.i32
23 ; CHECK: adds {{w[0-9]+}}, w0, #4
24 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
25 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 4)
26 %val = extractvalue {i32, i1} %t, 0
27 %obit = extractvalue {i32, i1} %t, 1
28 store i32 %val, i32* %res
32 ; Test negative immediates.
33 define zeroext i1 @saddo3.i32(i32 %v1, i32* %res) {
35 ; CHECK-LABEL: saddo3.i32
36 ; CHECK: subs {{w[0-9]+}}, w0, #4
37 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
38 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 -4)
39 %val = extractvalue {i32, i1} %t, 0
40 %obit = extractvalue {i32, i1} %t, 1
41 store i32 %val, i32* %res
45 ; Test immediates that are too large to be encoded.
46 define zeroext i1 @saddo4.i32(i32 %v1, i32* %res) {
48 ; CHECK-LABEL: saddo4.i32
49 ; CHECK: adds {{w[0-9]+}}, w0, {{w[0-9]+}}
50 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
51 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 16777215)
52 %val = extractvalue {i32, i1} %t, 0
53 %obit = extractvalue {i32, i1} %t, 1
54 store i32 %val, i32* %res
59 define zeroext i1 @saddo5.i32(i32 %v1, i32 %v2, i32* %res) {
61 ; CHECK-LABEL: saddo5.i32
62 ; CHECK: adds {{w[0-9]+}}, w0, w1
63 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
64 %lsl = shl i32 %v2, 16
65 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %lsl)
66 %val = extractvalue {i32, i1} %t, 0
67 %obit = extractvalue {i32, i1} %t, 1
68 store i32 %val, i32* %res
72 define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) {
74 ; CHECK-LABEL: saddo1.i64
75 ; CHECK: adds {{x[0-9]+}}, x0, x1
76 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
77 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
78 %val = extractvalue {i64, i1} %t, 0
79 %obit = extractvalue {i64, i1} %t, 1
80 store i64 %val, i64* %res
84 define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) {
86 ; CHECK-LABEL: saddo2.i64
87 ; CHECK: adds {{x[0-9]+}}, x0, #4
88 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
89 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
90 %val = extractvalue {i64, i1} %t, 0
91 %obit = extractvalue {i64, i1} %t, 1
92 store i64 %val, i64* %res
96 define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) {
98 ; CHECK-LABEL: saddo3.i64
99 ; CHECK: subs {{x[0-9]+}}, x0, #4
100 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
101 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -4)
102 %val = extractvalue {i64, i1} %t, 0
103 %obit = extractvalue {i64, i1} %t, 1
104 store i64 %val, i64* %res
108 define zeroext i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
110 ; CHECK-LABEL: uaddo.i32
111 ; CHECK: adds {{w[0-9]+}}, w0, w1
112 ; CHECK-NEXT: cset {{w[0-9]+}}, hs
113 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
114 %val = extractvalue {i32, i1} %t, 0
115 %obit = extractvalue {i32, i1} %t, 1
116 store i32 %val, i32* %res
120 define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
122 ; CHECK-LABEL: uaddo.i64
123 ; CHECK: adds {{x[0-9]+}}, x0, x1
124 ; CHECK-NEXT: cset {{w[0-9]+}}, hs
125 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
126 %val = extractvalue {i64, i1} %t, 0
127 %obit = extractvalue {i64, i1} %t, 1
128 store i64 %val, i64* %res
132 define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) {
134 ; CHECK-LABEL: ssubo1.i32
135 ; CHECK: subs {{w[0-9]+}}, w0, w1
136 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
137 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
138 %val = extractvalue {i32, i1} %t, 0
139 %obit = extractvalue {i32, i1} %t, 1
140 store i32 %val, i32* %res
144 define zeroext i1 @ssubo2.i32(i32 %v1, i32* %res) {
146 ; CHECK-LABEL: ssubo2.i32
147 ; CHECK: adds {{w[0-9]+}}, w0, #4
148 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
149 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 -4)
150 %val = extractvalue {i32, i1} %t, 0
151 %obit = extractvalue {i32, i1} %t, 1
152 store i32 %val, i32* %res
156 define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
158 ; CHECK-LABEL: ssubo.i64
159 ; CHECK: subs {{x[0-9]+}}, x0, x1
160 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
161 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
162 %val = extractvalue {i64, i1} %t, 0
163 %obit = extractvalue {i64, i1} %t, 1
164 store i64 %val, i64* %res
168 define zeroext i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
170 ; CHECK-LABEL: usubo.i32
171 ; CHECK: subs {{w[0-9]+}}, w0, w1
172 ; CHECK-NEXT: cset {{w[0-9]+}}, lo
173 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
174 %val = extractvalue {i32, i1} %t, 0
175 %obit = extractvalue {i32, i1} %t, 1
176 store i32 %val, i32* %res
180 define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
182 ; CHECK-LABEL: usubo.i64
183 ; CHECK: subs {{x[0-9]+}}, x0, x1
184 ; CHECK-NEXT: cset {{w[0-9]+}}, lo
185 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
186 %val = extractvalue {i64, i1} %t, 0
187 %obit = extractvalue {i64, i1} %t, 1
188 store i64 %val, i64* %res
192 define zeroext i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
194 ; CHECK-LABEL: smulo.i32
195 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
196 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
197 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
198 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
199 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
200 %val = extractvalue {i32, i1} %t, 0
201 %obit = extractvalue {i32, i1} %t, 1
202 store i32 %val, i32* %res
206 define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
208 ; CHECK-LABEL: smulo.i64
209 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
210 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
211 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
212 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
213 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
214 %val = extractvalue {i64, i1} %t, 0
215 %obit = extractvalue {i64, i1} %t, 1
216 store i64 %val, i64* %res
220 define zeroext i1 @smulo2.i64(i64 %v1, i64* %res) {
222 ; CHECK-LABEL: smulo2.i64
223 ; CHECK: adds [[MREG:x[0-9]+]], x0, x0
224 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
225 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 2)
226 %val = extractvalue {i64, i1} %t, 0
227 %obit = extractvalue {i64, i1} %t, 1
228 store i64 %val, i64* %res
232 define zeroext i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
234 ; CHECK-LABEL: umulo.i32
235 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
236 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
237 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
238 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
239 %val = extractvalue {i32, i1} %t, 0
240 %obit = extractvalue {i32, i1} %t, 1
241 store i32 %val, i32* %res
245 define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
247 ; CHECK-LABEL: umulo.i64
248 ; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
249 ; CHECK-NEXT: cmp xzr, [[MREG]]
250 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
251 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
252 %val = extractvalue {i64, i1} %t, 0
253 %obit = extractvalue {i64, i1} %t, 1
254 store i64 %val, i64* %res
258 define zeroext i1 @umulo2.i64(i64 %v1, i64* %res) {
260 ; CHECK-LABEL: umulo2.i64
261 ; CHECK: adds [[MREG:x[0-9]+]], x0, x0
262 ; CHECK-NEXT: cset {{w[0-9]+}}, hs
263 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 2)
264 %val = extractvalue {i64, i1} %t, 0
265 %obit = extractvalue {i64, i1} %t, 1
266 store i64 %val, i64* %res
272 ; Check the use of the overflow bit in combination with a select instruction.
274 define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
276 ; CHECK-LABEL: saddo.select.i32
278 ; CHECK-NEXT: csel w0, w0, w1, vs
279 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
280 %obit = extractvalue {i32, i1} %t, 1
281 %ret = select i1 %obit, i32 %v1, i32 %v2
285 define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
287 ; CHECK-LABEL: saddo.select.i64
289 ; CHECK-NEXT: csel x0, x0, x1, vs
290 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
291 %obit = extractvalue {i64, i1} %t, 1
292 %ret = select i1 %obit, i64 %v1, i64 %v2
296 define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
298 ; CHECK-LABEL: uaddo.select.i32
300 ; CHECK-NEXT: csel w0, w0, w1, hs
301 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
302 %obit = extractvalue {i32, i1} %t, 1
303 %ret = select i1 %obit, i32 %v1, i32 %v2
307 define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
309 ; CHECK-LABEL: uaddo.select.i64
311 ; CHECK-NEXT: csel x0, x0, x1, hs
312 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
313 %obit = extractvalue {i64, i1} %t, 1
314 %ret = select i1 %obit, i64 %v1, i64 %v2
318 define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
320 ; CHECK-LABEL: ssubo.select.i32
322 ; CHECK-NEXT: csel w0, w0, w1, vs
323 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
324 %obit = extractvalue {i32, i1} %t, 1
325 %ret = select i1 %obit, i32 %v1, i32 %v2
329 define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
331 ; CHECK-LABEL: ssubo.select.i64
333 ; CHECK-NEXT: csel x0, x0, x1, vs
334 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
335 %obit = extractvalue {i64, i1} %t, 1
336 %ret = select i1 %obit, i64 %v1, i64 %v2
340 define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
342 ; CHECK-LABEL: usubo.select.i32
344 ; CHECK-NEXT: csel w0, w0, w1, lo
345 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
346 %obit = extractvalue {i32, i1} %t, 1
347 %ret = select i1 %obit, i32 %v1, i32 %v2
351 define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
353 ; CHECK-LABEL: usubo.select.i64
355 ; CHECK-NEXT: csel x0, x0, x1, lo
356 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
357 %obit = extractvalue {i64, i1} %t, 1
358 %ret = select i1 %obit, i64 %v1, i64 %v2
362 define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
364 ; CHECK-LABEL: smulo.select.i32
365 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
366 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
367 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
368 ; CHECK-NEXT: csel w0, w0, w1, ne
369 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
370 %obit = extractvalue {i32, i1} %t, 1
371 %ret = select i1 %obit, i32 %v1, i32 %v2
375 define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
377 ; CHECK-LABEL: smulo.select.i64
378 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
379 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
380 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
381 ; CHECK-NEXT: csel x0, x0, x1, ne
382 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
383 %obit = extractvalue {i64, i1} %t, 1
384 %ret = select i1 %obit, i64 %v1, i64 %v2
388 define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
390 ; CHECK-LABEL: umulo.select.i32
391 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
392 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
393 ; CHECK-NEXT: csel w0, w0, w1, ne
394 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
395 %obit = extractvalue {i32, i1} %t, 1
396 %ret = select i1 %obit, i32 %v1, i32 %v2
400 define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
402 ; CHECK-LABEL: umulo.select.i64
403 ; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
404 ; CHECK-NEXT: cmp xzr, [[MREG]]
405 ; CHECK-NEXT: csel x0, x0, x1, ne
406 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
407 %obit = extractvalue {i64, i1} %t, 1
408 %ret = select i1 %obit, i64 %v1, i64 %v2
414 ; Check the use of the overflow bit in combination with a branch instruction.
416 define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
418 ; CHECK-LABEL: saddo.br.i32
421 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
422 %val = extractvalue {i32, i1} %t, 0
423 %obit = extractvalue {i32, i1} %t, 1
424 br i1 %obit, label %overflow, label %continue
433 define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
435 ; CHECK-LABEL: saddo.br.i64
438 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
439 %val = extractvalue {i64, i1} %t, 0
440 %obit = extractvalue {i64, i1} %t, 1
441 br i1 %obit, label %overflow, label %continue
450 define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
452 ; CHECK-LABEL: uaddo.br.i32
455 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
456 %val = extractvalue {i32, i1} %t, 0
457 %obit = extractvalue {i32, i1} %t, 1
458 br i1 %obit, label %overflow, label %continue
467 define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
469 ; CHECK-LABEL: uaddo.br.i64
472 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
473 %val = extractvalue {i64, i1} %t, 0
474 %obit = extractvalue {i64, i1} %t, 1
475 br i1 %obit, label %overflow, label %continue
484 define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
486 ; CHECK-LABEL: ssubo.br.i32
489 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
490 %val = extractvalue {i32, i1} %t, 0
491 %obit = extractvalue {i32, i1} %t, 1
492 br i1 %obit, label %overflow, label %continue
501 define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
503 ; CHECK-LABEL: ssubo.br.i64
506 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
507 %val = extractvalue {i64, i1} %t, 0
508 %obit = extractvalue {i64, i1} %t, 1
509 br i1 %obit, label %overflow, label %continue
518 define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
520 ; CHECK-LABEL: usubo.br.i32
523 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
524 %val = extractvalue {i32, i1} %t, 0
525 %obit = extractvalue {i32, i1} %t, 1
526 br i1 %obit, label %overflow, label %continue
535 define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
537 ; CHECK-LABEL: usubo.br.i64
540 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
541 %val = extractvalue {i64, i1} %t, 0
542 %obit = extractvalue {i64, i1} %t, 1
543 br i1 %obit, label %overflow, label %continue
552 define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
554 ; CHECK-LABEL: smulo.br.i32
555 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
556 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x8, #32
557 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
559 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
560 %val = extractvalue {i32, i1} %t, 0
561 %obit = extractvalue {i32, i1} %t, 1
562 br i1 %obit, label %overflow, label %continue
571 define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
573 ; CHECK-LABEL: smulo.br.i64
574 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
575 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
576 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
578 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
579 %val = extractvalue {i64, i1} %t, 0
580 %obit = extractvalue {i64, i1} %t, 1
581 br i1 %obit, label %overflow, label %continue
590 define zeroext i1 @smulo2.br.i64(i64 %v1) {
592 ; CHECK-LABEL: smulo2.br.i64
595 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 2)
596 %val = extractvalue {i64, i1} %t, 0
597 %obit = extractvalue {i64, i1} %t, 1
598 br i1 %obit, label %overflow, label %continue
607 define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
609 ; CHECK-LABEL: umulo.br.i32
610 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
611 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
613 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
614 %val = extractvalue {i32, i1} %t, 0
615 %obit = extractvalue {i32, i1} %t, 1
616 br i1 %obit, label %overflow, label %continue
625 define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
627 ; CHECK-LABEL: umulo.br.i64
628 ; CHECK: umulh [[REG:x[0-9]+]], x0, x1
629 ; CHECK-NEXT: {{cbz|cmp}}
630 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
631 %val = extractvalue {i64, i1} %t, 0
632 %obit = extractvalue {i64, i1} %t, 1
633 br i1 %obit, label %overflow, label %continue
642 define zeroext i1 @umulo2.br.i64(i64 %v1) {
644 ; CHECK-LABEL: umulo2.br.i64
647 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 2)
648 %val = extractvalue {i64, i1} %t, 0
649 %obit = extractvalue {i64, i1} %t, 1
650 br i1 %obit, label %overflow, label %continue
659 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
660 declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
661 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
662 declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
663 declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
664 declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
665 declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
666 declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
667 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
668 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
669 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
670 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone