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[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR.
[oota-llvm.git]
/
test
/
CodeGen
/
AArch64
/
arm64-zext.ll
1
; RUN: llc < %s -march=arm64 | FileCheck %s
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define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: foo:
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; CHECK: add w0, w1, w0
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; CHECK: ret
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%add = add i32 %b, %a
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%conv = zext i32 %add to i64
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ret i64 %conv
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}