1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon
2 ; Bug: i8 type in FRP8 register but not registering with register class causes segmentation fault.
3 ; Fix: Removed i8 type from FPR8 register class.
5 ; Not relevant to arm64.
7 define void @test_concatvector_v8i8() {
9 br i1 undef, label %if.then, label %if.end
11 if.then: ; preds = %entry.split
14 if.end: ; preds = %entry.split
15 br i1 undef, label %if.then9, label %if.end18
17 if.then9: ; preds = %if.end
20 if.end18: ; preds = %if.end
23 for.body: ; preds = %for.inc, %if.end18
24 br i1 false, label %if.then30, label %for.inc
26 if.then30: ; preds = %for.body
29 for.inc: ; preds = %for.body
30 br i1 undef, label %for.end, label %for.body
32 for.end: ; preds = %for.inc
35 for.body77: ; preds = %for.body77, %for.end
36 br i1 undef, label %for.end106, label %for.body77
38 for.end106: ; preds = %for.body77
39 br i1 undef, label %for.body130.us.us, label %stmt.for.body130.us.us
41 stmt.for.body130.us.us: ; preds = %stmt.for.body130.us.us, %for.end106
42 %_p_splat.us = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <8 x i32> zeroinitializer
43 store <8 x i8> %_p_splat.us, <8 x i8>* undef, align 1
44 br label %stmt.for.body130.us.us
46 for.body130.us.us: ; preds = %for.body130.us.us, %for.end106
47 br label %for.body130.us.us
50 declare <1 x i16> @llvm.aarch64.neon.vuqrshrn.v1i16(<1 x i32>, i32)
52 define <8 x i16> @test_splat(i32 %l) nounwind {
53 ; CHECK-LABEL: test_splat:
55 %lhs = insertelement <1 x i32> undef, i32 %l, i32 0
56 %shift = tail call <1 x i16> @llvm.aarch64.neon.vuqrshrn.v1i16(<1 x i32> %lhs, i32 11)
57 %vec = shufflevector <1 x i16> %shift, <1 x i16> undef, <8 x i32> zeroinitializer
62 define <8 x i16> @test_notsplat(<8 x i16> %a, <8 x i16> %b, i32 %l) nounwind {
63 ; CHECK-LABEL: test_notsplat:
66 %lhs = insertelement <1 x i32> undef, i32 %l, i32 0
67 %shift = tail call <1 x i16> @llvm.aarch64.neon.vuqrshrn.v1i16(<1 x i32> %lhs, i32 11)
68 %vec = shufflevector <1 x i16> %shift, <1 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 0, i32 0, i32 0>