1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -mcpu=cyclone | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
3 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
4 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
9 define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
10 ; CHECK-LABEL: test_csel:
12 %tst1 = icmp ugt i32 %lhs32, %rhs32
13 %val1 = select i1 %tst1, i32 42, i32 52
14 store i32 %val1, i32* @var32
15 ; CHECK-DAG: movz [[W52:w[0-9]+]], #{{52|0x34}}
16 ; CHECK-DAG: movz [[W42:w[0-9]+]], #{{42|0x2a}}
17 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi
19 %rhs64 = sext i32 %rhs32 to i64
20 %tst2 = icmp sle i64 %lhs64, %rhs64
21 %val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64
22 store i64 %val2, i64* @var64
23 ; CHECK: sxtw [[EXT_RHS:x[0-9]+]], {{[wx]}}[[RHS:[0-9]+]]
24 ; CHECK: cmp [[LHS:x[0-9]+]], w[[RHS]], sxtw
25 ; CHECK: csel {{x[0-9]+}}, [[LHS]], [[EXT_RHS]], le
31 define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
32 ; CHECK-LABEL: test_floatcsel:
34 %tst1 = fcmp one float %lhs32, %rhs32
35 ; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
36 ; CHECK-NOFP-NOT: fcmp
37 %val1 = select i1 %tst1, i32 42, i32 52
38 store i32 %val1, i32* @var32
39 ; CHECK: movz [[W52:w[0-9]+]], #{{52|0x34}}
40 ; CHECK: movz [[W42:w[0-9]+]], #{{42|0x2a}}
41 ; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi
42 ; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt
45 %tst2 = fcmp ueq double %lhs64, %rhs64
46 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
47 ; CHECK-NOFP-NOT: fcmp
48 %val2 = select i1 %tst2, i64 9, i64 15
49 store i64 %val2, i64* @var64
50 ; CHECK-AARCH64: movz x[[CONST15:[0-9]+]], #15
51 ; CHECK-ARM64: orr w[[CONST15:[0-9]+]], wzr, #0xf
52 ; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}}
53 ; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq
54 ; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs
61 define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
62 ; CHECK-LABEL: test_csinc:
64 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
65 %tst1 = icmp ugt i32 %lhs32, %rhs32
66 %inc1 = add i32 %rhs32, 1
67 %val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
68 store volatile i32 %val1, i32* @var32
69 ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
70 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls
72 %rhs2 = add i32 %rhs32, 42
73 %tst2 = icmp sle i32 %lhs32, %rhs2
74 %inc2 = add i32 %rhs32, 1
75 %val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
76 store volatile i32 %val2, i32* @var32
77 ; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
78 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
80 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
81 %rhs3 = sext i32 %rhs32 to i64
82 %tst3 = icmp ugt i64 %lhs64, %rhs3
83 %inc3 = add i64 %rhs3, 1
84 %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
85 store volatile i64 %val3, i64* @var64
86 ; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
87 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
89 %rhs4 = zext i32 %rhs32 to i64
90 %tst4 = icmp sle i64 %lhs64, %rhs4
91 %inc4 = add i64 %rhs4, 1
92 %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
93 store volatile i64 %val4, i64* @var64
94 ; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
95 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
101 define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
102 ; CHECK-LABEL: test_csinv:
104 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
105 %tst1 = icmp ugt i32 %lhs32, %rhs32
106 %inc1 = xor i32 -1, %rhs32
107 %val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
108 store volatile i32 %val1, i32* @var32
109 ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
110 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
112 %rhs2 = add i32 %rhs32, 42
113 %tst2 = icmp sle i32 %lhs32, %rhs2
114 %inc2 = xor i32 -1, %rhs32
115 %val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
116 store volatile i32 %val2, i32* @var32
117 ; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
118 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
120 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
121 %rhs3 = sext i32 %rhs32 to i64
122 %tst3 = icmp ugt i64 %lhs64, %rhs3
123 %inc3 = xor i64 -1, %rhs3
124 %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
125 store volatile i64 %val3, i64* @var64
126 ; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
127 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
129 %rhs4 = zext i32 %rhs32 to i64
130 %tst4 = icmp sle i64 %lhs64, %rhs4
131 %inc4 = xor i64 -1, %rhs4
132 %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
133 store volatile i64 %val4, i64* @var64
134 ; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
135 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
141 define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
142 ; CHECK-LABEL: test_csneg:
144 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
145 %tst1 = icmp ugt i32 %lhs32, %rhs32
146 %inc1 = sub i32 0, %rhs32
147 %val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
148 store volatile i32 %val1, i32* @var32
149 ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
150 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], [[RHS]], ls
152 %rhs2 = add i32 %rhs32, 42
153 %tst2 = icmp sle i32 %lhs32, %rhs2
154 %inc2 = sub i32 0, %rhs32
155 %val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
156 store volatile i32 %val2, i32* @var32
157 ; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
158 ; CHECK: csneg {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
160 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
161 %rhs3 = sext i32 %rhs32 to i64
162 %tst3 = icmp ugt i64 %lhs64, %rhs3
163 %inc3 = sub i64 0, %rhs3
164 %val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
165 store volatile i64 %val3, i64* @var64
166 ; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
167 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
169 %rhs4 = zext i32 %rhs32 to i64
170 %tst4 = icmp sle i64 %lhs64, %rhs4
171 %inc4 = sub i64 0, %rhs4
172 %val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
173 store volatile i64 %val4, i64* @var64
174 ; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
175 ; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
181 define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
182 ; CHECK-LABEL: test_cset:
184 ; N.b. code is not optimal here (32-bit csinc would be better) but
185 ; incoming DAG is too complex
186 %tst1 = icmp eq i32 %lhs, %rhs
187 %val1 = zext i1 %tst1 to i32
188 store i32 %val1, i32* @var32
189 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
190 ; CHECK: cset {{w[0-9]+}}, eq
192 %rhs64 = sext i32 %rhs to i64
193 %tst2 = icmp ule i64 %lhs64, %rhs64
194 %val2 = zext i1 %tst2 to i64
195 store i64 %val2, i64* @var64
196 ; CHECK: cset {{w[0-9]+}}, ls
202 define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
203 ; CHECK-LABEL: test_csetm:
205 %tst1 = icmp eq i32 %lhs, %rhs
206 %val1 = sext i1 %tst1 to i32
207 store i32 %val1, i32* @var32
208 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
209 ; CHECK: csetm {{w[0-9]+}}, eq
211 %rhs64 = sext i32 %rhs to i64
212 %tst2 = icmp ule i64 %lhs64, %rhs64
213 %val2 = sext i1 %tst2 to i64
214 store i64 %val2, i64* @var64
215 ; CHECK: csetm {{x[0-9]+}}, ls