1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
2 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s
4 @var32_0 = global i32 0
5 @var32_1 = global i32 0
6 @var64_0 = global i64 0
7 @var64_1 = global i64 0
9 define void @rorv_i64() {
10 ; CHECK-LABEL: rorv_i64:
11 %val0_tmp = load i64* @var64_0
12 %val1_tmp = load i64* @var64_1
13 %val2_tmp = sub i64 64, %val1_tmp
14 %val3_tmp = shl i64 %val0_tmp, %val2_tmp
15 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
16 %val5_tmp = or i64 %val3_tmp, %val4_tmp
17 ; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
18 store volatile i64 %val5_tmp, i64* @var64_0
22 define void @asrv_i64() {
23 ; CHECK-LABEL: asrv_i64:
24 %val0_tmp = load i64* @var64_0
25 %val1_tmp = load i64* @var64_1
26 %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
27 ; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
28 store volatile i64 %val4_tmp, i64* @var64_1
32 define void @lsrv_i64() {
33 ; CHECK-LABEL: lsrv_i64:
34 %val0_tmp = load i64* @var64_0
35 %val1_tmp = load i64* @var64_1
36 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
37 ; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
38 store volatile i64 %val4_tmp, i64* @var64_0
42 define void @lslv_i64() {
43 ; CHECK-LABEL: lslv_i64:
44 %val0_tmp = load i64* @var64_0
45 %val1_tmp = load i64* @var64_1
46 %val4_tmp = shl i64 %val0_tmp, %val1_tmp
47 ; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
48 store volatile i64 %val4_tmp, i64* @var64_1
52 define void @udiv_i64() {
53 ; CHECK-LABEL: udiv_i64:
54 %val0_tmp = load i64* @var64_0
55 %val1_tmp = load i64* @var64_1
56 %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
57 ; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
58 store volatile i64 %val4_tmp, i64* @var64_0
62 define void @sdiv_i64() {
63 ; CHECK-LABEL: sdiv_i64:
64 %val0_tmp = load i64* @var64_0
65 %val1_tmp = load i64* @var64_1
66 %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
67 ; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
68 store volatile i64 %val4_tmp, i64* @var64_1
73 define void @lsrv_i32() {
74 ; CHECK-LABEL: lsrv_i32:
75 %val0_tmp = load i32* @var32_0
76 %val1_tmp = load i32* @var32_1
77 %val2_tmp = add i32 1, %val1_tmp
78 %val4_tmp = lshr i32 %val0_tmp, %val2_tmp
79 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
80 store volatile i32 %val4_tmp, i32* @var32_0
84 define void @lslv_i32() {
85 ; CHECK-LABEL: lslv_i32:
86 %val0_tmp = load i32* @var32_0
87 %val1_tmp = load i32* @var32_1
88 %val2_tmp = add i32 1, %val1_tmp
89 %val4_tmp = shl i32 %val0_tmp, %val2_tmp
90 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
91 store volatile i32 %val4_tmp, i32* @var32_1
95 define void @rorv_i32() {
96 ; CHECK-LABEL: rorv_i32:
97 %val0_tmp = load i32* @var32_0
98 %val6_tmp = load i32* @var32_1
99 %val1_tmp = add i32 1, %val6_tmp
100 %val2_tmp = sub i32 32, %val1_tmp
101 %val3_tmp = shl i32 %val0_tmp, %val2_tmp
102 %val4_tmp = lshr i32 %val0_tmp, %val1_tmp
103 %val5_tmp = or i32 %val3_tmp, %val4_tmp
104 ; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
105 store volatile i32 %val5_tmp, i32* @var32_0
109 define void @asrv_i32() {
110 ; CHECK-LABEL: asrv_i32:
111 %val0_tmp = load i32* @var32_0
112 %val1_tmp = load i32* @var32_1
113 %val2_tmp = add i32 1, %val1_tmp
114 %val4_tmp = ashr i32 %val0_tmp, %val2_tmp
115 ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
116 store volatile i32 %val4_tmp, i32* @var32_1
120 define void @sdiv_i32() {
121 ; CHECK-LABEL: sdiv_i32:
122 %val0_tmp = load i32* @var32_0
123 %val1_tmp = load i32* @var32_1
124 %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
125 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
126 store volatile i32 %val4_tmp, i32* @var32_1
130 define void @udiv_i32() {
131 ; CHECK-LABEL: udiv_i32:
132 %val0_tmp = load i32* @var32_0
133 %val1_tmp = load i32* @var32_1
134 %val4_tmp = udiv i32 %val0_tmp, %val1_tmp
135 ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
136 store volatile i32 %val4_tmp, i32* @var32_0
140 ; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
141 ; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
142 define i32 @test_lsl32() {
143 ; CHECK-LABEL: test_lsl32:
145 %val = load i32* @var32_0
146 %ret = shl i32 1, %val
147 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
152 define i32 @test_lsr32() {
153 ; CHECK-LABEL: test_lsr32:
155 %val = load i32* @var32_0
156 %ret = lshr i32 1, %val
157 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
162 define i32 @test_asr32(i32 %in) {
163 ; CHECK-LABEL: test_asr32:
165 %val = load i32* @var32_0
166 %ret = ashr i32 %in, %val
167 ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}