1 ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
2 ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
4 ; Load / Store Base Register only
5 define zeroext i1 @load_breg_i1(i1* %a) {
6 ; CHECK-LABEL: load_breg_i1
7 ; CHECK: ldrb {{w[0-9]+}}, [x0]
12 define zeroext i8 @load_breg_i8(i8* %a) {
13 ; CHECK-LABEL: load_breg_i8
14 ; CHECK: ldrb {{w[0-9]+}}, [x0]
19 define zeroext i16 @load_breg_i16(i16* %a) {
20 ; CHECK-LABEL: load_breg_i16
21 ; CHECK: ldrh {{w[0-9]+}}, [x0]
26 define i32 @load_breg_i32(i32* %a) {
27 ; CHECK-LABEL: load_breg_i32
28 ; CHECK: ldr {{w[0-9]+}}, [x0]
33 define i64 @load_breg_i64(i64* %a) {
34 ; CHECK-LABEL: load_breg_i64
35 ; CHECK: ldr {{x[0-9]+}}, [x0]
40 define float @load_breg_f32(float* %a) {
41 ; CHECK-LABEL: load_breg_f32
42 ; CHECK: ldr {{s[0-9]+}}, [x0]
47 define double @load_breg_f64(double* %a) {
48 ; CHECK-LABEL: load_breg_f64
49 ; CHECK: ldr {{d[0-9]+}}, [x0]
54 define void @store_breg_i1(i1* %a) {
55 ; CHECK-LABEL: store_breg_i1
56 ; CHECK: strb wzr, [x0]
61 define void @store_breg_i1_2(i1* %a) {
62 ; CHECK-LABEL: store_breg_i1_2
63 ; CHECK: strb {{w[0-9]+}}, [x0]
68 define void @store_breg_i8(i8* %a) {
69 ; CHECK-LABEL: store_breg_i8
70 ; CHECK: strb wzr, [x0]
75 define void @store_breg_i16(i16* %a) {
76 ; CHECK-LABEL: store_breg_i16
77 ; CHECK: strh wzr, [x0]
82 define void @store_breg_i32(i32* %a) {
83 ; CHECK-LABEL: store_breg_i32
84 ; CHECK: str wzr, [x0]
89 define void @store_breg_i64(i64* %a) {
90 ; CHECK-LABEL: store_breg_i64
91 ; CHECK: str xzr, [x0]
96 define void @store_breg_f32(float* %a) {
97 ; CHECK-LABEL: store_breg_f32
98 ; CHECK: str wzr, [x0]
99 store float 0.0, float* %a
103 define void @store_breg_f64(double* %a) {
104 ; CHECK-LABEL: store_breg_f64
105 ; CHECK: str xzr, [x0]
106 store double 0.0, double* %a
111 define i32 @load_immoff_1() {
112 ; CHECK-LABEL: load_immoff_1
113 ; CHECK: orr {{w|x}}[[REG:[0-9]+]], {{wzr|xzr}}, #0x80
114 ; CHECK: ldr {{w[0-9]+}}, {{\[}}x[[REG]]{{\]}}
115 %1 = inttoptr i64 128 to i32*
120 ; Load / Store Base Register + Immediate Offset
121 ; Max supported negative offset
122 define i32 @load_breg_immoff_1(i64 %a) {
123 ; CHECK-LABEL: load_breg_immoff_1
124 ; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
125 %1 = add i64 %a, -256
126 %2 = inttoptr i64 %1 to i32*
131 ; Min not-supported negative offset
132 define i32 @load_breg_immoff_2(i64 %a) {
133 ; SDAG-LABEL: load_breg_immoff_2
134 ; SDAG: sub [[REG:x[0-9]+]], x0, #257
135 ; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
136 ; FAST-LABEL: load_breg_immoff_2
137 ; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
138 ; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
139 %1 = add i64 %a, -257
140 %2 = inttoptr i64 %1 to i32*
145 ; Max supported unscaled offset
146 define i32 @load_breg_immoff_3(i64 %a) {
147 ; CHECK-LABEL: load_breg_immoff_3
148 ; CHECK: ldur {{w[0-9]+}}, [x0, #255]
150 %2 = inttoptr i64 %1 to i32*
155 ; Min un-supported unscaled offset
156 define i32 @load_breg_immoff_4(i64 %a) {
157 ; SDAG-LABEL: load_breg_immoff_4
158 ; SDAG: add [[REG:x[0-9]+]], x0, #257
159 ; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
160 ; FAST-LABEL: load_breg_immoff_4
161 ; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
162 ; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
164 %2 = inttoptr i64 %1 to i32*
169 ; Max supported scaled offset
170 define i32 @load_breg_immoff_5(i64 %a) {
171 ; CHECK-LABEL: load_breg_immoff_5
172 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
173 %1 = add i64 %a, 16380
174 %2 = inttoptr i64 %1 to i32*
179 ; Min un-supported scaled offset
180 define i32 @load_breg_immoff_6(i64 %a) {
181 ; SDAG-LABEL: load_breg_immoff_6
182 ; SDAG: add [[REG:x[0-9]+]], x0, #4, lsl #12
183 ; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
184 ; FAST-LABEL: load_breg_immoff_6
185 ; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
186 ; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
187 %1 = add i64 %a, 16384
188 %2 = inttoptr i64 %1 to i32*
193 ; Max supported negative offset
194 define void @store_breg_immoff_1(i64 %a) {
195 ; CHECK-LABEL: store_breg_immoff_1
196 ; CHECK: stur wzr, [x0, #-256]
197 %1 = add i64 %a, -256
198 %2 = inttoptr i64 %1 to i32*
203 ; Min not-supported negative offset
204 define void @store_breg_immoff_2(i64 %a) {
205 ; SDAG-LABEL: store_breg_immoff_2
206 ; SDAG: sub [[REG:x[0-9]+]], x0, #257
207 ; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
208 ; FAST-LABEL: store_breg_immoff_2
209 ; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
210 ; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
211 %1 = add i64 %a, -257
212 %2 = inttoptr i64 %1 to i32*
217 ; Max supported unscaled offset
218 define void @store_breg_immoff_3(i64 %a) {
219 ; CHECK-LABEL: store_breg_immoff_3
220 ; CHECK: stur wzr, [x0, #255]
222 %2 = inttoptr i64 %1 to i32*
227 ; Min un-supported unscaled offset
228 define void @store_breg_immoff_4(i64 %a) {
229 ; SDAG-LABEL: store_breg_immoff_4
230 ; SDAG: add [[REG:x[0-9]+]], x0, #257
231 ; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
232 ; FAST-LABEL: store_breg_immoff_4
233 ; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
234 ; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
236 %2 = inttoptr i64 %1 to i32*
241 ; Max supported scaled offset
242 define void @store_breg_immoff_5(i64 %a) {
243 ; CHECK-LABEL: store_breg_immoff_5
244 ; CHECK: str wzr, [x0, #16380]
245 %1 = add i64 %a, 16380
246 %2 = inttoptr i64 %1 to i32*
251 ; Min un-supported scaled offset
252 define void @store_breg_immoff_6(i64 %a) {
253 ; SDAG-LABEL: store_breg_immoff_6
254 ; SDAG: add [[REG:x[0-9]+]], x0, #4, lsl #12
255 ; SDAG-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
256 ; FAST-LABEL: store_breg_immoff_6
257 ; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
258 ; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
259 %1 = add i64 %a, 16384
260 %2 = inttoptr i64 %1 to i32*
265 define i64 @load_breg_immoff_7(i64 %a) {
266 ; CHECK-LABEL: load_breg_immoff_7
267 ; CHECK: ldr {{x[0-9]+}}, [x0, #48]
269 %2 = inttoptr i64 %1 to i64*
275 define i64 @load_breg_immoff_8(i64 %a) {
276 ; CHECK-LABEL: load_breg_immoff_8
277 ; CHECK: ldr {{x[0-9]+}}, [x0, #48]
279 %2 = inttoptr i64 %1 to i64*
284 ; Load Base Register + Register Offset
285 define i64 @load_breg_offreg_1(i64 %a, i64 %b) {
286 ; CHECK-LABEL: load_breg_offreg_1
287 ; CHECK: ldr {{x[0-9]+}}, [x0, x1]
289 %2 = inttoptr i64 %1 to i64*
295 define i64 @load_breg_offreg_2(i64 %a, i64 %b) {
296 ; CHECK-LABEL: load_breg_offreg_2
297 ; CHECK: ldr {{x[0-9]+}}, [x1, x0]
299 %2 = inttoptr i64 %1 to i64*
304 ; Load Base Register + Register Offset + Immediate Offset
305 define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
306 ; CHECK-LABEL: load_breg_offreg_immoff_1
307 ; CHECK: add [[REG:x[0-9]+]], x0, x1
308 ; CHECK-NEXT: ldr x0, {{\[}}[[REG]], #48{{\]}}
311 %3 = inttoptr i64 %2 to i64*
316 define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
317 ; SDAG-LABEL: load_breg_offreg_immoff_2
318 ; SDAG: add [[REG1:x[0-9]+]], x0, x1
319 ; SDAG-NEXT: add [[REG2:x[0-9]+]], [[REG1]], #15, lsl #12
320 ; SDAG-NEXT: ldr x0, {{\[}}[[REG2]]{{\]}}
321 ; FAST-LABEL: load_breg_offreg_immoff_2
322 ; FAST: add [[REG:x[0-9]+]], x0, {{x[0-9]+}}
323 ; FAST-NEXT: ldr x0, {{\[}}[[REG]], x1{{\]}}
325 %2 = add i64 %1, 61440
326 %3 = inttoptr i64 %2 to i64*
331 ; Load Scaled Register Offset
332 define i32 @load_shift_offreg_1(i64 %a) {
333 ; CHECK-LABEL: load_shift_offreg_1
334 ; CHECK: lsl [[REG:x[0-9]+]], x0, #2
335 ; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
337 %2 = inttoptr i64 %1 to i32*
342 define i32 @load_mul_offreg_1(i64 %a) {
343 ; CHECK-LABEL: load_mul_offreg_1
344 ; CHECK: lsl [[REG:x[0-9]+]], x0, #2
345 ; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
347 %2 = inttoptr i64 %1 to i32*
352 ; Load Base Register + Scaled Register Offset
353 define i32 @load_breg_shift_offreg_1(i64 %a, i64 %b) {
354 ; CHECK-LABEL: load_breg_shift_offreg_1
355 ; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
358 %3 = inttoptr i64 %2 to i32*
363 define i32 @load_breg_shift_offreg_2(i64 %a, i64 %b) {
364 ; CHECK-LABEL: load_breg_shift_offreg_2
365 ; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
368 %3 = inttoptr i64 %2 to i32*
373 define i32 @load_breg_shift_offreg_3(i64 %a, i64 %b) {
374 ; SDAG-LABEL: load_breg_shift_offreg_3
375 ; SDAG: lsl [[REG:x[0-9]+]], x0, #2
376 ; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
377 ; FAST-LABEL: load_breg_shift_offreg_3
378 ; FAST: lsl [[REG:x[0-9]+]], x1, #2
379 ; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
383 %4 = inttoptr i64 %3 to i32*
388 define i32 @load_breg_shift_offreg_4(i64 %a, i64 %b) {
389 ; SDAG-LABEL: load_breg_shift_offreg_4
390 ; SDAG: lsl [[REG:x[0-9]+]], x1, #2
391 ; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
392 ; FAST-LABEL: load_breg_shift_offreg_4
393 ; FAST: lsl [[REG:x[0-9]+]], x0, #2
394 ; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
398 %4 = inttoptr i64 %3 to i32*
403 define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) {
404 ; SDAG-LABEL: load_breg_shift_offreg_5
405 ; SDAG: lsl [[REG:x[0-9]+]], x1, #3
406 ; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
407 ; FAST-LABEL: load_breg_shift_offreg_5
408 ; FAST: lsl [[REG:x[0-9]+]], x1, #3
409 ; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
413 %4 = inttoptr i64 %3 to i32*
418 define i32 @load_breg_mul_offreg_1(i64 %a, i64 %b) {
419 ; CHECK-LABEL: load_breg_mul_offreg_1
420 ; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
423 %3 = inttoptr i64 %2 to i32*
428 define zeroext i8 @load_breg_and_offreg_1(i64 %a, i64 %b) {
429 ; CHECK-LABEL: load_breg_and_offreg_1
430 ; CHECK: ldrb {{w[0-9]+}}, [x1, w0, uxtw]
431 %1 = and i64 %a, 4294967295
433 %3 = inttoptr i64 %2 to i8*
438 define zeroext i16 @load_breg_and_offreg_2(i64 %a, i64 %b) {
439 ; CHECK-LABEL: load_breg_and_offreg_2
440 ; CHECK: ldrh {{w[0-9]+}}, [x1, w0, uxtw #1]
441 %1 = and i64 %a, 4294967295
444 %4 = inttoptr i64 %3 to i16*
449 define i32 @load_breg_and_offreg_3(i64 %a, i64 %b) {
450 ; CHECK-LABEL: load_breg_and_offreg_3
451 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
452 %1 = and i64 %a, 4294967295
455 %4 = inttoptr i64 %3 to i32*
460 define i64 @load_breg_and_offreg_4(i64 %a, i64 %b) {
461 ; CHECK-LABEL: load_breg_and_offreg_4
462 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
463 %1 = and i64 %a, 4294967295
466 %4 = inttoptr i64 %3 to i64*
471 ; Load Base Register + Scaled Register Offset + Sign/Zero extension
472 define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) {
473 ; CHECK-LABEL: load_breg_zext_shift_offreg_1
474 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
475 %1 = zext i32 %a to i64
478 %4 = inttoptr i64 %3 to i32*
483 define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) {
484 ; CHECK-LABEL: load_breg_zext_shift_offreg_2
485 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
486 %1 = zext i32 %a to i64
489 %4 = inttoptr i64 %3 to i32*
494 define i32 @load_breg_zext_mul_offreg_1(i32 %a, i64 %b) {
495 ; CHECK-LABEL: load_breg_zext_mul_offreg_1
496 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
497 %1 = zext i32 %a to i64
500 %4 = inttoptr i64 %3 to i32*
505 define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) {
506 ; CHECK-LABEL: load_breg_sext_shift_offreg_1
507 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
508 %1 = sext i32 %a to i64
511 %4 = inttoptr i64 %3 to i32*
516 define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) {
517 ; CHECK-LABEL: load_breg_sext_shift_offreg_2
518 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
519 %1 = sext i32 %a to i64
522 %4 = inttoptr i64 %3 to i32*
527 define i32 @load_breg_sext_mul_offreg_1(i32 %a, i64 %b) {
528 ; CHECK-LABEL: load_breg_sext_mul_offreg_1
529 ; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
530 %1 = sext i32 %a to i64
533 %4 = inttoptr i64 %3 to i32*
538 ; Load Scaled Register Offset + Immediate Offset + Sign/Zero extension
539 define i64 @load_sext_shift_offreg_imm1(i32 %a) {
540 ; CHECK-LABEL: load_sext_shift_offreg_imm1
541 ; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
542 ; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
543 %1 = sext i32 %a to i64
546 %4 = inttoptr i64 %3 to i64*
551 ; Load Base Register + Scaled Register Offset + Immediate Offset + Sign/Zero extension
552 define i64 @load_breg_sext_shift_offreg_imm1(i32 %a, i64 %b) {
553 ; CHECK-LABEL: load_breg_sext_shift_offreg_imm1
554 ; CHECK: add [[REG:x[0-9]+]], x1, w0, sxtw #3
555 ; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
556 %1 = sext i32 %a to i64
560 %5 = inttoptr i64 %4 to i64*
565 ; Test that the kill flag is not set - the machine instruction verifier does that for us.
566 define i64 @kill_reg(i64 %a) {
569 %3 = inttoptr i64 %2 to i64*