1 ; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
4 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xff
5 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
6 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xff
7 define zeroext i8 @lslv_i8(i8 %a, i8 %b) {
13 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
14 define zeroext i8 @lsl_i8(i8 %a) {
19 ; CHECK-LABEL: lsl_zext_i8_i16
20 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
21 define zeroext i16 @lsl_zext_i8_i16(i8 %b) {
22 %1 = zext i8 %b to i16
27 ; CHECK-LABEL: lsl_sext_i8_i16
28 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
29 define signext i16 @lsl_sext_i8_i16(i8 %b) {
30 %1 = sext i8 %b to i16
35 ; CHECK-LABEL: lsl_zext_i8_i32
36 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
37 define i32 @lsl_zext_i8_i32(i8 %b) {
38 %1 = zext i8 %b to i32
43 ; CHECK-LABEL: lsl_sext_i8_i32
44 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
45 define i32 @lsl_sext_i8_i32(i8 %b) {
46 %1 = sext i8 %b to i32
51 ; CHECK-LABEL: lsl_zext_i8_i64
52 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
53 define i64 @lsl_zext_i8_i64(i8 %b) {
54 %1 = zext i8 %b to i64
59 ; CHECK-LABEL: lsl_sext_i8_i64
60 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
61 define i64 @lsl_sext_i8_i64(i8 %b) {
62 %1 = sext i8 %b to i64
67 ; CHECK-LABEL: lslv_i16
68 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xffff
69 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
70 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xffff
71 define zeroext i16 @lslv_i16(i16 %a, i16 %b) {
76 ; CHECK-LABEL: lsl_i16
77 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
78 define zeroext i16 @lsl_i16(i16 %a) {
83 ; CHECK-LABEL: lsl_zext_i16_i32
84 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
85 define i32 @lsl_zext_i16_i32(i16 %b) {
86 %1 = zext i16 %b to i32
91 ; CHECK-LABEL: lsl_sext_i16_i32
92 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
93 define i32 @lsl_sext_i16_i32(i16 %b) {
94 %1 = sext i16 %b to i32
99 ; CHECK-LABEL: lsl_zext_i16_i64
100 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
101 define i64 @lsl_zext_i16_i64(i16 %b) {
102 %1 = zext i16 %b to i64
107 ; CHECK-LABEL: lsl_sext_i16_i64
108 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
109 define i64 @lsl_sext_i16_i64(i16 %b) {
110 %1 = sext i16 %b to i64
115 ; CHECK-LABEL: lslv_i32
116 ; CHECK: lsl {{w[0-9]*}}, w0, w1
117 define zeroext i32 @lslv_i32(i32 %a, i32 %b) {
122 ; CHECK-LABEL: lsl_i32
123 ; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
124 define zeroext i32 @lsl_i32(i32 %a) {
129 ; CHECK-LABEL: lsl_zext_i32_i64
130 ; CHECK: ubfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
131 define i64 @lsl_zext_i32_i64(i32 %b) {
132 %1 = zext i32 %b to i64
137 ; CHECK-LABEL: lsl_sext_i32_i64
138 ; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
139 define i64 @lsl_sext_i32_i64(i32 %b) {
140 %1 = sext i32 %b to i64
145 ; CHECK-LABEL: lslv_i64
146 ; CHECK: lsl {{x[0-9]*}}, x0, x1
147 define i64 @lslv_i64(i64 %a, i64 %b) {
152 ; CHECK-LABEL: lsl_i64
153 ; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, #32
154 define i64 @lsl_i64(i64 %a) {
159 ; CHECK-LABEL: lsrv_i8
160 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xff
161 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
162 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
163 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
164 define zeroext i8 @lsrv_i8(i8 %a, i8 %b) {
169 ; CHECK-LABEL: lsr_i8
170 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
171 define zeroext i8 @lsr_i8(i8 %a) {
176 ; CHECK-LABEL: lsr_zext_i8_i16
177 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
178 define zeroext i16 @lsr_zext_i8_i16(i8 %b) {
179 %1 = zext i8 %b to i16
184 ; CHECK-LABEL: lsr_sext_i8_i16
185 ; CHECK: sxtb [[REG:w[0-9]+]], w0
186 ; CHECK-NEXT: ubfx {{w[0-9]*}}, [[REG]], #4, #12
187 define signext i16 @lsr_sext_i8_i16(i8 %b) {
188 %1 = sext i8 %b to i16
193 ; CHECK-LABEL: lsr_zext_i8_i32
194 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
195 define i32 @lsr_zext_i8_i32(i8 %b) {
196 %1 = zext i8 %b to i32
201 ; CHECK-LABEL: lsr_sext_i8_i32
202 ; CHECK: sxtb [[REG:w[0-9]+]], w0
203 ; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG]], #4
204 define i32 @lsr_sext_i8_i32(i8 %b) {
205 %1 = sext i8 %b to i32
210 ; CHECK-LABEL: lsrv_i16
211 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xffff
212 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
213 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
214 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
215 define zeroext i16 @lsrv_i16(i16 %a, i16 %b) {
220 ; CHECK-LABEL: lsr_i16
221 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
222 define zeroext i16 @lsr_i16(i16 %a) {
227 ; CHECK-LABEL: lsrv_i32
228 ; CHECK: lsr {{w[0-9]*}}, w0, w1
229 define zeroext i32 @lsrv_i32(i32 %a, i32 %b) {
234 ; CHECK-LABEL: lsr_i32
235 ; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
236 define zeroext i32 @lsr_i32(i32 %a) {
241 ; CHECK-LABEL: lsrv_i64
242 ; CHECK: lsr {{x[0-9]*}}, x0, x1
243 define i64 @lsrv_i64(i64 %a, i64 %b) {
248 ; CHECK-LABEL: lsr_i64
249 ; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, #32
250 define i64 @lsr_i64(i64 %a) {
255 ; CHECK-LABEL: asrv_i8
256 ; CHECK: sxtb [[REG1:w[0-9]+]], w0
257 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
258 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
259 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
260 define zeroext i8 @asrv_i8(i8 %a, i8 %b) {
265 ; CHECK-LABEL: asr_i8
266 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
267 define zeroext i8 @asr_i8(i8 %a) {
272 ; CHECK-LABEL: asr_zext_i8_i16
273 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
274 define zeroext i16 @asr_zext_i8_i16(i8 %b) {
275 %1 = zext i8 %b to i16
280 ; CHECK-LABEL: asr_sext_i8_i16
281 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
282 define signext i16 @asr_sext_i8_i16(i8 %b) {
283 %1 = sext i8 %b to i16
288 ; CHECK-LABEL: asr_zext_i8_i32
289 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
290 define i32 @asr_zext_i8_i32(i8 %b) {
291 %1 = zext i8 %b to i32
296 ; CHECK-LABEL: asr_sext_i8_i32
297 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
298 define i32 @asr_sext_i8_i32(i8 %b) {
299 %1 = sext i8 %b to i32
304 ; CHECK-LABEL: asrv_i16
305 ; CHECK: sxth [[REG1:w[0-9]+]], w0
306 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
307 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
308 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
309 define zeroext i16 @asrv_i16(i16 %a, i16 %b) {
314 ; CHECK-LABEL: asr_i16
315 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
316 define zeroext i16 @asr_i16(i16 %a) {
321 ; CHECK-LABEL: asrv_i32
322 ; CHECK: asr {{w[0-9]*}}, w0, w1
323 define zeroext i32 @asrv_i32(i32 %a, i32 %b) {
328 ; CHECK-LABEL: asr_i32
329 ; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
330 define zeroext i32 @asr_i32(i32 %a) {
335 ; CHECK-LABEL: asrv_i64
336 ; CHECK: asr {{x[0-9]*}}, x0, x1
337 define i64 @asrv_i64(i64 %a, i64 %b) {
342 ; CHECK-LABEL: asr_i64
343 ; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, #32
344 define i64 @asr_i64(i64 %a) {
349 ; CHECK-LABEL: shift_test1
350 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
351 ; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
352 define i32 @shift_test1(i8 %a) {
355 %3 = sext i8 %2 to i32