1 ; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
3 ; CHECK-LABEL: lsl_zext_i1_i16
4 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
5 define zeroext i16 @lsl_zext_i1_i16(i1 %b) {
11 ; CHECK-LABEL: lsl_sext_i1_i16
12 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
13 define signext i16 @lsl_sext_i1_i16(i1 %b) {
14 %1 = sext i1 %b to i16
19 ; CHECK-LABEL: lsl_zext_i1_i32
20 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
21 define i32 @lsl_zext_i1_i32(i1 %b) {
22 %1 = zext i1 %b to i32
27 ; CHECK-LABEL: lsl_sext_i1_i32
28 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
29 define i32 @lsl_sext_i1_i32(i1 %b) {
30 %1 = sext i1 %b to i32
35 ; CHECK-LABEL: lsl_zext_i1_i64
36 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
37 define i64 @lsl_zext_i1_i64(i1 %b) {
38 %1 = zext i1 %b to i64
43 ; CHECK-LABEL: lsl_sext_i1_i64
44 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
45 define i64 @lsl_sext_i1_i64(i1 %b) {
46 %1 = sext i1 %b to i64
51 ; CHECK-LABEL: lslv_i8
52 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xff
53 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
54 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xff
55 define zeroext i8 @lslv_i8(i8 %a, i8 %b) {
61 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
62 define zeroext i8 @lsl_i8(i8 %a) {
67 ; CHECK-LABEL: lsl_zext_i8_i16
68 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
69 define zeroext i16 @lsl_zext_i8_i16(i8 %b) {
70 %1 = zext i8 %b to i16
75 ; CHECK-LABEL: lsl_sext_i8_i16
76 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
77 define signext i16 @lsl_sext_i8_i16(i8 %b) {
78 %1 = sext i8 %b to i16
83 ; CHECK-LABEL: lsl_zext_i8_i32
84 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
85 define i32 @lsl_zext_i8_i32(i8 %b) {
86 %1 = zext i8 %b to i32
91 ; CHECK-LABEL: lsl_sext_i8_i32
92 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
93 define i32 @lsl_sext_i8_i32(i8 %b) {
94 %1 = sext i8 %b to i32
99 ; CHECK-LABEL: lsl_zext_i8_i64
100 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
101 define i64 @lsl_zext_i8_i64(i8 %b) {
102 %1 = zext i8 %b to i64
107 ; CHECK-LABEL: lsl_sext_i8_i64
108 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
109 define i64 @lsl_sext_i8_i64(i8 %b) {
110 %1 = sext i8 %b to i64
115 ; CHECK-LABEL: lslv_i16
116 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xffff
117 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
118 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xffff
119 define zeroext i16 @lslv_i16(i16 %a, i16 %b) {
124 ; CHECK-LABEL: lsl_i16
125 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
126 define zeroext i16 @lsl_i16(i16 %a) {
131 ; CHECK-LABEL: lsl_zext_i16_i32
132 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
133 define i32 @lsl_zext_i16_i32(i16 %b) {
134 %1 = zext i16 %b to i32
139 ; CHECK-LABEL: lsl_sext_i16_i32
140 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
141 define i32 @lsl_sext_i16_i32(i16 %b) {
142 %1 = sext i16 %b to i32
147 ; CHECK-LABEL: lsl_zext_i16_i64
148 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
149 define i64 @lsl_zext_i16_i64(i16 %b) {
150 %1 = zext i16 %b to i64
155 ; CHECK-LABEL: lsl_sext_i16_i64
156 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
157 define i64 @lsl_sext_i16_i64(i16 %b) {
158 %1 = sext i16 %b to i64
163 ; CHECK-LABEL: lslv_i32
164 ; CHECK: lsl {{w[0-9]*}}, w0, w1
165 define zeroext i32 @lslv_i32(i32 %a, i32 %b) {
170 ; CHECK-LABEL: lsl_i32
171 ; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
172 define zeroext i32 @lsl_i32(i32 %a) {
177 ; CHECK-LABEL: lsl_zext_i32_i64
178 ; CHECK: ubfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
179 define i64 @lsl_zext_i32_i64(i32 %b) {
180 %1 = zext i32 %b to i64
185 ; CHECK-LABEL: lsl_sext_i32_i64
186 ; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
187 define i64 @lsl_sext_i32_i64(i32 %b) {
188 %1 = sext i32 %b to i64
193 ; CHECK-LABEL: lslv_i64
194 ; CHECK: lsl {{x[0-9]*}}, x0, x1
195 define i64 @lslv_i64(i64 %a, i64 %b) {
200 ; CHECK-LABEL: lsl_i64
201 ; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, #32
202 define i64 @lsl_i64(i64 %a) {
207 ; CHECK-LABEL: lsrv_i8
208 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xff
209 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
210 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
211 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
212 define zeroext i8 @lsrv_i8(i8 %a, i8 %b) {
217 ; CHECK-LABEL: lsr_i8
218 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
219 define zeroext i8 @lsr_i8(i8 %a) {
224 ; CHECK-LABEL: lsr_zext_i8_i16
225 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
226 define zeroext i16 @lsr_zext_i8_i16(i8 %b) {
227 %1 = zext i8 %b to i16
232 ; CHECK-LABEL: lsr_sext_i8_i16
233 ; CHECK: sxtb [[REG:w[0-9]+]], w0
234 ; CHECK-NEXT: ubfx {{w[0-9]*}}, [[REG]], #4, #12
235 define signext i16 @lsr_sext_i8_i16(i8 %b) {
236 %1 = sext i8 %b to i16
241 ; CHECK-LABEL: lsr_zext_i8_i32
242 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
243 define i32 @lsr_zext_i8_i32(i8 %b) {
244 %1 = zext i8 %b to i32
249 ; CHECK-LABEL: lsr_sext_i8_i32
250 ; CHECK: sxtb [[REG:w[0-9]+]], w0
251 ; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG]], #4
252 define i32 @lsr_sext_i8_i32(i8 %b) {
253 %1 = sext i8 %b to i32
258 ; CHECK-LABEL: lsrv_i16
259 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xffff
260 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
261 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
262 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
263 define zeroext i16 @lsrv_i16(i16 %a, i16 %b) {
268 ; CHECK-LABEL: lsr_i16
269 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
270 define zeroext i16 @lsr_i16(i16 %a) {
275 ; CHECK-LABEL: lsrv_i32
276 ; CHECK: lsr {{w[0-9]*}}, w0, w1
277 define zeroext i32 @lsrv_i32(i32 %a, i32 %b) {
282 ; CHECK-LABEL: lsr_i32
283 ; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
284 define zeroext i32 @lsr_i32(i32 %a) {
289 ; CHECK-LABEL: lsrv_i64
290 ; CHECK: lsr {{x[0-9]*}}, x0, x1
291 define i64 @lsrv_i64(i64 %a, i64 %b) {
296 ; CHECK-LABEL: lsr_i64
297 ; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, #32
298 define i64 @lsr_i64(i64 %a) {
303 ; CHECK-LABEL: asrv_i8
304 ; CHECK: sxtb [[REG1:w[0-9]+]], w0
305 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
306 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
307 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
308 define zeroext i8 @asrv_i8(i8 %a, i8 %b) {
313 ; CHECK-LABEL: asr_i8
314 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
315 define zeroext i8 @asr_i8(i8 %a) {
320 ; CHECK-LABEL: asr_zext_i8_i16
321 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
322 define zeroext i16 @asr_zext_i8_i16(i8 %b) {
323 %1 = zext i8 %b to i16
328 ; CHECK-LABEL: asr_sext_i8_i16
329 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
330 define signext i16 @asr_sext_i8_i16(i8 %b) {
331 %1 = sext i8 %b to i16
336 ; CHECK-LABEL: asr_zext_i8_i32
337 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
338 define i32 @asr_zext_i8_i32(i8 %b) {
339 %1 = zext i8 %b to i32
344 ; CHECK-LABEL: asr_sext_i8_i32
345 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
346 define i32 @asr_sext_i8_i32(i8 %b) {
347 %1 = sext i8 %b to i32
352 ; CHECK-LABEL: asrv_i16
353 ; CHECK: sxth [[REG1:w[0-9]+]], w0
354 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
355 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
356 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
357 define zeroext i16 @asrv_i16(i16 %a, i16 %b) {
362 ; CHECK-LABEL: asr_i16
363 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
364 define zeroext i16 @asr_i16(i16 %a) {
369 ; CHECK-LABEL: asrv_i32
370 ; CHECK: asr {{w[0-9]*}}, w0, w1
371 define zeroext i32 @asrv_i32(i32 %a, i32 %b) {
376 ; CHECK-LABEL: asr_i32
377 ; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
378 define zeroext i32 @asr_i32(i32 %a) {
383 ; CHECK-LABEL: asrv_i64
384 ; CHECK: asr {{x[0-9]*}}, x0, x1
385 define i64 @asrv_i64(i64 %a, i64 %b) {
390 ; CHECK-LABEL: asr_i64
391 ; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, #32
392 define i64 @asr_i64(i64 %a) {
397 ; CHECK-LABEL: shift_test1
398 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
399 ; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
400 define i32 @shift_test1(i8 %a) {
403 %3 = sext i8 %2 to i32