2 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM64 %s
3 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
4 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE --check-prefix=CHECK-ARM64-BE %s
5 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64_be-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
7 %myStruct = type { i64 , i8, i32 }
12 @var128 = global i128 0
13 @varfloat = global float 0.0
14 @vardouble = global double 0.0
15 @varstruct = global %myStruct zeroinitializer
17 define void @take_i8s(i8 %val1, i8 %val2) {
18 ; CHECK-LABEL: take_i8s:
19 store i8 %val2, i8* @var8
20 ; Not using w1 may be technically allowed, but it would indicate a
22 ; CHECK: strb w1, [{{x[0-9]+}}, {{#?}}:lo12:var8]
26 define void @add_floats(float %val1, float %val2) {
27 ; CHECK-LABEL: add_floats:
28 %newval = fadd float %val1, %val2
29 ; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
30 ; CHECK-NOFP-NOT: fadd
31 store float %newval, float* @varfloat
32 ; CHECK: str [[ADDRES]], [{{x[0-9]+}}, {{#?}}:lo12:varfloat]
36 ; byval pointers should be allocated to the stack and copied as if
38 define void @take_struct(%myStruct* byval %structval) {
39 ; CHECK-LABEL: take_struct:
40 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
41 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
43 %val0 = load volatile i32* %addr0
44 ; Some weird move means x0 is used for one access
45 ; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12]
46 store volatile i32 %val0, i32* @var32
47 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32]
49 %val1 = load volatile i64* %addr1
50 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
51 store volatile i64 %val1, i64* @var64
52 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
57 ; %structval should be at sp + 16
58 define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
59 ; CHECK-LABEL: check_byval_align:
61 %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
62 %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
64 %val0 = load volatile i32* %addr0
65 ; Some weird move means x0 is used for one access
66 ; CHECK-ARM64: ldr [[REG32:w[0-9]+]], [sp, #28]
67 store i32 %val0, i32* @var32
68 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32]
70 %val1 = load volatile i64* %addr1
71 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
72 store i64 %val1, i64* @var64
73 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
78 define i32 @return_int() {
79 ; CHECK-LABEL: return_int:
80 %val = load i32* @var32
82 ; CHECK: ldr w0, [{{x[0-9]+}}, {{#?}}:lo12:var32]
83 ; Make sure epilogue follows
87 define double @return_double() {
88 ; CHECK-LABEL: return_double:
90 ; CHECK: ldr d0, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI
91 ; CHECK-NOFP-NOT: ldr d0,
94 ; This is the kind of IR clang will produce for returning a struct
95 ; small enough to go into registers. Not all that pretty, but it
97 define [2 x i64] @return_struct() {
98 ; CHECK-LABEL: return_struct:
99 %addr = bitcast %myStruct* @varstruct to [2 x i64]*
100 %val = load [2 x i64]* %addr
102 ; CHECK-DAG: ldr x0, [{{x[0-9]+}}, {{#?}}:lo12:varstruct]
103 ; Odd register regex below disallows x0 which we want to be live now.
104 ; CHECK-DAG: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, {{#?}}:lo12:varstruct
105 ; CHECK: ldr x1, [{{x[1-9][0-9]*}}, #8]
106 ; Make sure epilogue immediately follows
110 ; Large structs are passed by reference (storage allocated by caller
111 ; to preserve value semantics) in x8. Strictly this only applies to
112 ; structs larger than 16 bytes, but C semantics can still be provided
113 ; if LLVM does it to %myStruct too. So this is the simplest check
114 define void @return_large_struct(%myStruct* sret %retval) {
115 ; CHECK-LABEL: return_large_struct:
116 %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
117 %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
118 %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
120 store i64 42, i64* %addr0
121 store i8 2, i8* %addr1
122 store i32 9, i32* %addr2
123 ; CHECK: str {{x[0-9]+}}, [x8]
124 ; CHECK: strb {{w[0-9]+}}, [x8, #8]
125 ; CHECK: str {{w[0-9]+}}, [x8, #12]
130 ; This struct is just too far along to go into registers: (only x7 is
131 ; available, but it needs two). Also make sure that %stacked doesn't
132 ; sneak into x7 behind.
133 define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
134 i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
135 double %notstacked) {
136 ; CHECK-LABEL: struct_on_stack:
137 %addr = getelementptr %myStruct* %struct, i64 0, i32 0
138 %val64 = load volatile i64* %addr
139 store volatile i64 %val64, i64* @var64
140 ; Currently nothing on local stack, so struct should be at sp
141 ; CHECK: ldr [[VAL64:x[0-9]+]], [sp]
142 ; CHECK: str [[VAL64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
144 store volatile double %notstacked, double* @vardouble
146 ; CHECK: str d0, [{{x[0-9]+}}, {{#?}}:lo12:vardouble
147 ; CHECK-NOFP-NOT: str d0,
149 %retval = load volatile i32* %stacked
151 ; CHECK-LE: ldr w0, [sp, #16]
152 ; CHECK-BE-AARCH64: ldr w0, [sp, #20]
155 define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
156 float %var4, float %var5, float %var6, float %var7,
158 ; CHECK-LABEL: stacked_fpu:
159 store float %var8, float* @varfloat
160 ; Beware as above: the offset would be different on big-endian
161 ; machines if the first ldr were changed to use s-registers.
162 ; CHECK-ARM64: ldr {{[ds]}}[[VALFLOAT:[0-9]+]], [sp]
163 ; CHECK-ARM64: str s[[VALFLOAT]], [{{x[0-9]+}}, {{#?}}:lo12:varfloat]
168 ; 128-bit integer types should be passed in xEVEN, xODD rather than
169 ; the reverse. In this case x2 and x3. Nothing should use x1.
170 define i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) {
171 ; CHECK-LABEL: check_i128_regalign
172 store i128 %val1, i128* @var128
173 ; CHECK-DAG: str x2, [{{x[0-9]+}}, {{#?}}:lo12:var128]
174 ; CHECK-DAG: str x3, [{{x[0-9]+}}, #8]
180 define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
181 i32 %val4, i32 %val5, i32 %val6, i32 %val7,
182 i32 %stack1, i128 %stack2) {
183 ; CHECK-LABEL: check_i128_stackalign
184 store i128 %stack2, i128* @var128
185 ; Nothing local on stack in current codegen, so first stack is 16 away
186 ; CHECK-LE: add x[[REG:[0-9]+]], sp, #16
187 ; CHECK-LE: ldr {{x[0-9]+}}, [x[[REG]], #8]
188 ; CHECK-BE-AARCH64: ldr {{x[0-9]+}}, [sp, #24]
190 ; Important point is that we address sp+24 for second dword
192 ; CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
196 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
198 define i32 @test_extern() {
199 ; CHECK-LABEL: test_extern:
200 call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0)
206 ; A sub-i32 stack argument must be loaded on big endian with ldr{h,b}, not just
207 ; implicitly extended to a 32-bit load.
208 define i16 @stacked_i16(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
209 i32 %val4, i32 %val5, i32 %val6, i32 %val7,
211 ; CHECK-LABEL: stacked_i16
212 ; CHECK-ARM64-BE: ldrh