1 ; RUN: llc < %s | FileCheck %s
2 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
3 target triple = "aarch64--linux-gnu"
5 ; This test verifies that we can enable subtarget features via
6 ; the function attributes and generate appropriate code (or,
7 ; in this case, select the instruction at all).
9 ; Function Attrs: nounwind
10 define <16 x i8> @foo(<16 x i8> %data, <16 x i8> %key) #0 {
12 %__p0.addr.i = alloca <16 x i8>, align 16
13 %__p1.addr.i = alloca <16 x i8>, align 16
14 %__ret.i = alloca <16 x i8>, align 16
15 %data.addr = alloca <16 x i8>, align 16
16 %key.addr = alloca <16 x i8>, align 16
17 store <16 x i8> %data, <16 x i8>* %data.addr, align 16
18 store <16 x i8> %key, <16 x i8>* %key.addr, align 16
19 %0 = load <16 x i8>, <16 x i8>* %data.addr, align 16
20 %1 = load <16 x i8>, <16 x i8>* %key.addr, align 16
21 store <16 x i8> %0, <16 x i8>* %__p0.addr.i, align 16
22 store <16 x i8> %1, <16 x i8>* %__p1.addr.i, align 16
23 %2 = load <16 x i8>, <16 x i8>* %__p0.addr.i, align 16
24 %3 = load <16 x i8>, <16 x i8>* %__p1.addr.i, align 16
25 %vaeseq_v.i = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %2, <16 x i8> %3)
26 store <16 x i8> %vaeseq_v.i, <16 x i8>* %__ret.i, align 16
27 %4 = load <16 x i8>, <16 x i8>* %__ret.i, align 16
34 ; Function Attrs: nounwind readnone
35 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>)
37 attributes #0 = { nounwind "target-features"="+neon,+crc,+crypto" }