1 ;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
4 ; CHECK-LABEL: test_inline_constraint_r:
5 %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
6 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
10 define i16 @test_small_reg(i16 %lhs, i16 %rhs) {
11 ; CHECK-LABEL: test_small_reg:
12 %val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs)
13 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
17 define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
18 ; CHECK-LABEL: test_inline_constraint_r_imm:
19 %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12)
20 ; CHECK: movz [[FOUR:x[0-9]+]], #4
21 ; CHECK: movz [[TWELVE:w[0-9]+]], #12
22 ; CHECK: add {{x[0-9]+}}, [[FOUR]], [[TWELVE]], sxtw
26 ; m is permitted to have a base/offset form. We don't do that
28 define i32 @test_inline_constraint_m(i32 *%ptr) {
29 ; CHECK-LABEL: test_inline_constraint_m:
30 %val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr)
31 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
35 @arr = global [8 x i32] zeroinitializer
37 ; Q should *never* have base/offset form even if given the chance.
38 define i32 @test_inline_constraint_Q(i32 *%ptr) {
39 ; CHECK-LABEL: test_inline_constraint_Q:
40 %val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1))
41 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
45 @dump = global fp128 zeroinitializer
47 define void @test_inline_constraint_w(<8 x i8> %vec64, <4 x float> %vec128, half %hlf, float %flt, double %dbl, fp128 %quad) {
48 ; CHECK: test_inline_constraint_w:
49 call <8 x i8> asm sideeffect "add $0.8b, $1.8b, $1.8b", "=w,w"(<8 x i8> %vec64)
50 call <8 x i8> asm sideeffect "fadd $0.4s, $1.4s, $1.4s", "=w,w"(<4 x float> %vec128)
51 ; CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
52 ; CHECK: fadd {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
54 ; Arguably semantically dodgy to output "vN", but it's what GCC does
55 ; so purely for compatibility we want vector registers to be output.
56 call float asm sideeffect "fcvt ${0:s}, ${1:h}", "=w,w"(half undef)
57 call float asm sideeffect "fadd $0.2s, $0.2s, $0.2s", "=w,w"(float %flt)
58 call double asm sideeffect "fadd $0.2d, $0.2d, $0.2d", "=w,w"(double %dbl)
59 call fp128 asm sideeffect "fadd $0.2d, $0.2d, $0.2d", "=w,w"(fp128 %quad)
60 ; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
61 ; CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
62 ; CHECK: fadd {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
63 ; CHECK: fadd {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
67 define void @test_inline_constraint_I() {
68 ; CHECK-LABEL: test_inline_constraint_I:
69 call void asm sideeffect "add x0, x0, $0", "I"(i32 0)
70 call void asm sideeffect "add x0, x0, $0", "I"(i64 4095)
71 ; CHECK: add x0, x0, #0
72 ; CHECK: add x0, x0, #4095
77 ; Skip J because it's useless
79 define void @test_inline_constraint_K() {
80 ; CHECK-LABEL: test_inline_constraint_K:
81 call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa
82 call void asm sideeffect "and w0, w0, $0", "K"(i32 65535)
83 ; CHECK: and w0, w0, #-1431655766
84 ; CHECK: and w0, w0, #65535
89 define void @test_inline_constraint_L() {
90 ; CHECK-LABEL: test_inline_constraint_L:
91 call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa
92 call void asm sideeffect "and x0, x0, $0", "L"(i64 65535)
93 ; CHECK: and x0, x0, #4294967296
94 ; CHECK: and x0, x0, #65535
99 ; Skip M and N because we don't support MOV pseudo-instructions yet.
103 define void @test_inline_constraint_S() {
104 ; CHECK-LABEL: test_inline_constraint_S:
105 call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
106 call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var)
107 call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var)
108 ; CHECK: adrp x0, var
109 ; CHECK: adrp x0, var
110 ; CHECK: add x0, x0, #:lo12:var
114 define i32 @test_inline_constraint_S_label(i1 %in) {
115 ; CHECK-LABEL: test_inline_constraint_S_label:
116 call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
117 ; CHECK: adr x0, .Ltmp{{[0-9]+}}
118 br i1 %in, label %loc, label %loc2
125 define void @test_inline_constraint_Y() {
126 ; CHECK-LABEL: test_inline_constraint_Y:
127 call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0)
128 ; CHECK: fcmp s0, #0.0
132 define void @test_inline_constraint_Z() {
133 ; CHECK-LABEL: test_inline_constraint_Z:
134 call void asm sideeffect "cmp w0, $0", "Z"(i32 0)