1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
3 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-linux-gnu | FileCheck %s
4 ; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
6 @var_8bit = global i8 0
7 @var_16bit = global i16 0
8 @var_32bit = global i32 0
9 @var_64bit = global i64 0
11 @var_float = global float 0.0
12 @var_double = global double 0.0
14 @varptr = global i8* null
16 define void @ldst_8bit() {
17 ; CHECK-LABEL: ldst_8bit:
19 ; No architectural support for loads to 16-bit or 8-bit since we
20 ; promote i8 during lowering.
21 %addr_8bit = load i8** @varptr
23 ; match a sign-extending load 8-bit -> 32-bit
24 %addr_sext32 = getelementptr i8* %addr_8bit, i64 -256
25 %val8_sext32 = load volatile i8* %addr_sext32
26 %val32_signed = sext i8 %val8_sext32 to i32
27 store volatile i32 %val32_signed, i32* @var_32bit
28 ; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
30 ; match a zero-extending load volatile 8-bit -> 32-bit
31 %addr_zext32 = getelementptr i8* %addr_8bit, i64 -12
32 %val8_zext32 = load volatile i8* %addr_zext32
33 %val32_unsigned = zext i8 %val8_zext32 to i32
34 store volatile i32 %val32_unsigned, i32* @var_32bit
35 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12]
37 ; match an any-extending load volatile 8-bit -> 32-bit
38 %addr_anyext = getelementptr i8* %addr_8bit, i64 -1
39 %val8_anyext = load volatile i8* %addr_anyext
40 %newval8 = add i8 %val8_anyext, 1
41 store volatile i8 %newval8, i8* @var_8bit
42 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
44 ; match a sign-extending load volatile 8-bit -> 64-bit
45 %addr_sext64 = getelementptr i8* %addr_8bit, i64 -5
46 %val8_sext64 = load volatile i8* %addr_sext64
47 %val64_signed = sext i8 %val8_sext64 to i64
48 store volatile i64 %val64_signed, i64* @var_64bit
49 ; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
51 ; match a zero-extending load volatile 8-bit -> 64-bit.
52 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
53 ; of x0 so it's identical to load volatileing to 32-bits.
54 %addr_zext64 = getelementptr i8* %addr_8bit, i64 -9
55 %val8_zext64 = load volatile i8* %addr_zext64
56 %val64_unsigned = zext i8 %val8_zext64 to i64
57 store volatile i64 %val64_unsigned, i64* @var_64bit
58 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9]
60 ; truncating store volatile 32-bits to 8-bits
61 %addr_trunc32 = getelementptr i8* %addr_8bit, i64 -256
62 %val32 = load volatile i32* @var_32bit
63 %val8_trunc32 = trunc i32 %val32 to i8
64 store volatile i8 %val8_trunc32, i8* %addr_trunc32
65 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
67 ; truncating store volatile 64-bits to 8-bits
68 %addr_trunc64 = getelementptr i8* %addr_8bit, i64 -1
69 %val64 = load volatile i64* @var_64bit
70 %val8_trunc64 = trunc i64 %val64 to i8
71 store volatile i8 %val8_trunc64, i8* %addr_trunc64
72 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
77 define void @ldst_16bit() {
78 ; CHECK-LABEL: ldst_16bit:
80 ; No architectural support for loads to 16-bit or 16-bit since we
81 ; promote i16 during lowering.
82 %addr_8bit = load i8** @varptr
84 ; match a sign-extending load 16-bit -> 32-bit
85 %addr8_sext32 = getelementptr i8* %addr_8bit, i64 -256
86 %addr_sext32 = bitcast i8* %addr8_sext32 to i16*
87 %val16_sext32 = load volatile i16* %addr_sext32
88 %val32_signed = sext i16 %val16_sext32 to i32
89 store volatile i32 %val32_signed, i32* @var_32bit
90 ; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
92 ; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned.
93 %addr8_zext32 = getelementptr i8* %addr_8bit, i64 15
94 %addr_zext32 = bitcast i8* %addr8_zext32 to i16*
95 %val16_zext32 = load volatile i16* %addr_zext32
96 %val32_unsigned = zext i16 %val16_zext32 to i32
97 store volatile i32 %val32_unsigned, i32* @var_32bit
98 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15]
100 ; match an any-extending load volatile 16-bit -> 32-bit
101 %addr8_anyext = getelementptr i8* %addr_8bit, i64 -1
102 %addr_anyext = bitcast i8* %addr8_anyext to i16*
103 %val16_anyext = load volatile i16* %addr_anyext
104 %newval16 = add i16 %val16_anyext, 1
105 store volatile i16 %newval16, i16* @var_16bit
106 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
108 ; match a sign-extending load volatile 16-bit -> 64-bit
109 %addr8_sext64 = getelementptr i8* %addr_8bit, i64 -5
110 %addr_sext64 = bitcast i8* %addr8_sext64 to i16*
111 %val16_sext64 = load volatile i16* %addr_sext64
112 %val64_signed = sext i16 %val16_sext64 to i64
113 store volatile i64 %val64_signed, i64* @var_64bit
114 ; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
116 ; match a zero-extending load volatile 16-bit -> 64-bit.
117 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
118 ; of x0 so it's identical to load volatileing to 32-bits.
119 %addr8_zext64 = getelementptr i8* %addr_8bit, i64 9
120 %addr_zext64 = bitcast i8* %addr8_zext64 to i16*
121 %val16_zext64 = load volatile i16* %addr_zext64
122 %val64_unsigned = zext i16 %val16_zext64 to i64
123 store volatile i64 %val64_unsigned, i64* @var_64bit
124 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9]
126 ; truncating store volatile 32-bits to 16-bits
127 %addr8_trunc32 = getelementptr i8* %addr_8bit, i64 -256
128 %addr_trunc32 = bitcast i8* %addr8_trunc32 to i16*
129 %val32 = load volatile i32* @var_32bit
130 %val16_trunc32 = trunc i32 %val32 to i16
131 store volatile i16 %val16_trunc32, i16* %addr_trunc32
132 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
134 ; truncating store volatile 64-bits to 16-bits
135 %addr8_trunc64 = getelementptr i8* %addr_8bit, i64 -1
136 %addr_trunc64 = bitcast i8* %addr8_trunc64 to i16*
137 %val64 = load volatile i64* @var_64bit
138 %val16_trunc64 = trunc i64 %val64 to i16
139 store volatile i16 %val16_trunc64, i16* %addr_trunc64
140 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
145 define void @ldst_32bit() {
146 ; CHECK-LABEL: ldst_32bit:
148 %addr_8bit = load i8** @varptr
150 ; Straight 32-bit load/store
151 %addr32_8_noext = getelementptr i8* %addr_8bit, i64 1
152 %addr32_noext = bitcast i8* %addr32_8_noext to i32*
153 %val32_noext = load volatile i32* %addr32_noext
154 store volatile i32 %val32_noext, i32* %addr32_noext
155 ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
156 ; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
158 ; Zero-extension to 64-bits
159 %addr32_8_zext = getelementptr i8* %addr_8bit, i64 -256
160 %addr32_zext = bitcast i8* %addr32_8_zext to i32*
161 %val32_zext = load volatile i32* %addr32_zext
162 %val64_unsigned = zext i32 %val32_zext to i64
163 store volatile i64 %val64_unsigned, i64* @var_64bit
164 ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
165 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
167 ; Sign-extension to 64-bits
168 %addr32_8_sext = getelementptr i8* %addr_8bit, i64 -12
169 %addr32_sext = bitcast i8* %addr32_8_sext to i32*
170 %val32_sext = load volatile i32* %addr32_sext
171 %val64_signed = sext i32 %val32_sext to i64
172 store volatile i64 %val64_signed, i64* @var_64bit
173 ; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12]
174 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
176 ; Truncation from 64-bits
177 %addr64_8_trunc = getelementptr i8* %addr_8bit, i64 255
178 %addr64_trunc = bitcast i8* %addr64_8_trunc to i64*
179 %addr32_8_trunc = getelementptr i8* %addr_8bit, i64 -20
180 %addr32_trunc = bitcast i8* %addr32_8_trunc to i32*
182 %val64_trunc = load volatile i64* %addr64_trunc
183 %val32_trunc = trunc i64 %val64_trunc to i32
184 store volatile i32 %val32_trunc, i32* %addr32_trunc
185 ; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255]
186 ; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #-20]
191 define void @ldst_float() {
192 ; CHECK-LABEL: ldst_float:
194 %addr_8bit = load i8** @varptr
195 %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
196 %addrfp = bitcast i8* %addrfp_8 to float*
198 %valfp = load volatile float* %addrfp
199 ; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]
200 ; CHECK-NOFP-NOT: ldur {{s[0-9]+}},
202 store volatile float %valfp, float* %addrfp
203 ; CHECK: stur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]
204 ; CHECK-NOFP-NOT: stur {{s[0-9]+}},
209 define void @ldst_double() {
210 ; CHECK-LABEL: ldst_double:
212 %addr_8bit = load i8** @varptr
213 %addrfp_8 = getelementptr i8* %addr_8bit, i64 4
214 %addrfp = bitcast i8* %addrfp_8 to double*
216 %valfp = load volatile double* %addrfp
217 ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4]
218 ; CHECK-NOFP-NOT: ldur {{d[0-9]+}},
220 store volatile double %valfp, double* %addrfp
221 ; CHECK: stur {{d[0-9]+}}, [{{x[0-9]+}}, #4]
222 ; CHECK-NOFP-NOT: stur {{d[0-9]+}},