2 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
4 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
5 ; much higher than the ADD instructions in order to hide latency. When not
6 ; specifying a subtarget, the MADD will remain near the end of the block.
8 ; CHECK: *** Final schedule for BB#2 ***
12 ; CHECK: ADDwwi_lsl0_s
13 ; CHECK: ********** MI Scheduling **********
14 @main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
15 @main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
17 ; Function Attrs: nounwind
18 define i32 @main() #0 {
20 %retval = alloca i32, align 4
21 %x = alloca [8 x i32], align 4
22 %y = alloca [8 x i32], align 4
23 %i = alloca i32, align 4
24 %xx = alloca i32, align 4
25 %yy = alloca i32, align 4
26 store i32 0, i32* %retval
27 %0 = bitcast [8 x i32]* %x to i8*
28 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
29 %1 = bitcast [8 x i32]* %y to i8*
30 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
31 store i32 0, i32* %xx, align 4
32 store i32 0, i32* %yy, align 4
33 store i32 0, i32* %i, align 4
36 for.cond: ; preds = %for.inc, %entry
37 %2 = load i32* %i, align 4
38 %cmp = icmp slt i32 %2, 8
39 br i1 %cmp, label %for.body, label %for.end
41 for.body: ; preds = %for.cond
42 %3 = load i32* %i, align 4
43 %idxprom = sext i32 %3 to i64
44 %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
45 %4 = load i32* %arrayidx, align 4
46 %add = add nsw i32 %4, 1
47 store i32 %add, i32* %xx, align 4
48 %5 = load i32* %xx, align 4
49 %add1 = add nsw i32 %5, 12
50 store i32 %add1, i32* %xx, align 4
51 %6 = load i32* %xx, align 4
52 %add2 = add nsw i32 %6, 23
53 store i32 %add2, i32* %xx, align 4
54 %7 = load i32* %xx, align 4
55 %add3 = add nsw i32 %7, 34
56 store i32 %add3, i32* %xx, align 4
57 %8 = load i32* %i, align 4
58 %idxprom4 = sext i32 %8 to i64
59 %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
60 %9 = load i32* %arrayidx5, align 4
61 %10 = load i32* %yy, align 4
62 %mul = mul nsw i32 %10, %9
63 store i32 %mul, i32* %yy, align 4
66 for.inc: ; preds = %for.body
67 %11 = load i32* %i, align 4
68 %inc = add nsw i32 %11, 1
69 store i32 %inc, i32* %i, align 4
72 for.end: ; preds = %for.cond
73 %12 = load i32* %xx, align 4
74 %13 = load i32* %yy, align 4
75 %add6 = add nsw i32 %12, %13
79 ; Function Attrs: nounwind
80 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
82 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
83 attributes #1 = { nounwind }