1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
3 declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)
5 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
7 declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>)
9 declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>)
11 declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>)
13 declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>)
15 declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>)
17 declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>)
19 declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>)
21 declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>)
23 declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>)
27 define <4 x i32> @test_vmull_high_n_s16(<8 x i16> %a, i16 %b) {
28 ; CHECK: test_vmull_high_n_s16:
29 ; CHECK: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[0]
31 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
32 %vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
33 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %b, i32 1
34 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %b, i32 2
35 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %b, i32 3
36 %vmull15.i.i = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
37 ret <4 x i32> %vmull15.i.i
40 define <2 x i64> @test_vmull_high_n_s32(<4 x i32> %a, i32 %b) {
41 ; CHECK: test_vmull_high_n_s32:
42 ; CHECK: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
44 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
45 %vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
46 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %b, i32 1
47 %vmull9.i.i = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
48 ret <2 x i64> %vmull9.i.i
51 define <4 x i32> @test_vmull_high_n_u16(<8 x i16> %a, i16 %b) {
52 ; CHECK: test_vmull_high_n_u16:
53 ; CHECK: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[0]
55 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
56 %vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
57 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %b, i32 1
58 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %b, i32 2
59 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %b, i32 3
60 %vmull15.i.i = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
61 ret <4 x i32> %vmull15.i.i
64 define <2 x i64> @test_vmull_high_n_u32(<4 x i32> %a, i32 %b) {
65 ; CHECK: test_vmull_high_n_u32:
66 ; CHECK: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
68 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
69 %vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
70 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %b, i32 1
71 %vmull9.i.i = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
72 ret <2 x i64> %vmull9.i.i
75 define <4 x i32> @test_vqdmull_high_n_s16(<8 x i16> %a, i16 %b) {
76 ; CHECK: test_vqdmull_high_n_s16:
77 ; CHECK: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[0]
79 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
80 %vecinit.i.i = insertelement <4 x i16> undef, i16 %b, i32 0
81 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %b, i32 1
82 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %b, i32 2
83 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %b, i32 3
84 %vqdmull15.i.i = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
85 ret <4 x i32> %vqdmull15.i.i
88 define <2 x i64> @test_vqdmull_high_n_s32(<4 x i32> %a, i32 %b) {
89 ; CHECK: test_vqdmull_high_n_s32:
90 ; CHECK: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
92 %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
93 %vecinit.i.i = insertelement <2 x i32> undef, i32 %b, i32 0
94 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %b, i32 1
95 %vqdmull9.i.i = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
96 ret <2 x i64> %vqdmull9.i.i
99 define <4 x i32> @test_vmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) {
100 ; CHECK: test_vmlal_high_n_s16:
101 ; CHECK: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[{{[0-9]+}}]
103 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
104 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
105 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1
106 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2
107 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3
108 %vmull2.i.i.i = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
109 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a
110 ret <4 x i32> %add.i.i
113 define <2 x i64> @test_vmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) {
114 ; CHECK: test_vmlal_high_n_s32:
115 ; CHECK: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
117 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
118 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
119 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1
120 %vmull2.i.i.i = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
121 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a
122 ret <2 x i64> %add.i.i
125 define <4 x i32> @test_vmlal_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) {
126 ; CHECK: test_vmlal_high_n_u16:
127 ; CHECK: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[{{[0-9]+}}]
129 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
130 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
131 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1
132 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2
133 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3
134 %vmull2.i.i.i = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
135 %add.i.i = add <4 x i32> %vmull2.i.i.i, %a
136 ret <4 x i32> %add.i.i
139 define <2 x i64> @test_vmlal_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) {
140 ; CHECK: test_vmlal_high_n_u32:
141 ; CHECK: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
143 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
144 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
145 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1
146 %vmull2.i.i.i = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
147 %add.i.i = add <2 x i64> %vmull2.i.i.i, %a
148 ret <2 x i64> %add.i.i
151 define <4 x i32> @test_vqdmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) {
152 ; CHECK: test_vqdmlal_high_n_s16:
153 ; CHECK: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[{{[0-9]+}}]
155 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
156 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
157 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1
158 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2
159 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3
160 %vqdmlal15.i.i = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
161 %vqdmlal17.i.i = tail call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal15.i.i)
162 ret <4 x i32> %vqdmlal17.i.i
165 define <2 x i64> @test_vqdmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) {
166 ; CHECK: test_vqdmlal_high_n_s32:
167 ; CHECK: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
169 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
170 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
171 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1
172 %vqdmlal9.i.i = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
173 %vqdmlal11.i.i = tail call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal9.i.i)
174 ret <2 x i64> %vqdmlal11.i.i
177 define <4 x i32> @test_vmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) {
178 ; CHECK: test_vmlsl_high_n_s16:
179 ; CHECK: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[{{[0-9]+}}]
181 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
182 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
183 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1
184 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2
185 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3
186 %vmull2.i.i.i = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
187 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i
188 ret <4 x i32> %sub.i.i
191 define <2 x i64> @test_vmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) {
192 ; CHECK: test_vmlsl_high_n_s32:
193 ; CHECK: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
195 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
196 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
197 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1
198 %vmull2.i.i.i = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
199 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i
200 ret <2 x i64> %sub.i.i
203 define <4 x i32> @test_vmlsl_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) {
204 ; CHECK: test_vmlsl_high_n_u16:
205 ; CHECK: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[{{[0-9]+}}]
207 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
208 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
209 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1
210 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2
211 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3
212 %vmull2.i.i.i = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
213 %sub.i.i = sub <4 x i32> %a, %vmull2.i.i.i
214 ret <4 x i32> %sub.i.i
217 define <2 x i64> @test_vmlsl_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) {
218 ; CHECK: test_vmlsl_high_n_u32:
219 ; CHECK: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
221 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
222 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
223 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1
224 %vmull2.i.i.i = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
225 %sub.i.i = sub <2 x i64> %a, %vmull2.i.i.i
226 ret <2 x i64> %sub.i.i
229 define <4 x i32> @test_vqdmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) {
230 ; CHECK: test_vqdmlsl_high_n_s16:
231 ; CHECK: sqdmlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[{{[0-9]+}}]
233 %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
234 %vecinit.i.i = insertelement <4 x i16> undef, i16 %c, i32 0
235 %vecinit1.i.i = insertelement <4 x i16> %vecinit.i.i, i16 %c, i32 1
236 %vecinit2.i.i = insertelement <4 x i16> %vecinit1.i.i, i16 %c, i32 2
237 %vecinit3.i.i = insertelement <4 x i16> %vecinit2.i.i, i16 %c, i32 3
238 %vqdmlsl15.i.i = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %shuffle.i.i, <4 x i16> %vecinit3.i.i)
239 %vqdmlsl17.i.i = tail call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl15.i.i)
240 ret <4 x i32> %vqdmlsl17.i.i
243 define <2 x i64> @test_vqdmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) {
244 ; CHECK: test_vqdmlsl_high_n_s32:
245 ; CHECK: sqdmlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
247 %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
248 %vecinit.i.i = insertelement <2 x i32> undef, i32 %c, i32 0
249 %vecinit1.i.i = insertelement <2 x i32> %vecinit.i.i, i32 %c, i32 1
250 %vqdmlsl9.i.i = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %shuffle.i.i, <2 x i32> %vecinit1.i.i)
251 %vqdmlsl11.i.i = tail call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl9.i.i)
252 ret <2 x i64> %vqdmlsl11.i.i
255 define <2 x float> @test_vmul_n_f32(<2 x float> %a, float %b) {
256 ; CHECK: test_vmul_n_f32:
257 ; CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[0]
259 %vecinit.i = insertelement <2 x float> undef, float %b, i32 0
260 %vecinit1.i = insertelement <2 x float> %vecinit.i, float %b, i32 1
261 %mul.i = fmul <2 x float> %vecinit1.i, %a
262 ret <2 x float> %mul.i
265 define <4 x float> @test_vmulq_n_f32(<4 x float> %a, float %b) {
266 ; CHECK: test_vmulq_n_f32:
267 ; CHECK: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[0]
269 %vecinit.i = insertelement <4 x float> undef, float %b, i32 0
270 %vecinit1.i = insertelement <4 x float> %vecinit.i, float %b, i32 1
271 %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %b, i32 2
272 %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %b, i32 3
273 %mul.i = fmul <4 x float> %vecinit3.i, %a
274 ret <4 x float> %mul.i
277 define <2 x double> @test_vmulq_n_f64(<2 x double> %a, double %b) {
278 ; CHECK: test_vmulq_n_f64:
279 ; CHECK: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
281 %vecinit.i = insertelement <2 x double> undef, double %b, i32 0
282 %vecinit1.i = insertelement <2 x double> %vecinit.i, double %b, i32 1
283 %mul.i = fmul <2 x double> %vecinit1.i, %a
284 ret <2 x double> %mul.i
287 define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) {
288 ; CHECK: test_vfma_n_f32:
289 ; CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[{{[0-9]+}}]
291 %vecinit.i = insertelement <2 x float> undef, float %n, i32 0
292 %vecinit1.i = insertelement <2 x float> %vecinit.i, float %n, i32 1
293 %0 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> %vecinit1.i, <2 x float> %a)
297 define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) {
298 ; CHECK: test_vfmaq_n_f32:
299 ; CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
301 %vecinit.i = insertelement <4 x float> undef, float %n, i32 0
302 %vecinit1.i = insertelement <4 x float> %vecinit.i, float %n, i32 1
303 %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %n, i32 2
304 %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %n, i32 3
305 %0 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %vecinit3.i, <4 x float> %a)
309 define <2 x float> @test_vfms_n_f32(<2 x float> %a, <2 x float> %b, float %n) {
310 ; CHECK: test_vfms_n_f32:
311 ; CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[{{[0-9]+}}]
313 %vecinit.i = insertelement <2 x float> undef, float %n, i32 0
314 %vecinit1.i = insertelement <2 x float> %vecinit.i, float %n, i32 1
315 %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %b
316 %1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %0, <2 x float> %vecinit1.i, <2 x float> %a)
320 define <4 x float> @test_vfmsq_n_f32(<4 x float> %a, <4 x float> %b, float %n) {
321 ; CHECK: test_vfmsq_n_f32:
322 ; CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[{{[0-9]+}}]
324 %vecinit.i = insertelement <4 x float> undef, float %n, i32 0
325 %vecinit1.i = insertelement <4 x float> %vecinit.i, float %n, i32 1
326 %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %n, i32 2
327 %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %n, i32 3
328 %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %b
329 %1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %vecinit3.i, <4 x float> %a)