1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
2 ; arm64 has a copy of this test in its own directory.
4 declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>)
6 define <8 x i8> @test_addp_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
7 ; Using registers other than v0, v1 are possible, but would be odd.
8 ; CHECK: test_addp_v8i8:
9 %tmp1 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
10 ; CHECK: addp v0.8b, v0.8b, v1.8b
14 declare <16 x i8> @llvm.arm.neon.vpadd.v16i8(<16 x i8>, <16 x i8>)
16 define <16 x i8> @test_addp_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
17 ; CHECK: test_addp_v16i8:
18 %tmp1 = call <16 x i8> @llvm.arm.neon.vpadd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
19 ; CHECK: addp v0.16b, v0.16b, v1.16b
23 declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>)
25 define <4 x i16> @test_addp_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
26 ; CHECK: test_addp_v4i16:
27 %tmp1 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
28 ; CHECK: addp v0.4h, v0.4h, v1.4h
32 declare <8 x i16> @llvm.arm.neon.vpadd.v8i16(<8 x i16>, <8 x i16>)
34 define <8 x i16> @test_addp_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
35 ; CHECK: test_addp_v8i16:
36 %tmp1 = call <8 x i16> @llvm.arm.neon.vpadd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
37 ; CHECK: addp v0.8h, v0.8h, v1.8h
41 declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>)
43 define <2 x i32> @test_addp_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
44 ; CHECK: test_addp_v2i32:
45 %tmp1 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
46 ; CHECK: addp v0.2s, v0.2s, v1.2s
50 declare <4 x i32> @llvm.arm.neon.vpadd.v4i32(<4 x i32>, <4 x i32>)
52 define <4 x i32> @test_addp_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
53 ; CHECK: test_addp_v4i32:
54 %tmp1 = call <4 x i32> @llvm.arm.neon.vpadd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
55 ; CHECK: addp v0.4s, v0.4s, v1.4s
60 declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
62 define <2 x i64> @test_addp_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
63 ; CHECK: test_addp_v2i64:
64 %val = call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
65 ; CHECK: addp v0.2d, v0.2d, v1.2d
69 declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>)
70 declare <4 x float> @llvm.arm.neon.vpadd.v4f32(<4 x float>, <4 x float>)
71 declare <2 x double> @llvm.arm.neon.vpadd.v2f64(<2 x double>, <2 x double>)
73 define <2 x float> @test_faddp_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
74 ; CHECK: test_faddp_v2f32:
75 %val = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %lhs, <2 x float> %rhs)
76 ; CHECK: faddp v0.2s, v0.2s, v1.2s
80 define <4 x float> @test_faddp_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
81 ; CHECK: test_faddp_v4f32:
82 %val = call <4 x float> @llvm.arm.neon.vpadd.v4f32(<4 x float> %lhs, <4 x float> %rhs)
83 ; CHECK: faddp v0.4s, v0.4s, v1.4s
87 define <2 x double> @test_faddp_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
88 ; CHECK: test_faddp_v2f64:
89 %val = call <2 x double> @llvm.arm.neon.vpadd.v2f64(<2 x double> %lhs, <2 x double> %rhs)
90 ; CHECK: faddp v0.2d, v0.2d, v1.2d
94 define i32 @test_vaddv.v2i32(<2 x i32> %a) {
95 ; CHECK-LABEL: test_vaddv.v2i32
96 ; CHECK: addp {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
97 %1 = tail call <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32> %a)
98 %2 = extractelement <1 x i32> %1, i32 0
102 declare <1 x i32> @llvm.aarch64.neon.vaddv.v1i32.v2i32(<2 x i32>)