1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2 ; arm64 has its own copy of this test
4 define <8 x i8> @add8xi8(<8 x i8> %A, <8 x i8> %B) {
5 ;CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
6 %tmp3 = add <8 x i8> %A, %B;
10 define <16 x i8> @add16xi8(<16 x i8> %A, <16 x i8> %B) {
11 ;CHECK: add {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
12 %tmp3 = add <16 x i8> %A, %B;
16 define <4 x i16> @add4xi16(<4 x i16> %A, <4 x i16> %B) {
17 ;CHECK: add {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
18 %tmp3 = add <4 x i16> %A, %B;
22 define <8 x i16> @add8xi16(<8 x i16> %A, <8 x i16> %B) {
23 ;CHECK: add {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
24 %tmp3 = add <8 x i16> %A, %B;
28 define <2 x i32> @add2xi32(<2 x i32> %A, <2 x i32> %B) {
29 ;CHECK: add {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
30 %tmp3 = add <2 x i32> %A, %B;
34 define <4 x i32> @add4x32(<4 x i32> %A, <4 x i32> %B) {
35 ;CHECK: add {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
36 %tmp3 = add <4 x i32> %A, %B;
40 define <2 x i64> @add2xi64(<2 x i64> %A, <2 x i64> %B) {
41 ;CHECK: add {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
42 %tmp3 = add <2 x i64> %A, %B;
46 define <2 x float> @add2xfloat(<2 x float> %A, <2 x float> %B) {
47 ;CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
48 %tmp3 = fadd <2 x float> %A, %B;
52 define <4 x float> @add4xfloat(<4 x float> %A, <4 x float> %B) {
53 ;CHECK: fadd {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
54 %tmp3 = fadd <4 x float> %A, %B;
57 define <2 x double> @add2xdouble(<2 x double> %A, <2 x double> %B) {
58 ;CHECK: add {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
59 %tmp3 = fadd <2 x double> %A, %B;
60 ret <2 x double> %tmp3
63 define <8 x i8> @sub8xi8(<8 x i8> %A, <8 x i8> %B) {
64 ;CHECK: sub {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
65 %tmp3 = sub <8 x i8> %A, %B;
69 define <16 x i8> @sub16xi8(<16 x i8> %A, <16 x i8> %B) {
70 ;CHECK: sub {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
71 %tmp3 = sub <16 x i8> %A, %B;
75 define <4 x i16> @sub4xi16(<4 x i16> %A, <4 x i16> %B) {
76 ;CHECK: sub {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
77 %tmp3 = sub <4 x i16> %A, %B;
81 define <8 x i16> @sub8xi16(<8 x i16> %A, <8 x i16> %B) {
82 ;CHECK: sub {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
83 %tmp3 = sub <8 x i16> %A, %B;
87 define <2 x i32> @sub2xi32(<2 x i32> %A, <2 x i32> %B) {
88 ;CHECK: sub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
89 %tmp3 = sub <2 x i32> %A, %B;
93 define <4 x i32> @sub4x32(<4 x i32> %A, <4 x i32> %B) {
94 ;CHECK: sub {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
95 %tmp3 = sub <4 x i32> %A, %B;
99 define <2 x i64> @sub2xi64(<2 x i64> %A, <2 x i64> %B) {
100 ;CHECK: sub {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
101 %tmp3 = sub <2 x i64> %A, %B;
105 define <2 x float> @sub2xfloat(<2 x float> %A, <2 x float> %B) {
106 ;CHECK: fsub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
107 %tmp3 = fsub <2 x float> %A, %B;
108 ret <2 x float> %tmp3
111 define <4 x float> @sub4xfloat(<4 x float> %A, <4 x float> %B) {
112 ;CHECK: fsub {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
113 %tmp3 = fsub <4 x float> %A, %B;
114 ret <4 x float> %tmp3
116 define <2 x double> @sub2xdouble(<2 x double> %A, <2 x double> %B) {
117 ;CHECK: sub {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
118 %tmp3 = fsub <2 x double> %A, %B;
119 ret <2 x double> %tmp3
122 define <1 x double> @test_vadd_f64(<1 x double> %a, <1 x double> %b) {
123 ; CHECK-LABEL: test_vadd_f64
124 ; CHECK: fadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
125 %1 = fadd <1 x double> %a, %b
129 define <1 x double> @test_vmul_f64(<1 x double> %a, <1 x double> %b) {
130 ; CHECK-LABEL: test_vmul_f64
131 ; CHECK: fmul d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
132 %1 = fmul <1 x double> %a, %b
136 define <1 x double> @test_vdiv_f64(<1 x double> %a, <1 x double> %b) {
137 ; CHECK-LABEL: test_vdiv_f64
138 ; CHECK: fdiv d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
139 %1 = fdiv <1 x double> %a, %b
143 define <1 x double> @test_vmla_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
144 ; CHECK-LABEL: test_vmla_f64
145 ; CHECK: fmul d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
146 ; CHECK: fadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
147 %1 = fmul <1 x double> %b, %c
148 %2 = fadd <1 x double> %1, %a
152 define <1 x double> @test_vmls_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
153 ; CHECK-LABEL: test_vmls_f64
154 ; CHECK: fmul d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
155 ; CHECK: fsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
156 %1 = fmul <1 x double> %b, %c
157 %2 = fsub <1 x double> %a, %1
161 define <1 x double> @test_vfms_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
162 ; CHECK-LABEL: test_vfms_f64
163 ; CHECK: fmsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
164 %1 = fsub <1 x double> <double -0.000000e+00>, %b
165 %2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a)
169 define <1 x double> @test_vfma_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
170 ; CHECK-LABEL: test_vfma_f64
171 ; CHECK: fmadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
172 %1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a)
176 define <1 x double> @test_vsub_f64(<1 x double> %a, <1 x double> %b) {
177 ; CHECK-LABEL: test_vsub_f64
178 ; CHECK: fsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
179 %1 = fsub <1 x double> %a, %b
183 define <1 x double> @test_vabd_f64(<1 x double> %a, <1 x double> %b) {
184 ; CHECK-LABEL: test_vabd_f64
185 ; CHECK: fabd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
186 %1 = tail call <1 x double> @llvm.arm.neon.vabds.v1f64(<1 x double> %a, <1 x double> %b)
190 define <1 x double> @test_vmax_f64(<1 x double> %a, <1 x double> %b) {
191 ; CHECK-LABEL: test_vmax_f64
192 ; CHECK: fmax d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
193 %1 = tail call <1 x double> @llvm.arm.neon.vmaxs.v1f64(<1 x double> %a, <1 x double> %b)
197 define <1 x double> @test_vmin_f64(<1 x double> %a, <1 x double> %b) {
198 ; CHECK-LABEL: test_vmin_f64
199 ; CHECK: fmin d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
200 %1 = tail call <1 x double> @llvm.arm.neon.vmins.v1f64(<1 x double> %a, <1 x double> %b)
204 define <1 x double> @test_vmaxnm_f64(<1 x double> %a, <1 x double> %b) {
205 ; CHECK-LABEL: test_vmaxnm_f64
206 ; CHECK: fmaxnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
207 %1 = tail call <1 x double> @llvm.aarch64.neon.vmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
211 define <1 x double> @test_vminnm_f64(<1 x double> %a, <1 x double> %b) {
212 ; CHECK-LABEL: test_vminnm_f64
213 ; CHECK: fminnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
214 %1 = tail call <1 x double> @llvm.aarch64.neon.vminnm.v1f64(<1 x double> %a, <1 x double> %b)
218 define <1 x double> @test_vabs_f64(<1 x double> %a) {
219 ; CHECK-LABEL: test_vabs_f64
220 ; CHECK: fabs d{{[0-9]+}}, d{{[0-9]+}}
221 %1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a)
225 define <1 x double> @test_vneg_f64(<1 x double> %a) {
226 ; CHECK-LABEL: test_vneg_f64
227 ; CHECK: fneg d{{[0-9]+}}, d{{[0-9]+}}
228 %1 = fsub <1 x double> <double -0.000000e+00>, %a
232 declare <1 x double> @llvm.fabs.v1f64(<1 x double>)
233 declare <1 x double> @llvm.aarch64.neon.vminnm.v1f64(<1 x double>, <1 x double>)
234 declare <1 x double> @llvm.aarch64.neon.vmaxnm.v1f64(<1 x double>, <1 x double>)
235 declare <1 x double> @llvm.arm.neon.vmins.v1f64(<1 x double>, <1 x double>)
236 declare <1 x double> @llvm.arm.neon.vmaxs.v1f64(<1 x double>, <1 x double>)
237 declare <1 x double> @llvm.arm.neon.vabds.v1f64(<1 x double>, <1 x double>)
238 declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>)
240 define <1 x i8> @test_add_v1i8(<1 x i8> %a, <1 x i8> %b) {
241 ;CHECK-LABEL: test_add_v1i8:
242 ;CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
243 %c = add <1 x i8> %a, %b
247 define <1 x i16> @test_add_v1i16(<1 x i16> %a, <1 x i16> %b) {
248 ;CHECK-LABEL: test_add_v1i16:
249 ;CHECK: add {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
250 %c = add <1 x i16> %a, %b
254 define <1 x i32> @test_add_v1i32(<1 x i32> %a, <1 x i32> %b) {
255 ;CHECK-LABEL: test_add_v1i32:
256 ;CHECK: add {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
257 %c = add <1 x i32> %a, %b
261 define <1 x i8> @test_sub_v1i8(<1 x i8> %a, <1 x i8> %b) {
262 ;CHECK-LABEL: test_sub_v1i8:
263 ;CHECK: sub {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
264 %c = sub <1 x i8> %a, %b
268 define <1 x i16> @test_sub_v1i16(<1 x i16> %a, <1 x i16> %b) {
269 ;CHECK-LABEL: test_sub_v1i16:
270 ;CHECK: sub {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
271 %c = sub <1 x i16> %a, %b
275 define <1 x i32> @test_sub_v1i32(<1 x i32> %a, <1 x i32> %b) {
276 ;CHECK-LABEL: test_sub_v1i32:
277 ;CHECK: sub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
278 %c = sub <1 x i32> %a, %b