1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
3 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
4 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
5 %tmp1 = and <8 x i8> %a, %b;
9 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
10 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
11 %tmp1 = and <16 x i8> %a, %b;
16 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
17 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
18 %tmp1 = or <8 x i8> %a, %b;
22 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
23 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
24 %tmp1 = or <16 x i8> %a, %b;
29 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
30 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
31 %tmp1 = xor <8 x i8> %a, %b;
35 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
36 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
37 %tmp1 = xor <16 x i8> %a, %b;
41 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
42 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
43 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
44 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
45 %tmp3 = or <8 x i8> %tmp1, %tmp2
49 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
50 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
51 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
52 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
53 %tmp3 = or <16 x i8> %tmp1, %tmp2
57 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
58 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
59 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
60 %tmp2 = or <8 x i8> %a, %tmp1
64 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
65 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
66 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
67 %tmp2 = or <16 x i8> %a, %tmp1
71 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
72 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
73 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
74 %tmp2 = and <8 x i8> %a, %tmp1
78 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
79 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
80 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
81 %tmp2 = and <16 x i8> %a, %tmp1
85 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
86 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
87 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
91 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
92 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
93 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
97 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
98 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
99 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
103 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
104 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
105 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
109 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
110 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
111 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
115 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
116 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
117 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
121 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
122 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
123 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
127 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
128 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
129 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
133 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
134 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
135 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
139 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
140 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
141 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
145 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
146 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
147 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
151 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
152 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
153 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
157 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
158 ;CHECK: bic {{v[0-9]+}}.2s, #0x10
159 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
163 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
164 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #8
165 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
169 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
170 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #16
171 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
175 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
176 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #24
177 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
181 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
182 ;CHECK: bic {{v[0-9]+}}.4s, #0x10
183 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
187 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
188 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #8
189 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
193 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
194 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #16
195 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
199 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
200 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #24
201 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
205 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
206 ;CHECK: bic {{v[0-9]+}}.4h, #0x10
207 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
211 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
212 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
213 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
217 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
218 ;CHECK: bic {{v[0-9]+}}.4h, #0x10, lsl #8
219 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
223 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
224 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
225 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
229 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
230 ;CHECK: bic {{v[0-9]+}}.8h, #0x10
231 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
232 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
236 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
237 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
238 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
242 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
243 ;CHECK: bic {{v[0-9]+}}.8h, #0x10, lsl #8
244 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
245 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
249 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
250 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
251 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
255 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
256 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
257 %tmp1 = and <2 x i32> %a, %b;
261 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
262 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
263 %tmp1 = and <4 x i16> %a, %b;
267 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
268 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
269 %tmp1 = and <1 x i64> %a, %b;
273 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
274 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
275 %tmp1 = and <4 x i32> %a, %b;
279 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
280 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
281 %tmp1 = and <8 x i16> %a, %b;
285 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
286 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
287 %tmp1 = and <2 x i64> %a, %b;
291 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
292 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
293 %tmp1 = or <2 x i32> %a, %b;
297 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
298 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
299 %tmp1 = or <4 x i16> %a, %b;
303 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
304 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
305 %tmp1 = or <1 x i64> %a, %b;
309 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
310 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
311 %tmp1 = or <4 x i32> %a, %b;
315 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
316 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
317 %tmp1 = or <8 x i16> %a, %b;
321 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
322 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
323 %tmp1 = or <2 x i64> %a, %b;
327 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
328 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
329 %tmp1 = xor <2 x i32> %a, %b;
333 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
334 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
335 %tmp1 = xor <4 x i16> %a, %b;
339 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
340 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
341 %tmp1 = xor <1 x i64> %a, %b;
345 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
346 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
347 %tmp1 = xor <4 x i32> %a, %b;
351 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
352 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
353 %tmp1 = xor <8 x i16> %a, %b;
357 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
358 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
359 %tmp1 = xor <2 x i64> %a, %b;
364 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
365 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
366 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
367 %tmp2 = and <2 x i32> %a, %tmp1
371 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
372 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
373 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
374 %tmp2 = and <4 x i16> %a, %tmp1
378 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
379 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
380 %tmp1 = xor <1 x i64> %b, < i64 -1>
381 %tmp2 = and <1 x i64> %a, %tmp1
385 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
386 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
387 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
388 %tmp2 = and <4 x i32> %a, %tmp1
392 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
393 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
394 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
395 %tmp2 = and <8 x i16> %a, %tmp1
399 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
400 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
401 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
402 %tmp2 = and <2 x i64> %a, %tmp1
406 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
407 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
408 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
409 %tmp2 = or <2 x i32> %a, %tmp1
413 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
414 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
415 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
416 %tmp2 = or <4 x i16> %a, %tmp1
420 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
421 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
422 %tmp1 = xor <1 x i64> %b, < i64 -1>
423 %tmp2 = or <1 x i64> %a, %tmp1
427 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
428 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
429 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
430 %tmp2 = or <4 x i32> %a, %tmp1
434 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
435 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
436 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
437 %tmp2 = or <8 x i16> %a, %tmp1
441 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
442 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
443 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
444 %tmp2 = or <2 x i64> %a, %tmp1
448 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
449 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
450 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
451 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
452 %tmp3 = or <2 x i32> %tmp1, %tmp2
457 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
458 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
459 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
460 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
461 %tmp3 = or <4 x i16> %tmp1, %tmp2
465 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
466 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
467 %tmp1 = and <1 x i64> %a, < i64 -16 >
468 %tmp2 = and <1 x i64> %b, < i64 15 >
469 %tmp3 = or <1 x i64> %tmp1, %tmp2
473 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
474 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
475 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
476 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
477 %tmp3 = or <4 x i32> %tmp1, %tmp2
481 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
482 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
483 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
484 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
485 %tmp3 = or <8 x i16> %tmp1, %tmp2
489 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
490 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
491 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
492 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
493 %tmp3 = or <2 x i64> %tmp1, %tmp2
498 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
499 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
500 %1 = and <8 x i8> %v1, %v2
501 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
502 %3 = and <8 x i8> %2, %v3
503 %4 = or <8 x i8> %1, %3
507 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
508 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
509 %1 = and <4 x i16> %v1, %v2
510 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
511 %3 = and <4 x i16> %2, %v3
512 %4 = or <4 x i16> %1, %3
516 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
517 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
518 %1 = and <2 x i32> %v1, %v2
519 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
520 %3 = and <2 x i32> %2, %v3
521 %4 = or <2 x i32> %1, %3
525 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
526 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
527 %1 = and <1 x i64> %v1, %v2
528 %2 = xor <1 x i64> %v1, <i64 -1>
529 %3 = and <1 x i64> %2, %v3
530 %4 = or <1 x i64> %1, %3
534 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
535 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
536 %1 = and <16 x i8> %v1, %v2
537 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
538 %3 = and <16 x i8> %2, %v3
539 %4 = or <16 x i8> %1, %3
543 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
544 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
545 %1 = and <8 x i16> %v1, %v2
546 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
547 %3 = and <8 x i16> %2, %v3
548 %4 = or <8 x i16> %1, %3
552 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
553 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
554 %1 = and <4 x i32> %v1, %v2
555 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
556 %3 = and <4 x i32> %2, %v3
557 %4 = or <4 x i32> %1, %3
561 define <8 x i8> @vselect_v8i8(<8 x i8> %a) {
562 ;CHECK: movi {{d[0-9]+}}, #0xffff
563 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
564 %b = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> <i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
568 define <4 x i16> @vselect_v4i16(<4 x i16> %a) {
569 ;CHECK: movi {{d[0-9]+}}, #0xffff
570 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
571 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %a, <4 x i16> <i16 undef, i16 0, i16 0, i16 0>
575 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
576 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
577 ;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
578 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
579 %cmp = icmp ne <8 x i8> %a, %b
580 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
584 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
585 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
586 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
587 %cmp = icmp eq <8 x i8> %a, %b
588 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
592 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
593 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
594 ;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
595 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
596 %cmp = icmp ne <8 x i8> %a, zeroinitializer
597 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
601 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
602 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
603 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
604 %cmp = icmp eq <8 x i8> %a, zeroinitializer
605 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
609 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
610 ;CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
611 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
612 %tmp3 = and <8 x i8> %a, %b
613 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
614 %d = select <8 x i1> %tmp4, <8 x i8> %b, <8 x i8> %c
618 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
619 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
620 %1 = and <2 x i64> %v1, %v2
621 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
622 %3 = and <2 x i64> %2, %v3
623 %4 = or <2 x i64> %1, %3
627 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
628 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
629 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
633 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
634 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
635 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
639 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
640 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
641 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
645 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
646 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
647 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
651 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
652 ;CHECK: bic {{v[0-9]+}}.2s, #0xff
653 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
657 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
658 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #8
659 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
663 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
664 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #16
665 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
669 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
670 ;CHECK: bic {{v[0-9]+}}.2s, #0xfe, lsl #24
671 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
675 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
676 ;CHECK: bic {{v[0-9]+}}.2s, #0xff
677 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
681 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
682 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #8
683 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
687 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
688 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #16
689 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
693 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
694 ;CHECK: bic {{v[0-9]+}}.2s, #0xfe, lsl #24
695 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
700 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
701 ;CHECK: bic {{v[0-9]+}}.2s, #0xff
702 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>
706 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
707 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #8
708 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>
712 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
713 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #16
714 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
718 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
719 ;CHECK: bic {{v[0-9]+}}.2s, #0xfe, lsl #24
720 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>
724 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
725 ;CHECK: bic {{v[0-9]+}}.4s, #0xff
726 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
730 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
731 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #8
732 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
736 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
737 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #16
738 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
742 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
743 ;CHECK: bic {{v[0-9]+}}.4s, #0xfe, lsl #24
744 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
748 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
749 ;CHECK: bic {{v[0-9]+}}.4s, #0xff
750 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
754 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
755 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #8
756 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
760 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
761 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #16
762 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
766 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
767 ;CHECK: bic {{v[0-9]+}}.4s, #0xfe, lsl #24
768 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
772 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
773 ;CHECK: bic {{v[0-9]+}}.4s, #0xff
774 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
778 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
779 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #8
780 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
784 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
785 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #16
786 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
790 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
791 ;CHECK: bic {{v[0-9]+}}.4s, #0xfe, lsl #24
792 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
796 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
797 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
798 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
802 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
803 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
804 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
808 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
809 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
810 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
814 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
815 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
816 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
820 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
821 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
822 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
826 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
827 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
828 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>
832 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
833 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
834 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
838 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
839 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
840 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
844 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
845 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
846 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
850 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
851 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
852 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
856 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
857 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
858 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
862 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
863 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
864 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
868 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
869 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
870 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
874 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
875 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
876 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
880 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
881 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
882 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
886 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
887 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
888 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
892 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
893 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
894 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
898 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
899 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
900 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
904 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
905 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
906 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
910 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
911 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
912 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
916 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
917 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
918 %tmp1 = or <1 x i64> %a, < i64 1095216660735>
922 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
923 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
924 %tmp1 = or <1 x i64> %a, < i64 280375465148160>
928 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
929 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
930 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>
934 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
935 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
936 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
940 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
941 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
942 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
946 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
947 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
948 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
952 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
953 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
954 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
958 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
959 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
960 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
964 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
965 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
966 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
970 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
971 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
972 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
976 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
977 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
978 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
982 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
983 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
984 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
988 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
989 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
990 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
994 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
995 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
996 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
1000 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
1001 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
1002 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
1006 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
1007 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
1008 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
1012 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
1013 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
1014 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1018 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
1019 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
1020 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1024 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
1025 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
1026 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
1030 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
1031 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
1032 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
1036 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
1037 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
1038 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>
1042 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
1043 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
1044 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
1048 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
1049 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
1050 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1054 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
1055 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
1056 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1060 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
1061 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
1062 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
1066 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
1067 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
1068 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
1072 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
1073 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
1074 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
1078 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
1079 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
1080 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>