1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
4 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
5 ; CHECK-LABEL: and8xi8:
6 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
7 %tmp1 = and <8 x i8> %a, %b;
11 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
12 ; CHECK-LABEL: and16xi8:
13 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
14 %tmp1 = and <16 x i8> %a, %b;
19 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
20 ; CHECK-LABEL: orr8xi8:
21 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
22 %tmp1 = or <8 x i8> %a, %b;
26 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
27 ; CHECK-LABEL: orr16xi8:
28 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
29 %tmp1 = or <16 x i8> %a, %b;
34 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
35 ; CHECK-LABEL: xor8xi8:
36 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
37 %tmp1 = xor <8 x i8> %a, %b;
41 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
42 ; CHECK-LABEL: xor16xi8:
43 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
44 %tmp1 = xor <16 x i8> %a, %b;
48 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
49 ; CHECK-LABEL: bsl8xi8_const:
50 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
51 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >
52 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >
53 %tmp3 = or <8 x i8> %tmp1, %tmp2
57 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
58 ; CHECK-LABEL: bsl16xi8_const:
59 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
60 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >
61 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >
62 %tmp3 = or <16 x i8> %tmp1, %tmp2
66 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
67 ; CHECK-LABEL: orn8xi8:
68 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
69 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
70 %tmp2 = or <8 x i8> %a, %tmp1
74 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
75 ; CHECK-LABEL: orn16xi8:
76 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
77 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
78 %tmp2 = or <16 x i8> %a, %tmp1
82 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
83 ; CHECK-LABEL: bic8xi8:
84 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
85 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
86 %tmp2 = and <8 x i8> %a, %tmp1
90 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
91 ; CHECK-LABEL: bic16xi8:
92 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
93 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
94 %tmp2 = and <16 x i8> %a, %tmp1
98 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
99 ; CHECK-LABEL: orrimm2s_lsl0:
100 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
101 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
105 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
106 ; CHECK-LABEL: orrimm2s_lsl8:
107 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
108 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
112 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
113 ; CHECK-LABEL: orrimm2s_lsl16:
114 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
115 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
119 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
120 ; CHECK-LABEL: orrimm2s_lsl24:
121 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
122 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
126 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
127 ; CHECK-LABEL: orrimm4s_lsl0:
128 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
129 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
133 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
134 ; CHECK-LABEL: orrimm4s_lsl8:
135 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
136 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
140 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
141 ; CHECK-LABEL: orrimm4s_lsl16:
142 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
143 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
147 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
148 ; CHECK-LABEL: orrimm4s_lsl24:
149 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
150 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
154 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
155 ; CHECK-LABEL: orrimm4h_lsl0:
156 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
157 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
161 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
162 ; CHECK-LABEL: orrimm4h_lsl8:
163 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
164 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
168 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
169 ; CHECK-LABEL: orrimm8h_lsl0:
170 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
171 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
175 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
176 ; CHECK-LABEL: orrimm8h_lsl8:
177 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
178 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
182 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
183 ; CHECK-LABEL: bicimm2s_lsl0:
184 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}
185 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
189 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
190 ; CHECK-LABEL: bicimm2s_lsl8:
191 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8
192 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
196 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
197 ; CHECK-LABEL: bicimm2s_lsl16:
198 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16
199 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
203 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
204 ; CHECK-LABEL: bicimm2s_lsl124:
205 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24
206 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
210 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
211 ; CHECK-LABEL: bicimm4s_lsl0:
212 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}
213 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
217 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
218 ; CHECK-LABEL: bicimm4s_lsl8:
219 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8
220 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
224 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
225 ; CHECK-LABEL: bicimm4s_lsl16:
226 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16
227 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
231 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
232 ; CHECK-LABEL: bicimm4s_lsl124:
233 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24
234 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
238 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
239 ; CHECK-LABEL: bicimm4h_lsl0_a:
240 ; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}}
241 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
245 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
246 ; CHECK-LABEL: bicimm4h_lsl0_b:
247 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
248 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
252 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
253 ; CHECK-LABEL: bicimm4h_lsl8_a:
254 ; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8
255 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
259 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
260 ; CHECK-LABEL: bicimm4h_lsl8_b:
261 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
262 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
266 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
267 ; CHECK-LABEL: bicimm8h_lsl0_a:
268 ; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}}
269 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
270 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
274 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
275 ; CHECK-LABEL: bicimm8h_lsl0_b:
276 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
277 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
281 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
282 ; CHECK-LABEL: bicimm8h_lsl8_a:
283 ; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8
284 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
285 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
289 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
290 ; CHECK-LABEL: bicimm8h_lsl8_b:
291 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
292 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
296 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
297 ; CHECK-LABEL: and2xi32:
298 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
299 %tmp1 = and <2 x i32> %a, %b;
303 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
304 ; CHECK-LABEL: and4xi16:
305 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
306 %tmp1 = and <4 x i16> %a, %b;
310 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
311 ; CHECK-LABEL: and1xi64:
312 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
313 %tmp1 = and <1 x i64> %a, %b;
317 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
318 ; CHECK-LABEL: and4xi32:
319 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
320 %tmp1 = and <4 x i32> %a, %b;
324 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
325 ; CHECK-LABEL: and8xi16:
326 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
327 %tmp1 = and <8 x i16> %a, %b;
331 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
332 ; CHECK-LABEL: and2xi64:
333 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
334 %tmp1 = and <2 x i64> %a, %b;
338 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
339 ; CHECK-LABEL: orr2xi32:
340 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
341 %tmp1 = or <2 x i32> %a, %b;
345 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
346 ; CHECK-LABEL: orr4xi16:
347 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
348 %tmp1 = or <4 x i16> %a, %b;
352 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
353 ; CHECK-LABEL: orr1xi64:
354 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
355 %tmp1 = or <1 x i64> %a, %b;
359 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
360 ; CHECK-LABEL: orr4xi32:
361 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
362 %tmp1 = or <4 x i32> %a, %b;
366 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
367 ; CHECK-LABEL: orr8xi16:
368 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
369 %tmp1 = or <8 x i16> %a, %b;
373 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
374 ; CHECK-LABEL: orr2xi64:
375 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
376 %tmp1 = or <2 x i64> %a, %b;
380 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
381 ; CHECK-LABEL: eor2xi32:
382 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
383 %tmp1 = xor <2 x i32> %a, %b;
387 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
388 ; CHECK-LABEL: eor4xi16:
389 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
390 %tmp1 = xor <4 x i16> %a, %b;
394 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
395 ; CHECK-LABEL: eor1xi64:
396 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
397 %tmp1 = xor <1 x i64> %a, %b;
401 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
402 ; CHECK-LABEL: eor4xi32:
403 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
404 %tmp1 = xor <4 x i32> %a, %b;
408 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
409 ; CHECK-LABEL: eor8xi16:
410 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
411 %tmp1 = xor <8 x i16> %a, %b;
415 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
416 ; CHECK-LABEL: eor2xi64:
417 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
418 %tmp1 = xor <2 x i64> %a, %b;
423 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
424 ; CHECK-LABEL: bic2xi32:
425 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
426 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
427 %tmp2 = and <2 x i32> %a, %tmp1
431 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
432 ; CHECK-LABEL: bic4xi16:
433 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
434 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
435 %tmp2 = and <4 x i16> %a, %tmp1
439 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
440 ; CHECK-LABEL: bic1xi64:
441 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
442 %tmp1 = xor <1 x i64> %b, < i64 -1>
443 %tmp2 = and <1 x i64> %a, %tmp1
447 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
448 ; CHECK-LABEL: bic4xi32:
449 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
450 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
451 %tmp2 = and <4 x i32> %a, %tmp1
455 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
456 ; CHECK-LABEL: bic8xi16:
457 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
458 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
459 %tmp2 = and <8 x i16> %a, %tmp1
463 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
464 ; CHECK-LABEL: bic2xi64:
465 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
466 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
467 %tmp2 = and <2 x i64> %a, %tmp1
471 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
472 ; CHECK-LABEL: orn2xi32:
473 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
474 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
475 %tmp2 = or <2 x i32> %a, %tmp1
479 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
480 ; CHECK-LABEL: orn4xi16:
481 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
482 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
483 %tmp2 = or <4 x i16> %a, %tmp1
487 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
488 ; CHECK-LABEL: orn1xi64:
489 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
490 %tmp1 = xor <1 x i64> %b, < i64 -1>
491 %tmp2 = or <1 x i64> %a, %tmp1
495 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
496 ; CHECK-LABEL: orn4xi32:
497 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
498 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
499 %tmp2 = or <4 x i32> %a, %tmp1
503 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
504 ; CHECK-LABEL: orn8xi16:
505 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
506 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
507 %tmp2 = or <8 x i16> %a, %tmp1
511 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
512 ; CHECK-LABEL: orn2xi64:
513 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
514 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
515 %tmp2 = or <2 x i64> %a, %tmp1
519 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
520 ; CHECK-LABEL: bsl2xi32_const:
521 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
522 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >
523 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >
524 %tmp3 = or <2 x i32> %tmp1, %tmp2
529 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
530 ; CHECK-LABEL: bsl4xi16_const:
531 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
532 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >
533 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >
534 %tmp3 = or <4 x i16> %tmp1, %tmp2
538 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
539 ; CHECK-LABEL: bsl1xi64_const:
540 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
541 %tmp1 = and <1 x i64> %a, < i64 -16 >
542 %tmp2 = and <1 x i64> %b, < i64 15 >
543 %tmp3 = or <1 x i64> %tmp1, %tmp2
547 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
548 ; CHECK-LABEL: bsl4xi32_const:
549 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
550 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >
551 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >
552 %tmp3 = or <4 x i32> %tmp1, %tmp2
556 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
557 ; CHECK-LABEL: bsl8xi16_const:
558 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
559 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >
560 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >
561 %tmp3 = or <8 x i16> %tmp1, %tmp2
565 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
566 ; CHECK-LABEL: bsl2xi64_const:
567 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
568 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >
569 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >
570 %tmp3 = or <2 x i64> %tmp1, %tmp2
575 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
576 ; CHECK-LABEL: bsl8xi8:
577 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
578 %1 = and <8 x i8> %v1, %v2
579 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
580 %3 = and <8 x i8> %2, %v3
581 %4 = or <8 x i8> %1, %3
585 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
586 ; CHECK-LABEL: bsl4xi16:
587 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
588 %1 = and <4 x i16> %v1, %v2
589 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
590 %3 = and <4 x i16> %2, %v3
591 %4 = or <4 x i16> %1, %3
595 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
596 ; CHECK-LABEL: bsl2xi32:
597 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
598 %1 = and <2 x i32> %v1, %v2
599 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
600 %3 = and <2 x i32> %2, %v3
601 %4 = or <2 x i32> %1, %3
605 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
606 ; CHECK-LABEL: bsl1xi64:
607 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
608 %1 = and <1 x i64> %v1, %v2
609 %2 = xor <1 x i64> %v1, <i64 -1>
610 %3 = and <1 x i64> %2, %v3
611 %4 = or <1 x i64> %1, %3
615 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
616 ; CHECK-LABEL: bsl16xi8:
617 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
618 %1 = and <16 x i8> %v1, %v2
619 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
620 %3 = and <16 x i8> %2, %v3
621 %4 = or <16 x i8> %1, %3
625 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
626 ; CHECK-LABEL: bsl8xi16:
627 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
628 %1 = and <8 x i16> %v1, %v2
629 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
630 %3 = and <8 x i16> %2, %v3
631 %4 = or <8 x i16> %1, %3
635 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
636 ; CHECK-LABEL: bsl4xi32:
637 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
638 %1 = and <4 x i32> %v1, %v2
639 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
640 %3 = and <4 x i32> %2, %v3
641 %4 = or <4 x i32> %1, %3
645 define <8 x i8> @vselect_v8i8(<8 x i8> %a) {
646 ; CHECK-LABEL: vselect_v8i8:
647 ; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff
648 ; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}}
649 %b = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> <i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
653 define <4 x i16> @vselect_v4i16(<4 x i16> %a) {
654 ; CHECK-LABEL: vselect_v4i16:
655 ; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff
656 ; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}}
657 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %a, <4 x i16> <i16 undef, i16 0, i16 0, i16 0>
661 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
662 ; CHECK-LABEL: vselect_cmp_ne:
663 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
664 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
665 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
666 %cmp = icmp ne <8 x i8> %a, %b
667 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
671 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
672 ; CHECK-LABEL: vselect_cmp_eq:
673 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
674 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
675 %cmp = icmp eq <8 x i8> %a, %b
676 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
680 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
681 ; CHECK-LABEL: vselect_cmpz_ne:
682 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
683 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
684 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
685 %cmp = icmp ne <8 x i8> %a, zeroinitializer
686 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
690 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
691 ; CHECK-LABEL: vselect_cmpz_eq:
692 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
693 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
694 %cmp = icmp eq <8 x i8> %a, zeroinitializer
695 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
699 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
700 ; CHECK-LABEL: vselect_tst:
701 ; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
702 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
703 %tmp3 = and <8 x i8> %a, %b
704 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
705 %d = select <8 x i1> %tmp4, <8 x i8> %b, <8 x i8> %c
709 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
710 ; CHECK-LABEL: bsl2xi64:
711 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
712 %1 = and <2 x i64> %v1, %v2
713 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
714 %3 = and <2 x i64> %2, %v3
715 %4 = or <2 x i64> %1, %3
719 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
720 ; CHECK-LABEL: orrimm8b_as_orrimm4h_lsl0:
721 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
722 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
726 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
727 ; CHECK-LABEL: orrimm8b_as_orimm4h_lsl8:
728 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
729 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
733 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
734 ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl0:
735 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
736 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
740 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
741 ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl8:
742 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
743 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
747 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
748 ; CHECK-LABEL: and8imm2s_lsl0:
749 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}
750 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
754 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
755 ; CHECK-LABEL: and8imm2s_lsl8:
756 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
757 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
761 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
762 ; CHECK-LABEL: and8imm2s_lsl16:
763 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
764 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
768 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
769 ; CHECK-LABEL: and8imm2s_lsl24:
770 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
771 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
775 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
776 ; CHECK-LABEL: and16imm2s_lsl0:
777 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}
778 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
782 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
783 ; CHECK-LABEL: and16imm2s_lsl8:
784 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
785 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
789 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
790 ; CHECK-LABEL: and16imm2s_lsl16:
791 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
792 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
796 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
797 ; CHECK-LABEL: and16imm2s_lsl24:
798 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
799 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
804 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
805 ; CHECK-LABEL: and64imm2s_lsl0:
806 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}
807 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>
811 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
812 ; CHECK-LABEL: and64imm2s_lsl8:
813 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
814 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>
818 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
819 ; CHECK-LABEL: and64imm2s_lsl16:
820 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
821 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
825 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
826 ; CHECK-LABEL: and64imm2s_lsl24:
827 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24
828 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>
832 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
833 ; CHECK-LABEL: and8imm4s_lsl0:
834 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}
835 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
839 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
840 ; CHECK-LABEL: and8imm4s_lsl8:
841 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
842 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
846 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
847 ; CHECK-LABEL: and8imm4s_lsl16:
848 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
849 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
853 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
854 ; CHECK-LABEL: and8imm4s_lsl24:
855 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
856 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
860 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
861 ; CHECK-LABEL: and16imm4s_lsl0:
862 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}
863 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
867 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
868 ; CHECK-LABEL: and16imm4s_lsl8:
869 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
870 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
874 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
875 ; CHECK-LABEL: and16imm4s_lsl16:
876 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
877 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
881 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
882 ; CHECK-LABEL: and16imm4s_lsl24:
883 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
884 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
888 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
889 ; CHECK-LABEL: and64imm4s_lsl0:
890 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}
891 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
895 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
896 ; CHECK-LABEL: and64imm4s_lsl8:
897 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
898 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
902 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
903 ; CHECK-LABEL: and64imm4s_lsl16:
904 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
905 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
909 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
910 ; CHECK-LABEL: and64imm4s_lsl24:
911 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24
912 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
916 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
917 ; CHECK-LABEL: and8imm4h_lsl0:
918 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
919 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
923 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
924 ; CHECK-LABEL: and8imm4h_lsl8:
925 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
926 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
930 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
931 ; CHECK-LABEL: and16imm4h_lsl0:
932 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
933 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
937 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
938 ; CHECK-LABEL: and16imm4h_lsl8:
939 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
940 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
944 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
945 ; CHECK-LABEL: and64imm4h_lsl0:
946 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}
947 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
951 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
952 ; CHECK-LABEL: and64imm4h_lsl8:
953 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
954 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>
958 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
959 ; CHECK-LABEL: and8imm8h_lsl0:
960 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
961 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
965 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
966 ; CHECK-LABEL: and8imm8h_lsl8:
967 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
968 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
972 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
973 ; CHECK-LABEL: and16imm8h_lsl0:
974 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
975 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
979 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
980 ; CHECK-LABEL: and16imm8h_lsl8:
981 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
982 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
986 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
987 ; CHECK-LABEL: and64imm8h_lsl0:
988 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}
989 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
993 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
994 ; CHECK-LABEL: and64imm8h_lsl8:
995 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
996 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
1000 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
1001 ; CHECK-LABEL: orr8imm2s_lsl0:
1002 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
1003 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
1007 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
1008 ; CHECK-LABEL: orr8imm2s_lsl8:
1009 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
1010 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
1014 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
1015 ; CHECK-LABEL: orr8imm2s_lsl16:
1016 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
1017 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
1021 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
1022 ; CHECK-LABEL: orr8imm2s_lsl24:
1023 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
1024 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
1028 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
1029 ; CHECK-LABEL: orr16imm2s_lsl0:
1030 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
1031 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
1035 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
1036 ; CHECK-LABEL: orr16imm2s_lsl8:
1037 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
1038 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
1042 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
1043 ; CHECK-LABEL: orr16imm2s_lsl16:
1044 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
1045 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
1049 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
1050 ; CHECK-LABEL: orr16imm2s_lsl24:
1051 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
1052 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
1056 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
1057 ; CHECK-LABEL: orr64imm2s_lsl0:
1058 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}
1059 %tmp1 = or <1 x i64> %a, < i64 1095216660735>
1063 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
1064 ; CHECK-LABEL: orr64imm2s_lsl8:
1065 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8
1066 %tmp1 = or <1 x i64> %a, < i64 280375465148160>
1070 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
1071 ; CHECK-LABEL: orr64imm2s_lsl16:
1072 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16
1073 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>
1077 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
1078 ; CHECK-LABEL: orr64imm2s_lsl24:
1079 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24
1080 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
1084 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
1085 ; CHECK-LABEL: orr8imm4s_lsl0:
1086 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
1087 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
1091 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
1092 ; CHECK-LABEL: orr8imm4s_lsl8:
1093 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
1094 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
1098 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
1099 ; CHECK-LABEL: orr8imm4s_lsl16:
1100 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
1101 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
1105 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
1106 ; CHECK-LABEL: orr8imm4s_lsl24:
1107 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
1108 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
1112 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
1113 ; CHECK-LABEL: orr16imm4s_lsl0:
1114 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
1115 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
1119 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
1120 ; CHECK-LABEL: orr16imm4s_lsl8:
1121 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
1122 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
1126 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
1127 ; CHECK-LABEL: orr16imm4s_lsl16:
1128 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
1129 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
1133 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
1134 ; CHECK-LABEL: orr16imm4s_lsl24:
1135 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
1136 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
1140 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
1141 ; CHECK-LABEL: orr64imm4s_lsl0:
1142 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}
1143 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
1147 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
1148 ; CHECK-LABEL: orr64imm4s_lsl8:
1149 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8
1150 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
1154 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
1155 ; CHECK-LABEL: orr64imm4s_lsl16:
1156 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16
1157 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
1161 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
1162 ; CHECK-LABEL: orr64imm4s_lsl24:
1163 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24
1164 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
1168 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
1169 ; CHECK-LABEL: orr8imm4h_lsl0:
1170 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
1171 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1175 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
1176 ; CHECK-LABEL: orr8imm4h_lsl8:
1177 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
1178 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1182 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
1183 ; CHECK-LABEL: orr16imm4h_lsl0:
1184 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
1185 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
1189 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
1190 ; CHECK-LABEL: orr16imm4h_lsl8:
1191 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
1192 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
1196 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
1197 ; CHECK-LABEL: orr64imm4h_lsl0:
1198 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}
1199 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>
1203 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
1204 ; CHECK-LABEL: orr64imm4h_lsl8:
1205 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
1206 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
1210 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
1211 ; CHECK-LABEL: orr8imm8h_lsl0:
1212 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
1213 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1217 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
1218 ; CHECK-LABEL: orr8imm8h_lsl8:
1219 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
1220 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1224 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
1225 ; CHECK-LABEL: orr16imm8h_lsl0:
1226 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
1227 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
1231 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
1232 ; CHECK-LABEL: orr16imm8h_lsl8:
1233 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
1234 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
1238 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
1239 ; CHECK-LABEL: orr64imm8h_lsl0:
1240 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}
1241 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
1245 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
1246 ; CHECK-LABEL: orr64imm8h_lsl8:
1247 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
1248 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>