1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) {
4 ; CHECK-LABEL: cmeq8xi8:
5 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
6 %tmp3 = icmp eq <8 x i8> %A, %B;
7 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
11 define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) {
12 ; CHECK-LABEL: cmeq16xi8:
13 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
14 %tmp3 = icmp eq <16 x i8> %A, %B;
15 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
19 define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) {
20 ; CHECK-LABEL: cmeq4xi16:
21 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
22 %tmp3 = icmp eq <4 x i16> %A, %B;
23 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
27 define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) {
28 ; CHECK-LABEL: cmeq8xi16:
29 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
30 %tmp3 = icmp eq <8 x i16> %A, %B;
31 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
35 define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) {
36 ; CHECK-LABEL: cmeq2xi32:
37 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
38 %tmp3 = icmp eq <2 x i32> %A, %B;
39 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
43 define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) {
44 ; CHECK-LABEL: cmeq4xi32:
45 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
46 %tmp3 = icmp eq <4 x i32> %A, %B;
47 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
51 define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
52 ; CHECK-LABEL: cmeq2xi64:
53 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
54 %tmp3 = icmp eq <2 x i64> %A, %B;
55 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
59 define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
60 ; CHECK-LABEL: cmne8xi8:
61 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
62 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
63 %tmp3 = icmp ne <8 x i8> %A, %B;
64 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
68 define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
69 ; CHECK-LABEL: cmne16xi8:
70 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
71 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
72 %tmp3 = icmp ne <16 x i8> %A, %B;
73 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
77 define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
78 ; CHECK-LABEL: cmne4xi16:
79 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
80 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
81 %tmp3 = icmp ne <4 x i16> %A, %B;
82 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
86 define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
87 ; CHECK-LABEL: cmne8xi16:
88 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
89 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
90 %tmp3 = icmp ne <8 x i16> %A, %B;
91 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
95 define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
96 ; CHECK-LABEL: cmne2xi32:
97 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
98 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
99 %tmp3 = icmp ne <2 x i32> %A, %B;
100 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
104 define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
105 ; CHECK-LABEL: cmne4xi32:
106 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
107 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
108 %tmp3 = icmp ne <4 x i32> %A, %B;
109 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
113 define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
114 ; CHECK-LABEL: cmne2xi64:
115 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
116 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
117 %tmp3 = icmp ne <2 x i64> %A, %B;
118 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
122 define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) {
123 ; CHECK-LABEL: cmgt8xi8:
124 ; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
125 %tmp3 = icmp sgt <8 x i8> %A, %B;
126 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
130 define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) {
131 ; CHECK-LABEL: cmgt16xi8:
132 ; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
133 %tmp3 = icmp sgt <16 x i8> %A, %B;
134 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
138 define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) {
139 ; CHECK-LABEL: cmgt4xi16:
140 ; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
141 %tmp3 = icmp sgt <4 x i16> %A, %B;
142 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
146 define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) {
147 ; CHECK-LABEL: cmgt8xi16:
148 ; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
149 %tmp3 = icmp sgt <8 x i16> %A, %B;
150 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
154 define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) {
155 ; CHECK-LABEL: cmgt2xi32:
156 ; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
157 %tmp3 = icmp sgt <2 x i32> %A, %B;
158 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
162 define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) {
163 ; CHECK-LABEL: cmgt4xi32:
164 ; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
165 %tmp3 = icmp sgt <4 x i32> %A, %B;
166 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
170 define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) {
171 ; CHECK-LABEL: cmgt2xi64:
172 ; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
173 %tmp3 = icmp sgt <2 x i64> %A, %B;
174 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
178 define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) {
179 ; CHECK-LABEL: cmlt8xi8:
180 ; Using registers other than v0, v1 are possible, but would be odd.
181 ; LT implemented as GT, so check reversed operands.
182 ; CHECK: cmgt {{v[0-9]+}}.8b, v1.8b, v0.8b
183 %tmp3 = icmp slt <8 x i8> %A, %B;
184 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
188 define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) {
189 ; CHECK-LABEL: cmlt16xi8:
190 ; Using registers other than v0, v1 are possible, but would be odd.
191 ; LT implemented as GT, so check reversed operands.
192 ; CHECK: cmgt {{v[0-9]+}}.16b, v1.16b, v0.16b
193 %tmp3 = icmp slt <16 x i8> %A, %B;
194 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
198 define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) {
199 ; CHECK-LABEL: cmlt4xi16:
200 ; Using registers other than v0, v1 are possible, but would be odd.
201 ; LT implemented as GT, so check reversed operands.
202 ; CHECK: cmgt {{v[0-9]+}}.4h, v1.4h, v0.4h
203 %tmp3 = icmp slt <4 x i16> %A, %B;
204 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
208 define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) {
209 ; CHECK-LABEL: cmlt8xi16:
210 ; Using registers other than v0, v1 are possible, but would be odd.
211 ; LT implemented as GT, so check reversed operands.
212 ; CHECK: cmgt {{v[0-9]+}}.8h, v1.8h, v0.8h
213 %tmp3 = icmp slt <8 x i16> %A, %B;
214 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
218 define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) {
219 ; CHECK-LABEL: cmlt2xi32:
220 ; Using registers other than v0, v1 are possible, but would be odd.
221 ; LT implemented as GT, so check reversed operands.
222 ; CHECK: cmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
223 %tmp3 = icmp slt <2 x i32> %A, %B;
224 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
228 define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) {
229 ; CHECK-LABEL: cmlt4xi32:
230 ; Using registers other than v0, v1 are possible, but would be odd.
231 ; LT implemented as GT, so check reversed operands.
232 ; CHECK: cmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
233 %tmp3 = icmp slt <4 x i32> %A, %B;
234 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
238 define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) {
239 ; CHECK-LABEL: cmlt2xi64:
240 ; Using registers other than v0, v1 are possible, but would be odd.
241 ; LT implemented as GT, so check reversed operands.
242 ; CHECK: cmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
243 %tmp3 = icmp slt <2 x i64> %A, %B;
244 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
248 define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) {
249 ; CHECK-LABEL: cmge8xi8:
250 ; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
251 %tmp3 = icmp sge <8 x i8> %A, %B;
252 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
256 define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) {
257 ; CHECK-LABEL: cmge16xi8:
258 ; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
259 %tmp3 = icmp sge <16 x i8> %A, %B;
260 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
264 define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) {
265 ; CHECK-LABEL: cmge4xi16:
266 ; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
267 %tmp3 = icmp sge <4 x i16> %A, %B;
268 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
272 define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) {
273 ; CHECK-LABEL: cmge8xi16:
274 ; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
275 %tmp3 = icmp sge <8 x i16> %A, %B;
276 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
280 define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) {
281 ; CHECK-LABEL: cmge2xi32:
282 ; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
283 %tmp3 = icmp sge <2 x i32> %A, %B;
284 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
288 define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) {
289 ; CHECK-LABEL: cmge4xi32:
290 ; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
291 %tmp3 = icmp sge <4 x i32> %A, %B;
292 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
296 define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) {
297 ; CHECK-LABEL: cmge2xi64:
298 ; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
299 %tmp3 = icmp sge <2 x i64> %A, %B;
300 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
304 define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) {
305 ; CHECK-LABEL: cmle8xi8:
306 ; Using registers other than v0, v1 are possible, but would be odd.
307 ; LE implemented as GE, so check reversed operands.
308 ; CHECK: cmge {{v[0-9]+}}.8b, v1.8b, v0.8b
309 %tmp3 = icmp sle <8 x i8> %A, %B;
310 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
314 define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) {
315 ; CHECK-LABEL: cmle16xi8:
316 ; Using registers other than v0, v1 are possible, but would be odd.
317 ; LE implemented as GE, so check reversed operands.
318 ; CHECK: cmge {{v[0-9]+}}.16b, v1.16b, v0.16b
319 %tmp3 = icmp sle <16 x i8> %A, %B;
320 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
324 define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) {
325 ; CHECK-LABEL: cmle4xi16:
326 ; Using registers other than v0, v1 are possible, but would be odd.
327 ; LE implemented as GE, so check reversed operands.
328 ; CHECK: cmge {{v[0-9]+}}.4h, v1.4h, v0.4h
329 %tmp3 = icmp sle <4 x i16> %A, %B;
330 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
334 define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) {
335 ; CHECK-LABEL: cmle8xi16:
336 ; Using registers other than v0, v1 are possible, but would be odd.
337 ; LE implemented as GE, so check reversed operands.
338 ; CHECK: cmge {{v[0-9]+}}.8h, v1.8h, v0.8h
339 %tmp3 = icmp sle <8 x i16> %A, %B;
340 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
344 define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) {
345 ; CHECK-LABEL: cmle2xi32:
346 ; Using registers other than v0, v1 are possible, but would be odd.
347 ; LE implemented as GE, so check reversed operands.
348 ; CHECK: cmge {{v[0-9]+}}.2s, v1.2s, v0.2s
349 %tmp3 = icmp sle <2 x i32> %A, %B;
350 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
354 define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) {
355 ; CHECK-LABEL: cmle4xi32:
356 ; Using registers other than v0, v1 are possible, but would be odd.
357 ; LE implemented as GE, so check reversed operands.
358 ; CHECK: cmge {{v[0-9]+}}.4s, v1.4s, v0.4s
359 %tmp3 = icmp sle <4 x i32> %A, %B;
360 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
364 define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) {
365 ; CHECK-LABEL: cmle2xi64:
366 ; Using registers other than v0, v1 are possible, but would be odd.
367 ; LE implemented as GE, so check reversed operands.
368 ; CHECK: cmge {{v[0-9]+}}.2d, v1.2d, v0.2d
369 %tmp3 = icmp sle <2 x i64> %A, %B;
370 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
374 define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) {
375 ; CHECK-LABEL: cmhi8xi8:
376 ; CHECK: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
377 %tmp3 = icmp ugt <8 x i8> %A, %B;
378 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
382 define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) {
383 ; CHECK-LABEL: cmhi16xi8:
384 ; CHECK: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
385 %tmp3 = icmp ugt <16 x i8> %A, %B;
386 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
390 define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) {
391 ; CHECK-LABEL: cmhi4xi16:
392 ; CHECK: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
393 %tmp3 = icmp ugt <4 x i16> %A, %B;
394 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
398 define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) {
399 ; CHECK-LABEL: cmhi8xi16:
400 ; CHECK: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
401 %tmp3 = icmp ugt <8 x i16> %A, %B;
402 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
406 define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) {
407 ; CHECK-LABEL: cmhi2xi32:
408 ; CHECK: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
409 %tmp3 = icmp ugt <2 x i32> %A, %B;
410 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
414 define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) {
415 ; CHECK-LABEL: cmhi4xi32:
416 ; CHECK: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
417 %tmp3 = icmp ugt <4 x i32> %A, %B;
418 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
422 define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) {
423 ; CHECK-LABEL: cmhi2xi64:
424 ; CHECK: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
425 %tmp3 = icmp ugt <2 x i64> %A, %B;
426 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
430 define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) {
431 ; CHECK-LABEL: cmlo8xi8:
432 ; Using registers other than v0, v1 are possible, but would be odd.
433 ; LO implemented as HI, so check reversed operands.
434 ; CHECK: cmhi {{v[0-9]+}}.8b, v1.8b, v0.8b
435 %tmp3 = icmp ult <8 x i8> %A, %B;
436 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
440 define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) {
441 ; CHECK-LABEL: cmlo16xi8:
442 ; Using registers other than v0, v1 are possible, but would be odd.
443 ; LO implemented as HI, so check reversed operands.
444 ; CHECK: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
445 %tmp3 = icmp ult <16 x i8> %A, %B;
446 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
450 define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) {
451 ; CHECK-LABEL: cmlo4xi16:
452 ; Using registers other than v0, v1 are possible, but would be odd.
453 ; LO implemented as HI, so check reversed operands.
454 ; CHECK: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
455 %tmp3 = icmp ult <4 x i16> %A, %B;
456 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
460 define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) {
461 ; CHECK-LABEL: cmlo8xi16:
462 ; Using registers other than v0, v1 are possible, but would be odd.
463 ; LO implemented as HI, so check reversed operands.
464 ; CHECK: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
465 %tmp3 = icmp ult <8 x i16> %A, %B;
466 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
470 define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) {
471 ; CHECK-LABEL: cmlo2xi32:
472 ; Using registers other than v0, v1 are possible, but would be odd.
473 ; LO implemented as HI, so check reversed operands.
474 ; CHECK: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
475 %tmp3 = icmp ult <2 x i32> %A, %B;
476 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
480 define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) {
481 ; CHECK-LABEL: cmlo4xi32:
482 ; Using registers other than v0, v1 are possible, but would be odd.
483 ; LO implemented as HI, so check reversed operands.
484 ; CHECK: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
485 %tmp3 = icmp ult <4 x i32> %A, %B;
486 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
490 define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) {
491 ; CHECK-LABEL: cmlo2xi64:
492 ; Using registers other than v0, v1 are possible, but would be odd.
493 ; LO implemented as HI, so check reversed operands.
494 ; CHECK: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
495 %tmp3 = icmp ult <2 x i64> %A, %B;
496 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
500 define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) {
501 ; CHECK-LABEL: cmhs8xi8:
502 ; CHECK: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
503 %tmp3 = icmp uge <8 x i8> %A, %B;
504 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
508 define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) {
509 ; CHECK-LABEL: cmhs16xi8:
510 ; CHECK: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
511 %tmp3 = icmp uge <16 x i8> %A, %B;
512 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
516 define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) {
517 ; CHECK-LABEL: cmhs4xi16:
518 ; CHECK: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
519 %tmp3 = icmp uge <4 x i16> %A, %B;
520 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
524 define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) {
525 ; CHECK-LABEL: cmhs8xi16:
526 ; CHECK: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
527 %tmp3 = icmp uge <8 x i16> %A, %B;
528 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
532 define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) {
533 ; CHECK-LABEL: cmhs2xi32:
534 ; CHECK: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
535 %tmp3 = icmp uge <2 x i32> %A, %B;
536 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
540 define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) {
541 ; CHECK-LABEL: cmhs4xi32:
542 ; CHECK: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
543 %tmp3 = icmp uge <4 x i32> %A, %B;
544 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
548 define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) {
549 ; CHECK-LABEL: cmhs2xi64:
550 ; CHECK: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
551 %tmp3 = icmp uge <2 x i64> %A, %B;
552 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
556 define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) {
557 ; CHECK-LABEL: cmls8xi8:
558 ; Using registers other than v0, v1 are possible, but would be odd.
559 ; LS implemented as HS, so check reversed operands.
560 ; CHECK: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
561 %tmp3 = icmp ule <8 x i8> %A, %B;
562 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
566 define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) {
567 ; CHECK-LABEL: cmls16xi8:
568 ; Using registers other than v0, v1 are possible, but would be odd.
569 ; LS implemented as HS, so check reversed operands.
570 ; CHECK: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
571 %tmp3 = icmp ule <16 x i8> %A, %B;
572 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
576 define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) {
577 ; CHECK-LABEL: cmls4xi16:
578 ; Using registers other than v0, v1 are possible, but would be odd.
579 ; LS implemented as HS, so check reversed operands.
580 ; CHECK: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
581 %tmp3 = icmp ule <4 x i16> %A, %B;
582 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
586 define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) {
587 ; CHECK-LABEL: cmls8xi16:
588 ; Using registers other than v0, v1 are possible, but would be odd.
589 ; LS implemented as HS, so check reversed operands.
590 ; CHECK: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
591 %tmp3 = icmp ule <8 x i16> %A, %B;
592 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
596 define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) {
597 ; CHECK-LABEL: cmls2xi32:
598 ; Using registers other than v0, v1 are possible, but would be odd.
599 ; LS implemented as HS, so check reversed operands.
600 ; CHECK: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
601 %tmp3 = icmp ule <2 x i32> %A, %B;
602 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
606 define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) {
607 ; CHECK-LABEL: cmls4xi32:
608 ; Using registers other than v0, v1 are possible, but would be odd.
609 ; LS implemented as HS, so check reversed operands.
610 ; CHECK: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
611 %tmp3 = icmp ule <4 x i32> %A, %B;
612 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
616 define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) {
617 ; CHECK-LABEL: cmls2xi64:
618 ; Using registers other than v0, v1 are possible, but would be odd.
619 ; LS implemented as HS, so check reversed operands.
620 ; CHECK: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
621 %tmp3 = icmp ule <2 x i64> %A, %B;
622 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
626 define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
627 ; CHECK-LABEL: cmtst8xi8:
628 ; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
629 %tmp3 = and <8 x i8> %A, %B
630 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
631 %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
635 define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
636 ; CHECK-LABEL: cmtst16xi8:
637 ; CHECK: cmtst {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
638 %tmp3 = and <16 x i8> %A, %B
639 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
640 %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
644 define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
645 ; CHECK-LABEL: cmtst4xi16:
646 ; CHECK: cmtst {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
647 %tmp3 = and <4 x i16> %A, %B
648 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
649 %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
653 define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
654 ; CHECK-LABEL: cmtst8xi16:
655 ; CHECK: cmtst {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
656 %tmp3 = and <8 x i16> %A, %B
657 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
658 %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
662 define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
663 ; CHECK-LABEL: cmtst2xi32:
664 ; CHECK: cmtst {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
665 %tmp3 = and <2 x i32> %A, %B
666 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
667 %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
671 define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
672 ; CHECK-LABEL: cmtst4xi32:
673 ; CHECK: cmtst {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
674 %tmp3 = and <4 x i32> %A, %B
675 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
676 %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
680 define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
681 ; CHECK-LABEL: cmtst2xi64:
682 ; CHECK: cmtst {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
683 %tmp3 = and <2 x i64> %A, %B
684 %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer
685 %tmp5 = sext <2 x i1> %tmp4 to <2 x i64>
691 define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
692 ; CHECK-LABEL: cmeqz8xi8:
693 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
694 %tmp3 = icmp eq <8 x i8> %A, zeroinitializer;
695 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
699 define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
700 ; CHECK-LABEL: cmeqz16xi8:
701 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
702 %tmp3 = icmp eq <16 x i8> %A, zeroinitializer;
703 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
707 define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
708 ; CHECK-LABEL: cmeqz4xi16:
709 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
710 %tmp3 = icmp eq <4 x i16> %A, zeroinitializer;
711 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
715 define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
716 ; CHECK-LABEL: cmeqz8xi16:
717 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
718 %tmp3 = icmp eq <8 x i16> %A, zeroinitializer;
719 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
723 define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
724 ; CHECK-LABEL: cmeqz2xi32:
725 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
726 %tmp3 = icmp eq <2 x i32> %A, zeroinitializer;
727 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
731 define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
732 ; CHECK-LABEL: cmeqz4xi32:
733 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
734 %tmp3 = icmp eq <4 x i32> %A, zeroinitializer;
735 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
739 define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
740 ; CHECK-LABEL: cmeqz2xi64:
741 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
742 %tmp3 = icmp eq <2 x i64> %A, zeroinitializer;
743 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
748 define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
749 ; CHECK-LABEL: cmgez8xi8:
750 ; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
751 %tmp3 = icmp sge <8 x i8> %A, zeroinitializer;
752 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
756 define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
757 ; CHECK-LABEL: cmgez16xi8:
758 ; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
759 %tmp3 = icmp sge <16 x i8> %A, zeroinitializer;
760 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
764 define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
765 ; CHECK-LABEL: cmgez4xi16:
766 ; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
767 %tmp3 = icmp sge <4 x i16> %A, zeroinitializer;
768 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
772 define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
773 ; CHECK-LABEL: cmgez8xi16:
774 ; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
775 %tmp3 = icmp sge <8 x i16> %A, zeroinitializer;
776 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
780 define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
781 ; CHECK-LABEL: cmgez2xi32:
782 ; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
783 %tmp3 = icmp sge <2 x i32> %A, zeroinitializer;
784 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
788 define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
789 ; CHECK-LABEL: cmgez4xi32:
790 ; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
791 %tmp3 = icmp sge <4 x i32> %A, zeroinitializer;
792 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
796 define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
797 ; CHECK-LABEL: cmgez2xi64:
798 ; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
799 %tmp3 = icmp sge <2 x i64> %A, zeroinitializer;
800 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
805 define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
806 ; CHECK-LABEL: cmgtz8xi8:
807 ; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
808 %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer;
809 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
813 define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
814 ; CHECK-LABEL: cmgtz16xi8:
815 ; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
816 %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer;
817 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
821 define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
822 ; CHECK-LABEL: cmgtz4xi16:
823 ; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
824 %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer;
825 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
829 define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
830 ; CHECK-LABEL: cmgtz8xi16:
831 ; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
832 %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer;
833 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
837 define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
838 ; CHECK-LABEL: cmgtz2xi32:
839 ; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
840 %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer;
841 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
845 define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
846 ; CHECK-LABEL: cmgtz4xi32:
847 ; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
848 %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer;
849 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
853 define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
854 ; CHECK-LABEL: cmgtz2xi64:
855 ; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
856 %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer;
857 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
861 define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
862 ; CHECK-LABEL: cmlez8xi8:
863 ; CHECK: cmle {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
864 %tmp3 = icmp sle <8 x i8> %A, zeroinitializer;
865 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
869 define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
870 ; CHECK-LABEL: cmlez16xi8:
871 ; CHECK: cmle {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
872 %tmp3 = icmp sle <16 x i8> %A, zeroinitializer;
873 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
877 define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
878 ; CHECK-LABEL: cmlez4xi16:
879 ; CHECK: cmle {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
880 %tmp3 = icmp sle <4 x i16> %A, zeroinitializer;
881 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
885 define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
886 ; CHECK-LABEL: cmlez8xi16:
887 ; CHECK: cmle {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
888 %tmp3 = icmp sle <8 x i16> %A, zeroinitializer;
889 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
893 define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
894 ; CHECK-LABEL: cmlez2xi32:
895 ; CHECK: cmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
896 %tmp3 = icmp sle <2 x i32> %A, zeroinitializer;
897 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
901 define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
902 ; CHECK-LABEL: cmlez4xi32:
903 ; CHECK: cmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
904 %tmp3 = icmp sle <4 x i32> %A, zeroinitializer;
905 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
909 define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
910 ; CHECK-LABEL: cmlez2xi64:
911 ; CHECK: cmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
912 %tmp3 = icmp sle <2 x i64> %A, zeroinitializer;
913 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
917 define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
918 ; CHECK-LABEL: cmltz8xi8:
919 ; CHECK: cmlt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
920 %tmp3 = icmp slt <8 x i8> %A, zeroinitializer;
921 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
925 define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
926 ; CHECK-LABEL: cmltz16xi8:
927 ; CHECK: cmlt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
928 %tmp3 = icmp slt <16 x i8> %A, zeroinitializer;
929 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
933 define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
934 ; CHECK-LABEL: cmltz4xi16:
935 ; CHECK: cmlt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
936 %tmp3 = icmp slt <4 x i16> %A, zeroinitializer;
937 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
941 define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
942 ; CHECK-LABEL: cmltz8xi16:
943 ; CHECK: cmlt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
944 %tmp3 = icmp slt <8 x i16> %A, zeroinitializer;
945 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
949 define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
950 ; CHECK-LABEL: cmltz2xi32:
951 ; CHECK: cmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
952 %tmp3 = icmp slt <2 x i32> %A, zeroinitializer;
953 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
957 define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
958 ; CHECK-LABEL: cmltz4xi32:
959 ; CHECK: cmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
960 %tmp3 = icmp slt <4 x i32> %A, zeroinitializer;
961 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
965 define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
966 ; CHECK-LABEL: cmltz2xi64:
967 ; CHECK: cmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
968 %tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
969 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
973 define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
974 ; CHECK-LABEL: cmneqz8xi8:
975 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
976 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
977 %tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
978 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
982 define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
983 ; CHECK-LABEL: cmneqz16xi8:
984 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
985 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
986 %tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
987 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
991 define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
992 ; CHECK-LABEL: cmneqz4xi16:
993 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
994 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
995 %tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
996 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1000 define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
1001 ; CHECK-LABEL: cmneqz8xi16:
1002 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
1003 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1004 %tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
1005 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1009 define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
1010 ; CHECK-LABEL: cmneqz2xi32:
1011 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
1012 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1013 %tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
1014 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1018 define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
1019 ; CHECK-LABEL: cmneqz4xi32:
1020 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
1021 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1022 %tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
1023 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1027 define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
1028 ; CHECK-LABEL: cmneqz2xi64:
1029 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
1030 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1031 %tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
1032 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1036 define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
1037 ; CHECK-LABEL: cmhsz8xi8:
1038 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1039 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1040 %tmp3 = icmp uge <8 x i8> %A, zeroinitializer;
1041 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1045 define <16 x i8> @cmhsz16xi8(<16 x i8> %A) {
1046 ; CHECK-LABEL: cmhsz16xi8:
1047 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1048 ; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1049 %tmp3 = icmp uge <16 x i8> %A, zeroinitializer;
1050 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1054 define <4 x i16> @cmhsz4xi16(<4 x i16> %A) {
1055 ; CHECK-LABEL: cmhsz4xi16:
1056 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1057 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1058 %tmp3 = icmp uge <4 x i16> %A, zeroinitializer;
1059 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1063 define <8 x i16> @cmhsz8xi16(<8 x i16> %A) {
1064 ; CHECK-LABEL: cmhsz8xi16:
1065 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1066 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
1067 %tmp3 = icmp uge <8 x i16> %A, zeroinitializer;
1068 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1072 define <2 x i32> @cmhsz2xi32(<2 x i32> %A) {
1073 ; CHECK-LABEL: cmhsz2xi32:
1074 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1075 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1076 %tmp3 = icmp uge <2 x i32> %A, zeroinitializer;
1077 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1081 define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
1082 ; CHECK-LABEL: cmhsz4xi32:
1083 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1084 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1085 %tmp3 = icmp uge <4 x i32> %A, zeroinitializer;
1086 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1090 define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
1091 ; CHECK-LABEL: cmhsz2xi64:
1092 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1093 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1094 %tmp3 = icmp uge <2 x i64> %A, zeroinitializer;
1095 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1100 define <8 x i8> @cmhiz8xi8(<8 x i8> %A) {
1101 ; CHECK-LABEL: cmhiz8xi8:
1102 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1103 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1104 %tmp3 = icmp ugt <8 x i8> %A, zeroinitializer;
1105 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1109 define <16 x i8> @cmhiz16xi8(<16 x i8> %A) {
1110 ; CHECK-LABEL: cmhiz16xi8:
1111 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1112 ; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1113 %tmp3 = icmp ugt <16 x i8> %A, zeroinitializer;
1114 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1118 define <4 x i16> @cmhiz4xi16(<4 x i16> %A) {
1119 ; CHECK-LABEL: cmhiz4xi16:
1120 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1121 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1122 %tmp3 = icmp ugt <4 x i16> %A, zeroinitializer;
1123 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1127 define <8 x i16> @cmhiz8xi16(<8 x i16> %A) {
1128 ; CHECK-LABEL: cmhiz8xi16:
1129 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1130 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
1131 %tmp3 = icmp ugt <8 x i16> %A, zeroinitializer;
1132 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1136 define <2 x i32> @cmhiz2xi32(<2 x i32> %A) {
1137 ; CHECK-LABEL: cmhiz2xi32:
1138 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1139 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1140 %tmp3 = icmp ugt <2 x i32> %A, zeroinitializer;
1141 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1145 define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
1146 ; CHECK-LABEL: cmhiz4xi32:
1147 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1148 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1149 %tmp3 = icmp ugt <4 x i32> %A, zeroinitializer;
1150 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1154 define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
1155 ; CHECK-LABEL: cmhiz2xi64:
1156 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1157 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1158 %tmp3 = icmp ugt <2 x i64> %A, zeroinitializer;
1159 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1163 define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
1164 ; CHECK-LABEL: cmlsz8xi8:
1165 ; Using registers other than v0, v1 are possible, but would be odd.
1166 ; LS implemented as HS, so check reversed operands.
1167 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1168 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
1169 %tmp3 = icmp ule <8 x i8> %A, zeroinitializer;
1170 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1174 define <16 x i8> @cmlsz16xi8(<16 x i8> %A) {
1175 ; CHECK-LABEL: cmlsz16xi8:
1176 ; Using registers other than v0, v1 are possible, but would be odd.
1177 ; LS implemented as HS, so check reversed operands.
1178 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1179 ; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
1180 %tmp3 = icmp ule <16 x i8> %A, zeroinitializer;
1181 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1185 define <4 x i16> @cmlsz4xi16(<4 x i16> %A) {
1186 ; CHECK-LABEL: cmlsz4xi16:
1187 ; Using registers other than v0, v1 are possible, but would be odd.
1188 ; LS implemented as HS, so check reversed operands.
1189 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1190 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
1191 %tmp3 = icmp ule <4 x i16> %A, zeroinitializer;
1192 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1196 define <8 x i16> @cmlsz8xi16(<8 x i16> %A) {
1197 ; CHECK-LABEL: cmlsz8xi16:
1198 ; Using registers other than v0, v1 are possible, but would be odd.
1199 ; LS implemented as HS, so check reversed operands.
1200 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1201 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
1202 %tmp3 = icmp ule <8 x i16> %A, zeroinitializer;
1203 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1207 define <2 x i32> @cmlsz2xi32(<2 x i32> %A) {
1208 ; CHECK-LABEL: cmlsz2xi32:
1209 ; Using registers other than v0, v1 are possible, but would be odd.
1210 ; LS implemented as HS, so check reversed operands.
1211 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1212 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
1213 %tmp3 = icmp ule <2 x i32> %A, zeroinitializer;
1214 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1218 define <4 x i32> @cmlsz4xi32(<4 x i32> %A) {
1219 ; CHECK-LABEL: cmlsz4xi32:
1220 ; Using registers other than v0, v1 are possible, but would be odd.
1221 ; LS implemented as HS, so check reversed operands.
1222 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1223 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
1224 %tmp3 = icmp ule <4 x i32> %A, zeroinitializer;
1225 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1229 define <2 x i64> @cmlsz2xi64(<2 x i64> %A) {
1230 ; CHECK-LABEL: cmlsz2xi64:
1231 ; Using registers other than v0, v1 are possible, but would be odd.
1232 ; LS implemented as HS, so check reversed operands.
1233 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1234 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
1235 %tmp3 = icmp ule <2 x i64> %A, zeroinitializer;
1236 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1240 define <8 x i8> @cmloz8xi8(<8 x i8> %A) {
1241 ; CHECK-LABEL: cmloz8xi8:
1242 ; Using registers other than v0, v1 are possible, but would be odd.
1243 ; LO implemented as HI, so check reversed operands.
1244 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1245 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, v1.8b, {{v[0-9]+}}.8b
1246 %tmp3 = icmp ult <8 x i8> %A, zeroinitializer;
1247 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1251 define <16 x i8> @cmloz16xi8(<16 x i8> %A) {
1252 ; CHECK-LABEL: cmloz16xi8:
1253 ; Using registers other than v0, v1 are possible, but would be odd.
1254 ; LO implemented as HI, so check reversed operands.
1255 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1256 ; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
1257 %tmp3 = icmp ult <16 x i8> %A, zeroinitializer;
1258 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1262 define <4 x i16> @cmloz4xi16(<4 x i16> %A) {
1263 ; CHECK-LABEL: cmloz4xi16:
1264 ; Using registers other than v0, v1 are possible, but would be odd.
1265 ; LO implemented as HI, so check reversed operands.
1266 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1267 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
1268 %tmp3 = icmp ult <4 x i16> %A, zeroinitializer;
1269 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1273 define <8 x i16> @cmloz8xi16(<8 x i16> %A) {
1274 ; CHECK-LABEL: cmloz8xi16:
1275 ; Using registers other than v0, v1 are possible, but would be odd.
1276 ; LO implemented as HI, so check reversed operands.
1277 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1278 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
1279 %tmp3 = icmp ult <8 x i16> %A, zeroinitializer;
1280 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1284 define <2 x i32> @cmloz2xi32(<2 x i32> %A) {
1285 ; CHECK-LABEL: cmloz2xi32:
1286 ; Using registers other than v0, v1 are possible, but would be odd.
1287 ; LO implemented as HI, so check reversed operands.
1288 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1289 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
1290 %tmp3 = icmp ult <2 x i32> %A, zeroinitializer;
1291 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1295 define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
1296 ; CHECK-LABEL: cmloz4xi32:
1297 ; Using registers other than v0, v1 are possible, but would be odd.
1298 ; LO implemented as HI, so check reversed operands.
1299 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1300 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
1301 %tmp3 = icmp ult <4 x i32> %A, zeroinitializer;
1302 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1306 define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
1307 ; CHECK-LABEL: cmloz2xi64:
1308 ; Using registers other than v0, v1 are possible, but would be odd.
1309 ; LO implemented as HI, so check reversed operands.
1310 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1311 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
1312 %tmp3 = icmp ult <2 x i64> %A, zeroinitializer;
1313 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1318 define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) {
1319 ; CHECK-LABEL: fcmoeq2xfloat:
1320 ; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1321 %tmp3 = fcmp oeq <2 x float> %A, %B
1322 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1326 define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) {
1327 ; CHECK-LABEL: fcmoeq4xfloat:
1328 ; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1329 %tmp3 = fcmp oeq <4 x float> %A, %B
1330 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1333 define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) {
1334 ; CHECK-LABEL: fcmoeq2xdouble:
1335 ; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1336 %tmp3 = fcmp oeq <2 x double> %A, %B
1337 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1341 define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) {
1342 ; CHECK-LABEL: fcmoge2xfloat:
1343 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1344 %tmp3 = fcmp oge <2 x float> %A, %B
1345 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1349 define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) {
1350 ; CHECK-LABEL: fcmoge4xfloat:
1351 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1352 %tmp3 = fcmp oge <4 x float> %A, %B
1353 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1356 define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) {
1357 ; CHECK-LABEL: fcmoge2xdouble:
1358 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1359 %tmp3 = fcmp oge <2 x double> %A, %B
1360 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1364 define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) {
1365 ; CHECK-LABEL: fcmogt2xfloat:
1366 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1367 %tmp3 = fcmp ogt <2 x float> %A, %B
1368 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1372 define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) {
1373 ; CHECK-LABEL: fcmogt4xfloat:
1374 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1375 %tmp3 = fcmp ogt <4 x float> %A, %B
1376 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1379 define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) {
1380 ; CHECK-LABEL: fcmogt2xdouble:
1381 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1382 %tmp3 = fcmp ogt <2 x double> %A, %B
1383 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1387 define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) {
1388 ; CHECK-LABEL: fcmole2xfloat:
1389 ; Using registers other than v0, v1 are possible, but would be odd.
1390 ; OLE implemented as OGE, so check reversed operands.
1391 ; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
1392 %tmp3 = fcmp ole <2 x float> %A, %B
1393 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1397 define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) {
1398 ; CHECK-LABEL: fcmole4xfloat:
1399 ; Using registers other than v0, v1 are possible, but would be odd.
1400 ; OLE implemented as OGE, so check reversed operands.
1401 ; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
1402 %tmp3 = fcmp ole <4 x float> %A, %B
1403 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1406 define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) {
1407 ; CHECK-LABEL: fcmole2xdouble:
1408 ; Using registers other than v0, v1 are possible, but would be odd.
1409 ; OLE implemented as OGE, so check reversed operands.
1410 ; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
1411 %tmp3 = fcmp ole <2 x double> %A, %B
1412 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1416 define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) {
1417 ; CHECK-LABEL: fcmolt2xfloat:
1418 ; Using registers other than v0, v1 are possible, but would be odd.
1419 ; OLE implemented as OGE, so check reversed operands.
1420 ; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1421 %tmp3 = fcmp olt <2 x float> %A, %B
1422 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1426 define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) {
1427 ; CHECK-LABEL: fcmolt4xfloat:
1428 ; Using registers other than v0, v1 are possible, but would be odd.
1429 ; OLE implemented as OGE, so check reversed operands.
1430 ; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1431 %tmp3 = fcmp olt <4 x float> %A, %B
1432 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1435 define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) {
1436 ; CHECK-LABEL: fcmolt2xdouble:
1437 ; Using registers other than v0, v1 are possible, but would be odd.
1438 ; OLE implemented as OGE, so check reversed operands.
1439 ; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1440 %tmp3 = fcmp olt <2 x double> %A, %B
1441 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1445 define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) {
1446 ; CHECK-LABEL: fcmone2xfloat:
1447 ; Using registers other than v0, v1 are possible, but would be odd.
1448 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1449 ; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1450 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1451 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1452 %tmp3 = fcmp one <2 x float> %A, %B
1453 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1457 define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) {
1458 ; CHECK-LABEL: fcmone4xfloat:
1459 ; Using registers other than v0, v1 are possible, but would be odd.
1460 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1461 ; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1462 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1463 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1464 %tmp3 = fcmp one <4 x float> %A, %B
1465 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1468 define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) {
1469 ; CHECK-LABEL: fcmone2xdouble:
1470 ; Using registers other than v0, v1 are possible, but would be odd.
1471 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1472 ; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1473 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1474 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1475 ; todo check reversed operands
1476 %tmp3 = fcmp one <2 x double> %A, %B
1477 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1482 define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) {
1483 ; CHECK-LABEL: fcmord2xfloat:
1484 ; Using registers other than v0, v1 are possible, but would be odd.
1485 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1486 ; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1487 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1488 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1489 %tmp3 = fcmp ord <2 x float> %A, %B
1490 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1495 define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) {
1496 ; CHECK-LABEL: fcmord4xfloat:
1497 ; Using registers other than v0, v1 are possible, but would be odd.
1498 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1499 ; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1500 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1501 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1502 %tmp3 = fcmp ord <4 x float> %A, %B
1503 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1507 define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) {
1508 ; CHECK-LABEL: fcmord2xdouble:
1509 ; Using registers other than v0, v1 are possible, but would be odd.
1510 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1511 ; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1512 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1513 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1514 %tmp3 = fcmp ord <2 x double> %A, %B
1515 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1520 define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) {
1521 ; CHECK-LABEL: fcmuno2xfloat:
1522 ; Using registers other than v0, v1 are possible, but would be odd.
1523 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1524 ; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1525 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1526 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1527 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1528 %tmp3 = fcmp uno <2 x float> %A, %B
1529 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1533 define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) {
1534 ; CHECK-LABEL: fcmuno4xfloat:
1535 ; Using registers other than v0, v1 are possible, but would be odd.
1536 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1537 ; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1538 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1539 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1540 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1541 %tmp3 = fcmp uno <4 x float> %A, %B
1542 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1546 define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) {
1547 ; CHECK-LABEL: fcmuno2xdouble:
1548 ; Using registers other than v0, v1 are possible, but would be odd.
1549 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1550 ; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1551 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1552 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1553 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1554 %tmp3 = fcmp uno <2 x double> %A, %B
1555 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1559 define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) {
1560 ; CHECK-LABEL: fcmueq2xfloat:
1561 ; Using registers other than v0, v1 are possible, but would be odd.
1562 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1563 ; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1564 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1565 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1566 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1567 %tmp3 = fcmp ueq <2 x float> %A, %B
1568 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1572 define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) {
1573 ; CHECK-LABEL: fcmueq4xfloat:
1574 ; Using registers other than v0, v1 are possible, but would be odd.
1575 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1576 ; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1577 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1578 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1579 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1580 %tmp3 = fcmp ueq <4 x float> %A, %B
1581 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1585 define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) {
1586 ; CHECK-LABEL: fcmueq2xdouble:
1587 ; Using registers other than v0, v1 are possible, but would be odd.
1588 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1589 ; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1590 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1591 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1592 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1593 %tmp3 = fcmp ueq <2 x double> %A, %B
1594 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1598 define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) {
1599 ; CHECK-LABEL: fcmuge2xfloat:
1600 ; Using registers other than v0, v1 are possible, but would be odd.
1601 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
1602 ; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1603 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1604 %tmp3 = fcmp uge <2 x float> %A, %B
1605 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1609 define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) {
1610 ; CHECK-LABEL: fcmuge4xfloat:
1611 ; Using registers other than v0, v1 are possible, but would be odd.
1612 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
1613 ; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1614 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1615 %tmp3 = fcmp uge <4 x float> %A, %B
1616 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1620 define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) {
1621 ; CHECK-LABEL: fcmuge2xdouble:
1622 ; Using registers other than v0, v1 are possible, but would be odd.
1623 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
1624 ; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1625 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1626 %tmp3 = fcmp uge <2 x double> %A, %B
1627 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1631 define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) {
1632 ; CHECK-LABEL: fcmugt2xfloat:
1633 ; Using registers other than v0, v1 are possible, but would be odd.
1634 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
1635 ; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
1636 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1637 %tmp3 = fcmp ugt <2 x float> %A, %B
1638 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1642 define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) {
1643 ; CHECK-LABEL: fcmugt4xfloat:
1644 ; Using registers other than v0, v1 are possible, but would be odd.
1645 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
1646 ; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
1647 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1648 %tmp3 = fcmp ugt <4 x float> %A, %B
1649 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1652 define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) {
1653 ; CHECK-LABEL: fcmugt2xdouble:
1654 ; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
1655 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1656 %tmp3 = fcmp ugt <2 x double> %A, %B
1657 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1661 define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) {
1662 ; CHECK-LABEL: fcmule2xfloat:
1663 ; Using registers other than v0, v1 are possible, but would be odd.
1664 ; ULE implemented as !OGT.
1665 ; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1666 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1667 %tmp3 = fcmp ule <2 x float> %A, %B
1668 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1672 define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) {
1673 ; CHECK-LABEL: fcmule4xfloat:
1674 ; Using registers other than v0, v1 are possible, but would be odd.
1675 ; ULE implemented as !OGT.
1676 ; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1677 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1678 %tmp3 = fcmp ule <4 x float> %A, %B
1679 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1682 define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) {
1683 ; CHECK-LABEL: fcmule2xdouble:
1684 ; Using registers other than v0, v1 are possible, but would be odd.
1685 ; ULE implemented as !OGT.
1686 ; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1687 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1688 %tmp3 = fcmp ule <2 x double> %A, %B
1689 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1693 define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) {
1694 ; CHECK-LABEL: fcmult2xfloat:
1695 ; Using registers other than v0, v1 are possible, but would be odd.
1696 ; ULT implemented as !OGE.
1697 ; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1698 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1699 %tmp3 = fcmp ult <2 x float> %A, %B
1700 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1704 define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) {
1705 ; CHECK-LABEL: fcmult4xfloat:
1706 ; Using registers other than v0, v1 are possible, but would be odd.
1707 ; ULT implemented as !OGE.
1708 ; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1709 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1710 %tmp3 = fcmp ult <4 x float> %A, %B
1711 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1714 define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) {
1715 ; CHECK-LABEL: fcmult2xdouble:
1716 ; Using registers other than v0, v1 are possible, but would be odd.
1717 ; ULT implemented as !OGE.
1718 ; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1719 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1720 %tmp3 = fcmp ult <2 x double> %A, %B
1721 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1725 define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) {
1726 ; CHECK-LABEL: fcmune2xfloat:
1727 ; Using registers other than v0, v1 are possible, but would be odd.
1729 ; CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s
1730 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1731 %tmp3 = fcmp une <2 x float> %A, %B
1732 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1736 define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) {
1737 ; CHECK-LABEL: fcmune4xfloat:
1738 ; Using registers other than v0, v1 are possible, but would be odd.
1740 ; CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s
1741 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1742 %tmp3 = fcmp une <4 x float> %A, %B
1743 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1746 define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
1747 ; CHECK-LABEL: fcmune2xdouble:
1748 ; Using registers other than v0, v1 are possible, but would be odd.
1750 ; CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d
1751 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1752 %tmp3 = fcmp une <2 x double> %A, %B
1753 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1757 define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) {
1758 ; CHECK-LABEL: fcmoeqz2xfloat:
1759 ; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1760 %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer
1761 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1765 define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) {
1766 ; CHECK-LABEL: fcmoeqz4xfloat:
1767 ; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1768 %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer
1769 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1772 define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) {
1773 ; CHECK-LABEL: fcmoeqz2xdouble:
1774 ; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1775 %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer
1776 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1781 define <2 x i32> @fcmogez2xfloat(<2 x float> %A) {
1782 ; CHECK-LABEL: fcmogez2xfloat:
1783 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1784 %tmp3 = fcmp oge <2 x float> %A, zeroinitializer
1785 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1789 define <4 x i32> @fcmogez4xfloat(<4 x float> %A) {
1790 ; CHECK-LABEL: fcmogez4xfloat:
1791 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1792 %tmp3 = fcmp oge <4 x float> %A, zeroinitializer
1793 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1796 define <2 x i64> @fcmogez2xdouble(<2 x double> %A) {
1797 ; CHECK-LABEL: fcmogez2xdouble:
1798 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1799 %tmp3 = fcmp oge <2 x double> %A, zeroinitializer
1800 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1804 define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) {
1805 ; CHECK-LABEL: fcmogtz2xfloat:
1806 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1807 %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer
1808 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1812 define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) {
1813 ; CHECK-LABEL: fcmogtz4xfloat:
1814 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1815 %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer
1816 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1819 define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) {
1820 ; CHECK-LABEL: fcmogtz2xdouble:
1821 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1822 %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer
1823 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1827 define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) {
1828 ; CHECK-LABEL: fcmoltz2xfloat:
1829 ; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1830 %tmp3 = fcmp olt <2 x float> %A, zeroinitializer
1831 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1835 define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) {
1836 ; CHECK-LABEL: fcmoltz4xfloat:
1837 ; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1838 %tmp3 = fcmp olt <4 x float> %A, zeroinitializer
1839 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1843 define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) {
1844 ; CHECK-LABEL: fcmoltz2xdouble:
1845 ; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1846 %tmp3 = fcmp olt <2 x double> %A, zeroinitializer
1847 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1851 define <2 x i32> @fcmolez2xfloat(<2 x float> %A) {
1852 ; CHECK-LABEL: fcmolez2xfloat:
1853 ; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1854 %tmp3 = fcmp ole <2 x float> %A, zeroinitializer
1855 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1859 define <4 x i32> @fcmolez4xfloat(<4 x float> %A) {
1860 ; CHECK-LABEL: fcmolez4xfloat:
1861 ; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1862 %tmp3 = fcmp ole <4 x float> %A, zeroinitializer
1863 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1867 define <2 x i64> @fcmolez2xdouble(<2 x double> %A) {
1868 ; CHECK-LABEL: fcmolez2xdouble:
1869 ; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1870 %tmp3 = fcmp ole <2 x double> %A, zeroinitializer
1871 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1875 define <2 x i32> @fcmonez2xfloat(<2 x float> %A) {
1876 ; CHECK-LABEL: fcmonez2xfloat:
1877 ; ONE with zero = OLT | OGT
1878 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1879 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1880 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1881 %tmp3 = fcmp one <2 x float> %A, zeroinitializer
1882 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1886 define <4 x i32> @fcmonez4xfloat(<4 x float> %A) {
1887 ; CHECK-LABEL: fcmonez4xfloat:
1888 ; ONE with zero = OLT | OGT
1889 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1890 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1891 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1892 %tmp3 = fcmp one <4 x float> %A, zeroinitializer
1893 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1896 define <2 x i64> @fcmonez2xdouble(<2 x double> %A) {
1897 ; CHECK-LABEL: fcmonez2xdouble:
1898 ; ONE with zero = OLT | OGT
1899 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1900 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1901 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1902 %tmp3 = fcmp one <2 x double> %A, zeroinitializer
1903 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1907 define <2 x i32> @fcmordz2xfloat(<2 x float> %A) {
1908 ; CHECK-LABEL: fcmordz2xfloat:
1909 ; ORD with zero = OLT | OGE
1910 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1911 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1912 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1913 %tmp3 = fcmp ord <2 x float> %A, zeroinitializer
1914 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1918 define <4 x i32> @fcmordz4xfloat(<4 x float> %A) {
1919 ; CHECK-LABEL: fcmordz4xfloat:
1920 ; ORD with zero = OLT | OGE
1921 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1922 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1923 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1924 %tmp3 = fcmp ord <4 x float> %A, zeroinitializer
1925 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1928 define <2 x i64> @fcmordz2xdouble(<2 x double> %A) {
1929 ; CHECK-LABEL: fcmordz2xdouble:
1930 ; ORD with zero = OLT | OGE
1931 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1932 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1933 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1934 %tmp3 = fcmp ord <2 x double> %A, zeroinitializer
1935 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1939 define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) {
1940 ; CHECK-LABEL: fcmueqz2xfloat:
1941 ; UEQ with zero = !ONE = !(OLT |OGT)
1942 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1943 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1944 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1945 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1946 %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer
1947 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1951 define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) {
1952 ; CHECK-LABEL: fcmueqz4xfloat:
1953 ; UEQ with zero = !ONE = !(OLT |OGT)
1954 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1955 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1956 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1957 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1958 %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer
1959 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1963 define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
1964 ; CHECK-LABEL: fcmueqz2xdouble:
1965 ; UEQ with zero = !ONE = !(OLT |OGT)
1966 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1967 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1968 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1969 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1970 %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer
1971 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1975 define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
1976 ; CHECK-LABEL: fcmugez2xfloat:
1977 ; UGE with zero = !OLT
1978 ; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1979 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1980 %tmp3 = fcmp uge <2 x float> %A, zeroinitializer
1981 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1985 define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
1986 ; CHECK-LABEL: fcmugez4xfloat:
1987 ; UGE with zero = !OLT
1988 ; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1989 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1990 %tmp3 = fcmp uge <4 x float> %A, zeroinitializer
1991 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1994 define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
1995 ; CHECK-LABEL: fcmugez2xdouble:
1996 ; UGE with zero = !OLT
1997 ; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1998 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1999 %tmp3 = fcmp uge <2 x double> %A, zeroinitializer
2000 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2004 define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
2005 ; CHECK-LABEL: fcmugtz2xfloat:
2006 ; UGT with zero = !OLE
2007 ; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2008 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2009 %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer
2010 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2014 define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
2015 ; CHECK-LABEL: fcmugtz4xfloat:
2016 ; UGT with zero = !OLE
2017 ; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2018 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2019 %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer
2020 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2023 define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
2024 ; CHECK-LABEL: fcmugtz2xdouble:
2025 ; UGT with zero = !OLE
2026 ; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2027 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2028 %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer
2029 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2033 define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
2034 ; CHECK-LABEL: fcmultz2xfloat:
2035 ; ULT with zero = !OGE
2036 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2037 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2038 %tmp3 = fcmp ult <2 x float> %A, zeroinitializer
2039 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2043 define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
2044 ; CHECK-LABEL: fcmultz4xfloat:
2045 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2046 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2047 %tmp3 = fcmp ult <4 x float> %A, zeroinitializer
2048 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2052 define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
2053 ; CHECK-LABEL: fcmultz2xdouble:
2054 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2055 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2056 %tmp3 = fcmp ult <2 x double> %A, zeroinitializer
2057 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2062 define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
2063 ; CHECK-LABEL: fcmulez2xfloat:
2064 ; ULE with zero = !OGT
2065 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2066 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2067 %tmp3 = fcmp ule <2 x float> %A, zeroinitializer
2068 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2072 define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
2073 ; CHECK-LABEL: fcmulez4xfloat:
2074 ; ULE with zero = !OGT
2075 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2076 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2077 %tmp3 = fcmp ule <4 x float> %A, zeroinitializer
2078 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2082 define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
2083 ; CHECK-LABEL: fcmulez2xdouble:
2084 ; ULE with zero = !OGT
2085 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2086 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2087 %tmp3 = fcmp ule <2 x double> %A, zeroinitializer
2088 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2092 define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
2093 ; CHECK-LABEL: fcmunez2xfloat:
2094 ; UNE with zero = !OEQ with zero
2095 ; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2096 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2097 %tmp3 = fcmp une <2 x float> %A, zeroinitializer
2098 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2102 define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
2103 ; CHECK-LABEL: fcmunez4xfloat:
2104 ; UNE with zero = !OEQ with zero
2105 ; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2106 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2107 %tmp3 = fcmp une <4 x float> %A, zeroinitializer
2108 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2111 define <2 x i64> @fcmunez2xdouble(<2 x double> %A) {
2112 ; CHECK-LABEL: fcmunez2xdouble:
2113 ; UNE with zero = !OEQ with zero
2114 ; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2115 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2116 %tmp3 = fcmp une <2 x double> %A, zeroinitializer
2117 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2122 define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) {
2123 ; CHECK-LABEL: fcmunoz2xfloat:
2124 ; UNO with zero = !ORD = !(OLT | OGE)
2125 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2126 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2127 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2128 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2129 %tmp3 = fcmp uno <2 x float> %A, zeroinitializer
2130 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2134 define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) {
2135 ; CHECK-LABEL: fcmunoz4xfloat:
2136 ; UNO with zero = !ORD = !(OLT | OGE)
2137 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2138 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2139 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2140 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2141 %tmp3 = fcmp uno <4 x float> %A, zeroinitializer
2142 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2146 define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) {
2147 ; CHECK-LABEL: fcmunoz2xdouble:
2148 ; UNO with zero = !ORD = !(OLT | OGE)
2149 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2150 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2151 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2152 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2153 %tmp3 = fcmp uno <2 x double> %A, zeroinitializer
2154 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>