1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
2 ; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
4 define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) {
5 ; CHECK-LABEL: cmeq8xi8:
6 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
7 %tmp3 = icmp eq <8 x i8> %A, %B;
8 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
12 define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) {
13 ; CHECK-LABEL: cmeq16xi8:
14 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
15 %tmp3 = icmp eq <16 x i8> %A, %B;
16 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
20 define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) {
21 ; CHECK-LABEL: cmeq4xi16:
22 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
23 %tmp3 = icmp eq <4 x i16> %A, %B;
24 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
28 define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) {
29 ; CHECK-LABEL: cmeq8xi16:
30 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
31 %tmp3 = icmp eq <8 x i16> %A, %B;
32 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
36 define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) {
37 ; CHECK-LABEL: cmeq2xi32:
38 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
39 %tmp3 = icmp eq <2 x i32> %A, %B;
40 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
44 define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) {
45 ; CHECK-LABEL: cmeq4xi32:
46 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
47 %tmp3 = icmp eq <4 x i32> %A, %B;
48 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
52 define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
53 ; CHECK-LABEL: cmeq2xi64:
54 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
55 %tmp3 = icmp eq <2 x i64> %A, %B;
56 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
60 define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
61 ; CHECK-LABEL: cmne8xi8:
62 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
63 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
64 %tmp3 = icmp ne <8 x i8> %A, %B;
65 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
69 define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
70 ; CHECK-LABEL: cmne16xi8:
71 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
72 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
73 %tmp3 = icmp ne <16 x i8> %A, %B;
74 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
78 define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
79 ; CHECK-LABEL: cmne4xi16:
80 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
81 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
82 %tmp3 = icmp ne <4 x i16> %A, %B;
83 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
87 define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
88 ; CHECK-LABEL: cmne8xi16:
89 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
90 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
91 %tmp3 = icmp ne <8 x i16> %A, %B;
92 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
96 define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
97 ; CHECK-LABEL: cmne2xi32:
98 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
99 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
100 %tmp3 = icmp ne <2 x i32> %A, %B;
101 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
105 define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
106 ; CHECK-LABEL: cmne4xi32:
107 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
108 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
109 %tmp3 = icmp ne <4 x i32> %A, %B;
110 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
114 define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
115 ; CHECK-LABEL: cmne2xi64:
116 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
117 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
118 %tmp3 = icmp ne <2 x i64> %A, %B;
119 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
123 define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) {
124 ; CHECK-LABEL: cmgt8xi8:
125 ; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
126 %tmp3 = icmp sgt <8 x i8> %A, %B;
127 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
131 define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) {
132 ; CHECK-LABEL: cmgt16xi8:
133 ; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
134 %tmp3 = icmp sgt <16 x i8> %A, %B;
135 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
139 define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) {
140 ; CHECK-LABEL: cmgt4xi16:
141 ; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
142 %tmp3 = icmp sgt <4 x i16> %A, %B;
143 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
147 define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) {
148 ; CHECK-LABEL: cmgt8xi16:
149 ; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
150 %tmp3 = icmp sgt <8 x i16> %A, %B;
151 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
155 define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) {
156 ; CHECK-LABEL: cmgt2xi32:
157 ; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
158 %tmp3 = icmp sgt <2 x i32> %A, %B;
159 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
163 define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) {
164 ; CHECK-LABEL: cmgt4xi32:
165 ; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
166 %tmp3 = icmp sgt <4 x i32> %A, %B;
167 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
171 define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) {
172 ; CHECK-LABEL: cmgt2xi64:
173 ; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
174 %tmp3 = icmp sgt <2 x i64> %A, %B;
175 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
179 define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) {
180 ; CHECK-LABEL: cmlt8xi8:
181 ; Using registers other than v0, v1 are possible, but would be odd.
182 ; LT implemented as GT, so check reversed operands.
183 ; CHECK: cmgt {{v[0-9]+}}.8b, v1.8b, v0.8b
184 %tmp3 = icmp slt <8 x i8> %A, %B;
185 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
189 define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) {
190 ; CHECK-LABEL: cmlt16xi8:
191 ; Using registers other than v0, v1 are possible, but would be odd.
192 ; LT implemented as GT, so check reversed operands.
193 ; CHECK: cmgt {{v[0-9]+}}.16b, v1.16b, v0.16b
194 %tmp3 = icmp slt <16 x i8> %A, %B;
195 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
199 define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) {
200 ; CHECK-LABEL: cmlt4xi16:
201 ; Using registers other than v0, v1 are possible, but would be odd.
202 ; LT implemented as GT, so check reversed operands.
203 ; CHECK: cmgt {{v[0-9]+}}.4h, v1.4h, v0.4h
204 %tmp3 = icmp slt <4 x i16> %A, %B;
205 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
209 define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) {
210 ; CHECK-LABEL: cmlt8xi16:
211 ; Using registers other than v0, v1 are possible, but would be odd.
212 ; LT implemented as GT, so check reversed operands.
213 ; CHECK: cmgt {{v[0-9]+}}.8h, v1.8h, v0.8h
214 %tmp3 = icmp slt <8 x i16> %A, %B;
215 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
219 define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) {
220 ; CHECK-LABEL: cmlt2xi32:
221 ; Using registers other than v0, v1 are possible, but would be odd.
222 ; LT implemented as GT, so check reversed operands.
223 ; CHECK: cmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
224 %tmp3 = icmp slt <2 x i32> %A, %B;
225 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
229 define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) {
230 ; CHECK-LABEL: cmlt4xi32:
231 ; Using registers other than v0, v1 are possible, but would be odd.
232 ; LT implemented as GT, so check reversed operands.
233 ; CHECK: cmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
234 %tmp3 = icmp slt <4 x i32> %A, %B;
235 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
239 define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) {
240 ; CHECK-LABEL: cmlt2xi64:
241 ; Using registers other than v0, v1 are possible, but would be odd.
242 ; LT implemented as GT, so check reversed operands.
243 ; CHECK: cmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
244 %tmp3 = icmp slt <2 x i64> %A, %B;
245 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
249 define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) {
250 ; CHECK-LABEL: cmge8xi8:
251 ; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
252 %tmp3 = icmp sge <8 x i8> %A, %B;
253 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
257 define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) {
258 ; CHECK-LABEL: cmge16xi8:
259 ; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
260 %tmp3 = icmp sge <16 x i8> %A, %B;
261 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
265 define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) {
266 ; CHECK-LABEL: cmge4xi16:
267 ; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
268 %tmp3 = icmp sge <4 x i16> %A, %B;
269 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
273 define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) {
274 ; CHECK-LABEL: cmge8xi16:
275 ; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
276 %tmp3 = icmp sge <8 x i16> %A, %B;
277 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
281 define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) {
282 ; CHECK-LABEL: cmge2xi32:
283 ; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
284 %tmp3 = icmp sge <2 x i32> %A, %B;
285 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
289 define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) {
290 ; CHECK-LABEL: cmge4xi32:
291 ; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
292 %tmp3 = icmp sge <4 x i32> %A, %B;
293 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
297 define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) {
298 ; CHECK-LABEL: cmge2xi64:
299 ; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
300 %tmp3 = icmp sge <2 x i64> %A, %B;
301 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
305 define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) {
306 ; CHECK-LABEL: cmle8xi8:
307 ; Using registers other than v0, v1 are possible, but would be odd.
308 ; LE implemented as GE, so check reversed operands.
309 ; CHECK: cmge {{v[0-9]+}}.8b, v1.8b, v0.8b
310 %tmp3 = icmp sle <8 x i8> %A, %B;
311 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
315 define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) {
316 ; CHECK-LABEL: cmle16xi8:
317 ; Using registers other than v0, v1 are possible, but would be odd.
318 ; LE implemented as GE, so check reversed operands.
319 ; CHECK: cmge {{v[0-9]+}}.16b, v1.16b, v0.16b
320 %tmp3 = icmp sle <16 x i8> %A, %B;
321 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
325 define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) {
326 ; CHECK-LABEL: cmle4xi16:
327 ; Using registers other than v0, v1 are possible, but would be odd.
328 ; LE implemented as GE, so check reversed operands.
329 ; CHECK: cmge {{v[0-9]+}}.4h, v1.4h, v0.4h
330 %tmp3 = icmp sle <4 x i16> %A, %B;
331 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
335 define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) {
336 ; CHECK-LABEL: cmle8xi16:
337 ; Using registers other than v0, v1 are possible, but would be odd.
338 ; LE implemented as GE, so check reversed operands.
339 ; CHECK: cmge {{v[0-9]+}}.8h, v1.8h, v0.8h
340 %tmp3 = icmp sle <8 x i16> %A, %B;
341 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
345 define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) {
346 ; CHECK-LABEL: cmle2xi32:
347 ; Using registers other than v0, v1 are possible, but would be odd.
348 ; LE implemented as GE, so check reversed operands.
349 ; CHECK: cmge {{v[0-9]+}}.2s, v1.2s, v0.2s
350 %tmp3 = icmp sle <2 x i32> %A, %B;
351 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
355 define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) {
356 ; CHECK-LABEL: cmle4xi32:
357 ; Using registers other than v0, v1 are possible, but would be odd.
358 ; LE implemented as GE, so check reversed operands.
359 ; CHECK: cmge {{v[0-9]+}}.4s, v1.4s, v0.4s
360 %tmp3 = icmp sle <4 x i32> %A, %B;
361 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
365 define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) {
366 ; CHECK-LABEL: cmle2xi64:
367 ; Using registers other than v0, v1 are possible, but would be odd.
368 ; LE implemented as GE, so check reversed operands.
369 ; CHECK: cmge {{v[0-9]+}}.2d, v1.2d, v0.2d
370 %tmp3 = icmp sle <2 x i64> %A, %B;
371 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
375 define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) {
376 ; CHECK-LABEL: cmhi8xi8:
377 ; CHECK: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
378 %tmp3 = icmp ugt <8 x i8> %A, %B;
379 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
383 define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) {
384 ; CHECK-LABEL: cmhi16xi8:
385 ; CHECK: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
386 %tmp3 = icmp ugt <16 x i8> %A, %B;
387 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
391 define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) {
392 ; CHECK-LABEL: cmhi4xi16:
393 ; CHECK: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
394 %tmp3 = icmp ugt <4 x i16> %A, %B;
395 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
399 define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) {
400 ; CHECK-LABEL: cmhi8xi16:
401 ; CHECK: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
402 %tmp3 = icmp ugt <8 x i16> %A, %B;
403 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
407 define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) {
408 ; CHECK-LABEL: cmhi2xi32:
409 ; CHECK: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
410 %tmp3 = icmp ugt <2 x i32> %A, %B;
411 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
415 define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) {
416 ; CHECK-LABEL: cmhi4xi32:
417 ; CHECK: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
418 %tmp3 = icmp ugt <4 x i32> %A, %B;
419 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
423 define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) {
424 ; CHECK-LABEL: cmhi2xi64:
425 ; CHECK: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
426 %tmp3 = icmp ugt <2 x i64> %A, %B;
427 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
431 define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) {
432 ; CHECK-LABEL: cmlo8xi8:
433 ; Using registers other than v0, v1 are possible, but would be odd.
434 ; LO implemented as HI, so check reversed operands.
435 ; CHECK: cmhi {{v[0-9]+}}.8b, v1.8b, v0.8b
436 %tmp3 = icmp ult <8 x i8> %A, %B;
437 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
441 define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) {
442 ; CHECK-LABEL: cmlo16xi8:
443 ; Using registers other than v0, v1 are possible, but would be odd.
444 ; LO implemented as HI, so check reversed operands.
445 ; CHECK: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
446 %tmp3 = icmp ult <16 x i8> %A, %B;
447 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
451 define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) {
452 ; CHECK-LABEL: cmlo4xi16:
453 ; Using registers other than v0, v1 are possible, but would be odd.
454 ; LO implemented as HI, so check reversed operands.
455 ; CHECK: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
456 %tmp3 = icmp ult <4 x i16> %A, %B;
457 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
461 define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) {
462 ; CHECK-LABEL: cmlo8xi16:
463 ; Using registers other than v0, v1 are possible, but would be odd.
464 ; LO implemented as HI, so check reversed operands.
465 ; CHECK: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
466 %tmp3 = icmp ult <8 x i16> %A, %B;
467 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
471 define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) {
472 ; CHECK-LABEL: cmlo2xi32:
473 ; Using registers other than v0, v1 are possible, but would be odd.
474 ; LO implemented as HI, so check reversed operands.
475 ; CHECK: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
476 %tmp3 = icmp ult <2 x i32> %A, %B;
477 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
481 define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) {
482 ; CHECK-LABEL: cmlo4xi32:
483 ; Using registers other than v0, v1 are possible, but would be odd.
484 ; LO implemented as HI, so check reversed operands.
485 ; CHECK: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
486 %tmp3 = icmp ult <4 x i32> %A, %B;
487 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
491 define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) {
492 ; CHECK-LABEL: cmlo2xi64:
493 ; Using registers other than v0, v1 are possible, but would be odd.
494 ; LO implemented as HI, so check reversed operands.
495 ; CHECK: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
496 %tmp3 = icmp ult <2 x i64> %A, %B;
497 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
501 define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) {
502 ; CHECK-LABEL: cmhs8xi8:
503 ; CHECK: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
504 %tmp3 = icmp uge <8 x i8> %A, %B;
505 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
509 define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) {
510 ; CHECK-LABEL: cmhs16xi8:
511 ; CHECK: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
512 %tmp3 = icmp uge <16 x i8> %A, %B;
513 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
517 define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) {
518 ; CHECK-LABEL: cmhs4xi16:
519 ; CHECK: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
520 %tmp3 = icmp uge <4 x i16> %A, %B;
521 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
525 define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) {
526 ; CHECK-LABEL: cmhs8xi16:
527 ; CHECK: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
528 %tmp3 = icmp uge <8 x i16> %A, %B;
529 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
533 define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) {
534 ; CHECK-LABEL: cmhs2xi32:
535 ; CHECK: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
536 %tmp3 = icmp uge <2 x i32> %A, %B;
537 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
541 define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) {
542 ; CHECK-LABEL: cmhs4xi32:
543 ; CHECK: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
544 %tmp3 = icmp uge <4 x i32> %A, %B;
545 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
549 define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) {
550 ; CHECK-LABEL: cmhs2xi64:
551 ; CHECK: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
552 %tmp3 = icmp uge <2 x i64> %A, %B;
553 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
557 define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) {
558 ; CHECK-LABEL: cmls8xi8:
559 ; Using registers other than v0, v1 are possible, but would be odd.
560 ; LS implemented as HS, so check reversed operands.
561 ; CHECK: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
562 %tmp3 = icmp ule <8 x i8> %A, %B;
563 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
567 define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) {
568 ; CHECK-LABEL: cmls16xi8:
569 ; Using registers other than v0, v1 are possible, but would be odd.
570 ; LS implemented as HS, so check reversed operands.
571 ; CHECK: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
572 %tmp3 = icmp ule <16 x i8> %A, %B;
573 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
577 define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) {
578 ; CHECK-LABEL: cmls4xi16:
579 ; Using registers other than v0, v1 are possible, but would be odd.
580 ; LS implemented as HS, so check reversed operands.
581 ; CHECK: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
582 %tmp3 = icmp ule <4 x i16> %A, %B;
583 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
587 define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) {
588 ; CHECK-LABEL: cmls8xi16:
589 ; Using registers other than v0, v1 are possible, but would be odd.
590 ; LS implemented as HS, so check reversed operands.
591 ; CHECK: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
592 %tmp3 = icmp ule <8 x i16> %A, %B;
593 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
597 define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) {
598 ; CHECK-LABEL: cmls2xi32:
599 ; Using registers other than v0, v1 are possible, but would be odd.
600 ; LS implemented as HS, so check reversed operands.
601 ; CHECK: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
602 %tmp3 = icmp ule <2 x i32> %A, %B;
603 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
607 define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) {
608 ; CHECK-LABEL: cmls4xi32:
609 ; Using registers other than v0, v1 are possible, but would be odd.
610 ; LS implemented as HS, so check reversed operands.
611 ; CHECK: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
612 %tmp3 = icmp ule <4 x i32> %A, %B;
613 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
617 define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) {
618 ; CHECK-LABEL: cmls2xi64:
619 ; Using registers other than v0, v1 are possible, but would be odd.
620 ; LS implemented as HS, so check reversed operands.
621 ; CHECK: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
622 %tmp3 = icmp ule <2 x i64> %A, %B;
623 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
627 define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
628 ; CHECK-LABEL: cmtst8xi8:
629 ; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
630 %tmp3 = and <8 x i8> %A, %B
631 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
632 %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
636 define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
637 ; CHECK-LABEL: cmtst16xi8:
638 ; CHECK: cmtst {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
639 %tmp3 = and <16 x i8> %A, %B
640 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
641 %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
645 define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
646 ; CHECK-LABEL: cmtst4xi16:
647 ; CHECK: cmtst {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
648 %tmp3 = and <4 x i16> %A, %B
649 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
650 %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
654 define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
655 ; CHECK-LABEL: cmtst8xi16:
656 ; CHECK: cmtst {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
657 %tmp3 = and <8 x i16> %A, %B
658 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
659 %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
663 define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
664 ; CHECK-LABEL: cmtst2xi32:
665 ; CHECK: cmtst {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
666 %tmp3 = and <2 x i32> %A, %B
667 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
668 %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
672 define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
673 ; CHECK-LABEL: cmtst4xi32:
674 ; CHECK: cmtst {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
675 %tmp3 = and <4 x i32> %A, %B
676 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
677 %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
681 define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
682 ; CHECK-LABEL: cmtst2xi64:
683 ; CHECK: cmtst {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
684 %tmp3 = and <2 x i64> %A, %B
685 %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer
686 %tmp5 = sext <2 x i1> %tmp4 to <2 x i64>
692 define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
693 ; CHECK-LABEL: cmeqz8xi8:
694 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
695 %tmp3 = icmp eq <8 x i8> %A, zeroinitializer;
696 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
700 define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
701 ; CHECK-LABEL: cmeqz16xi8:
702 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
703 %tmp3 = icmp eq <16 x i8> %A, zeroinitializer;
704 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
708 define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
709 ; CHECK-LABEL: cmeqz4xi16:
710 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
711 %tmp3 = icmp eq <4 x i16> %A, zeroinitializer;
712 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
716 define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
717 ; CHECK-LABEL: cmeqz8xi16:
718 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
719 %tmp3 = icmp eq <8 x i16> %A, zeroinitializer;
720 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
724 define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
725 ; CHECK-LABEL: cmeqz2xi32:
726 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
727 %tmp3 = icmp eq <2 x i32> %A, zeroinitializer;
728 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
732 define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
733 ; CHECK-LABEL: cmeqz4xi32:
734 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
735 %tmp3 = icmp eq <4 x i32> %A, zeroinitializer;
736 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
740 define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
741 ; CHECK-LABEL: cmeqz2xi64:
742 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
743 %tmp3 = icmp eq <2 x i64> %A, zeroinitializer;
744 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
749 define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
750 ; CHECK-LABEL: cmgez8xi8:
751 ; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
752 %tmp3 = icmp sge <8 x i8> %A, zeroinitializer;
753 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
757 define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
758 ; CHECK-LABEL: cmgez16xi8:
759 ; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
760 %tmp3 = icmp sge <16 x i8> %A, zeroinitializer;
761 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
765 define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
766 ; CHECK-LABEL: cmgez4xi16:
767 ; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
768 %tmp3 = icmp sge <4 x i16> %A, zeroinitializer;
769 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
773 define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
774 ; CHECK-LABEL: cmgez8xi16:
775 ; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
776 %tmp3 = icmp sge <8 x i16> %A, zeroinitializer;
777 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
781 define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
782 ; CHECK-LABEL: cmgez2xi32:
783 ; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
784 %tmp3 = icmp sge <2 x i32> %A, zeroinitializer;
785 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
789 define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
790 ; CHECK-LABEL: cmgez4xi32:
791 ; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
792 %tmp3 = icmp sge <4 x i32> %A, zeroinitializer;
793 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
797 define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
798 ; CHECK-LABEL: cmgez2xi64:
799 ; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
800 %tmp3 = icmp sge <2 x i64> %A, zeroinitializer;
801 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
806 define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
807 ; CHECK-LABEL: cmgtz8xi8:
808 ; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
809 %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer;
810 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
814 define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
815 ; CHECK-LABEL: cmgtz16xi8:
816 ; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
817 %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer;
818 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
822 define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
823 ; CHECK-LABEL: cmgtz4xi16:
824 ; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
825 %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer;
826 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
830 define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
831 ; CHECK-LABEL: cmgtz8xi16:
832 ; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
833 %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer;
834 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
838 define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
839 ; CHECK-LABEL: cmgtz2xi32:
840 ; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
841 %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer;
842 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
846 define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
847 ; CHECK-LABEL: cmgtz4xi32:
848 ; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
849 %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer;
850 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
854 define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
855 ; CHECK-LABEL: cmgtz2xi64:
856 ; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
857 %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer;
858 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
862 define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
863 ; CHECK-LABEL: cmlez8xi8:
864 ; CHECK: cmle {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
865 %tmp3 = icmp sle <8 x i8> %A, zeroinitializer;
866 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
870 define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
871 ; CHECK-LABEL: cmlez16xi8:
872 ; CHECK: cmle {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
873 %tmp3 = icmp sle <16 x i8> %A, zeroinitializer;
874 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
878 define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
879 ; CHECK-LABEL: cmlez4xi16:
880 ; CHECK: cmle {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
881 %tmp3 = icmp sle <4 x i16> %A, zeroinitializer;
882 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
886 define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
887 ; CHECK-LABEL: cmlez8xi16:
888 ; CHECK: cmle {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
889 %tmp3 = icmp sle <8 x i16> %A, zeroinitializer;
890 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
894 define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
895 ; CHECK-LABEL: cmlez2xi32:
896 ; CHECK: cmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
897 %tmp3 = icmp sle <2 x i32> %A, zeroinitializer;
898 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
902 define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
903 ; CHECK-LABEL: cmlez4xi32:
904 ; CHECK: cmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
905 %tmp3 = icmp sle <4 x i32> %A, zeroinitializer;
906 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
910 define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
911 ; CHECK-LABEL: cmlez2xi64:
912 ; CHECK: cmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
913 %tmp3 = icmp sle <2 x i64> %A, zeroinitializer;
914 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
918 define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
919 ; CHECK-LABEL: cmltz8xi8:
920 ; CHECK: cmlt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
921 %tmp3 = icmp slt <8 x i8> %A, zeroinitializer;
922 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
926 define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
927 ; CHECK-LABEL: cmltz16xi8:
928 ; CHECK: cmlt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
929 %tmp3 = icmp slt <16 x i8> %A, zeroinitializer;
930 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
934 define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
935 ; CHECK-LABEL: cmltz4xi16:
936 ; CHECK: cmlt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
937 %tmp3 = icmp slt <4 x i16> %A, zeroinitializer;
938 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
942 define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
943 ; CHECK-LABEL: cmltz8xi16:
944 ; CHECK: cmlt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
945 %tmp3 = icmp slt <8 x i16> %A, zeroinitializer;
946 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
950 define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
951 ; CHECK-LABEL: cmltz2xi32:
952 ; CHECK: cmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
953 %tmp3 = icmp slt <2 x i32> %A, zeroinitializer;
954 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
958 define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
959 ; CHECK-LABEL: cmltz4xi32:
960 ; CHECK: cmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
961 %tmp3 = icmp slt <4 x i32> %A, zeroinitializer;
962 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
966 define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
967 ; CHECK-LABEL: cmltz2xi64:
968 ; CHECK: cmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
969 %tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
970 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
974 define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
975 ; CHECK-LABEL: cmneqz8xi8:
976 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
977 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
978 %tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
979 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
983 define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
984 ; CHECK-LABEL: cmneqz16xi8:
985 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
986 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
987 %tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
988 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
992 define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
993 ; CHECK-LABEL: cmneqz4xi16:
994 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
995 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
996 %tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
997 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1001 define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
1002 ; CHECK-LABEL: cmneqz8xi16:
1003 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
1004 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1005 %tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
1006 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1010 define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
1011 ; CHECK-LABEL: cmneqz2xi32:
1012 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
1013 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1014 %tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
1015 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1019 define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
1020 ; CHECK-LABEL: cmneqz4xi32:
1021 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
1022 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1023 %tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
1024 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1028 define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
1029 ; CHECK-LABEL: cmneqz2xi64:
1030 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}}
1031 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1032 %tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
1033 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1037 define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
1038 ; CHECK-LABEL: cmhsz8xi8:
1039 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1040 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1041 %tmp3 = icmp uge <8 x i8> %A, zeroinitializer;
1042 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1046 define <16 x i8> @cmhsz16xi8(<16 x i8> %A) {
1047 ; CHECK-LABEL: cmhsz16xi8:
1048 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1049 ; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1050 %tmp3 = icmp uge <16 x i8> %A, zeroinitializer;
1051 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1055 define <4 x i16> @cmhsz4xi16(<4 x i16> %A) {
1056 ; CHECK-LABEL: cmhsz4xi16:
1057 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1058 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1059 %tmp3 = icmp uge <4 x i16> %A, zeroinitializer;
1060 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1064 define <8 x i16> @cmhsz8xi16(<8 x i16> %A) {
1065 ; CHECK-LABEL: cmhsz8xi16:
1066 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1067 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
1068 %tmp3 = icmp uge <8 x i16> %A, zeroinitializer;
1069 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1073 define <2 x i32> @cmhsz2xi32(<2 x i32> %A) {
1074 ; CHECK-LABEL: cmhsz2xi32:
1075 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1076 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1077 %tmp3 = icmp uge <2 x i32> %A, zeroinitializer;
1078 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1082 define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
1083 ; CHECK-LABEL: cmhsz4xi32:
1084 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1085 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1086 %tmp3 = icmp uge <4 x i32> %A, zeroinitializer;
1087 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1091 define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
1092 ; CHECK-LABEL: cmhsz2xi64:
1093 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1094 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1095 %tmp3 = icmp uge <2 x i64> %A, zeroinitializer;
1096 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1101 define <8 x i8> @cmhiz8xi8(<8 x i8> %A) {
1102 ; CHECK-LABEL: cmhiz8xi8:
1103 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1104 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1105 %tmp3 = icmp ugt <8 x i8> %A, zeroinitializer;
1106 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1110 define <16 x i8> @cmhiz16xi8(<16 x i8> %A) {
1111 ; CHECK-LABEL: cmhiz16xi8:
1112 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1113 ; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1114 %tmp3 = icmp ugt <16 x i8> %A, zeroinitializer;
1115 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1119 define <4 x i16> @cmhiz4xi16(<4 x i16> %A) {
1120 ; CHECK-LABEL: cmhiz4xi16:
1121 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1122 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1123 %tmp3 = icmp ugt <4 x i16> %A, zeroinitializer;
1124 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1128 define <8 x i16> @cmhiz8xi16(<8 x i16> %A) {
1129 ; CHECK-LABEL: cmhiz8xi16:
1130 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1131 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
1132 %tmp3 = icmp ugt <8 x i16> %A, zeroinitializer;
1133 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1137 define <2 x i32> @cmhiz2xi32(<2 x i32> %A) {
1138 ; CHECK-LABEL: cmhiz2xi32:
1139 ; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}}
1140 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1141 %tmp3 = icmp ugt <2 x i32> %A, zeroinitializer;
1142 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1146 define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
1147 ; CHECK-LABEL: cmhiz4xi32:
1148 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1149 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1150 %tmp3 = icmp ugt <4 x i32> %A, zeroinitializer;
1151 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1155 define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
1156 ; CHECK-LABEL: cmhiz2xi64:
1157 ; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}}
1158 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1159 %tmp3 = icmp ugt <2 x i64> %A, zeroinitializer;
1160 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1164 define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
1165 ; CHECK-LABEL: cmlsz8xi8:
1166 ; Using registers other than v0, v1 are possible, but would be odd.
1167 ; LS implemented as HS, so check reversed operands.
1168 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1169 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
1170 %tmp3 = icmp ule <8 x i8> %A, zeroinitializer;
1171 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1175 define <16 x i8> @cmlsz16xi8(<16 x i8> %A) {
1176 ; CHECK-LABEL: cmlsz16xi8:
1177 ; Using registers other than v0, v1 are possible, but would be odd.
1178 ; LS implemented as HS, so check reversed operands.
1179 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1180 ; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
1181 %tmp3 = icmp ule <16 x i8> %A, zeroinitializer;
1182 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1186 define <4 x i16> @cmlsz4xi16(<4 x i16> %A) {
1187 ; CHECK-LABEL: cmlsz4xi16:
1188 ; Using registers other than v0, v1 are possible, but would be odd.
1189 ; LS implemented as HS, so check reversed operands.
1190 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1191 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
1192 %tmp3 = icmp ule <4 x i16> %A, zeroinitializer;
1193 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1197 define <8 x i16> @cmlsz8xi16(<8 x i16> %A) {
1198 ; CHECK-LABEL: cmlsz8xi16:
1199 ; Using registers other than v0, v1 are possible, but would be odd.
1200 ; LS implemented as HS, so check reversed operands.
1201 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1202 ; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
1203 %tmp3 = icmp ule <8 x i16> %A, zeroinitializer;
1204 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1208 define <2 x i32> @cmlsz2xi32(<2 x i32> %A) {
1209 ; CHECK-LABEL: cmlsz2xi32:
1210 ; Using registers other than v0, v1 are possible, but would be odd.
1211 ; LS implemented as HS, so check reversed operands.
1212 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1213 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
1214 %tmp3 = icmp ule <2 x i32> %A, zeroinitializer;
1215 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1219 define <4 x i32> @cmlsz4xi32(<4 x i32> %A) {
1220 ; CHECK-LABEL: cmlsz4xi32:
1221 ; Using registers other than v0, v1 are possible, but would be odd.
1222 ; LS implemented as HS, so check reversed operands.
1223 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1224 ; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
1225 %tmp3 = icmp ule <4 x i32> %A, zeroinitializer;
1226 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1230 define <2 x i64> @cmlsz2xi64(<2 x i64> %A) {
1231 ; CHECK-LABEL: cmlsz2xi64:
1232 ; Using registers other than v0, v1 are possible, but would be odd.
1233 ; LS implemented as HS, so check reversed operands.
1234 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1235 ; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
1236 %tmp3 = icmp ule <2 x i64> %A, zeroinitializer;
1237 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1241 define <8 x i8> @cmloz8xi8(<8 x i8> %A) {
1242 ; CHECK-LABEL: cmloz8xi8:
1243 ; Using registers other than v0, v1 are possible, but would be odd.
1244 ; LO implemented as HI, so check reversed operands.
1245 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1246 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, v1.8b, {{v[0-9]+}}.8b
1247 %tmp3 = icmp ult <8 x i8> %A, zeroinitializer;
1248 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
1252 define <16 x i8> @cmloz16xi8(<16 x i8> %A) {
1253 ; CHECK-LABEL: cmloz16xi8:
1254 ; Using registers other than v0, v1 are possible, but would be odd.
1255 ; LO implemented as HI, so check reversed operands.
1256 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1257 ; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
1258 %tmp3 = icmp ult <16 x i8> %A, zeroinitializer;
1259 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
1263 define <4 x i16> @cmloz4xi16(<4 x i16> %A) {
1264 ; CHECK-LABEL: cmloz4xi16:
1265 ; Using registers other than v0, v1 are possible, but would be odd.
1266 ; LO implemented as HI, so check reversed operands.
1267 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1268 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
1269 %tmp3 = icmp ult <4 x i16> %A, zeroinitializer;
1270 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
1274 define <8 x i16> @cmloz8xi16(<8 x i16> %A) {
1275 ; CHECK-LABEL: cmloz8xi16:
1276 ; Using registers other than v0, v1 are possible, but would be odd.
1277 ; LO implemented as HI, so check reversed operands.
1278 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1279 ; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
1280 %tmp3 = icmp ult <8 x i16> %A, zeroinitializer;
1281 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
1285 define <2 x i32> @cmloz2xi32(<2 x i32> %A) {
1286 ; CHECK-LABEL: cmloz2xi32:
1287 ; Using registers other than v0, v1 are possible, but would be odd.
1288 ; LO implemented as HI, so check reversed operands.
1289 ; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}}
1290 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
1291 %tmp3 = icmp ult <2 x i32> %A, zeroinitializer;
1292 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1296 define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
1297 ; CHECK-LABEL: cmloz4xi32:
1298 ; Using registers other than v0, v1 are possible, but would be odd.
1299 ; LO implemented as HI, so check reversed operands.
1300 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1301 ; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
1302 %tmp3 = icmp ult <4 x i32> %A, zeroinitializer;
1303 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1307 define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
1308 ; CHECK-LABEL: cmloz2xi64:
1309 ; Using registers other than v0, v1 are possible, but would be odd.
1310 ; LO implemented as HI, so check reversed operands.
1311 ; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}}
1312 ; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
1313 %tmp3 = icmp ult <2 x i64> %A, zeroinitializer;
1314 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1319 define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) {
1320 ; CHECK-LABEL: fcmoeq2xfloat:
1321 ; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1322 %tmp3 = fcmp oeq <2 x float> %A, %B
1323 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1327 define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) {
1328 ; CHECK-LABEL: fcmoeq4xfloat:
1329 ; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1330 %tmp3 = fcmp oeq <4 x float> %A, %B
1331 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1334 define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) {
1335 ; CHECK-LABEL: fcmoeq2xdouble:
1336 ; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1337 %tmp3 = fcmp oeq <2 x double> %A, %B
1338 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1342 define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) {
1343 ; CHECK-LABEL: fcmoge2xfloat:
1344 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1345 %tmp3 = fcmp oge <2 x float> %A, %B
1346 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1350 define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) {
1351 ; CHECK-LABEL: fcmoge4xfloat:
1352 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1353 %tmp3 = fcmp oge <4 x float> %A, %B
1354 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1357 define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) {
1358 ; CHECK-LABEL: fcmoge2xdouble:
1359 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1360 %tmp3 = fcmp oge <2 x double> %A, %B
1361 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1365 define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) {
1366 ; CHECK-LABEL: fcmogt2xfloat:
1367 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
1368 %tmp3 = fcmp ogt <2 x float> %A, %B
1369 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1373 define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) {
1374 ; CHECK-LABEL: fcmogt4xfloat:
1375 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1376 %tmp3 = fcmp ogt <4 x float> %A, %B
1377 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1380 define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) {
1381 ; CHECK-LABEL: fcmogt2xdouble:
1382 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1383 %tmp3 = fcmp ogt <2 x double> %A, %B
1384 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1388 define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) {
1389 ; CHECK-LABEL: fcmole2xfloat:
1390 ; Using registers other than v0, v1 are possible, but would be odd.
1391 ; OLE implemented as OGE, so check reversed operands.
1392 ; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
1393 %tmp3 = fcmp ole <2 x float> %A, %B
1394 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1398 define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) {
1399 ; CHECK-LABEL: fcmole4xfloat:
1400 ; Using registers other than v0, v1 are possible, but would be odd.
1401 ; OLE implemented as OGE, so check reversed operands.
1402 ; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
1403 %tmp3 = fcmp ole <4 x float> %A, %B
1404 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1407 define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) {
1408 ; CHECK-LABEL: fcmole2xdouble:
1409 ; Using registers other than v0, v1 are possible, but would be odd.
1410 ; OLE implemented as OGE, so check reversed operands.
1411 ; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
1412 %tmp3 = fcmp ole <2 x double> %A, %B
1413 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1417 define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) {
1418 ; CHECK-LABEL: fcmolt2xfloat:
1419 ; Using registers other than v0, v1 are possible, but would be odd.
1420 ; OLE implemented as OGE, so check reversed operands.
1421 ; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1422 %tmp3 = fcmp olt <2 x float> %A, %B
1423 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1427 define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) {
1428 ; CHECK-LABEL: fcmolt4xfloat:
1429 ; Using registers other than v0, v1 are possible, but would be odd.
1430 ; OLE implemented as OGE, so check reversed operands.
1431 ; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1432 %tmp3 = fcmp olt <4 x float> %A, %B
1433 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1436 define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) {
1437 ; CHECK-LABEL: fcmolt2xdouble:
1438 ; Using registers other than v0, v1 are possible, but would be odd.
1439 ; OLE implemented as OGE, so check reversed operands.
1440 ; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1441 %tmp3 = fcmp olt <2 x double> %A, %B
1442 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1446 define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) {
1447 ; CHECK-LABEL: fcmone2xfloat:
1448 ; Using registers other than v0, v1 are possible, but would be odd.
1449 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1450 ; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1451 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1452 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1453 %tmp3 = fcmp one <2 x float> %A, %B
1454 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1458 define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) {
1459 ; CHECK-LABEL: fcmone4xfloat:
1460 ; Using registers other than v0, v1 are possible, but would be odd.
1461 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1462 ; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1463 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1464 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1465 %tmp3 = fcmp one <4 x float> %A, %B
1466 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1469 define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) {
1470 ; CHECK-LABEL: fcmone2xdouble:
1471 ; Using registers other than v0, v1 are possible, but would be odd.
1472 ; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
1473 ; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1474 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1475 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1476 ; todo check reversed operands
1477 %tmp3 = fcmp one <2 x double> %A, %B
1478 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1483 define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) {
1484 ; CHECK-LABEL: fcmord2xfloat:
1485 ; Using registers other than v0, v1 are possible, but would be odd.
1486 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1487 ; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1488 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1489 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1490 %tmp3 = fcmp ord <2 x float> %A, %B
1491 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1496 define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) {
1497 ; CHECK-LABEL: fcmord4xfloat:
1498 ; Using registers other than v0, v1 are possible, but would be odd.
1499 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1500 ; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1501 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1502 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1503 %tmp3 = fcmp ord <4 x float> %A, %B
1504 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1508 define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) {
1509 ; CHECK-LABEL: fcmord2xdouble:
1510 ; Using registers other than v0, v1 are possible, but would be odd.
1511 ; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
1512 ; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1513 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1514 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1515 %tmp3 = fcmp ord <2 x double> %A, %B
1516 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1521 define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) {
1522 ; CHECK-LABEL: fcmuno2xfloat:
1523 ; Using registers other than v0, v1 are possible, but would be odd.
1524 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1525 ; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1526 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1527 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1528 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1529 %tmp3 = fcmp uno <2 x float> %A, %B
1530 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1534 define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) {
1535 ; CHECK-LABEL: fcmuno4xfloat:
1536 ; Using registers other than v0, v1 are possible, but would be odd.
1537 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1538 ; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1539 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1540 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1541 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1542 %tmp3 = fcmp uno <4 x float> %A, %B
1543 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1547 define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) {
1548 ; CHECK-LABEL: fcmuno2xdouble:
1549 ; Using registers other than v0, v1 are possible, but would be odd.
1550 ; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
1551 ; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1552 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1553 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1554 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1555 %tmp3 = fcmp uno <2 x double> %A, %B
1556 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1560 define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) {
1561 ; CHECK-LABEL: fcmueq2xfloat:
1562 ; Using registers other than v0, v1 are possible, but would be odd.
1563 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1564 ; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1565 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1566 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1567 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1568 %tmp3 = fcmp ueq <2 x float> %A, %B
1569 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1573 define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) {
1574 ; CHECK-LABEL: fcmueq4xfloat:
1575 ; Using registers other than v0, v1 are possible, but would be odd.
1576 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1577 ; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1578 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1579 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1580 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1581 %tmp3 = fcmp ueq <4 x float> %A, %B
1582 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1586 define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) {
1587 ; CHECK-LABEL: fcmueq2xdouble:
1588 ; Using registers other than v0, v1 are possible, but would be odd.
1589 ; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
1590 ; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1591 ; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1592 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1593 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1594 %tmp3 = fcmp ueq <2 x double> %A, %B
1595 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1599 define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) {
1600 ; CHECK-LABEL: fcmuge2xfloat:
1601 ; Using registers other than v0, v1 are possible, but would be odd.
1602 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
1603 ; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
1604 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1605 %tmp3 = fcmp uge <2 x float> %A, %B
1606 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1610 define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) {
1611 ; CHECK-LABEL: fcmuge4xfloat:
1612 ; Using registers other than v0, v1 are possible, but would be odd.
1613 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
1614 ; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
1615 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1616 %tmp3 = fcmp uge <4 x float> %A, %B
1617 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1621 define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) {
1622 ; CHECK-LABEL: fcmuge2xdouble:
1623 ; Using registers other than v0, v1 are possible, but would be odd.
1624 ; UGE = ULE with swapped operands, ULE implemented as !OGT.
1625 ; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
1626 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1627 %tmp3 = fcmp uge <2 x double> %A, %B
1628 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1632 define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) {
1633 ; CHECK-LABEL: fcmugt2xfloat:
1634 ; Using registers other than v0, v1 are possible, but would be odd.
1635 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
1636 ; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
1637 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1638 %tmp3 = fcmp ugt <2 x float> %A, %B
1639 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1643 define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) {
1644 ; CHECK-LABEL: fcmugt4xfloat:
1645 ; Using registers other than v0, v1 are possible, but would be odd.
1646 ; UGT = ULT with swapped operands, ULT implemented as !OGE.
1647 ; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
1648 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1649 %tmp3 = fcmp ugt <4 x float> %A, %B
1650 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1653 define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) {
1654 ; CHECK-LABEL: fcmugt2xdouble:
1655 ; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
1656 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1657 %tmp3 = fcmp ugt <2 x double> %A, %B
1658 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1662 define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) {
1663 ; CHECK-LABEL: fcmule2xfloat:
1664 ; Using registers other than v0, v1 are possible, but would be odd.
1665 ; ULE implemented as !OGT.
1666 ; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
1667 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1668 %tmp3 = fcmp ule <2 x float> %A, %B
1669 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1673 define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) {
1674 ; CHECK-LABEL: fcmule4xfloat:
1675 ; Using registers other than v0, v1 are possible, but would be odd.
1676 ; ULE implemented as !OGT.
1677 ; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
1678 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1679 %tmp3 = fcmp ule <4 x float> %A, %B
1680 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1683 define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) {
1684 ; CHECK-LABEL: fcmule2xdouble:
1685 ; Using registers other than v0, v1 are possible, but would be odd.
1686 ; ULE implemented as !OGT.
1687 ; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
1688 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1689 %tmp3 = fcmp ule <2 x double> %A, %B
1690 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1694 define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) {
1695 ; CHECK-LABEL: fcmult2xfloat:
1696 ; Using registers other than v0, v1 are possible, but would be odd.
1697 ; ULT implemented as !OGE.
1698 ; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
1699 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1700 %tmp3 = fcmp ult <2 x float> %A, %B
1701 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1705 define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) {
1706 ; CHECK-LABEL: fcmult4xfloat:
1707 ; Using registers other than v0, v1 are possible, but would be odd.
1708 ; ULT implemented as !OGE.
1709 ; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
1710 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1711 %tmp3 = fcmp ult <4 x float> %A, %B
1712 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1715 define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) {
1716 ; CHECK-LABEL: fcmult2xdouble:
1717 ; Using registers other than v0, v1 are possible, but would be odd.
1718 ; ULT implemented as !OGE.
1719 ; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
1720 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1721 %tmp3 = fcmp ult <2 x double> %A, %B
1722 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1726 define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) {
1727 ; CHECK-LABEL: fcmune2xfloat:
1728 ; Using registers other than v0, v1 are possible, but would be odd.
1730 ; CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s
1731 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1732 %tmp3 = fcmp une <2 x float> %A, %B
1733 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1737 define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) {
1738 ; CHECK-LABEL: fcmune4xfloat:
1739 ; Using registers other than v0, v1 are possible, but would be odd.
1741 ; CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s
1742 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1743 %tmp3 = fcmp une <4 x float> %A, %B
1744 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1747 define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
1748 ; CHECK-LABEL: fcmune2xdouble:
1749 ; Using registers other than v0, v1 are possible, but would be odd.
1751 ; CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d
1752 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1753 %tmp3 = fcmp une <2 x double> %A, %B
1754 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1758 define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) {
1759 ; CHECK-LABEL: fcmoeqz2xfloat:
1760 ; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1761 %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer
1762 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1766 define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) {
1767 ; CHECK-LABEL: fcmoeqz4xfloat:
1768 ; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1769 %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer
1770 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1773 define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) {
1774 ; CHECK-LABEL: fcmoeqz2xdouble:
1775 ; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1776 %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer
1777 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1782 define <2 x i32> @fcmogez2xfloat(<2 x float> %A) {
1783 ; CHECK-LABEL: fcmogez2xfloat:
1784 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1785 %tmp3 = fcmp oge <2 x float> %A, zeroinitializer
1786 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1790 define <4 x i32> @fcmogez4xfloat(<4 x float> %A) {
1791 ; CHECK-LABEL: fcmogez4xfloat:
1792 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1793 %tmp3 = fcmp oge <4 x float> %A, zeroinitializer
1794 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1797 define <2 x i64> @fcmogez2xdouble(<2 x double> %A) {
1798 ; CHECK-LABEL: fcmogez2xdouble:
1799 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1800 %tmp3 = fcmp oge <2 x double> %A, zeroinitializer
1801 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1805 define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) {
1806 ; CHECK-LABEL: fcmogtz2xfloat:
1807 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1808 %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer
1809 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1813 define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) {
1814 ; CHECK-LABEL: fcmogtz4xfloat:
1815 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1816 %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer
1817 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1820 define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) {
1821 ; CHECK-LABEL: fcmogtz2xdouble:
1822 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1823 %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer
1824 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1828 define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) {
1829 ; CHECK-LABEL: fcmoltz2xfloat:
1830 ; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1831 %tmp3 = fcmp olt <2 x float> %A, zeroinitializer
1832 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1836 define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) {
1837 ; CHECK-LABEL: fcmoltz4xfloat:
1838 ; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1839 %tmp3 = fcmp olt <4 x float> %A, zeroinitializer
1840 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1844 define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) {
1845 ; CHECK-LABEL: fcmoltz2xdouble:
1846 ; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1847 %tmp3 = fcmp olt <2 x double> %A, zeroinitializer
1848 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1852 define <2 x i32> @fcmolez2xfloat(<2 x float> %A) {
1853 ; CHECK-LABEL: fcmolez2xfloat:
1854 ; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1855 %tmp3 = fcmp ole <2 x float> %A, zeroinitializer
1856 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1860 define <4 x i32> @fcmolez4xfloat(<4 x float> %A) {
1861 ; CHECK-LABEL: fcmolez4xfloat:
1862 ; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1863 %tmp3 = fcmp ole <4 x float> %A, zeroinitializer
1864 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1868 define <2 x i64> @fcmolez2xdouble(<2 x double> %A) {
1869 ; CHECK-LABEL: fcmolez2xdouble:
1870 ; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1871 %tmp3 = fcmp ole <2 x double> %A, zeroinitializer
1872 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1876 define <2 x i32> @fcmonez2xfloat(<2 x float> %A) {
1877 ; CHECK-LABEL: fcmonez2xfloat:
1878 ; ONE with zero = OLT | OGT
1879 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1880 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1881 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1882 %tmp3 = fcmp one <2 x float> %A, zeroinitializer
1883 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1887 define <4 x i32> @fcmonez4xfloat(<4 x float> %A) {
1888 ; CHECK-LABEL: fcmonez4xfloat:
1889 ; ONE with zero = OLT | OGT
1890 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1891 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1892 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1893 %tmp3 = fcmp one <4 x float> %A, zeroinitializer
1894 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1897 define <2 x i64> @fcmonez2xdouble(<2 x double> %A) {
1898 ; CHECK-LABEL: fcmonez2xdouble:
1899 ; ONE with zero = OLT | OGT
1900 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1901 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1902 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1903 %tmp3 = fcmp one <2 x double> %A, zeroinitializer
1904 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1908 define <2 x i32> @fcmordz2xfloat(<2 x float> %A) {
1909 ; CHECK-LABEL: fcmordz2xfloat:
1910 ; ORD with zero = OLT | OGE
1911 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1912 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1913 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1914 %tmp3 = fcmp ord <2 x float> %A, zeroinitializer
1915 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1919 define <4 x i32> @fcmordz4xfloat(<4 x float> %A) {
1920 ; CHECK-LABEL: fcmordz4xfloat:
1921 ; ORD with zero = OLT | OGE
1922 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1923 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1924 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1925 %tmp3 = fcmp ord <4 x float> %A, zeroinitializer
1926 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1929 define <2 x i64> @fcmordz2xdouble(<2 x double> %A) {
1930 ; CHECK-LABEL: fcmordz2xdouble:
1931 ; ORD with zero = OLT | OGE
1932 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1933 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1934 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1935 %tmp3 = fcmp ord <2 x double> %A, zeroinitializer
1936 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1940 define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) {
1941 ; CHECK-LABEL: fcmueqz2xfloat:
1942 ; UEQ with zero = !ONE = !(OLT |OGT)
1943 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1944 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1945 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1946 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1947 %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer
1948 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1952 define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) {
1953 ; CHECK-LABEL: fcmueqz4xfloat:
1954 ; UEQ with zero = !ONE = !(OLT |OGT)
1955 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1956 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1957 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1958 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1959 %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer
1960 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1964 define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
1965 ; CHECK-LABEL: fcmueqz2xdouble:
1966 ; UEQ with zero = !ONE = !(OLT |OGT)
1967 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1968 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1969 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1970 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1971 %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer
1972 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
1976 define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
1977 ; CHECK-LABEL: fcmugez2xfloat:
1978 ; UGE with zero = !OLT
1979 ; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
1980 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1981 %tmp3 = fcmp uge <2 x float> %A, zeroinitializer
1982 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
1986 define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
1987 ; CHECK-LABEL: fcmugez4xfloat:
1988 ; UGE with zero = !OLT
1989 ; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
1990 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1991 %tmp3 = fcmp uge <4 x float> %A, zeroinitializer
1992 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
1995 define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
1996 ; CHECK-LABEL: fcmugez2xdouble:
1997 ; UGE with zero = !OLT
1998 ; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
1999 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2000 %tmp3 = fcmp uge <2 x double> %A, zeroinitializer
2001 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2005 define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
2006 ; CHECK-LABEL: fcmugtz2xfloat:
2007 ; UGT with zero = !OLE
2008 ; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2009 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2010 %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer
2011 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2015 define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
2016 ; CHECK-LABEL: fcmugtz4xfloat:
2017 ; UGT with zero = !OLE
2018 ; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2019 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2020 %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer
2021 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2024 define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
2025 ; CHECK-LABEL: fcmugtz2xdouble:
2026 ; UGT with zero = !OLE
2027 ; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2028 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2029 %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer
2030 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2034 define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
2035 ; CHECK-LABEL: fcmultz2xfloat:
2036 ; ULT with zero = !OGE
2037 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2038 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2039 %tmp3 = fcmp ult <2 x float> %A, zeroinitializer
2040 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2044 define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
2045 ; CHECK-LABEL: fcmultz4xfloat:
2046 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2047 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2048 %tmp3 = fcmp ult <4 x float> %A, zeroinitializer
2049 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2053 define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
2054 ; CHECK-LABEL: fcmultz2xdouble:
2055 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2056 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2057 %tmp3 = fcmp ult <2 x double> %A, zeroinitializer
2058 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2063 define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
2064 ; CHECK-LABEL: fcmulez2xfloat:
2065 ; ULE with zero = !OGT
2066 ; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2067 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2068 %tmp3 = fcmp ule <2 x float> %A, zeroinitializer
2069 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2073 define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
2074 ; CHECK-LABEL: fcmulez4xfloat:
2075 ; ULE with zero = !OGT
2076 ; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2077 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2078 %tmp3 = fcmp ule <4 x float> %A, zeroinitializer
2079 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2083 define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
2084 ; CHECK-LABEL: fcmulez2xdouble:
2085 ; ULE with zero = !OGT
2086 ; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2087 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2088 %tmp3 = fcmp ule <2 x double> %A, zeroinitializer
2089 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2093 define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
2094 ; CHECK-LABEL: fcmunez2xfloat:
2095 ; UNE with zero = !OEQ with zero
2096 ; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2097 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2098 %tmp3 = fcmp une <2 x float> %A, zeroinitializer
2099 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2103 define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
2104 ; CHECK-LABEL: fcmunez4xfloat:
2105 ; UNE with zero = !OEQ with zero
2106 ; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2107 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2108 %tmp3 = fcmp une <4 x float> %A, zeroinitializer
2109 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2112 define <2 x i64> @fcmunez2xdouble(<2 x double> %A) {
2113 ; CHECK-LABEL: fcmunez2xdouble:
2114 ; UNE with zero = !OEQ with zero
2115 ; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2116 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2117 %tmp3 = fcmp une <2 x double> %A, zeroinitializer
2118 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
2123 define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) {
2124 ; CHECK-LABEL: fcmunoz2xfloat:
2125 ; UNO with zero = !ORD = !(OLT | OGE)
2126 ; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2127 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}}
2128 ; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2129 ; CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
2130 %tmp3 = fcmp uno <2 x float> %A, zeroinitializer
2131 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
2135 define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) {
2136 ; CHECK-LABEL: fcmunoz4xfloat:
2137 ; UNO with zero = !ORD = !(OLT | OGE)
2138 ; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2139 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}}
2140 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2141 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2142 %tmp3 = fcmp uno <4 x float> %A, zeroinitializer
2143 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
2147 define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) {
2148 ; CHECK-LABEL: fcmunoz2xdouble:
2149 ; UNO with zero = !ORD = !(OLT | OGE)
2150 ; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2151 ; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}}
2152 ; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2153 ; CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2154 %tmp3 = fcmp uno <2 x double> %A, zeroinitializer
2155 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>