1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
4 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
5 ;CHECK: ins {{v[0-9]+}}.b[15], {{w[0-9]+}}
6 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
10 define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
11 ;CHECK: ins {{v[0-9]+}}.h[6], {{w[0-9]+}}
12 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
16 define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
17 ;CHECK: ins {{v[0-9]+}}.s[2], {{w[0-9]+}}
18 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
22 define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
23 ;CHECK: ins {{v[0-9]+}}.d[1], {{x[0-9]+}}
24 %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
28 define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
29 ;CHECK: ins {{v[0-9]+}}.b[5], {{w[0-9]+}}
30 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
34 define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
35 ;CHECK: ins {{v[0-9]+}}.h[3], {{w[0-9]+}}
36 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
40 define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
41 ;CHECK: ins {{v[0-9]+}}.s[1], {{w[0-9]+}}
42 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
46 define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
47 ;CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
48 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
49 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
53 define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
54 ;CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
55 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
56 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
60 define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
61 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
62 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
63 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
67 define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
68 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
69 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
70 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
74 define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
75 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
76 %tmp3 = extractelement <4 x float> %tmp1, i32 2
77 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
81 define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
82 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
83 %tmp3 = extractelement <2 x double> %tmp1, i32 0
84 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
85 ret <2 x double> %tmp4
88 define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
89 ;CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
90 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
91 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
95 define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
96 ;CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
97 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
98 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
102 define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
103 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
104 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
105 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
109 define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
110 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
111 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
112 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
116 define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
117 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
118 %tmp3 = extractelement <2 x float> %tmp1, i32 1
119 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
120 ret <4 x float> %tmp4
123 define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
124 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
125 %tmp3 = extractelement <1 x double> %tmp1, i32 0
126 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
127 ret <2 x double> %tmp4
130 define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
131 ;CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
132 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
133 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
137 define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
138 ;CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
139 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
140 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
144 define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
145 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
146 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
147 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
151 define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
152 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
153 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
154 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
158 define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
159 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
160 %tmp3 = extractelement <4 x float> %tmp1, i32 2
161 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
162 ret <2 x float> %tmp4
165 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
166 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
167 %tmp3 = extractelement <2 x double> %tmp1, i32 0
168 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
169 ret <1 x double> %tmp4
172 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
173 ;CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
174 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
175 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
179 define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
180 ;CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
181 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
182 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
186 define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
187 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
188 %tmp3 = extractelement <2 x i32> %tmp1, i32 0
189 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
193 define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
194 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
195 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
196 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
200 define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
201 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
202 %tmp3 = extractelement <2 x float> %tmp1, i32 0
203 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
204 ret <2 x float> %tmp4
207 define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
208 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
209 %tmp3 = extractelement <1 x double> %tmp1, i32 0
210 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
211 ret <1 x double> %tmp4
214 define i32 @umovw16b(<16 x i8> %tmp1) {
215 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
216 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
217 %tmp4 = zext i8 %tmp3 to i32
221 define i32 @umovw8h(<8 x i16> %tmp1) {
222 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
223 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
224 %tmp4 = zext i16 %tmp3 to i32
228 define i32 @umovw4s(<4 x i32> %tmp1) {
229 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.s[2]
230 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
234 define i64 @umovx2d(<2 x i64> %tmp1) {
235 ;CHECK: umov {{x[0-9]+}}, {{v[0-9]+}}.d[0]
236 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
240 define i32 @umovw8b(<8 x i8> %tmp1) {
241 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.b[7]
242 %tmp3 = extractelement <8 x i8> %tmp1, i32 7
243 %tmp4 = zext i8 %tmp3 to i32
247 define i32 @umovw4h(<4 x i16> %tmp1) {
248 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
249 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
250 %tmp4 = zext i16 %tmp3 to i32
254 define i32 @umovw2s(<2 x i32> %tmp1) {
255 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.s[1]
256 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
260 define i64 @umovx1d(<1 x i64> %tmp1) {
261 ;CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
262 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
266 define i32 @smovw16b(<16 x i8> %tmp1) {
267 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
268 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
269 %tmp4 = sext i8 %tmp3 to i32
270 %tmp5 = add i32 5, %tmp4
274 define i32 @smovw8h(<8 x i16> %tmp1) {
275 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
276 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
277 %tmp4 = sext i16 %tmp3 to i32
278 %tmp5 = add i32 5, %tmp4
282 define i32 @smovx16b(<16 x i8> %tmp1) {
283 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[8]
284 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
285 %tmp4 = sext i8 %tmp3 to i32
289 define i32 @smovx8h(<8 x i16> %tmp1) {
290 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
291 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
292 %tmp4 = sext i16 %tmp3 to i32
296 define i64 @smovx4s(<4 x i32> %tmp1) {
297 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[2]
298 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
299 %tmp4 = sext i32 %tmp3 to i64
303 define i32 @smovw8b(<8 x i8> %tmp1) {
304 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[4]
305 %tmp3 = extractelement <8 x i8> %tmp1, i32 4
306 %tmp4 = sext i8 %tmp3 to i32
307 %tmp5 = add i32 5, %tmp4
311 define i32 @smovw4h(<4 x i16> %tmp1) {
312 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
313 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
314 %tmp4 = sext i16 %tmp3 to i32
315 %tmp5 = add i32 5, %tmp4
319 define i32 @smovx8b(<8 x i8> %tmp1) {
320 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[6]
321 %tmp3 = extractelement <8 x i8> %tmp1, i32 6
322 %tmp4 = sext i8 %tmp3 to i32
326 define i32 @smovx4h(<4 x i16> %tmp1) {
327 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
328 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
329 %tmp4 = sext i16 %tmp3 to i32
333 define i64 @smovx2s(<2 x i32> %tmp1) {
334 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[1]
335 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
336 %tmp4 = sext i32 %tmp3 to i64
340 define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {
341 ;CHECK: ins {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
342 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>
343 ret <8 x i8> %vset_lane
346 define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {
347 ;CHECK: ins {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
348 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15>
349 ret <16 x i8> %vset_lane
352 define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {
353 ;CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
354 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
355 ret <8 x i8> %vset_lane
358 define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
359 ;CHECK: ins {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
360 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
361 ret <16 x i8> %vset_lane
364 define <8 x i8> @test_vdup_n_u8(i8 %v1) #0 {
365 ;CHECK: dup {{v[0-9]+}}.8b, {{w[0-9]+}}
366 %vecinit.i = insertelement <8 x i8> undef, i8 %v1, i32 0
367 %vecinit1.i = insertelement <8 x i8> %vecinit.i, i8 %v1, i32 1
368 %vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 %v1, i32 2
369 %vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 %v1, i32 3
370 %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 %v1, i32 4
371 %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 %v1, i32 5
372 %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 %v1, i32 6
373 %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 %v1, i32 7
374 ret <8 x i8> %vecinit7.i
377 define <4 x i16> @test_vdup_n_u16(i16 %v1) #0 {
378 ;CHECK: dup {{v[0-9]+}}.4h, {{w[0-9]+}}
379 %vecinit.i = insertelement <4 x i16> undef, i16 %v1, i32 0
380 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %v1, i32 1
381 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %v1, i32 2
382 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %v1, i32 3
383 ret <4 x i16> %vecinit3.i
386 define <2 x i32> @test_vdup_n_u32(i32 %v1) #0 {
387 ;CHECK: dup {{v[0-9]+}}.2s, {{w[0-9]+}}
388 %vecinit.i = insertelement <2 x i32> undef, i32 %v1, i32 0
389 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %v1, i32 1
390 ret <2 x i32> %vecinit1.i
393 define <1 x i64> @test_vdup_n_u64(i64 %v1) #0 {
394 ;CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
395 %vecinit.i = insertelement <1 x i64> undef, i64 %v1, i32 0
396 ret <1 x i64> %vecinit.i
399 define <16 x i8> @test_vdupq_n_u8(i8 %v1) #0 {
400 ;CHECK: dup {{v[0-9]+}}.16b, {{w[0-9]+}}
401 %vecinit.i = insertelement <16 x i8> undef, i8 %v1, i32 0
402 %vecinit1.i = insertelement <16 x i8> %vecinit.i, i8 %v1, i32 1
403 %vecinit2.i = insertelement <16 x i8> %vecinit1.i, i8 %v1, i32 2
404 %vecinit3.i = insertelement <16 x i8> %vecinit2.i, i8 %v1, i32 3
405 %vecinit4.i = insertelement <16 x i8> %vecinit3.i, i8 %v1, i32 4
406 %vecinit5.i = insertelement <16 x i8> %vecinit4.i, i8 %v1, i32 5
407 %vecinit6.i = insertelement <16 x i8> %vecinit5.i, i8 %v1, i32 6
408 %vecinit7.i = insertelement <16 x i8> %vecinit6.i, i8 %v1, i32 7
409 %vecinit8.i = insertelement <16 x i8> %vecinit7.i, i8 %v1, i32 8
410 %vecinit9.i = insertelement <16 x i8> %vecinit8.i, i8 %v1, i32 9
411 %vecinit10.i = insertelement <16 x i8> %vecinit9.i, i8 %v1, i32 10
412 %vecinit11.i = insertelement <16 x i8> %vecinit10.i, i8 %v1, i32 11
413 %vecinit12.i = insertelement <16 x i8> %vecinit11.i, i8 %v1, i32 12
414 %vecinit13.i = insertelement <16 x i8> %vecinit12.i, i8 %v1, i32 13
415 %vecinit14.i = insertelement <16 x i8> %vecinit13.i, i8 %v1, i32 14
416 %vecinit15.i = insertelement <16 x i8> %vecinit14.i, i8 %v1, i32 15
417 ret <16 x i8> %vecinit15.i
420 define <8 x i16> @test_vdupq_n_u16(i16 %v1) #0 {
421 ;CHECK: dup {{v[0-9]+}}.8h, {{w[0-9]+}}
422 %vecinit.i = insertelement <8 x i16> undef, i16 %v1, i32 0
423 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %v1, i32 1
424 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %v1, i32 2
425 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %v1, i32 3
426 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %v1, i32 4
427 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %v1, i32 5
428 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %v1, i32 6
429 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %v1, i32 7
430 ret <8 x i16> %vecinit7.i
433 define <4 x i32> @test_vdupq_n_u32(i32 %v1) #0 {
434 ;CHECK: dup {{v[0-9]+}}.4s, {{w[0-9]+}}
435 %vecinit.i = insertelement <4 x i32> undef, i32 %v1, i32 0
436 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %v1, i32 1
437 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %v1, i32 2
438 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %v1, i32 3
439 ret <4 x i32> %vecinit3.i
442 define <2 x i64> @test_vdupq_n_u64(i64 %v1) #0 {
443 ;CHECK: dup {{v[0-9]+}}.2d, {{x[0-9]+}}
444 %vecinit.i = insertelement <2 x i64> undef, i64 %v1, i32 0
445 %vecinit1.i = insertelement <2 x i64> %vecinit.i, i64 %v1, i32 1
446 ret <2 x i64> %vecinit1.i
449 define <8 x i8> @test_vdup_lane_s8(<8 x i8> %v1) #0 {
450 ;CHECK: dup {{v[0-9]+}}.8b, {{v[0-9]+}}.b[5]
451 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
452 ret <8 x i8> %shuffle
455 define <4 x i16> @test_vdup_lane_s16(<4 x i16> %v1) #0 {
456 ;CHECK: dup {{v[0-9]+}}.4h, {{v[0-9]+}}.h[2]
457 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
458 ret <4 x i16> %shuffle
461 define <2 x i32> @test_vdup_lane_s32(<2 x i32> %v1) #0 {
462 ;CHECK: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
463 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
464 ret <2 x i32> %shuffle
467 define <16 x i8> @test_vdupq_lane_s8(<8 x i8> %v1) #0 {
468 ;CHECK: {{v[0-9]+}}.16b, {{v[0-9]+}}.b[5]
469 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
470 ret <16 x i8> %shuffle
473 define <8 x i16> @test_vdupq_lane_s16(<4 x i16> %v1) #0 {
474 ;CHECK: {{v[0-9]+}}.8h, {{v[0-9]+}}.h[2]
475 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
476 ret <8 x i16> %shuffle
479 define <4 x i32> @test_vdupq_lane_s32(<2 x i32> %v1) #0 {
480 ;CHECK: {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
481 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
482 ret <4 x i32> %shuffle
485 define <2 x i64> @test_vdupq_lane_s64(<1 x i64> %v1) #0 {
486 ;CHECK: {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
487 %shuffle = shufflevector <1 x i64> %v1, <1 x i64> undef, <2 x i32> zeroinitializer
488 ret <2 x i64> %shuffle
491 define <8 x i8> @test_vdup_laneq_s8(<16 x i8> %v1) #0 {
492 ;CHECK: dup {{v[0-9]+}}.8b, {{v[0-9]+}}.b[5]
493 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
494 ret <8 x i8> %shuffle
497 define <4 x i16> @test_vdup_laneq_s16(<8 x i16> %v1) #0 {
498 ;CHECK: dup {{v[0-9]+}}.4h, {{v[0-9]+}}.h[2]
499 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
500 ret <4 x i16> %shuffle
503 define <2 x i32> @test_vdup_laneq_s32(<4 x i32> %v1) #0 {
504 ;CHECK: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
505 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
506 ret <2 x i32> %shuffle
509 define <16 x i8> @test_vdupq_laneq_s8(<16 x i8> %v1) #0 {
510 ;CHECK: dup {{v[0-9]+}}.16b, {{v[0-9]+}}.b[5]
511 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
512 ret <16 x i8> %shuffle
515 define <8 x i16> @test_vdupq_laneq_s16(<8 x i16> %v1) #0 {
516 ;CHECK: {{v[0-9]+}}.8h, {{v[0-9]+}}.h[2]
517 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
518 ret <8 x i16> %shuffle
521 define <4 x i32> @test_vdupq_laneq_s32(<4 x i32> %v1) #0 {
522 ;CHECK: dup {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
523 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
524 ret <4 x i32> %shuffle
527 define <2 x i64> @test_vdupq_laneq_s64(<2 x i64> %v1) #0 {
528 ;CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
529 %shuffle = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
530 ret <2 x i64> %shuffle
533 define i64 @test_bitcastv8i8toi64(<8 x i8> %in) {
534 ; CHECK-LABEL: test_bitcastv8i8toi64:
535 %res = bitcast <8 x i8> %in to i64
536 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
540 define i64 @test_bitcastv4i16toi64(<4 x i16> %in) {
541 ; CHECK-LABEL: test_bitcastv4i16toi64:
542 %res = bitcast <4 x i16> %in to i64
543 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
547 define i64 @test_bitcastv2i32toi64(<2 x i32> %in) {
548 ; CHECK-LABEL: test_bitcastv2i32toi64:
549 %res = bitcast <2 x i32> %in to i64
550 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
554 define i64 @test_bitcastv2f32toi64(<2 x float> %in) {
555 ; CHECK-LABEL: test_bitcastv2f32toi64:
556 %res = bitcast <2 x float> %in to i64
557 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
561 define i64 @test_bitcastv1i64toi64(<1 x i64> %in) {
562 ; CHECK-LABEL: test_bitcastv1i64toi64:
563 %res = bitcast <1 x i64> %in to i64
564 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
568 define i64 @test_bitcastv1f64toi64(<1 x double> %in) {
569 ; CHECK-LABEL: test_bitcastv1f64toi64:
570 %res = bitcast <1 x double> %in to i64
571 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
575 define <8 x i8> @test_bitcasti64tov8i8(i64 %in) {
576 ; CHECK-LABEL: test_bitcasti64tov8i8:
577 %res = bitcast i64 %in to <8 x i8>
578 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
582 define <4 x i16> @test_bitcasti64tov4i16(i64 %in) {
583 ; CHECK-LABEL: test_bitcasti64tov4i16:
584 %res = bitcast i64 %in to <4 x i16>
585 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
589 define <2 x i32> @test_bitcasti64tov2i32(i64 %in) {
590 ; CHECK-LABEL: test_bitcasti64tov2i32:
591 %res = bitcast i64 %in to <2 x i32>
592 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
596 define <2 x float> @test_bitcasti64tov2f32(i64 %in) {
597 ; CHECK-LABEL: test_bitcasti64tov2f32:
598 %res = bitcast i64 %in to <2 x float>
599 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
603 define <1 x i64> @test_bitcasti64tov1i64(i64 %in) {
604 ; CHECK-LABEL: test_bitcasti64tov1i64:
605 %res = bitcast i64 %in to <1 x i64>
606 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
610 define <1 x double> @test_bitcasti64tov1f64(i64 %in) {
611 ; CHECK-LABEL: test_bitcasti64tov1f64:
612 %res = bitcast i64 %in to <1 x double>
613 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
614 ret <1 x double> %res
617 define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {
618 ; CHECK-LABEL: test_bitcastv8i8tov1f64:
619 ; CHECK: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
620 ; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
621 %sub.i = sub <8 x i8> zeroinitializer, %a
622 %1 = bitcast <8 x i8> %sub.i to <1 x double>
623 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
624 ret <1 x i64> %vcvt.i
627 define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {
628 ; CHECK-LABEL: test_bitcastv4i16tov1f64:
629 ; CHECK: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
630 ; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
631 %sub.i = sub <4 x i16> zeroinitializer, %a
632 %1 = bitcast <4 x i16> %sub.i to <1 x double>
633 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
634 ret <1 x i64> %vcvt.i
637 define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 {
638 ; CHECK-LABEL: test_bitcastv2i32tov1f64:
639 ; CHECK: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
640 ; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
641 %sub.i = sub <2 x i32> zeroinitializer, %a
642 %1 = bitcast <2 x i32> %sub.i to <1 x double>
643 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
644 ret <1 x i64> %vcvt.i
647 define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 {
648 ; CHECK-LABEL: test_bitcastv1i64tov1f64:
649 ; CHECK: neg {{d[0-9]+}}, {{d[0-9]+}}
650 ; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
651 %sub.i = sub <1 x i64> zeroinitializer, %a
652 %1 = bitcast <1 x i64> %sub.i to <1 x double>
653 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
654 ret <1 x i64> %vcvt.i
657 define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 {
658 ; CHECK-LABEL: test_bitcastv2f32tov1f64:
659 ; CHECK: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
660 ; CHECK-NEXT: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}
661 %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a
662 %1 = bitcast <2 x float> %sub.i to <1 x double>
663 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>
664 ret <1 x i64> %vcvt.i
667 define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 {
668 ; CHECK-LABEL: test_bitcastv1f64tov8i8:
669 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
670 ; CHECK-NEXT: neg {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
671 %vcvt.i = sitofp <1 x i64> %a to <1 x double>
672 %1 = bitcast <1 x double> %vcvt.i to <8 x i8>
673 %sub.i = sub <8 x i8> zeroinitializer, %1
677 define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 {
678 ; CHECK-LABEL: test_bitcastv1f64tov4i16:
679 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
680 ; CHECK-NEXT: neg {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
681 %vcvt.i = sitofp <1 x i64> %a to <1 x double>
682 %1 = bitcast <1 x double> %vcvt.i to <4 x i16>
683 %sub.i = sub <4 x i16> zeroinitializer, %1
687 define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 {
688 ; CHECK-LABEL: test_bitcastv1f64tov2i32:
689 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
690 ; CHECK-NEXT: neg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
691 %vcvt.i = sitofp <1 x i64> %a to <1 x double>
692 %1 = bitcast <1 x double> %vcvt.i to <2 x i32>
693 %sub.i = sub <2 x i32> zeroinitializer, %1
697 define <1 x i64> @test_bitcastv1f64tov1i64(<1 x i64> %a) #0 {
698 ; CHECK-LABEL: test_bitcastv1f64tov1i64:
699 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
700 ; CHECK-NEXT: neg {{d[0-9]+}}, {{d[0-9]+}}
701 %vcvt.i = sitofp <1 x i64> %a to <1 x double>
702 %1 = bitcast <1 x double> %vcvt.i to <1 x i64>
703 %sub.i = sub <1 x i64> zeroinitializer, %1
707 define <2 x float> @test_bitcastv1f64tov2f32(<1 x i64> %a) #0 {
708 ; CHECK-LABEL: test_bitcastv1f64tov2f32:
709 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
710 ; CHECK-NEXT: fneg {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
711 %vcvt.i = sitofp <1 x i64> %a to <1 x double>
712 %1 = bitcast <1 x double> %vcvt.i to <2 x float>
713 %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %1
714 ret <2 x float> %sub.i
717 ; Test insert element into an undef vector
718 define <8 x i8> @scalar_to_vector.v8i8(i8 %a) {
719 ; CHECK-LABEL: scalar_to_vector.v8i8:
720 ; CHECK: ins {{v[0-9]+}}.b[0], {{w[0-9]+}}
721 %b = insertelement <8 x i8> undef, i8 %a, i32 0
725 define <16 x i8> @scalar_to_vector.v16i8(i8 %a) {
726 ; CHECK-LABEL: scalar_to_vector.v16i8:
727 ; CHECK: ins {{v[0-9]+}}.b[0], {{w[0-9]+}}
728 %b = insertelement <16 x i8> undef, i8 %a, i32 0
732 define <4 x i16> @scalar_to_vector.v4i16(i16 %a) {
733 ; CHECK-LABEL: scalar_to_vector.v4i16:
734 ; CHECK: ins {{v[0-9]+}}.h[0], {{w[0-9]+}}
735 %b = insertelement <4 x i16> undef, i16 %a, i32 0
739 define <8 x i16> @scalar_to_vector.v8i16(i16 %a) {
740 ; CHECK-LABEL: scalar_to_vector.v8i16:
741 ; CHECK: ins {{v[0-9]+}}.h[0], {{w[0-9]+}}
742 %b = insertelement <8 x i16> undef, i16 %a, i32 0
746 define <2 x i32> @scalar_to_vector.v2i32(i32 %a) {
747 ; CHECK-LABEL: scalar_to_vector.v2i32:
748 ; CHECK: ins {{v[0-9]+}}.s[0], {{w[0-9]+}}
749 %b = insertelement <2 x i32> undef, i32 %a, i32 0
753 define <4 x i32> @scalar_to_vector.v4i32(i32 %a) {
754 ; CHECK-LABEL: scalar_to_vector.v4i32:
755 ; CHECK: ins {{v[0-9]+}}.s[0], {{w[0-9]+}}
756 %b = insertelement <4 x i32> undef, i32 %a, i32 0
760 define <2 x i64> @scalar_to_vector.v2i64(i64 %a) {
761 ; CHECK-LABEL: scalar_to_vector.v2i64:
762 ; CHECK: ins {{v[0-9]+}}.d[0], {{x[0-9]+}}
763 %b = insertelement <2 x i64> undef, i64 %a, i32 0
767 define <8 x i8> @testDUP.v1i8(<1 x i8> %a) {
768 ; CHECK-LABEL: testDUP.v1i8:
769 ; CHECK: dup {{v[0-9]+}}.8b, {{w[0-9]+}}
770 %b = extractelement <1 x i8> %a, i32 0
771 %c = insertelement <8 x i8> undef, i8 %b, i32 0
772 %d = insertelement <8 x i8> %c, i8 %b, i32 1
773 %e = insertelement <8 x i8> %d, i8 %b, i32 2
774 %f = insertelement <8 x i8> %e, i8 %b, i32 3
775 %g = insertelement <8 x i8> %f, i8 %b, i32 4
776 %h = insertelement <8 x i8> %g, i8 %b, i32 5
777 %i = insertelement <8 x i8> %h, i8 %b, i32 6
778 %j = insertelement <8 x i8> %i, i8 %b, i32 7
782 define <8 x i16> @testDUP.v1i16(<1 x i16> %a) {
783 ; CHECK-LABEL: testDUP.v1i16:
784 ; CHECK: dup {{v[0-9]+}}.8h, {{w[0-9]+}}
785 %b = extractelement <1 x i16> %a, i32 0
786 %c = insertelement <8 x i16> undef, i16 %b, i32 0
787 %d = insertelement <8 x i16> %c, i16 %b, i32 1
788 %e = insertelement <8 x i16> %d, i16 %b, i32 2
789 %f = insertelement <8 x i16> %e, i16 %b, i32 3
790 %g = insertelement <8 x i16> %f, i16 %b, i32 4
791 %h = insertelement <8 x i16> %g, i16 %b, i32 5
792 %i = insertelement <8 x i16> %h, i16 %b, i32 6
793 %j = insertelement <8 x i16> %i, i16 %b, i32 7
797 define <4 x i32> @testDUP.v1i32(<1 x i32> %a) {
798 ; CHECK-LABEL: testDUP.v1i32:
799 ; CHECK: dup {{v[0-9]+}}.4s, {{w[0-9]+}}
800 %b = extractelement <1 x i32> %a, i32 0
801 %c = insertelement <4 x i32> undef, i32 %b, i32 0
802 %d = insertelement <4 x i32> %c, i32 %b, i32 1
803 %e = insertelement <4 x i32> %d, i32 %b, i32 2
804 %f = insertelement <4 x i32> %e, i32 %b, i32 3
808 define <8 x i8> @getl(<16 x i8> %x) #0 {
811 %vecext = extractelement <16 x i8> %x, i32 0
812 %vecinit = insertelement <8 x i8> undef, i8 %vecext, i32 0
813 %vecext1 = extractelement <16 x i8> %x, i32 1
814 %vecinit2 = insertelement <8 x i8> %vecinit, i8 %vecext1, i32 1
815 %vecext3 = extractelement <16 x i8> %x, i32 2
816 %vecinit4 = insertelement <8 x i8> %vecinit2, i8 %vecext3, i32 2
817 %vecext5 = extractelement <16 x i8> %x, i32 3
818 %vecinit6 = insertelement <8 x i8> %vecinit4, i8 %vecext5, i32 3
819 %vecext7 = extractelement <16 x i8> %x, i32 4
820 %vecinit8 = insertelement <8 x i8> %vecinit6, i8 %vecext7, i32 4
821 %vecext9 = extractelement <16 x i8> %x, i32 5
822 %vecinit10 = insertelement <8 x i8> %vecinit8, i8 %vecext9, i32 5
823 %vecext11 = extractelement <16 x i8> %x, i32 6
824 %vecinit12 = insertelement <8 x i8> %vecinit10, i8 %vecext11, i32 6
825 %vecext13 = extractelement <16 x i8> %x, i32 7
826 %vecinit14 = insertelement <8 x i8> %vecinit12, i8 %vecext13, i32 7
827 ret <8 x i8> %vecinit14
830 define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) {
831 ; CHECK-LABEL: test_dup_v2i32_v4i16:
832 ; CHECK: dup v0.4h, v0.h[2]
834 %x = extractelement <2 x i32> %a, i32 1
835 %vget_lane = trunc i32 %x to i16
836 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
837 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
838 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
839 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
840 ret <4 x i16> %vecinit3.i
843 define <8 x i16> @test_dup_v4i32_v8i16(<4 x i32> %a) {
844 ; CHECK-LABEL: test_dup_v4i32_v8i16:
845 ; CHECK: dup v0.8h, v0.h[6]
847 %x = extractelement <4 x i32> %a, i32 3
848 %vget_lane = trunc i32 %x to i16
849 %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
850 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
851 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
852 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
853 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
854 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
855 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
856 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
857 ret <8 x i16> %vecinit7.i
860 define <4 x i16> @test_dup_v1i64_v4i16(<1 x i64> %a) {
861 ; CHECK-LABEL: test_dup_v1i64_v4i16:
862 ; CHECK: dup v0.4h, v0.h[0]
864 %x = extractelement <1 x i64> %a, i32 0
865 %vget_lane = trunc i64 %x to i16
866 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
867 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
868 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
869 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
870 ret <4 x i16> %vecinit3.i
873 define <2 x i32> @test_dup_v1i64_v2i32(<1 x i64> %a) {
874 ; CHECK-LABEL: test_dup_v1i64_v2i32:
875 ; CHECK: dup v0.2s, v0.s[0]
877 %x = extractelement <1 x i64> %a, i32 0
878 %vget_lane = trunc i64 %x to i32
879 %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 0
880 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 1
881 ret <2 x i32> %vecinit1.i
884 define <8 x i16> @test_dup_v2i64_v8i16(<2 x i64> %a) {
885 ; CHECK-LABEL: test_dup_v2i64_v8i16:
886 ; CHECK: dup v0.8h, v0.h[4]
888 %x = extractelement <2 x i64> %a, i32 1
889 %vget_lane = trunc i64 %x to i16
890 %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
891 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
892 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
893 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
894 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
895 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
896 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
897 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
898 ret <8 x i16> %vecinit7.i
901 define <4 x i32> @test_dup_v2i64_v4i32(<2 x i64> %a) {
902 ; CHECK-LABEL: test_dup_v2i64_v4i32:
903 ; CHECK: dup v0.4s, v0.s[2]
905 %x = extractelement <2 x i64> %a, i32 1
906 %vget_lane = trunc i64 %x to i32
907 %vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 0
908 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 1
909 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 2
910 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 3
911 ret <4 x i32> %vecinit3.i
914 define <4 x i16> @test_dup_v4i32_v4i16(<4 x i32> %a) {
915 ; CHECK-LABEL: test_dup_v4i32_v4i16:
916 ; CHECK: dup v0.4h, v0.h[2]
918 %x = extractelement <4 x i32> %a, i32 1
919 %vget_lane = trunc i32 %x to i16
920 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
921 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
922 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
923 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
924 ret <4 x i16> %vecinit3.i
927 define <4 x i16> @test_dup_v2i64_v4i16(<2 x i64> %a) {
928 ; CHECK-LABEL: test_dup_v2i64_v4i16:
929 ; CHECK: dup v0.4h, v0.h[0]
931 %x = extractelement <2 x i64> %a, i32 0
932 %vget_lane = trunc i64 %x to i16
933 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
934 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
935 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
936 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
937 ret <4 x i16> %vecinit3.i
940 define <2 x i32> @test_dup_v2i64_v2i32(<2 x i64> %a) {
941 ; CHECK-LABEL: test_dup_v2i64_v2i32:
942 ; CHECK: dup v0.2s, v0.s[0]
944 %x = extractelement <2 x i64> %a, i32 0
945 %vget_lane = trunc i64 %x to i32
946 %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 0
947 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 1
948 ret <2 x i32> %vecinit1.i
951 define <2 x i32> @test_concat_undef_v1i32(<1 x i32> %a) {
952 ; CHECK-LABEL: test_concat_undef_v1i32:
953 ; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
955 %0 = extractelement <1 x i32> %a, i32 0
956 %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 1
957 ret <2 x i32> %vecinit1.i
960 define <2 x i32> @test_concat_v1i32_v1i32(<1 x i32> %a) {
961 ; CHECK-LABEL: test_concat_v1i32_v1i32:
962 ; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
964 %0 = extractelement <1 x i32> %a, i32 0
965 %vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 0
966 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 1
967 ret <2 x i32> %vecinit1.i
971 define <2 x float> @test_scalar_to_vector_f32_to_v2f32(<2 x float> %a) {
972 ; CHECK-LABEL: test_scalar_to_vector_f32_to_v2f32:
973 ; CHECK: fmaxp s{{[0-9]+}}, v{{[0-9]+}}.2s
976 %0 = call float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float> %a)
977 %1 = insertelement <1 x float> undef, float %0, i32 0
978 %2 = extractelement <1 x float> %1, i32 0
979 %vecinit1.i = insertelement <2 x float> undef, float %2, i32 0
980 ret <2 x float> %vecinit1.i
983 define <4 x float> @test_scalar_to_vector_f32_to_v4f32(<2 x float> %a) {
984 ; CHECK-LABEL: test_scalar_to_vector_f32_to_v4f32:
985 ; CHECK: fmaxp s{{[0-9]+}}, v{{[0-9]+}}.2s
988 %0 = call float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float> %a)
989 %1 = insertelement <1 x float> undef, float %0, i32 0
990 %2 = extractelement <1 x float> %1, i32 0
991 %vecinit1.i = insertelement <4 x float> undef, float %2, i32 0
992 ret <4 x float> %vecinit1.i
995 declare float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float>)
997 define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {
998 ; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:
999 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1001 %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
1002 ret <16 x i8> %vecinit30
1005 define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
1006 ; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:
1007 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1009 %vecext = extractelement <8 x i8> %x, i32 0
1010 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
1011 %vecext1 = extractelement <8 x i8> %x, i32 1
1012 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
1013 %vecext3 = extractelement <8 x i8> %x, i32 2
1014 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
1015 %vecext5 = extractelement <8 x i8> %x, i32 3
1016 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 3
1017 %vecext7 = extractelement <8 x i8> %x, i32 4
1018 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 4
1019 %vecext9 = extractelement <8 x i8> %x, i32 5
1020 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 5
1021 %vecext11 = extractelement <8 x i8> %x, i32 6
1022 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 6
1023 %vecext13 = extractelement <8 x i8> %x, i32 7
1024 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 7
1025 %vecinit30 = shufflevector <16 x i8> %vecinit14, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
1026 ret <16 x i8> %vecinit30
1029 define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
1030 ; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:
1031 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1033 %vecext = extractelement <16 x i8> %x, i32 0
1034 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
1035 %vecext1 = extractelement <16 x i8> %x, i32 1
1036 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
1037 %vecext3 = extractelement <16 x i8> %x, i32 2
1038 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
1039 %vecext5 = extractelement <16 x i8> %x, i32 3
1040 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 3
1041 %vecext7 = extractelement <16 x i8> %x, i32 4
1042 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 4
1043 %vecext9 = extractelement <16 x i8> %x, i32 5
1044 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 5
1045 %vecext11 = extractelement <16 x i8> %x, i32 6
1046 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 6
1047 %vecext13 = extractelement <16 x i8> %x, i32 7
1048 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 7
1049 %vecext15 = extractelement <8 x i8> %y, i32 0
1050 %vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 8
1051 %vecext17 = extractelement <8 x i8> %y, i32 1
1052 %vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 9
1053 %vecext19 = extractelement <8 x i8> %y, i32 2
1054 %vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 10
1055 %vecext21 = extractelement <8 x i8> %y, i32 3
1056 %vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 11
1057 %vecext23 = extractelement <8 x i8> %y, i32 4
1058 %vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 12
1059 %vecext25 = extractelement <8 x i8> %y, i32 5
1060 %vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 13
1061 %vecext27 = extractelement <8 x i8> %y, i32 6
1062 %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 14
1063 %vecext29 = extractelement <8 x i8> %y, i32 7
1064 %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 15
1065 ret <16 x i8> %vecinit30
1068 define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
1069 ; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:
1070 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1072 %vecext = extractelement <8 x i8> %x, i32 0
1073 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
1074 %vecext1 = extractelement <8 x i8> %x, i32 1
1075 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
1076 %vecext3 = extractelement <8 x i8> %x, i32 2
1077 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
1078 %vecext5 = extractelement <8 x i8> %x, i32 3
1079 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 3
1080 %vecext7 = extractelement <8 x i8> %x, i32 4
1081 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 4
1082 %vecext9 = extractelement <8 x i8> %x, i32 5
1083 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 5
1084 %vecext11 = extractelement <8 x i8> %x, i32 6
1085 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 6
1086 %vecext13 = extractelement <8 x i8> %x, i32 7
1087 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 7
1088 %vecext15 = extractelement <8 x i8> %y, i32 0
1089 %vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 8
1090 %vecext17 = extractelement <8 x i8> %y, i32 1
1091 %vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 9
1092 %vecext19 = extractelement <8 x i8> %y, i32 2
1093 %vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 10
1094 %vecext21 = extractelement <8 x i8> %y, i32 3
1095 %vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 11
1096 %vecext23 = extractelement <8 x i8> %y, i32 4
1097 %vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 12
1098 %vecext25 = extractelement <8 x i8> %y, i32 5
1099 %vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 13
1100 %vecext27 = extractelement <8 x i8> %y, i32 6
1101 %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 14
1102 %vecext29 = extractelement <8 x i8> %y, i32 7
1103 %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 15
1104 ret <16 x i8> %vecinit30
1107 define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {
1108 ; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:
1109 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1111 %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
1112 ret <8 x i16> %vecinit14
1115 define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
1116 ; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:
1117 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1119 %vecext = extractelement <4 x i16> %x, i32 0
1120 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
1121 %vecext1 = extractelement <4 x i16> %x, i32 1
1122 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
1123 %vecext3 = extractelement <4 x i16> %x, i32 2
1124 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
1125 %vecext5 = extractelement <4 x i16> %x, i32 3
1126 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
1127 %vecinit14 = shufflevector <8 x i16> %vecinit6, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
1128 ret <8 x i16> %vecinit14
1131 define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
1132 ; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:
1133 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1135 %vecext = extractelement <8 x i16> %x, i32 0
1136 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
1137 %vecext1 = extractelement <8 x i16> %x, i32 1
1138 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
1139 %vecext3 = extractelement <8 x i16> %x, i32 2
1140 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
1141 %vecext5 = extractelement <8 x i16> %x, i32 3
1142 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
1143 %vecext7 = extractelement <4 x i16> %y, i32 0
1144 %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 4
1145 %vecext9 = extractelement <4 x i16> %y, i32 1
1146 %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 5
1147 %vecext11 = extractelement <4 x i16> %y, i32 2
1148 %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 6
1149 %vecext13 = extractelement <4 x i16> %y, i32 3
1150 %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 7
1151 ret <8 x i16> %vecinit14
1154 define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
1155 ; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:
1156 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1158 %vecext = extractelement <4 x i16> %x, i32 0
1159 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
1160 %vecext1 = extractelement <4 x i16> %x, i32 1
1161 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
1162 %vecext3 = extractelement <4 x i16> %x, i32 2
1163 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
1164 %vecext5 = extractelement <4 x i16> %x, i32 3
1165 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
1166 %vecext7 = extractelement <4 x i16> %y, i32 0
1167 %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 4
1168 %vecext9 = extractelement <4 x i16> %y, i32 1
1169 %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 5
1170 %vecext11 = extractelement <4 x i16> %y, i32 2
1171 %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 6
1172 %vecext13 = extractelement <4 x i16> %y, i32 3
1173 %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 7
1174 ret <8 x i16> %vecinit14
1177 define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {
1178 ; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:
1179 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1181 %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1182 ret <4 x i32> %vecinit6
1185 define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
1186 ; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:
1187 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1189 %vecext = extractelement <2 x i32> %x, i32 0
1190 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
1191 %vecext1 = extractelement <2 x i32> %x, i32 1
1192 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
1193 %vecinit6 = shufflevector <4 x i32> %vecinit2, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
1194 ret <4 x i32> %vecinit6
1197 define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
1198 ; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:
1199 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1201 %vecext = extractelement <4 x i32> %x, i32 0
1202 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
1203 %vecext1 = extractelement <4 x i32> %x, i32 1
1204 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
1205 %vecext3 = extractelement <2 x i32> %y, i32 0
1206 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
1207 %vecext5 = extractelement <2 x i32> %y, i32 1
1208 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 3
1209 ret <4 x i32> %vecinit6
1212 define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {
1213 ; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:
1214 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1216 %vecext = extractelement <2 x i32> %x, i32 0
1217 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
1218 %vecext1 = extractelement <2 x i32> %x, i32 1
1219 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
1220 %vecext3 = extractelement <2 x i32> %y, i32 0
1221 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
1222 %vecext5 = extractelement <2 x i32> %y, i32 1
1223 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 3
1224 ret <4 x i32> %vecinit6
1227 define <2 x i64> @test_concat_v2i64_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) #0 {
1228 ; CHECK-LABEL: test_concat_v2i64_v2i64_v2i64:
1229 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1231 %vecinit2 = shufflevector <2 x i64> %x, <2 x i64> %y, <2 x i32> <i32 0, i32 2>
1232 ret <2 x i64> %vecinit2
1235 define <2 x i64> @test_concat_v2i64_v1i64_v2i64(<1 x i64> %x, <2 x i64> %y) #0 {
1236 ; CHECK-LABEL: test_concat_v2i64_v1i64_v2i64:
1237 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1239 %vecext = extractelement <1 x i64> %x, i32 0
1240 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
1241 %vecinit2 = shufflevector <2 x i64> %vecinit, <2 x i64> %y, <2 x i32> <i32 0, i32 2>
1242 ret <2 x i64> %vecinit2
1245 define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {
1246 ; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:
1247 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1249 %vecext = extractelement <2 x i64> %x, i32 0
1250 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
1251 %vecext1 = extractelement <1 x i64> %y, i32 0
1252 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
1253 ret <2 x i64> %vecinit2
1256 define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {
1257 ; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:
1258 ; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
1260 %vecext = extractelement <1 x i64> %x, i32 0
1261 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
1262 %vecext1 = extractelement <1 x i64> %y, i32 0
1263 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
1264 ret <2 x i64> %vecinit2