1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -mattr=+crypto | FileCheck %s
2 ; RUN: not llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
4 declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
6 declare <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
8 declare <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
10 declare <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
12 declare <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32>, <1 x i32>, <4 x i32>) #1
14 declare <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32>, <1 x i32>, <4 x i32>) #1
16 declare <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32>, <1 x i32>, <4 x i32>) #1
18 declare <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32>, <4 x i32>) #1
20 declare <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32>, <4 x i32>) #1
22 declare <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32>) #1
24 declare <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8>) #1
26 declare <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8>) #1
28 declare <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8>, <16 x i8>) #1
30 declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>) #1
32 define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) {
33 ; CHECK: test_vaeseq_u8:
34 ; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
35 ; CHECK-NO-CRYPTO: Cannot select: intrinsic %llvm.arm.neon.aese
37 %aese.i = tail call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %data, <16 x i8> %key)
41 define <16 x i8> @test_vaesdq_u8(<16 x i8> %data, <16 x i8> %key) {
42 ; CHECK: test_vaesdq_u8:
43 ; CHECK: aesd {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
45 %aesd.i = tail call <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8> %data, <16 x i8> %key)
49 define <16 x i8> @test_vaesmcq_u8(<16 x i8> %data) {
50 ; CHECK: test_vaesmcq_u8:
51 ; CHECK: aesmc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
53 %aesmc.i = tail call <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8> %data)
54 ret <16 x i8> %aesmc.i
57 define <16 x i8> @test_vaesimcq_u8(<16 x i8> %data) {
58 ; CHECK: test_vaesimcq_u8:
59 ; CHECK: aesimc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
61 %aesimc.i = tail call <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8> %data)
62 ret <16 x i8> %aesimc.i
65 define i32 @test_vsha1h_u32(i32 %hash_e) {
66 ; CHECK: test_vsha1h_u32:
67 ; CHECK: sha1h {{s[0-9]+}}, {{s[0-9]+}}
69 %sha1h.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
70 %sha1h1.i = tail call <1 x i32> @llvm.arm.neon.sha1h.v1i32(<1 x i32> %sha1h.i)
71 %0 = extractelement <1 x i32> %sha1h1.i, i32 0
75 define <4 x i32> @test_vsha1su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w12_15) {
76 ; CHECK: test_vsha1su1q_u32:
77 ; CHECK: sha1su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
79 %sha1su12.i = tail call <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w12_15)
80 ret <4 x i32> %sha1su12.i
83 define <4 x i32> @test_vsha256su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7) {
84 ; CHECK: test_vsha256su0q_u32:
85 ; CHECK: sha256su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
87 %sha256su02.i = tail call <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7)
88 ret <4 x i32> %sha256su02.i
91 define <4 x i32> @test_vsha1cq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
92 ; CHECK: test_vsha1cq_u32:
93 ; CHECK: sha1c {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
95 %sha1c.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
96 %sha1c1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1c(<4 x i32> %hash_abcd, <1 x i32> %sha1c.i, <4 x i32> %wk)
97 ret <4 x i32> %sha1c1.i
100 define <4 x i32> @test_vsha1pq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
101 ; CHECK: test_vsha1pq_u32:
102 ; CHECK: sha1p {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
104 %sha1p.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
105 %sha1p1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1p(<4 x i32> %hash_abcd, <1 x i32> %sha1p.i, <4 x i32> %wk)
106 ret <4 x i32> %sha1p1.i
109 define <4 x i32> @test_vsha1mq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
110 ; CHECK: test_vsha1mq_u32:
111 ; CHECK: sha1m {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
113 %sha1m.i = insertelement <1 x i32> undef, i32 %hash_e, i32 0
114 %sha1m1.i = tail call <4 x i32> @llvm.aarch64.neon.sha1m(<4 x i32> %hash_abcd, <1 x i32> %sha1m.i, <4 x i32> %wk)
115 ret <4 x i32> %sha1m1.i
118 define <4 x i32> @test_vsha1su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) {
119 ; CHECK: test_vsha1su0q_u32:
120 ; CHECK: sha1su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
122 %sha1su03.i = tail call <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
123 ret <4 x i32> %sha1su03.i
126 define <4 x i32> @test_vsha256hq_u32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
127 ; CHECK: test_vsha256hq_u32:
128 ; CHECK: sha256h {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
130 %sha256h3.i = tail call <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
131 ret <4 x i32> %sha256h3.i
134 define <4 x i32> @test_vsha256h2q_u32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
135 ; CHECK: test_vsha256h2q_u32:
136 ; CHECK: sha256h2 {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
138 %sha256h23.i = tail call <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
139 ret <4 x i32> %sha256h23.i
142 define <4 x i32> @test_vsha256su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
143 ; CHECK: test_vsha256su1q_u32:
144 ; CHECK: sha256su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
146 %sha256su13.i = tail call <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
147 ret <4 x i32> %sha256su13.i