1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -mattr=+crypto | FileCheck %s
2 ; RUN: not llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
4 declare <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32>, <4 x i32>, <4 x i32>) #1
6 declare <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32>, <4 x i32>, <4 x i32>) #1
8 declare <4 x i32> @llvm.arm.neon.sha256h(<4 x i32>, <4 x i32>, <4 x i32>) #1
10 declare <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32>, <4 x i32>, <4 x i32>) #1
12 declare <4 x i32> @llvm.arm.neon.sha1m(<4 x i32>, i32, <4 x i32>) #1
14 declare <4 x i32> @llvm.arm.neon.sha1p(<4 x i32>, i32, <4 x i32>) #1
16 declare <4 x i32> @llvm.arm.neon.sha1c(<4 x i32>, i32, <4 x i32>) #1
18 declare <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32>, <4 x i32>) #1
20 declare <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32>, <4 x i32>) #1
22 declare i32 @llvm.arm.neon.sha1h(i32) #1
24 declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8>) #1
26 declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8>) #1
28 declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8>, <16 x i8>) #1
30 declare <16 x i8> @llvm.arm.neon.aese(<16 x i8>, <16 x i8>) #1
32 define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) {
33 ; CHECK: test_vaeseq_u8:
34 ; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
35 ; CHECK-NO-CRYPTO: Cannot select: intrinsic %llvm.arm.neon.aese
37 %aese.i = tail call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %data, <16 x i8> %key)
41 define <16 x i8> @test_vaesdq_u8(<16 x i8> %data, <16 x i8> %key) {
42 ; CHECK: test_vaesdq_u8:
43 ; CHECK: aesd {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
45 %aesd.i = tail call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %data, <16 x i8> %key)
49 define <16 x i8> @test_vaesmcq_u8(<16 x i8> %data) {
50 ; CHECK: test_vaesmcq_u8:
51 ; CHECK: aesmc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
53 %aesmc.i = tail call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %data)
54 ret <16 x i8> %aesmc.i
57 define <16 x i8> @test_vaesimcq_u8(<16 x i8> %data) {
58 ; CHECK: test_vaesimcq_u8:
59 ; CHECK: aesimc {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
61 %aesimc.i = tail call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %data)
62 ret <16 x i8> %aesimc.i
65 define i32 @test_vsha1h_u32(i32 %hash_e) {
66 ; CHECK: test_vsha1h_u32:
67 ; CHECK: sha1h {{s[0-9]+}}, {{s[0-9]+}}
69 %sha1h1.i = tail call i32 @llvm.arm.neon.sha1h(i32 %hash_e)
73 define <4 x i32> @test_vsha1su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w12_15) {
74 ; CHECK: test_vsha1su1q_u32:
75 ; CHECK: sha1su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
77 %sha1su12.i = tail call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %tw0_3, <4 x i32> %w12_15)
78 ret <4 x i32> %sha1su12.i
81 define <4 x i32> @test_vsha256su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7) {
82 ; CHECK: test_vsha256su0q_u32:
83 ; CHECK: sha256su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
85 %sha256su02.i = tail call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
86 ret <4 x i32> %sha256su02.i
89 define <4 x i32> @test_vsha1cq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
90 ; CHECK: test_vsha1cq_u32:
91 ; CHECK: sha1c {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
93 %sha1c1.i = tail call <4 x i32> @llvm.arm.neon.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
94 ret <4 x i32> %sha1c1.i
97 define <4 x i32> @test_vsha1pq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
98 ; CHECK: test_vsha1pq_u32:
99 ; CHECK: sha1p {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
101 %sha1p1.i = tail call <4 x i32> @llvm.arm.neon.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
102 ret <4 x i32> %sha1p1.i
105 define <4 x i32> @test_vsha1mq_u32(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
106 ; CHECK: test_vsha1mq_u32:
107 ; CHECK: sha1m {{q[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.4s
109 %sha1m1.i = tail call <4 x i32> @llvm.arm.neon.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
110 ret <4 x i32> %sha1m1.i
113 define <4 x i32> @test_vsha1su0q_u32(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11) {
114 ; CHECK: test_vsha1su0q_u32:
115 ; CHECK: sha1su0 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
117 %sha1su03.i = tail call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
118 ret <4 x i32> %sha1su03.i
121 define <4 x i32> @test_vsha256hq_u32(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
122 ; CHECK: test_vsha256hq_u32:
123 ; CHECK: sha256h {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
125 %sha256h3.i = tail call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
126 ret <4 x i32> %sha256h3.i
129 define <4 x i32> @test_vsha256h2q_u32(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
130 ; CHECK: test_vsha256h2q_u32:
131 ; CHECK: sha256h2 {{q[0-9]+}}, {{q[0-9]+}}, {{v[0-9]+}}.4s
133 %sha256h23.i = tail call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
134 ret <4 x i32> %sha256h23.i
137 define <4 x i32> @test_vsha256su1q_u32(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
138 ; CHECK: test_vsha256su1q_u32:
139 ; CHECK: sha256su1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
141 %sha256su13.i = tail call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %tw0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
142 ret <4 x i32> %sha256su13.i