1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
4 define <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) {
5 ; CHECK-LABEL: test_vext_s8:
6 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
8 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
12 define <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) {
13 ; CHECK-LABEL: test_vext_s16:
14 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
16 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
20 define <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) {
21 ; CHECK-LABEL: test_vext_s32:
22 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
24 %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>
28 define <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) {
29 ; CHECK-LABEL: test_vext_s64:
31 %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>
35 define <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) {
36 ; CHECK-LABEL: test_vextq_s8:
37 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
39 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
43 define <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) {
44 ; CHECK-LABEL: test_vextq_s16:
45 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
47 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
51 define <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) {
52 ; CHECK-LABEL: test_vextq_s32:
53 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
55 %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
59 define <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) {
60 ; CHECK-LABEL: test_vextq_s64:
61 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
63 %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
67 define <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) {
68 ; CHECK-LABEL: test_vext_u8:
69 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
71 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
75 define <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) {
76 ; CHECK-LABEL: test_vext_u16:
77 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
79 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
83 define <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) {
84 ; CHECK-LABEL: test_vext_u32:
85 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
87 %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>
91 define <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) {
92 ; CHECK-LABEL: test_vext_u64:
94 %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>
98 define <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) {
99 ; CHECK-LABEL: test_vextq_u8:
100 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
102 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
106 define <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) {
107 ; CHECK-LABEL: test_vextq_u16:
108 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
110 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
114 define <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) {
115 ; CHECK-LABEL: test_vextq_u32:
116 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
118 %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
122 define <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) {
123 ; CHECK-LABEL: test_vextq_u64:
124 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
126 %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
130 define <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) {
131 ; CHECK-LABEL: test_vext_f32:
132 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
134 %vext = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 2>
135 ret <2 x float> %vext
138 define <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) {
139 ; CHECK-LABEL: test_vext_f64:
141 %vext = shufflevector <1 x double> %a, <1 x double> %b, <1 x i32> <i32 0>
142 ret <1 x double> %vext
145 define <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) {
146 ; CHECK-LABEL: test_vextq_f32:
147 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
149 %vext = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
150 ret <4 x float> %vext
153 define <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) {
154 ; CHECK-LABEL: test_vextq_f64:
155 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
157 %vext = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
158 ret <2 x double> %vext
161 define <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) {
162 ; CHECK-LABEL: test_vext_p8:
163 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
165 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
169 define <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) {
170 ; CHECK-LABEL: test_vext_p16:
171 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
173 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
177 define <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) {
178 ; CHECK-LABEL: test_vextq_p8:
179 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
181 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
185 define <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) {
186 ; CHECK-LABEL: test_vextq_p16:
187 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
189 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
193 define <8 x i8> @test_undef_vext_s8(<8 x i8> %a) {
194 ; CHECK-LABEL: test_undef_vext_s8:
195 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
197 %vext = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 10, i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
201 define <16 x i8> @test_undef_vextq_s8(<16 x i8> %a) {
202 ; CHECK-LABEL: test_undef_vextq_s8:
203 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
205 %vext = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 20, i32 20, i32 20, i32 20, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 20, i32 20, i32 20, i32 20, i32 20>
209 define <4 x i16> @test_undef_vext_s16(<4 x i16> %a) {
210 ; CHECK-LABEL: test_undef_vext_s16:
211 ; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
213 %vext = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
217 define <8 x i16> @test_undef_vextq_s16(<8 x i16> %a) {
218 ; CHECK-LABEL: test_undef_vextq_s16:
219 ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
221 %vext = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>