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AArch64: More correctly constrain target vector extend lowering.
[oota-llvm.git]
/
test
/
CodeGen
/
AArch64
/
neon-idiv.ll
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; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mattr=+neon | FileCheck %s
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define <4 x i32> @test1(<4 x i32> %a) {
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%rem = srem <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %rem
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; CHECK-LABEL: test1
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; FIXME: Can we lower this more efficiently?
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; CHECK: mul
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; CHECK: mul
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; CHECK: mul
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; CHECK: mul
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}
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