1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
4 define <8 x i8> @test_vrev16_s8(<8 x i8> %a) #0 {
5 ; CHECK: rev16 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
6 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
7 ret <8 x i8> %shuffle.i
10 define <16 x i8> @test_vrev16q_s8(<16 x i8> %a) #0 {
11 ; CHECK: rev16 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
12 %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
13 ret <16 x i8> %shuffle.i
16 define <8 x i8> @test_vrev32_s8(<8 x i8> %a) #0 {
17 ; CHECK: rev32 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
18 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
19 ret <8 x i8> %shuffle.i
22 define <4 x i16> @test_vrev32_s16(<4 x i16> %a) #0 {
23 ; CHECK: rev32 v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
24 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
25 ret <4 x i16> %shuffle.i
28 define <16 x i8> @test_vrev32q_s8(<16 x i8> %a) #0 {
29 ; CHECK: rev32 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
30 %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
31 ret <16 x i8> %shuffle.i
34 define <8 x i16> @test_vrev32q_s16(<8 x i16> %a) #0 {
35 ; CHECK: rev32 v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
36 %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
37 ret <8 x i16> %shuffle.i
40 define <8 x i8> @test_vrev64_s8(<8 x i8> %a) #0 {
41 ; CHECK: rev64 v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
42 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
43 ret <8 x i8> %shuffle.i
46 define <4 x i16> @test_vrev64_s16(<4 x i16> %a) #0 {
47 ; CHECK: rev64 v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
48 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
49 ret <4 x i16> %shuffle.i
52 define <2 x i32> @test_vrev64_s32(<2 x i32> %a) #0 {
53 ; CHECK: rev64 v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
54 %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
55 ret <2 x i32> %shuffle.i
58 define <2 x float> @test_vrev64_f32(<2 x float> %a) #0 {
59 ; CHECK: rev64 v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
60 %shuffle.i = shufflevector <2 x float> %a, <2 x float> undef, <2 x i32> <i32 1, i32 0>
61 ret <2 x float> %shuffle.i
64 define <16 x i8> @test_vrev64q_s8(<16 x i8> %a) #0 {
65 ; CHECK: rev64 v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
66 %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
67 ret <16 x i8> %shuffle.i
70 define <8 x i16> @test_vrev64q_s16(<8 x i16> %a) #0 {
71 ; CHECK: rev64 v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
72 %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
73 ret <8 x i16> %shuffle.i
76 define <4 x i32> @test_vrev64q_s32(<4 x i32> %a) #0 {
77 ; CHECK: rev64 v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
78 %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
79 ret <4 x i32> %shuffle.i
82 define <4 x float> @test_vrev64q_f32(<4 x float> %a) #0 {
83 ; CHECK: rev64 v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
84 %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
85 ret <4 x float> %shuffle.i
88 define <4 x i16> @test_vpaddl_s8(<8 x i8> %a) #0 {
89 ; CHECK: saddlp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b
90 %vpaddl.i = tail call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %a) #4
91 ret <4 x i16> %vpaddl.i
94 define <2 x i32> @test_vpaddl_s16(<4 x i16> %a) #0 {
95 ; CHECK: saddlp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h
96 %vpaddl1.i = tail call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %a) #4
97 ret <2 x i32> %vpaddl1.i
100 define <1 x i64> @test_vpaddl_s32(<2 x i32> %a) #0 {
101 ; CHECK: saddlp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s
102 %vpaddl1.i = tail call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %a) #4
103 ret <1 x i64> %vpaddl1.i
106 define <4 x i16> @test_vpaddl_u8(<8 x i8> %a) #0 {
107 ; CHECK: uaddlp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b
108 %vpaddl.i = tail call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %a) #4
109 ret <4 x i16> %vpaddl.i
112 define <2 x i32> @test_vpaddl_u16(<4 x i16> %a) #0 {
113 ; CHECK: uaddlp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h
114 %vpaddl1.i = tail call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %a) #4
115 ret <2 x i32> %vpaddl1.i
118 define <1 x i64> @test_vpaddl_u32(<2 x i32> %a) #0 {
119 ; CHECK: uaddlp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s
120 %vpaddl1.i = tail call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %a) #4
121 ret <1 x i64> %vpaddl1.i
124 define <8 x i16> @test_vpaddlq_s8(<16 x i8> %a) #0 {
125 ; CHECK: saddlp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b
126 %vpaddl.i = tail call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %a) #4
127 ret <8 x i16> %vpaddl.i
130 define <4 x i32> @test_vpaddlq_s16(<8 x i16> %a) #0 {
131 ; CHECK: saddlp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h
132 %vpaddl1.i = tail call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %a) #4
133 ret <4 x i32> %vpaddl1.i
136 define <2 x i64> @test_vpaddlq_s32(<4 x i32> %a) #0 {
137 ; CHECK: saddlp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s
138 %vpaddl1.i = tail call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %a) #4
139 ret <2 x i64> %vpaddl1.i
142 define <8 x i16> @test_vpaddlq_u8(<16 x i8> %a) #0 {
143 ; CHECK: uaddlp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b
144 %vpaddl.i = tail call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %a) #4
145 ret <8 x i16> %vpaddl.i
148 define <4 x i32> @test_vpaddlq_u16(<8 x i16> %a) #0 {
149 ; CHECK: uaddlp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h
150 %vpaddl1.i = tail call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %a) #4
151 ret <4 x i32> %vpaddl1.i
154 define <2 x i64> @test_vpaddlq_u32(<4 x i32> %a) #0 {
155 ; CHECK: uaddlp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s
156 %vpaddl1.i = tail call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %a) #4
157 ret <2 x i64> %vpaddl1.i
160 define <4 x i16> @test_vpadal_s8(<4 x i16> %a, <8 x i8> %b) #0 {
161 ; CHECK: sadalp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b
162 %vpadal1.i = tail call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %a, <8 x i8> %b) #4
163 ret <4 x i16> %vpadal1.i
166 define <2 x i32> @test_vpadal_s16(<2 x i32> %a, <4 x i16> %b) #0 {
167 ; CHECK: sadalp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h
168 %vpadal2.i = tail call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %a, <4 x i16> %b) #4
169 ret <2 x i32> %vpadal2.i
172 define <1 x i64> @test_vpadal_s32(<1 x i64> %a, <2 x i32> %b) #0 {
173 ; CHECK: sadalp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s
174 %vpadal2.i = tail call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %a, <2 x i32> %b) #4
175 ret <1 x i64> %vpadal2.i
178 define <4 x i16> @test_vpadal_u8(<4 x i16> %a, <8 x i8> %b) #0 {
179 ; CHECK: uadalp v{{[0-9]+}}.4h, v{{[0-9]+}}.8b
180 %vpadal1.i = tail call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %a, <8 x i8> %b) #4
181 ret <4 x i16> %vpadal1.i
184 define <2 x i32> @test_vpadal_u16(<2 x i32> %a, <4 x i16> %b) #0 {
185 ; CHECK: uadalp v{{[0-9]+}}.2s, v{{[0-9]+}}.4h
186 %vpadal2.i = tail call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %a, <4 x i16> %b) #4
187 ret <2 x i32> %vpadal2.i
190 define <1 x i64> @test_vpadal_u32(<1 x i64> %a, <2 x i32> %b) #0 {
191 ; CHECK: uadalp v{{[0-9]+}}.1d, v{{[0-9]+}}.2s
192 %vpadal2.i = tail call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %a, <2 x i32> %b) #4
193 ret <1 x i64> %vpadal2.i
196 define <8 x i16> @test_vpadalq_s8(<8 x i16> %a, <16 x i8> %b) #0 {
197 ; CHECK: sadalp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b
198 %vpadal1.i = tail call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %a, <16 x i8> %b) #4
199 ret <8 x i16> %vpadal1.i
202 define <4 x i32> @test_vpadalq_s16(<4 x i32> %a, <8 x i16> %b) #0 {
203 ; CHECK: sadalp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h
204 %vpadal2.i = tail call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %a, <8 x i16> %b) #4
205 ret <4 x i32> %vpadal2.i
208 define <2 x i64> @test_vpadalq_s32(<2 x i64> %a, <4 x i32> %b) #0 {
209 ; CHECK: sadalp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s
210 %vpadal2.i = tail call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %a, <4 x i32> %b) #4
211 ret <2 x i64> %vpadal2.i
214 define <8 x i16> @test_vpadalq_u8(<8 x i16> %a, <16 x i8> %b) #0 {
215 ; CHECK: uadalp v{{[0-9]+}}.8h, v{{[0-9]+}}.16b
216 %vpadal1.i = tail call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %a, <16 x i8> %b) #4
217 ret <8 x i16> %vpadal1.i
220 define <4 x i32> @test_vpadalq_u16(<4 x i32> %a, <8 x i16> %b) #0 {
221 ; CHECK: uadalp v{{[0-9]+}}.4s, v{{[0-9]+}}.8h
222 %vpadal2.i = tail call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %a, <8 x i16> %b) #4
223 ret <4 x i32> %vpadal2.i
226 define <2 x i64> @test_vpadalq_u32(<2 x i64> %a, <4 x i32> %b) #0 {
227 ; CHECK: uadalp v{{[0-9]+}}.2d, v{{[0-9]+}}.4s
228 %vpadal2.i = tail call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %a, <4 x i32> %b) #4
229 ret <2 x i64> %vpadal2.i
232 define <8 x i8> @test_vqabs_s8(<8 x i8> %a) #0 {
233 ; CHECK: sqabs v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
234 %vqabs.i = tail call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %a) #4
235 ret <8 x i8> %vqabs.i
238 define <16 x i8> @test_vqabsq_s8(<16 x i8> %a) #0 {
239 ; CHECK: sqabs v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
240 %vqabs.i = tail call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %a) #4
241 ret <16 x i8> %vqabs.i
244 define <4 x i16> @test_vqabs_s16(<4 x i16> %a) #0 {
245 ; CHECK: sqabs v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
246 %vqabs1.i = tail call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %a) #4
247 ret <4 x i16> %vqabs1.i
250 define <8 x i16> @test_vqabsq_s16(<8 x i16> %a) #0 {
251 ; CHECK: sqabs v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
252 %vqabs1.i = tail call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %a) #4
253 ret <8 x i16> %vqabs1.i
256 define <2 x i32> @test_vqabs_s32(<2 x i32> %a) #0 {
257 ; CHECK: sqabs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
258 %vqabs1.i = tail call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %a) #4
259 ret <2 x i32> %vqabs1.i
262 define <4 x i32> @test_vqabsq_s32(<4 x i32> %a) #0 {
263 ; CHECK: sqabs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
264 %vqabs1.i = tail call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %a) #4
265 ret <4 x i32> %vqabs1.i
268 define <2 x i64> @test_vqabsq_s64(<2 x i64> %a) #0 {
269 ; CHECK: sqabs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
270 %vqabs1.i = tail call <2 x i64> @llvm.arm.neon.vqabs.v2i64(<2 x i64> %a) #4
271 ret <2 x i64> %vqabs1.i
274 define <8 x i8> @test_vqneg_s8(<8 x i8> %a) #0 {
275 ; CHECK: sqneg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
276 %vqneg.i = tail call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %a) #4
277 ret <8 x i8> %vqneg.i
280 define <16 x i8> @test_vqnegq_s8(<16 x i8> %a) #0 {
281 ; CHECK: sqneg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
282 %vqneg.i = tail call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %a) #4
283 ret <16 x i8> %vqneg.i
286 define <4 x i16> @test_vqneg_s16(<4 x i16> %a) #0 {
287 ; CHECK: sqneg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
288 %vqneg1.i = tail call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %a) #4
289 ret <4 x i16> %vqneg1.i
292 define <8 x i16> @test_vqnegq_s16(<8 x i16> %a) #0 {
293 ; CHECK: sqneg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
294 %vqneg1.i = tail call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %a) #4
295 ret <8 x i16> %vqneg1.i
298 define <2 x i32> @test_vqneg_s32(<2 x i32> %a) #0 {
299 ; CHECK: sqneg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
300 %vqneg1.i = tail call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %a) #4
301 ret <2 x i32> %vqneg1.i
304 define <4 x i32> @test_vqnegq_s32(<4 x i32> %a) #0 {
305 ; CHECK: sqneg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
306 %vqneg1.i = tail call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %a) #4
307 ret <4 x i32> %vqneg1.i
310 define <2 x i64> @test_vqnegq_s64(<2 x i64> %a) #0 {
311 ; CHECK: sqneg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
312 %vqneg1.i = tail call <2 x i64> @llvm.arm.neon.vqneg.v2i64(<2 x i64> %a) #4
313 ret <2 x i64> %vqneg1.i
316 define <8 x i8> @test_vneg_s8(<8 x i8> %a) #0 {
317 ; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
318 %sub.i = sub <8 x i8> zeroinitializer, %a
322 define <16 x i8> @test_vnegq_s8(<16 x i8> %a) #0 {
323 ; CHECK: neg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
324 %sub.i = sub <16 x i8> zeroinitializer, %a
328 define <4 x i16> @test_vneg_s16(<4 x i16> %a) #0 {
329 ; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
330 %sub.i = sub <4 x i16> zeroinitializer, %a
334 define <8 x i16> @test_vnegq_s16(<8 x i16> %a) #0 {
335 ; CHECK: neg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
336 %sub.i = sub <8 x i16> zeroinitializer, %a
340 define <2 x i32> @test_vneg_s32(<2 x i32> %a) #0 {
341 ; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
342 %sub.i = sub <2 x i32> zeroinitializer, %a
346 define <4 x i32> @test_vnegq_s32(<4 x i32> %a) #0 {
347 ; CHECK: neg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
348 %sub.i = sub <4 x i32> zeroinitializer, %a
352 define <2 x i64> @test_vnegq_s64(<2 x i64> %a) #0 {
353 ; CHECK: neg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
354 %sub.i = sub <2 x i64> zeroinitializer, %a
358 define <2 x float> @test_vneg_f32(<2 x float> %a) #0 {
359 ; CHECK: fneg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
360 %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a
361 ret <2 x float> %sub.i
364 define <4 x float> @test_vnegq_f32(<4 x float> %a) #0 {
365 ; CHECK: fneg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
366 %sub.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a
367 ret <4 x float> %sub.i
370 define <2 x double> @test_vnegq_f64(<2 x double> %a) #0 {
371 ; CHECK: fneg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
372 %sub.i = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a
373 ret <2 x double> %sub.i
376 define <8 x i8> @test_vabs_s8(<8 x i8> %a) #0 {
377 ; CHECK: abs v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
378 %vabs.i = tail call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %a) #4
382 define <16 x i8> @test_vabsq_s8(<16 x i8> %a) #0 {
383 ; CHECK: abs v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
384 %vabs.i = tail call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %a) #4
385 ret <16 x i8> %vabs.i
388 define <4 x i16> @test_vabs_s16(<4 x i16> %a) #0 {
389 ; CHECK: abs v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
390 %vabs1.i = tail call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %a) #4
391 ret <4 x i16> %vabs1.i
394 define <8 x i16> @test_vabsq_s16(<8 x i16> %a) #0 {
395 ; CHECK: abs v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
396 %vabs1.i = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %a) #4
397 ret <8 x i16> %vabs1.i
400 define <2 x i32> @test_vabs_s32(<2 x i32> %a) #0 {
401 ; CHECK: abs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
402 %vabs1.i = tail call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %a) #4
403 ret <2 x i32> %vabs1.i
406 define <4 x i32> @test_vabsq_s32(<4 x i32> %a) #0 {
407 ; CHECK: abs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
408 %vabs1.i = tail call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %a) #4
409 ret <4 x i32> %vabs1.i
412 define <2 x i64> @test_vabsq_s64(<2 x i64> %a) #0 {
413 ; CHECK: abs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
414 %vabs1.i = tail call <2 x i64> @llvm.arm.neon.vabs.v2i64(<2 x i64> %a) #4
415 ret <2 x i64> %vabs1.i
418 define <2 x float> @test_vabs_f32(<2 x float> %a) #1 {
419 ; CHECK: fabs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
420 %vabs1.i = tail call <2 x float> @llvm.fabs.v2f32(<2 x float> %a) #4
421 ret <2 x float> %vabs1.i
424 define <4 x float> @test_vabsq_f32(<4 x float> %a) #1 {
425 ; CHECK: fabs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
426 %vabs1.i = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) #4
427 ret <4 x float> %vabs1.i
430 define <2 x double> @test_vabsq_f64(<2 x double> %a) #1 {
431 ; CHECK: fabs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
432 %vabs1.i = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %a) #4
433 ret <2 x double> %vabs1.i
436 define <8 x i8> @test_vuqadd_s8(<8 x i8> %a, <8 x i8> %b) #0 {
437 ; CHECK: suqadd v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
438 %vuqadd.i = tail call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> %a, <8 x i8> %b) #4
439 ret <8 x i8> %vuqadd.i
442 define <16 x i8> @test_vuqaddq_s8(<16 x i8> %a, <16 x i8> %b) #0 {
443 ; CHECK: suqadd v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
444 %vuqadd.i = tail call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> %a, <16 x i8> %b) #4
445 ret <16 x i8> %vuqadd.i
448 define <4 x i16> @test_vuqadd_s16(<4 x i16> %a, <4 x i16> %b) #0 {
449 ; CHECK: suqadd v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
450 %vuqadd2.i = tail call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> %a, <4 x i16> %b) #4
451 ret <4 x i16> %vuqadd2.i
454 define <8 x i16> @test_vuqaddq_s16(<8 x i16> %a, <8 x i16> %b) #0 {
455 ; CHECK: suqadd v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
456 %vuqadd2.i = tail call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> %a, <8 x i16> %b) #4
457 ret <8 x i16> %vuqadd2.i
460 define <2 x i32> @test_vuqadd_s32(<2 x i32> %a, <2 x i32> %b) #0 {
461 ; CHECK: suqadd v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
462 %vuqadd2.i = tail call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> %a, <2 x i32> %b) #4
463 ret <2 x i32> %vuqadd2.i
466 define <4 x i32> @test_vuqaddq_s32(<4 x i32> %a, <4 x i32> %b) #0 {
467 ; CHECK: suqadd v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
468 %vuqadd2.i = tail call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> %a, <4 x i32> %b) #4
469 ret <4 x i32> %vuqadd2.i
472 define <2 x i64> @test_vuqaddq_s64(<2 x i64> %a, <2 x i64> %b) #0 {
473 ; CHECK: suqadd v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
474 %vuqadd2.i = tail call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> %a, <2 x i64> %b) #4
475 ret <2 x i64> %vuqadd2.i
478 define <8 x i8> @test_vcls_s8(<8 x i8> %a) #0 {
479 ; CHECK: cls v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
480 %vcls.i = tail call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %a) #4
484 define <16 x i8> @test_vclsq_s8(<16 x i8> %a) #0 {
485 ; CHECK: cls v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
486 %vcls.i = tail call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %a) #4
487 ret <16 x i8> %vcls.i
490 define <4 x i16> @test_vcls_s16(<4 x i16> %a) #0 {
491 ; CHECK: cls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
492 %vcls1.i = tail call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %a) #4
493 ret <4 x i16> %vcls1.i
496 define <8 x i16> @test_vclsq_s16(<8 x i16> %a) #0 {
497 ; CHECK: cls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
498 %vcls1.i = tail call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %a) #4
499 ret <8 x i16> %vcls1.i
502 define <2 x i32> @test_vcls_s32(<2 x i32> %a) #0 {
503 ; CHECK: cls v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
504 %vcls1.i = tail call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %a) #4
505 ret <2 x i32> %vcls1.i
508 define <4 x i32> @test_vclsq_s32(<4 x i32> %a) #0 {
509 ; CHECK: cls v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
510 %vcls1.i = tail call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %a) #4
511 ret <4 x i32> %vcls1.i
514 define <8 x i8> @test_vclz_s8(<8 x i8> %a) #0 {
515 ; CHECK: clz v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
516 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) #4
520 define <16 x i8> @test_vclzq_s8(<16 x i8> %a) #0 {
521 ; CHECK: clz v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
522 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) #4
523 ret <16 x i8> %vclz.i
526 define <4 x i16> @test_vclz_s16(<4 x i16> %a) #0 {
527 ; CHECK: clz v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
528 %vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) #4
529 ret <4 x i16> %vclz1.i
532 define <8 x i16> @test_vclzq_s16(<8 x i16> %a) #0 {
533 ; CHECK: clz v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
534 %vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) #4
535 ret <8 x i16> %vclz1.i
538 define <2 x i32> @test_vclz_s32(<2 x i32> %a) #0 {
539 ; CHECK: clz v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
540 %vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) #4
541 ret <2 x i32> %vclz1.i
544 define <4 x i32> @test_vclzq_s32(<4 x i32> %a) #0 {
545 ; CHECK: clz v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
546 %vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) #4
547 ret <4 x i32> %vclz1.i
550 define <8 x i8> @test_vcnt_s8(<8 x i8> %a) #0 {
551 ; CHECK: cnt v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
552 %vctpop.i = tail call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %a) #4
553 ret <8 x i8> %vctpop.i
556 define <16 x i8> @test_vcntq_s8(<16 x i8> %a) #0 {
557 ; CHECK: cnt v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
558 %vctpop.i = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) #4
559 ret <16 x i8> %vctpop.i
562 define <8 x i8> @test_vmvn_s8(<8 x i8> %a) #0 {
563 ; CHECK: not v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
564 %neg.i = xor <8 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
568 define <16 x i8> @test_vmvnq_s8(<16 x i8> %a) #0 {
569 ; CHECK: not v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
570 %neg.i = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
574 define <4 x i16> @test_vmvn_s16(<4 x i16> %a) #0 {
575 ; CHECK: not v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
576 %neg.i = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
580 define <8 x i16> @test_vmvnq_s16(<8 x i16> %a) #0 {
581 ; CHECK: not v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
582 %neg.i = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
586 define <2 x i32> @test_vmvn_s32(<2 x i32> %a) #0 {
587 ; CHECK: not v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
588 %neg.i = xor <2 x i32> %a, <i32 -1, i32 -1>
592 define <4 x i32> @test_vmvnq_s32(<4 x i32> %a) #0 {
593 ; CHECK: not v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
594 %neg.i = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
598 define <8 x i8> @test_vrbit_s8(<8 x i8> %a) #0 {
599 ; CHECK: rbit v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
600 %vrbit.i = tail call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %a) #4
601 ret <8 x i8> %vrbit.i
604 define <16 x i8> @test_vrbitq_s8(<16 x i8> %a) #0 {
605 ; CHECK: rbit v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
606 %vrbit.i = tail call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %a) #4
607 ret <16 x i8> %vrbit.i
610 define <8 x i8> @test_vmovn_s16(<8 x i16> %a) #0 {
611 ; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
612 %vmovn.i = trunc <8 x i16> %a to <8 x i8>
613 ret <8 x i8> %vmovn.i
616 define <4 x i16> @test_vmovn_s32(<4 x i32> %a) #0 {
617 ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
618 %vmovn.i = trunc <4 x i32> %a to <4 x i16>
619 ret <4 x i16> %vmovn.i
622 define <2 x i32> @test_vmovn_s64(<2 x i64> %a) #0 {
623 ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
624 %vmovn.i = trunc <2 x i64> %a to <2 x i32>
625 ret <2 x i32> %vmovn.i
628 define <16 x i8> @test_vmovn_high_s16(<8 x i8> %a, <8 x i16> %b) #0 {
629 ; CHECK: xtn2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h
630 %vmovn.i.i = trunc <8 x i16> %b to <8 x i8>
631 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vmovn.i.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
632 ret <16 x i8> %shuffle.i
635 define <8 x i16> @test_vmovn_high_s32(<4 x i16> %a, <4 x i32> %b) #0 {
636 ; CHECK: xtn2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s
637 %vmovn.i.i = trunc <4 x i32> %b to <4 x i16>
638 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vmovn.i.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
639 ret <8 x i16> %shuffle.i
642 define <4 x i32> @test_vmovn_high_s64(<2 x i32> %a, <2 x i64> %b) #0 {
643 ; CHECK: xtn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d
644 %vmovn.i.i = trunc <2 x i64> %b to <2 x i32>
645 %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vmovn.i.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
646 ret <4 x i32> %shuffle.i
649 define <8 x i8> @test_vqmovun_s16(<8 x i16> %a) #0 {
650 ; CHECK: sqxtun v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
651 %vqdmull1.i = tail call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %a) #4
652 ret <8 x i8> %vqdmull1.i
655 define <4 x i16> @test_vqmovun_s32(<4 x i32> %a) #0 {
656 ; CHECK: sqxtun v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
657 %vqdmull1.i = tail call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %a) #4
658 ret <4 x i16> %vqdmull1.i
661 define <2 x i32> @test_vqmovun_s64(<2 x i64> %a) #0 {
662 ; CHECK: sqxtun v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
663 %vqdmull1.i = tail call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %a) #4
664 ret <2 x i32> %vqdmull1.i
667 define <16 x i8> @test_vqmovun_high_s16(<8 x i8> %a, <8 x i16> %b) #0 {
668 ; CHECK: sqxtun2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h
669 %vqdmull1.i.i = tail call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %b) #4
670 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vqdmull1.i.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
671 ret <16 x i8> %shuffle.i
674 define <8 x i16> @test_vqmovun_high_s32(<4 x i16> %a, <4 x i32> %b) #0 {
675 ; CHECK: sqxtun2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s
676 %vqdmull1.i.i = tail call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %b) #4
677 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vqdmull1.i.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
678 ret <8 x i16> %shuffle.i
681 define <4 x i32> @test_vqmovun_high_s64(<2 x i32> %a, <2 x i64> %b) #0 {
682 ; CHECK: sqxtun2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d
683 %vqdmull1.i.i = tail call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %b) #4
684 %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vqdmull1.i.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
685 ret <4 x i32> %shuffle.i
688 define <8 x i8> @test_vqmovn_s16(<8 x i16> %a) #0 {
689 ; CHECK: sqxtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
690 %vqmovn1.i = tail call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %a) #4
691 ret <8 x i8> %vqmovn1.i
694 define <4 x i16> @test_vqmovn_s32(<4 x i32> %a) #0 {
695 ; CHECK: sqxtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
696 %vqmovn1.i = tail call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %a) #4
697 ret <4 x i16> %vqmovn1.i
700 define <2 x i32> @test_vqmovn_s64(<2 x i64> %a) #0 {
701 ; CHECK: sqxtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
702 %vqmovn1.i = tail call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %a) #4
703 ret <2 x i32> %vqmovn1.i
706 define <16 x i8> @test_vqmovn_high_s16(<8 x i8> %a, <8 x i16> %b) #0 {
707 ; CHECK: sqxtn2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h
708 %vqmovn1.i.i = tail call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %b) #4
709 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vqmovn1.i.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
710 ret <16 x i8> %shuffle.i
713 define <8 x i16> @test_vqmovn_high_s32(<4 x i16> %a, <4 x i32> %b) #0 {
714 ; CHECK: test_vqmovn_high_s32
715 %vqmovn1.i.i = tail call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %b) #4
716 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vqmovn1.i.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
717 ret <8 x i16> %shuffle.i
720 define <4 x i32> @test_vqmovn_high_s64(<2 x i32> %a, <2 x i64> %b) #0 {
721 ; CHECK: test_vqmovn_high_s64
722 %vqmovn1.i.i = tail call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %b) #4
723 %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vqmovn1.i.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
724 ret <4 x i32> %shuffle.i
727 define <8 x i8> @test_vqmovn_u16(<8 x i16> %a) #0 {
728 ; CHECK: uqxtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
729 %vqmovn1.i = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %a) #4
730 ret <8 x i8> %vqmovn1.i
733 define <4 x i16> @test_vqmovn_u32(<4 x i32> %a) #0 {
734 ; CHECK: uqxtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
735 %vqmovn1.i = tail call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %a) #4
736 ret <4 x i16> %vqmovn1.i
739 define <2 x i32> @test_vqmovn_u64(<2 x i64> %a) #0 {
740 ; CHECK: uqxtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
741 %vqmovn1.i = tail call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %a) #4
742 ret <2 x i32> %vqmovn1.i
745 define <16 x i8> @test_vqmovn_high_u16(<8 x i8> %a, <8 x i16> %b) #0 {
746 ; CHECK: uqxtn2 v{{[0-9]+}}.16b, v{{[0-9]+}}.8h
747 %vqmovn1.i.i = tail call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %b) #4
748 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %vqmovn1.i.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
749 ret <16 x i8> %shuffle.i
752 define <8 x i16> @test_vqmovn_high_u32(<4 x i16> %a, <4 x i32> %b) #0 {
753 ; CHECK: uqxtn2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s
754 %vqmovn1.i.i = tail call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %b) #4
755 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vqmovn1.i.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
756 ret <8 x i16> %shuffle.i
759 define <4 x i32> @test_vqmovn_high_u64(<2 x i32> %a, <2 x i64> %b) #0 {
760 ; CHECK: uqxtn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d
761 %vqmovn1.i.i = tail call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %b) #4
762 %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %vqmovn1.i.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
763 ret <4 x i32> %shuffle.i
766 define <8 x i16> @test_vshll_n_s8(<8 x i8> %a) #0 {
767 ; CHECK: shll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #8
768 %1 = sext <8 x i8> %a to <8 x i16>
769 %vshll_n = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
770 ret <8 x i16> %vshll_n
773 define <4 x i32> @test_vshll_n_s16(<4 x i16> %a) #0 {
774 ; CHECK: shll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #16
775 %1 = sext <4 x i16> %a to <4 x i32>
776 %vshll_n = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
777 ret <4 x i32> %vshll_n
780 define <2 x i64> @test_vshll_n_s32(<2 x i32> %a) #0 {
781 ; CHECK: shll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #32
782 %1 = sext <2 x i32> %a to <2 x i64>
783 %vshll_n = shl <2 x i64> %1, <i64 32, i64 32>
784 ret <2 x i64> %vshll_n
787 define <8 x i16> @test_vshll_n_u8(<8 x i8> %a) #0 {
788 ; CHECK: shll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #8
789 %1 = zext <8 x i8> %a to <8 x i16>
790 %vshll_n = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
791 ret <8 x i16> %vshll_n
794 define <4 x i32> @test_vshll_n_u16(<4 x i16> %a) #0 {
795 ; CHECK: shll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #16
796 %1 = zext <4 x i16> %a to <4 x i32>
797 %vshll_n = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
798 ret <4 x i32> %vshll_n
801 define <2 x i64> @test_vshll_n_u32(<2 x i32> %a) #0 {
802 ; CHECK: shll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #32
803 %1 = zext <2 x i32> %a to <2 x i64>
804 %vshll_n = shl <2 x i64> %1, <i64 32, i64 32>
805 ret <2 x i64> %vshll_n
808 define <8 x i16> @test_vshll_high_n_s8(<16 x i8> %a) #0 {
809 ; CHECK: shll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #8
810 %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
811 %1 = sext <8 x i8> %shuffle.i to <8 x i16>
812 %vshll_n = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
813 ret <8 x i16> %vshll_n
816 define <4 x i32> @test_vshll_high_n_s16(<8 x i16> %a) #0 {
817 ; CHECK: shll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #16
818 %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
819 %1 = sext <4 x i16> %shuffle.i to <4 x i32>
820 %vshll_n = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
821 ret <4 x i32> %vshll_n
824 define <2 x i64> @test_vshll_high_n_s32(<4 x i32> %a) #0 {
825 ; CHECK: shll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #32
826 %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
827 %1 = sext <2 x i32> %shuffle.i to <2 x i64>
828 %vshll_n = shl <2 x i64> %1, <i64 32, i64 32>
829 ret <2 x i64> %vshll_n
832 define <8 x i16> @test_vshll_high_n_u8(<16 x i8> %a) #0 {
833 ; CHECK: shll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #8
834 %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
835 %1 = zext <8 x i8> %shuffle.i to <8 x i16>
836 %vshll_n = shl <8 x i16> %1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
837 ret <8 x i16> %vshll_n
840 define <4 x i32> @test_vshll_high_n_u16(<8 x i16> %a) #0 {
841 ; CHECK: shll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #16
842 %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
843 %1 = zext <4 x i16> %shuffle.i to <4 x i32>
844 %vshll_n = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
845 ret <4 x i32> %vshll_n
848 define <2 x i64> @test_vshll_high_n_u32(<4 x i32> %a) #0 {
849 ; CHECK: shll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #32
850 %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
851 %1 = zext <2 x i32> %shuffle.i to <2 x i64>
852 %vshll_n = shl <2 x i64> %1, <i64 32, i64 32>
853 ret <2 x i64> %vshll_n
856 define <4 x i16> @test_vcvt_f16_f32(<4 x float> %a) #0 {
857 ; CHECK: fcvtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
858 %vcvt1.i = tail call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %a) #4
859 ret <4 x i16> %vcvt1.i
862 define <8 x i16> @test_vcvt_high_f16_f32(<4 x i16> %a, <4 x float> %b) #0 {
863 ; CHECK: fcvtn2 v{{[0-9]+}}.8h, v{{[0-9]+}}.4s
864 %vcvt1.i.i = tail call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %b) #4
865 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %vcvt1.i.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
866 ret <8 x i16> %shuffle.i
869 define <4 x float> @test_vcvt_f32_f16(<4 x i16> %a) #0 {
870 ; CHECK: fcvtl v{{[0-9]+}}.4s, v{{[0-9]+}}.4h
871 %vcvt1.i = tail call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %a) #4
872 ret <4 x float> %vcvt1.i
875 define <4 x float> @test_vcvt_high_f32_f16(<8 x i16> %a) #0 {
876 ; CHECK: fcvtl2 v{{[0-9]+}}.4s, v{{[0-9]+}}.8h
877 %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
878 %vcvt1.i.i = tail call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %shuffle.i.i) #4
879 ret <4 x float> %vcvt1.i.i
882 define <2 x float> @test_vcvt_f32_f64(<2 x double> %a) #0 {
883 ; CHECK: fcvtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
884 %vcvt.i = fptrunc <2 x double> %a to <2 x float>
885 ret <2 x float> %vcvt.i
888 define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %a, <2 x double> %b) #0 {
889 ; CHECK: fcvtn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d
890 %vcvt.i.i = fptrunc <2 x double> %b to <2 x float>
891 %shuffle.i = shufflevector <2 x float> %a, <2 x float> %vcvt.i.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
892 ret <4 x float> %shuffle.i
895 define <2 x float> @test_vcvtx_f32_f64(<2 x double> %a) #0 {
896 ; CHECK: fcvtxn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
897 %vcvtx_f32_f641.i = call <2 x float> @llvm.aarch64.neon.vcvtxn.v2f32.v2f64(<2 x double> %a) #4
898 ret <2 x float> %vcvtx_f32_f641.i
901 define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %a, <2 x double> %b) #0 {
902 ; CHECK: fcvtxn2 v{{[0-9]+}}.4s, v{{[0-9]+}}.2d
903 %vcvtx_f32_f641.i.i = tail call <2 x float> @llvm.aarch64.neon.vcvtxn.v2f32.v2f64(<2 x double> %b) #4
904 %shuffle.i = shufflevector <2 x float> %a, <2 x float> %vcvtx_f32_f641.i.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
905 ret <4 x float> %shuffle.i
908 define <2 x double> @test_vcvt_f64_f32(<2 x float> %a) #0 {
909 ; CHECK: fcvtl v{{[0-9]+}}.2d, v{{[0-9]+}}.2s
910 %vcvt.i = fpext <2 x float> %a to <2 x double>
911 ret <2 x double> %vcvt.i
914 define <2 x double> @test_vcvt_high_f64_f32(<4 x float> %a) #0 {
915 ; CHECK: fcvtl2 v{{[0-9]+}}.2d, v{{[0-9]+}}.4s
916 %shuffle.i.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 2, i32 3>
917 %vcvt.i.i = fpext <2 x float> %shuffle.i.i to <2 x double>
918 ret <2 x double> %vcvt.i.i
921 define <2 x float> @test_vrndn_f32(<2 x float> %a) #0 {
922 ; CHECK: frintn v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
923 %vrndn1.i = tail call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float> %a) #4
924 ret <2 x float> %vrndn1.i
927 define <4 x float> @test_vrndnq_f32(<4 x float> %a) #0 {
928 ; CHECK: frintn v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
929 %vrndn1.i = tail call <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float> %a) #4
930 ret <4 x float> %vrndn1.i
933 define <2 x double> @test_vrndnq_f64(<2 x double> %a) #0 {
934 ; CHECK: frintn v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
935 %vrndn1.i = tail call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double> %a) #4
936 ret <2 x double> %vrndn1.i
939 define <2 x float> @test_vrnda_f32(<2 x float> %a) #0 {
940 ; CHECK: frinta v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
941 %vrnda1.i = tail call <2 x float> @llvm.round.v2f32(<2 x float> %a) #4
942 ret <2 x float> %vrnda1.i
945 define <4 x float> @test_vrndaq_f32(<4 x float> %a) #0 {
946 ; CHECK: frinta v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
947 %vrnda1.i = tail call <4 x float> @llvm.round.v4f32(<4 x float> %a) #4
948 ret <4 x float> %vrnda1.i
951 define <2 x double> @test_vrndaq_f64(<2 x double> %a) #0 {
952 ; CHECK: frinta v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
953 %vrnda1.i = tail call <2 x double> @llvm.round.v2f64(<2 x double> %a) #4
954 ret <2 x double> %vrnda1.i
957 define <2 x float> @test_vrndp_f32(<2 x float> %a) #0 {
958 ; CHECK: frintp v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
959 %vrndp1.i = tail call <2 x float> @llvm.ceil.v2f32(<2 x float> %a) #4
960 ret <2 x float> %vrndp1.i
963 define <4 x float> @test_vrndpq_f32(<4 x float> %a) #0 {
964 ; CHECK: frintp v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
965 %vrndp1.i = tail call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) #4
966 ret <4 x float> %vrndp1.i
969 define <2 x double> @test_vrndpq_f64(<2 x double> %a) #0 {
970 ; CHECK: frintp v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
971 %vrndp1.i = tail call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) #4
972 ret <2 x double> %vrndp1.i
975 define <2 x float> @test_vrndm_f32(<2 x float> %a) #0 {
976 ; CHECK: frintm v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
977 %vrndm1.i = tail call <2 x float> @llvm.floor.v2f32(<2 x float> %a) #4
978 ret <2 x float> %vrndm1.i
981 define <4 x float> @test_vrndmq_f32(<4 x float> %a) #0 {
982 ; CHECK: frintm v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
983 %vrndm1.i = tail call <4 x float> @llvm.floor.v4f32(<4 x float> %a) #4
984 ret <4 x float> %vrndm1.i
987 define <2 x double> @test_vrndmq_f64(<2 x double> %a) #0 {
988 ; CHECK: frintm v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
989 %vrndm1.i = tail call <2 x double> @llvm.floor.v2f64(<2 x double> %a) #4
990 ret <2 x double> %vrndm1.i
993 define <2 x float> @test_vrndx_f32(<2 x float> %a) #0 {
994 ; CHECK: frintx v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
995 %vrndx1.i = tail call <2 x float> @llvm.rint.v2f32(<2 x float> %a) #4
996 ret <2 x float> %vrndx1.i
999 define <4 x float> @test_vrndxq_f32(<4 x float> %a) #0 {
1000 ; CHECK: frintx v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1001 %vrndx1.i = tail call <4 x float> @llvm.rint.v4f32(<4 x float> %a) #4
1002 ret <4 x float> %vrndx1.i
1005 define <2 x double> @test_vrndxq_f64(<2 x double> %a) #0 {
1006 ; CHECK: frintx v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1007 %vrndx1.i = tail call <2 x double> @llvm.rint.v2f64(<2 x double> %a) #4
1008 ret <2 x double> %vrndx1.i
1011 define <2 x float> @test_vrnd_f32(<2 x float> %a) #0 {
1012 ; CHECK: frintz v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1013 %vrnd1.i = tail call <2 x float> @llvm.trunc.v2f32(<2 x float> %a) #4
1014 ret <2 x float> %vrnd1.i
1017 define <4 x float> @test_vrndq_f32(<4 x float> %a) #0 {
1018 ; CHECK: frintz v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1019 %vrnd1.i = tail call <4 x float> @llvm.trunc.v4f32(<4 x float> %a) #4
1020 ret <4 x float> %vrnd1.i
1023 define <2 x double> @test_vrndq_f64(<2 x double> %a) #0 {
1024 ; CHECK: frintz v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1025 %vrnd1.i = tail call <2 x double> @llvm.trunc.v2f64(<2 x double> %a) #4
1026 ret <2 x double> %vrnd1.i
1029 define <2 x float> @test_vrndi_f32(<2 x float> %a) #0 {
1030 ; CHECK: frinti v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1031 %vrndi1.i = tail call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %a) #4
1032 ret <2 x float> %vrndi1.i
1035 define <4 x float> @test_vrndiq_f32(<4 x float> %a) #0 {
1036 ; CHECK: frinti v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1037 %vrndi1.i = tail call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a) #4
1038 ret <4 x float> %vrndi1.i
1041 define <2 x double> @test_vrndiq_f64(<2 x double> %a) #0 {
1042 ; CHECK: frinti v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1043 %vrndi1.i = tail call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %a) #4
1044 ret <2 x double> %vrndi1.i
1047 define <2 x i32> @test_vcvt_s32_f32(<2 x float> %a) #0 {
1048 ; CHECK: fcvtzs v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1049 %vcvt.i = fptosi <2 x float> %a to <2 x i32>
1050 ret <2 x i32> %vcvt.i
1053 define <4 x i32> @test_vcvtq_s32_f32(<4 x float> %a) #0 {
1054 ; CHECK: fcvtzs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1055 %vcvt.i = fptosi <4 x float> %a to <4 x i32>
1056 ret <4 x i32> %vcvt.i
1059 define <2 x i64> @test_vcvtq_s64_f64(<2 x double> %a) #0 {
1060 ; CHECK: fcvtzs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1061 %vcvt.i = fptosi <2 x double> %a to <2 x i64>
1062 ret <2 x i64> %vcvt.i
1065 define <2 x i32> @test_vcvt_u32_f32(<2 x float> %a) #0 {
1066 ; CHECK: fcvtzu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1067 %vcvt.i = fptoui <2 x float> %a to <2 x i32>
1068 ret <2 x i32> %vcvt.i
1071 define <4 x i32> @test_vcvtq_u32_f32(<4 x float> %a) #0 {
1072 ; CHECK: fcvtzu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1073 %vcvt.i = fptoui <4 x float> %a to <4 x i32>
1074 ret <4 x i32> %vcvt.i
1077 define <2 x i64> @test_vcvtq_u64_f64(<2 x double> %a) #0 {
1078 ; CHECK: fcvtzu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1079 %vcvt.i = fptoui <2 x double> %a to <2 x i64>
1080 ret <2 x i64> %vcvt.i
1083 define <2 x i64> @test_vcvt_s64_f32(<2 x float> %a) #0 {
1084 ; CHECK: fcvtl v{{[0-9]+}}.2d, v{{[0-9]+}}.2s
1085 ; CHECK: fcvtzs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1086 %vcvt.i = fptosi <2 x float> %a to <2 x i64>
1087 ret <2 x i64> %vcvt.i
1090 define <2 x i64> @test_vcvt_u64_f32(<2 x float> %a) #0 {
1091 ; CHECK: fcvtl v{{[0-9]+}}.2d, v{{[0-9]+}}.2s
1092 ; CHECK: fcvtzu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1093 %vcvt.i = fptoui <2 x float> %a to <2 x i64>
1094 ret <2 x i64> %vcvt.i
1097 define <4 x i16> @test_vcvt_s16_f32(<4 x float> %a) #0 {
1098 ; CHECK: fcvtzs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1099 ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
1100 %vcvt.i = fptosi <4 x float> %a to <4 x i16>
1101 ret <4 x i16> %vcvt.i
1104 define <4 x i16> @test_vcvt_u16_f32(<4 x float> %a) #0 {
1105 ; CHECK: fcvtzu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1106 ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
1107 %vcvt.i = fptoui <4 x float> %a to <4 x i16>
1108 ret <4 x i16> %vcvt.i
1111 define <2 x i32> @test_vcvt_s32_f64(<2 x double> %a) #0 {
1112 ; CHECK: fcvtzs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1113 ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
1114 %vcvt.i = fptosi <2 x double> %a to <2 x i32>
1115 ret <2 x i32> %vcvt.i
1118 define <2 x i32> @test_vcvt_u32_f64(<2 x double> %a) #0 {
1119 ; CHECK: fcvtzu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1120 ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
1121 %vcvt.i = fptoui <2 x double> %a to <2 x i32>
1122 ret <2 x i32> %vcvt.i
1125 define <1 x i8> @test_vcvt_s8_f64(<1 x double> %a) #0 {
1126 ; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
1127 ; CHECK: ins v{{[0-9]+}}.b[0], w{{[0-9]+}}
1128 %vcvt.i = fptosi <1 x double> %a to <1 x i8>
1129 ret <1 x i8> %vcvt.i
1132 define <1 x i8> @test_vcvt_u8_f64(<1 x double> %a) #0 {
1133 ; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
1134 ; CHECK: ins v{{[0-9]+}}.b[0], w{{[0-9]+}}
1135 %vcvt.i = fptoui <1 x double> %a to <1 x i8>
1136 ret <1 x i8> %vcvt.i
1139 define <1 x i16> @test_vcvt_s16_f64(<1 x double> %a) #0 {
1140 ; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
1141 ; CHECK: ins v{{[0-9]+}}.h[0], w{{[0-9]+}}
1142 %vcvt.i = fptosi <1 x double> %a to <1 x i16>
1143 ret <1 x i16> %vcvt.i
1146 define <1 x i16> @test_vcvt_u16_f64(<1 x double> %a) #0 {
1147 ; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
1148 ; CHECK: ins v{{[0-9]+}}.h[0], w{{[0-9]+}}
1149 %vcvt.i = fptoui <1 x double> %a to <1 x i16>
1150 ret <1 x i16> %vcvt.i
1153 define <1 x i32> @test_vcvt_s32_f64_v1(<1 x double> %a) #0 {
1154 ; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
1155 ; CHECK: fmov s{{[0-9]+}}, w{{[0-9]+}}
1156 %vcvt.i = fptosi <1 x double> %a to <1 x i32>
1157 ret <1 x i32> %vcvt.i
1160 define <1 x i32> @test_vcvt_u32_f64_v1(<1 x double> %a) #0 {
1161 ; CHECK: fcvtzu w{{[0-9]+}}, d{{[0-9]+}}
1162 ; CHECK: fmov s{{[0-9]+}}, w{{[0-9]+}}
1163 %vcvt.i = fptoui <1 x double> %a to <1 x i32>
1164 ret <1 x i32> %vcvt.i
1167 define <2 x i32> @test_vcvtn_s32_f32(<2 x float> %a) {
1168 ; CHECK-LABEL: test_vcvtn_s32_f32
1169 ; CHECK: fcvtns v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1170 %vcvtns_f321.i = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %a)
1171 ret <2 x i32> %vcvtns_f321.i
1174 define <4 x i32> @test_vcvtnq_s32_f32(<4 x float> %a) {
1175 ; CHECK-LABEL: test_vcvtnq_s32_f32
1176 ; CHECK: fcvtns v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1177 %vcvtns_f321.i = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %a)
1178 ret <4 x i32> %vcvtns_f321.i
1181 define <2 x i64> @test_vcvtnq_s64_f64(<2 x double> %a) {
1182 ; CHECK-LABEL: test_vcvtnq_s64_f64
1183 ; CHECK: fcvtns v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1184 %vcvtns_f641.i = call <2 x i64> @llvm.arm.neon.vcvtns.v2i64.v2f64(<2 x double> %a)
1185 ret <2 x i64> %vcvtns_f641.i
1188 define <2 x i32> @test_vcvtn_u32_f32(<2 x float> %a) {
1189 ; CHECK-LABEL: test_vcvtn_u32_f32
1190 ; CHECK: fcvtnu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1191 %vcvtnu_f321.i = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %a)
1192 ret <2 x i32> %vcvtnu_f321.i
1195 define <4 x i32> @test_vcvtnq_u32_f32(<4 x float> %a) {
1196 ; CHECK-LABEL: test_vcvtnq_u32_f32
1197 ; CHECK: fcvtnu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1198 %vcvtnu_f321.i = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %a)
1199 ret <4 x i32> %vcvtnu_f321.i
1202 define <2 x i64> @test_vcvtnq_u64_f64(<2 x double> %a) {
1203 ; CHECK-LABEL: test_vcvtnq_u64_f64
1204 ; CHECK: fcvtnu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1205 %vcvtnu_f641.i = call <2 x i64> @llvm.arm.neon.vcvtnu.v2i64.v2f64(<2 x double> %a)
1206 ret <2 x i64> %vcvtnu_f641.i
1209 define <2 x i32> @test_vcvtp_s32_f32(<2 x float> %a) {
1210 ; CHECK-LABEL: test_vcvtp_s32_f32
1211 ; CHECK: fcvtps v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1212 %vcvtps_f321.i = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %a)
1213 ret <2 x i32> %vcvtps_f321.i
1216 define <4 x i32> @test_vcvtpq_s32_f32(<4 x float> %a) {
1217 ; CHECK-LABEL: test_vcvtpq_s32_f32
1218 ; CHECK: fcvtps v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1219 %vcvtps_f321.i = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %a)
1220 ret <4 x i32> %vcvtps_f321.i
1223 define <2 x i64> @test_vcvtpq_s64_f64(<2 x double> %a) {
1224 ; CHECK-LABEL: test_vcvtpq_s64_f64
1225 ; CHECK: fcvtps v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1226 %vcvtps_f641.i = call <2 x i64> @llvm.arm.neon.vcvtps.v2i64.v2f64(<2 x double> %a)
1227 ret <2 x i64> %vcvtps_f641.i
1230 define <2 x i32> @test_vcvtp_u32_f32(<2 x float> %a) {
1231 ; CHECK-LABEL: test_vcvtp_u32_f32
1232 ; CHECK: fcvtpu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1233 %vcvtpu_f321.i = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %a)
1234 ret <2 x i32> %vcvtpu_f321.i
1237 define <4 x i32> @test_vcvtpq_u32_f32(<4 x float> %a) {
1238 ; CHECK-LABEL: test_vcvtpq_u32_f32
1239 ; CHECK: fcvtpu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1240 %vcvtpu_f321.i = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %a)
1241 ret <4 x i32> %vcvtpu_f321.i
1244 define <2 x i64> @test_vcvtpq_u64_f64(<2 x double> %a) {
1245 ; CHECK-LABEL: test_vcvtpq_u64_f64
1246 ; CHECK: fcvtpu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1247 %vcvtpu_f641.i = call <2 x i64> @llvm.arm.neon.vcvtpu.v2i64.v2f64(<2 x double> %a)
1248 ret <2 x i64> %vcvtpu_f641.i
1251 define <2 x i32> @test_vcvtm_s32_f32(<2 x float> %a) {
1252 ; CHECK-LABEL: test_vcvtm_s32_f32
1253 ; CHECK: fcvtms v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1254 %vcvtms_f321.i = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %a)
1255 ret <2 x i32> %vcvtms_f321.i
1258 define <4 x i32> @test_vcvtmq_s32_f32(<4 x float> %a) {
1259 ; CHECK-LABEL: test_vcvtmq_s32_f32
1260 ; CHECK: fcvtms v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1261 %vcvtms_f321.i = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %a)
1262 ret <4 x i32> %vcvtms_f321.i
1265 define <2 x i64> @test_vcvtmq_s64_f64(<2 x double> %a) {
1266 ; CHECK-LABEL: test_vcvtmq_s64_f64
1267 ; CHECK: fcvtms v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1268 %vcvtms_f641.i = call <2 x i64> @llvm.arm.neon.vcvtms.v2i64.v2f64(<2 x double> %a)
1269 ret <2 x i64> %vcvtms_f641.i
1272 define <2 x i32> @test_vcvtm_u32_f32(<2 x float> %a) {
1273 ; CHECK-LABEL: test_vcvtm_u32_f32
1274 ; CHECK: fcvtmu v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1275 %vcvtmu_f321.i = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %a)
1276 ret <2 x i32> %vcvtmu_f321.i
1279 define <4 x i32> @test_vcvtmq_u32_f32(<4 x float> %a) {
1280 ; CHECK-LABEL: test_vcvtmq_u32_f32
1281 ; CHECK: fcvtmu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1282 %vcvtmu_f321.i = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %a)
1283 ret <4 x i32> %vcvtmu_f321.i
1286 define <2 x i64> @test_vcvtmq_u64_f64(<2 x double> %a) {
1287 ; CHECK-LABEL: test_vcvtmq_u64_f64
1288 ; CHECK: fcvtmu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1289 %vcvtmu_f641.i = call <2 x i64> @llvm.arm.neon.vcvtmu.v2i64.v2f64(<2 x double> %a)
1290 ret <2 x i64> %vcvtmu_f641.i
1293 define <2 x i32> @test_vcvta_s32_f32(<2 x float> %a) {
1294 ; CHECK-LABEL: test_vcvta_s32_f32
1295 ; CHECK: fcvtas v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1296 %vcvtas_f321.i = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %a)
1297 ret <2 x i32> %vcvtas_f321.i
1300 define <4 x i32> @test_vcvtaq_s32_f32(<4 x float> %a) {
1301 ; CHECK-LABEL: test_vcvtaq_s32_f32
1302 ; CHECK: fcvtas v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1303 %vcvtas_f321.i = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %a)
1304 ret <4 x i32> %vcvtas_f321.i
1307 define <2 x i64> @test_vcvtaq_s64_f64(<2 x double> %a) {
1308 ; CHECK-LABEL: test_vcvtaq_s64_f64
1309 ; CHECK: fcvtas v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1310 %vcvtas_f641.i = call <2 x i64> @llvm.arm.neon.vcvtas.v2i64.v2f64(<2 x double> %a)
1311 ret <2 x i64> %vcvtas_f641.i
1314 define <2 x i32> @test_vcvta_u32_f32(<2 x float> %a) {
1315 ; CHECK-LABEL: test_vcvta_u32_f32
1316 ; CHECK: fcvtau v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1317 %vcvtau_f321.i = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %a)
1318 ret <2 x i32> %vcvtau_f321.i
1321 define <4 x i32> @test_vcvtaq_u32_f32(<4 x float> %a) {
1322 ; CHECK-LABEL: test_vcvtaq_u32_f32
1323 ; CHECK: fcvtau v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1324 %vcvtau_f321.i = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %a)
1325 ret <4 x i32> %vcvtau_f321.i
1328 define <2 x i64> @test_vcvtaq_u64_f64(<2 x double> %a) {
1329 ; CHECK-LABEL: test_vcvtaq_u64_f64
1330 ; CHECK: fcvtau v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1331 %vcvtau_f641.i = call <2 x i64> @llvm.arm.neon.vcvtau.v2i64.v2f64(<2 x double> %a)
1332 ret <2 x i64> %vcvtau_f641.i
1335 define <2 x float> @test_vrsqrte_f32(<2 x float> %a) #0 {
1336 ; CHECK: frsqrte v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1337 %vrsqrte1.i = tail call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %a) #4
1338 ret <2 x float> %vrsqrte1.i
1341 define <4 x float> @test_vrsqrteq_f32(<4 x float> %a) #0 {
1342 ; CHECK: frsqrte v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1343 %vrsqrte1.i = tail call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %a) #4
1344 ret <4 x float> %vrsqrte1.i
1347 define <2 x double> @test_vrsqrteq_f64(<2 x double> %a) #0 {
1348 ; CHECK: frsqrte v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1349 %vrsqrte1.i = tail call <2 x double> @llvm.arm.neon.vrsqrte.v2f64(<2 x double> %a) #4
1350 ret <2 x double> %vrsqrte1.i
1353 define <2 x float> @test_vrecpe_f32(<2 x float> %a) #0 {
1354 ; CHECK: frecpe v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1355 %vrecpe1.i = tail call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %a) #4
1356 ret <2 x float> %vrecpe1.i
1359 define <4 x float> @test_vrecpeq_f32(<4 x float> %a) #0 {
1360 ; CHECK: frecpe v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1361 %vrecpe1.i = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %a) #4
1362 ret <4 x float> %vrecpe1.i
1365 define <2 x double> @test_vrecpeq_f64(<2 x double> %a) #0 {
1366 ; CHECK: frecpe v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1367 %vrecpe1.i = tail call <2 x double> @llvm.arm.neon.vrecpe.v2f64(<2 x double> %a) #4
1368 ret <2 x double> %vrecpe1.i
1371 define <2 x i32> @test_vrecpe_u32(<2 x i32> %a) #0 {
1372 ; CHECK: urecpe v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1373 %vrecpe1.i = tail call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %a) #4
1374 ret <2 x i32> %vrecpe1.i
1377 define <4 x i32> @test_vrecpeq_u32(<4 x i32> %a) #0 {
1378 ; CHECK: urecpe v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1379 %vrecpe1.i = tail call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %a) #4
1380 ret <4 x i32> %vrecpe1.i
1383 define <2 x float> @test_vsqrt_f32(<2 x float> %a) #0 {
1384 ; CHECK: fsqrt v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1385 %vsqrt1.i = tail call <2 x float> @llvm.sqrt.v2f32(<2 x float> %a) #4
1386 ret <2 x float> %vsqrt1.i
1389 define <4 x float> @test_vsqrtq_f32(<4 x float> %a) #0 {
1390 ; CHECK: fsqrt v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1391 %vsqrt1.i = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) #4
1392 ret <4 x float> %vsqrt1.i
1395 define <2 x double> @test_vsqrtq_f64(<2 x double> %a) #0 {
1396 ; CHECK: fsqrt v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1397 %vsqrt1.i = tail call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) #4
1398 ret <2 x double> %vsqrt1.i
1401 define <2 x float> @test_vcvt_f32_s32(<2 x i32> %a) #0 {
1402 ; CHECK: scvtf v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1403 %vcvt.i = sitofp <2 x i32> %a to <2 x float>
1404 ret <2 x float> %vcvt.i
1407 define <2 x float> @test_vcvt_f32_u32(<2 x i32> %a) #0 {
1408 ; CHECK: ucvtf v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
1409 %vcvt.i = uitofp <2 x i32> %a to <2 x float>
1410 ret <2 x float> %vcvt.i
1413 define <4 x float> @test_vcvtq_f32_s32(<4 x i32> %a) #0 {
1414 ; CHECK: scvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1415 %vcvt.i = sitofp <4 x i32> %a to <4 x float>
1416 ret <4 x float> %vcvt.i
1419 define <4 x float> @test_vcvtq_f32_u32(<4 x i32> %a) #0 {
1420 ; CHECK: ucvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1421 %vcvt.i = uitofp <4 x i32> %a to <4 x float>
1422 ret <4 x float> %vcvt.i
1425 define <2 x double> @test_vcvtq_f64_s64(<2 x i64> %a) #0 {
1426 ; CHECK: scvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1427 %vcvt.i = sitofp <2 x i64> %a to <2 x double>
1428 ret <2 x double> %vcvt.i
1431 define <2 x double> @test_vcvtq_f64_u64(<2 x i64> %a) #0 {
1432 ; CHECK: ucvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1433 %vcvt.i = uitofp <2 x i64> %a to <2 x double>
1434 ret <2 x double> %vcvt.i
1437 define <2 x float> @test_vcvt_f32_s64(<2 x i64> %a) #0 {
1438 ; CHECK: scvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1439 ; CHECK: fcvtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
1440 %vcvt.i = sitofp <2 x i64> %a to <2 x float>
1441 ret <2 x float> %vcvt.i
1444 define <2 x float> @test_vcvt_f32_u64(<2 x i64> %a) #0 {
1445 ; CHECK: ucvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1446 ; CHECK: fcvtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
1447 %vcvt.i = uitofp <2 x i64> %a to <2 x float>
1448 ret <2 x float> %vcvt.i
1451 define <4 x float> @test_vcvt_f32_s16(<4 x i16> %a) #0 {
1452 ; CHECK: sshll v{{[0-9]+}}.4s, v{{[0-9]+}}.4h, #0
1453 ; CHECK: scvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1454 %vcvt.i = sitofp <4 x i16> %a to <4 x float>
1455 ret <4 x float> %vcvt.i
1458 define <4 x float> @test_vcvt_f32_u16(<4 x i16> %a) #0 {
1459 ; CHECK: ushll v{{[0-9]+}}.4s, v{{[0-9]+}}.4h, #0
1460 ; CHECK: ucvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
1461 %vcvt.i = uitofp <4 x i16> %a to <4 x float>
1462 ret <4 x float> %vcvt.i
1465 define <2 x double> @test_vcvt_f64_s32(<2 x i32> %a) #0 {
1466 ; CHECK: sshll v{{[0-9]+}}.2d, v{{[0-9]+}}.2s, #0
1467 ; CHECK: scvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1468 %vcvt.i = sitofp <2 x i32> %a to <2 x double>
1469 ret <2 x double> %vcvt.i
1472 define <2 x double> @test_vcvt_f64_u32(<2 x i32> %a) #0 {
1473 ; CHECK: ushll v{{[0-9]+}}.2d, v{{[0-9]+}}.2s, #0
1474 ; CHECK: ucvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
1475 %vcvt.i = uitofp <2 x i32> %a to <2 x double>
1476 ret <2 x double> %vcvt.i
1479 define <1 x double> @test_vcvt_f64_s8(<1 x i8> %a) #0 {
1480 ; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.b[0]
1481 ; CHECK: sxtb w{{[0-9]+}}, w{{[0-9]+}}
1482 ; CHECK: scvtf d{{[0-9]+}}, w{{[0-9]+}}
1483 %vcvt.i = sitofp <1 x i8> %a to <1 x double>
1484 ret <1 x double> %vcvt.i
1487 define <1 x double> @test_vcvt_f64_u8(<1 x i8> %a) #0 {
1488 ; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.b[0]
1489 ; CHECK: and w{{[0-9]+}}, w{{[0-9]+}}, #0xff
1490 ; CHECK: ucvtf d{{[0-9]+}}, w{{[0-9]+}}
1491 %vcvt.i = uitofp <1 x i8> %a to <1 x double>
1492 ret <1 x double> %vcvt.i
1495 define <1 x double> @test_vcvt_f64_s16(<1 x i16> %a) #0 {
1496 ; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.h[0]
1497 ; CHECK: sxth w{{[0-9]+}}, w{{[0-9]+}}
1498 ; CHECK: scvtf d{{[0-9]+}}, w{{[0-9]+}}
1499 %vcvt.i = sitofp <1 x i16> %a to <1 x double>
1500 ret <1 x double> %vcvt.i
1503 define <1 x double> @test_vcvt_f64_u16(<1 x i16> %a) #0 {
1504 ; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.h[0]
1505 ; CHECK: and w{{[0-9]+}}, w{{[0-9]+}}, #0xffff
1506 ; CHECK: ucvtf d{{[0-9]+}}, w{{[0-9]+}}
1507 %vcvt.i = uitofp <1 x i16> %a to <1 x double>
1508 ret <1 x double> %vcvt.i
1511 define <1 x double> @test_vcvt_f64_s32_v1(<1 x i32> %a) #0 {
1512 ; CHECK: fmov w{{[0-9]+}}, s{{[0-9]+}}
1513 ; CHECK: scvtf d{{[0-9]+}}, w{{[0-9]+}}
1514 %vcvt.i = sitofp <1 x i32> %a to <1 x double>
1515 ret <1 x double> %vcvt.i
1518 define <1 x double> @test_vcvt_f64_u32_v1(<1 x i32> %a) #0 {
1519 ; CHECK: fmov w{{[0-9]+}}, s{{[0-9]+}}
1520 ; CHECK: ucvtf d{{[0-9]+}}, w{{[0-9]+}}
1521 %vcvt.i = uitofp <1 x i32> %a to <1 x double>
1522 ret <1 x double> %vcvt.i
1525 declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) #2
1527 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #2
1529 declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #2
1531 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) #2
1533 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) #2
1535 declare <2 x double> @llvm.arm.neon.vrecpe.v2f64(<2 x double>) #2
1537 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) #2
1539 declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) #2
1541 declare <2 x double> @llvm.arm.neon.vrsqrte.v2f64(<2 x double>) #2
1543 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) #2
1545 declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) #2
1547 declare <2 x i64> @llvm.arm.neon.vcvtau.v2i64.v2f64(<2 x double>)
1549 declare <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float>)
1551 declare <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float>)
1553 declare <2 x i64> @llvm.arm.neon.vcvtas.v2i64.v2f64(<2 x double>)
1555 declare <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float>)
1557 declare <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float>)
1559 declare <2 x i64> @llvm.arm.neon.vcvtmu.v2i64.v2f64(<2 x double>)
1561 declare <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float>)
1563 declare <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float>)
1565 declare <2 x i64> @llvm.arm.neon.vcvtms.v2i64.v2f64(<2 x double>)
1567 declare <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float>)
1569 declare <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float>)
1571 declare <2 x i64> @llvm.arm.neon.vcvtpu.v2i64.v2f64(<2 x double>)
1573 declare <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float>)
1575 declare <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float>)
1577 declare <2 x i64> @llvm.arm.neon.vcvtps.v2i64.v2f64(<2 x double>)
1579 declare <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float>)
1581 declare <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float>)
1583 declare <2 x i64> @llvm.arm.neon.vcvtnu.v2i64.v2f64(<2 x double>)
1585 declare <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float>)
1587 declare <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float>)
1589 declare <2 x i64> @llvm.arm.neon.vcvtns.v2i64.v2f64(<2 x double>)
1591 declare <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float>)
1593 declare <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float>)
1595 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #3
1597 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #3
1599 declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #3
1601 declare <2 x double> @llvm.trunc.v2f64(<2 x double>) #3
1603 declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #3
1605 declare <2 x float> @llvm.trunc.v2f32(<2 x float>) #3
1607 declare <2 x double> @llvm.rint.v2f64(<2 x double>) #3
1609 declare <4 x float> @llvm.rint.v4f32(<4 x float>) #3
1611 declare <2 x float> @llvm.rint.v2f32(<2 x float>) #3
1613 declare <2 x double> @llvm.floor.v2f64(<2 x double>) #3
1615 declare <4 x float> @llvm.floor.v4f32(<4 x float>) #3
1617 declare <2 x float> @llvm.floor.v2f32(<2 x float>) #3
1619 declare <2 x double> @llvm.ceil.v2f64(<2 x double>) #3
1621 declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #3
1623 declare <2 x float> @llvm.ceil.v2f32(<2 x float>) #3
1625 declare <2 x double> @llvm.round.v2f64(<2 x double>) #3
1627 declare <4 x float> @llvm.round.v4f32(<4 x float>) #3
1629 declare <2 x float> @llvm.round.v2f32(<2 x float>) #3
1631 declare <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>) #2
1633 declare <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float>) #2
1635 declare <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float>) #2
1637 declare <2 x float> @llvm.aarch64.neon.vcvtxn.v2f32.v2f64(<2 x double>) #2
1639 declare <2 x float> @llvm.aarch64.neon.fcvtn.v2f32.v2f64(<2 x double>) #2
1641 declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) #2
1643 declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) #2
1645 declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) #2
1647 declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) #2
1649 declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) #2
1651 declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) #2
1653 declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) #2
1655 declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) #2
1657 declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) #2
1659 declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) #2
1661 declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) #2
1663 declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) #2
1665 declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) #2
1667 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) #2
1669 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) #2
1671 declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) #2
1673 declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) #2
1675 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) #2
1677 declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) #2
1679 declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) #2
1681 declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) #2
1683 declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) #2
1685 declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) #2
1687 declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) #2
1689 declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) #2
1691 declare <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64>, <2 x i64>) #2
1693 declare <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32>, <4 x i32>) #2
1695 declare <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) #2
1697 declare <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) #2
1699 declare <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) #2
1701 declare <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) #2
1703 declare <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) #2
1705 declare <2 x double> @llvm.fabs.v2f64(<2 x double>) #3
1707 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #3
1709 declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #3
1711 declare <2 x i64> @llvm.arm.neon.vabs.v2i64(<2 x i64>) #2
1713 declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) #2
1715 declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) #2
1717 declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) #2
1719 declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) #2
1721 declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) #2
1723 declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) #2
1725 declare <2 x i64> @llvm.arm.neon.vqneg.v2i64(<2 x i64>) #2
1727 declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) #2
1729 declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) #2
1731 declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) #2
1733 declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) #2
1735 declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) #2
1737 declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) #2
1739 declare <2 x i64> @llvm.arm.neon.vqabs.v2i64(<2 x i64>) #2
1741 declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) #2
1743 declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) #2
1745 declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) #2
1747 declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) #2
1749 declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) #2
1751 declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) #2
1753 declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) #2
1755 declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) #2
1757 declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) #2
1759 declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) #2
1761 declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) #2
1763 declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) #2
1765 declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) #2
1767 declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) #2
1769 declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) #2
1771 declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) #2
1773 declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) #2
1775 declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) #2
1777 declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) #2
1779 declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) #2
1781 declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) #2
1783 declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) #2
1785 declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) #2
1787 declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) #2
1789 declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) #2
1791 declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) #2
1793 declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) #2
1795 declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) #2
1797 declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) #2
1799 declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) #2
1801 declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) #2
1803 declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) #2
1806 define <1 x i64> @test_vcvt_s64_f64(<1 x double> %a) {
1807 ; CHECK-LABEL: test_vcvt_s64_f64
1808 ; CHECK: fcvtzs d{{[0-9]+}}, d{{[0-9]+}}
1809 %1 = fptosi <1 x double> %a to <1 x i64>
1813 define <1 x i64> @test_vcvt_u64_f64(<1 x double> %a) {
1814 ; CHECK-LABEL: test_vcvt_u64_f64
1815 ; CHECK: fcvtzu d{{[0-9]+}}, d{{[0-9]+}}
1816 %1 = fptoui <1 x double> %a to <1 x i64>
1820 define <1 x i64> @test_vcvtn_s64_f64(<1 x double> %a) {
1821 ; CHECK-LABEL: test_vcvtn_s64_f64
1822 ; CHECK: fcvtns d{{[0-9]+}}, d{{[0-9]+}}
1823 %1 = call <1 x i64> @llvm.arm.neon.vcvtns.v1i64.v1f64(<1 x double> %a)
1827 define <1 x i64> @test_vcvtn_u64_f64(<1 x double> %a) {
1828 ; CHECK-LABEL: test_vcvtn_u64_f64
1829 ; CHECK: fcvtnu d{{[0-9]+}}, d{{[0-9]+}}
1830 %1 = call <1 x i64> @llvm.arm.neon.vcvtnu.v1i64.v1f64(<1 x double> %a)
1834 define <1 x i64> @test_vcvtp_s64_f64(<1 x double> %a) {
1835 ; CHECK-LABEL: test_vcvtp_s64_f64
1836 ; CHECK: fcvtps d{{[0-9]+}}, d{{[0-9]+}}
1837 %1 = call <1 x i64> @llvm.arm.neon.vcvtps.v1i64.v1f64(<1 x double> %a)
1841 define <1 x i64> @test_vcvtp_u64_f64(<1 x double> %a) {
1842 ; CHECK-LABEL: test_vcvtp_u64_f64
1843 ; CHECK: fcvtpu d{{[0-9]+}}, d{{[0-9]+}}
1844 %1 = call <1 x i64> @llvm.arm.neon.vcvtpu.v1i64.v1f64(<1 x double> %a)
1848 define <1 x i64> @test_vcvtm_s64_f64(<1 x double> %a) {
1849 ; CHECK-LABEL: test_vcvtm_s64_f64
1850 ; CHECK: fcvtms d{{[0-9]+}}, d{{[0-9]+}}
1851 %1 = call <1 x i64> @llvm.arm.neon.vcvtms.v1i64.v1f64(<1 x double> %a)
1855 define <1 x i64> @test_vcvtm_u64_f64(<1 x double> %a) {
1856 ; CHECK-LABEL: test_vcvtm_u64_f64
1857 ; CHECK: fcvtmu d{{[0-9]+}}, d{{[0-9]+}}
1858 %1 = call <1 x i64> @llvm.arm.neon.vcvtmu.v1i64.v1f64(<1 x double> %a)
1862 define <1 x i64> @test_vcvta_s64_f64(<1 x double> %a) {
1863 ; CHECK-LABEL: test_vcvta_s64_f64
1864 ; CHECK: fcvtas d{{[0-9]+}}, d{{[0-9]+}}
1865 %1 = call <1 x i64> @llvm.arm.neon.vcvtas.v1i64.v1f64(<1 x double> %a)
1869 define <1 x i64> @test_vcvta_u64_f64(<1 x double> %a) {
1870 ; CHECK-LABEL: test_vcvta_u64_f64
1871 ; CHECK: fcvtau d{{[0-9]+}}, d{{[0-9]+}}
1872 %1 = call <1 x i64> @llvm.arm.neon.vcvtau.v1i64.v1f64(<1 x double> %a)
1876 define <1 x double> @test_vcvt_f64_s64(<1 x i64> %a) {
1877 ; CHECK-LABEL: test_vcvt_f64_s64
1878 ; CHECK: scvtf d{{[0-9]+}}, d{{[0-9]+}}
1879 %1 = sitofp <1 x i64> %a to <1 x double>
1883 define <1 x double> @test_vcvt_f64_u64(<1 x i64> %a) {
1884 ; CHECK-LABEL: test_vcvt_f64_u64
1885 ; CHECK: ucvtf d{{[0-9]+}}, d{{[0-9]+}}
1886 %1 = uitofp <1 x i64> %a to <1 x double>
1890 declare <1 x i64> @llvm.arm.neon.vcvtau.v1i64.v1f64(<1 x double>)
1891 declare <1 x i64> @llvm.arm.neon.vcvtas.v1i64.v1f64(<1 x double>)
1892 declare <1 x i64> @llvm.arm.neon.vcvtmu.v1i64.v1f64(<1 x double>)
1893 declare <1 x i64> @llvm.arm.neon.vcvtms.v1i64.v1f64(<1 x double>)
1894 declare <1 x i64> @llvm.arm.neon.vcvtpu.v1i64.v1f64(<1 x double>)
1895 declare <1 x i64> @llvm.arm.neon.vcvtps.v1i64.v1f64(<1 x double>)
1896 declare <1 x i64> @llvm.arm.neon.vcvtnu.v1i64.v1f64(<1 x double>)
1897 declare <1 x i64> @llvm.arm.neon.vcvtns.v1i64.v1f64(<1 x double>)
1899 define <1 x double> @test_vrndn_f64(<1 x double> %a) {
1900 ; CHECK-LABEL: test_vrndn_f64
1901 ; CHECK: frintn d{{[0-9]+}}, d{{[0-9]+}}
1902 %1 = tail call <1 x double> @llvm.aarch64.neon.frintn.v1f64(<1 x double> %a)
1906 define <1 x double> @test_vrnda_f64(<1 x double> %a) {
1907 ; CHECK-LABEL: test_vrnda_f64
1908 ; CHECK: frinta d{{[0-9]+}}, d{{[0-9]+}}
1909 %1 = tail call <1 x double> @llvm.round.v1f64(<1 x double> %a)
1913 define <1 x double> @test_vrndp_f64(<1 x double> %a) {
1914 ; CHECK-LABEL: test_vrndp_f64
1915 ; CHECK: frintp d{{[0-9]+}}, d{{[0-9]+}}
1916 %1 = tail call <1 x double> @llvm.ceil.v1f64(<1 x double> %a)
1920 define <1 x double> @test_vrndm_f64(<1 x double> %a) {
1921 ; CHECK-LABEL: test_vrndm_f64
1922 ; CHECK: frintm d{{[0-9]+}}, d{{[0-9]+}}
1923 %1 = tail call <1 x double> @llvm.floor.v1f64(<1 x double> %a)
1927 define <1 x double> @test_vrndx_f64(<1 x double> %a) {
1928 ; CHECK-LABEL: test_vrndx_f64
1929 ; CHECK: frintx d{{[0-9]+}}, d{{[0-9]+}}
1930 %1 = tail call <1 x double> @llvm.rint.v1f64(<1 x double> %a)
1934 define <1 x double> @test_vrnd_f64(<1 x double> %a) {
1935 ; CHECK-LABEL: test_vrnd_f64
1936 ; CHECK: frintz d{{[0-9]+}}, d{{[0-9]+}}
1937 %1 = tail call <1 x double> @llvm.trunc.v1f64(<1 x double> %a)
1941 define <1 x double> @test_vrndi_f64(<1 x double> %a) {
1942 ; CHECK-LABEL: test_vrndi_f64
1943 ; CHECK: frinti d{{[0-9]+}}, d{{[0-9]+}}
1944 %1 = tail call <1 x double> @llvm.nearbyint.v1f64(<1 x double> %a)
1948 declare <1 x double> @llvm.nearbyint.v1f64(<1 x double>)
1949 declare <1 x double> @llvm.trunc.v1f64(<1 x double>)
1950 declare <1 x double> @llvm.rint.v1f64(<1 x double>)
1951 declare <1 x double> @llvm.floor.v1f64(<1 x double>)
1952 declare <1 x double> @llvm.ceil.v1f64(<1 x double>)
1953 declare <1 x double> @llvm.round.v1f64(<1 x double>)
1954 declare <1 x double> @llvm.aarch64.neon.frintn.v1f64(<1 x double>)
1956 define <1 x double> @test_vrsqrte_f64(<1 x double> %a) {
1957 ; CHECK-LABEL: test_vrsqrte_f64
1958 ; CHECK: frsqrte d{{[0-9]+}}, d{{[0-9]+}}
1959 %1 = tail call <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double> %a)
1963 define <1 x double> @test_vrecpe_f64(<1 x double> %a) {
1964 ; CHECK-LABEL: test_vrecpe_f64
1965 ; CHECK: frecpe d{{[0-9]+}}, d{{[0-9]+}}
1966 %1 = tail call <1 x double> @llvm.arm.neon.vrecpe.v1f64(<1 x double> %a)
1970 define <1 x double> @test_vsqrt_f64(<1 x double> %a) {
1971 ; CHECK-LABEL: test_vsqrt_f64
1972 ; CHECK: fsqrt d{{[0-9]+}}, d{{[0-9]+}}
1973 %1 = tail call <1 x double> @llvm.sqrt.v1f64(<1 x double> %a)
1977 define <1 x double> @test_vrecps_f64(<1 x double> %a, <1 x double> %b) {
1978 ; CHECK-LABEL: test_vrecps_f64
1979 ; CHECK: frecps d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
1980 %1 = tail call <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double> %a, <1 x double> %b)
1984 define <1 x double> @test_vrsqrts_f64(<1 x double> %a, <1 x double> %b) {
1985 ; CHECK-LABEL: test_vrsqrts_f64
1986 ; CHECK: frsqrts d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
1987 %1 = tail call <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double> %a, <1 x double> %b)
1991 declare <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double>, <1 x double>)
1992 declare <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double>, <1 x double>)
1993 declare <1 x double> @llvm.sqrt.v1f64(<1 x double>)
1994 declare <1 x double> @llvm.arm.neon.vrecpe.v1f64(<1 x double>)
1995 declare <1 x double> @llvm.arm.neon.vrsqrte.v1f64(<1 x double>)
1997 define i64 @test_vaddlv_s32(<2 x i32> %a) {
1998 ; CHECK-LABEL: test_vaddlv_s32
1999 ; CHECK: saddlp {{v[0-9]+}}.1d, {{v[0-9]+}}.2s
2000 %1 = tail call <1 x i64> @llvm.aarch64.neon.saddlv.v1i64.v2i32(<2 x i32> %a)
2001 %2 = extractelement <1 x i64> %1, i32 0
2005 define i64 @test_vaddlv_u32(<2 x i32> %a) {
2006 ; CHECK-LABEL: test_vaddlv_u32
2007 ; CHECK: uaddlp {{v[0-9]+}}.1d, {{v[0-9]+}}.2s
2008 %1 = tail call <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32> %a)
2009 %2 = extractelement <1 x i64> %1, i32 0
2013 declare <1 x i64> @llvm.aarch64.neon.saddlv.v1i64.v2i32(<2 x i32>)
2014 declare <1 x i64> @llvm.aarch64.neon.uaddlv.v1i64.v2i32(<2 x i32>)