1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 ;; Scalar Integer Compare
5 define i64 @test_vceqd(i64 %a, i64 %b) {
7 ; CHECK: cmeq {{d[0-9]+}}, {{d[0-9]}}, {{d[0-9]}}
9 %vceq.i = insertelement <1 x i64> undef, i64 %a, i32 0
10 %vceq1.i = insertelement <1 x i64> undef, i64 %b, i32 0
11 %vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64> %vceq.i, <1 x i64> %vceq1.i)
12 %0 = extractelement <1 x i64> %vceq2.i, i32 0
16 define i64 @test_vceqzd(i64 %a) {
18 ; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0
20 %vceqz.i = insertelement <1 x i64> undef, i64 %a, i32 0
21 %vceqz1.i = call <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64> %vceqz.i, <1 x i64> zeroinitializer)
22 %0 = extractelement <1 x i64> %vceqz1.i, i32 0
26 define i64 @test_vcged(i64 %a, i64 %b) {
28 ; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
30 %vcge.i = insertelement <1 x i64> undef, i64 %a, i32 0
31 %vcge1.i = insertelement <1 x i64> undef, i64 %b, i32 0
32 %vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
33 %0 = extractelement <1 x i64> %vcge2.i, i32 0
37 define i64 @test_vcgezd(i64 %a) {
39 ; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, #0x0
41 %vcgez.i = insertelement <1 x i64> undef, i64 %a, i32 0
42 %vcgez1.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcgez.i, <1 x i64> zeroinitializer)
43 %0 = extractelement <1 x i64> %vcgez1.i, i32 0
47 define i64 @test_vcgtd(i64 %a, i64 %b) {
49 ; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
51 %vcgt.i = insertelement <1 x i64> undef, i64 %a, i32 0
52 %vcgt1.i = insertelement <1 x i64> undef, i64 %b, i32 0
53 %vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
54 %0 = extractelement <1 x i64> %vcgt2.i, i32 0
58 define i64 @test_vcgtzd(i64 %a) {
60 ; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, #0x0
62 %vcgtz.i = insertelement <1 x i64> undef, i64 %a, i32 0
63 %vcgtz1.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgtz.i, <1 x i64> zeroinitializer)
64 %0 = extractelement <1 x i64> %vcgtz1.i, i32 0
68 define i64 @test_vcled(i64 %a, i64 %b) {
70 ; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
72 %vcgt.i = insertelement <1 x i64> undef, i64 %b, i32 0
73 %vcgt1.i = insertelement <1 x i64> undef, i64 %a, i32 0
74 %vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
75 %0 = extractelement <1 x i64> %vcgt2.i, i32 0
79 define i64 @test_vclezd(i64 %a) {
81 ; CHECK: cmle {{d[0-9]}}, {{d[0-9]}}, #0x0
83 %vclez.i = insertelement <1 x i64> undef, i64 %a, i32 0
84 %vclez1.i = call <1 x i64> @llvm.aarch64.neon.vclez(<1 x i64> %vclez.i, <1 x i64> zeroinitializer)
85 %0 = extractelement <1 x i64> %vclez1.i, i32 0
89 define i64 @test_vcltd(i64 %a, i64 %b) {
91 ; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
93 %vcge.i = insertelement <1 x i64> undef, i64 %b, i32 0
94 %vcge1.i = insertelement <1 x i64> undef, i64 %a, i32 0
95 %vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
96 %0 = extractelement <1 x i64> %vcge2.i, i32 0
100 define i64 @test_vcltzd(i64 %a) {
102 ; CHECK: cmlt {{d[0-9]}}, {{d[0-9]}}, #0x0
104 %vcltz.i = insertelement <1 x i64> undef, i64 %a, i32 0
105 %vcltz1.i = call <1 x i64> @llvm.aarch64.neon.vcltz(<1 x i64> %vcltz.i, <1 x i64> zeroinitializer)
106 %0 = extractelement <1 x i64> %vcltz1.i, i32 0
110 define i64 @test_vtstd(i64 %a, i64 %b) {
112 ; CHECK: cmtst {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
114 %vtst.i = insertelement <1 x i64> undef, i64 %a, i32 0
115 %vtst1.i = insertelement <1 x i64> undef, i64 %b, i32 0
116 %vtst2.i = call <1 x i64> @llvm.aarch64.neon.vtstd(<1 x i64> %vtst.i, <1 x i64> %vtst1.i)
117 %0 = extractelement <1 x i64> %vtst2.i, i32 0
121 declare <1 x i64> @llvm.aarch64.neon.vtstd(<1 x i64>, <1 x i64>)
122 declare <1 x i64> @llvm.aarch64.neon.vcltz(<1 x i64>, <1 x i64>)
123 declare <1 x i64> @llvm.aarch64.neon.vchs(<1 x i64>, <1 x i64>)
124 declare <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64>, <1 x i64>)
125 declare <1 x i64> @llvm.aarch64.neon.vclez(<1 x i64>, <1 x i64>)
126 declare <1 x i64> @llvm.aarch64.neon.vchi(<1 x i64>, <1 x i64>)
127 declare <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64>, <1 x i64>)
128 declare <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64>, <1 x i64>)