1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
2 ; arm64 has a different approach to scalars. Discarding.
4 define float @test_vcvts_f32_s32(i32 %a) {
5 ; CHECK: test_vcvts_f32_s32
6 ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}
8 %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
9 %0 = call float @llvm.aarch64.neon.vcvtint2fps.f32.v1i32(<1 x i32> %vcvtf.i)
13 declare float @llvm.aarch64.neon.vcvtint2fps.f32.v1i32(<1 x i32>)
15 define double @test_vcvtd_f64_s64(i64 %a) {
16 ; CHECK: test_vcvtd_f64_s64
17 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
19 %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
20 %0 = call double @llvm.aarch64.neon.vcvtint2fps.f64.v1i64(<1 x i64> %vcvtf.i)
24 declare double @llvm.aarch64.neon.vcvtint2fps.f64.v1i64(<1 x i64>)
26 define float @test_vcvts_f32_u32(i32 %a) {
27 ; CHECK: test_vcvts_f32_u32
28 ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}
30 %vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
31 %0 = call float @llvm.aarch64.neon.vcvtint2fpu.f32.v1i32(<1 x i32> %vcvtf.i)
35 declare float @llvm.aarch64.neon.vcvtint2fpu.f32.v1i32(<1 x i32>)
37 define double @test_vcvtd_f64_u64(i64 %a) {
38 ; CHECK: test_vcvtd_f64_u64
39 ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}
41 %vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
42 %0 = call double @llvm.aarch64.neon.vcvtint2fpu.f64.v1i64(<1 x i64> %vcvtf.i)
46 declare double @llvm.aarch64.neon.vcvtint2fpu.f64.v1i64(<1 x i64>)
48 define float @test_vcvts_n_f32_s32(i32 %a) {
49 ; CHECK: test_vcvts_n_f32_s32
50 ; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
52 %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
53 %0 = call float @llvm.aarch64.neon.vcvtfxs2fp.n.f32.v1i32(<1 x i32> %vcvtf, i32 1)
57 declare float @llvm.aarch64.neon.vcvtfxs2fp.n.f32.v1i32(<1 x i32>, i32)
59 define double @test_vcvtd_n_f64_s64(i64 %a) {
60 ; CHECK: test_vcvtd_n_f64_s64
61 ; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
63 %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
64 %0 = call double @llvm.aarch64.neon.vcvtfxs2fp.n.f64.v1i64(<1 x i64> %vcvtf, i32 1)
68 declare double @llvm.aarch64.neon.vcvtfxs2fp.n.f64.v1i64(<1 x i64>, i32)
70 define float @test_vcvts_n_f32_u32(i32 %a) {
71 ; CHECK: test_vcvts_n_f32_u32
72 ; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
74 %vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
75 %0 = call float @llvm.aarch64.neon.vcvtfxu2fp.n.f32.v1i32(<1 x i32> %vcvtf, i32 1)
79 declare float @llvm.aarch64.neon.vcvtfxu2fp.n.f32.v1i32(<1 x i32>, i32)
81 define double @test_vcvtd_n_f64_u64(i64 %a) {
82 ; CHECK: test_vcvtd_n_f64_u64
83 ; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
85 %vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
86 %0 = call double @llvm.aarch64.neon.vcvtfxu2fp.n.f64.v1i64(<1 x i64> %vcvtf, i32 1)
90 declare double @llvm.aarch64.neon.vcvtfxu2fp.n.f64.v1i64(<1 x i64>, i32)
92 define i32 @test_vcvts_n_s32_f32(float %a) {
93 ; CHECK: test_vcvts_n_s32_f32
94 ; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1
96 %fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float %a, i32 1)
97 %0 = extractelement <1 x i32> %fcvtzs1, i32 0
101 declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float, i32)
103 define i64 @test_vcvtd_n_s64_f64(double %a) {
104 ; CHECK: test_vcvtd_n_s64_f64
105 ; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1
107 %fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double %a, i32 1)
108 %0 = extractelement <1 x i64> %fcvtzs1, i32 0
112 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double, i32)
114 define i32 @test_vcvts_n_u32_f32(float %a) {
115 ; CHECK: test_vcvts_n_u32_f32
116 ; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32
118 %fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float %a, i32 32)
119 %0 = extractelement <1 x i32> %fcvtzu1, i32 0
123 declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float, i32)
125 define i64 @test_vcvtd_n_u64_f64(double %a) {
126 ; CHECK: test_vcvtd_n_u64_f64
127 ; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64
129 %fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double %a, i32 64)
130 %0 = extractelement <1 x i64> %fcvtzu1, i32 0
134 declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double, i32)