1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
2 ; arm64 duplicates these tests in cvt.ll
4 ;; Scalar Floating-point Convert
6 define float @test_vcvtxn(double %a) {
8 ; CHECK: fcvtxn {{s[0-9]}}, {{d[0-9]}}
10 %vcvtf = call float @llvm.aarch64.neon.fcvtxn(double %a)
14 declare float @llvm.aarch64.neon.fcvtxn(double)
16 define i32 @test_vcvtass(float %a) {
18 ; CHECK: fcvtas {{s[0-9]}}, {{s[0-9]}}
20 %vcvtas1.i = call <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.f32(float %a)
21 %0 = extractelement <1 x i32> %vcvtas1.i, i32 0
25 declare <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.f32(float)
27 define i64 @test_test_vcvtasd(double %a) {
28 ; CHECK: test_test_vcvtasd
29 ; CHECK: fcvtas {{d[0-9]}}, {{d[0-9]}}
31 %vcvtas1.i = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.f64(double %a)
32 %0 = extractelement <1 x i64> %vcvtas1.i, i32 0
36 declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.f64(double)
38 define i32 @test_vcvtaus(float %a) {
40 ; CHECK: fcvtau {{s[0-9]}}, {{s[0-9]}}
42 %vcvtau1.i = call <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.f32(float %a)
43 %0 = extractelement <1 x i32> %vcvtau1.i, i32 0
47 declare <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.f32(float)
49 define i64 @test_vcvtaud(double %a) {
51 ; CHECK: fcvtau {{d[0-9]}}, {{d[0-9]}}
53 %vcvtau1.i = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.f64(double %a)
54 %0 = extractelement <1 x i64> %vcvtau1.i, i32 0
58 declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.f64(double)
60 define i32 @test_vcvtmss(float %a) {
62 ; CHECK: fcvtms {{s[0-9]}}, {{s[0-9]}}
64 %vcvtms1.i = call <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.f32(float %a)
65 %0 = extractelement <1 x i32> %vcvtms1.i, i32 0
69 declare <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.f32(float)
71 define i64 @test_vcvtmd_s64_f64(double %a) {
72 ; CHECK: test_vcvtmd_s64_f64
73 ; CHECK: fcvtms {{d[0-9]}}, {{d[0-9]}}
75 %vcvtms1.i = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.f64(double %a)
76 %0 = extractelement <1 x i64> %vcvtms1.i, i32 0
80 declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.f64(double)
82 define i32 @test_vcvtmus(float %a) {
84 ; CHECK: fcvtmu {{s[0-9]}}, {{s[0-9]}}
86 %vcvtmu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.f32(float %a)
87 %0 = extractelement <1 x i32> %vcvtmu1.i, i32 0
91 declare <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.f32(float)
93 define i64 @test_vcvtmud(double %a) {
95 ; CHECK: fcvtmu {{d[0-9]}}, {{d[0-9]}}
97 %vcvtmu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.f64(double %a)
98 %0 = extractelement <1 x i64> %vcvtmu1.i, i32 0
102 declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.f64(double)
104 define i32 @test_vcvtnss(float %a) {
105 ; CHECK: test_vcvtnss
106 ; CHECK: fcvtns {{s[0-9]}}, {{s[0-9]}}
108 %vcvtns1.i = call <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.f32(float %a)
109 %0 = extractelement <1 x i32> %vcvtns1.i, i32 0
113 declare <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.f32(float)
115 define i64 @test_vcvtnd_s64_f64(double %a) {
116 ; CHECK: test_vcvtnd_s64_f64
117 ; CHECK: fcvtns {{d[0-9]}}, {{d[0-9]}}
119 %vcvtns1.i = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.f64(double %a)
120 %0 = extractelement <1 x i64> %vcvtns1.i, i32 0
124 declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.f64(double)
126 define i32 @test_vcvtnus(float %a) {
127 ; CHECK: test_vcvtnus
128 ; CHECK: fcvtnu {{s[0-9]}}, {{s[0-9]}}
130 %vcvtnu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.f32(float %a)
131 %0 = extractelement <1 x i32> %vcvtnu1.i, i32 0
135 declare <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.f32(float)
137 define i64 @test_vcvtnud(double %a) {
138 ; CHECK: test_vcvtnud
139 ; CHECK: fcvtnu {{d[0-9]}}, {{d[0-9]}}
141 %vcvtnu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.f64(double %a)
142 %0 = extractelement <1 x i64> %vcvtnu1.i, i32 0
146 declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.f64(double)
148 define i32 @test_vcvtpss(float %a) {
149 ; CHECK: test_vcvtpss
150 ; CHECK: fcvtps {{s[0-9]}}, {{s[0-9]}}
152 %vcvtps1.i = call <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.f32(float %a)
153 %0 = extractelement <1 x i32> %vcvtps1.i, i32 0
157 declare <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.f32(float)
159 define i64 @test_vcvtpd_s64_f64(double %a) {
160 ; CHECK: test_vcvtpd_s64_f64
161 ; CHECK: fcvtps {{d[0-9]}}, {{d[0-9]}}
163 %vcvtps1.i = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.f64(double %a)
164 %0 = extractelement <1 x i64> %vcvtps1.i, i32 0
168 declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.f64(double)
170 define i32 @test_vcvtpus(float %a) {
171 ; CHECK: test_vcvtpus
172 ; CHECK: fcvtpu {{s[0-9]}}, {{s[0-9]}}
174 %vcvtpu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.f32(float %a)
175 %0 = extractelement <1 x i32> %vcvtpu1.i, i32 0
179 declare <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.f32(float)
181 define i64 @test_vcvtpud(double %a) {
182 ; CHECK: test_vcvtpud
183 ; CHECK: fcvtpu {{d[0-9]}}, {{d[0-9]}}
185 %vcvtpu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.f64(double %a)
186 %0 = extractelement <1 x i64> %vcvtpu1.i, i32 0
190 declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.f64(double)
192 define i32 @test_vcvtss(float %a) {
194 ; CHECK: fcvtzs {{s[0-9]}}, {{s[0-9]}}
196 %vcvtzs1.i = call <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.f32(float %a)
197 %0 = extractelement <1 x i32> %vcvtzs1.i, i32 0
201 declare <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.f32(float)
203 define i64 @test_vcvtd_s64_f64(double %a) {
204 ; CHECK: test_vcvtd_s64_f64
205 ; CHECK: fcvtzs {{d[0-9]}}, {{d[0-9]}}
207 %vcvzs1.i = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.f64(double %a)
208 %0 = extractelement <1 x i64> %vcvzs1.i, i32 0
212 declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.f64(double)
214 define i32 @test_vcvtus(float %a) {
216 ; CHECK: fcvtzu {{s[0-9]}}, {{s[0-9]}}
218 %vcvtzu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.f32(float %a)
219 %0 = extractelement <1 x i32> %vcvtzu1.i, i32 0
223 declare <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.f32(float)
225 define i64 @test_vcvtud(double %a) {
227 ; CHECK: fcvtzu {{d[0-9]}}, {{d[0-9]}}
229 %vcvtzu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.f64(double %a)
230 %0 = extractelement <1 x i64> %vcvtzu1.i, i32 0
234 declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.f64(double)