1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 ;; Scalar Floating-point Convert
5 define float @test_vcvtxn(double %a) {
7 ; CHECK: fcvtxn {{s[0-9]}}, {{d[0-9]}}
9 %vcvtf = call float @llvm.aarch64.neon.fcvtxn(double %a)
13 declare float @llvm.aarch64.neon.fcvtxn(double)
15 define i32 @test_vcvtass(float %a) {
17 ; CHECK: fcvtas {{s[0-9]}}, {{s[0-9]}}
19 %vcvtas1.i = call <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.f32(float %a)
20 %0 = extractelement <1 x i32> %vcvtas1.i, i32 0
24 declare <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.f32(float)
26 define i64 @test_test_vcvtasd(double %a) {
27 ; CHECK: test_test_vcvtasd
28 ; CHECK: fcvtas {{d[0-9]}}, {{d[0-9]}}
30 %vcvtas1.i = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.f64(double %a)
31 %0 = extractelement <1 x i64> %vcvtas1.i, i32 0
35 declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.f64(double)
37 define i32 @test_vcvtaus(float %a) {
39 ; CHECK: fcvtau {{s[0-9]}}, {{s[0-9]}}
41 %vcvtau1.i = call <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.f32(float %a)
42 %0 = extractelement <1 x i32> %vcvtau1.i, i32 0
46 declare <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.f32(float)
48 define i64 @test_vcvtaud(double %a) {
50 ; CHECK: fcvtau {{d[0-9]}}, {{d[0-9]}}
52 %vcvtau1.i = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.f64(double %a)
53 %0 = extractelement <1 x i64> %vcvtau1.i, i32 0
57 declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.f64(double)
59 define i32 @test_vcvtmss(float %a) {
61 ; CHECK: fcvtms {{s[0-9]}}, {{s[0-9]}}
63 %vcvtms1.i = call <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.f32(float %a)
64 %0 = extractelement <1 x i32> %vcvtms1.i, i32 0
68 declare <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.f32(float)
70 define i64 @test_vcvtmd_s64_f64(double %a) {
71 ; CHECK: test_vcvtmd_s64_f64
72 ; CHECK: fcvtms {{d[0-9]}}, {{d[0-9]}}
74 %vcvtms1.i = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.f64(double %a)
75 %0 = extractelement <1 x i64> %vcvtms1.i, i32 0
79 declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.f64(double)
81 define i32 @test_vcvtmus(float %a) {
83 ; CHECK: fcvtmu {{s[0-9]}}, {{s[0-9]}}
85 %vcvtmu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.f32(float %a)
86 %0 = extractelement <1 x i32> %vcvtmu1.i, i32 0
90 declare <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.f32(float)
92 define i64 @test_vcvtmud(double %a) {
94 ; CHECK: fcvtmu {{d[0-9]}}, {{d[0-9]}}
96 %vcvtmu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.f64(double %a)
97 %0 = extractelement <1 x i64> %vcvtmu1.i, i32 0
101 declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.f64(double)
103 define i32 @test_vcvtnss(float %a) {
104 ; CHECK: test_vcvtnss
105 ; CHECK: fcvtns {{s[0-9]}}, {{s[0-9]}}
107 %vcvtns1.i = call <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.f32(float %a)
108 %0 = extractelement <1 x i32> %vcvtns1.i, i32 0
112 declare <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.f32(float)
114 define i64 @test_vcvtnd_s64_f64(double %a) {
115 ; CHECK: test_vcvtnd_s64_f64
116 ; CHECK: fcvtns {{d[0-9]}}, {{d[0-9]}}
118 %vcvtns1.i = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.f64(double %a)
119 %0 = extractelement <1 x i64> %vcvtns1.i, i32 0
123 declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.f64(double)
125 define i32 @test_vcvtnus(float %a) {
126 ; CHECK: test_vcvtnus
127 ; CHECK: fcvtnu {{s[0-9]}}, {{s[0-9]}}
129 %vcvtnu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.f32(float %a)
130 %0 = extractelement <1 x i32> %vcvtnu1.i, i32 0
134 declare <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.f32(float)
136 define i64 @test_vcvtnud(double %a) {
137 ; CHECK: test_vcvtnud
138 ; CHECK: fcvtnu {{d[0-9]}}, {{d[0-9]}}
140 %vcvtnu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.f64(double %a)
141 %0 = extractelement <1 x i64> %vcvtnu1.i, i32 0
145 declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.f64(double)
147 define i32 @test_vcvtpss(float %a) {
148 ; CHECK: test_vcvtpss
149 ; CHECK: fcvtps {{s[0-9]}}, {{s[0-9]}}
151 %vcvtps1.i = call <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.f32(float %a)
152 %0 = extractelement <1 x i32> %vcvtps1.i, i32 0
156 declare <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.f32(float)
158 define i64 @test_vcvtpd_s64_f64(double %a) {
159 ; CHECK: test_vcvtpd_s64_f64
160 ; CHECK: fcvtps {{d[0-9]}}, {{d[0-9]}}
162 %vcvtps1.i = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.f64(double %a)
163 %0 = extractelement <1 x i64> %vcvtps1.i, i32 0
167 declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.f64(double)
169 define i32 @test_vcvtpus(float %a) {
170 ; CHECK: test_vcvtpus
171 ; CHECK: fcvtpu {{s[0-9]}}, {{s[0-9]}}
173 %vcvtpu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.f32(float %a)
174 %0 = extractelement <1 x i32> %vcvtpu1.i, i32 0
178 declare <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.f32(float)
180 define i64 @test_vcvtpud(double %a) {
181 ; CHECK: test_vcvtpud
182 ; CHECK: fcvtpu {{d[0-9]}}, {{d[0-9]}}
184 %vcvtpu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.f64(double %a)
185 %0 = extractelement <1 x i64> %vcvtpu1.i, i32 0
189 declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.f64(double)
191 define i32 @test_vcvtss(float %a) {
193 ; CHECK: fcvtzs {{s[0-9]}}, {{s[0-9]}}
195 %vcvtzs1.i = call <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.f32(float %a)
196 %0 = extractelement <1 x i32> %vcvtzs1.i, i32 0
200 declare <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.f32(float)
202 define i64 @test_vcvtd_s64_f64(double %a) {
203 ; CHECK: test_vcvtd_s64_f64
204 ; CHECK: fcvtzs {{d[0-9]}}, {{d[0-9]}}
206 %vcvzs1.i = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.f64(double %a)
207 %0 = extractelement <1 x i64> %vcvzs1.i, i32 0
211 declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.f64(double)
213 define i32 @test_vcvtus(float %a) {
215 ; CHECK: fcvtzu {{s[0-9]}}, {{s[0-9]}}
217 %vcvtzu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.f32(float %a)
218 %0 = extractelement <1 x i32> %vcvtzu1.i, i32 0
222 declare <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.f32(float)
224 define i64 @test_vcvtud(double %a) {
226 ; CHECK: fcvtzu {{d[0-9]}}, {{d[0-9]}}
228 %vcvtzu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.f64(double %a)
229 %0 = extractelement <1 x i64> %vcvtzu1.i, i32 0
233 declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.f64(double)