1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
2 ; arm64 does not use intrinsics for comparisons.
4 ;; Scalar Floating-point Compare
6 define i32 @test_vceqs_f32(float %a, float %b) {
7 ; CHECK-LABEL: test_vceqs_f32
8 ; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
10 %fceq2.i = call <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float %a, float %b)
11 %0 = extractelement <1 x i32> %fceq2.i, i32 0
15 define i64 @test_vceqd_f64(double %a, double %b) {
16 ; CHECK-LABEL: test_vceqd_f64
17 ; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
19 %fceq2.i = call <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f64(double %a, double %b)
20 %0 = extractelement <1 x i64> %fceq2.i, i32 0
24 define <1 x i64> @test_vceqz_f64(<1 x double> %a) {
25 ; CHECK-LABEL: test_vceqz_f64
26 ; CHECK: fcmeq {{d[0-9]+}}, {{d[0-9]+}}, #0.0
28 %0 = fcmp oeq <1 x double> %a, zeroinitializer
29 %vceqz.i = sext <1 x i1> %0 to <1 x i64>
30 ret <1 x i64> %vceqz.i
33 define i32 @test_vceqzs_f32(float %a) {
34 ; CHECK-LABEL: test_vceqzs_f32
35 ; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, #0.0
37 %fceq1.i = call <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float %a, float 0.0)
38 %0 = extractelement <1 x i32> %fceq1.i, i32 0
42 define i64 @test_vceqzd_f64(double %a) {
43 ; CHECK-LABEL: test_vceqzd_f64
44 ; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, #0.0
46 %fceq1.i = call <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f32(double %a, float 0.0)
47 %0 = extractelement <1 x i64> %fceq1.i, i32 0
51 define i32 @test_vcges_f32(float %a, float %b) {
52 ; CHECK-LABEL: test_vcges_f32
53 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
55 %fcge2.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float %b)
56 %0 = extractelement <1 x i32> %fcge2.i, i32 0
60 define i64 @test_vcged_f64(double %a, double %b) {
61 ; CHECK-LABEL: test_vcged_f64
62 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
64 %fcge2.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double %a, double %b)
65 %0 = extractelement <1 x i64> %fcge2.i, i32 0
69 define i32 @test_vcgezs_f32(float %a) {
70 ; CHECK-LABEL: test_vcgezs_f32
71 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, #0.0
73 %fcge1.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float 0.0)
74 %0 = extractelement <1 x i32> %fcge1.i, i32 0
78 define i64 @test_vcgezd_f64(double %a) {
79 ; CHECK-LABEL: test_vcgezd_f64
80 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, #0.0
82 %fcge1.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f32(double %a, float 0.0)
83 %0 = extractelement <1 x i64> %fcge1.i, i32 0
87 define i32 @test_vcgts_f32(float %a, float %b) {
88 ; CHECK-LABEL: test_vcgts_f32
89 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
91 %fcgt2.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float %b)
92 %0 = extractelement <1 x i32> %fcgt2.i, i32 0
96 define i64 @test_vcgtd_f64(double %a, double %b) {
97 ; CHECK-LABEL: test_vcgtd_f64
98 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
100 %fcgt2.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double %a, double %b)
101 %0 = extractelement <1 x i64> %fcgt2.i, i32 0
105 define i32 @test_vcgtzs_f32(float %a) {
106 ; CHECK-LABEL: test_vcgtzs_f32
107 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, #0.0
109 %fcgt1.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float 0.0)
110 %0 = extractelement <1 x i32> %fcgt1.i, i32 0
114 define i64 @test_vcgtzd_f64(double %a) {
115 ; CHECK-LABEL: test_vcgtzd_f64
116 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, #0.0
118 %fcgt1.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f32(double %a, float 0.0)
119 %0 = extractelement <1 x i64> %fcgt1.i, i32 0
123 define i32 @test_vcles_f32(float %a, float %b) {
124 ; CHECK-LABEL: test_vcles_f32
125 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
127 %fcge2.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float %b)
128 %0 = extractelement <1 x i32> %fcge2.i, i32 0
132 define i64 @test_vcled_f64(double %a, double %b) {
133 ; CHECK-LABEL: test_vcled_f64
134 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
136 %fcge2.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double %a, double %b)
137 %0 = extractelement <1 x i64> %fcge2.i, i32 0
141 define i32 @test_vclezs_f32(float %a) {
142 ; CHECK-LABEL: test_vclezs_f32
143 ; CHECK: fcmle {{s[0-9]}}, {{s[0-9]}}, #0.0
145 %fcle1.i = call <1 x i32> @llvm.aarch64.neon.fclez.v1i32.f32.f32(float %a, float 0.0)
146 %0 = extractelement <1 x i32> %fcle1.i, i32 0
150 define i64 @test_vclezd_f64(double %a) {
151 ; CHECK-LABEL: test_vclezd_f64
152 ; CHECK: fcmle {{d[0-9]}}, {{d[0-9]}}, #0.0
154 %fcle1.i = call <1 x i64> @llvm.aarch64.neon.fclez.v1i64.f64.f32(double %a, float 0.0)
155 %0 = extractelement <1 x i64> %fcle1.i, i32 0
159 define i32 @test_vclts_f32(float %a, float %b) {
160 ; CHECK-LABEL: test_vclts_f32
161 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
163 %fcgt2.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float %b)
164 %0 = extractelement <1 x i32> %fcgt2.i, i32 0
168 define i64 @test_vcltd_f64(double %a, double %b) {
169 ; CHECK-LABEL: test_vcltd_f64
170 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
172 %fcgt2.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double %a, double %b)
173 %0 = extractelement <1 x i64> %fcgt2.i, i32 0
177 define i32 @test_vcltzs_f32(float %a) {
178 ; CHECK-LABEL: test_vcltzs_f32
179 ; CHECK: fcmlt {{s[0-9]}}, {{s[0-9]}}, #0.0
181 %fclt1.i = call <1 x i32> @llvm.aarch64.neon.fcltz.v1i32.f32.f32(float %a, float 0.0)
182 %0 = extractelement <1 x i32> %fclt1.i, i32 0
186 define i64 @test_vcltzd_f64(double %a) {
187 ; CHECK-LABEL: test_vcltzd_f64
188 ; CHECK: fcmlt {{d[0-9]}}, {{d[0-9]}}, #0.0
190 %fclt1.i = call <1 x i64> @llvm.aarch64.neon.fcltz.v1i64.f64.f32(double %a, float 0.0)
191 %0 = extractelement <1 x i64> %fclt1.i, i32 0
195 define i32 @test_vcages_f32(float %a, float %b) {
196 ; CHECK-LABEL: test_vcages_f32
197 ; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
199 %fcage2.i = call <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float %a, float %b)
200 %0 = extractelement <1 x i32> %fcage2.i, i32 0
204 define i64 @test_vcaged_f64(double %a, double %b) {
205 ; CHECK-LABEL: test_vcaged_f64
206 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
208 %fcage2.i = call <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double %a, double %b)
209 %0 = extractelement <1 x i64> %fcage2.i, i32 0
213 define i32 @test_vcagts_f32(float %a, float %b) {
214 ; CHECK-LABEL: test_vcagts_f32
215 ; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
217 %fcagt2.i = call <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float %a, float %b)
218 %0 = extractelement <1 x i32> %fcagt2.i, i32 0
222 define i64 @test_vcagtd_f64(double %a, double %b) {
223 ; CHECK-LABEL: test_vcagtd_f64
224 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
226 %fcagt2.i = call <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double %a, double %b)
227 %0 = extractelement <1 x i64> %fcagt2.i, i32 0
231 define i32 @test_vcales_f32(float %a, float %b) {
232 ; CHECK-LABEL: test_vcales_f32
233 ; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
235 %fcage2.i = call <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float %a, float %b)
236 %0 = extractelement <1 x i32> %fcage2.i, i32 0
240 define i64 @test_vcaled_f64(double %a, double %b) {
241 ; CHECK-LABEL: test_vcaled_f64
242 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
244 %fcage2.i = call <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double %a, double %b)
245 %0 = extractelement <1 x i64> %fcage2.i, i32 0
249 define i32 @test_vcalts_f32(float %a, float %b) {
250 ; CHECK-LABEL: test_vcalts_f32
251 ; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
253 %fcalt2.i = call <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float %a, float %b)
254 %0 = extractelement <1 x i32> %fcalt2.i, i32 0
258 define i64 @test_vcaltd_f64(double %a, double %b) {
259 ; CHECK-LABEL: test_vcaltd_f64
260 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
262 %fcalt2.i = call <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double %a, double %b)
263 %0 = extractelement <1 x i64> %fcalt2.i, i32 0
267 declare <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float, float)
268 declare <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f32(double, float)
269 declare <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f64(double, double)
270 declare <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float, float)
271 declare <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f32(double, float)
272 declare <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double, double)
273 declare <1 x i32> @llvm.aarch64.neon.fclez.v1i32.f32.f32(float, float)
274 declare <1 x i64> @llvm.aarch64.neon.fclez.v1i64.f64.f32(double, float)
275 declare <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float, float)
276 declare <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f32(double, float)
277 declare <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double, double)
278 declare <1 x i32> @llvm.aarch64.neon.fcltz.v1i32.f32.f32(float, float)
279 declare <1 x i64> @llvm.aarch64.neon.fcltz.v1i64.f64.f32(double, float)
280 declare <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float, float)
281 declare <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double, double)
282 declare <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float, float)
283 declare <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double, double)