1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 ;; Scalar Floating-point Compare
5 define i32 @test_vceqs_f32(float %a, float %b) {
6 ; CHECK-LABEL: test_vceqs_f32
7 ; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
9 %fceq2.i = call <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float %a, float %b)
10 %0 = extractelement <1 x i32> %fceq2.i, i32 0
14 define i64 @test_vceqd_f64(double %a, double %b) {
15 ; CHECK-LABEL: test_vceqd_f64
16 ; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
18 %fceq2.i = call <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f64(double %a, double %b)
19 %0 = extractelement <1 x i64> %fceq2.i, i32 0
23 define <1 x i64> @test_vceqz_f64(<1 x double> %a) {
24 ; CHECK-LABEL: test_vceqz_f64
25 ; CHECK: fcmeq {{d[0-9]+}}, {{d[0-9]+}}, #0.0
27 %0 = fcmp oeq <1 x double> %a, zeroinitializer
28 %vceqz.i = zext <1 x i1> %0 to <1 x i64>
29 ret <1 x i64> %vceqz.i
32 define i32 @test_vceqzs_f32(float %a) {
33 ; CHECK-LABEL: test_vceqzs_f32
34 ; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, #0.0
36 %fceq1.i = call <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float %a, float 0.0)
37 %0 = extractelement <1 x i32> %fceq1.i, i32 0
41 define i64 @test_vceqzd_f64(double %a) {
42 ; CHECK-LABEL: test_vceqzd_f64
43 ; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, #0.0
45 %fceq1.i = call <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f32(double %a, float 0.0)
46 %0 = extractelement <1 x i64> %fceq1.i, i32 0
50 define i32 @test_vcges_f32(float %a, float %b) {
51 ; CHECK-LABEL: test_vcges_f32
52 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
54 %fcge2.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float %b)
55 %0 = extractelement <1 x i32> %fcge2.i, i32 0
59 define i64 @test_vcged_f64(double %a, double %b) {
60 ; CHECK-LABEL: test_vcged_f64
61 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
63 %fcge2.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double %a, double %b)
64 %0 = extractelement <1 x i64> %fcge2.i, i32 0
68 define i32 @test_vcgezs_f32(float %a) {
69 ; CHECK-LABEL: test_vcgezs_f32
70 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, #0.0
72 %fcge1.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float 0.0)
73 %0 = extractelement <1 x i32> %fcge1.i, i32 0
77 define i64 @test_vcgezd_f64(double %a) {
78 ; CHECK-LABEL: test_vcgezd_f64
79 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, #0.0
81 %fcge1.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f32(double %a, float 0.0)
82 %0 = extractelement <1 x i64> %fcge1.i, i32 0
86 define i32 @test_vcgts_f32(float %a, float %b) {
87 ; CHECK-LABEL: test_vcgts_f32
88 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
90 %fcgt2.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float %b)
91 %0 = extractelement <1 x i32> %fcgt2.i, i32 0
95 define i64 @test_vcgtd_f64(double %a, double %b) {
96 ; CHECK-LABEL: test_vcgtd_f64
97 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
99 %fcgt2.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double %a, double %b)
100 %0 = extractelement <1 x i64> %fcgt2.i, i32 0
104 define i32 @test_vcgtzs_f32(float %a) {
105 ; CHECK-LABEL: test_vcgtzs_f32
106 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, #0.0
108 %fcgt1.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float 0.0)
109 %0 = extractelement <1 x i32> %fcgt1.i, i32 0
113 define i64 @test_vcgtzd_f64(double %a) {
114 ; CHECK-LABEL: test_vcgtzd_f64
115 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, #0.0
117 %fcgt1.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f32(double %a, float 0.0)
118 %0 = extractelement <1 x i64> %fcgt1.i, i32 0
122 define i32 @test_vcles_f32(float %a, float %b) {
123 ; CHECK-LABEL: test_vcles_f32
124 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
126 %fcge2.i = call <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float %a, float %b)
127 %0 = extractelement <1 x i32> %fcge2.i, i32 0
131 define i64 @test_vcled_f64(double %a, double %b) {
132 ; CHECK-LABEL: test_vcled_f64
133 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
135 %fcge2.i = call <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double %a, double %b)
136 %0 = extractelement <1 x i64> %fcge2.i, i32 0
140 define i32 @test_vclezs_f32(float %a) {
141 ; CHECK-LABEL: test_vclezs_f32
142 ; CHECK: fcmle {{s[0-9]}}, {{s[0-9]}}, #0.0
144 %fcle1.i = call <1 x i32> @llvm.aarch64.neon.fclez.v1i32.f32.f32(float %a, float 0.0)
145 %0 = extractelement <1 x i32> %fcle1.i, i32 0
149 define i64 @test_vclezd_f64(double %a) {
150 ; CHECK-LABEL: test_vclezd_f64
151 ; CHECK: fcmle {{d[0-9]}}, {{d[0-9]}}, #0.0
153 %fcle1.i = call <1 x i64> @llvm.aarch64.neon.fclez.v1i64.f64.f32(double %a, float 0.0)
154 %0 = extractelement <1 x i64> %fcle1.i, i32 0
158 define i32 @test_vclts_f32(float %a, float %b) {
159 ; CHECK-LABEL: test_vclts_f32
160 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
162 %fcgt2.i = call <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float %a, float %b)
163 %0 = extractelement <1 x i32> %fcgt2.i, i32 0
167 define i64 @test_vcltd_f64(double %a, double %b) {
168 ; CHECK-LABEL: test_vcltd_f64
169 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
171 %fcgt2.i = call <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double %a, double %b)
172 %0 = extractelement <1 x i64> %fcgt2.i, i32 0
176 define i32 @test_vcltzs_f32(float %a) {
177 ; CHECK-LABEL: test_vcltzs_f32
178 ; CHECK: fcmlt {{s[0-9]}}, {{s[0-9]}}, #0.0
180 %fclt1.i = call <1 x i32> @llvm.aarch64.neon.fcltz.v1i32.f32.f32(float %a, float 0.0)
181 %0 = extractelement <1 x i32> %fclt1.i, i32 0
185 define i64 @test_vcltzd_f64(double %a) {
186 ; CHECK-LABEL: test_vcltzd_f64
187 ; CHECK: fcmlt {{d[0-9]}}, {{d[0-9]}}, #0.0
189 %fclt1.i = call <1 x i64> @llvm.aarch64.neon.fcltz.v1i64.f64.f32(double %a, float 0.0)
190 %0 = extractelement <1 x i64> %fclt1.i, i32 0
194 define i32 @test_vcages_f32(float %a, float %b) {
195 ; CHECK-LABEL: test_vcages_f32
196 ; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
198 %fcage2.i = call <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float %a, float %b)
199 %0 = extractelement <1 x i32> %fcage2.i, i32 0
203 define i64 @test_vcaged_f64(double %a, double %b) {
204 ; CHECK-LABEL: test_vcaged_f64
205 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
207 %fcage2.i = call <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double %a, double %b)
208 %0 = extractelement <1 x i64> %fcage2.i, i32 0
212 define i32 @test_vcagts_f32(float %a, float %b) {
213 ; CHECK-LABEL: test_vcagts_f32
214 ; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
216 %fcagt2.i = call <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float %a, float %b)
217 %0 = extractelement <1 x i32> %fcagt2.i, i32 0
221 define i64 @test_vcagtd_f64(double %a, double %b) {
222 ; CHECK-LABEL: test_vcagtd_f64
223 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
225 %fcagt2.i = call <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double %a, double %b)
226 %0 = extractelement <1 x i64> %fcagt2.i, i32 0
230 define i32 @test_vcales_f32(float %a, float %b) {
231 ; CHECK-LABEL: test_vcales_f32
232 ; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
234 %fcage2.i = call <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float %a, float %b)
235 %0 = extractelement <1 x i32> %fcage2.i, i32 0
239 define i64 @test_vcaled_f64(double %a, double %b) {
240 ; CHECK-LABEL: test_vcaled_f64
241 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
243 %fcage2.i = call <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double %a, double %b)
244 %0 = extractelement <1 x i64> %fcage2.i, i32 0
248 define i32 @test_vcalts_f32(float %a, float %b) {
249 ; CHECK-LABEL: test_vcalts_f32
250 ; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
252 %fcalt2.i = call <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float %a, float %b)
253 %0 = extractelement <1 x i32> %fcalt2.i, i32 0
257 define i64 @test_vcaltd_f64(double %a, double %b) {
258 ; CHECK-LABEL: test_vcaltd_f64
259 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
261 %fcalt2.i = call <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double %a, double %b)
262 %0 = extractelement <1 x i64> %fcalt2.i, i32 0
266 declare <1 x i32> @llvm.aarch64.neon.fceq.v1i32.f32.f32(float, float)
267 declare <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f32(double, float)
268 declare <1 x i64> @llvm.aarch64.neon.fceq.v1i64.f64.f64(double, double)
269 declare <1 x i32> @llvm.aarch64.neon.fcge.v1i32.f32.f32(float, float)
270 declare <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f32(double, float)
271 declare <1 x i64> @llvm.aarch64.neon.fcge.v1i64.f64.f64(double, double)
272 declare <1 x i32> @llvm.aarch64.neon.fclez.v1i32.f32.f32(float, float)
273 declare <1 x i64> @llvm.aarch64.neon.fclez.v1i64.f64.f32(double, float)
274 declare <1 x i32> @llvm.aarch64.neon.fcgt.v1i32.f32.f32(float, float)
275 declare <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f32(double, float)
276 declare <1 x i64> @llvm.aarch64.neon.fcgt.v1i64.f64.f64(double, double)
277 declare <1 x i32> @llvm.aarch64.neon.fcltz.v1i32.f32.f32(float, float)
278 declare <1 x i64> @llvm.aarch64.neon.fcltz.v1i64.f64.f32(double, float)
279 declare <1 x i32> @llvm.aarch64.neon.fcage.v1i32.f32.f32(float, float)
280 declare <1 x i64> @llvm.aarch64.neon.fcage.v1i64.f64.f64(double, double)
281 declare <1 x i32> @llvm.aarch64.neon.fcagt.v1i32.f32.f32(float, float)
282 declare <1 x i64> @llvm.aarch64.neon.fcagt.v1i64.f64.f64(double, double)