1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 define i16 @test_vqdmulhh_s16(i16 %a, i16 %b) {
4 ; CHECK: test_vqdmulhh_s16
5 ; CHECK: sqdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
6 %1 = insertelement <1 x i16> undef, i16 %a, i32 0
7 %2 = insertelement <1 x i16> undef, i16 %b, i32 0
8 %3 = call <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
9 %4 = extractelement <1 x i16> %3, i32 0
13 define i32 @test_vqdmulhs_s32(i32 %a, i32 %b) {
14 ; CHECK: test_vqdmulhs_s32
15 ; CHECK: sqdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
16 %1 = insertelement <1 x i32> undef, i32 %a, i32 0
17 %2 = insertelement <1 x i32> undef, i32 %b, i32 0
18 %3 = call <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
19 %4 = extractelement <1 x i32> %3, i32 0
23 declare <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16>, <1 x i16>)
24 declare <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32>, <1 x i32>)
26 define i16 @test_vqrdmulhh_s16(i16 %a, i16 %b) {
27 ; CHECK: test_vqrdmulhh_s16
28 ; CHECK: sqrdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
29 %1 = insertelement <1 x i16> undef, i16 %a, i32 0
30 %2 = insertelement <1 x i16> undef, i16 %b, i32 0
31 %3 = call <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
32 %4 = extractelement <1 x i16> %3, i32 0
36 define i32 @test_vqrdmulhs_s32(i32 %a, i32 %b) {
37 ; CHECK: test_vqrdmulhs_s32
38 ; CHECK: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
39 %1 = insertelement <1 x i32> undef, i32 %a, i32 0
40 %2 = insertelement <1 x i32> undef, i32 %b, i32 0
41 %3 = call <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
42 %4 = extractelement <1 x i32> %3, i32 0
46 declare <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16>, <1 x i16>)
47 declare <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32>, <1 x i32>)
49 define float @test_vmulxs_f32(float %a, float %b) {
50 ; CHECK: test_vmulxs_f32
51 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
52 %1 = insertelement <1 x float> undef, float %a, i32 0
53 %2 = insertelement <1 x float> undef, float %b, i32 0
54 %3 = call <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float> %1, <1 x float> %2)
55 %4 = extractelement <1 x float> %3, i32 0
59 define double @test_vmulxd_f64(double %a, double %b) {
60 ; CHECK: test_vmulxd_f64
61 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
62 %1 = insertelement <1 x double> undef, double %a, i32 0
63 %2 = insertelement <1 x double> undef, double %b, i32 0
64 %3 = call <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double> %1, <1 x double> %2)
65 %4 = extractelement <1 x double> %3, i32 0
69 declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>)
70 declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>)