1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 define i16 @test_vqdmulhh_s16(i16 %a, i16 %b) {
4 ; CHECK: test_vqdmulhh_s16
5 ; CHECK: sqdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
6 %1 = insertelement <1 x i16> undef, i16 %a, i32 0
7 %2 = insertelement <1 x i16> undef, i16 %b, i32 0
8 %3 = call <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
9 %4 = extractelement <1 x i16> %3, i32 0
13 define i32 @test_vqdmulhs_s32(i32 %a, i32 %b) {
14 ; CHECK: test_vqdmulhs_s32
15 ; CHECK: sqdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
16 %1 = insertelement <1 x i32> undef, i32 %a, i32 0
17 %2 = insertelement <1 x i32> undef, i32 %b, i32 0
18 %3 = call <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
19 %4 = extractelement <1 x i32> %3, i32 0
23 declare <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16>, <1 x i16>)
24 declare <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32>, <1 x i32>)
26 define i16 @test_vqrdmulhh_s16(i16 %a, i16 %b) {
27 ; CHECK: test_vqrdmulhh_s16
28 ; CHECK: sqrdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
29 %1 = insertelement <1 x i16> undef, i16 %a, i32 0
30 %2 = insertelement <1 x i16> undef, i16 %b, i32 0
31 %3 = call <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
32 %4 = extractelement <1 x i16> %3, i32 0
36 define i32 @test_vqrdmulhs_s32(i32 %a, i32 %b) {
37 ; CHECK: test_vqrdmulhs_s32
38 ; CHECK: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
39 %1 = insertelement <1 x i32> undef, i32 %a, i32 0
40 %2 = insertelement <1 x i32> undef, i32 %b, i32 0
41 %3 = call <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
42 %4 = extractelement <1 x i32> %3, i32 0
46 declare <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16>, <1 x i16>)
47 declare <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32>, <1 x i32>)
49 define float @test_vmulxs_f32(float %a, float %b) {
50 ; CHECK: test_vmulxs_f32
51 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
52 %1 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %b)
56 define double @test_vmulxd_f64(double %a, double %b) {
57 ; CHECK: test_vmulxd_f64
58 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
59 %1 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %b)
63 declare float @llvm.aarch64.neon.vmulx.f32(float, float)
64 declare double @llvm.aarch64.neon.vmulx.f64(double, double)
66 define i32 @test_vqdmlalh_s16(i32 %a, i16 %b, i16 %c) {
67 ; CHECK: test_vqdmlalh_s16
68 ; CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
70 %vqdmlal.i = insertelement <1 x i32> undef, i32 %a, i32 0
71 %vqdmlal1.i = insertelement <1 x i16> undef, i16 %b, i32 0
72 %vqdmlal2.i = insertelement <1 x i16> undef, i16 %c, i32 0
73 %vqdmlal3.i = call <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i32> %vqdmlal.i, <1 x i16> %vqdmlal1.i, <1 x i16> %vqdmlal2.i)
74 %0 = extractelement <1 x i32> %vqdmlal3.i, i32 0
78 define i64 @test_vqdmlals_s32(i64 %a, i32 %b, i32 %c) {
79 ; CHECK: test_vqdmlals_s32
80 ; CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
82 %vqdmlal.i = insertelement <1 x i64> undef, i64 %a, i32 0
83 %vqdmlal1.i = insertelement <1 x i32> undef, i32 %b, i32 0
84 %vqdmlal2.i = insertelement <1 x i32> undef, i32 %c, i32 0
85 %vqdmlal3.i = call <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i64> %vqdmlal.i, <1 x i32> %vqdmlal1.i, <1 x i32> %vqdmlal2.i)
86 %0 = extractelement <1 x i64> %vqdmlal3.i, i32 0
90 declare <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i32>, <1 x i16>, <1 x i16>)
91 declare <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i64>, <1 x i32>, <1 x i32>)
93 define i32 @test_vqdmlslh_s16(i32 %a, i16 %b, i16 %c) {
94 ; CHECK: test_vqdmlslh_s16
95 ; CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
97 %vqdmlsl.i = insertelement <1 x i32> undef, i32 %a, i32 0
98 %vqdmlsl1.i = insertelement <1 x i16> undef, i16 %b, i32 0
99 %vqdmlsl2.i = insertelement <1 x i16> undef, i16 %c, i32 0
100 %vqdmlsl3.i = call <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i32> %vqdmlsl.i, <1 x i16> %vqdmlsl1.i, <1 x i16> %vqdmlsl2.i)
101 %0 = extractelement <1 x i32> %vqdmlsl3.i, i32 0
105 define i64 @test_vqdmlsls_s32(i64 %a, i32 %b, i32 %c) {
106 ; CHECK: test_vqdmlsls_s32
107 ; CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
109 %vqdmlsl.i = insertelement <1 x i64> undef, i64 %a, i32 0
110 %vqdmlsl1.i = insertelement <1 x i32> undef, i32 %b, i32 0
111 %vqdmlsl2.i = insertelement <1 x i32> undef, i32 %c, i32 0
112 %vqdmlsl3.i = call <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i64> %vqdmlsl.i, <1 x i32> %vqdmlsl1.i, <1 x i32> %vqdmlsl2.i)
113 %0 = extractelement <1 x i64> %vqdmlsl3.i, i32 0
117 declare <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i32>, <1 x i16>, <1 x i16>)
118 declare <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i64>, <1 x i32>, <1 x i32>)
120 define i32 @test_vqdmullh_s16(i16 %a, i16 %b) {
121 ; CHECK: test_vqdmullh_s16
122 ; CHECK: sqdmull {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
124 %vqdmull.i = insertelement <1 x i16> undef, i16 %a, i32 0
125 %vqdmull1.i = insertelement <1 x i16> undef, i16 %b, i32 0
126 %vqdmull2.i = call <1 x i32> @llvm.arm.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i)
127 %0 = extractelement <1 x i32> %vqdmull2.i, i32 0
131 define i64 @test_vqdmulls_s32(i32 %a, i32 %b) {
132 ; CHECK: test_vqdmulls_s32
133 ; CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
135 %vqdmull.i = insertelement <1 x i32> undef, i32 %a, i32 0
136 %vqdmull1.i = insertelement <1 x i32> undef, i32 %b, i32 0
137 %vqdmull2.i = call <1 x i64> @llvm.arm.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i)
138 %0 = extractelement <1 x i64> %vqdmull2.i, i32 0
142 declare <1 x i32> @llvm.arm.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>)
143 declare <1 x i64> @llvm.arm.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>)