1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 define i16 @test_vqdmulhh_s16(i16 %a, i16 %b) {
4 ; CHECK: test_vqdmulhh_s16
5 ; CHECK: sqdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
6 %1 = insertelement <1 x i16> undef, i16 %a, i32 0
7 %2 = insertelement <1 x i16> undef, i16 %b, i32 0
8 %3 = call <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
9 %4 = extractelement <1 x i16> %3, i32 0
13 define i32 @test_vqdmulhs_s32(i32 %a, i32 %b) {
14 ; CHECK: test_vqdmulhs_s32
15 ; CHECK: sqdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
16 %1 = insertelement <1 x i32> undef, i32 %a, i32 0
17 %2 = insertelement <1 x i32> undef, i32 %b, i32 0
18 %3 = call <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
19 %4 = extractelement <1 x i32> %3, i32 0
23 declare <1 x i16> @llvm.arm.neon.vqdmulh.v1i16(<1 x i16>, <1 x i16>)
24 declare <1 x i32> @llvm.arm.neon.vqdmulh.v1i32(<1 x i32>, <1 x i32>)
26 define i16 @test_vqrdmulhh_s16(i16 %a, i16 %b) {
27 ; CHECK: test_vqrdmulhh_s16
28 ; CHECK: sqrdmulh {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
29 %1 = insertelement <1 x i16> undef, i16 %a, i32 0
30 %2 = insertelement <1 x i16> undef, i16 %b, i32 0
31 %3 = call <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16> %1, <1 x i16> %2)
32 %4 = extractelement <1 x i16> %3, i32 0
36 define i32 @test_vqrdmulhs_s32(i32 %a, i32 %b) {
37 ; CHECK: test_vqrdmulhs_s32
38 ; CHECK: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
39 %1 = insertelement <1 x i32> undef, i32 %a, i32 0
40 %2 = insertelement <1 x i32> undef, i32 %b, i32 0
41 %3 = call <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32> %1, <1 x i32> %2)
42 %4 = extractelement <1 x i32> %3, i32 0
46 declare <1 x i16> @llvm.arm.neon.vqrdmulh.v1i16(<1 x i16>, <1 x i16>)
47 declare <1 x i32> @llvm.arm.neon.vqrdmulh.v1i32(<1 x i32>, <1 x i32>)
49 define float @test_vmulxs_f32(float %a, float %b) {
50 ; CHECK: test_vmulxs_f32
51 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
52 %1 = insertelement <1 x float> undef, float %a, i32 0
53 %2 = insertelement <1 x float> undef, float %b, i32 0
54 %3 = call <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float> %1, <1 x float> %2)
55 %4 = extractelement <1 x float> %3, i32 0
59 define double @test_vmulxd_f64(double %a, double %b) {
60 ; CHECK: test_vmulxd_f64
61 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
62 %1 = insertelement <1 x double> undef, double %a, i32 0
63 %2 = insertelement <1 x double> undef, double %b, i32 0
64 %3 = call <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double> %1, <1 x double> %2)
65 %4 = extractelement <1 x double> %3, i32 0
69 declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>)
70 declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>)
72 define i32 @test_vqdmlalh_s16(i32 %a, i16 %b, i16 %c) {
73 ; CHECK: test_vqdmlalh_s16
74 ; CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
76 %vqdmlal.i = insertelement <1 x i32> undef, i32 %a, i32 0
77 %vqdmlal1.i = insertelement <1 x i16> undef, i16 %b, i32 0
78 %vqdmlal2.i = insertelement <1 x i16> undef, i16 %c, i32 0
79 %vqdmlal3.i = call <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i32> %vqdmlal.i, <1 x i16> %vqdmlal1.i, <1 x i16> %vqdmlal2.i)
80 %0 = extractelement <1 x i32> %vqdmlal3.i, i32 0
84 define i64 @test_vqdmlals_s32(i64 %a, i32 %b, i32 %c) {
85 ; CHECK: test_vqdmlals_s32
86 ; CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
88 %vqdmlal.i = insertelement <1 x i64> undef, i64 %a, i32 0
89 %vqdmlal1.i = insertelement <1 x i32> undef, i32 %b, i32 0
90 %vqdmlal2.i = insertelement <1 x i32> undef, i32 %c, i32 0
91 %vqdmlal3.i = call <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i64> %vqdmlal.i, <1 x i32> %vqdmlal1.i, <1 x i32> %vqdmlal2.i)
92 %0 = extractelement <1 x i64> %vqdmlal3.i, i32 0
96 declare <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i32>, <1 x i16>, <1 x i16>)
97 declare <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i64>, <1 x i32>, <1 x i32>)
99 define i32 @test_vqdmlslh_s16(i32 %a, i16 %b, i16 %c) {
100 ; CHECK: test_vqdmlslh_s16
101 ; CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
103 %vqdmlsl.i = insertelement <1 x i32> undef, i32 %a, i32 0
104 %vqdmlsl1.i = insertelement <1 x i16> undef, i16 %b, i32 0
105 %vqdmlsl2.i = insertelement <1 x i16> undef, i16 %c, i32 0
106 %vqdmlsl3.i = call <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i32> %vqdmlsl.i, <1 x i16> %vqdmlsl1.i, <1 x i16> %vqdmlsl2.i)
107 %0 = extractelement <1 x i32> %vqdmlsl3.i, i32 0
111 define i64 @test_vqdmlsls_s32(i64 %a, i32 %b, i32 %c) {
112 ; CHECK: test_vqdmlsls_s32
113 ; CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
115 %vqdmlsl.i = insertelement <1 x i64> undef, i64 %a, i32 0
116 %vqdmlsl1.i = insertelement <1 x i32> undef, i32 %b, i32 0
117 %vqdmlsl2.i = insertelement <1 x i32> undef, i32 %c, i32 0
118 %vqdmlsl3.i = call <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i64> %vqdmlsl.i, <1 x i32> %vqdmlsl1.i, <1 x i32> %vqdmlsl2.i)
119 %0 = extractelement <1 x i64> %vqdmlsl3.i, i32 0
123 declare <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i32>, <1 x i16>, <1 x i16>)
124 declare <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i64>, <1 x i32>, <1 x i32>)
126 define i32 @test_vqdmullh_s16(i16 %a, i16 %b) {
127 ; CHECK: test_vqdmullh_s16
128 ; CHECK: sqdmull {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
130 %vqdmull.i = insertelement <1 x i16> undef, i16 %a, i32 0
131 %vqdmull1.i = insertelement <1 x i16> undef, i16 %b, i32 0
132 %vqdmull2.i = call <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i)
133 %0 = extractelement <1 x i32> %vqdmull2.i, i32 0
137 define i64 @test_vqdmulls_s32(i32 %a, i32 %b) {
138 ; CHECK: test_vqdmulls_s32
139 ; CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
141 %vqdmull.i = insertelement <1 x i32> undef, i32 %a, i32 0
142 %vqdmull1.i = insertelement <1 x i32> undef, i32 %b, i32 0
143 %vqdmull2.i = call <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i)
144 %0 = extractelement <1 x i64> %vqdmull2.i, i32 0
148 declare <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>)
149 declare <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>)