1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2 ; Intrinsic wrangling. arm64 does it differently.
4 define i64 @test_vnegd_s64(i64 %a) {
5 ; CHECK: test_vnegd_s64
6 ; CHECK: neg {{d[0-9]+}}, {{d[0-9]+}}
8 %vneg.i = insertelement <1 x i64> undef, i64 %a, i32 0
9 %vneg1.i = tail call <1 x i64> @llvm.aarch64.neon.vneg(<1 x i64> %vneg.i)
10 %0 = extractelement <1 x i64> %vneg1.i, i32 0
14 declare <1 x i64> @llvm.aarch64.neon.vneg(<1 x i64>)
16 define i8 @test_vqnegb_s8(i8 %a) {
17 ; CHECK: test_vqnegb_s8
18 ; CHECK: sqneg {{b[0-9]+}}, {{b[0-9]+}}
20 %vqneg.i = insertelement <1 x i8> undef, i8 %a, i32 0
21 %vqneg1.i = call <1 x i8> @llvm.arm.neon.vqneg.v1i8(<1 x i8> %vqneg.i)
22 %0 = extractelement <1 x i8> %vqneg1.i, i32 0
26 declare <1 x i8> @llvm.arm.neon.vqneg.v1i8(<1 x i8>)
28 define i16 @test_vqnegh_s16(i16 %a) {
29 ; CHECK: test_vqnegh_s16
30 ; CHECK: sqneg {{h[0-9]+}}, {{h[0-9]+}}
32 %vqneg.i = insertelement <1 x i16> undef, i16 %a, i32 0
33 %vqneg1.i = call <1 x i16> @llvm.arm.neon.vqneg.v1i16(<1 x i16> %vqneg.i)
34 %0 = extractelement <1 x i16> %vqneg1.i, i32 0
38 declare <1 x i16> @llvm.arm.neon.vqneg.v1i16(<1 x i16>)
40 define i32 @test_vqnegs_s32(i32 %a) {
41 ; CHECK: test_vqnegs_s32
42 ; CHECK: sqneg {{s[0-9]+}}, {{s[0-9]+}}
44 %vqneg.i = insertelement <1 x i32> undef, i32 %a, i32 0
45 %vqneg1.i = call <1 x i32> @llvm.arm.neon.vqneg.v1i32(<1 x i32> %vqneg.i)
46 %0 = extractelement <1 x i32> %vqneg1.i, i32 0
50 declare <1 x i32> @llvm.arm.neon.vqneg.v1i32(<1 x i32>)
52 define i64 @test_vqnegd_s64(i64 %a) {
53 ; CHECK: test_vqnegd_s64
54 ; CHECK: sqneg {{d[0-9]+}}, {{d[0-9]+}}
56 %vqneg.i = insertelement <1 x i64> undef, i64 %a, i32 0
57 %vqneg1.i = call <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64> %vqneg.i)
58 %0 = extractelement <1 x i64> %vqneg1.i, i32 0
62 declare <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64>)