1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
2 ; Intrinsic wrangling. Duplicates various arm64 tests.
4 declare <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64>)
6 define <1 x i64> @test_addp_v1i64(<2 x i64> %a) {
7 ; CHECK: test_addp_v1i64:
8 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
9 %val = call <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64> %a)
13 declare float @llvm.aarch64.neon.vpfadd.f32.v2f32(<2 x float>)
15 define float @test_faddp_f32(<2 x float> %a) {
16 ; CHECK: test_faddp_f32:
17 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
18 %val = call float @llvm.aarch64.neon.vpfadd.f32.v2f32(<2 x float> %a)
22 declare double @llvm.aarch64.neon.vpfadd.f64.v2f64(<2 x double>)
24 define double @test_faddp_f64(<2 x double> %a) {
25 ; CHECK: test_faddp_f64:
26 ; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
27 %val = call double @llvm.aarch64.neon.vpfadd.f64.v2f64(<2 x double> %a)
32 declare float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float>)
34 define float @test_fmaxp_f32(<2 x float> %a) {
35 ; CHECK: test_fmaxp_f32:
36 ; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
37 %val = call float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float> %a)
41 declare double @llvm.aarch64.neon.vpmax.f64.v2f64(<2 x double>)
43 define double @test_fmaxp_f64(<2 x double> %a) {
44 ; CHECK: test_fmaxp_f64:
45 ; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
46 %val = call double @llvm.aarch64.neon.vpmax.f64.v2f64(<2 x double> %a)
50 declare float @llvm.aarch64.neon.vpmin.f32.v2f32(<2 x float>)
52 define float @test_fminp_f32(<2 x float> %a) {
53 ; CHECK: test_fminp_f32:
54 ; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
55 %val = call float @llvm.aarch64.neon.vpmin.f32.v2f32(<2 x float> %a)
59 declare double @llvm.aarch64.neon.vpmin.f64.v2f64(<2 x double>)
61 define double @test_fminp_f64(<2 x double> %a) {
62 ; CHECK: test_fminp_f64:
63 ; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
64 %val = call double @llvm.aarch64.neon.vpmin.f64.v2f64(<2 x double> %a)
68 declare float @llvm.aarch64.neon.vpfmaxnm.f32.v2f32(<2 x float>)
70 define float @test_fmaxnmp_f32(<2 x float> %a) {
71 ; CHECK: test_fmaxnmp_f32:
72 ; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
73 %val = call float @llvm.aarch64.neon.vpfmaxnm.f32.v2f32(<2 x float> %a)
77 declare double @llvm.aarch64.neon.vpfmaxnm.f64.v2f64(<2 x double>)
79 define double @test_fmaxnmp_f64(<2 x double> %a) {
80 ; CHECK: test_fmaxnmp_f64:
81 ; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
82 %val = call double @llvm.aarch64.neon.vpfmaxnm.f64.v2f64(<2 x double> %a)
86 declare float @llvm.aarch64.neon.vpfminnm.f32.v2f32(<2 x float>)
88 define float @test_fminnmp_f32(<2 x float> %a) {
89 ; CHECK: test_fminnmp_f32:
90 ; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
91 %val = call float @llvm.aarch64.neon.vpfminnm.f32.v2f32(<2 x float> %a)
95 declare double @llvm.aarch64.neon.vpfminnm.f64.v2f64(<2 x double>)
97 define double @test_fminnmp_f64(<2 x double> %a) {
98 ; CHECK: test_fminnmp_f64:
99 ; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
100 %val = call double @llvm.aarch64.neon.vpfminnm.f64.v2f64(<2 x double> %a)
104 define float @test_vaddv_f32(<2 x float> %a) {
105 ; CHECK-LABEL: test_vaddv_f32
106 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
107 %1 = call float @llvm.aarch64.neon.vpfadd.f32.v2f32(<2 x float> %a)
111 define float @test_vaddvq_f32(<4 x float> %a) {
112 ; CHECK-LABEL: test_vaddvq_f32
113 ; CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
114 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
115 %1 = call float @llvm.aarch64.neon.vpfadd.f32.v4f32(<4 x float> %a)
119 define double @test_vaddvq_f64(<2 x double> %a) {
120 ; CHECK-LABEL: test_vaddvq_f64
121 ; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
122 %1 = call double @llvm.aarch64.neon.vpfadd.f64.v2f64(<2 x double> %a)
126 define float @test_vmaxv_f32(<2 x float> %a) {
127 ; CHECK-LABEL: test_vmaxv_f32
128 ; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
129 %1 = call float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float> %a)
133 define double @test_vmaxvq_f64(<2 x double> %a) {
134 ; CHECK-LABEL: test_vmaxvq_f64
135 ; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
136 %1 = call double @llvm.aarch64.neon.vpmax.f64.v2f64(<2 x double> %a)
140 define float @test_vminv_f32(<2 x float> %a) {
141 ; CHECK-LABEL: test_vminv_f32
142 ; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
143 %1 = call float @llvm.aarch64.neon.vpmin.f32.v2f32(<2 x float> %a)
147 define double @test_vminvq_f64(<2 x double> %a) {
148 ; CHECK-LABEL: test_vminvq_f64
149 ; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
150 %1 = call double @llvm.aarch64.neon.vpmin.f64.v2f64(<2 x double> %a)
154 define double @test_vmaxnmvq_f64(<2 x double> %a) {
155 ; CHECK-LABEL: test_vmaxnmvq_f64
156 ; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
157 %1 = call double @llvm.aarch64.neon.vpfmaxnm.f64.v2f64(<2 x double> %a)
161 define float @test_vmaxnmv_f32(<2 x float> %a) {
162 ; CHECK-LABEL: test_vmaxnmv_f32
163 ; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
164 %1 = call float @llvm.aarch64.neon.vpfmaxnm.f32.v2f32(<2 x float> %a)
168 define double @test_vminnmvq_f64(<2 x double> %a) {
169 ; CHECK-LABEL: test_vminnmvq_f64
170 ; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
171 %1 = call double @llvm.aarch64.neon.vpfminnm.f64.v2f64(<2 x double> %a)
175 define float @test_vminnmv_f32(<2 x float> %a) {
176 ; CHECK-LABEL: test_vminnmv_f32
177 ; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
178 %1 = call float @llvm.aarch64.neon.vpfminnm.f32.v2f32(<2 x float> %a)
182 define <2 x i64> @test_vpaddq_s64(<2 x i64> %a, <2 x i64> %b) {
183 ; CHECK-LABEL: test_vpaddq_s64
184 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
185 %1 = call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
189 define <2 x i64> @test_vpaddq_u64(<2 x i64> %a, <2 x i64> %b) {
190 ; CHECK-LABEL: test_vpaddq_u64
191 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
192 %1 = call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
196 define i64 @test_vaddvq_s64(<2 x i64> %a) {
197 ; CHECK-LABEL: test_vaddvq_s64
198 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
199 %1 = call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
200 %2 = extractelement <1 x i64> %1, i32 0
204 define i64 @test_vaddvq_u64(<2 x i64> %a) {
205 ; CHECK-LABEL: test_vaddvq_u64
206 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
207 %1 = call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
208 %2 = extractelement <1 x i64> %1, i32 0
212 declare <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64>)
214 declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
216 declare float @llvm.aarch64.neon.vpfadd.f32.v4f32(<4 x float>)