1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 declare <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8>, <1 x i8>)
4 declare <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8>, <1 x i8>)
6 define <1 x i8> @test_uqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
7 ; CHECK: test_uqadd_v1i8_aarch64:
8 %tmp1 = call <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
9 ;CHECK: uqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
13 define <1 x i8> @test_sqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
14 ; CHECK: test_sqadd_v1i8_aarch64:
15 %tmp1 = call <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
16 ;CHECK: sqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
20 declare <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8>, <1 x i8>)
21 declare <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8>, <1 x i8>)
23 define <1 x i8> @test_uqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
24 ; CHECK: test_uqsub_v1i8_aarch64:
25 %tmp1 = call <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
26 ;CHECK: uqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
30 define <1 x i8> @test_sqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
31 ; CHECK: test_sqsub_v1i8_aarch64:
32 %tmp1 = call <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
33 ;CHECK: sqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
37 declare <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16>, <1 x i16>)
38 declare <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16>, <1 x i16>)
40 define <1 x i16> @test_uqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
41 ; CHECK: test_uqadd_v1i16_aarch64:
42 %tmp1 = call <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
43 ;CHECK: uqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
47 define <1 x i16> @test_sqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
48 ; CHECK: test_sqadd_v1i16_aarch64:
49 %tmp1 = call <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
50 ;CHECK: sqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
54 declare <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16>, <1 x i16>)
55 declare <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16>, <1 x i16>)
57 define <1 x i16> @test_uqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
58 ; CHECK: test_uqsub_v1i16_aarch64:
59 %tmp1 = call <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
60 ;CHECK: uqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
64 define <1 x i16> @test_sqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
65 ; CHECK: test_sqsub_v1i16_aarch64:
66 %tmp1 = call <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
67 ;CHECK: sqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
71 declare <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32>, <1 x i32>)
72 declare <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32>, <1 x i32>)
74 define <1 x i32> @test_uqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
75 ; CHECK: test_uqadd_v1i32_aarch64:
76 %tmp1 = call <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
77 ;CHECK: uqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
81 define <1 x i32> @test_sqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
82 ; CHECK: test_sqadd_v1i32_aarch64:
83 %tmp1 = call <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
84 ;CHECK: sqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
88 declare <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32>, <1 x i32>)
89 declare <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32>, <1 x i32>)
91 define <1 x i32> @test_uqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
92 ; CHECK: test_uqsub_v1i32_aarch64:
93 %tmp1 = call <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
94 ;CHECK: uqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
99 define <1 x i32> @test_sqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
100 ; CHECK: test_sqsub_v1i32_aarch64:
101 %tmp1 = call <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
102 ;CHECK: sqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
106 declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>)
107 declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>)
109 define <1 x i64> @test_uqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
110 ; CHECK: test_uqadd_v1i64_aarch64:
111 %tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
112 ;CHECK: uqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
116 define <1 x i64> @test_sqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
117 ; CHECK: test_sqadd_v1i64_aarch64:
118 %tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
119 ;CHECK: sqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
123 declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>)
124 declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>)
126 define <1 x i64> @test_uqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
127 ; CHECK: test_uqsub_v1i64_aarch64:
128 %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
129 ;CHECK: uqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
133 define <1 x i64> @test_sqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
134 ; CHECK: test_sqsub_v1i64_aarch64:
135 %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
136 ;CHECK: sqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
140 define i8 @test_vuqaddb_s8(i8 %a, i8 %b) {
141 ; CHECK: test_vuqaddb_s8
142 ; CHECK: suqadd {{b[0-9]+}}, {{b[0-9]+}}
144 %vuqadd.i = insertelement <1 x i8> undef, i8 %a, i32 0
145 %vuqadd1.i = insertelement <1 x i8> undef, i8 %b, i32 0
146 %vuqadd2.i = call <1 x i8> @llvm.aarch64.neon.vuqadd.v1i8(<1 x i8> %vuqadd.i, <1 x i8> %vuqadd1.i)
147 %0 = extractelement <1 x i8> %vuqadd2.i, i32 0
151 declare <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8>, <1 x i8>)
153 define i16 @test_vuqaddh_s16(i16 %a, i16 %b) {
154 ; CHECK: test_vuqaddh_s16
155 ; CHECK: suqadd {{h[0-9]+}}, {{h[0-9]+}}
157 %vuqadd.i = insertelement <1 x i16> undef, i16 %a, i32 0
158 %vuqadd1.i = insertelement <1 x i16> undef, i16 %b, i32 0
159 %vuqadd2.i = call <1 x i16> @llvm.aarch64.neon.vuqadd.v1i16(<1 x i16> %vuqadd.i, <1 x i16> %vuqadd1.i)
160 %0 = extractelement <1 x i16> %vuqadd2.i, i32 0
164 declare <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16>, <1 x i16>)
166 define i32 @test_vuqadds_s32(i32 %a, i32 %b) {
167 ; CHECK: test_vuqadds_s32
168 ; CHECK: suqadd {{s[0-9]+}}, {{s[0-9]+}}
170 %vuqadd.i = insertelement <1 x i32> undef, i32 %a, i32 0
171 %vuqadd1.i = insertelement <1 x i32> undef, i32 %b, i32 0
172 %vuqadd2.i = call <1 x i32> @llvm.aarch64.neon.vuqadd.v1i32(<1 x i32> %vuqadd.i, <1 x i32> %vuqadd1.i)
173 %0 = extractelement <1 x i32> %vuqadd2.i, i32 0
177 declare <1 x i32> @llvm.aarch64.neon.vsqadd.v1i32(<1 x i32>, <1 x i32>)
179 define i64 @test_vuqaddd_s64(i64 %a, i64 %b) {
180 ; CHECK: test_vuqaddd_s64
181 ; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
183 %vuqadd.i = insertelement <1 x i64> undef, i64 %a, i32 0
184 %vuqadd1.i = insertelement <1 x i64> undef, i64 %b, i32 0
185 %vuqadd2.i = call <1 x i64> @llvm.aarch64.neon.vuqadd.v1i64(<1 x i64> %vuqadd.i, <1 x i64> %vuqadd1.i)
186 %0 = extractelement <1 x i64> %vuqadd2.i, i32 0
190 declare <1 x i64> @llvm.aarch64.neon.vsqadd.v1i64(<1 x i64>, <1 x i64>)
192 define i8 @test_vsqaddb_u8(i8 %a, i8 %b) {
193 ; CHECK: test_vsqaddb_u8
194 ; CHECK: usqadd {{b[0-9]+}}, {{b[0-9]+}}
196 %vsqadd.i = insertelement <1 x i8> undef, i8 %a, i32 0
197 %vsqadd1.i = insertelement <1 x i8> undef, i8 %b, i32 0
198 %vsqadd2.i = call <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8> %vsqadd.i, <1 x i8> %vsqadd1.i)
199 %0 = extractelement <1 x i8> %vsqadd2.i, i32 0
203 declare <1 x i8> @llvm.aarch64.neon.vuqadd.v1i8(<1 x i8>, <1 x i8>)
205 define i16 @test_vsqaddh_u16(i16 %a, i16 %b) {
206 ; CHECK: test_vsqaddh_u16
207 ; CHECK: usqadd {{h[0-9]+}}, {{h[0-9]+}}
209 %vsqadd.i = insertelement <1 x i16> undef, i16 %a, i32 0
210 %vsqadd1.i = insertelement <1 x i16> undef, i16 %b, i32 0
211 %vsqadd2.i = call <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16> %vsqadd.i, <1 x i16> %vsqadd1.i)
212 %0 = extractelement <1 x i16> %vsqadd2.i, i32 0
216 declare <1 x i16> @llvm.aarch64.neon.vuqadd.v1i16(<1 x i16>, <1 x i16>)
218 define i32 @test_vsqadds_u32(i32 %a, i32 %b) {
219 ; CHECK: test_vsqadds_u32
220 ; CHECK: usqadd {{s[0-9]+}}, {{s[0-9]+}}
222 %vsqadd.i = insertelement <1 x i32> undef, i32 %a, i32 0
223 %vsqadd1.i = insertelement <1 x i32> undef, i32 %b, i32 0
224 %vsqadd2.i = call <1 x i32> @llvm.aarch64.neon.vsqadd.v1i32(<1 x i32> %vsqadd.i, <1 x i32> %vsqadd1.i)
225 %0 = extractelement <1 x i32> %vsqadd2.i, i32 0
229 declare <1 x i32> @llvm.aarch64.neon.vuqadd.v1i32(<1 x i32>, <1 x i32>)
231 define i64 @test_vsqaddd_u64(i64 %a, i64 %b) {
232 ; CHECK: test_vsqaddd_u64
233 ; CHECK: usqadd {{d[0-9]+}}, {{d[0-9]+}}
235 %vsqadd.i = insertelement <1 x i64> undef, i64 %a, i32 0
236 %vsqadd1.i = insertelement <1 x i64> undef, i64 %b, i32 0
237 %vsqadd2.i = call <1 x i64> @llvm.aarch64.neon.vsqadd.v1i64(<1 x i64> %vsqadd.i, <1 x i64> %vsqadd1.i)
238 %0 = extractelement <1 x i64> %vsqadd2.i, i32 0
242 declare <1 x i64> @llvm.aarch64.neon.vuqadd.v1i64(<1 x i64>, <1 x i64>)