1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
3 declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>)
4 declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>)
6 define <1 x i64> @test_ushl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
7 ; CHECK: test_ushl_v1i64:
8 %tmp1 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
9 ; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
14 define <1 x i64> @test_sshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
15 ; CHECK: test_sshl_v1i64:
16 %tmp1 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
17 ; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
21 declare <1 x i64> @llvm.aarch64.neon.vshldu(<1 x i64>, <1 x i64>)
22 declare <1 x i64> @llvm.aarch64.neon.vshlds(<1 x i64>, <1 x i64>)
24 define <1 x i64> @test_ushl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
25 ; CHECK: test_ushl_v1i64_aarch64:
26 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vshldu(<1 x i64> %lhs, <1 x i64> %rhs)
27 ; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
31 define <1 x i64> @test_sshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
32 ; CHECK: test_sshl_v1i64_aarch64:
33 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vshlds(<1 x i64> %lhs, <1 x i64> %rhs)
34 ; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
38 define <1 x i64> @test_vtst_s64(<1 x i64> %a, <1 x i64> %b) {
39 ; CHECK-LABEL: test_vtst_s64
40 ; CHECK: cmtst {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
42 %0 = and <1 x i64> %a, %b
43 %1 = icmp ne <1 x i64> %0, zeroinitializer
44 %vtst.i = sext <1 x i1> %1 to <1 x i64>
48 define <1 x i64> @test_vtst_u64(<1 x i64> %a, <1 x i64> %b) {
49 ; CHECK-LABEL: test_vtst_u64
50 ; CHECK: cmtst {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
52 %0 = and <1 x i64> %a, %b
53 %1 = icmp ne <1 x i64> %0, zeroinitializer
54 %vtst.i = sext <1 x i1> %1 to <1 x i64>
58 define <1 x i64> @test_vsli_n_p64(<1 x i64> %a, <1 x i64> %b) {
59 ; CHECK-LABEL: test_vsli_n_p64
60 ; CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #0
62 %vsli_n2 = tail call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %a, <1 x i64> %b, i32 0)
63 ret <1 x i64> %vsli_n2
66 declare <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32)
68 define <2 x i64> @test_vsliq_n_p64(<2 x i64> %a, <2 x i64> %b) {
69 ; CHECK-LABEL: test_vsliq_n_p64
70 ; CHECK: sli {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
72 %vsli_n2 = tail call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %a, <2 x i64> %b, i32 0)
73 ret <2 x i64> %vsli_n2
76 declare <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32)
78 define <2 x i32> @test_vrsqrte_u32(<2 x i32> %a) {
79 ; CHECK-LABEL: test_vrsqrte_u32
80 ; CHECK: ursqrte {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
82 %vrsqrte1.i = tail call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %a)
83 ret <2 x i32> %vrsqrte1.i
86 define <4 x i32> @test_vrsqrteq_u32(<4 x i32> %a) {
87 ; CHECK-LABEL: test_vrsqrteq_u32
88 ; CHECK: ursqrte {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
90 %vrsqrte1.i = tail call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %a)
91 ret <4 x i32> %vrsqrte1.i
94 define <8 x i8> @test_vqshl_n_s8(<8 x i8> %a) {
95 ; CHECK-LABEL: test_vqshl_n_s8
96 ; CHECK: sqshl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
98 %vqshl_n = tail call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %a, <8 x i8> zeroinitializer)
102 declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>)
104 define <16 x i8> @test_vqshlq_n_s8(<16 x i8> %a) {
105 ; CHECK-LABEL: test_vqshlq_n_s8
106 ; CHECK: sqshl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
108 %vqshl_n = tail call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %a, <16 x i8> zeroinitializer)
109 ret <16 x i8> %vqshl_n
112 declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>)
114 define <4 x i16> @test_vqshl_n_s16(<4 x i16> %a) {
115 ; CHECK-LABEL: test_vqshl_n_s16
116 ; CHECK: sqshl {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
118 %vqshl_n1 = tail call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %a, <4 x i16> zeroinitializer)
119 ret <4 x i16> %vqshl_n1
122 declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>)
124 define <8 x i16> @test_vqshlq_n_s16(<8 x i16> %a) {
125 ; CHECK-LABEL: test_vqshlq_n_s16
126 ; CHECK: sqshl {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
128 %vqshl_n1 = tail call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %a, <8 x i16> zeroinitializer)
129 ret <8 x i16> %vqshl_n1
132 declare <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16>, <8 x i16>)
134 define <2 x i32> @test_vqshl_n_s32(<2 x i32> %a) {
135 ; CHECK-LABEL: test_vqshl_n_s32
136 ; CHECK: sqshl {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
138 %vqshl_n1 = tail call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %a, <2 x i32> zeroinitializer)
139 ret <2 x i32> %vqshl_n1
142 declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>)
144 define <4 x i32> @test_vqshlq_n_s32(<4 x i32> %a) {
145 ; CHECK-LABEL: test_vqshlq_n_s32
146 ; CHECK: sqshl {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
148 %vqshl_n1 = tail call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)
149 ret <4 x i32> %vqshl_n1
152 declare <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32>, <4 x i32>)
154 define <2 x i64> @test_vqshlq_n_s64(<2 x i64> %a) {
155 ; CHECK-LABEL: test_vqshlq_n_s64
156 ; CHECK: sqshl {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
158 %vqshl_n1 = tail call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %a, <2 x i64> zeroinitializer)
159 ret <2 x i64> %vqshl_n1
162 declare <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64>, <2 x i64>)
164 define <8 x i8> @test_vqshl_n_u8(<8 x i8> %a) {
165 ; CHECK-LABEL: test_vqshl_n_u8
166 ; CHECK: uqshl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
168 %vqshl_n = tail call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %a, <8 x i8> zeroinitializer)
169 ret <8 x i8> %vqshl_n
172 declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>)
174 define <16 x i8> @test_vqshlq_n_u8(<16 x i8> %a) {
175 ; CHECK-LABEL: test_vqshlq_n_u8
176 ; CHECK: uqshl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
178 %vqshl_n = tail call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %a, <16 x i8> zeroinitializer)
179 ret <16 x i8> %vqshl_n
182 declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>)
184 define <4 x i16> @test_vqshl_n_u16(<4 x i16> %a) {
185 ; CHECK-LABEL: test_vqshl_n_u16
186 ; CHECK: uqshl {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
188 %vqshl_n1 = tail call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %a, <4 x i16> zeroinitializer)
189 ret <4 x i16> %vqshl_n1
192 declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>)
194 define <8 x i16> @test_vqshlq_n_u16(<8 x i16> %a) {
195 ; CHECK-LABEL: test_vqshlq_n_u16
196 ; CHECK: uqshl {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
198 %vqshl_n1 = tail call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %a, <8 x i16> zeroinitializer)
199 ret <8 x i16> %vqshl_n1
202 declare <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16>, <8 x i16>)
204 define <2 x i32> @test_vqshl_n_u32(<2 x i32> %a) {
205 ; CHECK-LABEL: test_vqshl_n_u32
206 ; CHECK: uqshl {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
208 %vqshl_n1 = tail call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %a, <2 x i32> zeroinitializer)
209 ret <2 x i32> %vqshl_n1
212 declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>)
214 define <4 x i32> @test_vqshlq_n_u32(<4 x i32> %a) {
215 ; CHECK-LABEL: test_vqshlq_n_u32
216 ; CHECK: uqshl {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
218 %vqshl_n1 = tail call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)
219 ret <4 x i32> %vqshl_n1
222 declare <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32>, <4 x i32>)
224 define <2 x i64> @test_vqshlq_n_u64(<2 x i64> %a) {
225 ; CHECK-LABEL: test_vqshlq_n_u64
226 ; CHECK: uqshl {{v[0-9]+}}.2d, {{v[0-9]+}}.2d,
228 %vqshl_n1 = tail call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %a, <2 x i64> zeroinitializer)
229 ret <2 x i64> %vqshl_n1
232 declare <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64>, <2 x i64>)
234 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>)
236 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>)