1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2 ; Duplicates existing arm64 tests in vshift.ll and vcmp.ll
4 declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>)
5 declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>)
7 define <1 x i64> @test_ushl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
8 ; CHECK: test_ushl_v1i64:
9 %tmp1 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
10 ; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
15 define <1 x i64> @test_sshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
16 ; CHECK: test_sshl_v1i64:
17 %tmp1 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
18 ; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
22 declare <1 x i64> @llvm.aarch64.neon.vshldu(<1 x i64>, <1 x i64>)
23 declare <1 x i64> @llvm.aarch64.neon.vshlds(<1 x i64>, <1 x i64>)
25 define <1 x i64> @test_ushl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
26 ; CHECK: test_ushl_v1i64_aarch64:
27 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vshldu(<1 x i64> %lhs, <1 x i64> %rhs)
28 ; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
32 define <1 x i64> @test_sshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
33 ; CHECK: test_sshl_v1i64_aarch64:
34 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vshlds(<1 x i64> %lhs, <1 x i64> %rhs)
35 ; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
39 define <1 x i64> @test_vtst_s64(<1 x i64> %a, <1 x i64> %b) {
40 ; CHECK-LABEL: test_vtst_s64
41 ; CHECK: cmtst {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
43 %0 = and <1 x i64> %a, %b
44 %1 = icmp ne <1 x i64> %0, zeroinitializer
45 %vtst.i = sext <1 x i1> %1 to <1 x i64>
49 define <1 x i64> @test_vtst_u64(<1 x i64> %a, <1 x i64> %b) {
50 ; CHECK-LABEL: test_vtst_u64
51 ; CHECK: cmtst {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
53 %0 = and <1 x i64> %a, %b
54 %1 = icmp ne <1 x i64> %0, zeroinitializer
55 %vtst.i = sext <1 x i1> %1 to <1 x i64>
59 define <1 x i64> @test_vsli_n_p64(<1 x i64> %a, <1 x i64> %b) {
60 ; CHECK-LABEL: test_vsli_n_p64
61 ; CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #0
63 %vsli_n2 = tail call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %a, <1 x i64> %b, i32 0)
64 ret <1 x i64> %vsli_n2
67 declare <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32)
69 define <2 x i64> @test_vsliq_n_p64(<2 x i64> %a, <2 x i64> %b) {
70 ; CHECK-LABEL: test_vsliq_n_p64
71 ; CHECK: sli {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
73 %vsli_n2 = tail call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %a, <2 x i64> %b, i32 0)
74 ret <2 x i64> %vsli_n2
77 declare <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32)
79 define <2 x i32> @test_vrsqrte_u32(<2 x i32> %a) {
80 ; CHECK-LABEL: test_vrsqrte_u32
81 ; CHECK: ursqrte {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
83 %vrsqrte1.i = tail call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %a)
84 ret <2 x i32> %vrsqrte1.i
87 define <4 x i32> @test_vrsqrteq_u32(<4 x i32> %a) {
88 ; CHECK-LABEL: test_vrsqrteq_u32
89 ; CHECK: ursqrte {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
91 %vrsqrte1.i = tail call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %a)
92 ret <4 x i32> %vrsqrte1.i
95 define <8 x i8> @test_vqshl_n_s8(<8 x i8> %a) {
96 ; CHECK-LABEL: test_vqshl_n_s8
97 ; CHECK: sqshl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
99 %vqshl_n = tail call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %a, <8 x i8> zeroinitializer)
100 ret <8 x i8> %vqshl_n
103 declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>)
105 define <16 x i8> @test_vqshlq_n_s8(<16 x i8> %a) {
106 ; CHECK-LABEL: test_vqshlq_n_s8
107 ; CHECK: sqshl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
109 %vqshl_n = tail call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %a, <16 x i8> zeroinitializer)
110 ret <16 x i8> %vqshl_n
113 declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>)
115 define <4 x i16> @test_vqshl_n_s16(<4 x i16> %a) {
116 ; CHECK-LABEL: test_vqshl_n_s16
117 ; CHECK: sqshl {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
119 %vqshl_n1 = tail call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %a, <4 x i16> zeroinitializer)
120 ret <4 x i16> %vqshl_n1
123 declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>)
125 define <8 x i16> @test_vqshlq_n_s16(<8 x i16> %a) {
126 ; CHECK-LABEL: test_vqshlq_n_s16
127 ; CHECK: sqshl {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
129 %vqshl_n1 = tail call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %a, <8 x i16> zeroinitializer)
130 ret <8 x i16> %vqshl_n1
133 declare <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16>, <8 x i16>)
135 define <2 x i32> @test_vqshl_n_s32(<2 x i32> %a) {
136 ; CHECK-LABEL: test_vqshl_n_s32
137 ; CHECK: sqshl {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
139 %vqshl_n1 = tail call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %a, <2 x i32> zeroinitializer)
140 ret <2 x i32> %vqshl_n1
143 declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>)
145 define <4 x i32> @test_vqshlq_n_s32(<4 x i32> %a) {
146 ; CHECK-LABEL: test_vqshlq_n_s32
147 ; CHECK: sqshl {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
149 %vqshl_n1 = tail call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)
150 ret <4 x i32> %vqshl_n1
153 declare <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32>, <4 x i32>)
155 define <2 x i64> @test_vqshlq_n_s64(<2 x i64> %a) {
156 ; CHECK-LABEL: test_vqshlq_n_s64
157 ; CHECK: sqshl {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
159 %vqshl_n1 = tail call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %a, <2 x i64> zeroinitializer)
160 ret <2 x i64> %vqshl_n1
163 declare <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64>, <2 x i64>)
165 define <8 x i8> @test_vqshl_n_u8(<8 x i8> %a) {
166 ; CHECK-LABEL: test_vqshl_n_u8
167 ; CHECK: uqshl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
169 %vqshl_n = tail call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %a, <8 x i8> zeroinitializer)
170 ret <8 x i8> %vqshl_n
173 declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>)
175 define <16 x i8> @test_vqshlq_n_u8(<16 x i8> %a) {
176 ; CHECK-LABEL: test_vqshlq_n_u8
177 ; CHECK: uqshl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
179 %vqshl_n = tail call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %a, <16 x i8> zeroinitializer)
180 ret <16 x i8> %vqshl_n
183 declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>)
185 define <4 x i16> @test_vqshl_n_u16(<4 x i16> %a) {
186 ; CHECK-LABEL: test_vqshl_n_u16
187 ; CHECK: uqshl {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
189 %vqshl_n1 = tail call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %a, <4 x i16> zeroinitializer)
190 ret <4 x i16> %vqshl_n1
193 declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>)
195 define <8 x i16> @test_vqshlq_n_u16(<8 x i16> %a) {
196 ; CHECK-LABEL: test_vqshlq_n_u16
197 ; CHECK: uqshl {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
199 %vqshl_n1 = tail call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %a, <8 x i16> zeroinitializer)
200 ret <8 x i16> %vqshl_n1
203 declare <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16>, <8 x i16>)
205 define <2 x i32> @test_vqshl_n_u32(<2 x i32> %a) {
206 ; CHECK-LABEL: test_vqshl_n_u32
207 ; CHECK: uqshl {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
209 %vqshl_n1 = tail call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %a, <2 x i32> zeroinitializer)
210 ret <2 x i32> %vqshl_n1
213 declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>)
215 define <4 x i32> @test_vqshlq_n_u32(<4 x i32> %a) {
216 ; CHECK-LABEL: test_vqshlq_n_u32
217 ; CHECK: uqshl {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
219 %vqshl_n1 = tail call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)
220 ret <4 x i32> %vqshl_n1
223 declare <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32>, <4 x i32>)
225 define <2 x i64> @test_vqshlq_n_u64(<2 x i64> %a) {
226 ; CHECK-LABEL: test_vqshlq_n_u64
227 ; CHECK: uqshl {{v[0-9]+}}.2d, {{v[0-9]+}}.2d,
229 %vqshl_n1 = tail call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %a, <2 x i64> zeroinitializer)
230 ret <2 x i64> %vqshl_n1
233 declare <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64>, <2 x i64>)
235 declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>)
237 declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>)